User Manual CORE-2
Contents
1. 06 O CITTTTTYYTTTITIIITLITIITIT11101 71 111111111111 06 6 6 6 0 0 0 6 8 86 09 6 6 TITTTTT1111111111111111111 11 111111117T T ITTTTTYTTTTTTT 999999999999 99999 4 r 6 060 e e ebo e 4444444444444444444444444 9 Y ern o 1 11111111111111111111111111111111111 1111111111111111111111111111111111 31 11111111111111111111111111111111111131 11111111111111111131111111111111 32. Requirements tsARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics tppAT DATA15 0 Disable After CLKOUT DATA15 0 Enable After CLKOUT tpo Output Delay After CLKOUT tuo Output Hold After CLKOUT CORE 2 100mm ACCESSORIES PROTOTYPE BOARD 0900000000000000000090000000000020 0 9000000000000 060000000000000000000000000000000 00000000000000000000000000000000 0000000000000000000009000000000000 0000000000000000000000000 0000000000000000000000000000 54 Sa pad LA 4 00000000090090090901 LE E E 0000000 Qoo 117 11 1111 111121 121111 1111 210224 K X K X K X X X X X R K X K K N Y W K 0202028220288 Y 882488 R R K K X K X R RW Y R Y Y K R KE
3. 1 1111111111111111111111111111 1 1 e 4 0000060600600600090000006006 100000080009600p 00 E Ea 4 4 4 2 9 94 9 9 eo 1 19917 21 5 Rn 4 2 0 06000000000000000000000000 600600000 ok 00000000000 600000600000 9 9 o 9 9 000000000000 000000000000 000000000000 000000000000 6000000000 00000000007 oeoooooooo 00000000 0000000 o0 CORE 2 the property of their respective companies www digitaltechnologyart com 2012 2015 D T A srl All rights reserved Trademarks and registered trademarks are IGITAL HNOLOGY RT C
4. 9 Pc8 06 07 PG10 40 05 sck MiSo 2 MOSI 53 0 Di PFO PF A18 419 PF2 PF3 A16 4 5 AM T 15 PF6 12 Als A10 All 0 PF A8 Ag 12 PFi3 16 A7 14 PFi5 14 5 PHO PH 42 PH GND 4 PHS SDQMD 5DON PH6 PH7 SWE 510 GND GND SRAS SCAS _SDA SCL SCKE SMS RESET 25MHZ ARE ANSI 5V 5V AMSO AWE GND GND GND CLKOUT 2 1 CORE 2 J3 I O CONNECTOR SIGNAL DESCRIPTION GND Power supply return GND Power supply return 5 Power supply 5 5 max 70mA 400MHz 5 Power supply 5 5 max 70mA 400MHz 25MHz Oscillator output RESET Active low RESET output signal SCL TWI Serial Clock SDA TWI Serial Data GND Power supply return GND Power supply return PH7 GPIO SPORTO Transmit Data Primary SPI1 Slave Select Enable 6 GPIO SPORT1 Secondary Rx Data UART1 Receive Timer 7 Timer2 Alternate Clock Input PH6 GPIO SPORT1 Secondary Tx Data UART1 Transmit SPI1 Slave Select 1 Counter Zero Marker PH5 GPIO SPORT1 Tx Clock Asynchronous Memory Hardware Ready Control External Clock for PTP TSYNC Counter Down Gate PHA GPIO SPORT1 Tx Frame Sync Asynchronous Memory Output Enable SPIO Slave Select 3 Counter Up Direction PH3 GPIO SPORT1 Primary Tx Data SPI1 Master Out Slave In RSI Data 7 PH2 GPIO SP
5. O 8000 gt 4000 OxFFAO 0000 OxFF90 8000 OxFF90 4000 OxFF90 0000 OxFF80 8000 OxFF80 4000 OxFF80 0000 OxEFOO 8000 0000 lt 0x2040 0000 ASYNC MEMORY BANK 3 1M BYTES gt 0 2030 0000 ASYNC MEMORY BANK 2 1M BYTES 0x2020 0000 ASYNC MEMORY BANK 1 1M BYTES 4 0x2010 0000 lt ASYNC MEMORY BANK 0 1M BYTES 0x2000 0000 z 0x08 00 0000 SDRAM MEMORY 16M BYTES 128M BYTES 0x0000 0000 CORE 2 BLACKFIN PROCESSORE CORE 7 ADDRESS ARITHMETIC UNIT AHON3MN OL LLI n uo LOOP BUFFER DATA ARITHMETIC UNIT CORE 2 READ CYCLE TIMING ON BUS SETUP PROGRAMMED READ ACCESS EXTENDED HOLD 2 CYCLES ACCESS 4 CYCLES 3 CYCLES 1 CYCLE tpo tuo AMSx tpo ARE ABE1 0 ADDR19 1 tsARDY tuARDY ARDY DATA 15 0 3 3 V Nominal Timing Requirements tspAT DATA15 0 Setup Before CLKOUT tupAT DATA15 0 Hold After CLKOUT tsarpy ARDY Setup Before CLKOUT tuarpy ARDY Hold After CLKOUT Switching Characteristics too Output Delay After CLKOUT tuo Output Hold After CLKOUT CORE 2 WRITE CYCLE TIMING ON BUS PROGRAMMED WRITE ACCESS SETUP ACCESS EXTEND HOLD 2 CYCLES 2 CYCLES 1 CYCLE 1 CYCLE CLKOUT AMSx ABE1 0 ADDR19 1 AWE ARDY LE GENES Parameter Timing
6. ORT1 Rx Clock SPI1 Clock RSI Data 6 PH1 GPIO SPORT1 Rx Frame Sync SPI1 Master In Slave Out RSI Data 5 PHO GPIO SPORT1 Primary Rx Data SPI1 Device Select RSI Data 4 PF15 GPIO SPI1 Master Out Slave In PPI Data 1 GPIO Ethernet PHY Interrupt PPI Data 15 Alternate PWM Sync PF14 GPIO Ethernet MII Transmit Enable PPI Data 14 PWM BL Out PF13 GPIO Ethernet MII or RMII Receive D1 PPI Data 13 PWM BH Output PF12 GPIO Ethernet MII Transmit D1 PPI Data 12 PWM AL Output PF11 GPIO Ethernet MII Receive DO PPI Data 11 PWM AH output Timer3 Alternate Capture Input PF10 GPIO Ethernet Transmit DO PPI Data 10 Timer PF9 GPIO Ethernet Management Channel Serial Data PPl Data 9 Timer 2 PF8 GPIO Ethernet Management Channel Clock PPI Data 8 SPI1 Slave Select 4 PF7 GPIO SPIO Slave Select 1 PPI Data 7 PWM Sync PF6 GPIO Ethernet MII Collision PPI Data 6 PWM CL Out Timer1 Alternate Capture Input C PF5 GPIO Ethernet Receive Data Valid PPI Data 5 PWM CH Out TimerO Alternate Capture Input PF4 GPIO Ethernet MII Receive Clock PPI Data 4 PWM BL Out Timer1 Alternate CLK PF3 GPIO Ethernet Data Receive D3 PPI Data 3 PWM BH Output TimerO Alternate Clock PF2 GPIO Ethernet Transmit D3 PPI Data 2 PWM AL Output PF1 GPIO Ethernet MII Receive D2 PPI Data 1 PWM AH Output Timer7 Alternate Clock PFO GPIO Ethernet MII Transmit D2 PPI Data O SPI1 Slave Select 2 Timer6 Alternate Clock AMS3 GPIO SPIO Slave Select 2 PPI Frame Sync3 Asynchronous Memory Ba
7. RAM Boot from UARTO Host Y3 JTAG X ICE 100 Y5 SERIAL I O SIGNAL DESCRIPTION SIGNAL DESCRIPTION 3 3V Pull Up 10K to 3 3V 5V Power supply 330uA RTS Request To Send EMU Emulation Output TXD Transmit Serial Data TMS JTAG Mode Select RXD Receive Serial Data TCK JTAG CLK GND Power supply return TRST JTAGReset GND Power supply return TDI JTAG Serial Data In TDO JTAG Serial Data Out GND Power supply return Y2 RTC BATTERY SIGNAL DESCRIPTION VBAT 3V RTC supply GND Power supply return USB2 CONNECTION With a TTL 232RG VSW5V WE by FTDI is possible to connect and supply CORE 2 with a personal computer by USB 2 interface With this link you can download and debug the program with our GNU toolchain available in MDI program SIGNAL TTL 232RG VSW5V WE 5V RED wire RTS No connection TXD YELLOW wire RXD ORANGE wire GND No connection GND BLACK wire CORE 2 BF518 FUNCTIONAL BLOCK DIAGRAM PERIPHERAL ACCESS BUS COUNTER __ ke 7 0 INTERRUPT TWI qe CONTROLLER p SPORT1 0 Reuse e PORTS e I MEMORY E E m UART1 0 je 1 e FLASH SDRAM CONTROL ROM 1 See Table 1 BF518 MEMORY MAP OxFFFF FFFF CORE MMR REGISTERS 2M BYTES OxFFEO 0000 SYSTEM MMR REGISTERS 2M BYTES JTAG TEST AND EMULATION EXTERNAL BUS OxFFCO 0000 OxFFBO 1000 SCRATCHPAD SRAM 4K BYTES OxFFBO 0000 OxFFA1 4000 OxFFA1 0000 OxFFA
8. USR MAN C2 151028 IGITAL ECHNOLOGY User Manual RT CORE 2 is mini module based on Blackfin BF518F16 by Analog Device Inc In a minimum space are available all voltages supply required by DSP plus an external SDRAM 64 Mbyte 133 MHz and an optional NAND FLASH by 8 Gbyte DSP bus signals and its ports are accessible trough two 1 27 mm spaceg male connectors Is a system ready to use simply you must supply a 5 and with our free development system GNU Toolchain or with Analog Device CROSSCORE you can start the development aq CORE 2 2015 Digital Technology Art SRL Rev 1 0 BF518F16 45 Rev 1 Information furnished by D T A is believed to be accurate and reliable However no responsibility is assumed by D T A for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is Via Tosco Romagnola 187 56021 Cascina PISA ITALY granted by implication or otherwise under any patent or patent rights of Tel 39 050 711126 www digitaltechnologyart com D T A Trademarks and registered trademarks are the property of their FAX 39 050 715347 D T A srl All Rights Reserved respective companies CORE 2 BOTTOM VIEW BOTTOM VIEW SIGNALS J3 JA Peo 014 D 5 PG2 PG3 012 015 4 P65 010 Dit 6 7 08 0
9. mory Read Enable SMS SDRAM Bank Select SCKE SDRAM Clock Enable SCAS SDRAM Column Address Strobe 10 SRAS SDRAM Row Address Strobe SA10 SDRAM A10 Signal SWE SDRAM Write Enable SDQM1 Byte Enable or Data Mask SDQMD Byte Enable or Data Mask 2 A1 Address Bus GND Power supply return A3 Address Bus A2 Address Bus A5 Address Bus A4 Address Bus A7 Address Bus A6 Address Bus A9 Address Bus A8 Address Bus A11 Address Bus A10 Address Bus A13 Address Bus A12 Address Bus A15 Address Bus A14 Address Bus A17 Address Bus A16 Address Bus A19 Address Bus A18 Address Bus D1 Data Bus DO Data Bus D3 Data Bus D2 Data Bus D5 Data Bus 04 Data Bus D7 Data Bus D6 Data Bus D9 Data Bus D8 Data Bus D11 Data Bus D10 Data Bus D13 Data Bus D12 Data Bus D15 Data Bus D14 Data Bus P O O OO o QI IN N O 31 NEN EN Lp 10 EON 16 20 2 E PN EON Ea F C E NN EM ERN Ea INN EUREN EN EN EON EN EON 50 w CO CO O O NIOJ U Ui CORE 2 BOOT MODE SW1 BOOT MODE Idle No Boot Boot from 8 or 16 bit external flash memory Boot from internal SPI memory Boot from external SPI memory EEPROM or flash Boot from SPIO host Boot from OTP memory Boot from SD
10. nk Select 3 MOSI GPIO SPIO Master Out Slave In Timer 1 PPI Frame Sync2 PWM Trip PTP Auxiliary Snapshot Trigger Input MISO GPIO SPIO Master In Slave Out TimerO PPI Frame Sync1 PTP Clock Out SCK GPIO SPIO Clock PPI Clock External Timer Reference PTP Pulse Per Second Out PG11 GPIO SPIO Slave Device Select Asynchronous Memory Bank Select 2 SPI1 Slave Select 5 Timer2 Alternate CLK PG10 GPIO SPORTO Secondary Rx Data UARTO Receive Timer4 Alternate Capture Input PG9 GPIO SPORTO Secondary Tx Data UARTO Transmit Timer 4 PG8 GPIO SPORTO Tx Clock RSI Clock Timer 6 Timer6 Alternate Capture Input PG7 GPIO SPORTO Tx Primary Data RSI Command Timer 1 PPI Frame Sync2 PG6 GPIO SPORTO Tx Frame Sync RSI Data 3 TimerO PPI Frame Sync1 PG5 GPIO SPORTO Rx Frame Sync RSI Data 2 Clock External Timer Reference PG4 GPIO SPORTO Rx Clock RSI Data 1 Timer 5 Timer5 Alternate Capture Input PG3 GPIO SPORTO Primary Rx Data RSI Data O SPIO Slave Select 5 Timer3 Alternate CLK PG2 GPIO Ethernet or RMII Reference Clock DMA Req 0 PWM CL Out PG1 GPIO Ethernet MII or RMII Receive Error DMA Req 1 PWM CH Out PGO GPIO Ethernet Carrier Sense RMII Data Valid HWAIT SPI1 Slave Select3 6 8 2 15 36 45 CORE 2 JA BUS CONNECTOR SIGNAL DESCRIPTION CLKOUT SDRAM Clock Output GND Power supply return AWE Asynchronous Memory Write Enable AMSO Asynchronous Memory Bank Selects AMS1 Asynchronous Memory Bank Selects ARE Asynchronous Me
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