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1. J29 DIMM VREF 1 2 321 vss 2 DIMMB DQ4 DIMMB 51 55 004 r6 DIMME DOS DIMME DOT 7_ 090 Ders 091 VSS 19 DIMMB DIMMB T 311 VSS H2 2 DIMME DOST 13 i 34 DIMMB DIMMB_DQ2 Fl vss DIMM_VTT DIMME DO3 18 a 20 DIMMB 2 21 22 DIMMB 0013 RN25 DIMMB avs 0913 24 DIMMB 5 0 Domme DOs 25 7 DIMMB DMt 27 28 DIMMB_DQSn1 T 39 55_ VSS 730 f DWWE D sT 37 DOST 30 5 DIMMB 33 DQS1 34 DIMMB CKno 56R DIMMB DQ10 1 35 53 VSS 38 f DIMMB DQ14 DIMME DGIT 37 0010 Da14 3g DMMB DOTS 3 0011 pais 1 vss vss HS 34 D 41 42 RN22 DIMMB DQ16 Ta VSS VSS 25 _ 20 DIMMB_A15 DIMME DGT7 0016 0920 45 DIMME DGZT DIMME ATI 27 DQi7 0921 Tas T DIMME A DIMMB DOsSn2 T 49 VSS VSS 750 T DIM DIMMB 0052 51 EE ae 52 lt DIMMB_DM2 53 54 DIMMB DQ18 155 VSS VSS 55 DIMMB_Da22 DIMME DOTS 7 0018 0022 5g DIMMB DG23 59 0019 DO23 DIMMB DQ24 er BES 62 f DIMMB_Da28 DIMME D025 DIMME DO29 83 25 Daze 4 DIMMB DM3 1 87 Ed 68 DIMMB DIMME DOSS xH pasa
2. Figure 37 QSE Connector ISEI6 RxP R34 _103 AVCCAUXRXA 103 39 RXNPADA 103 AVCCAUXRXB 103 H95 AVCCAUXTX 103 59 5 QSE16_TxP an Wet TXPPADA 103 TXNPADA 103 SAMTEC cabl VR HRS cable VITXA 103 VITXB 103 15_ VTRXA 103 H45 Use a cable with pins 1 and OSES TN TXPPADB 103 40 swapped LBBPMA TXNPADB 103 J33 QSE15_RxP a RXPPADB 103 OSEN DN RXNPADB 103 AVCCAUXMGT 103 S8 QSET4 TxP 3 4 14_ AxN 5 6 c0 cO QSE13 T N 7 1 888888 QSET3 TxP 9 10 QSE13 HxN dada 11 12T 5588858 QSE12_TxN 13 14 QSE12_AxP 222222 QSE12 TxP 15 16 QSE12 FxN LEE 17 18 Virtex 4 FX 1152 06 CABLE 20 CABLE CINp CABLE COUTp 21 22 CABLE CINN CABLE CINp pl gt 22 SS QSE11 TxN T 25 26 f QSE11 RxP QSETi TP 27 28 QSETI FN 6 tor 2 QSE14 QSE16_TxN 31 32 QSE16 RxP Rx A31 B32 QSET6_TxP 38 34 OSE16 RxN OSEI4 HXN Aga RXPPADA 102 AVOGAUXRXA 102 33 C 32 x RXNPADA 102 AVCCAUXRXB 102 633 QSE15 1372 38 f 15 RxP AVCCAUXTX 102 225 ISE4 QSEI5 TxP 49 OSEI5 AN Tx D34 zyepap 102 1 5 TXNPADA 102 Pe 46x 102 HS VTTXB_102 peso SE13 VITXA 102 H970 SS TXPPADB 102 VTRXA 302 S885 r AS TXNPADB 102 ISE13
3. cae MB 96D ADB1 0 Bi 310 ALE Spartan MB B2 When the WR signal is asserted by the Spartan the FPGA should register the data on the AD bus Note that by convention FPGAs on the main bus are assigned the address range corresponding to one value of the highest nibble of the address Hex addresses OXXXXXXXX are FPGA A are FPGA B and 2XXXXXXX fpga Some time after this the FPGA should assert the DONE signal This will allow the Spartan to begin more transactions The FPGA may delay this for up to 256 clock cycles before a timeout 15 recorded and the transaction is cancelled Main bus can be controlled from the USB Controller program Read and write single addresses or to from files It can also be written from the main txt configuration method The main txt syntax is MAIN BUS Ox lt addr gt Ox lt data gt Where lt addr gt and lt data gt are 8 digit 32 bit hexadecimal numbers 3 1 Compiling the Reference Design This section deals with the source code to the Reference Design which can be found on the CD ROM All file references are with respect to the root directory of the Reference Design soutce code source FPGA Files that are specific to the DN8000K10PCIE design ate found DN8000K10PCIE User Guide www dinigroup com 103 INTRODUCTION TO THE SOFTWARE TOOLS in the DN8000K10PCIE subdirectory whereas general application code
4. DNG80D0K10P CI FPGAB J 31 28 DOT zz 27 1 261 Internal 3 11 4 Regs MB access 31 0 Internal Regs 3 11 4 31 0 250Mhz PX1011A 200Mhz BCLK 200Mhz BCLK DDR2 DDR2 Host PCI Express 2 1 Using the Reference Design 2 1 1 Built In RocketlO test From the AETest main menu select option 4 MGT Menu The MGT test sends a repeating test pattern out all of the RocketIO transmit pairs and compares the input of each RocketlO channel to that pattern To run the test you must loop back each RocketIO pair DN8000K10PCIE User Guide www dinigroup com 99 INTRODUCTION TO THE SOFTWARE TOOLS mulator PCI Controller Driver M on Jul 22 2005 at 12 58 24 P PCI Menu Memory Menu FPGAs stuffed A B 1 Interconnect test 2 Read clock frequencies 3 Configure FPGA 4 Menu Q Quit PCI ru z z 0 1 1 0000900 2 41900060 3 de000000 4 44000000 5 dc809000 Please select option _ You can easily loopback the SMA channels by connecting the RX and TX connectors of each MGT pair together with an SMA cable SFP modules be tested with an LR loopback attenuator Opti
5. Assembly Number Signal Comment DS9 5 0V PRESENT The 5 0V power rail is present above 1 7V DS10 3 5V PRESENT The 3 3V power rail is present abobe 1 7V DS11 2 V PRESENT The 2 5V power rail is present above 1 7V DS12 1 8V_PRESENT The 1 8V power rail is present above 1 7V DS13 ATX_POK The ATX power supply is generating 5 0V and 3 3V DN8000K10PCIE User Guide www dinigroup com 23 within 5 at the soutce 13515 SPARTAN LED3 DS17 SPARTAN_LED2 This LED will flicker when there is Main Bus activity See section X X X DS19 SPARTAN_LED1 This LED will flicker when there is USB activity Bulk Transfer DS20 SPARTAN_LEDO This LED will flicker when there is SmartMedia card activity DS21 1 top MCU_LEDO MCU_LED I 0 Codes DS21 2 MCU_LED1 01 FPGA A is configuring 10 FPGA B is configuring 11 FPGA is configuring DS21 3 MCU_LED2 last FPGA configuration was successful DS21 4 bottom MCU_LED3 Blinking There was configuration error Use the RS232 port to read the error Off Configuring On The last configuration command was successful DS24 SPARTAN_DONE The Spartan 2 configuration FPGA is configured This light will turn off if the board is in power reset DN8000K10PCIE User Guide www dinigroup com 24 DS18 FPGA A DONE The Virtex 4 F
6. FPGAA FPGAB FPGAC LX100 160 200 LX100 160 200 FX60 100 Eu FF1513 FF1513 FF1152 uP Config Virtex 4 Virtex 4 oer _ Control piros Ir CY7C68013 noor tEPROM differential or single ended GL9714 GL9714 ia PCle Phy PCle Phy 1 up to 4GB addressing up to 4GB addressing l ac k 4 jr 8442 a Br 19 Ics A lt I N 20A PCI Express pou y Bok JTAG Hash me sai 20A 2 9 0 l PLL Clock Synthesizers DN8000K10PCIE User Guide www dinigroup com 42 Figure 19 DN8000K10PCIE Block Diagram DN8000K10PCIE 8 The number of connections between FPGA A and FPGA C in the 8 Lane Version of the DNS8000K10PCIE compared to the 1 lane version is reduced from 52 pairs to 26 pairs The following sections describe in detail each circuit on the DIN8000K10PCIE Note that Schematics appearing in this section are illustrative and may have had details omitted or have been modified for clarity and brevity If you need to probe modify or design around the DN8000K10PCIE you will need to examine the complete schematics The DN8000K10PCIE schematics are provided on the user CD along with a netlist of the DN8000K10PCIE 2 Configuration Circuit 2 1 Overview The goal of the configuration circuit on the DN8000K10PCIE is to allow the user to configure his FPGAs using any host interface The configurat
7. atn 4 SOR E 4 B0mm PR B mm R TYP 50mm x 45 TYP a Rd 33 50 The topside clearance with the factory installed active heatsinks is 23mm This leaves just enough room for airflow if the adjacent PCI slot is left unoccupied or the DN8000K10PCIE is the last PCI card in the row The default heatsinks can be removed if you do not require high power operation allowing the DN8000K10PCIE to meet the PCI height restriction The back side clearance is 3 5mm This exceeds the PCI specification by 1 5mm If it is required that the DN8000K10PCIE use only one PCI slot the fan can be removed from the active heatsink assembly as long as sufficient airflow is provided Most PC cases do not provide sufficient airflow for high power applications DN8000K10PCIE User Guide www dinigroup com 94 UWOS POL INTRODUCTION VIRTEX 4 AND ISE DN8000K10PCIE User Guide www dinigroup com 95 INTRODUCTION TO THE SOFTWARE TOOLS Chapter Introduction to the Reference Design This chapter introdu s the DINSOOOK10PCIE Reference Design including information on what the reference design does how to build zt from the source files and how to modify t 1 Exploring the Reference Design 1 1 What is the Reference Design The reference design is a fully functional Virtex 4 FPGA design capable of demonstrating most of the features available on th
8. 99 2 1 1 Built In RockelfQ test aaa EHI E HC ER NR EN 99 3 MEMORY MAPPED DA TA LEO 102 3 1 COMPILING THE REFERENCE DESIGN tle et E E TE E E E 103 3 1 1 The Xilinx Embedded Development Kit EDK eese esent te tenete tetne tette trennen trennen 104 321 2 Xilin XT setae erp deca 4 3 1 3 Xilinx ISE 3 1 4 The Build Utility Makeibt itae en d a e E EE e CO Oed red 4 GETTING MORE INFOR MA TION asccscssessiseossestectesssisvacenscoiesesscntsonscesnstesvsneccdecssessssscveessadessbossasoodsessecessoussvasendcod essaveuedess 104 4 1 PRINTED DOCUMENTATION HERR NER UMEN REESE RR ES 104 4 2 ELECTRONIC DOCUMENTATION ciere o exon vu eva EE PH REVUE i ux 090 80 EN an PR RENE A a ER Senn 104 4 3 SUPPORT 105 44 ONLINE DOCUMENTATION seen eine EVE E EE 105 1 107 1 1 FPGA AS o E 107 1 2 107 1 3 FPGA G rne e en 2 MULTI GIGABIT SERIAL OPTIONS ees i 108 2 1 SERIAL CLOCK CRSTALS nn ne E 108 22 MODULE SOCKETS ERROR E
9. USBp 2 FB99 C672 tT USBp i U27 USBn_OV 2 C620 USBn OV USB Transient Protection The USB protocol is completed by the Cypress CPU The Cypress receives a 24Mhz clock from an oscillator X3 The Cypress internally multiplies this clock to 480Mhz for USB 2 0 and 48Mhz for GPIF operation The core runs at 24Mhz along with the external memory interface Communication over this external memory interface is clocked using the MCU IFCLK signal driven from the MCU at 48Mhz The Spartan communicates over main bus with the Virtex 4 FPGAs using a separate 48Mhz oscillator X1 and distributes this clock to each FPGA including itself DN8000K10PCIE User Guide www dinigroup com 58 40Mhz PLL IFCLK Spartan 2 Memory Mapped 10 Main Bus SYS_CLK FPGA A FPGA 2 5 6 Smart media CompactFlash The SmartMedia card socket pins are bussed among the Cypress MCU GPIF pins the Spartan 2 FPGA IOs and the SmartMedia card socket After teset the MCU uses this connection to look for and read the contents of the file main txt on the SmartMedia card The main txt file contains instructions for configuring the user design into the three Virtex 4 FPGAs After reading the configuration instructions the MCU reads the headers of the user s FPGA design bit files and verifies that they target the correct type of FPGA that are installed on yout DN8000K10PCIE This
10. Done FPGA B cleared successfully FPGA A cleared successfully Doing a sanity check Sanity Check passed Configuring FPGA B via USB please wait File D dn BitFiles DN8000K10PCIE MainTest LX100 fpga_b bit transferred Configured FPGA B via USB Figure 12 USB Controller Log Output 8 The message box below the DN8000K10PCIE graphic should display some information about the configuration process The USB Controller program also allows you to easily configure and transfer data to and from the user design on the emulation board More information is provided in the chapter Controller Sofhvare 4 2 Communicating to the User Design over the Serial Port You may want to communicate with your design over the user serial port Pl Only one FPGA can use Pl at a time Before you can communicate to your design change the RS232 multiplexing settings as described in Section 3 6 4 You can also change the RS232 multiplexing settings using the USB Controller software Connect a second RS232 cable to P1 the FPGA RS232 It is located right next to the configuration RS232 port P2 If you have the reference design loaded the FPGA RS232 port runs at 19200 bps 8 bit no parity By default the FPGA RS232 port is connected to FPGA A One the computer s terminal the reference design is programmed to digitally loopback the input to the output If on the terminal you can read your own output then the reference design was able to capture t
11. Instruction Function comment The MCU performs no operation and moves to the next command VERBOSE LEVEL level This command will set the amount of output the MCU will produce over the RS232 port during configuration When level is set to 0 the MCU will produce only error output Before this command is executed the level is set to the default value 3 FPGA A lt filename gt The Virtex 4 FPGA A will be configured with the file named by lt filename gt FPGA B lt filename gt The Virtex 4 FPGA B will be configured with the file named by lt filename gt FPGA C lt filename gt The Virtex 4 FPGA will be configured with the file named by lt filename gt SANITY CHECK lt yn gt If lt yn gt is set to y then the MCU will examine the headers in the bit files on the SmartMedia card before using them to configure each FPGA If the target FPGA annotated in the bit file header is not the same type as the FPGA the MCU detects on the board it will reject the file and flash the error LED Before this command is executed lt yn gt is set to the default value y If you want to encrypt of compress your bit files you will need to set lt yn gt to n Encrypting bit files is not supported or recommended by Dini Group Previous revisions of Xilinx parts have been vulnerable to permanent damage caused by bugs in the encryption circuitry DN8000K10PCIE User Guide ww
12. U6 14 uL Qo DCLKA ES Y 2 fera roum 4 Date o 3 Dan S 16 0MHz FOUTO nCLK 15 12 DCLKB Qi DCLKB C455 18pF 4 25 xTaL2 cours HI E z DCLKBn Four 2x X Mo 9 DCLKTEST He BEE DCLKC xw TEST 1 58 S DCLKCn x oH x 7 0 Xs 2 5 sale 43 3V ET To 5 5 gwe 2 po Ep B Nc 19 vaa 20 vaa as H o 6 dcos Vad 2 0 28 18 1 5 enD 33V R79 AA 1 22 set 2r GND em vco se KU 18 21 mST DCLK 18 sc k vopa o 0585408 ALLCLK SDATA 19 SDATA ALLCLK SLOAD 20 s oan EN OH PLOAD ALLCLK sast C gt E 17 124 veo Hjo GND vec 30 CSEAAZILGFP32 The 8442 outputs are connected to a 1 8 LVDS buffer and distributed to the FPGAs Aclk and Bclk are also distributed to the expansion headers as well Each global clock is delivered to the as an LVDS differential clock The IO input on this clock should be configured as a differential clock input the IBUFGDS primitive The example below shows the Verilog instantiation of this module using the ACLK signal Wire aclk_ibufds IBUFGDS ACLK_IBUFG O aclk_ibufg IB ACLKn The signal aclk_ibufds should then be fed to either a BUFG or a DCM before being used as an internal
13. Figure 21 Spartan II Configuration As soon as the Spartan II FPGA is configured it resets the Cypress microcontroller Pull downs on the PROG pin of FPGAs A B and C ensure that the FPGAs cannot be active unless the Spartan is successfully configured 2 2 2 Smart Media Compact Flash The Smart Media card interface is connected to the IOs of the Spartan 2 FPGA DN8000K10PCIE User Guide www dinigroup com 45 SM D 0 7 To Microcontroller SM 2 U21C SM ALE 3 CLE vo1 m ALE 1 02 10 SM WEn 4 V8 WE 103 10 10 Papel SM WPn 5 ABB WP 04 10 10 Hyp SM CEn 210 WE wo SM REn 209 CE 105 10 10 Fagg RE 06 10 10 Hyg 07 10 108 10 10 ag SM CD tid zp io 2 A 10 10 SM_WPin 27 WP CARD INS 1 2 10 10 WP CARD INS 10 10 Ward 10 10 AB6 AAT 1 19 SM RDYBUSYn AAT 10 10 70 GND 47 07110 10 Te GND LVD x Lg 10 pir 25 GND 22 ya 10 io Ha 8 CGND vec 75 n lo CGND VCC 555555 SmartMedia gt gt gt gt gt gt 25200 oJ F4 TM 565555 43 3V NEM POLYSWITCH C1027 C1028 3 3V 0 1uF 0 1uF Figure 22 Smart Media interface The Smart Media data bus D 0 7 also connects to the microcontroller Currently the MCU connection is not used The Microcontroller is able to read from the Smart Media interface by accessing the Spartan s memory mapped data ove
14. J13 hk hk 1 2 5 A JTAG FPGA TMs FPGA TMS 5 6 RJTAG FPGA TCK L i EN 4 JTAG FPGA E 10 1 FPGA FPGA TDI Hx i8 14 UTAG_FPGA_INITh AG ERES Bh Figure 25 FPGA JTAG Header The JTAG signals TMS is bussed to all three Virtex 4 FPGAs connects to FPGA A the TDO of FPGA is connected to TDI of FPGA B the TDO of FPGA B connects to the TDI of FPGA C and TDO of FPGA C is connected to the TDI of J13 TCK is buffered and passed to each FPGA in a point to point fassion Note These signals should be matched length JTAG Clock Buffer U32 1 RFPGA R278 33R JTAG FPGA TCKA 3 BUFIN CLKO N JTAG FPGA TCKA 5 HFPGA TCK E R279 38H JTAG FPGA _FPGA eua 7 HFPGA TCK C R27i VM 33H JTAG JTAG FPGA TCKB Tg vv JTAG_FPGA_TCKC i a 9 HH CLK6 45 X H X CLK8 49 X 42 5V 19 NT 2 ano von H FPGA JTAG AVDD 4 16 GND VDD Hig TTD Yee 20 0851 44 0826 c914 G 10uF 0 1uF CY2CC9100C wiles 10V 20 TANT Figure 26 TCK buffer The INITn signal is not used DN8000K10PCIE User Guide www dinigroup com 48 Utt FPGA CCLK A w20 Mode FPGA_CCLK_A CCLK selection Slave FPGA PROGn A wee PROGRAM_B HSWAPEN 395 Select FPGA INITn A FOR yas INIT o electmap FP
15. BIT FILE ATTRIBUTES FILE NAME FPGA_B BIT FILE SIZE 003A943B bytes PART 4v1x100ff151317 05 01 DATA 2005 07 19 TIME 17 05 01 Sanity check passed DONE WITH CONFIGURATION OF FPGA The MCU is setting the temperature threshold to cause a board reset TEMPERATURE SENSORS YES B YES FPGA Temperature Alarm Threshold 80 degrees C DN8000K10PCIe MAIN MENU Jul 27 2005 10 38 05 1 Configure FPGAs using MAIN TXT 2 Interactive configuration menu 3 Check configuration status 4 Change MAIN configuration file 5 List files on Smart Media 6 Display Smart Media text file 7 Change RS232 PPC Port 8 Set FPGA Address 9 Write to FPGA at current address a Read from FPGA at current addres Here is the MCU main menu g Display FPGA Temperatures h Set FPGA Temperature Alarm Threshold ENTER SELECTION Options 8 9 and A are only available when the DN8000K10PCIE reference design is loaded For more information on how the MCU communicates with the reference design see Chapeter X The Reference Design Figure 5 RS232 Output You should see the DN8000K10PCIE MCU main menu If the reference design is loaded in the Virtex 4 FPGAs then you should see the above on your terminal Try pressing 3 to see see if the configration circuit was successful in programming the FPGAs ENTER SELECTION 3 CONFIGURATION STATUS kkk kkk kk ke ke ke e e e e FPGA B NO
16. SFP SFP default OPTICAL OPTICAL SFP XFP 3 Other Options 3 1 3 3 V Headers The DN8000K10PCIE can be configured to accept 3 3V input and output on subset of expansion header pins These IOs are not voltage selectable by the software You must specify on your order that you would like this option Select any of the following options The default option is all 2 5V header IO 3 3V Header A 3 3V Header B 3 2 12V Power Daughtercard supply voltages 12V and 12V are by default disabled by jumpers R411 Header A 12V R412 Header B 12V R414 Header A 12V R413 Header B 12V This default setting reduces the chance of damage to the Virtex 4 IO buffers due to user error or careless use of probes Specify this option to have the jumpers factory installed 4 Optional Equipment The Dinigroup supplies standard daughtercards and memory modules that you can use with the DN8000K10PCIE e SE card 80 signals on 1 pitch headers 109 Mictor Card 5 Mictor38 headers for use with logic analyzers SRAM module for use in the 200 pin SODIMM sockets of the DN8000K10PCIE QDRII 300Mhz 64x2Mb SRAM module for use in the 200 pin SODIMM socket 64x2Mb Standard SDR SRAM Pipelined or Flowthrough NoBL available RLDRAM module for use in the 200 pin SODIMM socket 64x16Mb 300Mhz DDRII Flash module for use in the 200 pin SODIMM header Mictor module for use in the 200 pin SODIMM hea
17. er pare E vee it Bes MGTCLK P 105 Zi CAGE GND fre Foren Rxrpi_Los P28 MGTCLK N05 888888888 CAGE GND ot 3 ARH memos 333333333 Er 10 osr Bs MOTEROS 222222222 SAGE 71 REDLED OPT fy REDLED OPT 553588385 CAGE ono x x E 5 E CAGE and xti AK Los RED 48 10 3 D mA 1 INTERRUPT N 893 dV oq qv nw Te XFP2 Connector Ries 5 5 Ri82 RiS7 Rie 185 Risa SIK 51K S 51K SIK S Sik SIK S SIK Virtex 4 FX 1152 ur XFP2 MOD DESEL ANT AVGGAUXRIA 1095 mE tye 2 MOD DES Xre2 MOD 15 AVCCAUXRXS 109 RXPPADA 109 AES INTERRUPT N DCDIS XFP2 INTERRUPT _N AVGCAUXTX T09 RXNPADA 109 m TX DIS i XFPA TX DIS A P so 19 SOL L TXPPADA 109 4685 a SDA XFP2 SDA TKNPADA 109 REFCLK 0810 23 REFCLK MOD ABS HE E E ANO XFP2 MOD ABS P REFCLKn 1 FPZ RX IO EB VTRXB 109 TXPPADB 109 A513 rupto RX Los 44 ae i XFP2 RX LOS 2 109 TXNPADB 109 P DOWN n EXP 2 DOWN VTAXA 109 u VEES XFP Q AREY 109 en yess 6 RXPPADB 109 mars vecs RQNCGESI XEPS RXNPADB 109 8 ne ix AV oe NGOS TES VCC18 XFP2 5 1K o CAGE voce 22 CAGE vo
18. 0x0C000X X4 0x0CO00X X8 0x0C000X XC 0x10000000 Ox17FFFFFF 0x18000002 0x18000004 0x18000006 0x18000010 0x18000011 0x18100001 0x18100002 0x18100003 0x18100004 0x18000001 0x18000003 0x18000005 0x18000007 0x18000008 Ox1CO000X Ox1CO000X X4 Ox1 COOOXX8 Ox1CO000X XC 0x20000000 0x27FFFFFF 0x28000002 0x28000004 0x28000006 DN8000K10PCIE User Guide ABPO IN Name ABP1 OUT ABP1 OE ABP1 IN ABP1 Name BUS XX OUT BUS XX OE BUS XX IN BUS XX Name DDR2B space IDCODE INTERCONTYPE RWREG LED OE LED OUT CLK_COUNTER CLK_COUNTER CLK_COUNTER CLK_COUNTER DDR2HIADDR HIADDRSIZE DDR2SIZEHIADDR DDR2TAPCNTO DDR2TAPCNT1 BUS XX OUT BUS XX OE BUS XX IN BUS XX Name DDR2 space IDCODE INTERCONTYPE RWREG IO on the ABPO interconnect bus The input state of each FPGA IO on ABPO interconnect bus ABPO ascii W ABP1 IO output values W Output enable of ABP1 bus R ABP1 input values ABP1 acsii XX can be 0 21 hex Output status of IOs on bus XX XX can be 0 21 hex OE status of IOs XX can be 0 21 hex The input values The name of the bus XX schematic Mapped to DDR2 SODIMM interface 0x05000121 0x34561111 Scratch Register for testing Controls LED output enables Controls LED outputs Contains contents of ACLK counter Contains contents of BCLK counter Contains contents of DCLK counter Contains contents of SYSCLK counte
19. 9 e 82106 arpa FAULT 8 DAW 3191 103 SPP FAALT E gt DIMM C 18V 0082 SODIMM 10 5 1 SFP SEP modules support 1 4 5Gbs serial trasmission rate Two ted LEDs show the status of the channel The LOS LED indicates that the far end transmitter is not operating the cables are not secured or matched to the transmitter wavelength The FAULT LED indicates a transmission laser failure or an unsecured module D VCCR_SFP1 VCCT_SFP1 9 U10 17 VCCR_SFP1 SFP1 Connector 3 Virtex 4 FX 1152 C332 O 01uF R141 AVCCAUXRXA_105 RXPPADA 105 AESA D nm 105 RXNPADA 106 0 01uF OPT 20 i AVGCAUXRXB_105 C333 TxDn iS seer SFP1 TxFAULT d 84 To TxDISABLE 3 TxDIS tooo veer MOD DEF 2 SFP1 MOD DEF2 TXPPADA 105 Aes 0 kur oen 18 vccr MOD DEF 1 See DES SFP1_MOD DEF1 TXNPADA 105 VCCR MOD DEF 9 4 SEE SFP1 MOD DEFO SFP1_AxDp VEER RATE SELECT Fg SFP1_RATE SEL 105 IDE RD LOS u SFP1_LOS VTRXA_105 RD VEER VTRXB 105 VEER VEER 105 CAGE CAGE VCCT SFP1 TXPPADB 105 HARES CAGE M CAGE en M e BE TXNPADB 105 CAGE CAGE Bi
20. 20 100R TANT TANT TANT l 4 4 Five linear rails 5 2 3 Optical Module Power Optional optical modules have a variety of power by the DN8000K10PCIE XFP power filtering 5 0V L4 5 0V Y s VCC50 XFP1 4 7uH 6820 403377 0317 0 tuF m 0 tuF gt TANT 3 3V L3 3 3V AR gt VCC33 XFP1 4 7uH 5 0V 0519 0336 0316 9 45 0V 22uF 0 1uF 10V 0 1uF 42 5V 1 8V gt 20 9 42 5V L7 TANT 1 8V VCC18_XFP1 Y 3 3V 1 1 1 9 43 3V 089 210594 C619 GND 22uF 0 1uF 10V 0 1uF gt le 20 TANT supply requirements most of which are met 0 5 0 75 1 Since the DN8000K10PCIE has no negative voltage supply it cannot generate the 5 2V required to supply ECL based optical tranciever modules An auxiliary power connector is supplied to connect to an external voltage supply if ECL signaling is required DN8000K10PCIE User Guide www dinigroup com 70 5 Mountin support L5 4 7uH LVEE5_XFP Rey for 5 2V U1 2 1 JMPR DNI 5 3 Heat dissipation Virtex 4 FPGAs are capable of drawing incredible amounts of current from their 1 2V and 2 5V power supplies According to Xilinx online power estimator tool a fully utilized FPGA running at 300Mhz can draw more than 30W of power With this much power used in each FPGA the DN8000K10PCIE can dissipate 75 or more Watts of heat For all but
21. FPGA Design Guide Information needed to use the DN8000K10PCIE with third party software including Xilinx ISE Certify and Identify Some commonly asked questions and problems specific to the DN8000K10PCIE Ordering Information Contains a list of the available options and available optional equipment Some suggested parts and equipment available from third party vendors 2 Additional Resources For additional information go to http www dinigroup com The following table lists some of the resources you can access from this website You can also directly access these resources using the provided URLs DN8000K10PCIE User Guide www dinigroup com 7 Resource Description URL UserDN8000K10PCIE This is the main source of technical information The User Guide manual should contain most of the answers to your questions Dini Group Web Site The web page will contain the latest manual application notes FAQ articles and any device errata and manual addenda Please visit and bookmark http www dinigroup com Virtex 4 User Guide Xilinx publication UG070 http www xilinx com bvdocs userguides ug070 pdf Most of your questions regarding usage and capabilities of the Virtex 4 devices will be answered here including readback boundary scan configuration and debugging E Mail You may direct questions and feedback to the Dini Group using this e mail address support dinigroup com Phone Support Call us at 858 454 3419 d
22. modules if required Xilinx Parallel IV cable LVPECL oscillators for RocketlO MGT clocking The DN8000K10PCIE is supplied with a 250Mhz oscillator Epson Part EG 2102CA PECL Xilinx Chipscope for embedded logic analyzer functionality 112
23. 2 7nF GND 71 5K TOBSOOMSOPIO 1018 as 2 7nF 433v WV e pus MA 25 5 R374 10K V3 1 8V MAL V4 ADJ V2 2 5V Ee Sees 0 5 V V3 1 8V v4 ADJ 0 5 V HARD RESET 5 2 Secondary Power Supplies The secondary power supplies are derived from a primary supply 5 2 1 DDR2 Termination Power DDR2 memory modules use the SSTL18 signaling standard Properly terminating SSTL18 requires a termination power supply of 0 9V Since as much as 1 6 Amps of termination current are needed a switching power supply is required DDR Switching Power Supply VTT 0 9V amp 3A C981 ur C980 C967 43V 100uF DNI 100uF DNI 100 10V 10V 10V C959 TAN TANT TANT n 0 9 AVCC IN R328 100R 1 8V i cosa C982 Sr 100uF u40 w T T 1 8V 16 1 10 R325 71 0858 VDD Fg TANT 1K 1 15 VDD 2 vcca PvDD1 PvDD2 HZ TEAS VREF IN A een is m DIMM_VTT C957 R326 3 3V_R327 10K 09V SHDN 12 3 LDIMM VIT c DIMM VIT 010 1K 1 SHDN vrg T 958 C950 O 9VFB 10 3 3uH il 150uF 150uF 0 1uF als VFB 6 3V Tem C956 4 T 206 20 5 zu PGND1 B 0 001uF 87 PeND2 vrer our H4 TANT TANT AGND 17 DIMM_VREF PKGGND kosvrs 55547 5 16 R316 1K The ML6554 produces up t
24. 25 312 MHz 2 Reference Design Memory Map The Dini Group reference design memory maps the main features of the DN8000K10PCIE to the host interfaces PCI USB and RS232 The Main Bus interface is used to access the reference design memory map Addresses are 32 bits Each address contains a 32 bit word FPGA A 0x08000002 IDCODE 0x05000121 FPGA A 0 08000004 INTERCONTYPE 0x34561111 FPGA A 0x08000000 Scratch Register for testing FPGA A 0x08000010 LED OE Controls LED output enables FPGA A 0x0800001 LED OUT Controls LED outputs FPGA A 0x08100001 CLK_COUNTER Contains contents of ACLK counter FPGA A 0x08100002 CLK_COUNTER Contains contents of BCLK counter FPGA A 0x08100003 CLK_COUNTER Contains contents of DCLK counter FPGA A 0 08100004 CLK COUNTER Contains contents of SYSCLK counte FPGA A 0 0 000000 ABPO OUT W the output state of FPGA IOs connected to the ABPO interconenct bus FPGA A 0 0 000004 OE W The ouput enable of each FPGA DN8000K10PCIE User Guide www dinigroup com 97 INTRODUCTION TO THE SOFTWARE TOOLS FPGA A FPGA A FPGA A FPGA A FPGA A FPGA A FPGA A FPGA A FPGA A FPGA A FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA B FPGA C FPGA C FPGA C FPGA C FPGA C 0x0C000008 0x0C00000C 0 0 000010 0 0 000014 0 0 000018 0 0 00001 0x0C000X XO
25. 61000000 UN 2 41900060 3 de000000 4 04000000 5 dc000000 Please select option _ Figure 13 AETEST Main Menu Run one of the tests Choose option 1 Remember the FPGA you test has to be loaded with the reference design or the test will fail DN8000K10PCIE User Guide www dinigroup com 29 S TEST WITH ANY DAUGHTER BOARDS PLUGGED Verbose output 0 none 9 11 12 on Errors default N y N y Loop default Y Y n n Random test data default N for walking bit test y Drive rest of board to test short circuit y n n Enter all FPGA s to be tested fo ed by a return example ABDEF AB Loop 1 of 1 drive from FPGA_A 468 pins 104 single ended on FPGA_A rive from FPGA_B sted 514 pins 150 single ended on FPGA_B shed with testing ALL TESTS PASSED press any key Figure 14 AETest Interconnect Menu For more information on the AETEST program see Chapter 3 4 4 Moving On Congratulations You have just programmed the DN8000K10PCIE and learned all of the features that you must know to start your emulation project If you are new to Xilinx FPGA you might want move to chapter 4 introduction to ISE and Virtex 4 and start adding your Verilog code to the reference design The user CD contains a netlist of the board to be used as a connection summary All of the source code for the reference design in Verilo
26. 75 78 125 81 25 84 375 87 5 93 75 100 10625 1125 118 75 125 13125 1375 143 75 150 156 25 1625 168 75 175 1875 200 2125 225 237 5 250 262 5 275 2675 300 325 325 3375 350 375 400 425 450 45 500 525 550 575 600 625 650 675 700 BCLK is generated from a 14 318 Mhz crystal Supported frequencies ate 32 22 34 00 35 80 37 58 239 37 4116 4295 44 74 46 53 48 32 5011 51 90 53 69 55 48 5727 59 06 60 85 6264 6443 66 22 68 01 6980 71 59 73 38 7517 76 96 78 75 80 54 82 33 84 12 85 91 89 49 93 07 96 65 100 2 103 8 1074 1110 1145 118 1 121 7 125 3 128 9 132 4 136 0 139 6 1432 146 8 150 3 153 9 157 5 161 1 1647 1682 171 8 179 0 186 1 193 3 200 5 207 6 2148 2219 2291 2362 2434 2506 2577 2649 2720 2792 286 4 2935 3007 3078 3150 3222 3293 3365 2343 6 358 0 3723 386 6 400 9 4152 429 5 443 9 4582 472 55 4868 5011 515 4 5298 5441 5584 5727 587 0 601 4 6157 6300 6443 658 6 672 9 687 3 DN8000K10PCIE User Guide www dinigroup com 34 DCLK DCLK is generated from a 16 0 Fundamental crystal Supported frequencies 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 12 74 76 78 80 82 84 86 88 92 96 100 104 108 112 16 120 124 128 122 136 140 144 148 152 156 160 164 168 172 176 184 192 200 208 26 224 232 240 245 256 264 272 280 288 26 304 312 30 328 336 336 344 352 368 384 400 416 432 448 464 480 496 52 528 544 560 576 59 608 624 640 656 672 688 3 Change Text Editor This options allows the user to select text editor to use the d
27. 9 c 79 10 tes 79 10 1 ROCKETIO CEOCK RESOURCES Rn ER Denen ee Be AERE EYE ER ENS RESTE 79 10 2 MGT POWER NETWORK ea LEANER EEAO ETENE 82 10 3 THE CONNECTIONS eere 82 10 4 SAMTEC MULTI GIGABIT RIBBON CABLE 82 10 5 OPTICAL MODULES 2 84 10 5 1 SEP 2 85 10 5 2 XFP 2 86 10 6 THE SMA Sii Be nete e e RO 87 11 PELEXPRESS M UD IO D 89 11 1 PET EDGE CONNECTOR eer T e teren LEE HE Eee 404 EE EP REPE LER EE 89 11 2 THE GENESYS GL9714 11 2 1 Clocking Methods 11 3 THE PHILLIPS PX10114A 2 92 11 4 VIRTEX 4 FPGA COMMUNICATION 11 5 PCI CLOCKING eee 92 11 6 H 92 12 SYSTEM MONITORA DC s r A E E ES EET AEO ESEETO OEE S E KATTUS 93 13 MECHANICA reco 93 1 EXPLORING THE REFERENCE DESIGN ntn ooo on ost sro NEO KEI OKEE KE ESE AI IEEE prese REPE eR ee 96 1 1 WHAT IS THE REFERENCE DESIGN nun ee 96 2 REFERENCE DESIGN MEMORY MAP 2 1 USING THE REFERENCE DESIGN asus ERE EGER E ELEME EA
28. CLOCK MP 63 3 3 FEEDBACK CLOCKS een REIR 64 4 5 M M 64 5 POWER qe 66 5 1 SWITCHING POWER SUPPLIES YR GORGE 68 5 2 SECONDARY POWER SUPPLIES 69 5 2 1 DDR2 Termina non coe d DR 69 3 2 2 RocketlO power ates 5 2 3 Optical Module Power ann RE ae Xa n ERR devas to EE ED RR EE 70 5 3 HEAT DISSIPATION ar DRE ANN ARR RETRO TREE ROSE 71 6 gue WU Ces diee 72 7 GH OTDDURRUR 73 7 1 CROCKING 4 2 UN 73 7 2 SERIAL PRESENCE DETECH nO ST ERRAT QUEARIS oH EONAR EOS 74 8 HEADERS 8 1 3000K10 C0OMPATBILITY sine nie ED eee EE 75 8 2 PRGA CONNECTION E DU 75 8 3 GETTING LVDS ON THE HEADER 76 84 2000000000 in 77 8 5 77 8 6 DAUGHTERCARD POWER TI 8 7 THE MICTOR de NURSE ERR ERR OB He et Edere Ce ERE ede d 78
29. QOUT IOB 2 Name CLKIN Horizontal ellipsis Repetitive material that has been omitted allow block name hoc loc2 locn Prefix or suffix h Indicates hexadecimal notation Read from address 0x00110373 returned 4552494h Letter H or n 3 2 Content 3 2 1 File names Paths to documents included on the User CD ate prefixed with D This refers to your CD drive s root directory DN8000K10PCIE User Guide Signal is active low INT is active low fpga_inta_n is active low www dinigroup com 3 2 2 Physical orientation and Origin By convention the board is oriented as show on page 3 with the top of the board being the edge near Headers A and B and the edge with the optical module connectors The right edge is near the SMA connectors the left side is the side with the PCI bezel topside refers to the side of the PWB with FPGAs soldered to it backside is the side with the daughtercard connectors The reference origin of the board is the center of the lower PCI bezel mounting hole 3 2 8 Part Pin Names Pin names are given in the form lt X gt lt Y gt lt Z gt The lt X gt is one of U for ICs R for resistors C for capacitors P or J for connectors FB or L for inductors TP for test points MH for mounting structures FD for fiducials BT for sockets DS for diodes F for fuses HS for mechanicals PSU for pow
30. USB Contoller program If the DN8000K10PCIE powered on in firmware update mode there will be an Update Flash button near the top of the USB Controller window Click on this button DN8000K10PCIE User Guide www dinigroup com 36 DiNi Products USB Controller File Edit F r Settings Info Clear Log Maximum packet size is 0x00000200 512 MCU FLASH VERSION Ox4 4 BOARD VERSION DN8000k10PCI SPARTAN CONFIG FPGA VERSION USB to fpga communication enabled Maximum packet size is 0x00000200 512 MCU FLASH VERSION 0 4 4 BOARD VERSION DN8000k10PCI SPARTAN CONFIG FPGA VERSION Figure 16 USB Controller Firmware Update Mode When the Open dialog box appears navigate to the Firmware image file supplied by Dini Group The file name should be flash_flp hex Press OK The USB Controller should freeze for about 10 seconds while the firmware update is taking place When the download is complete the Log window should print Update Complete Power cycle the board to return it to normal operation mode 2 2 Updating the Spartan EEPROM firmware Connect a Xilinx Parallel or Platform USB configuration cable to the parallel port of your computer The Parallel cable requires external power to operate so you may need to connect the keyboard connector power adapter When the Parallel IV cable has power the status LED on Parallel IV turns amber Use a 2mm IDC cable to
31. behavior can be turned off if you have generated unusual bit files for readback or partial reconfiguration etc If this check is passed MCU uses its memory mapped interface with the Spartanll to instruct the SpartanlI to read the Media card and configure the Virtex 4 FPGAs over SelectMap bus 3 Clocking The clocking circuitry on the DN8000K10PCIE is designed for high speed operation The flexible clock design should meet the most difficult clocking needs allowing 8 totally asynchronous controllable clock sources for each FPGA ACLK BCLK DCLK FBACLK FBBCLK DDRFBCLK DDRREFCLK UCLK are differential LVDS signaled clocks The user should use a IBUFDS module in their HDL to receive these clocks on inputs RCLKO RCLK1 RCLK2 and RCLK3 are differential LVPECL signals The user doesn t need to instantiate inputs for these in their HDL because these clocks are automatically routed by the ISE tools when rocketIO is used SYSCLK SCLK1 SCLK2 are 2 5V LVCMOS signals PCLK is a 2 5V SSTL2 signal DN8000K10PCIE User Guide www dinigroup com 59 2 LVPECL lowyjitter Oscillators 250Mhz or other speeds SYSCLK 48Mhz FBACLK FBBCLK DDR SODimm 25 Mhz ICS8442 CET x ur 14 3 Mhz ICS8442 Daughtercard Header 16 0 Mhz Xa SYSCLK 48Mhz FBACLK FBBCLK DDR SCLKI SOD
32. bit into FPGA A CLOCK FREQUENCY AN 4 M 10 This will cause Aclk frequency to be 25 10 250 4 62 5Mhz MAIN BUS 0x0000 0x0001 Writes to a register in FPGA A Even if you are not planning to configure your Virtex 4 FPGAs using a SmartMedia card you may want to leave a SmartMedia card in the socket to automatically program your global and rocketIO clock Clocks may also be programmed using the provided USB application or over the MCU RS232 terminal 2 3 3 USB The USB interface on the DN8000K10PCIE is provided by the Cypress microcontroller unit The Cypress microcontroller is programmed to interrupt when it recetves a USB vendor request When the MCU receives over USB a Bulk Transfer type request it does not interrupt The raw data contained in the bulk transfer is driven out on the GPIF pins of the MCU the SM 0 7 DN8000K10PCIE User Guide www dinigroup com 51 Figure 28 Main txt Commands signals to the Spartan 2 The data is clocked out using MCU_IFCLK clock signal to the Spartan 2 As long as the signal GPIF_CTL is held high by the MCU the Spartan 2 clocks to receive the USB data When data is written to the Spartan 2 from a bulk transfer over the MCU s GPIF interface the Spartan 2 either writes that data onto the SelectMap interface of the Vitex4 FPGAs or onto the Main bus using the Main Bus interface described in the Reference Design chapter The control register SELEC
33. clock for FPGA logic 3 2 User Clock The DN8000K10PCIE has an SMA pair reserved specifically for inputing a clock The SMA pair is connected to a differential clock input on FPGA A LVDS DCI is a preferred input standard but LVCMOS_25 will work also DN8000K10PCIE User Guide www dinigroup com 63 User CLK Input Note these have been changed to SMA J6 4 UCLK 5 CONN SMA J5 UCLKn T 4 at CONN SMA GND VRNA3 VRPA3 J19 3 LC 3 IO LaN GC VREF LC IO L5N GC 1C 3 IO L6N GC 1C 3 IO L7N GC 1C 3 IO L8N GC LC 3 0 VCCO 3 VCCO 3 K19 N2 5 IO 13N GC LC 3 22 J21 J20 M21 M20 12 Lig p2 P21 L21 K21 K20 il N21 I S z CC 1C IO L1N GC CC IO L2P GC VRN 1 lO L2N GC VRP LC 3 IO L3P GC LC 3 IO L4P GC LC 3 IO 15 GC LC 3 0 IO 16 GC LC 3 2 IO L7P GC LC 3 IO L amp P GC LC 3 Uri AL DNB8000K10PCI Virtex 4 LX 1513 To use this clock in synchronous design send a copy of the clock out through the Feedback A clock output pairs A B and C 3 3 Feedback Clocks User FPGA A and B each are capable of sourcing a clock that is distributed to all FPGAs including back to itself These feedback clocks allow the user to control a clock from inside the user design for single stepping multiplication division or distributing a clock to which only one
34. connect the programmign cable to the DN8000K10PCIE connector SPARTAN JTAG DN8000K10PCIE User Guide www dinigroup com 37 SPARTAN JTAG Figure 17 Firmware Update Header Power on the DN8000K10PCIE When the Parallel IV cable is connected to a header the status light turns green Open the Xilinx program Impact usually found at Start gt programs gt Xilinx ISE 7 1 gt Accessories gt impact Impact may ask you to open an impact project Hit cancel Choose the menu option File gt Initialize Chain Impact should detect 2 devices in the JTAG chain Xc18v02 and Xc2s200 For each item in the chain Impact will direct you to select a programming file for each For the xc18v02 device select the Spartan Firmware update file provided by Dini Group This file should be named prom mcs Hit Open Impact will then ask for a programming file to program the 25200 Press Bypass DN8000K10PCIE User Guide www dinigroup com 38 7 Uatitied Configuration Mode IMPACT Dn BHimosss3x 300g460n08YV Boundary Scan Slave Serial SelectMAP Desktop Configuration Erne Before Progamming 7 r Pead Protect r Validating chain idary tcan chain validated s PROGRESS END End E Tm xct 045 vo20 xct 8p Ls4U set ttribute position 1 attr devicePartName value xcl v02 setAttribute position 1 attr configFileHeme value blackhorse F DiniProd DN50001 17 Loading file blackho
35. daughtercard terminate the signal with the following circuit DN8000K10PCIE User Guide www dinigroup com PDETECTA DN8000K10PCI Daughtercard Daughtercard Virtex 4 Header r Receiver Device LVCMOS25 2mA Data in This circuit terminates the differential signal at the destination with 100 Ohms differential impedance It also divides the voltage produced by the LVCMOS25 buffers down to a lt 400mV differential voltage The power requirement for this IO remains fixed at 6 2mA regardless of frequency of operation 8 4 IO Power The IOs connected to the headers on the Virtex 4 FPGAs are powered with a 2 5V power rail 8 5 Physical Micropax part number FCI 91294 003 The standard Dini Group mounting hole location for all 200 pin Micropax connections 1s 430 mils 8 6 Daughtercard Power Power is supplied to the daughtercard though dedicated power supply pins The maximum allowed current for each of the daughtercatd supplies is 5 0V 1A 3 3V 1A 25 12V 250mA 12V 250mA The 12V and 12V supplies are by default disconnected by removing the series jumper resistors R413 R412 R411 R414 This help prevent accidental damage due to careless probing The 12V and 12V supplies may be able to source as much as 0 5A of current if the current can be supplied by the host PC DN8000K10PCIE User Guide www dinigroup com 77 8 7 The Mictor There is a Mictor conne
36. is found in the common subdirectory 3 1 4 The Xilinx Embedded Development Kit EDK EDK is not used 3 1 2 Xilinx XST The Dini Group uses XST software for design synthesis The XST projects for each of the 3 FPGAs on the DN8000K10PCIe can be found at buildxst xst These projects have been compiled using XST version 9 1 3 1 3 Xilinx ISE The Xilinx project manager program is not used to compile the reference design Instead each of the ISE software components are called separately It is possible to create a project file for the reference design In this case the top level edif file and the correct UCF file for the you would like to compile will have to be added to the project The correct type and package FPGA will have to be selected in the project options 3 1 4 The Build Utility Make bat The Build Utility is found at IDN8000K10PCIE build make bat This batch file is used to set system parameters to the desired configuration i e V4FX60 vs V4FX100 etc and to invoke all of the above tools from the command line Instructions for invoking the batch file can be found by viewing the batch file with a text editor Additional information about using the batch file to build the reference design is found below Taking the reference design through all of the various tools for several FPGA s can be very tedious and time consuming this batch file can do it allin one command The command line utility Make bat is an MS
37. that controls single stepping designs Both clocks are delivered to FPGAs A B and C The clock is sourced directly from the Spartan 2 configuration FPGA These signals have no defined control interface Contact Dini Support if these clock paths are required Sysclk this 48Mhz single ended clock is driven from the configuration FPGA at a fixed frequency It is delivered to FPGAs A B C and the configuration FPGA This clock is used by the Dini Group reference design to clock the Main Bus interface MCU clk this reference clock is used by the MCU to generate frequencies required for the USB protocol It is not available to the user UCLK This differential clock input is delivered to FPGA A It connects directly to a pair of external SMA connectors FBACLK This differential clock is driven from FPGA and delieverd to FPGA A B and C This clock can be used for controlled clocks odd clock division and multiplication or forwarding a clock from on FPGA to another FBBCLK This differential clock is driven from FPGA B and recived at FPGA A B and C HACLK This differential clock is driven from the daughtercard header A to FPGA A HBCLK This differential clock is driven from the daughtercard header B to FPGA B DDRACLK DDRBCLK This differential clock is driven by the FPGA to its associated DDR2 Sodimm header A copy of the clock is externally buffered and the clock is recived on the FPGA synchronized with its atrival at the S
38. the most trivial designs heatsink must be used with the Virtex 4 FPGA The DN8000K10PCIE comes with a forced air heatsink rated at 2 degrees per Watt Since the maximum operating junction temperature of a Virtex 4 FPGA is 85 degrees assuming an ambient temperature of 50 degrees the inside of yout computer case the most amount of energy dissipated by the FPGA using the standard fan is 85 30 2 27 5W This should be sufficient for most applications If you intend to operate the Virtex 4 FPGA at very high speeds are getting overheating issues with your design you will need to install a larger heatsink 011 1 Virtex 4 LX 1513 295 28 HSWAPEN PROGRAM aeri INIT 977 0 CS B xg 2 DONE cH PWRDWN B RDWR B DOUT BUSY LTy24 0 Y 6 aY2 2 DIN cW24 Vaart Haat TCK A17 AB1 vcco baste em rS VCCO 0 HAE LI vcco oa FF R165 515 1K u4 TEMPA_STBY 2 STBY vec tl FPGA DXP A SCL 14 SCL 2 esa 312 SMBCLK lIC SDA 12 3 C280 C428 SDA SMBDATA 4 1100 1000pF IIC_IRQn 11 DN IRQn lt ALERT FPGA DXN A TEMPA SAO 5 TEMPA SAT 15 ADDO NG 5 2 Bis ADD NC 19 X 1K R167 7 NOTIS GND NC Hia X GND NC 5 x IAX1617A QSOP1 Above The FPGA temperature monitor circuit The MAX161
39. upper address bits for DDR2 interface number of bits in DDR2HIADDR The size of the DDR2 module Current IDELAY values of DDR2 interface XX can be 0 21 hex Output status of IOs on bus XX XX can be 0 21 hex OE status of IOs XX can be 0 21 hex The input values The name of the bus XX schematic Mapped to DDR2 SODIMM interface 0x05000121 0x34561111 Scratch Register for testing www dinigroup com 98 INTRODUCTION TO THE SOFTWARE TOOLS FPGA C 0x28000010 LED OE Controls LED output enables FPGA C 0x28000011 LED OUT Controls LED outputs FPGA C 0x28100001 CLK COUNTER Contains contents of ACLK counter FPGA C 0x28100002 CLK COUNTER Contains contents of BCLK counter FPGA C 0x28100003 CLK COUNTER Contains contents of DCLK counter FPGA C 0x28100004 CLK COUNTER Contains contents of SYSCLK counte FPGA C 0x28000001 DDR2HIADDR upper address bits for DDR2 interface FPGA C 0x28000003 HIADDRSIZE number of bits in DDR2HIADDR FPGA C 0x28000005 DDR2SIZEHIADDR The size of the DDR2 module FPGA C 0x28000007 DDR2TAPCNTO Current IDELAY values of DDR2 FPGA C 0x28000008 DDR2TAPCNT1 interface Spartan 2 USB Requests Vendor Oxb6 PPC RS232 Oxbe MEM MAPPED Oxbb SET EPBTC CONFIG 0580 CLEAR_FPGA Oxad REBOOT 0 5 CHECK FPGA CONFIG 0xb7 SETUP CONFIG Oxbd END_CONFIG MCU RS232 FPGA RS232 Port MB interface
40. 0K10PCI i COPYRIGHT 2005 mm THE DINI GROUP L JOLLA INC 2 v JA n lar Z UI s 9 a 1 5 34 UNIVERSAL M A Figure 9 Configuration Status LEDs Check the power voltage indication LEDs to confirm that all voltage rails of the DN8000K10PCIE are present From the top the LEDs indicate the presence of 5V 3 3V 2 5V and ATX POWER OK Green lit LED s on the voltage present LEDs indicate the rails are greater than 1 7V A green lit ATX power indicates that the voltage monitors inside the ATX power supply are within acceptable operating ranges 5V is 4 5 5 5V 3 3V is 3 0 3 6V If this LED is not lit green the DN8000K10PCIE might not function properly Check the Configuration status LEDs These LEDs are visible from outside the case when the DN8000K10PCIE is installed in an ATX case Under error conditions all four ted LEDs will blink Check the Spartan FPGA status LED DS24 This LED indicates that the Spartan FPGA has been configured If this LED is not lit soon after power on then there may be a problem with the firmware on the DN8000K10PCIE This LED off or blinking may indicate a problem with one of the board s power supplies DN8000K10PCIE User Guide www dinigroup com 22 Check the FPGA status LED DS18 to the upper left of FPGA A This green LED 15 lit when FPGA is config
41. 4 Watch the configuration status output DN8000K10PCIE User Guide www dinigroup com 16 No USB cable detected rebooting from FLASH please wait Setting ACLK N 01 M 000001000 DONE Setting BCLK N 01 M 000001000 DONE Setting DCLK N 01 M 000001000 DONE Setting RICLK N 01 M 000001000 DONE Setting R2CLK N 01 M 000001000 DONE DN8000K10PCIe MCU FLASH BOOT FPGAS STUFFED AB SMART MEDIA INFO MAKER ID EC DEVICE ID 75 SIZE 32 MB FILES FOUND ON SMART MEDIA CARD FPGA_B BIT FPGA_A BIT MAIN 1 TXT MAIN TXT CONFIGURATION FILES FPGA A FPGA_A BIT FPGA B FPGA_B BIT OPTIONS Message level set to default 2 Sanity check is set to default ON N 00 M 000001010 DONE Setting BCLK N 01 M 000001100 DONE Setting DCLK N 01 M 000001000 DONE Setting RICLK N 01 M 000001000 DONE Setting R2CLK N 01 M 000001000 DONE CONFIGURING FPGA AK RAR Performing Sanity Check on Bit File BIT FILE ATTRIBUTES FILE NAME FPGA_A BIT FILE SIZE 003A943B bytes PART 4vlx100ff151317 09 38 DATA 2005 07 25 TIME 17 09 38 The global clocks ACLK BCLK DCLK are frequency configurable The M binary sequence represents the multiplication applied to the installed crystal The N represents the division applied U6 U14 U20 U31 and the ICS8442AY datasheet The MCU is setting the clocks t
42. 50Mhz 4 lanes 10 bit 250Mhz 4 lanes 16 bit 125Mhz 2 lanes 20 bit 125Mhz 2 lanes The DN8000K10PCIE 8 can only be used in the first mode This means that the interface between the GL9714 and the FPGA can only run at 250Mhz The Genesys GL9714 has four power states The default state when the FPGA A is not configured or does not implement a PCI express controller is full powered mode It is required that the mode is changed to power down to reset the PHY See the datasheet 11 2 1 Clocking Methods The following diagram shows a clocking method validated on the DN8000K10PCIES This method is suitable for 8 lane operation Since this method uses the PCIE2_PCLK signal revision 1 boards require a rework wire to use this method DN8000K10PCIE User Guide www dinigroup com 90 FPGAA 10B Flip flops RX 25 anne GL9714 Channel B Resync Channel c Lane 0 DCM BUFG Optional Channel D BELKIN eLKo gt b 8 or 10 bit Lane 1 b CLKFB 250Mhz he Kane PCI EXPRESS CLKOUT PHASE SHIFT HONE TX Channel A Lane CORE Logic nel anne Resync e ioni Channel D BUFG DCM CLKIN CLKO CLKFB CLKOUT PHASE SHIFT FIXED PHASE SHIFT 90 PCIE PCLK SSTL I DCI 250Mhz RX d 2 5 Gbs anne Logi ChannelB GL9714 Reape Channel E DCM BUFG Channel D l
43. 7 s bus is connected to the Cypress MCU DN8000K10PCIE User Guide www dinigroup com 71 Above Colling fan power connector 6 FPGA interconnect The DN8000K10PCIE was designed to maximize the amount of interconnect between the two primary Virtex 4 FPGAs A and B This interconnect was routed as tightly coupled differential LVDS to provide the best immunity to power supply and crosstalk noise so that your interconnect can operate at the full switching speed of the output buffers Following Xilinx recommendations the interconnect on the DN8000K10PCIE was designed to operate at 1Gb s for every LVDS pair Note 1Gb s operation requites the fasted speed grade patt LX200 12 In order to achieve such breakneck speeds you will need to operate the busses of signals using a source synchronous clocking scheme The interconnect signals on the DN8000K10PCIE have been optimized to operate in lanes There are 7 lanes between FPGAs A and B three between B and C and two between FPGAs A and C Each lane has a differential LVDS source synchronous clock in each direction You can get a summary of the FPGA interconnect signals in the customer netlist provided on the user CD or using the UCF files used for the LVDS reference design FPGA A Utt 7 FPGA B U12 8 AH o ue 6 10 19 CC LC 6 Ho AES AS Io LIN 6 OLN cC 1C 6 HERO ee f io LiP 5 10 CC LC 5 HE ABC ee Ass i2 Hi ABpi2 ABN
44. 7 26 L28 Per aan REPT 830 10 01705 IO L25N CC LC 5 FERRO AG 20 ABNi3 H29 O L18P_5 5 F33 23 6 n20 ABP14_ B32 IO_LIEN 5 1 126 5 H30 ABP1 Jio ABp21 ABNI4 B33 O L19P 5 5 J30 ABNT T 11 J29 10 195 to t27N S Ga2 ABP25 FB 22 ABNTI Keo G33 ABN25 8855 REBT Bae IO L20N VREF 5 IO L28N VREF 5 Fass ABPSo p23 ABNI7 B31 9 L21P_ 5 A36 ABN20 n23 Rt ABP 1g C33 O L21N_5 IO L29N 5 31 ABP21 RB 499R IO L22P 5 IO L30P 5 2 5V 24 499R ABNIg C34 10 1228 10 13085 kat ABN21 Lit 24 42 5V VAN B5 Fai O L22N 5 N 5 B36 ABPTO R7 L10 ABp25 VRP B5 Gai B37 ABN1O AR KS 25 Bas 10 123 1013105 730 ABP24 R18 Daag 0 124P_00 10 5 io 31 ABN24 pim IO L24N CC LC 5 1O L32N 5 pS SENS a dd 9999999990 90909999999 59559999599 2 5V Clocking incoming data at high speeds required the used of the each input s delay buffer to align each bit The incoming clock needs to be adjusted and used to clock the inputs within its lane This process can be automated by the use of the new Virtex 4 feature IDELAYCTL DN8000K10PCIE User Guide www dinigroup com 72 For detailed description of the required user design to achieve 1Gbs operation see Xilinx Application note XAPP704 High Speed SDR LVDS Tranceiver Synchronus clocking and single ended signaling are still possible on the D
45. 88 7R 88 7R 6 S 88 7R MGTCLK N 102 E 10 28 C1047 I 1 12 850 13pF al 9 0 01uF 13 14 R77 i a 30 TEST 7 PS 3VAFXO 15 16 1001 U34 499R 25 Bar M2 I 17 18 An nour 2 R61 5 32 Ll T 319 20 f ze 1 M R415 1 Virtex 4 FX 1152 OPT A Ed 4 outs 5 2 Ms 12 25 26 71 T 383V DIN BOUT P3 3VAFXO al R45 2 R452 R453 R454 27 28 P3 3VAFXO 49 98 gt 49 9R 49 9R 49 08 i TOE 30 F iss anp _ 31 32 R62 N R416 TR 33 34 49 9R ISOLV179W 255 1K 55 E iK 23 TEST_CLK 5 100 XTALSEL gt S gt 01044 RIOO_VCOSEL XTAL_SEL ER 39 40 27 0 01uF 41 42 7 gt N ERO 1 MaTCLK 113 RCLK2 SCLK xp 1 43 54 PET cor K 18 SCLK VDDA Kal 2 en MGTCLK N 113 SDATA P3 3VAFXo ALLCLK SLOAD E 20 PS SVAFXO C1045 gt al R244 TK PE HEADER 23x2 F ALLCLK_SRST 17 P3 3VAFXO ALLCLK SRST DIPS ast a 8 10 10R Virtex 4 FX 1152 OPT 76 GND vcc Hs GND vec CS843020 01 Figure 35 MGT 8442 Connections The LVPECL outputs of the ICS843020 are scaled down to meet the input requirements of the MGTCLK inputs An output from the ICS843020 01 is also converted to LVDS and driven to J3 pins 19 and 21 the Samtec QSE DP connector This can be used to forward a RocketIO clock off board along with rocketIO signals to support standards that require an exact reference clock like PCI Express J3 may also drive pins 20 and 22 The ICS843020 01 c
46. AB b pm VITXB 109 TXNPADB 109 CAGE N 109 x CAGE EE 109 mxPPADB 109 LAE CAGE ps Ton RXNPADB 109 5 CAGE CAGE CAGE DAGE Los 88888 00 CAGE RED AVCCAUXMGT 108 58555 CAGE 5555 d 1367073 OPT 10 084 W os 2228 ma REDLED OPT y REDLED OPT x x JpsFr2_FAULT 8 8 sera 690 92 J mA ER ANE CHANG CNDA SFP2_LOS Figure 38 SFP modules 10 5 2 XFP modules are the fastest optical modules that do not require a The specification allows for an optional 5 2V power supply to be provided by the host board for ECL transmitter modules The DN8000K10PCIE provides no 5 2V power so a mounting point U1 is provided for the use of a bench supply if ECL signaling is required VEES_XFP L5 5 PY LVEES XFP C453 22uF gt C496 10V HUE DNI TANT dio 2096 Mounting Holes for 5 2V support Some modules may require a reference clock to retime the transmitted signal The REFCLK signal in the specification The REFCLK signal is connected to a RocketIO output on FPGA C The REFCLK signal should be 1 64 of the data rate driven onto the XFP s TX pins To drive this signal See Xilinx Application note XAPP656 To meet the input requirements of the XFP module you must increase the differential sw
47. AUXMGT 106 ANI Virtex 4 FX 1152 OPT FPGA C RocketIO RIO SMA TXni Figure 40 SMA Connections SMA RXp1 RXPPADA 110 RXNPADA 110 TXPPADA 110 TXNPADA 110 TXPPADB 110 TXNPADB 110 RXPPADB 110 RXNPADB 110 AVCCAUXRXA 110 AVCCAUXRXB 110 AVCCAUXTX 110 VTRXB 110 VTTXA 110 VTRXA 110 VTTXB 110 AVCCAUXMGT 110 MGTVREF 110 EU EE RTERM 110 Tz za ESL S al 555555555 110 222222222 MGTCLK 110 6500000000 RE Virtex 4 FX 1152 OPT lt lt lt lt lt lt lt lt lt The loopback pair AP26 AP25 can be used to test your Virtex 4 fabric design You may want to get the loopback pair working before attempting to transmit high data rates over a cable system DN8000K10PCIE User Guide www dinigroup com 88 11 PCI Express interface 11 1 PCI edge US E oon EMIL M EN p Al 7 2 242 DN800OKIOPCIe COPYRIGHT C 2005 EB THE DINI GROUP LA JOLLA INC MADE IN if BDA WD AAD AV ns moss DN R R een IMM 18 DDR2 SODIMM 11 2 The Genesys GL9714 This section applies to the 8 lane version of the DN8000K10PCIE only The Genesys phy chip takes care of the serialization deserialization of the PCI express interface It also recovers a clock and accomplish
48. DD1 NC NC 1K R167 7 GND NC 1K 8 ND NG MAX1617A QSOP16 This circuit shows the MAX1617 temperature monitor The IIC bus is connected to the Cypress microcontroller 5 Power The DN8000K10PCIE gets is power from the 12V and 3 3V rails of the PCI Express card edge connector It can also be operated in stand alone mode with a 20 pin ATX power supply connector The PCI slot is capable of sourcing 25W DN8000K10PCIE User Guide www dinigroup com 66 The main rails of the DN8000K10PCIE 12 This is the main power supply rail used for the internal digital logic of Virtex 4 FPGAs 1 8V This is used for IO signaling and interal logic of DDR2 SDRAM memory It is also used to supply some Gigabit optical modules and is used as a low power current source to supply RocketlO isolated power rails 2 5V This is used to power FPGA interconnect with low power LVDS It is also used as the analog power supply on the Virtex 4 FPGAs 33V This voltage supplies the LVDS clock distribution trees It is also used to power the LVTTL interfaces of the Cypress microcontroller 12V This voltage is used to supply power to the 1 2 2 5 5 0 and 1 8V switching power supplies It also powers the FPGA cooling fans If the PCI slot isn t providing enough power then a Hard Drive 4 pin power cable can be connected to the board from the same ATX power supply to reduce the voltage droop on 12V Please note that the
49. DOS batch file compatible with Windows 2000 and later operating systems Make bat should be run from the command line with command line parameters It should not be double clicked from the windows environment command prompt shortcut is provided in the same directory as Make bat and can be double clicked to open a command prompt window with the proper working directory 4 Getting More Information 4 1 Printed Documentation The printed documentation as mentioned previously takes the form of a Virtex 4 datasheet and a DN8000K10PCIE User Guide 4 2 Electronic Documentation Multiple documents and datasheets have been included on the CD DN8000K10PCIE User Guide www dinigroup com 104 INTRODUCTION TO THE SOFTWARE TOOLS 4 3 Support Email support is recommended Email support dinigroup com for technical questions Email sales dinigroup com for sales questions Before contacting support you should minimally make the following checks for common errors e Make sure that the clock your design uses is running Output the clock to a probe able IO pin and check it with an oscilloscope e Check the pinout in your constraint file against the provided UCF files and the board netlist on the user CD e Check the PAR report file to make sure that 100 of your IOBs used have LOC consttaints There is never a reason to have fewer than 100 of IOs located e Use the PAD report to make sure your constraints were applied correctly Some s
50. E Sic ILI 23 34 DDRB CK TEST 88 99 go uo go ez gg vs H35 1 idi EI STE el seer OR DN DDRB AVDD Yan a Za EE ES OE Z C22 8 8 83 55 2 35 53 55 33 33 52 ATUF 210 peas foz04 PPP ve oo oo za 2 ur ur lur R79 R80 n go zo gg 55 0n oR 29 DIMMB_CKO 3 He DNNE CRT DIMMB 94 Yin DIMMB CKno 9 E Z aan PLL Bypassed id yen DIMMB CKnt UIZ4 Viriex4LX 1818 ane 1 16 FPGA B Clock m yon HZ Inputs E 5 FBIN FBOUT 0125 Vitex4LX 1513 25 a EROUT IE Y CDCUS77 4 2 5 g VS ws 99 go 100R 18 I2 gv 85 84 35 gd oo 8 89 88 98 98 08 DDRB PLL az az az DORE PI FE 5 55 88 33 33 33 3 88 go o9 gt gt SS Se SI x e SET 55 og lt x 224 54 lt lt 22422 524 lt lt 25V DDRB FB Cn DORE FE Cp DN8000K10PCIE User Guide www dinigroup com 73 SODIMM interfaces 7 2 Serial presence detect The EEPROM on the SODIMM is accessable by PCI USB or configuration UART
51. FPGA has access like a header clock or the user clock input FPGA A has 6 feedback outputs one differential pair to each Virtex 4 FPGA FBACLKAp FBACLKAn FBACLKBp FBACLKBn FBACLKCp FBACLKCn FPGA B has 6 feedback outputs one differential pair to each Virtex 4 FPGA FBBCLKAp FBBCLKAn FBBCLKBp FBBCLKBn FBBCLKCp FBBCLKCn Clocks can also be exchanged from one FPGA to another on the source Synchronous clock inputs See Chapter X Section X FPGA interconnect 4 Reset Topology The DN8000K10PCIE is protected from undervoltage and over temperature by a reset circuit When the board powers on a voltage monitor waits until all voltages are above their minimum DN8000K10PCIE User Guide www dinigroup com 64 voltage levels then deasserts reset The Spartan 2 distributes the reset signal to all FPGAs and the Microcontroller unit so until the Spartan 2 is configured reset remains asserted Temperature Monitors 85 deg C gt Microcontroller FPGA A RESET le W FPGAA PROG Soft Y PROG SEIEN INS Reset PROG Fe v LNL NL NL NL Spartan II FPGA gt Hard Voltage Monitor Reset gehen RESET_FGPAS The user may also assert reset by pressing S3 Hard reset This will trigger the reset signal SYS RSTn which is monitored by the Spartan FPGA When SYS_RST is asserted the Spartan FPGA
52. GA CSn yig CS_B 5 ERS DONE FPGA RD WRn A FPGA X18 PRDWR B PWRDWN B Heto R226 PECA BUSY FPGA BUSY A 20 0 x ix a DOUT BUSY Y23 MSELAO GND x WE Y24 MSELAT R20 3Z5V E Vie uN Mo Y22 KY y 325V R214 JTAG FPGA TMS 1K ET is vBATT Hn JTAG FPGA TCK JTAG FPGA TDI p STAG FRGA TOL _ 4917 vo vooo o LAA TDO VCCO 0 zm VCCO 0 2 R223 ru JTAG FPGA TDIB JTAG FPGA Figure 27 FPGA A Configuration Bank If you ordered your DN8000K10PCIE with one or more FPGAs not installed Option FPGA A NONE FPGA B NONE or FPGA C NONE then a bypass resistor is installed connecting the TDI pin to the TDO pin of the uninstalled FPGA This is so the JTAG chain will remain intact when FPGAs are missing 2 3 2 Media Card SmartMedia or Compact Flash When the DN8000K10PCIE powers on the microcontroller reads the contents of any Flash card that is in the Media Card slot The microcontroller by default opens a file on the root directoy named Main txt if it exists This file contains instructions for the configuration circuitty to configure the Virtex 4 FPGAs To create a SmartMedia card to control the DN8000K10PCIE configuration insert the Media card into a card reader provided and connect it to a PC Create a file on the root directory of the card and call it In main txt write a series of configuration commands separated
53. GA configuration data from a SmartMedia card To program the FPGAs on the DN8000K10PCIE FPGA design files with a bit file extension put on the root directoty of the SmartMedia catd file using the provided usb card reader The DN8000K10PCIE 1 1 lane PCI express ships with a 32 MB SmartMedia card preloaded with the Dini Group reference design The DN8000K10PCIE 8 8 lane PCI express ships with a 128MB CompactFlash preloaded with the Dini Group reference design DN8000K10PCIE User Guide www dinigroup com 14 1 Insert the provided flash card labeled Reference Design into your usb card reader provided Make sure the card contains the files FPGA_A bit FPGA_B bit FPGA_C bit main txt The files FPG_A C bit are files created by the Xilinx program bitgen part of the ISE 8 1 tools The file main txt contains instructions for the DN8000K10PCIE configuration circuitry including which FPGAs to configure and to which frequency the global clock networks should be automatically adjusted Eject the card from the computer using the Eject command on windows insert the flash card labeled Reference Design into the DN8000K10PCIE s SmartMedia slot contacts down or CompactFlash slot label up 3 3 Connect cables The configuration circuitry can accept user input to control FPGA configuration or provide feedback during the configuration process The configuration circuitry IO can also be used to transfer data to and from t
54. He DIMMB DQ26 1 73 55 VSS 74 1 DIMMB BOR DNI DIMME DO27 75 0026 DQ30 7g DIMMB_DOST 0027 HE vss vss om DIMMB_CKEO lt __ 18 E CKEO CKE1 50 zd gt DIMMB_CKE1 83 VDD VDD DIMMB A15 R348 DIMMB BA2 NC Tas DIMME AT4 R347 DIMM VIT 1K LB 37 NC Tas 1K 9 DINMEATZ 8g VOD VOD sn DIMMEATT DIMMB 45 91 412 52 DIMMB 7 DIMMB A6 DIMMB_AB 93 9 AT 94 DIMMB 4 95 6 56 DIMMB AZ DIMME AS 97 YOD von Fos DIMME AT DIMME AT 99 5 DIMME AZ DIMMB_AT 101 102 DIMMB AO 18 103 1 AO 104 TBV _ 56R DIMME ATO 305 VDD os DIMME EAT DIMME BAD 1671 a 108 DIMME RAST BAQ RAS DIMMB RASn DIMMB WEn lt 109 We so HHL Lm DIMMB 8 0 31 8 111 VDD vDD 112 41 8 DIMMB CAS SA H3 CAS Fe DEE DIMMB_ODTO DIMMB_Sn1 HH Si NC Fae HIV DIMMB ODTT VDD VDD DIMMB_ODT E 1 opti NC DIMMB DQ32 Tas VSS VSS 724 f DIMMB DIMM_VTT 0033 125 0032 0936 126 DIMME DQ37 Oi 157 0033 153 RN39 DIMMB DQSn4 T 128 YSS WSS 130 DIMMB DIMMB A5 DIMME 054 131 0054 DM4 732 MM 133 0054 VSS 434 f DIMMB DIMMB T5 VSS 0038 7136 DIMMB DQ39 DIMME DGS5 137 0034 0039 738 139 0035 VSS 146 DIMMB 0044 DIMMB DO40 mar KSA 5 142 DIMME DO45 DIMMB 0041 Lok 148 DQ41 yss Hat DIMMB DQSn5 DIMM VIT DIMMB_DMS a7 V8s DO
55. I express core used at Dini Group for testing purposes is the Xilinx 1 lane PCI express core Contact Xilinx 11 4 Virtex 4 FPGA Communication 11 5 PCI clocking The PHY receives a 100Mhz clock from the PClexpress edge connector This clock is used as a reference to capture the 2 5Gbs PCI express signal The PCIE PCLK and pcie2 pclk on the 8 lane signal is synchronous to both the RX and TX signals of the parallel interface 11 6 PCI Power In some applications the DN8000K10PCIE can draw its power from the PCI Express slot The PCI express specification guarentees that the motherboard provide 25W of 12V power for the DN8000K10PCIE to use Most motherboards provide well in excess of this amount supplying the power for PCI cards directly from the ATX power supply In high power applications exceeding 25W you may need to connect the Auxiliary power connector P3 DN8000K10PCIE User Guide www dinigroup com 92 1 HEADER A am 5 D Lr IH The Aux Power connector is a standard IDE hard drive power connector and should be supplied by the ATX power supply that is in your computer case Aux power connector 12V is shorted to the PCI slot 12V The power suppy driving the PCI slot and IDE power cable must be the same unit 12 FPGA System monitor ADC The System Monitor and ADC functions of the
56. N8000K10PCIE you are not required to use highspeed serial design techniques Single ended interconnect is recommended for signaling below 133Mhz Because of the DN8000K10PCIE s excellent low skew clocking network global synchronous clocking should work fine for your interconnect at speeds lower than 300Mhz The source synchronous clock signals can also be used as single ended or differential interconnect or to forward clocks from one FPGA to another The total interconnect counts between FPGAs e 378 e B C154 e 112 7 Memory interface There are two standard 200 pin DDR2 SODIMM module sockets on the DN8000K10PCIE These sockets are supplied with 1 8V power and keyed for use with DDR2 SDRAMs One socket is connected to FPGA B and the other is connected to FPGA C 7 1 Clocking DIMM VIT place near 954 DDR Buffer R296 4758 R297 47 5R DDRB_PLL_CKOUTp n DDRB PLL 4 38 DDRE PLL CKOUTR lem DORE PIOR cK yo H a 17 Yon a Co38 21 39 22 OS A Indo iw OE Yin a 2 5 6 221 Y2n a m 4 ee vona vs 5 0 SS sls s SE su VDDQ yan a 28 ae 14 Sal 22 vs 2 15 VDDQ ds tr 4 TOKEN 8 Ho 00 99 99 99 99 99 69 99 20 VoDa a OS Sa ov U
57. ODIMM on the signal DDR FBCLK DN8000K10PCIE User Guide www dinigroup com 61 PCLK This SSTL25 signal is driven from the PCI express PHY to the FPGA A It runs at a fixed 250Mhz when the phy is in its default mode This clock cannot be used by FPGAs B and C 3 1 Global Clocks The three main global clocks are driven by ICS8442 clock synthesizers each capable of producing frequencies of 700Mhz or greater The clock synthesizers can be programmed from main txt file SmartMedia and CompactFlash card from the GUI application See Chapter 3 controller software BLock DIAGRAM PiN As VCO SEL XTAL SEL TEST CLK XTAL1 MR CONFIGURATION s GLocK L INTERFACE nP LOAD I gt LOGIC Each ICS8442 has an interal multiplication PLL that can operate between 250 and 700 Mhz With 1 2 4 or 8x division on the output the possible output frequencies are 31 25 700Mhz SEL be used to disable the PLL so ACLK BCLK and DCLK can operate at their fundamental 25Mhz 14 3Mhz and 16Mhz respectively This function has not defined control interface Contact Dini Group support The Serial configuration bus is connected to the Cypress MCU The crystals required to supply a reference to the ICS8442 synthesizers are parallel resonant fundamental mode 18pf DN8000K10PCIE User Guide www dinigroup com 62 DCLK generator C341 18 V R181 100R 26
58. ONE LX100 10 11 12 LX160 10 11 12 LX200 10 11 1 3 FPGA Select an FPGA part to be supplied in the C position This fpga is connected to a momory module socket This FPGA is required to provide Multi Gigabit serial communication In order to achieve 10 Gbs selectIO operation the 12 speed grade is required NONE FX40 10 11 11x 12 This option makes the 200 pin SODIMM memory socket one SMA channel four QSE cable channels and one optical module socket unusable FX60 10 11 11x 12 This option makes four channels of OSE cable unusable FX100 10 11 11x 12 2 Multi Gigabit Serial Options 2 1 Serial Clock Crstals If you need to interface to a specific Multi gigabit serial IO protocol you may want to specify a compatible crystal Chose one of the following frequencies in Mhz 9 8304 12 890 14 318 16 000 21 477 24 576 25 000 The default option is 25 000 Mhz 2 2 Module Sockets 108 and SFP Modules provide 1 0 10 5 Gb optical serial communications to FPGA C DN8000K10PCIE has two optical ports each can be installed with either an SFP connector modules operate only in the 9 5 10 5 Gb s range Available SFP modules operate between 1 4 25 Gb s For 10Gb operation a 12 speed grade FX part may be required These parts may not yet be available before If you have the FPGA C option you may select one of the following options OPTICAL
59. PGA A is configured DS14 FPGA_B DONE The Virtex 4 FPGA is configured DS16 FPGA_C_DONE The Virtex 4 FPGA C is configured DS8 SFP2 LOS SFP module 2 Loss of signal DS4 SEP2 FAULT SFP module 2 transmitter fault DS5 XFP2 INT module 2 error DS1 XFP2 FAULT XFP module 2 transmitter fault DS6 SEP1 LOS SEP module 1 Loss of signal DS2 SEP1 FAULT SEP module 1 transmitter fault DS7 XFP1 INT XFP module 1 error DS3 XFP1 LOS module 1 Loss of signal DS48 DS47 DS46 DS45 User LEDs from FPGA C DS44 DS43 DS42 DS41 DS40 DS39 DS38 DS37 User LEDs from FPGA A DS36 DS35 DS34 DS33 DS32 DS31 DS30 DS29 User LEDs from FPGA A DS28 DS27 DS26 DS25 Figure 10 DN8000K10PCIE LEDs DN8000K10PCIE User Guide www dinigroup com 25 4 Using the Reference Design with the Provided Software To communicate with the reference design on the DN8000k10PCIE you should use the USB interface The USB interface allows configuration of the FPGAs and bulk data transfer to and from the User design The RS232 interface allows low speed data transfers to and from the User design and control and monitoring of the configuration process This section will get you started and show you how to operate the provided software For detailed information about the reference design and implementation details see The Reference Design chapter 4 1 Operating the USB controller program Use the provided USB monit
60. RENTO GA IEE LED 108 3 OTHER OPTIONS a cena psa eoe Ven 109 3 1 ES HEADER S aus I aaa are 109 3 2 I2V POWER 109 4 OPTIONAL EQUIPMENT Chapter About This Manual to DINSO00KTOPCIE Logic Emulation Board Congratulations on your purdhase of the DNS000K10PCIE LOGIC Emulation Board If you are unfambar with Dini Group produds you should read Chapter 2 Quick Start Guide to yourself with the user interfaces the DINS8000K10PCIE provides Figure 1 DN8000K10PCIE 1 Manual Contents This manual contains the following chapters About This Manual List of available documentation and resources available Reader s Guide to this manual Quick Start Guide Step by step instructions for powering on the DN8000K10PCIE loading and communicating with a simple provided FPGA design and using the board controls Board Hardware Detailed description and operating instructions of each individual circuit on the DN8000K10PCIE Controller Software summary of the functionality of the provided software Implementation details for the remote USB board control functions and instructions for developing your own USB host software Reference Design Detailed description of the provided DN8000K10PCIE reference design Implementation details of the reference design interaction with DN8000K10PCIE hardware features
61. S20 0 7 The DN8000K10PCIE is shipped with a fun mounted above the power supplies to help keep them cool If you need to remove this fan the DN8000K10PCIE will function properly without it but be careful not to touch the power supplies with your fingers because they will burn Each power supply is protected with a 15A fuse on the inputs If you need to operate the DN8000K10PCIE with more than 15A of current for a power supply you can change this fuse but you need to find a heatsink solution for keeping the Virtex 4 FPGAs cool The heatsink and fan provided are appropriate for a power consumption of about 10 15W per FPGA DN8000K10PCIE User Guide www dinigroup com 68 Each of the primary power rails 5 0 3 3 2 5 1 8 1 2 is monitored for undervoltage If the voltage monitor circuit detects a low voltage it will hold the board in reset until the supply is back within 5 of its setpoint See section X Reset Circuit for information on reset 12V 18 25V 50V 433v 43 3V Reset Circuit R359 124R R373 R367 R358 1K 845R OR R364 R371 1K 2 EXE 88 7R u23 RST 2 VREF amm t 324 H Svs RSTn 8 28 0K us A360 VPG va R368 9 7 28 0K R361 5 3 1108 T M VEG T 100R SORT R372 R363 5 z C102 71 5K 100R TI TORT R357 TCZ800MMSOPi0
62. SS Tag DIMME DASS 14g DM5 Dass Hey RN24 DIMMB_DQ42 t51 VSS VSS 152 DIMMB_DQ46 DIMMB_BA1 0043 153 0042 0046 154 DIMMB_DOf DIMMB_RASn 155 0043 0047 156 DIMMB DO48 T3257 55 VSS A58 f DIMMB_Das2 DIMMB A13 DIMME DO49 159 0048 0952 160 DIMME DG53 ter 0049 Das3 455 121631 VSS VSS 164 DIMMB 56R X165 NC TEST OKI DIMMB_CK1 DIMMB_DaSns__ 167 YES CK 168 DIMMB_CKn1 DIMM_VTT DIMME DASE 168 i A 170 DIMMB DM6 171 172 RN38 DIMMB_DQ50 T7177 VSS VSS 74 f DIMMB_DQ54 DIMMB_BA2 DIMMB 0051 175 0050 0054 7176 DIMMB 0055 DIMME ATZ 177 0051 0955 DIMMB DQ56 1757 Ss VSS 80 DIMMB_Daso DIMME 10057 181 0056 0960 189 DINNE DOST 183 0057 past Hist DIMMB_DM7 185 s d 186 f DIMMB DQSn7 DIMMB 095 DIMMB DQ58 tae vss Hag Dass vss Ha I DIMM_VTT DIMME DOSI 5521 0055 192 DIMMB DQ62 DINME DOES SDA fiss vss Dasa Fr Toc IO EDA s IC SCL 197 SDA 55 388 7 DDRB SAO TS SA0 200 DORE SAT 333 R350 CONN_DDR2_SODIMM200 10K 8 Headers There are two daughtercard headers on the DN8000K10PCIE one attached to FPGA A Header A and one attached to FPGA B Header B Header A contains 135 user IOs designed to operate as 134 differential pairs Header B has 154 user IOs that can be used as 77 differential pairs DN8000K10PCIE User Guide www dinigroup com 74 The signals RESET is driven by the
63. Spartan Configuration FPGA This signal is the same as the RESET FPGAs driven to FPGAs A and PDETECTA and PDETECTB are signle ended signal with an external pull up resistor The daughtercard can ground these signals to indicate the daughtercard s presence The HAp nCC and HBp nCC signals are connected to global clock input pins on the FPGAs These can be used as differential clock inputs from the daughtercard headers to the FPGAs They can also be used as outputs The ACLK and BCLK signals are copies of the DN8000K10PCIE global differential clocks ACLK and BCLK The signals are synchronized at the daughtercard connector with the ACLK BCLK signals at the pins of the FPGA Header B has more signals than Header A A daughtercard designed to work with header A will work with header A 8 1 3000K10 Compatibility The DN8000K10PCIE headers use pinout similar to that on the DN3000K10 A compatibility chart with the DN3000K10SD and Mictor daughtercards is given on the user CD in the daughtercard directory 8 2 FPGA Connection On the DN8000K10PCIE all header signals are connected to LC pins on the Virtex 4 FPGA See the Virtex 4 User s Guide for detail about these signals The main result of this is that the headers on the DN8000K10PCIE may not be used with the Virtex 4 s current mode LVDS drivers Virtex 4 LVDS receivers may still be used Outputs compatible with LVDS can still be achieved using the proper selectIO driver setti
64. Sse 134 RXPPADB 102 AVCCAUXMGT 102 HH Note These signals should be routed RNP ADEE Ge as differential pairs Each of the airs shall be matched length Each y MGTCLK P 102 34 pair must be 100 ohm controlled MGTCLK N 102 NSS differential impedance S88888828828888838 15 lt 5444 2 lt 22222222222222 oeooooooooooooo EREEREER EE 1152 28 THIS BANK DOES NOT CONNECT FX 60 FX 100 Only U10 14 id SEI2 RxP AGO RXPPADA 101 AVCCAUXRXA 101 PRETO RXNPADA 101 AVCCAUXRXB 101 FBS AVCCAUXTX 101 825 12_ SSE an TXPPADA 101 DEON _ BA TXNPADA 101 101 27 0 ISEI1 TxP ic ER VTRXA 101 855 L6 TXNPADB 101 VITXA 101 vrTXB 101 28s ISEI QESEN Rx 28 RXPPADB_101 RXNPADB 101 CHB29 GNDA 101 101 228 9 GNDA 101 GNDA 101 8221 GNDA 101 ET 101 cAI GuDA 101 ilex 4 FX 1152 Each connector also has a clock input that can be routed to the MGT CLK of FPGA C to allow standards that require transmitting at an exact frequency such as PCI Express 10 5 Optical Modules The DN8000K10PCIE comes with two optical module connectors If you need to interface to a specific standard the easiest way is to buy an SFP or module that supports that standard DN8000K10PCIE User Guide www dinigroup com 84
65. T configured The easiest way to verify your FPGAs are configured is to look at DS18 DS14 DS16 located above each FPGA When the green LEDs are lit the FPGA under it is successfully configured DN8000K10PCIE User Guide www dinigroup com 19 3 3 2 Interactive configuration If you want to put multiple designs on a single Smart Media card you can use the interactive configuration menu to select which bit file to use on each Select menu option 2 ENTER SELECTION 2 INTERACTIVE CONFIGURATION MENU 1 Select bit files to configure FPGA s 2 Set verbose level current level 3 Enable sanity check for bit files M Main Menu Enter Selection Figure 6 Interactive Config Menu 3 3 3 Read temperature sensors The DN8000K10PCIE is equipped with temperature sensors to measure and monitor the temperature on the die of the Virtex 4 FPGAs According to the Virtex 4 datasheet the maximum recommended operating temperature of the die is 85C degrees If the microcontroller measures a temperature above 80 degrees it will reset the DN8000K10PCIE If you think your DN8000K10PCIE is resetting due to temperature overload you can use the temperature monitor menu to measure the current junction temperature of each FPGA ENTER SELECTION g FPGA TEMPERATURES Degrees Celsius 4 B 29 Set FPGA Temerature Alarm Threshold degrees C decimal values range 1 127 Old Thresh
66. T within the Spartan 2 determine to which interface this data is touted to 2 4 FPGA configuration Process For information regarding the JTAG interface and configuration See Xilinx publication UG071 Virtex 4 configuration guide When configuring over USB or SmartMedia the FPGAs are configured over the Virtex 4 SelectMap bus All SelectMap signals are connected directly to the Spartan2 FPGA The SelectMap signals are D 0 7 SelectMap data signals PROGRAM_B Active low asynchronous reset to the configuration logic This will cause the FPGA to become unconfigured The documentation refers to this signal as PROGn DONE After the FPGA is configured it is driven high by the FPGA INIT Low indicates that the FPGA configuration memory is cleared After configuration this could indicate and error RDWR_B Active low write enable The Documentation refers to this signal as RDWR BUSY When busy is high the SelectMap configuration stream must stop until BUSY goes low CS B SelectMap chip select The documentation refers to this signal as CSn CCLK Signals D 0 7 DONE RDWR B and CS B are clocked on CCLK Each Virtex 4 FPGA has a complete set of SelectMap signals connected point to point to the Spartan 2 except for FPGA B and C who share signals D 0 7 All signals are 25V CMOS signals except for D 0 7 of FPGA A Signals SELECTMAP DJ0 7p which 3 3V CMOS DN8000K10PCIE User Guide www dinigroup com 52 All commands requi
67. The INI Group LOGIC Emulation Source User Guide IoNSO000IKKTOPCTEe LOGIC EMULATION SOURCE DN8000K10PCIEe User Manual Version 1 The Dini Group 2006 7469 Draper Ave La Jolla CA92037 Phone 858 454 3419 Fax 858 454 1728 support dinigroup com www dinigroup com Table of Contents TABLE OF CONTENTS ABOUT THIS MANUAL s 1 2 3 MANUAL CONTENTS DEDE 7 ABOUT THIS MANUVA D ETAT SEN CRT NE ORA cn AE IAN T QUICK START GUIDE BOARD HARDWARE ud CONTROLLER SOFTWARE Ti REFERENCE DESIGN 7 FPGA DESIGN G DEN seen Ss 7 ORDERING eu ees 7 ADDITIONAL RESOURCES 7 Char 8 3 1 DIENEN TRO ERUN EAR ER HOw Ea vai oe wR Uae Sw ER wea RN ERA 8 32 CONTENT 29 3 2 1 File names 29 3 2 2 Physical orientation and Origin 32 3 Part Pin 10 3 2 4 Schematic Clippings 2 10 3 2 5 10 QUICK START GUIDEW 1 2 3 4 PROVIDED MATERIALS seiscese onere too eae ese
68. Virtex 4 FPGA are no longer supported by Xilinx The most important responsibility of the System Monitor temperature sensing has been moved to the configuration circuitry The DN8000K10PCIE will automatically monitor and prevent thermal overload in the three Virtex 4 FPGAs No user action is required FPGAALX 200 Reserved pins U11 18 9 Av20 VREFN SM VCCAUXA 2 5V Aw21 VREFP_SM AVI SI AVSS_SM gt gt E 5554 S Se lt lt Es Qn lt lt Virtex 4 LX 1513 E VREFP ADC VCCAUXA 2 5V E s paa AVDD ADC 20 VN 55 ADC 13 Mechanical The dimensions of the PWB are 312mm long by 135mm tall plus a 8 25mm PCI edge connector This is taller than the PCI specification allows although the DN8000K10PCIE fits easily inside most ATX computer cases DN8000K10PCIE User Guide www dinigroup com 93 IU TURF XT Fr E 138 47 a 4 434434444444 N PEPEE E 4444144 4 4 44 4 QU Ml viis ie ng t HeH H f tapaa SH HIE HEHE 3 MES UNES di EM rem Qe tI gp H qu t amb 4 Jine rb ir pe At HE B Gt 8 MS HH a Hi teuer er fa xi p E agat the Er 4 i tH uh ee gg ate gh t MG ste ate ate Ht M oW E Af
69. an receive this clock and use it to generate a frequency for the MGTCLK inputs For 10Gb serial transmission rates you should use one of the low jitter fundamental frequency SAW oscillators These oscillators operate at 250Mhz and so cover the gaps in the frequency synthesis options given by the ICS843020 01 DN8000K10PCIE User Guide www dinigroup com 81 Error NEAR FPGA OSC2 3 3VREG NEAR OSCILLATOR FB103 NL FOR EG 2101CA R432 10 0K R433 1K Rin 74 OHM TO NOTE 42 R435 R436 129 OHM T 240R 240R OSC2 1 oE vec H OSC2 PU 2 uc Guns OSC2 Yn OSC2 ano our 4 als EG Z101CA 250Mhz AES R439 R440 010 20 33R 33R C1048 0 01uF T MGTCLK N 110 MGTCLK_P_110 C1049 R441 R442 0 01uF 49 9R 49 9R Virtex 4 FX 1152 OPT OSC3_3 3VREG NEAR FPGA NEAR OSCILLATOR OSC3_3 3VFILT 102 NL FOR EG 2101CA R419 10 0K R421 1K M PULL R422 R423 is 100R 100R Osca vc 1 AC COUPLING ON HAVE DONE FURTHER OSCS PU x EIS duis 5 OSCS Yn 1 OSC3 3 an our 1 EM EG ZTOTCA 250 R426 R427 U10 17 88 7R 88 7R C1053 0 01uF Ane MGTCLK 105 MGTCLK N 105 C1054 R428 R429 0 01uF 49 9R 49 9R Vinex 4 FX 1152 OPT Figure 36 MGT PECL Oscillators There are two Epson2101CA SAW oscil
70. asuring the voltage levels of each rail near the top left of the DN8000K10PCIE Each rail is monitored by a voltage monitor circuit and will cause a reset if any of the primary supplies drop 5 or more below their setpoints There are also LEDs next to each testpoint to indicate the presence of each voltage rail These LEDs do not indicate that a rail is within 5 of its setpoint only that the rail is present and above 1 6V A power OK led shows the status of the ATX power supplys PWR_OK signal If this LED is lit then 5 0V and 3 3V and 12V 12V are within 5 of their setpoints 5 0V 42 5V 43 3V 41 8V o o PWR OK 2 R129 R131 R130 R134 R155 390R 82R 150R 30R 287R Japwr_oK Jo5 ov laz sv 1 sv mA 59 DS11 DS10 DS12 10 DS13 4 4 4 green wp x x x x x x 5 1 Switching power supplies The main power rails for the Virtex 4 FPGAs are produced on board with three 20A switching power supplies one for each of 1 8V 2 5V and 1 2V TP5 F2 Qn Switching Power Supply 1 2V 20A 41 2V PSU2 4 ag 25V IN L2V 6 yw vour ate C288 C264 C338 C279 C310 C357 SENSE 2 C339 C340 l Q00uF 24 100uF 100uF 1OuF 10uF 1OuF il 150ur L 150uF 10V 10V 10V 6 3V 6 10 10 10 1 2 ONOFF 1 ON OFF 20 20 C TANT F TANT TANT ES 12V VTRIM C TANT TANT R2 R177 R176 10K 1 8M zl YNCO5
71. board is capable of exceeding the 25W limit of the PCI connector depending on the desity of the FPGAs utilized and the operating frequency 5 This voltage supplies some RocketIO power The DN8000K10PCIE also has these secondary rails 0 9 This voltage is used to terminate the SSTL18 signaling of the DDR2 memory module Current is drawn from 3 3V RocketIO 1 2V top 1 2V right 1 2V bottom These linear regulated rails are very low noise supplies for the RocketlO CML inputs and outputs and RocketIO logic They are isolated from each other to improve the isolation of multiple RocketIO channels operating simultaneously RocketIO 1 5V This linearly regulated voltage rail supplies the internal digital logic of the RocketlOs RocketIO 2 5V this linearly regulated voltage rail supplies the internal analog circuits of the RocketlO 12V This rail is passed directly from the PCI edge connector and ATX power connector to the Micropax expansion header See Chapter X Section X Expasion Headers Note that the fuse between 12V and the expansion headers is not installed on the board DN8000K10PCIE User Guide www dinigroup com 67 VEE5 Power for this rail is not supplied by the DN8000K10PCIE but is required for the operation of ECL optical modules To power this rail you will need to connect an external power connector to the board from a low noise voltage supply There are test points for me
72. ce 88888 CAGE ia 109 88888 CASE m 25255 CAGE GND 28088 CAGE GND 6666 CAGE GND CAGE GND SEE 055 psi 2222 SAGE ano REDLED OPT RED LED OPT CAGE GND XFP2 RX LOS Se AGE GND CAGE GND RED ol g g RED 10 2 2 TOETST RFP OPT 1 D8 10 a ma Figure 39 XFP Modules 10 6 The SMAs The easiest way to connect two RocketIO channels is through the use of SMA cables The SMA connections on the DN8000K10PCIE were designed to operate at the full 11Gb potential of the Virtex 4 RocketIO trancievers DN8000K10PCIE User Guide www dinigroup com 87 J20 CONN SMA Bag J21 CONN SMA 5 1 4 J22 CONN SMA RIO SMA TXpO AP21 Bank not present in FX 40 Part U10 18 AP26 AP25 AP23 AP22 RIO SMA TXnO AP20 RIO SMA 0 AP18 5 9 1 4 J23 CONN SMA 5 1 4 J16 CONN SMA 5 1 3 4 J17 SMA J18 SMA 5 1 RIO_SMA_RXn0 17 U10 20 RXPPADA 106 RXNPADA 106 TXPPADA 106 TXNPADA 106 TXPPADB 106 TXNPADB 106 RXPPADB 106 RXNPADB 106 GNDA 106 GNDA 106 GNDA 106 GNDA 106 lt a z 1 AN AN AVCCAUXRXB 106 AVCCAUXRXA 106 AN AVCCAUXTX 106 AN2 VTTXB_106 106 VTRXB 106 VTTXA 106 AVCC
73. cted designed to be used with an aginlent logic analyzer Riscwatch power PC debugger can also be used over this connection J4 MICTORO MICTOR13 GND 4 OR14 MICTOR DBG HALTn g MICTOR MICTOR q 0 PPC_JTAG_TDO PPC_TRC_VSENSE R101 1K_ 3 3V ORA 4 PPC_JTAG_TMS a PPC JTAG TD 9 0 _TRSTn V OR 4 TRC TS10 PPC TRC TS2O a PPC TRC TS1E rU ern MICTOR10 PPC_TRC_TS4 7 OR PP R 40 GND 42 al 43S CONN_MICTOR38 Figure 32 Mictor Header DN8000K10PCIE User Guide www dinigroup com 78 9 LEDs Green 10mA ea 80mW tot 0530 0528 GREEN LED GREEN LED DS32 GREENLED K EN GREEN LED DS31 DS29 GREEN LED REEN LED LEDA3 LEDA2 QLEDA QLEDAO eo r u ETT Re 2222 56R TINO Q FPGA A is connected to 8 green LEDs 4 LEDs on 8 lane version FPGA C is connected to 16 LEDs These LEDs can be used for the user design The brightness of these LEDs can be controlled by changing the output standard the LED signals from 2 4 12 16 or 24mA Also pulsing can be used to reduce the brightness of these LEDs Figure 33 FPGA C LEDs 10 RocketlO 10 1 RocketlO Clock Resources Since it is impossible to determine during manufacturing the clocking requirements of every possible end application the DN8000K10PCIE comes with a flexible clock network capable of a wide range of serial frequencies w
74. d writes is initiated by the Spartan II FPGA when the reference design is in use USB_CLK evscaky77 Meo dx A ge pe Are RD Spartan MB 34D WR ET MB l I DONE 4 4 MBBp6 AD 211 Bi MBB1 0D ALE Spartan MB 32D All transfers a synchronous to the USB or SYS signal This clock is fixed at 48Mhz and cannot be changed by the user This clock is LVCMOS single ended When the ALE signal is asserted by the configuration circuit the slave device on the bus the FPGA is DN8000K10PCIE User Guide www dinigroup com 102 INTRODUCTION TO THE SOFTWARE TOOLS required to register the data on the on AD bus This is the main bus address All future transfers over the main bus ate said to be at this address until a new address is latched On a later clock cycle the master may assert the RD signal Some time after this within 256 clock cycles the FPGA should assert DONE for one clock cycle On this cycle the master Spartan will register the data on the AD bus and that will be the read data If DONE is not asserted then a timeout will be recorded and the transaction cancelled 15 a wtite transaction USB CLK SYS CLK RD Spartan SEN E SR Fei Y TELE CUI Te RN VOTERS RE ERE NO MB WR Spartan MB 33 DONE e
75. der 2 Mictor 38 connectors for use with logic analyzer 110 L DiNi Products USB Controller File Edit FPGA Configuration FPGA Mer Settings Info Exi Refresh Enable USB gt FPGA Com Port 1 Clear Log BOARD VERSION DN8000k10PCI SPARTAN CONFIG FPGA VERSION 0x9 Maximum packet size is 0 00000200 512 MCU FLASH VERSION 0x4 4 BOARD VERSION DN8000k10PCI SPARTAN CONFIG FPGA VERSION 0x9 MCU ERROR REGISTER 0x0 Maximum packet size is 0 00000200 512 MCU FLASH VERSION 0x4 4 BOARD VERSION DN8000k10PCI SPARTAN CONFIG FPGA VERSION 0x9 The Dini Group can optionally provide the following accessories DN3k10SD Daughter card Provides tenth inch pitch test points DNMictor Daughter card Provides 5 Mictor connectors compatible with logic analyzets Memory modules for use in the DN8000K10PCIE DDR2 SODIMM sockets and B Available Q4 05 QDRII SRAM 64x1Mb 300Mhz Flash memory 32x4Mb 2x4Mb serial flash Reduced Latency DRAM RLDRAM 64x8Mb 300Mhz Standard SRAM 64x2M Select ZBT Pipelined Flowthrogh Test connection module with two Mictor38 You may also want to obtain from a third party vendor 200 pin DDR2 SODIMM s SEP modules for Gigabit Ethernet infiniband IBM part 13N1796 from insight com 180 XFP modules Intel part TXN181070850X18 from insight com 692 heatsink clip Tyco part 1542992 2 5 2V bench supply for powering ECL based
76. e DN8000K10PCIE Features exercised in the reference design include e Access to the DDR2 SDRAM Modules At 200Mhz e Communication e FPGA Interconnect e Interaction with the Configuration FPGA and MCU e Use of Embedded PowerPC Processors eventually e Memory Mapped Access Between PPC And User Design eventually e Access to external LEDs e Communication via Rocket I O Transceivers e Instantiation of Daughter Card Test Headers e USB memory map to DDR2 memory Pin multiplexed FPGA interconnect using LVDS at 650Mbs per signal pair DN8000K10PCIE User Guide www dinigroup com 96 INTRODUCTION TO THE SOFTWARE TOOLS All source code for the reference design is included on the CD and may be used freely in customer development Precompiled bit files for the most common stuffing options are also included and can be used to verify board functionality before beginning development A build utility described in the section Compiling The Reference Design can be used to generate new bit files to generate bit files for less common configurations of the DN8000K10PCIE The reference design was created using Here ate the default main txt file lines verbose level 2 sanity check y clock frequency AN 4 M 16 100 MHz used for PCI MB test header test uses this clk clock frequency B N 2 M 28 200 MHz clock frequency D N 2 M 25 200 MHz clock frequency 1 N 2 M 25 312 MHz clock frequency 2 N 2 M
77. e Design Mainbus Settings Info Extras Refresh Enable USB gt FPGA Com PPC Port 1 Clear Log USB to FPGA communication is disabled Enable if you warto usee desatures MCU FLASH VERSION 0 16 22 BOARD VERSION DN8000k10PCIe8 SPARTAN CONFIG FPGA VERSION 0x20 Figure 11 USB Controller Window 5 This window will appear showing the current state of the DN8000K10PCIE Next to each FPGA a green light will appear if that FPGA is configured successfully If you have the reference design loaded and a DDR2 SODIMM installed you can use the USB Controller to run tests of the SODIMM From the FPGA Memory menu select Test DDR DN8000K10PCIE User Guide www dinigroup com 27 6 Clear the FPGAs of their configurations Right click and select from the popup menu Clear FPGA The green light above the FPGA on the GUI and on the board should stop shinning green 7 Configure an FPGA using the USB Controller program Right click on an and select Configure FPGA via USB from the popup menu The program will open a dialog box for you to select the configuration file to use for configuration Browse to the provided user s CD USERCD BitFiles 8000K10PCIE MainTest LX100 fpga_a bit If you are configuring an LX200 or FX60 devices you should select a bit file from the LX200 or FX60 directories instead If you are configuring FPGA B or FPGA C you should select fpga_b bit or fpga_c bit instead
78. e s aont epe ineo Yon is ea endorse 12 ESD WARN N G 13 POWER ON INS TFRUCTIONS EST M 13 3 1 MEMORY AND HEATSINK Seia een Ea ERN GA PERDERE CX EBENE LEEREN SERNEC RAPERE God rub REEL RR 14 32 PREPARE CONFIGRATION FILES 14 3 3 CONNECT CABLES eren 3 3 1 Watch the configuration status output 16 3 3 2 Interactive configuration 2 20 3 3 3 Read temperature sensors 20 3 3 4 Multiplex Serial port 2521 3 4 CHECK LED STATUS LIGHTS NeT 21 USING THE REFERENCE DESIGN WITH THE PROVIDED 0 2 2 26 4 1 OPERATING THE USB CONTROLLER PROGRAM ceeeseesessenseesnesnssnennennensensensensonsonsnnsonsnennessensensensensensensonsonsnnsnsssessensessessensensenson 26 42 COMMUNICATING TO THE USER DESIGN OVER THE SERIAL PORT 28 4 3 USING AETEST TO RUN HARDWARE TESTS 29 4 3 1 AETest on Linux or Solaris 4 3 2 Use AET estones s 4 4 MOVING ON lesen 30 CONTROLLER SOFTWARE n 1 LONI AOH YELO H 32 1 1 MENU M 32 1 1 1 File Menu 1 1 2 Edit Menu 25 1 1 3 FPGA Configuration Men
79. each by a new line A valid command is one of the following comment FPGA A filename FPGA B filename FPGA C filename CLOCK FREQUENCY lt clockname gt N number M number SANITY CHECK yn VERBOSE LEVEL level RS232 lt portnumer gt lt fpganame gt MEMORY MAPPED 0x lt SHORTADDR gt 0x lt BYTE gt MAIN BUS 0x lt WORDADDR gt 0x lt WORDDATA gt DN8000K10PCIE User Guide www dinigroup com 49 lt comment gt can be any string of characters except for newline lt filename gt can be the name of a file on the root directory of the SmartMedia Card number can be any one or two digit positive integer in decimal lt clockname gt can be A B D 2 A is ACLK B is BCLK D is DCLK and 2 is the RocketlO clock synthesizet lt yn gt can be the letter y or the letter n lt level gt can be 0 1 2 or 3 lt portnumber gt can be 1 2 3 or 4 The DN8000K10PCIe only has 1 user RS232 port 1 so 2 4 will cause no operation lt gt can be A B C D E F G H I The DN8000K10PCIE only has 3 fpgas A B C so D I will cause the RS232 pott to not function lt SHORTADDR gt is 2 digit hex number 16 bits BYTE is a 1 digit hex number 8 bits WORDADDR 4 digit 32 bit hex number representing a main bus address WORDDATA 4 digit 32 bit hex number containing data for a main bus transaction The following table describes the function of each of the available main txt commands
80. efault editor is notepad 4 FPGA Stuffing Information This option will display the type of FPGAs that are stuffed on the DN8000K10PCIE 5 MCU Firmware Version This option will display the MCU Firmware version in the log window 6 BOARD SPARTAN Version This option will display the Board Version along with the Spartan Config Fpga Version 2 Updating the Firmware Dini Group may release firmware bug fixes or added features to the DN8000K10PCIE If a firmware update is released you will need to There are two firmware files that Dini Group may release the first is a Micro controller MCU software update that is stored in a flash memory This update can be accomplished easily from within the USBController application The second update that may be required is a Spartan FGPA core update The configuration data for the Spartan FPGA is contained in a Xilinx configuration PROM This update can be accomplished with the Xilinx JTAG programming program iMpact 2 1 Updating the MCU flash firmware To protect against accidental erasure the MCU firmware cannot be updated unless the board is put in firmware update mode during power on DN8000K10PCIE User Guide www dinigroup com 35 Figure 15 Switchblock 1 To put the board in firmware update mode find the User Reset button Hold down this button while the board powers on or hold down this button and also press and release the Hard Reset button Open the
81. er supply modules Q for discreet semiconductors RN for resistor networks X for oscillators Y for crystals lt Y gt is a number uniquely identifying each part from other parts of the same X class on the same PWB lt Z gt is the pin or terminal number or name as defined in the datasheet of the part Datasheets for all standard and optional parts used on the DN8000K10PCIE ate included in the Document library on the provided User CD 3 2 4 Schematic Clippings Partial schematic drawings are included in this document to aid quick understanding of the features of the DN8000K10PCIE These clippings have been modified for clarity and brevity and may have omitted parts and connections Unmodified Schematics are included in the User CD Please refer to this document Use the PDF search feature to search for nets and patts 3 2 5 Terminology Abbreviations and pronouns are used for some commonly used phrases MGT and RocketIO are used interchangeably MGT is multi gigabit transceiver RocketlO is the Xilinx trademark on their multi gigabit transceiver hardware MCU is the Cypress FX2 Microcontroller U39 DN8000K10PCIE User Guide www dinigroup com 10 Quick Start Guide The Dini Group DNS000K10PCIE zs the user friendhest board available with multiple Virtex 4 FPGAs However due to the number of features and flexibility of the board it will take some time to become familiar with all the control and monitoring interfaces equip
82. es receive detect The Dini Group does not supply a PCI express FPGA core You must implement this in the FPGA fabric or aquire one from an IP vendor One such vendor is ASIC Architect http www asic architectinc com Each genesys GL9714 is connected to four of the eight PCI express lanes Each lane is sent to the FPGA A over the signals Signal Name PCIE lane Direction Synchronous Clock PCIeRXA 0 7 Lane 0 Receive PCIe PCLK PCIeRXB 0 7 Lane 1 Receive PCle PCLK 0 7 2 Receive PCle PCL PCIeRXDJ0 7 Lane 3 Receive PCle PCLK PCIe2RXA 0 7 Lane 4 Receive PCIe2 PCLK PClIe2RXB 0 7 Lane 5 Receive PCIe2 PCLK PCIe2RXC 0 7 Lane 6 Receive PCIe2 PCLK PCIe2RXD 0 7 Lane 7 Receive PCIe2 PCLK DN8000K10PCIE User Guide www dinigroup com 89 The GL9714 provides a 250Mhz clock PCLK to the FPGA Revision 1 Boards The signal PCIE2 PCLK is not connected to a FPGA clock input pin and is not suitable for use as a clock Your board must be reworked to connect PCIE2 PCLK to a GC pin on the FPGA When this rework is complete the PCIE2 PCLK signal will connect to pin AP22 on FPGA The clock source of the GL9714 comes externally from the 100 MHz PCI express REFCLK The GL9714 uses the clock source with its PLL to generate the 2 5 GHz bit rate for transmitting and receiving The GL9714 also drives a clock output for the synchronization of MAC interface in the FPGA The GL9714 supports four modes 8 bit 2
83. ference crystals The MCU loads the user s desired multiplication value and division N value into the settings registers in the ICS8442 chip 2 5 3 LEDs The MCU is connected to 4 red LEDs that are visible from outside the PC case when the DN8000K10PCIE is plugged into a PCIe slot 1 lane only The LEDs flash a status code during and after configuration All four flashing LEDs means there has been an error configuring at least one FPGA 2 5 4 Memory space The XDATA memory space of the MCU is partitioned into four sections 0x0000 Ox1 FFF internal data program memory 0x2000 external SRAM OxDFFO OXDFFF memory mapped registers no external memory accesses OxE000 OxFFFF reserved by MCU RD WR strobes not active in this region The internal data memory region is mapped to an internal SRAM in the Cypress MCU When the microcontroller code calls memory access from this region the external Address and Data busses are not used After power on reset the MCU reads from the IIC Eprom connected to the MCU_EPROM signals and fills this internal memory before allowing the PC to run The code in this section of memory contains core functions of the Dini Group firmware like setting up the interrupt registers communicating with USB and allowing firmware updates The external SRAM 15 used for heap data The memory mapped register region The DF region contains registers in the Spartan 2 FPGA that control FPGA confi
84. g including embedded PowerPC code and utility is included on the provided CD DN8000K10PCIE User Guide www dinigroup com 30 Controller Software 1 USB Controller USBController application is used to communicate with the DN8000K10PCIE USBController source code is included on the CD ROM shipped with the DNS000K10PCIE The USBController can be installed on Windows 98 ME 2000 XP There is a command line version called AETEST_USB that can be installed on Linux and Solatis The USBController Application contains the following functionality Verify Configuration Status Configure FPGA s over USB Configure FPGAs via Smartmedia card Clear FPGA s Reset FPGA s Set Global clocks frequency Set RocketIO CLK Frequency Update MCU FLASH firmware The following function interface with the Dini Group reference design Read Write to FPGA s see the reference design chapter for address maps Test DDRs FLASH Reigsters FPGA Interconnect 1 1 Menu Options 111 File Menu The File Menu has the following 2 options a Open opens a file with the selected text editor notepad by default change the text editor see Settings Info Menu section b Exit Closes the USBController application 1 1 2 Edit Menu The Edit Menu performs the basic edit commands on the command log in the bottom half of the USBController window 1 1 3 FPGA Configuration Menu The FPGA Configuration Menu has the foll
85. guration The program memory space of the MCU is directly mapped to the external Flash memory When the Cypress MCU is reset which happens after the Spartan 2 is configured it loads its boot code into its 8kB of internal memory from a serial EEProm U13 The code in the EPROM instructs the MCU to execute code located on the FLASH memory U19 The code in the EEPROM and FLASH is located on the user CD 3 3V 3 3V 3 3V EEPROM R251 R250 013 2 2K 2 2K 3 R240 1K R239 VV AD VCC IIC_SCL_MCU SDA R238 IK I es U_EPROM 1 co ro 2 SDA GND WP 24LC64 TSSOPB R252 1K Address 00000001 0x01 em RAM Space 0x0000 to Ox1FFF DN8000K10PCIE User Guide www dinigroup com 55 Communication over the MCU memory bus to the Spartan 2 is synchronized to the 24Mhz MCU CLK For information regarding the timing of transactions on this bus see the Cypress CY7C68013 user manual 480Mhz PLL IFCLK Spartan 2 Memory Mapped 10 Main Bus SYS_CLK FPGA A FPGA The Configuration FPGA is connected to the MCU_DATAJ7 0 signals the MCU ADDR 15 0 signals and the OE signal allowing it to decode address accesses of the MCU The Configuration FPGA is programmed to respond to accesses in the XDATA address space in the address range of OxDFO00 to OxDFFF Communication over the MCU memory bus to t
86. he Config FPGA is synchronized to the 24Mhz MCU CLK X2 For information regarding the timing of transactions on this bus see the Cypress CY7C68013 user manual 430Mhz PLL IFCLK Spartan 2 Memory Mapped 10 Main Bus SYS_CLK FPGA FPGAB FPGA C The following registers implemented in the Configuration FPGA are accessible as part of the MCU s XDATA addtess space Register Name XDATA Description Address DATA DFO00 Used when reading from SM but not configuring COMMAND DFO1 Commands for the SM DN8000K10PCIE User Guide www dinigroup com 56 ROW LADDR DF02 Holds lower 8 bits of SM addtess ROW HADDR DF03 Holds upper 8 bits of SM address ROW XADDR DF04 Holds extra bits of SM address NUM BYTES 0 DF05 Holds lower 8 bits of the number of bytes to read NUM BYTES 1 DF06 Holds upper bits of number of bytes to read in BITS 1 DF07 BIT7 mcu config rd BIT6 BITS_2 DF08 4 FPGA DONE BIT3 CPLD idle BIT2 SM SIGNALS DF09 MCU_XADDR DFOA Address register for upper FLASH SRAM bits MCU_CNTL DFOB Addtess register for upper FLASH SRAM bits FPGA_SELECT DFOC FPGA select 5 0 bits 5 0 PPC RS232 ABSELECT DFOD PPC RS232 CDSELECT DFOE FPGA_CNTRL DFOF bits 1 0 01 write address 10 data write 11 FPGA_BE DF10 select byte in addr read a
87. he DONE light goes on you will know that the configuration process was successful 2 5 MCU The operation of the Spartan II is monitored and controlled by a Cypress CY7C68013 microcontroller The microcontroller also has a USB 2 0 interface that can be used to monitor the board control configuration or transfer data to and from the user FPGA design Basic operation can be controlled over an RS232 link from a computer terminal 2 51 RS232 The primary method of user interaction with the DN8000K10PCIE configuration circuitry is the MCU s RS232 port P2 The Cypress CY7C68013 has two RS232 pins that are buffered through a 12V voltage translation buffer for use with a standard computer serial port DN8000K10PCIE User Guide www dinigroup com 53 PPC RS232 Interface MCU and 2 5V RS232 ppc 5232 TX 5 7 RS232 TXD3 A 8 E XD4 o H 5232 RX S 13 RS232 RXD3 m R1OUT RIIN ASS RYDT MCU 12 R2oUT R2IN ND x tour LIN 11 EET c2 0 1uF 1 3 4 5 C1 O 1uF 22 C229 0 1uF E H H Figure 29 RS232 Buffer and Headers The RS232 port will be able to communicate with a standard PC serial port set to 19200 baud 8 data bits no parity no handshaking When you connect a computer terminal to the port and power on the DN8000K10PCIE the firmware loaded on the microcontroller unit will display a menu on the terminal This menu will allow you to cont
88. he RS232 signal and generate RS232 signal that your computer could capture DN8000K10PCIE User Guide www dinigroup com 28 If you familiar with previous Dini Group products the reference design test outputs could be read from this serial port On the DN8000K10PCIE you must use the AETEST application to read the results of self test 4 3 Using AETEST to run hardware tests AETest is the program that you can use to verify the hardware on the DN8000K10PCIE as well as to demonstrate the reference design function The following instructions assume you have a PC running the Windows XP operating system The user CD includes a Windows version of the AETest program If you plan to use the DN8000K10PCIE in stand alone mode connect the DN8000K10PCIE to your WindowsXP computer and use aetest_usb in D aetest_usb aeusb_wdm exe If the computer asks for a driver click Have Disk and browse to D AETest_sb driver win_wdm dndevusb inf 4 3 1 AETest on Linux or Solaris To use the AETest application on Linux or Solaris you must compile the source code included on the User CD Instructions for compiling AETest are found in chapter 3 4 3 2 Use AETest The Aetest application should display it s main menu mulator PCI Controller Driver VA M on Jul 22 2005 at 12 58 24 P PCI Menu M Memory Menu FPGAs stuffed AB 1 Interconnect test 2 Read clock frequencies 3 Configure FPGA 4 HGT Menu Q Quit PCI ru z z 0
89. he user design 1 Use the provided ribbon cable to connect the MCU RS232 port P2 to a computer setial port to view feedback from the configuration circuitry during FPGA configuration Run a serial terminal program on your PC On Windows you can use HyperTerminal Start gt Programs gt Accessories gt Communications gt HyperTeminal and make sure the computer serial port is configured with the following options Bits per second 19200 e Data bits 8 e Parity None e Stop Bits 1 e Flow control None e Terminal Emulation VT100 Use the provided USB cable to connect the DN8000K10PCIE to a Windows computer Windows XP is recommended Plug an ATX power supply into J1 or plug the DN8000K10PCI into a PCI slot Do not plug an external power supply into J1 if the DN8000K10PCI is in a PCI slot Turn on the ATX power supply The 4 pin aux power supply connector P3 can be used if connected to the same power supply as the host computer This is not required for operation so you should leave it disconnected DN8000K10PCIE User Guide www dinigroup com 15 4 When the DN8000K10PCIE powers on it automatically loads Xilinx FPGA design files ending with a bit extension found on the SmartMedia or CompactFlash card in the SmartMedia slot into the FPGAs View configuration feedback over RS232 As the DN8000K10PCIE powers on your RS232 terminal connected to P2 will display useful information about the Configuration process 3 3
90. hile maintaining the tight jitter requirements of the 10 Gigabit serial trancievers DN8000K10PCIE User Guide www dinigroup com 79 The RocketlO clock tree is driven by a synthesizer and two oscillators and dedicated multiplexers inside the Virtex 4 FPGA allow the user to switch between these clock sources Rock gt MUX 2 5 Rocket MUX H io 102 f 2 1 SAMTEC cable MGTCLK Oscillator AP29 AP28 4 1 gt 250Mhz MUX H oio 2 MGTCLK Rocket M34 N34 MUX H IO 105 1 Optical Module 1 gt wx ICS843020 e gt MUX age 1 Optical Module 2 px MGTCLK LY 1 MIET IO fio sma a 7 0 H sma 1 1 SMA 1 Rocket K 1 H SMA Oscillator y MSTELK jy 10 112 j sma 250Mhz SMA 1 L5 Rocket MUX H 1o 113 SMA 2 Rocket ty SAMTEC cable MUX H jo 114 K 2 Figure 34 Internal MGT clocking The RocketlOs on the Virtex 4 FPGA is divided into two columns and X1 The clock network of each column is separate and clocks may
91. i8 A26 827 ABCLKn 14 io 12 6 IO L10P 6 ABE E28 IO LIN ADC7 5 IO L9N CC LC 5 ABBTE spot BIg 12 6 IO L10N 6 3 ABIT BNT Boe 1012 ADC6 5 IO L10P 5 Hass ABNIE 825 612 1 _6 IO LHP 6 ES AB gt FR ADC6 5 IO L10N 5 Di1 IO L1IN 6 ABpi BACLKno 027 O L3P ADCS 5 IO_L11P 5 H27 ABNIZ ABna D10 6 59 ABn a BP 10 13 5 5 ION 5 c32 ar Di 14 VREF 6 10 Li2N VREF 6 Bis Br ABRE l 5 1O L12P 5 535 ABNE ABna Cu 6 A15 ABni5 ABP22 G8 O L4N VREF 5 IO L12N 5 B28 ABP2 ABp Aii O L5N_6 10 L13N 6 Ft1 ABpi6 ABN22 G26 5 5 10_L13P_5 cos ABNZ bd Aio 16 _6 IO L14P 6 Harr ABS1E BPS Bee 15 ADC4 5 1O L13N 5 Fass ABP IT 21910 6 IO L14N 6 B12 ABETT BNE E29 10 16 5 1O L14P 5 A34 ABNIS ABB IO L7P 5 10_L15P_6 HB ABar ABO res 16 ADC3 5 IO L14N 5 Hess ABES Bio 17 6 IO L15N 6 Fas ABNG A28 1 IO L7P ADC2 5 IO L15P 5 Fess Dei CC LC 6 IO Lt6P 6 Hes AB IO L7N ADC2 5 10 L15N 5 Fest ABSS IO L8N CC LC 6 10 L16N 6 Pe DBS 10 L8P ADCI LC 5 5 E35 io LN ADCT LC 5 10 L1eN 5 7 J14 E16 BACLKpO ABn7 Hi3 O L17P_6 Io L25P CC LC 6 pie BACLKnO ABP7 _ H25 M27 Be 6 HBr m SENS e 0 117 _5 10 L25P CC LC 5 eg LD7 ABpi9 ABN
92. iki sranie IOTER Ee TELE 33 1 1 4 Settings Info Mehta p e PER ODE e A be e tn alt edu tee ee 34 2 UPDATING THE FIRMWARE T Y 35 21 UPDATING THE MGU FLASH FIRMWARE ern In 35 22 UPDATING THE SPARTAN EEPROM FIRMWARE cccsccsscssscsssscseccssccssccescesecesscsnscsescsnscenscsnecsuscenscenacsnscsuscsnscenscsnscsneseneaenees 37 HARDWARE ho hh hy yh 1 OVERVIEW 2 CONFIGURATION CIRCUIT E 43 2 1 OVERVIEW ne Moose E 43 2 2 THE SPARTAN 2 FPGA 44 2 2 1 Spartan Configuration 2 2 2 Smart Media Compact Flash 2 2 3 MCU communication 2 46 2 2 4 8232 46 2 2 5 TL ses 47 2 3 2 3 1 2 3 2 2 3 3 24 2 5 2 5 1 is 2 5 2 ur 0 RR 54 2 5 3 LEDS 55 2 5 4 Memory space ER 2 5 5 2 5 6 Smart media Compa ctFlash cci tc Re URINE 59 3 LGB eO 4 C 59 3 1 O OBAT IS VE eve level 62 312 USER
93. imm SCLK2 48 Mhz _ Osc SCLK1 pak SCLK2____ PP SYSCLK 48Mhz SYSCLK 48Mhz cr L SYSCLK 48Mhz BCLK Daughtercard ACLK MCU CLK 24Mhz PCI express PHY REFCLK 100Mhz PCI Connedor SMA Connector Figure 31 DN8000K10 clocking DN8000K10PCIE User Guide www dinigroup com 60 From the above diagram the global clocks are listed here RCLKO 1 An ICS frequency synthesizer an ICS84020 up to 667Mhz This clock is configured from the MCU using the USB controller or the main txt file SmartMedia CompactFlash This clock is supplied to MGT_CLK pins on FPGA C and can be used as an MGT reference clock for any MGT tile on the left column The Synthesizer can also be configured to use an external clock input from the QSE DP Samtec RocketIO connector 3 Contact Dini Group support for instructions if this clock path 15 required RCLK2 3 An Epson 250Mhz oscillator This clock can be used to supply an MGT reference clock to FPGA C in either the right of left columns ACLK BCLK DCLK These global clocks ate supplied by ICS8442 frequency synthesizers They ate configured from the MCU to output a user specified frequency from 31 to 700Mhz They are each distribuited to FPGAs A B and C The maximum usable frequency by the FPGAs is 500Mhz SCLK1 2 These single ended clocks run at low speed and ate controllable from the USB interface allowing for software
94. ing voltage of the MGT transmitter outputs Set TXDAT DAC to 800mV DN8000K10PCIE User Guide www dinigroup com 86 SFP2 RATE SEL SFP2 LOS Mv qv Virtex 4 FX 1152 OPT XFP1 Connector Ria 191 5 190 Rias 2125 Riss Riss mio SATTE erron Hb 5109 54K 9510 QBIK Sk S AVCCAUXTX 305 RXNPADA 105 ua AVCCAUXRXB 105 Bim mon pese i enge yep woo pese INTERRUPT N 5 aama i XFP1 INTERRUPT N TXPPADA 105 AJ34 XFP1 REFCLK 18 ap DiS 5 XFPI TX DIS 5 TXNPADA 105 AKS 17 gp HE 4 XrPi SCL SDA H li XFP1 SDA VTTXB 105 N 25 REFCLK Nag VTRXA 105 Qi arm 24 REFCLK ABS H2 NE 4 XFP1_MOD_ABS 33 106 MOD NR 13 E i XFP1 MOD NR VITXA105 RX LOS 21 XFPi P DOWN _ LOS ALs4_XEP1_TxDp P DOWN XFP1 P DOWN TXPPADB 105 FPi TxDn VEES 108 _ _ vees 2 _ gav VOCS pe VCCSH XFPT er coace AVCCAUXMGT 105 CAGE vecs os VCC18 XFP1 R110 2 XFP1_RxDp GAGE 2 150R R104
95. ion system on the DN8000K10PCIE allows configuration over PCI USB JTAG or automatic configuration from a SmartMedia CompactFlash catd FPGAA XC18v02 Master Serial JTAG Header amp SelectMap 2 5 Spartan 2 5200 FPGAB o FPGAC JTAG Header SRAM Memory Map Flash Memory Smart Media MicroController Clocks l 1 58442 0 2 5 EPROM The circuit is designed to provide an easy configuration solution that will work out of the box for most users For special configuration requirements the configuration circuitry is programmable The verilog code for the configureation FPGA and the C code for the DN8000K10PCIE User Guide www dinigroup com 43 microcontroller are both provided on the reference CD The C code for the USB Windows GUI controller program are also included on the User CD 2 2 The Spartan 2 FPGA The configuration circuitry of the DN8000K10PCIE is built around a Xilinx Spartan II Fpga The SelectMap interface of the user FPGAs is connected directly to the general purpose IOs of the Spartan 2 allowing the maximum flexibility of configuration The Spartan 2 also shares connectivity with the three user over a 40 bit Main bus allowing fast transfers from a computer t
96. ituations may cause ISE to reject your constraints e If you are having problems with Main Bus make sure that only one FPGA is driving Main Bus at a time Make sure that Enable USB communication is not selected in the USB Controller program default This setting can interfere with MB 32 37 e Make sure that the Unused IOBs option in the ISE settings is set to Float This may be required for correct operation e When using the SD daughtercatd make sure you using the OE signals on the active buffers 4 4 Online Documentation There is a public access site that can be found on the Dini Group web site at http www dinigroup com DN8000K10PCIE User Guide www dinigroup com 105 DN8000K10PCIE User Guide www dinigroup com 106 Ordering Information Part Number DN8000K10PCIE 1 FPGA Options 1 1 FPGA A Select an FPGA part to be supplied in the A position This FPGA is connected to the PCI bus an expansion header and can source global clocks The 12 speed grade is required for full speed operation 1Gbs pair of the interconnect between fpgas NONE LX100 10 11 12 LX160 10 11 12 LX200 10 11 1 2 FPGA B Select an FPGA part to be supplied in the B position This FPGA is connected to an expansion header a memory module socket and can source global clocks 12 speed grade is required for full speed operation 1Gbs pait of the interconnect between FPGAs N
97. lators U51 and U48 Each one drives a MGTCLK on to one side of the The 1CS843020 01 Frequency Synthesizer is a very low phase noise With the default 25Mhz oscillator the frequency synthesizer is capable of producing frequencies in the ranges 71 875 84 375 143 75 168 75 287 5 337 5 and 575 675 Mhz 10 2 MGT Power network The RocketIO strict power supply constraints require the use of heavy power supply filtering The RocketIO s three power rails are each generated by a linear voltage regulator 10 3 The connections The following sections list the individual RocketIO connections 10 4 Samtec Multi Gigabit ribbon cable For board to board high density connections two Samtec ribbon cable connectors J2 and J3 are connected to RocketIO The pinouts on the cable allow two DN8000K10PCIE boards to DN8000K10PCIE User Guide www dinigroup com 82 be connected to each other for a total of 10 bi directional channels operating at 5Gbs per channel per direction The Samtec part number J2 J3 QSE 014 01 F D DP A An appropriate crossover cable for cabling two DN8000K10PCIEs together is the Samtec EQDP 014 09 00 TBR TBL 4 P 49 e 4 38 1 gx DET OTK GATX rri No Le ej Fd k FPI DN8000K10PCIE User Guide www dinigroup com 83 CABLE_COUT CABLE COUT U10 16
98. nd data bytes FPGA_RD_DATA DF11 WR DATA DF12 FPGA ADDR DF13 FPGA ERROR DF14 GPIF DATA DF20 GPIF ERROR DF21 HOLD DONES DF22 STATES DF23 7 4 STATE 3 0 STATE FPGA FREQ H DF24 FREQ SEL DF25 FREQ DF26 MCU STUFFING1 DF27 STUFFING2 DF28 SERIAL 0 DF29 SERIAL CTRL 1 DF30 MB80 1 CTRLO DF36 MB80_1_CTRL1 DF37 80 2 CTRLO DF38 COMMUNICATION DF39 80 2 CTRIA1 DF40 MB64 1 CTRL DF41 MB64 2 CTRL DF42 MB64 3 CTRL DF43 CPLD CS N CTRL DF44 CPLD DATA DF45 CPLD_ADDR DF46 GCLK_MSEL_CTRL DF47 DN8000K10PCIE User Guide www dinigroup com 57 FPGA PHO DVAL DF48 FPGA_PH1_DVAL DF49 FPGA_PH2_DVAL DF50 CF_REG_OFFSET DFE NEW_CONFIG_VERSION DFFD NEW BOARD VERSION DFFE OLD BOARD VERSION DFFF These registers can be written to from the USB interface See USB Software Programmers Guide These registers can also be wtitten to using the MEMORY MAPPED command from the main txt interface SmartMedia or CompactFlash See Configuration Options Media Card 2 5 5 USB The Cypress CY7C68013 has a built in USB 2 0 interface The USB type B connector on the DN8000K10PCIE J12 is connected directly to the USB pins on the Cypress MCU R248 VBUS VBUS VALID VA 3 9K R249 6 34K J12 D MCU USB MCU_USB GND SHIELD 76 GND SHIELD
99. ngs and termination DN8000K10PCIE User Guide www dinigroup com 75 Pins 011 2 IO LIP 031 LC Virtex 4 LX 1513 IO L16N GC CC LC 1 F24 49 E24 HAnj9 A18 HApSO 18 80 D24 PDETECTA Eat O L17P CC LC 1 avon FO 4999 VAN O LN GG L6 1 PAT NTE O L18P VRN LC 1 HApi7 H23 0 118 VRP LC 1 R5 49 9R HAT Ges O L19P LC 1 a I0 L19N LC 1 HAN Mi amp 120 LC 1 F23 O L20N VREF LC 1 IO L21P 1C 1 Hap2 ei IN LC 1 ri O L22P 1C 1 eg ONL E33 L28P LC 1 HAp29 D gig IO L23N LC 1 Hang Fig O L24P LC 1 u O UUAN LC 1 VHDRA 2 5V VHDRA D 3 3V 171 o On both Header A and Header B there is a bank that is dedicated entirely to the Headers For details about Virtex 4 IO banks see the Virtex 4 user guide This bank can be used for standards requiring a threshold volrage reference such as SSTL You can also use this bank for soutce synchronous clocking 8 3 Getting LVDS on the header Since all of the FPGA pins connected to header and header B are pins the Virtex 4 LVDS standard cannot be used as outputs LVDS signaling is still possible On inputs use the LVDS25 standard On outputs use two LVCMOS25 DRIVE 2 SLEW FAST On the
100. nnected in a JTAG chain attached to J14 This header is used when performing firmware updates to update the PROM Spartan Configuration rom CFPGA CCLK 43 40 00 Hean H0 CFPGA_INITn 18 nesers bs p ice 2 0 JTAG 7 0 25 D Spartan Configuration TWAE PROWTEL Ds 220 JTAG PHOM TMS 5 D6 195 0 Interface ST EG JTAG CFPGA TDI 31 cro 19___CEPGA PROGn 30 R356 Wi2 PCI UCLKM 0 53 NC F gt O 4 acko onc m m CFPGA CCLK R 5 A11 mcu CLKS O30 NC rie 822 cc k 1 GCK2 er Sv CIR E 0 54 Nc VCCO Fag CFPGA DONE GcK3 TT 5 12 NC Y Done 3 oY NC veco 0 54 Nc cat 2 2 35 33 3 CFPGA DO 2520 POUT 2 Mo 0 Master O F Nc VOCINT 5 Do 20 1 DIN 2 Mt yz erial 5 4 Nc VCCINT 47 M2 OH Nc VCCINT vig ag NC CFPOR WHITER A20 3 7 O37 Nc GND EER ER ie WRITEn 1 2 Past Tae PROM TET o 4 ne GND FE ci8 PROGRAMN TDI O57 NC 8 1 JTAG TMS E33 NC GND Tp 0 33 XC2S200 187027044 T 433V 33V 433v R365 100R fik 2 267 R2e9 270 4 JTAG PROM TMS 6 8 1 1 1 R268 5 1K CFPGA DONE 1 2 012 87832 1420
101. not be shared between the two columns Each column has two clock distribution trees and two clock inputs Each tree can be driven by a clock input by a clock from a global clock input not recommended or by a recovered clock Finally each tile has a multiplexer than can select from one of the two clock trees to clock that entire tile The diagram above shows the two RocketIO columns and the connectivity of each Once a clock is routed to an MGT tile that clock can be multiplied and divided by the MGT tile Most users will want to use the frequency synthesizer for generating RocketIO reference clocks The ICS843020 01 synthesizer is very low jitter and should suitable for operation up to 6Gbs RocketIO operation The frequency of the synthesizer can be adjusted through the main txt file on the SmartMedia catd or through the USB GUI program DN8000K10PCIE User Guide www dinigroup com 80 48 8V 43 8V CABLE COUTOn R443 R444 R445 R446 Be ei 100R 100R 100R 100R 010 15 u31 T C671 13pE LN rouro L4 1 C1046 1 2 I 15 0 01uF 3 4 en M34 MGTCLK P 102 5 6 25 11 R447 R448 R449 R450 N34 7 8 XTAL2 2 88 7R 6 5
102. o 3A of the required 0 9V termination power rail along with a stable 0 9V reference voltage supply DN8000K10PCIE User Guide www dinigroup com 69 5 2 2 RocketlO power MGT12 top U10 16 FB10 R34 T33 VCC MGT12 1 103 MGT12 1 103 FB17 VCC _MGT12_top T34 RXPPADA 103 AVCCAUXRXA 103 AE33 VCC 2 2 103 MGT12 2 103 FB13 8 gt RXNPADA 103 AVCCAUXRXB 103 yas MGTT2 3 103 MGTT2 3 103 T AVCCAUXTX 103 8 ae C26 L cao TXPPADA 103 0 22uF 24 TXNPADA 103 er Ar VCC MGTI5 FBIS VTRXB 103 anm VCC_MGT15_1_103 VCC_MGT15_1 u m VITXA 103 Hass STIS 3 10 T I c28 103184 MGTi5 4 103 MGTI5 4 103 8 C25 FB12 022uF VTRXA 103 c27 FB14 0 22uF JA34 103 C24 Fen p 022uF BASS TXNPADB 103 L 0221 1 VCC MGT25 094 nppaDs 103 ES 1 AD34 RXNPADB 103 AVCCAUXMGT_103 2O33 VCC MGT25_1_103 MGT25 1 103 16 VCC MGT25 2 888888 0 22uF 555544 ga 888888 222222 555556 Vinex 4 FX T1852 SISSE 852422 1 21V 25 VCC MGT12 top 18V Us t 5 veowen vout Sag HH I 1OuF SENSE 1 C301 C300 C49 c52 c51 C53 C50 10V C312 ADJ 2 gt 150uF 150uF 2 2uF 2 2uF 2 2uF 2 2uF 2 2uF 2 2uF 20 10uF 3V V C54 TANT 10V T1580CQ R21 20 20
103. o the RS232 headers you can use the provided USB application program or you can change the setting on a terminal connected to the Microcontroller unit s RS232 port P2 DN8000K10PCIE User Guide www dinigroup com 46 Since RS232 uses a 12V signal levels the RS232 signals from the Spartanll are first buffered through a voltage translation buffer shown below RS232 ppc u2 P1 7 21 RS232 TXD3 hi 2 RS282 TX S 1 MCU TX SH T2IN 449 t 2 9 19 5 x RS232 RXD3 RS282 RX S 434 RioUT run H TEDSECHXDY x2 10x MCU RX R2OUT R2IN 10 16 GND x Lour un 1 0 15 GND RS232 MCU x swour swn HE o 24 c2 BHDN EE 2 14 vec 23 3 pax 4161 14 7 41 c2 Ho wt Bx 2 v 2 6 aL 22 anD v 8 6 AX3388E TSOP24 Figure 23 RS232 buffer On the back side of the DN8000K10PCIE there are two duplicate RS232 ports P7 and P8 that can be used if an installed daughter catd is covering the headers on the front These duplicate headers are not installed by default but can be installed on request They are compatible with a surface mount 5x2 0 1 header 2 2 5 IIC There is a single IIC bus on the DN8000K10PCIE connecting all IIC enabled chips on the board On this bus ate three MAX1617A temperature sensing chi
104. o the user design over USB The Spartan 2 FPGA also provides IO expansion for the Cypress Microcontroller The Spartan II FPGA comes preloaded with a core that provides a way to program the Virtex 4 FPGAs over USB and a flash card SmartMedia or CompactFlash The Spartan FPGA 15 connected to the Cypress microcontroller s address and data busses and the control registers within the Spartan II FPGA that control FPGA configuration are memory mapped into the MCU s address space SRAM i MB 40 8 0 1 SYS SCERT73 RESETFPGRTT SELECT MEP 734 gt Switches WI Spartan 2 RS232 7 RS232 RE Cable RS232 Buttons JTAG Header Figure 20 Spartan II IO Connections DN8000K10PCIE User Guide www dinigroup com 44 2 2 4 Spartan Configuration The Spartan 2 FPGA is configured from a Xilinx serial prom The Spartan s configuration mode is hard wired into Master Serial mode After power up the Spartan automatically clocks an external PROM U41 which programs the FPGA over the serial configuration data pin DIN A green LED DS24 lights when the DONE pin is high This signal is driven by the Spartan 2 FPGA when it is configured and running Both the Spartan and the serial prom are co
105. o their default values ACLK 200Mhz BCLK 108 8Mhz DCLK 128Mhz R1CLK not available on DN8000K10PCIE R2CLK DEFAULT The MCU detects which FPGAs are present The MCU detects if a SmartMedia card is present The MCU tries to access the SmartMedia card If the MCU is not successful in reading the files on the SmartMedia card be sure you have not formatted the card in Windows Windows uses a non standard format for media cards and will make the card unreadable You can download a format utility from dinigroup com to repair your incorrectly formatted SM card The MCU reads the contents of the file MAIN TXT and executes each instruction line Here the MCU is setting the clocks according to instructions in MAIN TXT The MCU is configuring FPGA A according to instructions in MAIN TXT The sanity check option reads the design bit file headers and vetifies that the design is compiled for the same type of FPGA that the MCU detects on your DN8000K10PCIE If the design and FPGA do not match the MCU will reject the file and flash the Error LED You may need to disable to sanity check option See Chapter X section X if you want to encrypt or compress your configuration Sanity check passed files Bere DONE WITH CONFIGURATION OF FPGA A CONEIGURING FPGA The MCU is configuring FPGA B according to instructions in MAIN ee Performing Sanity Check on Bit File
106. old 80 New Threshold 85 Threshold Updated 85 Degrees C Figure 7 Temperature Threshold Menu The Virtex 4 FPGA can operate as hot as 120C degtees before damaging the part although timing specifications are not guaranteed The MCU allows you to change the reset threshold although we recommend improving your heat dissipation to maintain a low junction temperature DN8000K10PCIE User Guide www dinigroup com 20 3 34 Multiplex Serial port The DN8000K10PCIE has one serial port P1 for user use This single port is multiplexed so that any FPGA can access it through its RX and TX signals You can use the RS232 MCU interface to change the FPGA to which P1 is connected ENTER SELECTION 7 PORT 1 D PORT 2 A PORT 3 A PORT 4 A Enter Port to change 1 4 q to quit 1 Enter FPGA to set port to A I B Do you want to change more RS232 Ports y or n n Figure 8 RS232 Port Menu The DN8000K10PCIE only has one serial port Port 1 Changing ports 2 4 will have no effect 3 4 Check LED status lights The DN8000K10PCIE has many status LEDs to help the user confirm the status of the configuration process DN8000K10PCIE User Guide www dinigroup com 21 Configuration Control status status Spartan FPGA Configuration Activity 7 1000900096 TII MH 7 7 0 111111111 7 aan uns iif i FPoa a DN800
107. on 5 of the MGT menu allows you to invert the polarity of one of the SFP channels For the test to pass this must be done since SFP2 is received with inverted polarity The MGT tiles are connected as follows MGT A MGT COLO TILEO QSE 1 QSE 1 COLO TILE QSE 1 QSE 1 COLO TILE2 SFP 1 REFCLK1 XFP1 COLO TILE3 LOOPBACK SMA 22 COLI TILEO QSE 0 QSE 0 COLI TILE SMA J31 SMA 25 COLI TILE2 NC SMA 17 COLI TILE3 XFP2 SFP 2 REFCLK2 250MHz EPSON DN8000K10PCIE User Guide www dinigroup com 100 INTRODUCTION TO THE SOFTWARE TOOLS REFCLK 1 ICS 84020 Synthesizer DN8000K10PCIE User Guide www dinigroup com 101 INTRODUCTION TO THE SOFTWARE TOOLS ACkCckCckckck ck ckckck ck ckckck ck kckck FPGA A MAIN MENU KKKKKKKKKKKKKKKKKKK a Run Full Test Suite b Test Registers c Test SRAM d Test DDR e Test Interconnect f Write Memory Location g Read Memory Location h Display Memory in 8 DWORDS per Line Format i Fill Memory with specified DWORD pattern j Toggle Mem Owner INTERNAL User k Interconnect Test Menu q Quit 3 Memory Mapped Data flow All memory mapped transactions in the reference design occur over the MB bus This 40 signal bus connects to all Virtex 4 FPGAs and to the Spartan II configuration FPGA The Configuration circuit Spartan 2 is the master of the bus All access to the MB bus reads an
108. oring software to verify that the design is loaded into the FPGAs 1 Insert the CDROM that came with your DN8000K10PCIE into the CDROM drive of your computer 2 Connect the USB cable to yout DN8000K10PCIE and a Windows XP PC When the DN8000K10PCIE powers on Windows will launch the new hardware wizard Windows XP Found New Hardware Wizard Welcome to the Found New I Hardware Wizard This wizard helps you install software for DiniGroup DN6000K10 FLASH Boot If your hardware came with an installation CD SEP or floppy disk insert it now What do you want the wizard to do Install the software automatically Recommended Install from a list or specific location Advanced Click Next to continue Back Cancel DN8000K10PCIE User Guide www dinigroup com 26 Select Install from a list or specific location Advanced Select Don t search I will choose the driver to install Select Have Disk Browse to the user CD gt Controller Programs gt drivers gt win_wdm gt dndevusb inf Select Next gt Select Finish 3 After Windows installs the driver you will be able to see the following device in the USB section of Windows device mananger DiniGroup DN8000K 10PCIE FLASH boot 4 Run the USB controller application found on the product CD in Controller SoftwareNUSBControllerNUSBController exe DiNi Products USB Controller 10 x File Edit FPGA Configuration FPGA Referenc
109. owing options 1 2 3 4 5 Configure via USB individually After selecting this option a window will pop and ask which FPGA you want to configure and then what bitfile you want to configure the selected FPGA with The status of the FPGA configuration will detailed in the log window and the DN8000K10PCIE will be updated after the bitfile has been transferred Configure via USB using file This option allows the user to configure more than one FPGA over USB at a time To use this option you must create a setup file that contains information on which FPGA s should be configured and what bitfiles should be used for each FPGA The file should be in the following format the first character of each line represents which FPGA you want configured a f or A F this letter should be followed by a colon and then the path to the bitfile to use for this FPGA The path to the bitfile is realative to the directory where this setup file is or you can use the full path Below is an example of an accepted setup file A fpga_a bit B fpga_b bit C fpga_c bit Configure via SmartMedia Card This option allows the user to use a SmartMedia card to configure the FPGAs Please section Creating Configuration File main txt for information on what files should be on the SmartMedia card to use this option Clear All FPGAs This option will deconfigure all FPGAs Reset This options sends an active low reset active for a
110. ped on the DN6000K10PCIE Please follow this quick start guide to become familiar with the board before starting your ASIC emulation project 1 Provided Materials Examine the contents of your DN8000K10PCIE kit It should contain DN8000K10PCIE board e Two Smart Media cards or one CompactFlash card e USB SmartMedia card reader e RS232 IDC header cable to female DB9 e USB cable e CDROM containing Virtex 4 Reference Design User manual PDF Board Schematic PDF USB program usbcontroller exe Source code for USB program and DN8000K10PCIE firmware 2 ESD Warning The DN8000K10PCIE is sensitive to static electricity so treat the PCB accordingly The target markets for this product are engineers that are familiar with FPGAs and circuit boards However if needed the following web page has an excellent tutorial on the Fundamentals of ESD for those of you who ate new to ESD sensitive products http www esda otg basics part1 cfm There two large grounded metal rails on the DN8000K10PCIE The DN8000K10PCIE has been factory tested and pre programmed to ensure correct operation You do not need to alter any jumpers or program anything to see the board work A reference design is included on the provided CD and SmartMedia card The 200 pin connectors are not 5V tolerant According to the Virtex 4 datasheets the maximum applied voltage to these signals is VCCO 0 5V 3 0V while powered on These connections are no
111. pprox 20ns to all FPGAs on the signal called RESET_FPGASn which is connected to the following I O pins FPGA A AK19 FPGA B K21 FPGA C AG18 DN8000K10PCIE User Guide www dinigroup com 33 1 1 4 Settings Info Menu The Settings Info Menu has the following options 1 2 Set FPGA RocketIO CLK Frequency When the DN8000K10PCIE is first powered up the CLK inputs to the FPGAs are inactive The CLK Inputs connected to the following FPGA Differential CLK inputs on all FPGAs F21 G21 and AT21 AU21 This menu option allows the user to specify what frequency the CLKs should be set at for each FPGA The supported frequency range is 31 25MHz 700MHz After selecting this option a pop up window will ask which FPGA s RocketlO Frequency you want to set or you can choose to set all to the same frequency and then what frequency you want Check the log window to verify what frequency the CLKs were actually set at Set Global clock frequencies The clocks on the DN8000K10PCIE are automatically adjusted to the user s desired frequency by reading the setup file on the SmartMedia card If you wish to change the frequency after power on or do not want to use a SmartMedia card you can set the frequency in the USB program ACLK ACIK is generated from a 25MHz crystal Available frequencies are 31 25 34 375 37 5 40 625 43 75 46 875 50 53 125 56 25 59 375 62 5 65 625 68 75 71 875
112. ps U3 U4 U24 two DDR2 SODIMM sockets and a serial eprom The temperature sensors on the IIC bus are polled about once per second by the MCU to read the temperature of each FPGA 2 3 Configuration Options The DN8000K10PCIE allows FPGA configuration from any of four methods When a Virtex 4 FPGA is configured the DONE pin on the FPGA is pulled high The DN8000K10PCIE has a green LED attached to the DONE signal of each to indicate the state of the DONE pin on the three Virtex 4 FPGAs and on the Spartanll configuration FPGA 3 3V R169 120R FPGAA_DONE 2 5V DS18 FPGA_DONE_A 11 Figure 24 DONE LEDs DN8000K10PCIE User Guide www dinigroup com 47 2 3 4 Jtag Jtag is the only configuration method on the DN8000K10PCIE that does not use the Virtex 4 SelectMap configuration interface When programming the user FPGAs over a JTAG cable plugged into J13 the DN8000K10PCIE configuration circuitry is not used A JT AG connection is required to use some Xilinx configuration tools like ChipScope and readback from Impact Configuration over JTAG is slower than SelectMap You can still use the SmartMedia or USB interfaces to control clock settings if you plan to configure through JTAG To configure using JTAG we recommend using Xilinx Parallel cable IV or Xilinx platform USB cable The Xilinx program You should set the configuration speed of your JTAG cable to 4Mhz or below FPGA JTAG Cable IV 42 5V 2 5V Er
113. r the MCU memory interface for the purposes of reading instructions from SmartMedia cards For instructions on creating a Smart Media card for configuring the DN8000K10PCIE see the section Configuration Options Smart Media 2 2 3 MCU communication The MCU communicates to the Spartan 2 FPGA over it s external memory interface pins 00 7 and A0 15 The Spartan 2 is assigned the address range OxDFOO to OxDFFF in the Microcontrollers memory space The 480Mbs data rate of USB 2 0 is too fast for the microcontroller to control so the MCU s hardware passes USB bulk transfer data to the MCU GPIF interface These signals SM 0 7 and GPIF_CTL GPIF RDY connect to the Spartan FPGA The SM 0 7 signals also connect to the SmartMedia card socket although the MCU does not communicate with the SmartMedia interface directly The MCU IFCLK signal provides a clock for this interface The clock is driven from the Spartan 2 FPGA 2 2 44 RS232 The DN8000K10PCIE has two RS232 headers One P2 is used by the microcontoller unit to provide configuration feedback and control The other P1 is connected to the Spartan 2 FPGA The Spartan 2 FPGA has one RX and one TX signal connected to each Virtex 4 FPGA The Spartan FPGA will multiplex the RX and TX signals to the Virtex FPGAs to the RS232 header P1 The Spartan 2 internally multiplexes the signals on the user RS232 header P1 to one of these three sets of signals To change the Virtex 4 FPGA that has access t
114. red to configure a Virtex 4 are created and embedded in the bit files created by the Xilinx Bitgen program The DN8000K10PCIE does not interact with the SelectMap interface other than to reset the FPGA using the PROGn INTn PROGn tesetr sequence described in UG071 and to copy a bit stream file unaltered to the FPGA over the data pins D 7 0 Select map commands can be issued to the Virtex 4 FPGA from the host using the same interface used to configure and FPGA After a Virtex 4 FPGA is configured it asserts the signal DONE On the DN8000K10PCIE these signals have an LED attached to each DONE signal placed near the upper corner of each FPGA FPGA A s LED is DS18 B is DS14 C is DS16 DS15 on 8 lane 3 3 o R169 120R RFPGAA DONE DS18 JQFPGAA_DONE 3 FPGA_DONE_A Pgii If your Virtex 4 FPGA design is failing to produce the intended or any results you should check the DONE light above the FPGA to make sure it is configured correctly The design files created by Xilinx bitgen software contain a CRC check so if the Virtex 4 FPGA detects a CRC failure there was a trasmission error during configuration and the DONE light will not glow The DN8000K10PCIE microcontroller also checks the design files you send to make sure they are compiled for the FPGAs that are installed on your board If they are not then the microcontroller unit halts the configuration process As a result when t
115. resets the Virtex 4 FPGAs causing them to lose their configuration data and deactivate The Spartan also causes a reset on the Microcontroller unit which will cause the microcontroller to reload configuration instructions from the Smart Media card USB contact will be lost with the USB host and the DN8000K10PCIE will have to re enumerate There is a second button S2 called Soft Reset When this button is pressed the signal RESET FPGAs is asserted This signal is sent to the Virtex 4 FPGAs on a user IO pin and could be used by the user design as a reset signal This signal is also asserted to all FPGAs after any FPGA becomes configured RESET FPGAs is an asynchronous signal 12V 18V 25V 50V 43 3V 33V 480V 50 Reset Circuit R359 R362 124R oR R373 R367 R358 1K 845R OR R364 R371 1K 2 mers 88 7R u23 a 8 t 324 RST H svs RsTh VREF 9 vba Ez 28 0K R360 R368 9 7 28 0K R361 5 1108 T wa T 100R Sm R372 R363 5 3 a C1029 71 5K 100R 6 om R357 TOZSOOMSOPIO 2 7nF GND 71 5K TOZ80UMSOPi0 C1018 E 2 7nF 3 3 uw V2 2 5V 10K ne V3 l 9V vl 3 3V V4 ADJ V2 2 5V x 0 5 V V3 1 8V V4 ADJ 0 5 V HARD RESET The above circuit shows how two LTC2900 voltage monitors are dai
116. rol the basic configuration options of the DN8000K10PCIE including configuration clock frequencies and the Virtex 4 FPGA RS232 ports 2 5 2 Clocks The Cypress CY7C68013 is also responsible for configuring the global clocks and RocketlO clock of the DN8000K10PCIE The Cypress CY7C68013 MCU reads the file main txt from the SmartMedia card in the socket J24 and follows the users clock configuration commands U20 C852 18pF ACRYSp Tara H4 FOUTO pe 5 25 xrAL2 court Hi x T 25MHz 28 FOUTI Xx x 5H 29 9 ACLKTEST 11 C934 18pF ACRYSn 30 M1 TEST 1 1 x gt re 2 34 Me x 7 4 ng E ACLK 54 generator ni _ 03 XTAL SEL x24 vco SEL SCLK ACLK SCLK 18 scuk 2 n ALLCLK SDATA 19 ALLCLK_SDATA eee 19 SDATA ALLCLK SLOAD 20 SLOAD PLOAD R281 ALLCLK SRST 1K ALLCLK SRST 17 nee 10 TH GND vec bag GND vec CSBAA2 LGFP32 Figure 30 8442 Clock synthesizer The 3 ICS8442 clock synthesizers on the DN8000K10PCIE used for generating the global clocks ACLK BCLK and DCLK share a serial configuration bus connected to the MCU to DN8000K10PCIE User Guide www dinigroup com 54 program them The ICS8442 frequency synthesizers are capable of multiplying and dividing the reference frequencies provided by their re
117. rse F DiniProd DN5000121 SourcesConf igFPGANIMPLEHENT pros acs done Device 1 selected Figure 18 Impact Window To program the prom Right click on the prom and select Program from the popup menu In the options dialog that follows the options Erase before programming should be selected and Verify should be deselected Press OK The programming process takes about 35 seconds over the parallel port Power cycle the DN8000K10PCIE The new firmware is now loaded You can close impact and disconnect the Parallel IV cable DN8000K10PCIE User Guide www dinigroup com 39 Hardware 1 Overview The DN8000K10PCIE was designed to maximize the number of useful gates in your emulation project running at speed by providing the densest interconnect possible To achieve this goal the DN8000K10PCIE is equipped with the highest capacity FPGAs available today the Xilinx Virtex 4 LX200 The FPGAs on the DN8000K10PCIE are in the largest 1513 ball package to give the user extremely high IO count for high bandwidth and low latency interconnect between FPGAs Three hundred eighty nine differential links between FPGAs A and B allow for as much as 189 Gb s communication between the two FPGAs In order to support enough bandwidth to deliver real time data to your design at speed the DN8000K10PCIE is equipped with an optional Xilinx Virtex 4 FX100 with RocketIO Multi Gigabit Tranceivers Serial connections over Fibre Coa
118. s aii CAGE amp CAGE CAGE 5 CAGE AVCCAUXMGT_105 CAGE CAGE CAGE RXPPADB 105 TAPS CAGE E CAGE 4301 RXNPADB 106 o CAGE MGTCLK P 105 CAGE CAGE RsFP4 FAULT MGTCLK N 105 889555589 1887073 u R109 perpe er ns RTERM 105 555555535 150R matvREF 05 999222222 10 ose AAT PAPAS SA mA t REDLED OPT RSFP LOS Zee EER ae JoSFP1 FAULT RED WP 056 10 ls RED LED OPT 8 Y 2 SFP1_TxFAULT 2 Gp Los 8 2 LOS 1 92 5 a DN8000K10PCIE User Guide www dinigroup com 85 VCCT SFP2 SFP2 VCCR SFP2 7 NTS NTO P13 ANS N14 SFP2 Connector R221 Vitex 4 1182 OPT Jo R151 Ride 1K C1056 TOF 1K C667 0 01uF 20 O 0tuF i 19 VEET VEET SFP2 TXFAULT AVCCAUXRXA 109 Ape SFP2_RxDp 1 To TxFAULT Eu SFP2_TXFAULT AVCCAUXRXB 109 RXPPADA 109 HABS 110 TXDISABLE 08 SFP2 TXDI AVCCAUXTX 109 RXNPADA 109 Ds Voor i1 VEET MOD DEF 2 Bea SFP2 C617 0010 VCCRCSEPZ 18 MOD DEF 1 SFP2 MOD DEFO SFP2_MOD DEF1 AP9 2_ 14 MOD DEF 0 FPZ HATE SEL TXPPADA 109 HABS Her en RATE SELECT T SFPEIUS TXNPADA 109 LOS 4 VEER m 1K 2 VTRXB 109 TXPPADB 109 H
119. sy chained together to monitor 5 different voltages DN8000K10PCIE User Guide www dinigroup com 65 Each is also connected to a temperature monitor The Virtex 4 can easily ovetheat if a heatsink and fan not used The recommended operating temperature for the Virtex 4 is 85 degrees C The absolute maximum temperature for operation is 125 degrees C If at any time the junction temperature of the Virtex 4 exceeds 85 degrees the Microcontroller will reset the FPGAs causing them to lose their configuration data An overheating FPGA could be the result of a misconfiguration a clock that is set incorrectly or an inadequate heatsink unit The heatsink and fan assembly that comes with the DN8000K10PCIE is approptiate for dissipating the amount of heat energy available through a PCI slot without the auxiliary power connector 25W total for the card If you are operating the DN8000K10PCIE at very high speeds in stand alone mode and you are causing heat overload resets you may need to install a larger heatsink or increase the system airflow U11 1 Virtex 4 LX 1513 CCLK HSWAPEN PROGRAM B INIT CS B DONE PWRDWN B RDWR_B DOUT_BUSY MO M1 M2 VBATT VCCO 0 E dd VCCO 0 VCCO 0 R165 1K TEMPA STBY 15 5 5 FPGA DXP A sol C gt e S 127 SMBCLK C280 SDA gt SMBDATA DXP 1100pF mn IRQn 11 DAN Ran e ALERT FPGA DXN A TEMPA SAI 10 6 ADDO NC R168 A
120. t Lane 4 BCLKIN Koje b 8 or 10 bit Lane 5 P CLKFB 250Mhz CLKOUT_PHASE_SHIFT NONE TX Channel A Lene T Lodi Channel B en hannel B Resync 3 m a Channel D UFG DCM P CLKIN CLKFB CLKOUT_PHASE_SHIFT FIXED PHASE_SHIFT 90 PCIE2_PCLK SSTL2 DCI 250Mhz The interface has been validated in 4 lane operation using the following clocking method The PCLK signal in sent to a BUFG whose output is fed to DCM The DCM settings are as follows CLKDV DIVIDE 2 0 CLKOUT PHASE SHIFT FIXED PHASE_SHIFT 125 The CLKDV output of this DCM is sent through another BUFG The output of this is used to clock IDDR and ODDR registers on the input and output signals to the GL9714 DN8000K10PCIE User Guide www dinigroup com 91 250Mhz PCIE PCLK GL9417 Lane 0 8bit 250Mhz TX CLKOUT DIVIDE 2 0 CLKOUT PHASE 5 FIXED PHASE_SHIFT 125 l bit amp 125Mhz Lane 3 100Mhz PCI Express Core IEEE FPGA A This method is convienient if your PCI express core has a 125Mhz 16 bit interface 11 3 The Phillips PX1011A This section applies to the 1 Lane DN8000K10PCIE only The Phillips PX1011A is 1x PCI Express PHY chip providing an 8 bit 250Mhz interface to FPGA A Since this chip does nothing more than serializing and 8B 10B encoding the PCI express protocol will have to be implemented in the logic of FPGA A The PC
121. t buffered and the Virtex 4 part is sensitive to ESD Take care when handling the board to avoid touching the daughtercard connectors 3 Power On Instructions The image below represents your DN8000K10PCIE You will need to know the location of the following parts referenced in this chapter 7 MCU configuration RS232 P2 Media Card Socket DDR2 Sodimm DDR2 Sodimm B Figure 3 DN8000K10PCIE configuration controls To begin working with the DN8000K10PCIE follow the steps below DN8000K10PCIE User Guide www dinigroup com 13 3 1 Memory and heatsinks There should be an active heatsink installed on each FPGA on the DN8000K10PCIE and a fan over the power supply units Virtex 4 FPGAs are capable of dissipating 15W or more so you should always operate them with heatsinks installed The DN8000K10PCIE comes packaged without memory installed If you want the Dini Group reference design to test the DDR2 interface you can install them now in the 1 8 DDR2 DIMM sockets The reference design does not operate with the DNSODM products RLDRAM SRAM QDR RAM in these slots Figure 4 FPGA Names The socket DIMMB is connected to FPGA B The socket can accept any capacity DDR2 Sodimm module Note that DDR1 modules will not work in these slots since they are supplied with 1 8V power and DDR1 requires 2 5V power and a completely different pin out 3 2 Prepare configration files The DN8000K10PCIE reads FP
122. ured and operational This light should be on if you loaded the reference design from the SmartMedia card Check the FPGA B status LED DS14 directly above FPGA B This light should be lit green if your DN8000K10PCIE was installed with the FPGA B option and the reference design is loaded Check the FPGA C status LED DS16 to the upper left of FPGA C This green LED will light if you have the FPGA C option and the FPGA is configured Check the FPGA A User LEDs on the bottom side of the DN8000K10PCIE If you have successfully loaded the Dini Group s DN8000K10PCIE reference design these should flash all 8 green LEDs Check the FPGA C User LEDs on the bottom side of the DN8000K10PCIE If you have ordered the FPGA C option and the reference design is loaded these will flash all 16 LEDs If you suspect one or more FPGAs did not configure properly check the configuration circuitry s status lights These are four right angle mounted LEDs viewable out the side of the PC case If there has been an error the four LEDs will blink If there has been no error the two lower LEDs will be ON and the upper two OFF If there was an error the easiest way to determine the cause of the error is to connect a terminal to the RS232 port P2 and try to configure again Configuration feedback will be presented over this port You should also notice the Fans mounted above the 3 Virtex 4 FPGAs and the Fan mounted above the power supplies spinning
123. uring the hours of 8 00am to 5 00pm Pacific Time Figure 2 Support Resources 3 Conventions This document uses the following conventions An example illustrates each convention 3 1 Typographical The following typographical conventions ate used in this document Convention Meaning or Use Example Courier font Messages prompts and Speed grade program files that the system 100 displays Courier bold Literal commands that you ngdbuild enter in a syntactical statement design name Commands that you select File 2Open from a menu Garamond bold Keyboatd shortcuts Ctrl C DN8000K10PCIE User Guide www dinigroup com 8 Convention Meaning or Use Example font Variables in a syntax statement for which you must supply values nedbuild design_name References to other manuals See the Development System Reference Guide for more information Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected An optional entry or parameter However in bus specifications such as bus 7 0 they are required ngdbuild opton_name design name Braces A list of items from which you must choose one more lowpwr on off Vertical bar Separates items in a list of choices lowpwr on off Vertical ellipsis Repetitive material that has been omitted IOB 1 Name
124. w dinigroup com 50 MAIN BUS 0x lt WORDADDR gt O0x lt WORDDATA gt Writes data in lt WORDDATA gt to the address on the main bus interface at lt WORDADDR gt This command only makes sense in the context of the Dini Group reference design unless your design implements a compatible controller on the main bus pins The main bus interface is described in the reference design chapter MEMORY MAPPED 0x lt SHORTADDR gt Ox lt BYTE gt Writes to an address in the MCU XDATA memory space See the USB Software section for a list of valid addresses RS232 lt port gt lt fpga gt The RS232 port P1 will be controlled by the FPGA lt fpga gt if lt port gt is 1 CLOCK FREQUENCY lt clockname gt N lt number gt M lt number gt The MCU will adjust the clock synthesizer producing clock lt clockname gt to multiply it s reference frequency by lt M gt and divide it by lt N gt Note that the clock synthesizers have a limited bandwidth and for clocks A B and D the reference frequency M must fall in the range 250Mhz 700Mhz For clock 2 RocketlO reference M must fall between 540 and 680Mhz See datasheets for parts ICS8442AY and ICS843020 01 The reference frequencies are ACLK 25Mhz BCLK 14 18Mhz DCLK 16Mhz 2CLK 25Mhz An example main txt file VERBOSE LEVEL 0 This will prevent the MCU output over RS232 to speed up configuration FPGA A a bit this will load the configuration a
125. x ribbon cable and Coax SMA cables allow for a total aggregate 150 Gb s off boatd communication To allow you to connect the FPGA to the resources that will be on your end product the DN8000K10PCIE also has highspeed expansion capabilities Below is a block diagram of the DN8000K10PCIE DN8000K10PCIE User Guide www dinigroup com 41 One Lane Configuration d p Expansion Diner 1 50 50 ET Cable Configuration FGPA MB 8 Spartan II 152 Rocket VO Rocket VO Rocket ys al C SUAM Xilinx Xilinx FPGA A m FPGA FPGA LX100 160 200 LX100 160 200 FX60 100 FF1513 1513 1152 uP Contig Virtex 4 Virtex 4 Virtex 4 or single or single P4 Control ended ended CY7C68013 BE ET D x m 5 5 3 differential x lt pun dock config 1 2 8 i 2 or single ended Cable 12 eg Philips DDR2 SODIMM DDR2 SODIMM PX1011A PCI Express Phy up to 4GB addressing up to 4GB addressing 2 1 lane LS Qm 18 Heol A Mi ER 1 4 PCI Express 4 Eight Lane Configuration PROM config JTAG Samtec Cable Configuration FGPA Spartan Il 1 FP XFP mE MEE nsion Connector Expansion Connector SFP XFP Module 1 38 MB 38 Rocket VO Xilinx Xilinx I

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