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PCI8282 User`s Manual

1. Dimension of DASP 52282 and Accessories 51 DASP 52282 Card User s Manual e TB 88320 52 pi ol e DB 87822 O of 1 DO FF FT ma 0 i ale Ie le isla bl 4 A C_ O jo go go KO 16 1910 O jajaja ojo jo aja DO eann 52 Dimension of DASP 52282 and Accessories DASP 52282 Card User s Manual e DB 87825 palcalca a a LL FEr rr tn Dimension of DASP 52282 and Accessories 53
2. 1LSB 0 499756 00 000 0 5 0 000244V ed I E OxFFF 4095 0x800 2048 Ox0 0 1LSB 0 0499756 00 000 0 0000244V 0 05V OxFFF 4095 Ox800 2048 Ox0 0 1LSB 40 005 0 00499756 00 000 0 005 0 00000244V x OxFFF 4095 Ox800 2048 Ox0 0 1LSB Input Range Data Code and Resolution of DASP 52282H DASP 52282HL Bipolar Input Input Display 9 99756 00 7 0 00244V 0xFFF 4095 0x0 0 1LSB 0 999756 00 000 0 000244V OxFFF 4095 0x0 0 1LSB 0 09997 00 0 0000244V apay 400999756 200 000 0 0000 OxFFF 4095 0x0 0 1LSB 0 00999756 00 0 0000244V OxFFF 4095 0x0 0 1LSB Input Range Data Code and Resolution of DASP 52282H DASP 52282HL Uni Polar Input Theorem of Operation 35 DASP 52282 Card User s Manual This page does not contain any information DASP 52282 Card User s Manual Chapter 4 Register Structure and Format 4 1 Overview The DASP 52282 board occupies 16 consecutive I O address The address of each register is defined as the board s base address plus an offset The I O registers and their corresponding functions are listed in the followings Read Function Write Function BASE 0x00 Digital Input Low Byte Digital Output Low Byte BASE 0x01 Digital Input High Byte Digital Output High Byte BASE 0x02 Status Register Low Byte Command Register Low Byte BASE 0x03 Status Register High Byte Command Register High Byte BASE 0x04 A D Data R
3. 4 2 12 Clear Flag Register sss esse sssssees sse essen 45 4 2 13 Enable DAC1 and DAC2 Output Register 45 4 2 14 A D ADC Software Polling Control Register 46 4 2 15 Enable ADC Register 46 4 2 16 Disable ADC Register 46 Chapter S Calibration urca 47 5 1 Calibration VR Description 47 5 2 DA Calibration 48 5 3 A D Calibration Steps 48 Appendix A Analog Input Gain Mode CONE ATOR caccia 49 Appendix B Dimension of DASP 52282 and ACOCSSOTIGS iii 51 vi This page does not contain any information DASP 52282 Card User s Manual Chapter 1 Introduction remi imines I gt The DASP 52282 is a high performance PCI bus multi function card It supports a 330KHz sampling rate 16 single ended or 8 differential Al 16DI and 16 DO The DASP 52282 also features an all new free running mechanism to reduce the S W development efforts and provides high low gain options for user s applications Advanced S W Mechanism Free running Free running is a brand new data retrieving mechanism to mainly save software SW RD 30 50 of the time and effort in developing application programs It helps software RD by using several rows of simple programs to read data instead of countless numbers in the past Board identification Serial Number on EEPROM The DASP stores the
4. Hiv 7 DA Range 10v 10v 7 Selected ID 0 Card Type DASP52282 Signal Type Differential Dil Version 20040605 mame pur Taaa Amplitude Md B poo Channel gt CHO CHI ore DAQ Test PreTrigger Mid Trigger Auto Scan Interrupt Polling Pacer Post Trigger ICH Value CH Value 2000000 CH8 000000 00 0000 CH9 000000 00 0000 CH10 00 0000 1000000 CHi1 00 0000 00 0000 CH12 00 0000 00 0000 CH13 00 0060 a 00 0006 CH14 00 0000 2000000 CH15 00 0000 Star Polling Stop Palio DIO Test DI 0x0000 DO 00000 ERRE EFEEEEEE Bagaman Select Test Target DASP 52282 Hardware Installation Perform AD DA and DIO test of DASP 52282 as 21 DASP 52282 Card User s Manual AD Scale Fw E DA Range Fo MOV x Selected ID 0 Card Type DASP52282 Signal Type Differential Dil version 20040605 Enable Release Amplitude se vil Jo Channel 3 DAG Test PreTrigger Mid Trigger Auto Scan Interrupt Poling Pacer PostTrigger ICH Value CH Value CHO 4 4238 CHS 00 0000 CH1 4 5215 CH9 00 0000 CH2 4 4580 CH10 00 0000 CH3 4 6045 CH11 300 0000 CH 4 4 3701 CH12 00 0000 CH 5 4 4824 CH13 00 0050 CH6 4 4287 CH14 00 0000 CHT 4 6191 CH15 00 0000 Start Polling Stop Polling DIO Test DI om DO Ott ASYA MA LL ILITILIET III II Check Device Inf
5. 46 Registry Structure and Format DASP 52282 Card User s Manual Chapter 5 Calibration 5 1 Calibration VR Description There are ten variable resistors VR on the DASP 52282 to adjust the A D and D A channels A precision voltmeter with 4 1 2 digits should be used to take an accurate voltage reference A calibration program can be found on the DASP 52282 software disk to perform the calibration steps It is strongly recommended to warm up the computer 30 minute before performing calibration Locations of individual VR are shown in Chapter 2 The corresponding VR s function is depicted as below VR2 ADC Analog Input Span Adjustment Calibration 47 DASP 52282 Card User s Manual 5 2 D A Calibration Calibration procedure is easily performed by using the calibration program Step by step walkthrough of D A calibration is listed as follows Select DAC1 JP8 and DAC2 JP9 to 10V output range Set DAC1 and DAC2 output data to 10V and adjust VR5 VR8 until DAC1 and DAC2 output voltage to 10V with 1 LSB tolerance 2 44mV Set DAC1 and DAC2 output voltage to 10V and adjust VR9 VR10 until DAC1 DAC2 output voltage to 10V with 1 LSB tolerance Select DAC1 JP8 and DAC2 JP9 to 0 10V output range Set DAC1 and DAC2 output voltage to OV adjust VR6 and VR7 until DAC1 and DAC2 output voltage to OV with 1 LSB tolerance respectively Set DAC1 and DAC2 output voltage to 10V adjust VR9 and VR10 until DAC1 and DAC2 output v
6. BIOS setting of your PC has released enough IRQ resources for PCI devices Do not share the same IRQ of DASP 52282 with other devices The DASP 52282 is a plug and play device for MS Windows and the OS will detect your DASP 52282 after you power on the PC The detail of driver and software installation is described in software manual of DASP 52282 After the hardware and software installation user can emulate and test DASP 52282 step by step as follows e Launch the PCI Configuration Utility of DASP 52282 to ensure that the resource of DASP 52282 is properly dispatched by the OS Press the scan button in the toolbar of PCI Configuration Utility to find the installed DASP 52282 and then check the resource list as show in following figure Ready to Double Click Highlight Module NON 4 Scan DASP 52282 with PCI Configuration Utility and Check the Dispatched Resource Check the dispatched resource of DASP 52282 take care the IRQ resource especially Hardware Installation 19 DASP 52282 Card User s Manual e Exit the PCI Configuration Utility and launch the ToolWorkShop for DASP 52282 As shown in following Se Boe Bh AXIOMTEK CO LTD ToolWorkshop ToolWorkshop Launch ToolWorkShop ToolWorkshop Select board test e shown in follo DASP 52282 Card User s Manual wing ToolWorkshop race Informatin iD 08N 0x01038005 gt Ready AD Scale
7. Block Diagram of Massive Data Transfer of DASP 52282 When DASP 52282 is triggered to acquire data the ADC samples the analog input signal and pushes the converted AD data to the on board FIFO When free space of the on board FIFO is less than its half capacity a HF signal is fired and the internal control logic of DASP 52282 produces an IRQ to the host The FIFO HF IRQ in the host is dispatched to the ring 0 driver of DASP 52282 and a batch data transfer mechanism is launched to transfer the acquired data in on board FIFO of DASP 52282 to host as show in following figure DASP 52282 Card User s Manual N V RRON VEE N SSS NG SSS SS NSS S Rss anang RR XWWWWWY RR RR R V anang RR RE NNN TRN NNN III RSS RM IIKI anang RR BRE Rss RR ZE RR RR RR WWWWW RSs SSS SS RSs RR RSs RR BE NINI NY SWS BILIN N software buffer host computer HF Notification DASP 52282 On board FIFO N X 2 N 4 ADC ADC ADC Principle of HF Interrupt Driven Massive Data Transfer of DASP 52282 31 Theorem of Operation DASP 52282 Card User s Manual 3 3 2 Circular Buffer for Massive Data Buffering To achieve the desired double buffering mechanism for DASP 52282 a 256K word ring 0 software buffer is constructed by the ring 0 drive
8. Card User s Manual 2 4 A D D A and DI DO Circuits and Wiring The analog input block diagram of DASP 52282 is depicted as in following figure The analog input differential and single end input digital input and digital output wirings are depicted as follows respectively AD Ch 0 Ch 16 FIFO pi ADC T Multiplexer Ch 0 Ch 8 Input Range Selection Channl Selection Analog Input Block Diagram for DASP 52282 MUX PGA ADC Analog Input Wiring Diagram for DASP 52282 Differential Input MUX PGA ADC Analog Input Wiring Diagram for DASP 52282 Single End Input Hardware Installation 17 DASP 52282 Card User s Manual R 1250hms Is MUX PGA ADC I I I I I I I I I l Digital Output Wiring Diagram for DASP 5228 DASP 52282 Card User s Manual 2 5 Quick setup and test To install a new DASP 52282 into an IBM PC compatible computer at first power off the PC and open its chassis then plug the DASP 52282 into a PCI slot To fully benefit from the high data transfer efficiency of DASP 52282 during data acquisition it is recommended not to install your DASP 52282 at the first PCI slot beside the AGP slot of the mainboard of PC The first PCI slot beside the AGP slot always shares the same IRQ with AGP device Based on the same consideration please ensure that the
9. I Timer o p lt EXT CLK Counter 0 Se Ra Tanah le Logi gt OUTO ogic lo Contrll Timer gt Counter 1 NG Im lo La n Software Timer Trigg Counter 2 hee lt EX Trig 16 bits DI0 15 8M Hz J DIO0 15 osc DIA CHO CH1 System Block Diagram of DASP 52282 Theorem of Operation 25 DASP 52282 Card User s Manual 3 2 Acquisition Modes of Analog Input DASP 52282 provides internal software hardware trigger operation and external hardware trigger operation for data acquisition application The supported internal trigger operations include a software polling mode and a hardware clocked pacer mode To synchronize external event and data acquisition of the DASP 52282 a series of external trigger mechanism including pre rigger middle trigger and post trigger is provided The operation mode of analog input of the DASP 52282 is described in the following subsections 3 2 1 Polling Mode With polling mode operation according to the user s polling command DASP 52282 performs an AD conversion of user specified analog input channel To command DASP 52282 to perform a polling operation write BASE 0x16 and ADC will convert one time When AD conversion finish Pready BASE 0x02 Bit3 will be high 3 2 2 Pacer Mode Benefited by the double buffering mechanism and the auto scan mechanism DASP 52282 can be operated at high sampling rate up to 330KHz Instead of polling software commanded AD conversion a series
10. 4x 1 1 Ref0 1 A D Reference Control Instrumentation Gain Oooo ee 42 Registry Structure and Format DASP 52282 Card User s Manual 4 2 5 AID Data Register Read Base Address Offset 0x04 05 D7 pe ps D4 ps pa pi Do AD Data D0 D11 DIS DIA DI 012 DN DIE D D AD Data 00 041 4 2 6 DAC Channel 1 Output Latch Register Write Base Address Offset 0x04 05 7 Do ps p4 D3 D2 pi po DA Data to Channel 1 D0 D11 ois bia DIG 012 DN b10 Ds Di DA Data to Channel 1 Reserved D0 D11 4 2 7 AID FIFO Data Register Read Base Address Offset 0x06 07 D7 pe ps D4 ps p2 pi Do AD FIFO Data D0 D11 rows ora DIS DIE om DIO De Di AD FIFO Data D0 D11 Registry Structure and Format 43 DASP 52282 Card User s Manual 4 2 8 DAC Channel 2 Output Latch Register Write Base Address Offset 0x06 07 D7 pe ps p4 D3 D2 pi po DA Data to Channel 2 D0 D11 Reserved DA Data to Channel 2 DO D11 4 2 9 8254 Timer Counter Register Read Write Base Address Offset 0x08 0C or Ds Ds Da os 02 DI D0 DIS pia DIA 02 DII DIO ps De Please refer to Intel s Micro system Components Handbook for detailed 4 2 10 8254 Timer Counter Control Words Register Write Base Address Offset 0x0E 8254 Control Words Please refer to Intel s Micro syste
11. A almost linear mapping exist between the 12 bit ADC code and analog input for the DASP 52282 the nonlinearity of this linear mapping is described in section 1 2 Figure 4 6 depicts the linear mapping of AD code of DASP 52282 and the analog input signal FS denotes the full span of analog input under the user configured analog input range The mapping of analog input to ADC code of DASP 52282 DASP 52282L DASP 52282H DASP 52282HL at FS and 0 input under different analog input ranges are listed in following respectively OxFFF OxFFF 0x800 0x800 0 0 FS 0 FS 0 FS 2 FS Bipolar Input Uni Polar Input Mapping of 12 bit ADC Code and Analog Input for DASP 52282 Theorem of Operation 33 DASP 52282 Card User s Manual range resolution 9 99512 00 000 10 000 0 00488V 10V OxFFF 4095 0x800 2048 0x0 0 1LSB 4 99756 00 000 5 000 0 00244V a ee 5000 Input Range Data Code and Resolution of DASP 52282 DASP 52282L Bipolar Input Ainge sa zmo gie mesto OxFFF 4095 0x0 0 1LSB peasy 249939 00 000 0 00061V OxFFF 4095 0x0 0 1LSB 1 249695 00 000 0 000305 0 1 25V OxFFF 4095 Ox0 0 1LSB Input Range Data Code and Resolution of DASP 52282 DASP 52282L Uni Polar Input 34 Theorem of Operation DASP 52282 Card User s Manual Input Data 9 99512 00 000 10 000 0 00488V OxFFF 4095 0x800 2048 4 99756 00 000 5 000 0 00244v OxFFF 4095 Ox800 2048 Ox0 0
12. DASP 52282 12 bit 330KHz Multifunction w Free Running Card User s Manual Disclaimers The information in this manual has been carefully checked and is believed to be accurate Axiomtek Co Ltd assumes no responsibility for any infringements of patents or other rights of third parties which may result from its use Axiomtek assumes no responsibility for any inaccuracies that may be contained in this document Axiomtek makes no commitment to update or to keep current the information contained in this manual Axiomtek reserves the right to make improvements to this document and or product at any time and without notice No part of this document may be reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical photocopying recording or otherwise without the prior written permission of Axiomtek Co Ltd Copyright 2004 by Axiomtek Co Ltd All rights reserved September 2004 Version A1 0 Printed in Taiwan ESD Precautions Integrated circuits on computer boards are sensitive to static electricity To avoid damaging chips from electrostatic discharge observe the following precautions Do not remove boards or integrated circuits from their anti static packaging until you are ready to install them Before handling a board or integrated circuit touch an unpainted portion of the system unit chassis for a few seconds This helps to discharge any static electricity on y
13. I O connector CON1 on the DASP 52282 is a 20 pin flat connector for digital input signals CON1 enables you to connect to accessories either the daughter board DB 87822 or the terminal block TB 88320 with the flat cable CB 89320 2 or CB 89320 5 CON2 The I O connector CON2 on the DASP 52282 is a 20 pin flat connector for digital output signals CON2 enables you to connect to accessories either the daughter board DB 87825 or the terminal block TB 88320 with the flat cable CB 89320 2 or CB 89320 5 CONS The I O connector CON3 on the DASP 52282 is a JTAG test signal for internal usage only CON4 The I O connector CON4 on the DASP 52282 is a 37 pin D sub connector for analog input and output signals CON4 enables you to connect to accessory TB 88037 with the shielded cable CB 89037 2 or CB 89037 5 Hardware Installation DASP 52282 Card User s Manual 2 2 2 Digital Input Connector CON1 o O So 28 E con 51 S CONT CB 89320 DB 87822 Ol lel 7 Oka HA Ta ale ali E gt a GG sa G i 7 SIS GIS 6205 To CON1 CB 89320 TB 88320 DI Signal Connections for DASP 52282 Hardware Installation 9 DASP 52282 Card User s Manual e CONI Digital Input Connector Pin Assignment 20 pin Flat Connec
14. echanism with 1K FIFO A D trigger mode software trigger pacer trigger external trigger Supports software programmable gain e Supports Windows 98 NT 2000 XP Labview 6 0 7 0 driver e Supports VB VC BCB Delphi sample program 2 Introduction DASP 52282 Card User s Manual 1 2 Specifications Analog to Digital Converter A D Channels 16 Single ended or 8 differentials Resolution 12 bit FIFO size 1K samples Sampling Rate 330KS s max Conversion Time 34 s ADC input range 10V Input protect 30 Vp p On chip sample and hold Programmable Gain m Low Gain DASP 52282 DASP 52282L only Gan 05 1 2 4 8 unipolar Na 010v 0 5v ozs 0125 Bipolar 10V 5v 2 5v 1 25v 0 625v m High Gain DASP 52282H DASP 52282HL cam os 1 0 100 1000 Unipotar wa 0 10V GV Tn e Small signal bandwidth for PGA m Low Gain DASP 52282 DASP 52282L only an os 1 2 8 m High Gain DASP 52282H DASP 52282HL only cam os 1 o 100 100 Drift 0 1 LSB gain 0 5 Max input voltage 20V Input impedance 10000 MQ 6 pF On chip sample and hold Introduction 3 DASP 52282 Card User s Manual AD Trigger Method Software Pacer External Pre trigger Post trigger Middle trigger Analog Input Data Transfer Method Polling Interrupt FIFO Operation mode Polling mode Pacer mode Interrupt mode External pre trigger mode External p
15. egister Low Byte D A Channel 1 Low Byte BASE 0x05 A D Data Register High Byte D A Channel 1 High Byte Registry Structure and Format 37 DASP 52282 Card User s Manual 4 2 I O Register Map 4 2 1 Digital Input Buffer Register Read Base Address Offset 0x00 01 or ve os va os oz vr 00 ois ow om ow on ow EE Digital Input High Byte D8 D15 4 2 2 Digital Output Latch Register Write Base Address Offset 0x00 01 or ve os pa 03 oz or vo ois ow om ow Ta ow T 4 2 3 General Status Buffer Register Read Base Address Offset 0x02 03 D7 pe ps pa D3 D2 p1 po ois ow om TnS om ovo oo 8 38 Registry Structure and Format DASP 52282 Card User s Manual General Status Buffer Register is used to check the A D activity The format is described as bellows EF Bit 0 0 FIFO is Empty HF Bit 1 0 FIFO is Half Full FF Bit 2 0 FIFO is Full PReady Bit 3 1 End of A D Conversion ExtPulse Bit 4 1 External Trigger is active MidEnd Bit 5 1 End of External Middle Trigger Diff S E Bit 6 1 Single Ended Bit 6 0 Differential EnDAC Bit 7 0 Enable DAC1 and DAC2 output CMDOK Bit 8 1 PIC receive command and data are correct Handshak Bit 9 1 Setting Command to PIC ModSel0 1 2 Bit 10 11 12 Selected ADC operation mode refer to section 2 3 4 Mode0 2 OUTO Bit 13 1 Status
16. ith 2m and 5m are designed for the DASP 52282 digital I O connector respectively Terminal Block TB 88037 D sub 37P female terminal block with DIN rail mounting The terminal block is directly connected to analog I O connector of the DASP 52282 Introduction 5 DASP 52282 Card User s Manual TB 88320 Flat type 20P female terminal block with DIN rail mounting The terminal block is directly connected to D I or D O connector of the DASP 52282 Daughter Board DB 87822 16 isolated D I daughter board The board contains 16 channels isolated digital input which is designed for TTL level digital input signal to the DASP 52282 DB 87825 16 relay D O daughter board The board contains 16 channels relay output which is driven by TTL level digital output signal of the DASP 52282 Introduction DASP 52282 Card User s Manual Chapter 2 Hardware Installation 2 1 Board Layout DASP 52282 Board Layout for DASP 52282 Hardware Installation 7 DASP 52282 Card User s Manual 2 2 Signal Connections 2 2 1 Signal Connection Descriptions COM A AIO CB 89037 2 aay CB 890375 Ba 5 DI e B y CB 89320 2 DB 87822 TB 88320 DASP 52282 08893208 o H i CB 893202 DB 87825 TB 88320 CB 893205 Signal Connections for DASP 52282 Referring to above figure the accessories of the DASP 52282 are depicted and described as below CON1 The
17. m Components Handbook for detailed 44 Registry Structure and Format DASP 52282 Card User s Manual 4 2 11 Clear FIFO Content Register Write Base Address Offset 0x10 Tor ps os Da 03 D2 Di 00 D15 D14 D13 D12 D11 D10 pe pe Reserved 4 2 12 Clear Flag Register Write Base Address Offset 0x12 o7 06 05 Da Da 02 DI Do D15 D14 D13 D12 D11 Dio Do ps Reserved 4 2 13 Enable DAC1 and DAC2 Output Register Write Base Address Offset 0x14 D7 Do ps p4 D3 D2 pi po Write Any Value to Enable DAC1 and DAC2 ois bia Tas 012 DN DIE 0o Di Reseea Reserved Registry Structure and Format 45 DASP 52282 Card User s Manual 4 2 14 A D ADC Software Polling Control Register Write Base Address Offset 0x16 07 ps os Da 03 02 Di De D15 D14 p13 D12 D11 D10 pe pe Reserved Write this register to any value to generate a Conversion Signal and the PReady Bit Status Register Bit 3 will be set to TRUE 4 2 15 Enable ADC Register Write Base Address Offset 0x18 Write Any Value to Enable AD Conversion D15 D14 D13 D12 D11 Dio Do ps Reserved o J 4 2 16 Disable ADC Register Write Base Address Offset 0x1A b7 pe ps p4 ps pa pi Do Write Any Value to Disable AD Conversion D15 D14 D13 D12 D11 pio pe pe Reserved
18. of 8254 Counter0 is high SetINT Bit 14 1 Interrupt event active CMDCRL Bit 15 1 Write command and data to PIC Registry Structure and Format 39 DASP 52282 Card User s Manual 4 2 4 Command Output Latch Register Write Base Address Offset 0x02 03 or os os oa os o2 J or 00 pauna muxe muxo HOS ow oe nas ois ow om orz bn ow oo oe pesto x x_ ewoor err Reto Gain Cano Command Output Latch Register is used to set the A D operation User must write high byte bit8 bit15 first The format is described as bellows X Don t care bits Mode0 2 HDSK A D Operation Mode Selection Description HDSK Mod Mode Moden pm elofole Internal Pacer Mode Oa RSI A BOE sipas 0 0 1 1 Extema Post Trager Mode 0 1 0 1 Extema Made Trogermode 0 1 1 1 MUX0 3 A D Multiplex Selection e A D Input Channel Selection MUXO MUX3 e MUX3 MSB MUXO LSB e Single Ended Mode MUX0 MUX3 Channel 0 15 e Differential Mode MUXO MUX2 Channel 0 7 40 Registry Structure and Format DASP 52282 Card User s Manual m Single Ended mode channel selection 0 0 0 0 Cho zener Te O Jn o 1 0 Ko fo po m MUX3 Don t care bit in differential mode Registry Structure and Format 41 DASP 52282 Card User s Manual Gain0 1 A D Gain Control PGA205 or PGA206 ID GAIN Gano Gam xx fo o x o 1 es 1 o
19. of hardware clocked AD conversions can be performed to acquire data The hardware pacer clock can be programmed from several Hz to 330KHz With double buffering mechanism the host program can retrieve batch data from the software buffer periodically The only thing user need to consider is to retrieve buffered data frequently enough to prevent from the un retrieved data in the buffer been overwritten The functional block diagram of pacer mode operation of DASP 52282 is depicted as in following figure Digital Output Analog Input lt ADC Convert Command Timer Trigger Logic _ ounter Functional Block Diagram of Pacer Mode Operation of DASP 52282 DASP 52282 Card User s Manual 3 2 3 External Trigger Mode To synchronize external event and data acquisition of the DASP 52282 a series of external trigger mechanism including pre trigger middle trigger and post trigger is provided Based on the hardware pacer design described in 3 2 2 and the gate control logic for the hardware pacer clock various external trigger mode operations of DASP 52282 are realized According to the status of consumed external trigger signal and the amount of acquired data counted by hardware logic circuit the gate control logic of AD conversion of DASP 52282 is emulates With pre trigger mode operation DASP 52282 acquires and keeps the user specified amount of data before the external trigger signal fi
20. olling CHO CH1 Stop S Perform DIO Test of DASP 52282 the DO of DASP 52282 Can be Routed to DI and Test Them by Commanded the DO Port Value and Read Back the DI Port Value DIO Wiring Refer to Section 2 4 p DASP 52282 Informatin DON 001038005 Ready gt Interrupt Fy x CIEL Pollina Pacer PostTrigger DA Range Fav MOV O Selected ID 0 Card Type DASP52282 Value CH Value 1 442398 CH8 000000 Signal Type Differential 1 452315 CH9 00 0000 1 4 4580 CH10 00 0000 Dil version 20040605 7 4 6045 CHi1 00 0000 Eneble Release 7 4 3701 CHI2 00 0000 2 4 4824 CH13 000000 DA Test 2 4 4287 CH14 00 0000 Amplitude o o 3 ss val Jo 1 4619 CH15 00 0000 Channel Star Polling CHO CH1 Stop m DIO Test DI om DO Om Ecce APIHIN MA ERNERERE SEEEEEEE Perform the Analog Input Test of DASP 52282 A Reference Analog Input Signal can be Connected to AI Pins of Terminal Box of DASP 52282 Press Get Button to Read Back AI Value e Press Stop button to stop AD converting Before exiting ToolWorkShop press Release button to release DASP 52282 library Hardware Installation 23 DASP 52282 Card User s Manual This page does not contain any information 24 Hardware Installation DASP 52282 Card User s Manual Chapter 3 Theorem of Operation DASP 52282 is a high performance PCI inte
21. oltage to 10V with 1 LSB tolerance respectively 5 3 A D Calibration Steps Calibration procedure is easily performed by using the calibration program Step by step walkthrough of A D calibration is listed as follows Connect A D input channel 0 to ground OV Select bipolar input configuration adjust VR3 until ADC reading value to zero with 0 5 LSB tolerances 1 22mV Select unipolar input configuration adjust VR4 until ADC reading value to zero with 0 5 LSB tolerances 1 22mV Connect A D input channel 0 to a DC voltage source 5V or directly connect to D A output 5V Adjust VR2 until ADC reading data to 5V with 1 LSB tolerance 2 44mV Calibration DASP 52282 Card User s Manual Appendix A Analog Input Gain Mode Configuration Command Register High Byte bit11 bit8 Gal Gain Type ee Ea ange Do lol njan av S ce po fo ft oo 2 ax o fo 1 TSS por Tass 128v o fr o fo osx soa sov 2v i 0 0 0 8 tx mes 0 707 10v EBE e a ar ee Po 0n Ss User could fill the Gain Mode in this table into PCI828x_SetADConfig function in the driver DLL to set the analog input range configuration Analog Input Gain Mode Configuration 49 DASP 52282 Card User s Manual This page does not contain any information 50 Analog Input Gain Mode Configuration DASP 52282 Card User s Manual Appendix B Dimension of DASP 52282 and Accessories e DASP 52282 e TB 88037
22. onvert Command Pacer Tick Timer Convert le Counter 1 Logic Contrller 4 Middle Trigger Counter Timer Counter 2 External Trigger Functional Block Diagram of Middle Trigger of DASP 52282 Convert Counter N N1 N2 External Trigger signan N2 Middle Trigger Counter i N ia NG ya N2 c User Start Analog Signal Convert Start Convert Stop Middle Trigger Mode Principle of External Middle Trigger Operation of DASP 52282 Theorem of Operation 29 DASP 52282 Card User s Manual 3 3 Double Buffering Mechanism For Fast Data Acquisition To achieve gapless high speed data acquisition a double buffering mechanism has been designed and realized for DASP 52282 The on board FIFO of DASP 52282 serves as the hardware level data buffers and a 256K WORD software level data buffer is implemented by the ring 0 driver of DASP 52282 3 3 1 On Board FIFO and FIFO Half Full Interrupt The DASP 52282 provides a 1K WORD on board FIFO first in first out buffer to support massive data transfer to its host A FH half full interrupt supported by the on board FIFO is used to launch batch data transfer mechanism of ring O driver of DASP 52282 The following shows the functional block diagram of massive data transfer of DASP 52282 Analog Input ADC Digital Output FIFO Half Full Chipset KIRAN IRQ Logic Functional
23. ormation Setup AO Range and Press Setup Button to Load DASP 52282 Library p DASP 52282 Informatin fe Dan 0x0103B005 Ready AD Scale 187 z DA Range Fo MOV g Selected ID 0 Card Type DASP52282 Signal Type Differential Dil Version 20040605 Amplitude 55 val dol Channel e Mid Trigger Auto Scan Interrupt Pollina Pacer PostTrigger Value CH Value 44298 CH8 00 0000 1 45215 CH9 000000 1 44580 CH10 00 0000 7 4 6045 CH11 500 0000 7 4 3701 CH12 00 0000 1 4 4824 CH13 00 0000 144 4287 CHI4 00 0000 774 6191 CH15 00 0000 Star Polling Stop Polling Perform Analog Output Test by Set the DA Value and Measure the Output Signal of DASP 52282 by Multi meter 22 Hardware Installation DASP 52282 Card User s Manual p DASP 52282 Informatin DAG Test In 10101036008 Ready PreTrigger MidTrigger Auto Sean Interrupt 10V 10y g wss E Poling Pacer Post Trigger DA Range Fo 10V z Selected ID 0 Card Type DASP52282 ICH Value CH Value CHO 4 4238 CH8 00 0000 Signal Type Differential CH1 4 5215 CH9 000060 CH2 4 4580 CH10 00 0000 Dil version 20040605 CH 3 4 6045 CH11 00 0000 Eneble Release CH 4 4 3701 CH12 00 0000 DA CH 5 4 4824 CH13 00 0050 CH6 4 4287 CH14 00 0000 Test Amplitude ss Mal 99 CH7 46191 CH15 00 0000 Channel 1 Start Polling Stop P
24. ost trigger mode External middle trigger mode DC Accuracy INL 1 LSB gain 0 5 DNL 1LSB gain 0 5 AC Accuracy SNR 71dB gain 0 5 Automatic Scan Mechanism Digital to Analog Converter D A only DASP 52282 DASP 52282H Channels 2 independent Resolution 12 bit analog device AD7945BR Output range Bipolar 9 9998V 10 0003V 10 10V Unipolor 0 0003V 10 0002V 0 10V Accuracy 0 5 LSB Offset 1 Slew Rate 13V ps Drift 0 5 LSB Output Driver 5mA Max Transfer Rate 204 S s Output Impendence 15 Q Settling Time 0 6 ns to 0 01 for Full Scale Step Linearity 1 2 bit Introduction DASP 52282 Card User s Manual Digital I O Voltage high F Digital Input Digital Output TTL level TTL level Voltage low VIL 0 8V max VOL 0 5V max IIL 0 4mA max IOL 8mA max VIH 2 0V min VOH 2 7V min IIH 20 A max IOH 400A max 1 3 Accessories To make the DASP 52282 functionality complete we carry a versatility of accessories for different user requirements in the following items Wiring Cable e CB 89037 2 37 pin female D sub type cable with 2m length e CB 89037 5 37 pin female D sub type cable with 5m length The shielded D sub cable with 2m and 5m are designed for the DASP 52282 analog I O connector respectively e CB 89320 2 20 pin female flat type cable with 2m length e CB 89320 5 20 pin female flat type cable with 5m length The flat cable w
25. our body Wear a wrist grounding strap available from most electronic component stores when handling boards and components Trademarks Acknowledgments AXIOMTEK is a trademark of Axiomtek Co Ltd IBM is a registered trademark of International Business Machines Corporation MS DOS and Windows 95 98 NT 2000 are trademarks of Microsoft Corporation Phoenix Award is a trademark of Phoenix Award Software Inc IBM PC AT PS 2 VGA are trademarks of International Business Machines Corporation Intel and Celeron Pentium Ill are trademarks of Intel Corporation Other brand names and trademarks are the properties and registered brands of their respective owners Table of Contents Chapter 1 Introduetioni aaa 1 1 1 PALIN OS cia ricarica 2 TZ SpecliicatioliS iii 3 13 ACCESSO Sciare 5 Chapter 2 Hardware Installation eerrcreerene 7 2 1 Board LAYON iniziai 7 2 2 Signal Connections sissisodan 8 2 21 Signal Connection Descriptions 8 2 2 2 Digital Input Connector CONI 9 2 2 3 Digital Output Connector CON2 11 2 2 4 A D D A and Timer Counter Connector CON4 13 2 3 J mper SEIN 16 2 3 1 ADC Clock Source JP4 essen 16 2 3 2 DAC1 DAC2 Output Range Selection JP8 and JPI da 16 2 3 3 A D Single Ended Differential Selection JP1 16 2 4 AID D A and DI DO Circuits and Wiring 17 2 5 Quick setup andtes
26. r of DASP 52282 The ring 0 software buffer serves as the second data buffer for massive data transfer between DASP 52282 and host computer The ring 0 buffer operates as a circular buffer that will continuously update its contents and recursively overwrite the contents of the buffer when buffer is full Incorporate with a header contains current status of the circular buffer user can access the gapless acquired data through the provided ring 3 API 3 4 Automatic Scan To perform high speed multi channel data acquisition or automatic scan an on board micro controller is used to manipulate the input multiplexer and the PGA programmable gain amplifier of DASP 52282 Benefited by the capacity of embedded micro controller DASP 52282 can perform high speed channel multiplexing and gain adjustment automatically A sequence of instructions to perform automatic scan is stored in the on chip RAM of the micro controller and can be software configured through a complete set of ring 3 API of DASP 52282 Figure 3 10 describes the principle of operation of auto scan schematically The user configured auto scan instructions are stored into a queue structure and the on board micro controller executes these instructions recursively when data acquisition is triggered Ch 0 ba Ch 1 ipod Ch 7 Gain 1 Gain 0 5 Gain 2 Principle of Auto Scan DASP 52282 Card User s Manual 3 5 Analog Input Range ADC Code and AD Value
27. red With the post trigger operation DASP 52282 acquires and keeps the user specified amount of data after the external trigger signal fired The functional block diagram of external trigger mode operation of DASP 52282 is depicted as below figure Principles of pre trigger and post trigger are also shown in following Digital Output Analog Input CU ADC Convert Command Convert Logic _ Timer Contrller Counter L External Trigger Functional Block Diagram of External Trigger of DASP 52282 Theorem of Operation 27 DASP 52282 Card User s Manual Pre Trigger Mode External Trigger Signal Convert Counter N ie N gt User Start i Analog Signal Convert Start Convert Stop Pre Trigger Mode Principle of External Pre Trigger Operation of DASP 52282 Post Trigger Mode External Trigger Signal i Convert Counter N gt N gt User Stop Analog Signal Convert Start Convert Stop Post Trigger Mode Principle of External Post Trigger Operation of DASP 52282 Middle Trigger Mode For middle trigger operation DASP 52282 acquires and keeps user specified amount of data before the external trigger signal fired and continues to acquire and keep data after the external trigger signal fired till the user specified amount of data is acquired DASP 52282 Card User s Manual Digital Output Analog Input lt ADC C
28. rface multi function data acquisition board To facilitate high speed data acquisition and data transfer a series of hardware and software mechanism has been designed and implemented for DASP 52282 To synchronize external event and data acquisition a series of external trigger mechanism is provided To guarantee the gapless data acquisition a hardware software level double buffering and a hardware level automatic channel scanning is supported The theorem of these operations is described in the following sections Please refer to the software manual of DASP 52282 for the details and practices of them 3 1 Overview of DASP 52282 System Architecture and Operation The system block diagram of DASP 52282 is depicted as in following figure A PCI interface to host is constructed with a PCl bridge and a 33MHz bus clock is used to drive it In the local bus site 5 major functions of DASP 52282 have been implemented include the AD circuits the DA circuits the DIO circuits the internal control logical circuits and a FIFO buffer that provided the hardware level data buffering for double buffering mechanism of DASP 52282 16 8 to 1 Tr no gc 12 bits sai s AID ADC iiai CHO CH15 is a pei Y Bridge Channel AJ EOC Select FIFO h
29. serial number of each DASP in the EEPROM before shipping The PCI scan utility can scan all the DASP and show users the serial number of each DASP helping the user to easily identify and access each card Introduction 1 DASP 52282 Card User s Manual Easily Developing Application Programs Various Sample Programs The DASP 52282 series provides many user friendly sample programs to help users developing various application programs in different units such as VB VC BCB and Delphi And it also supports the most popular Labview 6 0 7 0 drivers The API of the DASP 52282 has passed strict assembling tests that helps users not necessarily writer such complicated and wordy programs while using it Easy to Troubleshoot Hardware Resource PCI Scan Utility The PCI scan utility can scan all the DASP products within the system and can show users all system resources such as serial numbers IRQ and I O addresses This lets users clearly see through and immediately know whether all DASPs are working normally decreasing the time of searching confirmation e DASP 52282 12 bit 330 KHz multifunction board e DASP 52282L 12 bit 330 KHz multifunction board w o DAC e DASP 52282H 12 bit 330 KHz high gain multifunction board e DASP 52282HL 12 bit 330 KHz high gain multifunction board w o DAC 1 1 Features e 2 channel 12 bit D A voltage output 16 D I and 16 D O TTL compatible Maximum sampling rate up to 330KHz Supports free running m
30. t 19 Chapter 3 Theorem of Operation sesesesesesesesesesesesesesese 25 3 1 Overview of DASP 52282 System Architecture and OPEration casas GD ASG SAGA AG 25 3 2 Acquisition Modes of Analog Input 26 3 21 Polling Mode 23am NUNG 26 3 2 2 Racer Mode 26 3 2 3 External Trigger Mode 27 3 3 Double Buffering Mechanism For Fast Data ACQUISITO nici 30 3 3 1 On Board FIFO and FIFO Half Full Interrupt 30 3 3 2 Circular Buffer for Massive Data Buffering 32 DH Automatio SCAM icsse 32 3 5 Analog Input Range ADC Code and AD Value 33 Chapter 4 Register Structure and Format 37 di delia 37 4 2 VO Register Map nie 38 4 2 1 Digital Input Buffer Register 38 4 2 2 Digital Output Latch Register 38 4 2 3 General Status Buffer Register 38 4 2 4 Command Output Latch Register 40 4 2 5 A D Data Register sss sss 43 4 2 6 DAC Channel 1 Output Latch Register 43 4 2 7 A D FIFO Data Register 43 4 2 8 DAC Channel 2 Output Latch Register 44 4 2 9 8254 Timer Counter Register 44 4 2 10 8254 Timer Counter Control Words Register 44 4 2 11 Clear FIFO Content Register 45
31. tion Pin Description i ang iuto 20 Anata nests 3 Andoginput2 22 ety put to 4 ang muto 20 lanang Analog Input 4 24 Analog Input 12 E a e Analoginput 27 Analog inputs o Analog Ground 28 Analog gang Pepe 1 14 Hardware Installation DASP 52282 Card User s Manual e CONA A D D A and Timer Counter Connector Pin Assignment D Sub 37 pin Connector for Differential Signal Pin Description Fin Description Analog Input 0 Analog Input 0 Analog Input 1 Analog Input 1 Analog Input 2 Analog Input 2 Analog Input 3 Analog Input 3 Analog Input 4 Analog Input 4 KA Analog Input 5 Analog Input 5 Analog Input 6 Analog Input 6 8 Analog Input 7 Analog Input 7 9 Analog Ground Analog Ground Analog Ground Analog Ground OSC clock Out 8MHz External Clock Input ref H oo Hardware Installation 15 DASP 52282 Card User s Manual 2 3 Jumper Setting 2 3 1 ADC Clock Source JP4 Pacer Tick Timer 8254 Counter1 J mper External OSC Clock Cascade from p Clock 8MHz 8254 COUTO JP4 3 5 5 6 5 7 General Purpose Timer Counter 8254 Counter0 External Clock OSC clock 8MHz 2 3 2 DAC1 DAC2 Output Range Selection JP8 and JP9 DAC Channel Jumper Output 0V 10V Output 10V 10V Ch2 JPY 1 3 and 2 4 3 5 and 4 6 2 3 3 A D Single Ended Differential Selection JP1 Single ended Differential JP1 1 3 and 2 4 3 5 and 4 6 DASP 52282
32. tor Fin Description Pm Description e Digital input arr 6 Diora mosar 7 Digita input rr 6 aane o Digita Input arte 10 Digter input orrri 10 Hardware Installation DASP 52282 Card User s Manual 2 2 3 Digital Output Connector CON2 so com lt lt w lo con a Do 90 O CON2 CB 89320 DB 87825 com a lt DI CON 0 po 85 e CON2 CB 89320 TB 88320 DO Signal Connections for DASP 52282 Hardware Installation 11 DASP 52282 Card User s Manual e CON2 Digital Output Connector Pin Assignment 20 pin Flat Connector Fin Description Fin Description e Dial Output 4 TTL__ _6_ Digital Ouput sT 7 Digi Output TTL__ _8_ Digital aea o Digital Output rr 10 Digita Output oTe 12 Hardware Installation DASP 52282 Card User s Manual 2 2 4 AID DIA and Timer Counter Connector CON4 e CONA A D D A and Timer Counter Connector Pin Assignment CB 89037 OOO VCH OO TOT HOO OOH COMO OMA AAO OOO AAO Og TB 88037 AIO Signal Connections for DASP 52282 Hardware Installation 13 DASP 52282 Card User s Manual D Sub 37 pin Connector for Single Ended Signal Pin Descrip

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