rtX PXI 75DL1-4CLF00-05
Contents
1. Model cPCI 75DL1 3U PEE Te Division SIXTEEN 16 LVDT RVDT STIMULUS Channels North Atlantic LVDT RVDT OUTPUTS PROGRAMMABLE 4 3 or 4 Wire or 8 2 Wire 16 BIT RESOLUTION WRAP AROUND SELF TEST Optional Excitation Supply Commercial amp Military Versions Available FEATURES 16 Bit Resolution Continuous background BIT testing with Reference loss detection Power On POST test Automatically supports either 5V or 3 3V PCI bus Transformer isolated 4 and 8 channel 2 wire versions available or 2 and 4 channel 3 or 4 wire versions available Stable output with temperature Watchdog timer and soft reset I O via Front Panel P2 or both No adjustments or trimming required Commercial or Extended Temperature Part number S N Date code amp Rev in nonvolatile memory DESCRIPTION This card offers eight 8 two wire or four 4 three four wire transformer isolated PROGRAMMABLE LVDT RVDT outputs with wrap around self test and optional excitation supply Instead of buying cards that are set for specific outputs the uniqueness of this design makes it possible to buy our generic card that can be programmed and reprogrammed in the field for any excitation and signal voltage between 2 0 and 28 volts Operating frequency between 360Hz and 10Khz can be specified see Part Number One transformer isolated excitation is supplied for each A B output pair The output format of this card can be configured for either two wi2. or 16 bit 2 s compliment word that represents position The data is available at any time Note In 3 4 wire mode only channels 1 4A need to be read Soft Reset Write an integer 1 to Soft Reset Register then clear to 0 before 50ms elapses CAUTION Register is level sensitive and for proper card operation the logic level 1 or pulsewidth must be lt 50ms Considering minimum and maximum 1 us lt pulsewidth lt 50ms Processor reboots in about 400 ms after which calibration procedures begin This function is equivalent to a power on reset Watchdog timer This feature monitors the Watchdog Timer Register When it detects that a code has been received that code will be inverted within 100 uSec The inverted code stays in the register until replaced by a new code The user should interrogate the Watchdog Timer Register after 100 uSec for the inverted code to confirm that the processor is operating Part Number Read as a 16 bit binary word from the Part Number Register A unique 16 bit code is assigned to each model number Serial Number Read as a 16 bit binary word from the Serial Number Register Date Code Read as decimal number from the Date Code Register Four digits represent YYWW Year Year Week Week Rev Levels There are a total of 4 Revision Level Registers which are listed below Each register is defined as 16 bits The integer value of that particular register corresponds to the actual revision Rev le
3. Status Register Reading will unlatch register Status Excitation Check the corresponding bit of the Excitation Status Register for status of the excitation input for each active channel A 1 means Excitation ON 0 means Excitation Loss on active channels Channels that are inactive are also set to O Excitation loss is detected after 2 seconds Note The Excitation voltage is shared among the channel pairs however each channel pair can have distinct external excitation voltages Excitation monitoring is always enabled Any Excitation status failure transient or intermittent will latch the Excitation Status Register Reading will unlatch register Status Sig Signal status is only available in 3 or 4 wire mode Check the corresponding bit of the Signal Status Register for status of the output signal for each active channel A 1 means Signal is valid 0 means Signal loss Channels that are inactive are also set to O Signal loss is detected after 2 seconds Signal monitoring is always enabled except in 2 wire mode Any Signal status failure transient or intermittent will latch the Signal Status Register Reading will unlatch register Read Wrap Around Position Wrap around positions are read from the Wrap around D L Ch Registers Each enabled D L channel is measured prior to the transformer output and can be read from the corresponding Wrap around D L Register The generated result is a 16 bit binary word
4. no external programming and can be Initiated or terminated via the bus CAUTION Outputs are active during this test Check connected loads for possible interaction The POST test when enabled will initiate a D3 test at power turn on Temperature Range This board is available for C or E operating temperature ranges See part number designation The C version operates from 0 C to 70 C and is populated with standard high quality commercial semiconductors The E version used for severe environmental condition operates from 40 C to 85 C and is populated with high quality extended temperature semiconductors North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 19 2005 75_DL1_A001_Rev_2 4 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 1 of 8 SPECIFICATIONS Resolution Linearity Output Format Load Regulation Excitation Frequency excitation Phase Shift input to output Phase shift A B Excitation each Z in Interrupts Signal Logic Level Power Supply Temperature operating Temperature storage Size REFERENCE SUPPLY Voltage Frequency Regulation Output power North Atlantic Industries Inc 110 Wilbur Place Bohemia NY 11716 16 bits 001526 FS 0 1 FS for 2 lt TR lt 2 0 05 FS available at a specified frequency and TR Configurable for either 3 4 wire or 2 wire Transformer isolated Output voltage wil
5. 2 A B Hi CH4 B Lo CH1 A Hi CH3 A Lo 3 Exc 4 A B Lo CH1 B Lo 8 CH3 B Hi Exc 4 A B Hi Exc 1 A B Lo 7 CH3 A Hi Exc Out Lo Exc 1 A B Hi CH3 B Lo Exc Out Hi CH2 A Lo Exc 3 A B Lo CH2 B Hi Exc 3 A B Hi CH2 A Hi CH4 A Lo CH2 B Lo CH4 B Hi TABLE 4 North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 19 2005 75_DL1_A001_Rev_2 4 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 7 of 9 CODE TABLE Code Frequency Hz Notes 01 400 02 2 8k 3 2K 03 2K 04 2 69K 05 3K See code list addendum for descriptions of code 50 and above TABLE 5 PART NUMBER DESIGNATION 75DL1 X X LX X X XX TOTAL NUMBER OF CHANNELS CODE See Code Table 2 2 Channels of 3 or 4 wire OR 4 channels of 2 wire OPTIONS 4 4 Channels of 3 or 4 wire 0 NONE OR 8 channels of 2 wire ENVIRONMENTAL OPTIONAL REFERENCE SELECTION C 0 C to 70 C 0 No On Board Reference E 40 C to 85 C A 2 28 VRMS output H E With Removable Conformal Coating C 115 VRMS fixed output K C With Removable Conformal Coating contact factory for other temperature requirements MECHANICAL F Front Panel I O P Rear I O only B Front Panel I O and Rear I O Note J2 connections can not be used for Analog signals in a PXI chassis Analog Outputs must be via the front panel I O only F North Atlantic Industries Inc 631 567 1100 631 567 1823
6. GS 4 19 5 2 4 Changed Address DD 05 07 07 North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 19 2005 75_DL1_A001_Rev_2 4 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 9 of 9
7. age of zero when the core is at the electrical center When the core is displaced in either direction from center the voltage increases linearly either in phase or out of phase with the excitation depending on the direction Output Configurations LVDT Coil Voltage vs Position 2 WIRE OR 2 WIRE 1 CHANNEL 2 CHANNEL Va Vb K A oo A oo In Phase elo A Va Re A Va Vb Example 10Vrms Excitation z ENA z By HE O 4 O DE Ta j SS my Va Ss E oa O sC O lt o x lt PARI x lt Paia i gt B Vb f S B Va Vb ye YO 5 0V Vb 4 WIRE 3 WIRE Ave Ave 0 0V St aie gt gt A Va POSITION FS 0 FS O 5 O SIC Va Vb 10V Va Vb 10V Va Vb 10V T J ae T Si Va Vb 10V_ Va Vb 0V Va Vb 10V Pre y A Va OV Va 5V Va 10V Q JS Q Vb 10V Vb 5V Vb OV W s B Vb ii S B Vb Yoo ve POSITION Va Vb Va Vb PROGRAMMING INSTRUCTIONS Power On Reset or System Reset All parameters are restored to last saved setup and if POST was previously enabled in last setup a D3 Test will be initiated A power on automatic calibration test is ran and completes in approximately 30 seconds Configuring Channels for 2 and 3 4 Wire Outputs When referring to the register map make note that there are references made to channels 1A amp B through 4A amp B For channels programmed for 3 4 wire mode the A amp B Position Data Registers are shared Therefore only Position Data Register A is s
8. endently Factory default POSITION 0 Calculate using register value POSITION 32768 Example For a POSITION 0 5 gt register value 0 5 32768 16384 OxC000 Example For a POSITION 0 75 gt register value 0 75 32768 24576 0x6000 The Output voltages in 3 4 wire mode are related to the position by Va Excitation Voltage TR 0 5 Position 0 5 Vb Excitation Voltage TR 1 0 5 Position 0 5 The Output voltage in 2 wire mode is related to the position by V Excitation Input TR Position Transformation Ratio TR Enter the transformation ratio as an integer for each channel pair A amp B in the Transformation Ratio Channel Register When entering a ratio for channels that are configured for 2 wire mode both channels A amp B of that number pair will have the same transformation ratio Factory default TR 1 Set the TR using the following formula TR register value TR 1000 Example For a TR of 0 5 gt TR register value 0 5 1000 500 01F4h The valid range of TR is 0 00 lt TR lt 2 00 NOTE TR Input Voltage must be less than 28V Optional Excitation Output Frequency Enter the excitation output frequency as an integer directly in Hz in the Frequency Register Example For a Excitation Output Frequency of 1000Hz gt register value 1000 O3E8h The valid range is 360 lt Freq lt 10KHz Factory default is F 400Hz It is recommended that user program the re
9. et when configuring the registers The card can be programmed for use in combination but as previously stated the 3 4 wire channels are paired off with the same number channel A amp B and cannot be separated Channels programmed for 2 wire mode the A amp B outputs are set individually allowing for up to a total of 8 separate output channels l e the output Ch1 A will produce a voltage equivalent to the Va Vb voltage of a 2 wire system representing the Position in Ch 1 A Data Register and Ch1 B will produce the equivalent voltage representing the Position in Ch1 B Data Register North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 19 2005 75_DL1_A001_Rev_2 4 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 3 of 8 REGISTER MEMORY MAP O00 Postion ChTAData reads 090 Stas Suna ead 0B0_ Test 02 very TABLE TABLE 1 cont REGISTER BIT MAP o iw a J Status Test Status Signal Status Excitation Interrupt Enable Status Note 1 Values are rounded off Note 2 0 3 or 4 wire 1 2 wire Note 3 Signal status is not monitored for 2 wire mode Active channels Set the bit corresponding to each channel to be monitored during BIT testing in the Active Channel Register 1 active 0 not used Omitting this step will produce erroneous errors on unused channels causing false alarms hence unused channels will set faults i e status b
10. fax 4 19 2005 75_DL1_A001_Rev_2 4 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 8 of 9 Revision Page Revision Description of Change Engineer Date 1 Original FH 07 262001 1 4 Added memory map register map and connector information Added descriptions and FH BC 11 09 01 explanation for configuring 2 amp 4 wire Added code 05 3Khz to code table Modified title part number X gt L Revised reference added 115V 1 5 Removed reference made to VME in specifcations Changed M to E in spec amp PN Added FH BC 11 27 01 note in PN for J2 connections in PXI Chassis 1 6 See code list addendum for descriptions of code 50 and above GS 02 06 02 Part Number contact factory for other temperature requirements Updated PN Mech Formatting Automatically supports either 5V or 3 3V logic levels 1 7 For proper Soft Reset operation 1u lt pulsewidth lt 50ms GS 6 27 02 1 8 Update LARGE DL Graphic GS 6 27 02 1 9 Removed 2 13 5 volt reference option from spec and PN GS 6 28 02 2 1 PN Total number of A amp B channels gt Total number of channels A amp B deleted GS 1 28 4 2 2 Conducted cooled versions available As of June 1 2004 S4 CH4 and RLO OUT has been GS 7 714 moved from E22 and D22 to E18 and D20 respectively to support cPCI Geographical Addressing 2 3 Removes Wedgelock option from PN Conduction cooled version is NOT available
11. hose interrupts not used Refer to Table 2 Interrupt Status Registers When an interrupt is initiated via a problem failure the Interrupt Status Register can be interrogated by a read to identify which interrupt occurred Refer to Table 2 Register is latched when interrupt is generated and unlatched when read Note This register is typically read and cleared by the device driver Subsequent readings of this register will give clear status Outputs ON OFF Set the bit corresponding to each channel to be turned on to 1 in the Output On Off Register To turn OFF a channel set corresponding bit to 0 Both channels A amp B are controlled simultaneously i e in 2 wire mode the A amp B channel pairs are controlled concurrently Default Set to OFF 2 Wire or 3 4 Wire Mode Set the bit corresponding for each output channel pair A amp B in the 2 3 4 Wire Mode Register Setting the bit to 0 gt 3 4 wire mode Setting the bit to 1 gt 2 wire mode When setting a channel pair to 2 wire mode both channels A amp B of that number pair will be set for 2 wire Factory default is 3 4 wire mode Position Output Enter the position as a 2 s complement number in the corresponding Position Ch Data Register within the range of 1 00 lt Position lt 1 00 Isb In 3 4 wire mode position is written only to the A channel of that number pair The B channel register is ignored In 2 wire mode the A and B channels are set indep
12. its interrupts etc Note Signal status is not monitored in 2 wire mode Save Setup Writing 5555h to the Save Register will save the current setup This location will automatically clear to 0000h when save is completed within 5 seconds When save is elected all parameters are saved However any parameter can be changed at any time Saving is optional If not saved reenter parameters at each Power On To restore factory shipped parameters write AAAAh to the Save Register followed by System Reset Note After a SAVE or RESTORE poll the Save Register and do not perform any operation until word is at 0000h To restore factory shipped parameters write AAAAh to the Save register followed by system reset Note After a Save or Restore poll the Save register and do not perform any other operation until the Save register is equal to 0 Interrupt Enable Registers Interrupts can be enabled to report specific problems failures detected by the card The problem failures that generate these interrupts are D L Signal Loss D L Reference Loss D L Test Accuracy Error North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 19 2005 75_DL1_A001_Rev_2 4 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 4 of 9 Each external interrupt can be enabled individually This is accomplished by writing a 1 to the bit corresponding interrupts to the Interrupt Enable Register and a 0 to disable t
13. l vary directly with excitation With output voltages from 2 0 to 20 0Vrms 10 kQ min With output voltages from 20 to 28 0Vrms 15 kQ min Short circuit protected 2 max 2 0 to 28 Vrms Transformer isolated 360 Hz to 10Khz see code table 3 max 0 5 50 KQ min Interface implements a single Interrupt capability One of seven priority lines can be selected Automatically supports either 5V or 3 3V PCI bus 5 VDC 5 at 0 35 A 1A 3A peak 5VA Load on optional Reference 12 VDC 5 at 0 5 A C 0 C to 70 C E 40 C to 85 C See part number 55 C to 105 C 3U 3 94 height 4HP 0 8 width 6 3 depth 100mm x 20 3mm x 160mm Optional See part number 2 0 28Vrms programmable or 115Vrms fixed resolution 0 1Vrms Accuracy 2 360 Hz to 10 kHz 1 with 1 Hz resolution 10 max No load to full load 5VA max 40 min inductive 190mA RMS 2 26VAC 45mA RMS 115VAC Note Power is reduced linearly as the Reference Voltage decreases 4 19 2005 Cage Code OVGU1 631 567 1100 631 567 1823 fax www naii com e mail sales naii com 75_DL1_A001_Rev_2 4 Page 2 of 8 Principal of Operation LVDT Typically the primary is excited by an ac source causing a magnetic flux to be generated within the transducer Voltages are induced in the two secondaries with the magnitude varying with the position of the core Usually the secondaries are connected in series opposition causing a net output volt
14. quired frequency before setting the output voltage Optional Excitation Output Voltage Enter the output reference voltage as an integer in the Voltage Register Set the Excitation output voltage using the following formula Exc Out voltage register value V 10 Example For a Excitation output voltage of 7V gt register value 7 10 70 0046h The valid range is 0 0 or 2 0 lt V lt 28 0 with 0 1 volt resolution Factory default is V OV Note Units supplied with high voltage reference supply can only be set to 0 0 or 115 volts Power On Self Test POST The unit will initiate the D3 Test on Power On if POST is enabled and saved Enable by writing 1 or Disable by writing 0 to POST Register and then save setup Test Enable D2 Writing 1 to D2 of the Test register initiates automatic background BIT testing that compares the output of each channel with the commanded input to a testing accuracy of 0 2 FS Results can be read from the Test Status register A O deactivates this test This test is totally transparent to the user requires no external North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 19 2005 75_DL1_A001_Rev_2 4 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 5 of 9 programming has no effect on the standard operation of this card and can be enabled or disabled via the bus Outputs must be ON and Excitation supplied for test to function The ca
15. rd will every 30 seconds write 55h to the Test D2 verify register when D2 is enabled User can periodically clear to 00h and then after 30 seconds read the Test D2 verify register again to verify that background bit testing is activated In addition each Excitation input and Signal output is continually monitored Any failure triggers an Interrupt if enabled and the results are available in the Signal and Excitation Status Registers Note Signal Monitoring is not valid in 2 wire mode Test Enable D3 Writing 1 to D3 of the Test register initiates a BIT test that generates and tests 20 different inputs to a testing accuracy of 0 2 FS Test cycle takes about 45 seconds and results can be read from the Test Status register when D3 bit changes from 1 to 0 and if enabled an interrupt will be generated if a BIT failure is detected See nterrupt Register The testing can be terminated at any time by writing 0 to D3 bit of the Test Enable Register Excitation is required CAUTION During the D3 test the outputs are active Verify that changing those outputs will not effect connected equipment Status Test Check the corresponding bit of the Test Status Register for status of BIT Testing for each active channel A 1 means Accuracy OK 0 failed Channels that are inactive are also set to 0 Test cycle takes 2 seconds for accuracy error Any Test status failure transient or intermittent will latch the Test
16. re or three four wire The transformation ratio TR same for each pair of outputs sets the maximum output voltage with relation to the excitation voltage TR Max Output Voltage Excitation Voltage Use of a ratio metric design eliminates errors caused by excitation voltage variations The outputs are stable with temperature and switching spikes are not noticeable A watchdog timer is provided to monitor the processor To simplify logistics Part number S N Date code amp Rev are located in nonvolatile memory locations Major diagnostics are incorporated to offer substantial improvements to system reliability because the user is alerted within 5 seconds to channel malfunctions This approach reduces bus traffic because the Status registers do not require constant polling See Programming Instructions for further details The D2 test initiates automatic background BIT testing that compares the output of each channel against the commanded input to a test accuracy of 0 2 FS and monitors each Output and Excitation A failure triggers an Interrupt if enabled and results are available in Status Registers Testing requires no external programming has no effect on the standard operation of this card and can be enabled or disabled via the bus The D3 test starts a BIT test that generates and tests 20 different positions to a testing accuracy of 0 2 FS Results can be read from Status Registers External reference is required Testing requires
17. vel PCB Rev level DSP Rev level FPGA Rev level Interface FPGA Software PCI Programming North Atlantic Industries Inc 631 567 1100 631 567 1823 fax 4 19 2005 75_DL1_A001_Rev_2 4 110 Wilbur Place Bohemia NY 11716 www naii com e mail sales naii com Cage Code OVGU1 Page 6 of 9 This section provides programmers the information needed for developing drivers other than those supplied The following information resides in the PCI configuration registers Device ID 7541 hex Vendor ID 15AC hex Rev 01 hex Subsystem ID 000115AC hex Base Address Assigned by the PCI BIOS Interrogate the PCI BIOS for this information Required Address space 1K for each card CONNECTOR J2 Exc Out Lo CH4 B Lo Exc Out Hi CH4 B Hi N C CH4 A Hi N C CH4 A Lo Exc 4 A B Lo N C Exc 4 A B Hi N C N C CH3 B Lo N C CH3 B Hi N C CH3 A Hi N C CH3 A Lo Exc 3 A B Lo N C Exc 3 A B Hi N C N C CH2 B Lo N C CH2 B Hi N C CH2 A Hi N C CH2 A Lo Exc 2 A B Lo N C Exc 2 A B Hi N C N C CH1 B Lo N C CH1 B Hi Exc 1 A B Lo CH1 A Hi Exc 1 A B Hi CH1 A Lo TABLE 3 As of June 1 2004 S4 CH4 and RLO OUT has been moved from E22 and D22 to E18 and D20 respectively to support cPCI Geographical Addressing P1 Front Connector DC37P Mate DC37S Designation i Designation i Designation CH1 A Lo Exc 2 A B Lo 1 CH4 A Hi CH1 B Hi Exc
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