GR-MCC-C_user_manual
Contents
1. HDR2X25 J5b HDR2X25 J4b aX 72 IM R71 PT1000 HDR2X25 J5a HDR2X25 ere PJ 0024 SMT 2 x R103 C30 eee 8 x x 10k 1000 moo g a a seat ag gt gt HDR2X3 8 1 1 1 9 5 5 5 5 5 A be 8 3 8 8 6 5 5 ee or on E R61 249k LM1086CM sn SQ eo 5 R63 1 a 82 10 C74 10 5 EER x R65 249K i R68 OR 8 R64 40k 22 ong RM oS C20 C26 R105 R28 OR E 08 ORT 100p 58 100p 100p R25 OR 110100 2 p 2 000 810058 000 SED 18 eR fic o5 5 2595 5 25 2 5 250808 858208 380 85 29 100r g Cor Ji 8 s 85 Ton B e U18 o 1 01 D 5 5 LM1086CM Beg 552 055595 252. 9 2 1 peche setis Eres 9 2 2 Listor 16 2 3 List of 0 16 2 4 16 25 Note about pin Numbering of expansion 5 17 2 6 15 07 Test 18 LIST TABLES Table 2 1 List of 2 1 10 Table 2 2 J1 SPW O interface connections 0 4 0 1410 2 2 0 11 Table 2 3 42 SPW 1 interface connections 0 110 2 1 rennen 11 Table 2 4 CANBUS interface 1 1 11 Table 2 5 J4a GPIO Connector 2 04 4 aerae nn 12 Table 2 6 GPIO Connector 0 40 1 emen 12 Table 2 7 J5a Analog Power
3. 13 Table 2 8 J5b Analog Power 13 Table 2 9 46 POWER External Power 14 Table 2 10 7 FPGA JTAG Connector 0 0 0 0 0 10 14 Table 2 11 Expansion connector J8 004 0 0 01 15 Table 2 12 J9 PIO Header Pin 2 2 1 101 en enne 16 Table 2 13 Expansion connector J10 nennen nns 16 Table 2 14 List and definition of 0 00 0 nennen 17 Table 2 15 List and definition of eene rennen 17 Table 2 16 List and definition of PCB 17 Table 2 17 List of Test 20 00 0 nn nnn 18 LIST FIGURES Figure 1 1 GR MCC C Development 2 4 2 6 Figure 1 2 GR MCC C Block 2 2 7 Figure 2 1 PCB Top VIEW 5 A ere EN ere ee ER 19 Figure 2 2 GR MCC C Assembly Photo 20 Aeroflex Gais
4. GAISLER User Manual Pin Name Comment 1 DINO Data In ve 6 DINO Data In ve 2 SINO Strobe In ve 7 SINO Strobe In ve 3 SHIELD Inner Shield 8 SOUTO Strobe Out ve 4 SOUTO Strobe Out ve 9 DOUTO Data Out ve 5 DOUTO Data Out ve Table 2 2 J1 SPW 0 interface connections Pin Name Comment 1 DIN1 Data In ve 6 DIN1 Data In ve 2 SIN1 Strobe In ve 7 SIN1 Strobe In ve 3 SHIELD Inner Shield 8 SOUT1 Strobe Out ve 4 SOUT1 Strobe Out ve 9 DOUT1 Data Out ve 5 DOUT1 Data Out ve Table 2 3 2 SPW 1 interface connections Pin Name Comment 1 CANO H CAN Dominant High Interface 0 6 CANO L CAN Dominant Low Interface 0 2 7 GND Ground 3 CANSHD Shield Ground 8 GND Ground 4 nc no connection 9 CAN1_L CAN Dominant Low Interface 1 5 CAN1_H CAN Dominant High Interface 1 Table 2 4 CANBUS interface connections Aeroflex Gaisler AB August 2013 Rev 2 2 GAISLER Aeroflex Gaisler AB 11 GR MCC C ProAsic3E Development Board FUNCTION FPGA pin CONNECTOR FPGA pin FUNCTION 3 3V 1 B 2 3 3V DGND 3 4
5. GAISLER GR MCC C ProAsic3E Development Board User Manual GAISLER 2 2 2013 08 28 LEX 2 GR MCC C ProAsic3E Development Board GAISLER User Manual Information furnished by Aeroflex Gaisler AB is believed to be accurate and reliable However no responsibility is assumed by Aeroflex Gaisler AB for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Aeroflex Gaisler AB Aeroflex Gaisler AB tel 46 31 7758650 Kungsgatan 12 fax 46 31 421407 EROF LEX 411 19 G teborg sales gaisler com M Sweden www aeroflex com gaisler GAISLER Copyright 2013 Aeroflex Gaisler All information is provided as is There is no warranty that it is correct or suitable for any purpose neither implicit nor explicit Aeroflex Gaisler AB August 2013 Rev 2 2 EROFLEX 3 GR MCC C ProAsic3E Development Board GAISLER User Manual TABLE OF CONTENTS 1 INTRODEUGTIO RN 5 1 1 reU 5 1 2 Actel ProASIC3 FPGAS 4000040 sna as 7 1 3 tec NR 7 7 1 5 21 7 2 INTERFACES AND
6. ep 12 58 D ox 7 1069 TSOP2 54 52 16 5 16 o U48 55 95 E 047 ri 5 ES 2 SW ms mEx 198 0 00107454 0958880 Tg pracy 808 R R22 R7 gy2 24 S Est B ELS 288 5 53 5 u E zou gt x i RE 8 5383838 8 88888 85 n 2 BE gef OO t 0 0000000 00068006 x 5 333333 R69 ee ES 80 le ee R94 54 SWDP 8 es em NF 8 amp 6 J7 HDR5X2_SHROUDED J1 GAISLER August 2013 Rev 2 2 Top Vi 2 Figure 2 Aeroflex Gaisler AB 20 GR MCC C ProAsic3E Development Board GAISLER User Manual PT 5 gt SST LER gt Sri apii VEM Bo 2 S Wo 980111 LT wand Aeroflex Gaisler AB August 2013 Rev
7. RT Radiation Tolerant FT Fault SEU Single Event Upset SPW Spacewire Aeroflex Gaisler AB August 2013 Rev 2 2 EROFLEX 9 GR MCC C ProAsic3E Development Board GAISLER User Manual 2 INTERFACES AND CONFIGURATION 2 1 List of Connectors Name Function Type Description J1 SPW 0 9 5 female LVDS connections for Spacewire Interface 0 J2 SPW 1 9 5 female LVDS connections for Spacewire Interface 1 J3 1 MDMSP male Dual CAN bus interface J4a GPIO 2 25 0 1 header digital signals GPIO 29 0 30 signals J4b GPIO 2x25pin 0 1 header GPIO digital signals GPIO 59 30 30 signals 5 ANALOG 2 25 0 1 header ADC inputs 24 signals J5b ANALOG 2x25pin 0 1 header Assorted ADC 3 signals and Power Connections J6 POWER IN 2 1mm center ve DC power input connector J7 JTAG 2 5 0 1 header JTAG programming amp DSU interface J8 MEM AMP 5177984 5 PIO GPIO connector 52 signals 120 pin 0 8mm pitch J9 PIO 2x10pin 0 1 header connections compatible with GR Accessories J10 GEN AMP 5177984 2 GPIO connector 32 signals 60 pin 0 8mm pitch Table 2 1 List of Connectors Aeroflex Gaisler August 2013 Rev 2 2 10 GR MCC C Development Board
8. 30 32 34 36 38 40 42 44 46 48 50 5 GND EXT GND EXT EXT2 3V3 3V3 5V 5V DGND DGND DGND DGND 7V_EXT1 7V_EXT1 7V_EXT1 HEATER HEATER HEATER HEATER 1000 2 1000 1 1000 0 DGND DGND DGND Table 2 8 56 Analog Power Connector User Manual August 2013 Rev 2 2 LEX 13 GR MCC C ProAsic3E Development Board GAISLER User Manual Pin Name Comment VE Inner Pin nom 9V typically TBD A VE GND Outer Pin Return Table 2 9 J6 POWER External Power Connector Pin Name Comment 1 TCK JTAG TCK 2 DGND Ground 3 TDO JTAG TDO 4 nc no connect 5 TMS JTAG TMS 6 VREF 3 3V 7 VPUMP Programming Voltage 8 TRSTN JTAG TRSTN 9 TDI JTAG TDI 10 DGND Ground Table 2 10 J7 FPGA JTAG Connector Aeroflex Gaisler August 2013 Rev 2 2 GAISLER Aeroflex Gaisler AB 14 GR MCC C ProAsic3E Development Board FUNCTION FPGA CONNECTORPIN FPGA pin FUNCTION DGND 1 120 DGND 14 118 2 119 R18 015 012 V21 3 118 T20 PIO13 010 020 4 117 W20 PIO11 PIO8 22 5 116 022 9 3V3 6 115 3V3 DGND 7 114 6 021 8 113 119 PIO7 PIO4 R19 9 112 19 5 PIO2 P17 10 111 P17 PIOS PIOO P21 11 110 T22 PIO1 3V3 12 109 3V3 DGND 13 108 DGND GPIO56 A16 14 107 D18 GPIO57 GPIO54 14 15 106 G14 55 52 C13 16 105 C12 GPIO53
9. GPIO50 A14 17 104 D16 51 3V3 18 103 3V3 DGND 19 102 DGND GPIO48 A13 20 101 B13 GPIO49 GPIO46 F15 21 100 G12 47 44 12 22 99 13 45 GPIO42 E15 23 98 H12 GPIO43 3V3 24 97 3V3 DGND 25 96 DGND GPIO40 F12 26 95 A12 GPIO41 GPIO38 E12 27 94 G13 GPIO39 GPIO36 H11 28 93 G11 GPIO37 GPIO34 G9 29 92 G10 GPIO35 3V3 30 91 3V3 DGND 31 90 DGND GPIO32 F10 32 89 F11 GPIO30 F8 33 88 F9 GPIO31 GPIO28 E10 34 87 E11 GPIO29 GPIO26 E8 35 86 E9 GPIO27 3V3 36 85 3V3 DGND 37 84 DGND 24 011 38 83 7 GPIO25 GPIO22 D9 39 82 D10 GPIO23 GPIO20 D7 40 81 08 GPIO21 GPIO18 D5 41 80 D6 19 3V3 42 79 3V3 DGND 43 78 44 n 45 76 46 75 47 74 3V3 48 73 3V3 DGND 49 50 71 51 70 52 69 53 68 3V3 54 67 3V3 DGND 55 66 DGND 56 65 57 64 58 63 59 62 DGND 60 61 DGND Table 2 11 Expansion connector J8 Pin out User Manual August 2013 Rev 2 2 GAISLER Aeroflex Gaisler AB 15 GR MCC C ProAsic3E Development Board FUNCTION FPGA pin CONNECTOR FPGA pin FUNCTION PIOO P21 1 2 T22 PIO1 PIO2 R22 3 4 P17 4 R19 5 6 P19 PIOS PIO6 U21 7 8 T21 PIO7 22 9 10 022 PIO9 010 020 11 12 120 11 1012 21 13 14 W20 PIO13 14 T18 15 16 R18 PIO15 3 3V 17 18 3 3V DGND 19 20 DGND FUNCTION DGND DGND 3 3V GPIO58 GPIO60 GPIO62 GPIO64 GPI
10. 08 qi ca 5 3058 624252 5855 58 TE28F640J3 m 5 E Ly 4 JP3 Bq 8005 2x 88 200558 0 08 085 B e 1 zs 14 xa 880 10 2388 TOn BE 25 gt 08 07 100 100 069 TSOP2 54 058 R79 y 528 019 2 01 She 1 1086 TU 87 x 52 10k RIO ssp 5 08 9 88 8 1004 Pr 100n 2 o 199070532 p 25 m 8 00 i 5 580 85 100 5 Ug gk gt R78 Re n oc 100 005 6 Dis 06 ue Tok is a CY7C1069_TSOP2 54 058 Res jE a R75 2 DB 8 e E LED 1k ee LM1086CM 03 R100 s 02 C62 LED SS3H10 SS3H10 T 1291 5 LE LEE 010 558 LED s 008 00 dB es 95 haga gS 5 98 prox NS 1069 TSOP2 54 158 88 588885 5888 BS cm co co 85 10 16 gon 16 jn 18 190 0 e y T 4 25 Heo Mios 581 5 ol e 48 28 85 180 25 18 88 BB
11. 15 List and definition of Switches Name Function Type JP1 CONFIG 2x3 pin 0 1 Header Header to configure ground power connections JP2 RESET 2 pin 0 1 Header Header for external RESET switch JP3 DSU BREAK 2 pin 0 1 Header Header for external 050 BREAK switch Aeroflex Gaisler Table 2 16 List and definition of PCB Jumpers for details refer to schematic August 2013 Rev 2 2 17 GR MCC C ProAsic3E Development Board GAISLER User Manual 2 5 Note about pin Numbering of expansion connectors To make it feasible for users to define peripherals connected to from the FPGA and to implement mezzanine boards GPIO and PIO signals from the FPGA are connected to a 120 AMP connector 5 177984 5 J8 60 pin connector 5 177984 2 10 the board Table 2 11 and Table 2 13 list these signals and the pin numbers for these connectors Figure 2 1 shows the pin numbering scheme as implemented on the expansion connector 28 s 2 8 2 880 o g g R40 a a E R C78 1009 1009 1000 CH 1004 v Ton 150 Tn m U40 a m AD7891 44 5 2722 5
12. E11 GPIO29 GPIO28 E10 5 6 DGND GPIO27 E9 7 8 8 26 9 10 GPIO25 GPIO24 D11 11 12 DGND GPIO23 D10 13 14 D9 GPIO22 DGND 15 16 D8 GPIO21 GPIO20 D7 17 18 DGND GPIO19 D6 19 20 D5 GPIO18 DGND 21 22 C11 GPIO17 GPIO16 C10 23 24 DGND GPIO15 C7 25 26 14 27 28 C4 GPIO13 GPIO12 B11 29 30 DGND GPIO11 B10 31 32 B9 GPIO10 DGND 33 34 B8 GPIO9 GPIO8 B7 35 36 DGND GPIO7 B6 37 38 B5 GPIO6 DGND 39 40 B4 GPIO5 4 41 42 11 43 44 10 2 45 46 9 GPIO1 GPIOO A8 47 48 3 3V 49 50 3 3V Table 2 5 J4a GPIO Connector 3 3V 1 2 3 3 3 4 E14 GPIO59 58 16 5 6 57 018 7 8 16 56 9 10 G14 55 54 14 14 12 53 C12 13 14 C13 GPIO52 DGND 15 16 D16 GPIO51 GPIO50 14 17 18 49 13 19 20 13 48 21 22 G12 47 46 15 23 24 45 13 25 26 12 44 27 28 H12 GPIO43 GPIO42 E15 29 30 DGND GPIO41 A12 31 32 F12 GPIO40 DGND 33 34 G13 GPIO39 GPIO38 E12 35 36 DGND GPIO37 G11 37 g 38 H11 6 39 40 G10 5 4 G9 41 42 DGND 11 43 44 10 2 45 46 9 GPIO31 GPIO30 F8 47 48 DGND 3 3V 49 50 3 3 Table 2 6 J4b GPIO Connector User Manual August 2013 Rev 2 2 GAISLER Aerofl
13. 0 2727 85289 90 85 D A 8 s HH A FW 100 888 WY of 8 Z C57 R72 Toon 1 100n R80 E4 2 29 R77 2 6 6 6 5 6 5 5 6 5 5 6 6 a T 20 10k 10k 188 R85 gt R88 L 10k 10k d C50 CA 700 Ob oe 100 R102 51 ex C56 2 S 100 55 5 c C45 8 RS Tn L R84 e R81 3 2085521 1242444 2 10k 873 C49 0 E 20 57585958595 FR 88 79 gt 8 420 Sg H H H H 61 31 8 CONNECTOR 60X2 J CONNECTOR 30x2 Cy 58 Mj TU on 3 o R 59 100 100n if 8238 TS oma E agn Figure 2 1 Mezzanine Connector Pin Number Ordering Please note that this pin ordering does not match exactly the pin ordering which you will find on the Tyco part datasheets for the Mezzanine board mating connectors The reason for this is explained in more detail in the Technical Note RD 4 Therefore please take care when designing your own mezzanine boards to take account of this pin ordering If there is any confusion or you have any doubts please do not hesitate to contact in
14. O66 GPIO68 GPIO70 GPIO17 DGND 3 3V GPIO15 GPIO13 GPIO11 GPIO9 GPIO7 GPIO5 GPIO3 GPIO1 DGND Table 2 12 J9 PIO Header Pin out FPGA CONNECTORPIN FPGA pin 1 60 2 59 3 58 4 57 5 56 6 55 7 54 8 53 9 52 10 51 11 50 16 12 49 E14 17 13 48 014 015 14 47 B16 B17 15 46 15 18 16 45 18 19 17 44 B19 B20 18 43 B15 C10 19 42 20 41 21 40 22 39 C6 C4 23 38 B11 B10 24 37 B9 B8 25 36 B7 B6 26 35 B5 B4 27 34 B3 A11 28 33 A10 A9 29 32 A8 an 31 FUNCTION DGND DGND 3 3V GPIO59 GPIO61 GPIO63 GPIO65 GPIO67 GPIO69 GPIO71 GPIO16 DGND 3 3V 14 GPIO12 GPIO10 GPIO8 GPIO6 GPIO4 GPIO2 GPIOO DGND Table 2 13 Expansion connector J10 Pin out User Manual August 2013 Rev 2 2 16 GR MCC C ProAsic3E Development Board GAISLER User Manual 2 2 List of Oscillators Name Function Description X1 CLK_MAIN Main oscillator for FPGA 25 0MHz SMD oscillator soldered to board X2 CLK_USER 8 pin DIL socket for User installed oscillator 3 3V DIL8 type Table 2 14 List and definition of Oscillators 2 3 List of Switches Name Function Description S1 RESET Push button RESET switch S2 DSUBREAK Push button DSUBREAK switch 53 PIO 7 0 8 pole DIP SWITCH for GPIO signals 7 0 54 PIO 15 8 8 pole DIP SWITCH for GPIO signals 15 8 2 4 List of Jumpers Table 2
15. S JTAG DSU DUAL CAN SPW SPW VF VF VF VF Figure 1 2 GR MCC C Block Diagram The interface connectors on the front of the edge of the board provide Dual CAN interface MDM9P connector Two Spacewire interfaces MDMS9S connectors JTAG DSU interface 10 pin connector Aeroflex Gaisler AB August 2013 Rev 2 2 EROFLEX 7 GR MCC C ProAsic3E Development Board GAISLER User Manual The interface connectors on the back of the edge of the board provide e 60 GPIO pins on two 2x25 pin 0 1 standard headers e Analog connections two 2x25 pin 0 1 standard headers 27 ADC input channels 12 bit ADC Assorted power Connections 2 1mm connector for external DC power supply 7V to 12V DC centre 1 2 Actel ProASIC3 FPGAs The ProASIC3 low cost low power FPGA family offers a breakthrough in power price performance density and features for today s most demanding high volume applications The ProASIC3 low cost low power FPGAs are based on nonvolatile flash technology and support 15 000 to 3 000 000 gates and up to 620 high performance 1 RT ProASIC3 FPGAs offer designers of space flight hardware a radiation tolerant RT reprogrammable nonvolatile logic integration vehicle Unlike all of Actel s other radiation tolerant space flight FPGAs which use antifuse programming technology devices the RT ProASIC3 family use flash cells to store configuration information Technical
16. ex Gaisler AB FUNCT 12 GR MCC C ProAsic3E Development Board ION FPGA pin CONNECTOR FPGA pin FUNCTION DGN DGN DGN DGN DGN DGN DGN DGN DGN DGN DGN DGN DGN DGN DGN DGN DGN DGN DGN DGN DGN DGN DGN DGN DGN A 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 O O U O UO U U 0 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 _7 ADC3 6 ADC3 5 ADC3 4 ADC3 3 ADC3 2 ADC3 1 ADC3 0 ADC2 7 ADC2 6 ADC2 5 ADC2 4 DGND ADC2 3 ADC2 2 ADC2 1 ADC2 0 ADC1 7 ADC1 6 ADC1 5 ADC1 4 ADC1 3 ADC1 2 ADC1 1 ADC1 0 Table 2 7 J5a Analog Power Connector 5V COM 1m 5V COM 3 GND EXT 5 7V_EXT2 7 7V_EXT2 9 3v3 11 5V 13 5V 15 5V 17 DGND 19 DGND 21 DGND 23 7V_EXT1 25 7V_EXT1 27 7V_EXT1 29 HEATER 31 HEATER 33 HEATER 35 HEATER 1000 2 39 1000 1 41 1000 0 43 ADCO 7 45 ADCO 6 47 ADCO 5 49 BR N 10 12 14 16 18 20 22 24 26 28
17. fo pender ch Additional dimensional data or Gerber layout information can be provided if required to aid in the layout of the User s mezzanine board Aeroflex Gaisler AB August 2013 Rev 2 2 GAISLER 2 6 List of Test Points 18 GR MCC C ProAsic3E Development Board User Manual Name Name Comment TP1 5V_COM 5V TP2 5V_LVDS 5V TP3 5V_CAN 5V TP4 5V_Digital 5V TP5 5V 5V TP6 VREF 2 5V TP7 CLK_MAIN 25MHz 3 3V TP8 ROMRYBY Busy Ready signal of Flash 9 3V3 3 3V TP10 1V5 1 5V TP11 DGND OV TP12 DGND OV TP13 DGND OV TP14 DGND OV TP15 RESETn High low during RESET TP16 AUXRESETn High low when 51 pressed TP17 PRSTn High low when 51 pressed TP18 DSU_BREAK Low high when S2 pressed TP19 CLK_USER User Defined Oscillator Frequency Table 2 17 List of Test Points Aeroflex Gaisler AB August 2013 Rev 2 2 User Manual GR MCC C ProAsic3E Development Board 19
18. ler August 2013 Rev 2 2 GAISLER REVISION HISTORY 4 GR MCC C ProAsic3E Development Board User Manual Revision Date Page Description 0 0 DRAFT 2009 10 09 All New document draft 0 1 2010 06 02 All Text corrections to draft document 2 0 2010 05 29 All Revised for version 2 0 of GR MCC C Board 2 1 2011 09 06 7 13 Clarified Nominal input voltage to voltage regulators is range 7 to 12V DC 14 15 Changed GPIO13 11 in Table 2 11 and GPIO16 17 in Table 2 13 back to logic ordering acc Correction in rev 2 1 of PCB 2 1a 2012 01 26 Table 2 1 Corrected 80 pin to 60 pin 2 2 2013 08 28 RD 4 4 Added reference document and information on expansion connector pin 82 5 numbering Aeroflex Gaisler August 2013 Rev 2 2 EROFLEX 5 GR MCC C ProAsic3E Development Board GAISLER User Manual 1 INTRODUCTION 1 1 This document describes the GR MCC C Development Board The GR MCC C FPGA board has been created to support early development and fast prototyping of digital computer designs The board incorporates a footprint for an Actel ProASIC3E or RT ProASIC3E field programmable gate array or a corresponding socket and is capable of operating stand alone or in conjunction with other analogue boards To provide more I O possibilities additional mezzanine and accessory boards are available As the board is based on a program
19. mable FPGA device the actual functionality depends mainly on the logic which is designed and implemented in the FPGA device Figure 1 1 GR MCC C Development Board Features e Double Euro style PCB 233 5mm x 160mm form factor e Actel ProASIC3 FPGA in FGG484 package A3PE3000 FGG484 optional socket for FPGA Aeroflex Gaisler AB August 2013 Rev 2 2 EROFLEX 6 GR MCC C ProAsic3E Development Board GAISLER User Manual e One bank of SRAM memory on board 2Mword x 40bits 2nd bank as option not normally fitted e bank of 16 Mbit 8Mbyte x 8 bit 3 3V Flash PROM memory on board e Dual LVDS transceivers with opto isolation for dual SpaceWire interfaces Dual CAN transceivers 15011898 with opto isolation e Quad 12 bit ADC devices providing 32 analogue input channels of which 5 input channels are dedicated for on board supply current and temperature monitoring JTAG interface for programming and debug link On board linear regulators supply for 5V 3 3V 1 5V generated from a nom input e Optional mezzanine connector compatible with existing GR Mezzanine boards e Optional PIO expansion connector compatible with existing GR Accessory boards Power on reset with optional reset button e On board 25 MHz oscillator e Suitable for Single Event Upset SEU testing e LEON3 and LEON3FT compatible FPGA template designs available ANALOG POWER CONNECTIONS GPIO CONNECTIONS PIO CONNECTION
20. notes and further information can be found from the Actel website www actel com 1 3 References RD 1 J GR MCC C schematic pdf Schematic RD 2 GR MCC C assy drawing pdf Assembly Drawing RD 3 bom pdf Bill of Materials RD 4 GR MEZZ Technical Note Technical Note about Mezzanine connectors 1 4 Handling ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES This unit contains sensitive electronic components which can be damaged by Electrostatic Discharges ESD When handling or installing the unit observe appropriate precautions and ESD safe practices When not in use store the unit in an electrostatic protective container or bag When configuring the jumpers on the board or connecting disconnecting cables ensure that the unit is in an unpowered state 1 5 Abbreviations ADC Analog to Digital Converter FPGA Field Programmable Gate Array DIL Dual In Line Aeroflex Gaisler August 2013 Rev 2 2 LEX 8 GR MCC C ProAsic3E Development Board GAISLER User Manual ESD Electro Static Discharge FP Front Panel FT Fault Tolerant GPIO General Purpose Input Output Input Output IP Intellectual Property LVDS Low Voltage Digital Signalling MII Media Independent Interface MUX Multiplexer PCB Printed Circuit Board PROM Programmable Read only Memory SRAM Static Random Access Memory CAN Controller Area Network LVDS Low Voltage Digital Signalling JTAG Joint Test Action Group
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