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1. 1 The lo current sunk must always respect the absolute maximum rating and the sum of lig I O ports and control pins must not exceed lyss 2 The lio current sourced must always respect the absolute maximum rating and the sum of ljo I O ports and control pins must not exceed lypp 58 83 Figure 19 Typ Vo at Vpp 1 8 V standard ports Vol V lot mA MS30302V2 DoclD022344 Rev 5 Ly STM8TL52x4 STM8TL53x4 Electrical parameters Figure 20 Typ Vo at Vpp 3 0 V standard ports Vol V MS30303V2 Figure 21 Typ Vpp Vou at Vpp 1 8 V standard ports VDD VOH V lou mA MS30304V2 d DoclD022344 Rev 5 59 83 Electrical parameters STM8TL52x4 STM8TL53x4 Figure 22 Typ Vpp Vou at Vpp 3 0 V standard ports 5 5 g gt 0 2 4 6 8 10 12 14 16 18 lou mA MS30305V2 Figure 23 Typ Vpp Vou at Vpp 1 8 V ProxSense TX ports ES 8 0 01 02 03 04 05 06 07 08 09 1 lou mA MS30306V2 60 83 DoclD022344 Rev 5 Ly STM8TL52x4 STM8TL53x4 Electrical parameters Figure 24 Typ Vpp Vou at Vpp 1 8V ProxSense RX ports Vou V 0 01 02 03 04 05 06 07 08 09 1 lou mA MS30307V2 d DoclD022344 Rev 5 61 83 Electrical parameters STM8TL52x4 STM8TL53x4 62 83 NRST pin The NRST pin input driver is CMOS A permanent pull up is present which is the same as
2. y life augmented STM8TL52x4 STM8TL53x4 8 bit ultra low power touch sensing microcontroller with 16 Kbytes Flash ProxSense timers USART SPI I2C Features Operating conditions Operating power supply 1 65 V to 3 6 V Temperature range 40 C to 85 C Low power features Datasheet production data I UFQFPN48 7x7 mm TSSOP20 UFQFPN28 4x4 mm 4 low power modes Wait Active halt with S AWU 1 pA Active halt with ProxSense 10 pA with scan every 200 ms Halt 0 4 pA Dynamic power consumption 150 uA MHz Fast wakeup from Halt mode 4 7 us Ultra low leakage per I O 50 nA Advanced STM8 Core Harvard architecture with 3 stage pipeline Max freq 16 MHz 16 CISC MIPS peak Memories Up to 16 Kbytes of Flash program including up to 2 Kbytes of data EEPROM Error correction code ECC Flexible write and read protection modes In application and in circuit programming Data EEPROM capability 4 Kbytes of static RAM Clock management Internal 16 MHz factory trimmed RC Internal 38 kHz low consumption RC driving both the IWDG and the AWU Reset and supply management Ultra low power ultra safe power on reset power down reset Interrupt management Nested interrupt controller with software priority control Up to 22 external interrupt sources VOs Up to 23 with 22 mappable on external interrupt vectors VOs with programmable input pull ups high si
3. 0x00 5345 PXS RX5CSSELR ProxSense receiver sampling capacitor 0x00 x selection register 0x00 5346 PXS RX6CSSELR ProxSense receiver sampling capacitor 0x00 selection register 0x00 5347 PXS RX7CSSELR ProxSense receiver sampling capacitor 0x00 selection register 0x00 5348 PXS RX8CSSELR ProxSense receiver sampling capacitor 0x00 selection register 0x00 5349 PXS RX9CSSELR ProxSense receiver sampling capacitor 0x00 selection register 0x00 534A to Reserved area 6 bytes 0x00 534F Ly DocID022344 Rev 5 35 83 Memory and register map STM8TL52x4 STM8TL53x4 Table 7 General hardware register map continued Address Block Register label Register name EEE status 0x00 5350 PXS RXOEPCCSELR ProxSense receiver electrode parasitic 0x00 n compensation capacitor selection register 0x00 5351 PXS RX1EPCCSELR POSE RENO parasitic 0x00 compensation capacitor selection register 0x00 5352 PXS RX2EPCCSELR ProxSense receiver electrode parasitic 0x00 z compensation capacitor selection register 0x00 5353 PXS RX3EPCCSELR OT onse receiver elecirode parasite 0x00 compensation capacitor selection register 0x00 5354 PXS_RX4EPCCSELR ProxSense receiver electrode parasitig 0x00 aye compensation capacitor selection register 0x00 5355 PXS_RX5EPCCSELR Proxsense receiver old parasitic 0x00 m compensation capacitor selection register 0x00 5356 PXS RX6EPCCSELR SN fucelvel EE Co
4. Interrupt controller The STM8TL5xx4 devices feature a nested vectored interrupt controller e Nested interrupts with 3 software priority levels e 22interrupt vectors with hardware priority e Up to 22 external interrupt sources on 10 vectors e TRAP and RESET interrupts Memory The STM8TL5xx4 devices have the following main features e 4Kbytes of RAM e The EEPROM is divided into two memory arrays see the STM8TL5xxx reference manual RM0312 for details on the memory mapping 16 Kbytes of low density embedded Flash program including up to 2 Kbytes of data EEPROM Data EEPROM and Flash program areas can be write protected independently by using the memory access security mechanism MASS 64 option bytes one block of which 5 bytes are already used for the device Error correction code is implemented on the EEPROM DoclD022344 Rev 5 13 83 Product overview STM8TL52x4 STM8TL53x4 3 6 3 7 3 7 1 3 7 2 3 8 14 83 Low power modes To minimize power consumption the product features three MCU low power modes e Wait mode CPU clock stopped selected peripherals at full clock speed e Active halt mode When wakeup time is programmed in the AWU unit the CPU and peripheral clocks are stopped The RAM content is preserved When a ProxSense acquisition is ongoing the wakeup is on ProxSense interrupts the CPU and the other peripheral clocks are stopped e Halt mode CPU and peripheral
5. DoclD022344 Rev 5 75 83 Package information STM8TL52x4 STM8TL53x4 10 4 76 83 samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity TSSOP20 package information Figure 37 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch package outline PIN 1 IDENTIFICATION ion SEATING PLANE GAGE PLANE YA ME V3 1 Drawing is not to scale Table 43 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 200 0 0472 A1 0 050 0 150 0 0020 0 0059 A2 0 800 1 000 1 050 0 0315 0 0394 0 0413 b 0 190 0 300 0 0075 0 0118 C 0 090 0 200 0 0035 0 0079 6 400 6 500 6 600 0 2520 0 2559 0 2598 6 200 6 400 6 600 0 2441 0 2520 0 2598 E1 4 300 4 400 4 500 0 1693 0 1732 0 1772 e 0 650 0 0256 DocID022344 Rev 5 Ky STM8TL52x4 STM8TL53x4 Package information Table 43 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch package mechanical data continued millimeters inches Symbol Min Typ Max Min Typ Max L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 8 0 8 aaa 0 100 0 0039
6. 1 Values in inches are converted from mm and rounded to four decimal digits Figure 38 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch package footprint 0 25 Go 20 0 25 7 10 4 40 I 1 lh N LJ 10 biag 0 65 YA FP V1 1 Dimensions are expressed in millimeters Ly DoclD022344 Rev 5 77 83 Package information STM8TL52x4 STM8TL53x4 Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 39 TSSOP20 marking example package top view Product identification 6TL53F4Pb Date code Revision code Ijeu 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity Pin 1 identifier MSv37478V1 d 78 83 DoclD022344 Rev 5 STM8TL52x4 STM8TL53x4 Part numbering 11 d Part numbering 1 Table 44 Ordering information scheme Example Device type STM8 T STM8 microcontroller family Product type T Touch Sensing Device family L L low power
7. Sub family type 5 Projective capacitive sub family Peripheral set 2 Light 3 Basic Pin count C 48 pins G 28 pins F 20 pins Program Memory Size 4 16 Kbytes Package type U UFQFPN P TSSOP Temperature range 6 40 C to 85 C Shipping TR Tape and Reel Blank Tray DoclD022344 Rev 5 For a list of available options e g memory size package and orderable part numbers or for further information on any aspect of this device please go to www st com or contact the ST Sales Office nearest to you 79 83 STM8 development tools STM8TL52x4 STM8TL53x4 12 12 1 12 1 1 80 83 STM8 development tools Development tools for the STM8 microcontrollers include the very low cost debugger and programmer tool ST Link supported by a complete software tool package including C compiler assembler and integrated development environment with high level language debugger In addition the STM8 is to be supported by a complete range of tools including starter kits evaluation boards and a low cost in circuit debugger programmer Software tools STM8 development tools are supported by a complete free software package from STMicroelectronics that includes ST Visual Develop STVD IDE and the ST Visual Programmer STVP software interface STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8 A free version that outputs
8. including Data EEPROM up to 2 Kbytes 0x00 BFFF MS19123V1 1 Refer to Table 7 for an overview of hardware register mapping to Table 6 for details on I O port hardware registers and to Table 8 for information on CPU SWIM debug module controller registers d 26 83 DoclD022344 Rev 5 STM8TL52x4 STM8TL53x4 Memory and register map Table 5 Flash and RAM boundary addresses Memory area Size Start address End address RAM 4 Kbytes 0x00 0000 0x00 OFFF Flash program memory 16 Kbytes 0x00 8000 0x00 BFFF Table 6 VO Port hardware register map Address Block Register label Register name Hara 0x00 5000 PA ODR Port A data output latch register 0x00 0x00 5001 PA IDR Port A input pin value register OxXX 0x00 5002 Port A PA DDR Port A data direction register 0x00 0x00 5003 PA CR1 Port A control register 1 0x00 0x00 5004 PA CR2 Port A control register 2 0x00 0x00 5005 PB ODR Port B data output latch register 0x00 0x00 5006 PB IDR Port B input pin value register OxXX 0x00 5007 Port B PB DDR Port B data direction register 0x00 0x00 5008 PB CR1 Port B control register 1 0x00 0x00 5009 PB CR2 Port B control register 2 0x00 0x00 500A to Reserved area 5 bytes 0x00 500E 0x00 500F PD ODR Port D data output latch register 0x00 0x00 5010 PD IDR Port D input pin value register OxXX 0x00 5011 Port D PD DDR Port
9. volte x x X HS X X PortB2 P oxSense transmitter 10 46 PB3 PXS TXM WO TC x x x us x X PortBa P oxSense transmitter 11 47 PBA4 PXS TX12 U O TC x x X HS X X PortB4 P oxSense transmitter 12 48 PBsipxs TX13 U O TC x x X HS X X Portas P oxSense transmitter 13 1 The PAO SWIM pin is in input pull up during the reset phase and after reset release 2 Apull up is applied to PA2 PA3 and PB1 during the reset phase These three pins are input floating after reset release 3 At power up the PAS NRST pin is a reset input pin with pull up To be used as a general purpose pin PA5 it can be configured only as output open drain or push pull not as a general purpose input Refer to Section Configuring NRST PA5 pin as general purpose output in the STM8TL5xxx reference manual RM0312 4 Notavailable for STM8TL52xx d DoclD022344 Rev 5 25 83 Memory and register map STM8TL52x4 STM8TL53x4 5 Memory and register map Figure 7 Memory map Ox00 0000 RAM 4 Kbytes 0x00 OFFF including Stack 0x00 47FF 0x00 4800 Option Bytes 0x00 48FF 0x00 4900 Reserved 0x00 4924 0x00 4925 Unique ID 0x00 4930 0x00 4931 Reserved 0x00 49FF 0x00 5000 GPIO and 0x00 57FF Peripheral registers 0x00 5800 Reserved 0x00 7EFF 0x00 7F00 CPU SWIM Debug ITC 0x00 7FFF registers 0x00 8000 Interrupt vectors 0x00 807F 0x00 8080 Low density Flash program memory up to 16 Kbytes
10. 3 V They are given only as design guidelines and are not tested Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 8 Figure 8 Pin loading conditions p STM8TL5xx4 PIN BODE DoclD022344 Rev 5 43 83 Electrical parameters STM8TL52x4 STM8TL53x4 9 1 5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 9 Figure 9 Pin input voltage _ STM8TL5xx4 PIN 2 WS 9 2 Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 13 Voltage characteristics Symbol Ratings Min Max Unit Vpp Vss External supply voltage including Vpp and VppioY 0 3 4 0 Receiver channel pins PXS Rx0a Rx9b Vss 0 3 irs Pins used as General purpose I O Vss 0 3 ad Vin Input voltage on PBO 7 and PDO 79 Pins used as transmitter channel pins PXS_Tx0 to Vgg 0 3 Exo PXS Tx15 i Input voltage on any PA pins Vss 0 3 4 0 Electrostatic discharge see Absolute ma
11. Rpy see Table 31 on page 56 Subject to general operating conditions for Vpp and Ta unless otherwise specified Table 33 NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit Vii mRsT NRST input low level voltage Vss 0 8 ViuNRST NRST input high level voltage z 1 4 lt Vpp y Vownrs7 NRST output low level voltage lo 72 mA o RPU NRST NRST pull up equivalent resistor 30 45 60 KO VENRsT NRST input filtered pulse 50 toP NRST NRST output pulse width 20 ns VNF NRST NRST input not filtered pulse 300 B 1 Data based on characterization results not tested in production 2 The Rpy pull up equivalent resistor is based on a resistive transistor 3 Data guaranteed by design not tested in production The reset network shown in Figure 26 protects the device against parasitic resets The user must ensure that the level on the NRST pin can go below the Vi max level specified in Table 33 Otherwise the reset is not taken into account internally Figure 25 Typical NRST pull up resistance Rpy vs Vpp Pull up resistance KO VDD V MS30311V2 DoclD022344 Rev 5 Ly STM8TL52x4 STM8TL53x4 Electrical parameters d Figure 26 Recommended NRST pin configuration EXTERNAL RSTIN Filt INTERNAL RESET RESET e ilter p CIRCUIT TO 0 1pF STM8TL5xx4
12. Symbol Min Typ Max Min Typ Max A 0 500 0 550 0 600 0 0197 0 0217 0 0236 A1 0 000 0 050 0 0000 0 0020 D 3 900 4 000 4 100 0 1535 0 1575 0 1614 D1 2 900 3 000 3 100 0 1142 0 1181 0 1220 E 3 900 4 000 4 100 0 1535 0 1575 0 1614 E1 2 900 3 000 3 100 0 1142 0 1181 0 1220 L 0 300 0 400 0 500 0 0118 0 0157 0 0197 L1 0 250 0 350 0 450 0 0098 0 0138 0 0177 T 0 152 0 0060 b 0 200 0 250 0 300 0 0079 0 0098 0 0118 e 0 500 0 0197 DoclD022344 Rev 5 al STM8TL52x4 STM8TL53x4 Package information 1 Values in inches are converted from mm and rounded to 4 decimal digits Figure 35 UFQFPN28 28 lead 7x7 mm 0 5 mm pitch ultra thin fine pitch quad flat package recommended footprint 3 30 _ gt 0 50 A A 4 30 3 30 0 30 Y Y AOBO FP V2 1 Dimensions are expressed in millimeters Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 36 UFQFPN28 marking example package top view Product identification Revision code Pin 1 identifier MSv37479V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering d
13. Ta 40 to 85 C no floating I O unless otherwise specified Measured from interrupt event to interrupt vector fetch To get twy for another CPU frequency use twu FREQ tyy 16 MHz 1 5 TEREG T16 MHz The first word of interrupt routine is fetched 5 CPU cycles after ty 4 Tested in production Figure 13 Typ Ipp Hait VS Vpp fepu 2 MHz and 16 MHz Is Halt 16 mHz mA 0 0009 0 0008 0 0007 0 0006 0 0005 0 0004 0 0003 0 0002 0 0001 2 2 24 2 6 Vpp V 2 8 3 32 34 3 6 MS19192V1 1 Typical current consumption measured with code executed from Flash 50 83 DoclD022344 Rev 5 d STM8TL52x4 STM8TL53x4 Electrical parameters Current consumption of on chip peripherals Measurement made for fyasTER from 2 MHz to 16 MHz Table 22 Peripheral current consumption Symbol Parameter Typ Vpp 3 0 V nt IDD TIM2 TIM2 supply current 9 IDD TIM3 TIM3 supply current 9 IDD TIM4 TIM4 timer supply current 4 IDD USART USARTsupply current 7 IDD sP1 SPI supply current 4 Ipprc 12C supply current 4 1 Data based on a differential lnn measurement between all peripherals off and a timer counter running at 16 MHz The CPU is in Wait mode in both cases No IC OC programmed no I O pin toggling Not tested in production 2 Data based on a differential lnn measurement between the on chip peripheral when k
14. The reset network shown in Figure 26 protects the device against parasitic resets The user must ensure that the level on the NRST pin can go below the Vi max level specified in Table 33 Otherwise the reset is not taken into account internally For power consumption sensitive applications the capacity of the external reset capacitor can be reduced to limit the charge discharge current If the NRST signal is used to reset the external circuitry the user must pay attention to the charge discharge time of the external capacitor to meet the reset timing conditions of the external devices The minimum recommended capacity is 10 nF DoclD022344 Rev 5 63 83 Electrical parameters STM8TL52x4 STM8TL53x4 9 3 9 Communication interfaces Serial peripheral interface SPI The parameters given in Table 34 are derived from tests performed under ambient temperature fyAsTER frequency and Vpp supply voltage conditions summarized in Section 9 3 1 on page 45 unless otherwise specified Refer to I O port characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO Table 34 SPI characteristics Symbol Parameter Conditions Min Max Unit Master mode 0 8 fsck SPI clock frequency MHz Vise Slave mode 0 8 SOK SPI clock rise and fall time Capacitive load C 30 pF 30 f SCK tsunss NSS setup time Slave
15. l this Figure 28 SPI timing diagram slave mode and CPHA 1 NSS input CPHA 1 y N CPOL 0 if Ke 5 h h i o 1 1 1 1 7 S cme weg KP MEN uso mos inso TRE ta S0 gt l v SO NOH PEE dis MISO i OUTPUT Lj MSH OUT Bie OUT i sou OUT tsu SI K La gt MOSI usw GUT mon IN i BITI IN isn N ai14135 1 Measurement points are done at CMOS levels 0 3 Vpp and 0 7 Vpp d DoclD022344 Rev 5 65 83 Electrical parameters STM8TL52x4 STM8TL53x4 Figure 29 SPI timing diagram master mode High NSS input 1 tsc 3 CPHA 0 E CPOL 0 i 4 i I U 1 amp CRHA 0 I ia e I SCK Output OO 32 LT O LI CPHA 1 i l i t 1 w SCKH fees 0 SCK tsu MI PRE tw SCKL PAG T 1 iS ER E TEN INPUT pire E sa I l tt th M gt HAGN M MSBOUT OUT MSBOUT BIT OUT LSBOUT O OUT OUTPUT ai14136V2 66 83 1 Measurement points are done at CMOS levels 0 3 Vpp and 0 7 Vpp d DoclD022344 Rev 5 STM8TL52x4 STM8TL53x4 Electrical parameters Inter IC control interface I2C Subject to general operating conditions for Vpp fyasTER and TA unless otherwise specified The STM8TL5xx4 12C interface meets the requirements of the Standard I2C communication protocol described in the following table with the restrictions mentioned below Ref
16. 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 I STMSTL5xx4 block diagram oc rassa re k er sr ek Rer hem R RR NEE 11 STM8TL53 48 pin UFQFPN package pinout liliis 18 STM8TL53G4U6 28 pin UFQFPN package pinout llli 19 STM8TL52G4U6 28 pin UFQFPN package pinout llle 20 STM8TL53F4P6 TSSOP20 20 pin package pinout is EE EE Ee ee ee 21 STM8TL52F4P6 TSSOP20 20 pin package pinout EE EE EE Ee ee ee 21 Memory Mape irera N EA EE EE EE EE EE EE N 26 Pin loading conditions EE R KR ee ee ee nr ee ee ee ee ee 43 Pin input voltage iiec EE OR er PaaS Bade ER EE EE 44 Power supply scheme EE EE EE EE Ee lle 46 IDD RUN VS VDD fopy 16 MHZ OR OE a ea Goes EROR a ee ER e e 48 IDD Wait VS VDD fcPU 16 MHZ uos e eR bee DEERE kee DE Ee T DUE EE 49 TYD I DD Halt VS VDD fepu 2 MHz and 16 MHZ rann 50 Typical HSI frequency vs VD ES SE SS SS SE Se Se SS de ee ed se ee ee 52 Typical HSI accuracy vs temperature VDD 2 23 VY 53 Typical LSI frequency vs Vpp 2 62 ESE SS Se Se de ee de See de ee see 54 Typical pull up resistance Rpy vs Vpp with V2 Vss arv vr eee 56 Typical Vj and Vin VS VDD iese ES ES SS eee 57 Typ Vo at Vpp 1 8 V standard porsi narr narrer rank 58 Typ Vo at Vpp 3 0 V standard ports iss ES SS ES SS ES Ee ee ee 59 Typ Vpp Vou at Vpp 1 8 V sta
17. 300 450 Ipp wait current in all peripherals off HA Wait mode HSI internal RC osc fuasreR 8 MHz 380 600 TMASTER 16 MHz 500 800 1 Based on characterization results unless otherwise specified 2 Maximum values are given for TA 40 to 85 C DoclD022344 Rev 5 d STM8TL52x4 STM8TL53x4 Electrical parameters Figure 12 Ipp wait VS Vpp fepy 16 MHz IDD Wait HSI 16 MHz mA VDD V MS19199V2 1 Typical current consumption measured with code executed from RAM Ly DoclD022344 Rev 5 49 83 Electrical parameters STM8TL52x4 STM8TL53x4 Table 21 Total current consumption in Halt mode and Active halt mode Vpp 1 65 V to 3 6 VO 2 Symbol Parameter Conditions Typ Max Unit Supply current in Active halt LSI RC osc TA 40 C to 25 C 1 2 HA DD AH AH mode at 38 kHz T 85 C 14 32 pA Supply current during Ipp wuProx Wakeup time from Active halt fcpu 16 MHz 2 mA mode using HSI 3 Wakeup time from Active B WU AH halt mode to Run mode Topic Ja MP 6 5 ps TA 40 C to 25 C 0 4 1 2 pa Ipp Halt Supply current in Halt mode D Ta 85 C 1 2 5 HA Supply current during i IDD WUFH wakeup time from Halt mode fcpu 16 MHz a ma Wakeup time from Halt mode tWU Halt io Bun mode fepu 16 MHz 4 6 5 US N a Data based on characterization not tested in production
18. 4 Interrupt controller EE EE 00 0 13 3 5 ek EL OR koniki n ARES RS REAR Rea N FEE 13 3 6 Low power modes ES tenet ee ee 14 3 7 Voltage regulators 25 ike ee EE dex hen vee dee ci tole dd ete Vee RES RR EE 14 3 7 1 Dual mode voltage regulator ee EE Se EE ee eee 14 3 7 2 ProxSense voltage regulator SE Ee else 14 3 8 Clock Control is le Ee stp eo te Re CI d AG URN Rod d rct 14 3 9 System configuration controller EE ES EE Ee ee 15 3 10 Independent watchdog iis sk EE EE ER ER EE EE RE ee 15 3 11 Window watchdog se ese Hel aa ira ae a Ro aa a dee GA re o se RE 15 3 12 Auto wakeup counter ES EG EG ee 15 3 13 General purpose and basic timers EES SEE eee 15 3 14 BEEPEP si EER rt dr pec e epa ka 16 mo USART ieke EER Ed dE o CR a RE deo DA ER Rodi OER EE Re A d 16 ALONE NP 16 cd rm 16 3 18 ProxSense ia ga hastas ete ec ober ED DANG 17 3 19 TouchSensing dedicated library available upon request 17 4 Pin description ces x dude dog er ea e acl a RR dele Rc A RC aede 18 5 Memory and register map x x x cece eee RR RR RR RR RR RR ee 26 6 Interrupt vector mapping x x seks se ek kk aa ER RR Rae RR kke ee 38 2 83 DocID022344 Rev 5 Ly STM8TL52x4 STM8TL53x4 Contents 10 11 12 d Option bytes lt Kaa se SE oca e some je cde e e ace CR ERU eU ade i a 40 Unique ID 4 exe N RANGE RUE N 42 Electrical parameters RR RR R
19. 85 bytes 0x00 7F5F 0x00 7F60 CFG CFG GCR Global configuration register 0x00 Mes e Reserved area 15 bytes 0x00 7F70 ITC SPR1 Interrupt Software priority register 1 OxFF 0x00 7F71 ITC SPR2 Interrupt Software priority register 2 OxFF 0x00 7F72 ITC SPR3 Interrupt Software priority register 3 OxFF 0x00 7F73 ITC SPR ITC SPR4 Interrupt Software priority register 4 OxFF 0x00 7F74 v ITC SPR5 Interrupt Software priority register 5 OxFF 0x00 7F75 ITC SPR6 Interrupt Software priority register 6 OxFF 0x00 7F76 ITC SPR7 Interrupt Software priority register 7 OxFF 0x00 7F77 ITC SPR8 Interrupt Software priority register 8 OxFF 0x00 7F78 to Reserved area 2 bytes 0x00 7F79 0x00 7F80 SWIM SWIM CSR SWIM control status register 0x00 0x00 7F81 to Reserved area 15 bytes 0x00 7F8F 0x00 7F90 DM BK1RE Breakpoint 1 register extended byte OxFF 0x00 7F91 DM BK1RH Breakpoint 1 register high byte OxFF 0x00 7F92 DM BK1RL Breakpoint 1 register low byte OxFF 0x00 7F93 DM BK2RE Breakpoint 2 register extended byte OxFF 0x00 7F94 DM BK2RH Breakpoint 2 register high byte OxFF 0x00 7F95 DM DM BK2RL Breakpoint 2 register low byte OxFF 0x00 7F96 DM CR1 Debug module control register 1 0x00 0x00 7F97 DM CR2 Debug module control register 2 0x00 0x00 7F98 DM CSR1 Debug module control status register 1 0x10 0x00 7F99 DM CSR2 Debug module control status register 2 0x00 0x00 7F9A DM ENFCTR Enable function register OxFF 1 Refer to Table 7 General hardware register ma
20. 9 29 2 599 9 award LSI frequency MHz VDD V MS30310V2 9 3 7 Memory characteristics TA 7 40 to 85 C unless otherwise specified RAM characteristics Table 27 RAM and hardware registers me ooms Dum D VRM Data retention mode 1 Halt mode or Reset 1 Minimum supply voltage without losing data stored in RAM in Halt mode or under Reset or in hardware registers only in Halt mode Guaranteed by characterization not tested in production Flash memory characteristics Table 28 Flash program memory Symbol Parameter Conditions Min Typ Max Unit Operating voltage E VoD all modes read write erase ImasTER 16 MHz 1 65 E Y Programming time for 1 or 64 bytes block G 6 ms erase write cycles on programmed byte t AM Programming time for 1 to 64 bytes block R 3 ms write cycles on erased byte Ta 25 C Vpp 3 0 V Iprog Programming erasing consumption 0 7 mA TA 25 C Vpp 1 8 V 1 Data based on characterization results not tested in production d 54 83 DoclD022344 Rev 5 STM8TL52x4 STM8TL53x4 Electrical parameters d Table 29 Program memory endurance and retention Parameter Conditions Min Typ Max Unit Endurance TA 40 to 85 C 10 kcycles Data retention 10 kcycles at T4 85 c 3001 5 Years 1 Data based on characterization results not tested in
21. 9 3 5 Supply current characteristics Total current consumption The MCU is placed under the following conditions s AI VO pins in input mode with a static value at Vpp or Vss no load e All peripherals are disabled except if explicitly mentioned Subject to general operating conditions for Vpp and Ta Table 19 Total current consumption in Run mode Symbol Parameter Conditions Typ Max 9 Unit fMASTER 2MHz 0 4 0 6 Code executed from fmaster 4 MHz 0 55 0 7 RAM fuasTER 8 MHz 0 9 12 Supply fMASTER 16 MHz 1 6 240 IDD Run Current in mA Run mode fMASTER 7 2 MHz 0 56 0 7 Code executed from fvasTER 4 MHz 0 88 1 8 Flash fuAsTER 8 MHz 1 5 2 5 fMASTER 16 MHz 2 8 3 5 1 Based on characterization results unless otherwise specified 2 All peripherals off Vpp from 1 65 V to 3 6 V HSI internal RC oscillator fopy fMASTER 3 Maximum values are given for T4 7 40 to 85 C 4 Tested in production Ly DoclD022344 Rev 5 47 83 Electrical parameters STM8TL52x4 STM8TL53x4 48 83 Figure 11 Ipp RUN VS V pnp fcpu 16 MHz 25 C 3 uium 90 C 29 sil 40 C T 28 E N 2 7 I z 2 6 7 25 L c 24 amp a 23 22 2 1 2 1 5 2 2 5 3 Voo V MS30314V2 1 Typical current consumption measured with code executed from Flash Table 20 Total current consumption in Wait mode Symbol Parameter Conditions Typ Max Unit fMASTER 2 MHz 260 400 Supply CPU not clocked fmaster 4 MHz
22. CH1 VO FT X X X HS X X Port A1 Ge nrs SPI clock PA2 SPI SCK Timer 3 4 1 4 USART CK UO I EFT I X X X HS X X PortA2 USART channel TIM3 CH2 synchronous 2 clock SPI master in PA3 SPI_MISO slave out 5 2 5 USART_TX UO 1 ET 1 X X X HS X X PotA3 EER I2C SDA2 USART transmit I2C data SPI master out PA4 SPI MOSI slave in 6 3 6 USART RY UO 1 ET 1 X X X HS X X Port A4 I2C SCL USART receive 12C clock Digital 7 4 7 VDD S power supply 22 83 DoclD022344 Rev 5 Ky STM8TL52x4 STM8TL53x4 Pin description Table 4 STM8TL5xx4 pin description continued Pin no Input Output Alternate function c 7 S co 5 Oo O q e o ZI A Pin name 2 D 9 GE n o o o S 2 o dd a a x LiuL Oo aa 2 E 16 cz Default Remap o e 72 o z R T G LL LL o o s 2 5 t x c D gt I 8 5 8 lvss S Digital ground ProxSense voltage 9 6 9 PXS VREG S a gulatog External decoupling capacitor 10 7 10 PASINRSTO VO TC HS X X Reset dc output ProxSense BASE TRIG external trigger L input 418 CLK CC UO 1 ET 1 X x X HS X X Port AG CLK clock output 12 9 PAZIPXS REIN WO TC x x x us X X Port A7 oXSense antenna input 13 10 11 PXS RX0a PXS RXOa ProxSense receiver 0a ProxSense 14 PXS RX0b PXS RXOb receiver 0b 1
23. D data direction register 0x00 0x00 5012 PD CR1 Port D control register 1 0x00 0x00 5013 PD CR2 Port D control register 2 0x00 Ky DoclD022344 Rev 5 27 83 Memory and register map STM8TL52x4 STM8TL53x4 Table 7 General hardware register map Address Block Register label Register name pia status 0x00 5050 FLASH CR1 Flash control register 1 0x00 0x00 5051 FLASH CR2 Flash control register 2 0x00 0x00 5052 Flash FLASH PUKR Flash Program memory unprotection register 0x00 0x00 5053 FLASH DUKR Data EEPROM unprotection register 0x00 0x00 5054 FLASH IAPSR Flash in application programming status register OxXO 0x00 5055 to Reserved area 73 bytes 0x00 509D 0x00 509E SYSCFG SYSCFG RMPCR1 Remapping control register 1 0x00 0x00 509F Reserved area 1 byte 0x00 50A0 EXTI CR1 External interrupt control register 1 0x00 0x00 50A1 EXTI CR2 External interrupt control register 2 0x00 0x00 50A2 EXTI CR3 External interrupt control register 3 0x00 m ITC EXTI 0x00 50A3 EXTI SR1 External interrupt status register 1 0x00 0x00 50A4 EXTI SR2 External interrupt status register 2 0x00 0x00 50A5 EXTI CONF External interrupt port select register 0x00 0x00 50A6 WEE WFE_CR1 WFE control register 1 0x00 0x00 50A7 WFE_CR2 WFE control register 2 0x00 0x00 50A8 to Reserved area 8 bytes 0x00 50AF 0x00 50B0 Bem RST CR
24. Figure 5 STM8TL53F4P6 TSSOP20 20 pin package pinout TIM3 TRIG PXS TX8 HS PBO c 1e BEEP SWIM HS PAO c 2 TIM3 CH1 SPI NSS HS PA1 3 TIM3 CH2 USART CK SPI SCK HSJPA2 4 I2C SDA USART TX SPI MISO HS PA3 c4 5 I2C SCL USART RX SPI MOSI HS PA4 ls VDD 7 VSS Cis PXS VREG 9 NRST HS PA5 c 10 Dirt to ooo PD6 HS PXS_TX6 TIM3_CH1 PDS HSYPXS TX5 TIM2 CH2 PDA HSYPXS TX4 TIM2 CH1 PD1 HSYPXS TX1 PDO HSYPXS TXO PXS RX7a PXS RX6a PXS RX2a PXS RX1a PXS RX0a HS corresponds to 20 mA high sink source capability Power supply pins must be correctly decoupled with capacitors near the pins Please refer to the power supply circuitry details in Section 9 3 2 Power supply on page 46 and the STM8TL5xxx reference manual RM0312 Section 6 Power supply Figure 6 STM8TL52F4P6 TSSOP20 20 pin package pinout TIM3 TRIG HS PBO BEEP SWIM HS PAO TIM3 CH1 SPI NSS HS PA1 TIM3 CH2 USART CK SPI SCK HS PA2 I2C SDA USART TX SPI MISO HS PA3 I2C SCL USART RX SPI MOSI HSJPA4 VDD VSS PXS VREG NRST HS PA5 OON O OC A OON o 20 19 18 17 16 15 14 13 12 11 PD6 HS PD5 HS TIM3 CH1 TIM2 CH2 PD4 HS TIM2_CH1 PD1 HSYPXS TX1 HI PDO HS PXS TXO E3 PXS RX7a PXS RX6a La PXS RX2a PXS RX1a PXS RX0a EE EE H
25. Reset control register 0x00 0x00 50B1 RST SR Reset status register 0x01 1 0x00 50B2 to Reserved area 14 bytes 0x00 50BF 0x00 50CO CLK CKDIVR Clock divider register 0x00 0x00 50C1 to Reserved area 2 bytes 0x00 50C2 CLK 0x00 50C3 CLK PCKENR1 Peripheral clock gating register 1 0x00 0x00 50C4 CLK PCKENR2 Peripheral clock gating register 2 0x01 0x00 50C5 CLK CCOR Configurable clock control register 0x10 0x00 50C6 to Reserved area 12 bytes 0x00 50D2 28 83 DoclD022344 Rev 5 Kys STM8TL52x4 STM8TL53x4 Memory and register map Table 7 General hardware register map continued Address Block Register label Register name EEE status 0x00 50D3 WWDG CR WWDG control register WWDG Ox7F 0x00 50D4 WWDG WR WWDG window register 0x00 50D5 to Reserved area 11 bytes 0x00 50D7 0x00 50E0 IWDG KR IWDG key register OxXX 0x00 50E1 IWDG IWDG PR IWDG prescaler register 0x00 0x00 50E2 IWDG RLR IWDG reload register OxFF 0x00 50E3 to Reserved area 13 bytes 0x00 50EF 0x00 50F0 AWU CSR AWU control status register 0x00 0x00 50F1 AWU AWU APR AWU asynchronous prescaler buffer register Ox3F 0x00 50F2 AWU TBR AWU timebase selection register 0x00 0x00 50F3 BEEP BEEP CSR BEEP control status register Ox1F 0x00 50F4 to Reserved area 268 bytes 0x00 51FF 0x00 5200 SPI CR1 SPI control register 1 0x00 0x00 5201 SPI CR2 SPI control r
26. Yes Yes Yes 0x00 8044 16 Reserved 0x00 8048 0x00 804C 17 Reserved 0x00 804F 18 Reserved 0x00 8050 for Mer PE NT Yes Yes 0x00 8054 trigger break interrupt 20 mig EED OMIE Yes Yes 0x00 8058 interrupt Sr md HOE Ee ven Yes Yes 0x00 805C trigger break interrupt 38 83 DoclD022344 Rev 5 Ly STM8TL52x4 STM8TL53x4 Interrupt vector mapping Table 9 Interrupt mapping continued Wakeu Wakeup Wakeup Wakeup IRQ Source EG irom Fr from from Wait from Wait Vector No block P Active halt WFI WFE address mode 1 mode mode mode 22 nua IMS capture compare Yes Yes 0x00 8060 interrupt 23 Reserved 0x00 8064 24 0x00 806B 25 eo s Yes Yes 0x00 806C trigger interrupt SPI TX buffer empty 26 SPI RX buffer not empty Yes Yes Yes Yes 0x00 8070 error wakeup interrupt USART transmit data a7 UsART Ee epe 2 Yes Yes 0x00 8074 transmission complete interrupt USART received data ready overrun error 28 USART idle line detected parity Yes Yes 0x00 8078 error global error interrupt 29 I2C 12C interrupt Yes Yes Yes Yes 0x00 807C 1 The Low power wait mode is entered when executing a WFE instruction in Low power run mode In WFE mode the interrupt is served if it has been previously enabled After processing the interrupt the processor goes back to WFE mode When the interrupt is configured as a wakeup event the CPU wakes up and res
27. a file and replay later exhaustive record display not real time e 2 types of viewers Variable viewer Real time waveforms oscilloscope like graphs TouchPoint viewer Association of 2 variables one on the X axis one on the Y axis C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment making it possible to configure and control the building of your application directly from an easy to use graphical interface Available toolchains include e Cosmic C compiler for STM8 One free version that outputs up to 32 Kbytes of code is available For more information see www cosmic software com e lARembedded workbench The C compiler for STM8 which is included in the toolset is free for up to 8Kbytes of code For more information see www iar com e Haisonance C compiler for STM8 One free version that outputs up to 32 Kbytes of code For more information see www raisonance com e STM8 assembler linker Free assembly toolchain included in the STVD toolset which allows you to assemble and link your application source code Programming tools During the development cycle ST Link provides in circuit programming of the STM8 Flash microcontroller on your application board via the SWIM protocol For production environments programmers will include a complete range of gang and automated programming solutions from third party tool developers
28. already supplying programmers for the STM8 family DoclD022344 Rev 5 81 83 Revision history STM8TL52x4 STM8TL53x4 13 82 83 Revision history Table 45 Document revision history Date 14 Oct 2011 Revision 1 Changes Initial release 04 Apr 2012 Added STM8TL52G4 STM8TL52F4 STM8TL53F4 part numbers Added Figure 14 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Updated Figure 31 and Table 41 Added TSSOP20 package 06 Aug 2013 Removed STICE references and edited the text in Section 3 2 Development tools and Section 12 STM8 development tools In Table 7 General hardware register map changed the Reset status from 0x00 to 0x01 on CLK PCKENR2 row split address block Ox00 5055 to 0x00 509F into Ox00 5055 to 0x00 509D with Reserved 0x00 509E with SYSCFG and 0x00 509F with Reserved added a footnote to RST SR Reset status value updated CLK CCOR Reset status value to 0x10 Updated description of OPTO in Table 11 Option byte description Updated Vin Max values in Table 13 Voltage characteristics Added Section 9 3 4 ProxSense Regulator Voltage Removed ACCusi pxs rows from Table 25 HSI PXS oscillator characteristics and removed former Figure 17 Typical HSI PXS frequency vs VDD Added trog and Iprog Max values to Table 28 Flash program memory Re
29. logic arithmetic functions 8 bit by 8 bit multiplication 16 bit by 8 bit and 16 bit by 16 bit division Bit manipulation Data transfer between stack and accumulator push pop with direct stack access Data transfer using the X and Y registers or direct memory to memory transfers I DoclD022344 Rev 5 STM8TL52x4 STM8TL53x4 Product overview 3 2 3 3 3 4 3 5 d Development tools Development tools for the STM8 microcontrollers include e The ST Link very low cost professional tool to debug and program e The STVD high level language debugger including C compiler assembler and integrated development environment e The STVP Flash programming software e The STM STUDIO real time and non intrusive graphical interface used to probe application variables and data The STM8 also comes with starter kits evaluation boards and low cost in circuit debugging programming tools Single wire data interface SWIM and debug module The debug module with its single wire data interface SWIM permits non intrusive real time in circuit debugging and fast memory programming The Single wire interface is used for direct access to the debugging module and memory programming The interface can be activated in all device operation modes The non intrusive debugging module features a performance close to a full featured emulator Beside memory and peripherals also CPU operation can be monitored in real time by means of shadow registers
30. mode 4 X tMASTER trnss NSS hold time Slave mode 80 twsckH 2 Master mode SCK high and low time 105 145 tw SCKL J fyasTER 8 MHz fgck 4 MHz t 2 Master mode 30 su Mi Data input setup time tsu SI Slave mode 3 t 2 Master mode 15 AMI 3 Data input hold time ns tn si Slave mode 0 taso PB Data output access time Slave mode 3X tMASTER tuis so Data output disable time Slave mode 30 tso 2 Data output valid time Slave mode after enable edge 60 2 Master mode l tv MO Data output valid time after enable edge 20 tno Slave mode after enable edge 15 2 Data output hold time Master mode MO after enable edge 1 7 1 Parameters are given by selecting 10 MHz I O output frequency 2 Values based on design simulation and or characterization results and not tested in production 3 Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data 4 Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi Z 64 83 DoclD022344 Rev 5 d STM8TL52x4 STM8TL53x4 Electrical parameters Figure 27 SPI timing diagram slave mode and CPHA 0 NSS input A ka tesck tsu NSS I thss CPHA 0 VA O me 5 CPOL 0 a E X 9 CPHA 0 CPOL 1 f MISO de OUTPUT MSB OUT BIG OUT LSB OUT tus BIT1 IN en Y IN MSv37680V1 MOSI INPUT
31. of the external components used d DoclD022344 Rev 5 67 83 Electrical parameters STM8TL52x4 STM8TL53x4 9 3 10 68 83 Figure 30 Typical application with IC bus and timing diagram Vpp Vpp _ 4 7kQ 4 7kQ i 1000 SDA e NW STM8TL5xx4 PC BUS 1009 SCL NW REPEATED START 7 tsu STA i Iw STO STA SDA N x X a NI m START START lt X SDA r SDA I tsu SDA h SDA 1 STOP para i 1 i i i a NNN fs 1 na RE 1 Lea 1 T md EE EC ig e thsTA twscLH w scLL tusen tsc tsu STO 1 Measurement points are done at CMOS levels 0 3 x Vpp and 0 7 x Vpp EMC characteristics Susceptibility tests are performed on a sample 36 basis during product characterization Functional EMS electromagnetic susceptibility Based on a simple running application on the product toggling 2 LEDs through I O ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs e ESD Electrostatic discharge positive and negative is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 61000 4 2 standard e FTB A burst of fast transient voltage positive and negative is applied to Vpp and Vss through a 100 pF capacitor until a functional disturbance occurs This test conforms with the IEC 61000 4
32. pad solder joint life 3 There is an exposed die pad on the underside of the UFQFPN package It is recommended to connect and solder this back side pad to PCB ground DoclD022344 Rev 5 71 83 I Package information STM8TL52x4 STM8TL53x4 Table 41 UFQFPN48 48 lead 7x7 mm 0 5 mm pitch ultra thin fine pitch quad flat package mechanical data 1 Values in inches are converted from mm and rounded to 4 decimal digits millimeters inches Symbol Min Typ Max Min Typ Max A 0 500 0 550 0 600 0 0197 0 0217 0 0236 A1 0 000 0 020 0 050 0 0000 0 0008 0 0020 D 6 900 7 000 7 100 0 2717 0 2756 0 2795 6 900 7 000 7 100 0 2717 0 2756 0 2795 D2 5 500 5 600 5 700 0 2165 0 2205 0 2244 E2 5 500 5 600 5 700 0 2165 0 2205 0 2244 L 0 300 0 400 0 500 0 0118 0 0157 0 0197 T 0 152 0 0060 0 200 0 250 0 300 0 0079 0 0098 0 0118 e 0 500 0 0197 ddd 0 080 0 0031 Figure 32 UFQFPN48 48 lead 7x7 mm 0 5 mm pitch ultra thin fine pitch quad flat package recommended footprint A 7 30 7 30 Y HOOO a o H c o A00000006000 6 20 dOOOOOE lt HO00000000008 se AOOOODDDODOOOE e ng a 0 50 5 80 gt kag A0B9 FP V2 1 Dimensions are expressed in millimeters 72 83 DoclD022344 Rev 5 I STM8TL52x4 STM8TL53x4 Package inform
33. 00 0x00 5234 PEDE USART CR1 USART control register 1 0x00 0x00 5235 USART CR2 USART control register 2 0x00 0x00 5236 USART CR3 USART control register 3 0x00 0x00 5237 USART CR4 USART control register 4 0x00 0x00 5238 to Reserved area 18 bytes 0x00 524F 30 83 DoclD022344 Rev 5 Ky STM8TL52x4 STM8TL53x4 Memory and register map Table 7 General hardware register map continued Address Block Register label Register name ea 0x00 5250 TIM2 CR1 TIM2 control register 1 0x00 0x00 5251 TIM2 CR2 TIM2 control register 2 0x00 0x00 5252 TIM2 SMCR TIM2 slave mode control register 0x00 0x00 5253 TIM2 ETR TIM2 external trigger register 0x00 0x00 5254 TIM2 IER TIM2 interrupt enable register 0x00 0x00 5255 TIM2 SR1 TIM2 status register 1 0x00 0x00 5256 TIM2 SR2 TIM2 status register 2 0x00 0x00 5257 TIM2 EGR TIM2 event generation register 0x00 0x00 5258 TIM2 CCMR1 TIM2 capture compare mode register 1 0x00 0x00 5259 TIM2 CCMR2 TIM2 capture compare mode register 2 0x00 0x00 525A TIM2 CCER1 TIM2 capture compare enable register 1 0x00 0x00 525B P TIM2 CNTRH TIM2 counter register high 0x00 0x00 525C TIM2 CNTRL TIM2 counter register low 0x00 0x00 525D TIM2 PSCR TIM2 prescaler register 0x00 0x00 525E TIM2 ARRH TIM2 auto reload register high OxFF 0x00 525F TIM2 ARRL TIM2 auto reload register low OxFF 0x00 5260 TIM
34. 00 0x00 532B PXS RX5CNTRL ProxSense counter register receiver channel low 0x00 0x00 532C PXS PXS RX6CNTRH ProxSense counter register receiver channel high 0x00 0x00 532D PXS RX6CNTRL ProxSense counter register receiver channel low 0x00 0x00 532bE PXS RX7CNTRH ProxSense counter register receiver channel high 0x00 0x00 532F PXS RX7CNTRL ProxSense counter register receiver channel low 0x00 0x00 5330 PXS RX8CNTRH ProxSense counter register receiver channel high 0x00 0x00 5331 PXS RX8CNTRL ProxSense counter register receiver channel low 0x00 0x00 5332 PXS RX9CNTRH ProxSense counter register receiver channel high 0x00 0x00 5333 PXS RX9CNTRL ProxSense counter register receiver channel low 0x00 0x00 5334 to Reserved area 12 bytes 0x00 533F 34 83 DoclD022344 Rev 5 Ky STM8TL52x4 STM8TL53x4 Memory and register map Table 7 General hardware register map continued Address Block Register label Register name Reset status 0x00 5340 PXS RXOCSSELR ProxSense receiver sampling capacitor 0x00 E selection register 0x00 5341 PXS RX1CSSELR ProxSense receiver sampling capacitor 0x00 selection register 0x00 5342 PXS RX2CSSELR ProxSense receiver sampling capacitor 0x00 selection register 0x00 5343 PXS RX3CSSELR ProxSense receiver sampling capacitor 0x00 selection register Ox00 5344 PXS RXACSSELR ProxSense receiver sampling capacitor 0x00 selection register PXS
35. 2 CCR1H TIM2 capture compare register 1 high 0x00 0x00 5261 TIM2 CCR1L TIM2 capture compare register 1 low 0x00 0x00 5262 TIM2 CCR2H TIM2 capture compare register 2 high 0x00 0x00 5263 TIM2 CCR2L TIM2 capture compare register 2 low 0x00 0x00 5264 TIM2 BKR TIM2 break register 0x00 0x00 5265 TIM2 OISR TIM2 output idle state register 0x00 0x00 5266 to Reserved area 26 bytes 0x00 527F Ky DoclD022344 Rev 5 31 83 Memory and register map STM8TL52x4 STM8TL53x4 Table 7 General hardware register map continued Address Block Register label Register name ian 0x00 5280 TIM3 CR1 TIMS control register 1 0x00 0x00 5281 TIM3 CR2 TIM3 control register 2 0x00 0x00 5282 TIM3 SMCR TIM3 slave mode control register 0x00 0x00 5283 TIM3 ETR TIM3 external trigger register 0x00 0x00 5284 TIM3 IER TIM3 interrupt enable register 0x00 0x00 5285 TIM3 SR1 TIM3 status register 1 0x00 0x00 5286 TIM3 SR2 TIMS status register 2 0x00 0x00 5287 TIM3 EGR TIM3 event generation register 0x00 0x00 5288 TIM3 CCMR1 TIM3 capture compare mode register 1 0x00 0x00 5289 TIM3 CCMR2 TIM3 capture compare mode register 2 0x00 0x00 528A TIM3 CCER1 TIM3 capture compare enable register 1 0x00 0x00 528B Ld TIM3 CNTRH TIM3 counter register high 0x00 0x00 528C TIM3 CNTRL TIM3 counter
36. 28 UFQFPN48 10 83 DoclD022344 Rev 5 Ky STM8TL52x4 STM8TL53x4 Product overview 3 d Product overview Figure 1 STM8TL5xx4 block diagram PXS VREG C PXS_RX 0a 9a 0b 9b lt T PXS TX 0 14 L PXS RFIN CL PXS TRIG SCL SDA C MOSI MISO SCK NSS RX TX CK GL 16 MHz internal RC 38 kHz internal RC gt Clock Controller STMB8 core Nested interrupt controller Up to 22 external interrupts Debug module SWIM Voltage reg ProxSense 16 MHz dedicated internal RC 12C SPI USART 16 bit timer 2 16 bit timer 3 8 bit timer 4 Address control and data bases Clocks to core and peripherals Vop Power Voo 1 65 to 3 6 V Vonis 8 Voltage reg 1 Vss Y Supply supervisor PDR 4 POR PDR LJ NRST 16 Kbytes program memory 2 Kbytes Data EPROM 4 Kbytes RAM AWU 38 kHz clock IWDG 38 kHz clock WWDG Beeper gt BEEP PortA gt PA 7 0 Port B LE PB 6 0 Port D gt PD 7 0 MS19122V3 Legend AWU Auto wakeup unit Int RC internal RC oscillator ISC Inter integrated circuit multimaster interface POR PDR Power on reset power down reset SPI Seri
37. 4 standard A device reset allows normal operations to be resumed The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Prequalification trials Most of the common failures unexpected reset and program counter corruption can be reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 DocID022344 Rev 5 Ly STM8TL52x4 STM8TL53x4 Electrical parameters Table 36 EMS data Symbol Parameter Conditions Level Class Voltage limits to be applied on any O pin to N VFESD induce a functional disturbance UFQFPN48 Vpp 3 3 V 3B Fast transient voltage burst limits to be VErTB applied through 100 pF on Vpp
38. 5 11 12 PXS RX1a PXS RX1a ProxSense receiver 1a 16 PXS RX1b PXS RX1b ProxSense receiver 1b 17 12 13 PXS RX2a PXS_RX2a ProxSense E receiver 2a 18 PXS RX2b PXS nx ProxSense receiver 2b 19 13 PXS RX3a PXS RX3a ProxSense receiver 3a 20 PXS RX3b PXS RX3b ProxSense n receiver 3b 21 14 PXS RX4a PXS RX4a ProxSense receiver 4a 22 PXS RX4b PXS RX4b ProxSense receiver 4b Ly DoclD022344 Rev 5 23 83 Pin description STM8TL52x4 STM8TL53x4 Table 4 STM8TL5xx4 pin description continued Pin no Input Output Alternate function c 7 al S gilio o 5 o0 z 9 Rm Pin name 2 D 9 GE n a o o S 3 o a a ox LiuL Oo aa amp Itilfto x cg Default Remap oo 9 41 0 3 SG LL LL o o S dy 2 5 t x c uo I ProxSense 23 45 PXS RX5a PXS RX5a receiver 5a 24 PXS RX5b PXS RX5b ProxSense receiver 5b 25 16 14 PXS_RX6a PXS RX6a ProxSense receiver 6a ProxSense 26 PXS RX6b PXS RX6b receiver 6b 27 17 15 PXS RX7a PXS RX7a ProxSense receiver 7a 28 PXS_RX7b PXS RX7b ProxSense receiver 7b ProxSense 29 PXS RX8a PXS RX8a receiver 8a 30 PXS RX8b PXS RX8b ProxSense receiver 8b 31 PXS_RX9a PXS_RX9a TORN receiver 9a 32 PXS_RX9b PXS RX9b ProxSense receiver 9b 33 18 16 PDO PXS TXO voltc X x X Hs x X Port Do P oxSense transmitter O 34 19 17 P
39. 5 x 4 4 mm 0 65 mm pitch package footprint EE EE EE EE narr Ee es TT TSSOP20 marking example package top view lisse 78 DoclD022344 Rev 5 7 83 Introduction STM8TL52x4 STM8TL53x4 Note 8 83 Introduction This datasheet provides the STM8TL52G4 STM8TL52F4 STM8TL53C4 STM8TL53G4 and STM8TL53F4 pinouts ordering information mechanical and electrical device characteristics For complete information on the microcontroller memory registers and peripherals please refer to the STM8TL5xxx reference manual RM0312 and to the STM8TL5xxx Flash programming manual PM0212 for Flash memory related information For information on the debug module and SWIM single wire interface module refer to the STM8 SWIM communication protocol and debug module user manual UM0470 For information on the STMB core refer to the STM8 CPU programming manual PM0044 All devices of the STM8TL5xxx product line provide the following benefits e Advanced capacitive sensing Patented ProxSense acquisition peripheral providing high end acquisition filtering and environment adaptation Outstanding signal to noise ratio for touch and proximity sensing Up to 300 projected capacitive channels e Reduced system cost Up to 16 Kbytes of low density embedded Flash program memory including up to 2 Kbytes of data EEPROM A High system integration level with internal clock oscillators and watchdogs Smaller battery a
40. DUPXS TX1 10 1c X X X HS X X Port D1 PIE EES transmitter 1 35 20 PD2 xs DER vo TC X X X Ius x X PotD2 F oxSense transmitter 2 36 21 PD3 PXs TX30 o TC X X X HS X X Potpa ProxSense transmitter 3 37 VSSIO S lOs ground 38 VDDIO S s oua supply ProxSense 4 transmitter 40 39 22 1g DAPXS TXA o TC X X x Ius X X Port D4 I TIM2 CH1 Timer 2 channel 1 24 83 DocID022344 Rev 5 Ly STM8TL52x4 STM8TL53x4 Pin description Table 4 STM8TL5xx4 pin description continued Pin no Input Output Alternate function c 7 S 3 on o o Z Els Pin name 2 P se n o o o S 2 o dd a a ox LiuL Oo aa 2 E 16 cg Default Remap o e o o z T G LL LL o o0 Ss S S HE x lt uo r ProxSense 4 transmitter 5 40 23 19 DE TXS VO ITC X X X HS X X Port D5 TIM2 CH2 Timer 2 channel 2 ProxSense 4 transmitter 6 41 24 20 PD AMEND VO ITC X X X HS X X Port D6 TIM3 CH1 Timer 3 channel1 ProxSense 4 transmitter 74 42 25 EDIE TG VO ITC X X X HS X X Port D7 TIM3 CH2 Timer 3 channel 2 ProxSense 4 transmitter 8 43 26 1 ao lO TC X X X HS X X Port BO Timer 3 external trigger ProxSense 2 transmitter 9 44 pay EE NG VOITC X X X HS X X Port Bn TIM2 ETR Timer 2 external trigger 45 PB2 PXS Tx10
41. L5xx4 are based on a generic set of state of the art peripherals The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32 bit families This makes any transition to a different family very easy and simplified even more by the use of a common set of development tools DoclD022344 Rev 5 9 83 Description STM8TL52x4 STM8TL53x4 Table 2 Device features Features STM8TL52F4 STM8TL53F4 STM8TL52G4 STM8TL53G4 STM8TL53C4 Flash Kbytes 16 Data EEPROM 2 Kbytes RAM Kbytes 4 Basic 1 8 bit Timers General 2 16 bit purpose Communi S 1 cation I2C 1 Interfaces USART 1 GPIOs 12 17 23 Up to 12 touch Up to 30 touch Up to 25 touch Up to 72 touch Up to 300 touch sensing sensing sensing sensing sensing channels channels channels channels channels 5 receiver 5 receiver 8 receiver 8 receiver 20 receiver ProxSense i transmitter transmitter transmitter transmitter transmitter channels and 2 channels and 6 channels and 2 channels and 9 channels and 15 transmitter transmitter transmitter transmitter transmitter channels channels channels channels channels Others Window watchdog independent watchdog two 16 MHz and one 38 kHz internal RC auto wakeup counter beeper CPU frequency 16 MHz Operating voltage 1 65 to 3 6 V Operating 40 to 85 C temperature Packages TSSOP20 UFQFPN
42. PXS RX6a 19 14 15 16 17 18 19 20 21 22 23 OLD NAN D fF CL OL D f Z ZZ B S 2 5 2 S S X X X X X X X X Xx X C c amp c ir X CX C C G m m pa pa o pa pa pa o o pa x xX X X X X X X X X X X cC N N N O O NA N N O O n MS19101V1 HS corresponds to 20 mA high sink source capability 2 Power supply pins must be correctly decoupled with capacitors near the pins Please refer to the power supply circuitry details in Section 9 3 2 Power supply on page 46 and the STM8TL5xxx reference manual RM0312 Section 6 Power supply d 18 83 DoclD022344 Rev 5 STM8TL52x4 STM8TL53x4 Pin description d Figure 3 STM8TL53G4U6 28 pin UFQFPN package pinout O ar ar I mr I I I T O FO O O Oo e a ooN N z 2 2 2 2 Z pnt E EE u 9 N O O d D dd x x x x x 2 x ome b ty 12 0 na o i 3 x x x x x gO DELENE D o 000 0 O0 LIELIE CoRR OD x It 4M D DO OO f O O O n O O co ng NI N BR nm De TIM3 CH2 USART CK SPI SCK HS PA2I 1 I2C SDA USART TX SPI MISO HSJPA3ED 2 I2C SCL USART RX SPI MOSI HSJPA4D 3 21 PD3 HS PXS_TX3 20 PD2 HS PXS_TX2 19 CA PD1 HS PXS_TX1 Von UFQFPN 18 Cd PDO HS PXS_TXO Vss 17 J PXS_RX7a PXS Vngc D6 16CIPXS RX6a NRST HSPAS 7 15 CIPXS RX5a AAA AA Oo N 2222225259 GC O x x ox x x ip x Te By H BS ES I 190999 0 I FJ xX X x x x O Zn n O O n rm LL ct n 9 X D a gr O O 9 x zz o MS19100V1 HS correspond
43. R RR RR RR RR RA Re 43 9 1 Parameter conditions 22 06 a EER EER ER ER RE RE hn 43 9 1 1 Minimum and maximum values ee Ee SE eee 43 9 1 2 Typical values gea w R g Rr N R R R stread arenaene 43 9 1 3 Typical CUrves 2 44 datet Pha RE REK IRR RA E tad ex ER reke av 43 9 1 4 Loading capacitor sls 43 9 1 5 Pin input voltage RR I II 44 9 2 Absolute maximum ratings nrk 44 9 3 Operating conditions asd exces e nra rere e wee n RC ce Ua etr 45 9 3 1 General operating conditions illie eee 45 9 3 2 Power Supply rre 46 9 3 3 Power up power down operating conditions 46 9 3 4 ProxSense Regulator Voltage ie a 47 9 3 5 Supply current characteristics EE EG EE ee ee ee ee 47 9 3 6 Clock and timing characteristics llle 52 9 3 7 Memory characteristics eae 54 9 3 8 VO port pin characteristics ee ee 56 9 3 9 Communication interfaces e rn rn ravn 64 9 3 10 EMC characteristics lille 68 9 4 Thermal characteristics iusso gcc awed ns BRA ER HORE KAREN kaldes 70 Package information esse ek RR RR RR RR RR ER RR RR RR RR Rae 71 10 1 ECOPACK PEE 71 10 2 UFQFPN48 package information EE se ee EE ke eee 71 10 3 UFOFPN28 package Information es se ee EE Ee eee 74 10 4 TSSOP20 package information EE EE EE EE Ee eee 76 Part numbering uae u coe je ae a MNR de er Cee dr e GANAN d 79 STM8 development
44. S corresponds to 20 mA high sink source capability Power supply pins must be correctly decoupled with capacitors near the pins Please refer to the power supply circuitry details in Section 9 3 2 Power supply on page 46 and the STM8TL5xxx reference manual RM0312 Section 6 Power supply DoclDO22344 Rev 5 21 83 Pin description STM8TL52x4 STM8TL53x4 Table 3 Legends abbreviations Type input O output S power supply Input FT 5 V tolerant TC 3 V capable Level Output HS high sink source 20 mA Port and control Input float floating wpu weak pull up configuration Output T true open drain OD open drain PP push pull Bold X pin state after reset release Reset state Unless otherwise specified the pin state is the same during the reset phase i e under reset and after internal reset release i e at reset state Table 4 STM8TL5xx4 pin description Pin no Input Output Alternate function E a nG 8 25 tz Qo o 5 o0 Z 2 S Pin name 2 g 2 EIS Sr amp RIS zg g z na e eo Default Remap Gg 9 o 8 s 5 5 oja 35 IL C1 0 o mc SISIE x c uso 1 PB6 PXS_TX14 O TC x x X Ius x x PotBe ProxSense transmit 14 Port A00 1 2 27 2 PAO SWIM io Te x X x lus X x swm SWIM input and BEEP output Beep output PA1 SPI_NSS SPI master Ter 3 128 3 TIM3
45. al peripheral interface SWIM Single wire interface module USART Universal synchronous asynchronous receiver transmitter IWDG Independent watchdog WWDG Window watchdog ProxSenseTM capacitive sensing peripheral DoclD022344 Rev 5 11 83 Product overview STM8TL52x4 STM8TL53x4 3 1 12 83 Central processing unit STM8 The 8 bit STM8 core is designed for code efficiency and performance with an Harvard architecture and a 3 stage pipeline It contains 6 internal registers which are directly addressable in each execution context 20 addressing modes including indexed indirect and relative addressing and 80 instructions Architecture and registers Harvard architecture 3 stage pipeline 32 bit wide program memory bus single cycle fetching most instructions Xand Y 16 bit index registers enabling indexed addressing modes with or without offset and read modify write type data manipulations 8 bit accumulator 24 bit program counter 16 Mbyte linear memory space 16 bit stack pointer access to a 64 Kbytes level stack 8 bit condition code register 7 condition flags for the result of the last instruction Addressing 20 addressing modes Indexed indirect addressing mode for lookup tables located anywhere in the address space Stack pointer relative addressing mode for local variables and parameter passing Instruction set 80 instructions with 2 byte average instruction size Standard data movement and
46. and Vss UFQFPNAS Vpp 3 3 V fugi 3B pins to induce a functional disturbance Electromagnetic interference EMI Based on a simple application running on the product toggling 2 LEDs through the I O ports the product is monitored in terms of emission This emission test is in line with the norm SAE J 1752 3 which specifies the board and the loading of each pin Table 37 EMI data 0 25 Monitored frequency Max vs 16 Symbol Parameter Conditions band MHz Unit 0 1 MHz to 30 MHz 5 m 30 MHz to 130 MHz 5 dBuV SEMI Peak level Vop 3 6 V Ta 25 C 130 MHz to 1 GHz 0 SAE EMI Level 1 1 Not tested in production Absolute maximum ratings electrical sensitivity Based on two different tests ESD and LU using specific measurement methods the product is stressed in order to determine its performance in terms of electrical sensitivity For more details refer to application note AN1181 Electrostatic discharge ESD Electrostatic discharges a positive then a negative pulse separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n 1 supply pin Two models can be simulated human body model and charge device model This test conforms to the JESD22 A114A A115A standard Table 38 ESD absolute maximum ratings Symbol Ratings Conditio
47. ation Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 33 UFQFPN48 marking example package top view Product identification STMATL 53 Revision code Pin 1 identifier MSv37477V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity d DoclD022344 Rev 5 73 83 Package information STM8TL52x4 STM8TL53x4 10 3 74 83 UFQFPN28 package information Figure 34 UFQFPN28 28 lead 7x7 mm 0 5 mm pitch ultra thin fine pitch quad flat package outline PIN 1 IDENTIFIER LASER MARKING AREA D S 8 gt PIN 1 CORNER C0 130X45 Detail Y 0 1008 0 0500 Detail Z R0 125 TYP AOBO ME V5 1 Drawing is not to scale Table 42 UFQFPN28 28 lead 7x7 mm 0 5 mm pitch ultra thin fine pitch quad flat package mechanical data millimeters inches
48. clocks are stopped the device remains powered on Wakeup is triggered by an external interrupt The ProxSense peripheral can return to low power mode between each conversion The ProxSense acquisition can be operated in Run Wait and Active halt modes Voltage regulators The STM8TL5xx4 devices embed an internal voltage regulator for generating the 1 8 V power supply for the core and peripherals and a second internal voltage regulator providing a stable power supply around 1 45V for the ProxSense peripheral Dual mode voltage regulator This regulator has two different modes main voltage regulator mode MVR and low power voltage regulator mode LPVR When in Active halt mode the regulator remains in MVR if ProxSense is active When entering Halt or Active halt modes the system automatically switches from the MVR to the LPVR in order to reduce current consumption unless ProxSense is enabled ProxSense voltage regulator This regulator provides a very stable voltage to power the ProxSense peripheral including ProxSense pins in order to be independent of any power supply variations This regulator is switched on while the ProxSense peripheral is enabled bit PXSEN 1 and bit LOW POWER is set to 0 in register PXS CR1 Otherwise when LOW POWER is set to 1 this regulator is only enabled during conversions while CIPF 1 and SYNCPF 0 Clock control The STM8TL5xx4 embeds a robust clock controller It is used to distribu
49. cs ESE EE EE EE ee ee eee 56 Output driving current high sink ports EE ee Ee ee ke ee ee ee ee 58 NRST pin characteristics EE EE EE EE rn tees 62 SPI characteristics R R N apwe R R ee nn ee ee ee ee e 64 IC characteristics sess lin 67 EMS dala 2 cesta S saltern hend ual iet Le mE AA eM es 69 dtc ET 69 ESD absolute maximum ratings llle 69 Electrical sensitivities lille 70 Thermal characteristics 2 EE EE EE Ee ee ee ee nh 70 UFOFPN48 48 lead 7x7 mm 0 5 mm pitch ultra thin fine pitch quad flat package mechanical data AE EE EG eee rn ee 72 UFOFPN 28 28 lead 7x7 mm 0 5 mm pitch ultra thin fine pitch quad flat package mechanical data lise 74 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch package mechanical data lille 76 Ordering information scheme e x x K arver aner narr nn rn nrk 79 DoclD022344 Rev 5 5 83 List of tables STM8TL52x4 STM8TL53x4 Table 45 Document revision history en 82 I 6 83 DoclD022344 Rev 5 STM8TL52x4 STM8TL53x4 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure
50. de parang 0x00 compensation capacitor selection register 0x00 5357 PXS RX7EPCCSELR ProxSense receiver elgcirodeparasitic 0x00 compensation capacitor selection register 0x00 5358 PXS_RX8EPCCSELR ProxSense receiver electrode parasitig 0x00 T compensation capacitor selection register 0x00 5359 PXS RX9EPCCSELR Pen EN electrode parasiti 0x00 E compensation capacitor selection register 0x00 535A to Reserved area 11174 bytes 0x00 7EFF 1 After power on reset Table 8 CPU SWIM debug module interrupt controller registers Address Block Register label Register name Meset status 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x80 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 0x00 7F05 CPU XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x05 0x00 7F09 SPL Stack pointer low OxFF 0x00 7F0A CC Condition code register 0x28 36 83 DoclD022344 Rev 5 Ly STM8TL52x4 STM8TL53x4 Memory and register map Table 8 CPU SWIM debug module interrupt controller registers continued Address Block Register label Register name E 0x00 7F0B to Reserved area
51. e boot processes Table 12 Unique ID registers 96 bits ra Panid Unique ID bits 7 6 5 4 3 2 1 0 0x4925 X coordinate on U ID 7 0 0x4926 the wafer U ID 15 8 0x4927 Y coordinate on U ID 23 16 0x4928 the wafer U ID 31 24 0x4929 Wafer number U ID 39 32 0x492A U 1D 47 40 0x492B U ID 55 48 0x492C U ID 63 56 0x492D Lot number U ID 71 64 Ox492E U ID 79 72 0x492F U_ID 87 80 0x4930 U ID 95 88 42 83 DoclD022344 Rev 5 Ky STM8TL52x4 STM8TL53x4 Electrical parameters 9 9 1 9 1 4 d Electrical parameters Parameter conditions Unless otherwise specified all voltages are referred to Vss Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature of Taz 25 C and TA Ta max given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation meant 271 Typical values Unless otherwise specified typical data are based on Ta 25 C Vpp
52. egister 2 0x00 0x00 5202 SPI SPI ICR SPI interrupt control register 0x00 0x00 5203 SPI SR SPI status register 0x00 0x00 5204 SPI DR SPI data register 0x00 0x00 5205 to Reserved area 11 bytes 0x00 520F kyr DoclD022344 Rev 5 29 83 Memory and register map STM8TL52x4 STM8TL53x4 Table 7 General hardware register map continued Address Block Register label Register name bng 0x00 5210 I2C CR1 I2C control register 1 0x00 0x00 5211 I2C CR2 I2C control register 2 0x00 0x00 5212 I2C FREQR I2C frequency register 0x00 0x00 5213 I2C OAR1L I2C own address register 1 low 0x00 0x00 5214 I2C OAR1H I2C own address register 1 high 0x00 0x00 5215 12C OAR2 I2C own address register 2 0x00 0x00 5216 I2C DR I2C data register 0x00 0x00 5217 aid I2C SR1 I2C status register 1 0x00 0x00 5218 I2C SR2 I2C status register 2 0x00 0x00 5219 I2C SR3 I2C status register 3 0x00 0x00 521A I2C ITR I2C interrupt control register 0x00 0x00 521B I2C CCRL I2C Clock control register low 0x00 0x00 521C I2C CCRH I2C Clock control register high 0x00 0x00 521D I2C TRISER I2C TRISE register 0x00 0x00 521E to Reserved area 18 bytes 0x00 522F 0x00 5230 USART SR USART status register 0xCO 0x00 5231 USART DR USART data register OxXX 0x00 5232 USART BRR1 USART baud rate register 1 0x00 0x00 5233 USART BRR2 USART baud rate register 2 0x
53. ept under reset and not clocked and the on chip peripheral when clocked and not kept under reset The CPU is in Wait mode in both cases No I O pin toggling Not tested in production Current consumption with ProxSense peripherals Measurement made for fyasTER 16 MHZ fproxSense 16 MHZ all other peripherals off and under the following conditions PXS RxiCSSELR Sampling Capacitor 0x10 PXS_Rx EPCCSELR Electrode Parasitic Capacitance Compensation 0x80 Capacitance between Tx and Rx of 10nF Table 23 ProxSense peripheral current consumption ProxSense ProxSense Symbol transmitter receiver Typical Unit Tx Rx 1 1 0 6 Ipp Pxs 1 4 1 1 mA 1 10 2 3 1 Data based on characterization not tested in production Ly DoclD022344 Rev 5 51 83 Electrical parameters STM8TL52x4 STM8TL53x4 9 3 6 52 83 Clock and timing characteristics Internal clock source The parameters given in Table 24 are derived from tests performed under ambient temperature and Vpp supply voltage They are subject to general operating conditions for VDD and Ta High speed internal RC oscillator Table 24 HSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fus Frequency Vpp 3 0 V S 16 MHz Accuracy of HSI Vpp 3 0 V Ta 25 C 1 i 1 ACCnus oscillator factory 1 65 V lt VDD lt 3 6 V s calibrated Ta 40 to 85 C i 7 0 HSI oscillator
54. er to I O port characteristics for more details on the input output alternate function characteristics SDA and SCL Table 35 I C characteristics Standard mode IZC Fast mode IPC Symbol Parameter Unit Min Max Min Max usc SCL clock low time 4 7 1 3 us tw SCLH SCL clock high time 4 0 i 0 6 tsu sDa SDA setup time 250 100 twspA SDA data hold time 0 3 o 9 900 3 SDA SDA and SCL rise time 1000 300 ns t 5CL SDA SDA and SCL fall time 300 300 tscL th sta START condition hold time 4 0 2 0 6 Repeated START condition setu us teu STA ai P 47 0 6 tsusro STOP condition setup time 4 0 2 0 6 US STOP to START condition time tw STO STA bus free 47 S 1 8 us Cp Capacitive load for each bus line 400 400 pF 1 fsck must be at least 8 MHz to achieve max fast I C speed 400 kHz 2 Data based on standard I C protocol requirement not tested in production 3 The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal 4 The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL Note For speeds around 200 kHz achieved speed can have 5 tolerance For other speed ranges achieved speed can have 2 tolerance The above variations depend on the accuracy
55. g module interrupt controller registers iS Ee se ee ee 36 Interrupt mapping 23 ER EE ee PRU RR A RE RE 38 Option bytes x ANNA NG GG EE RARE Pee OE OE tn 40 Option byte description illl 40 Unique ID registers 96 bits llle III 42 Voltage characteristics R N E RR e R RR RR NR R RR R R rn 44 Current characteristics EE EE EE Ee ee elle 45 Thermal characteristics EE EE EE Ee ee ee ee ssh 45 General operating conditions EE EE EE EE Ee eh 45 Operating conditions at power up power down EE EE sells 46 ProxSense voltage regulator characteristics EE EE 000 eee eee eee 47 Total current consumption in Run mode ees 47 Total current consumption in Wait mode llli 48 Total current consumption in Halt mode and Active halt mode Mpp 1 09 VO 3 0 V con EE EE ad KAN RON Roue E RR E dcm M h 50 Peripheral current consumption liiis es 51 ProxSense peripheral current consumption EE EE EE EG cece eee eee 51 HSI oscillator characteristics EE EE SE SG EE Ge ee ee ee ee ee ee ee ee 52 HSI PXS oscillator characteristics ie EE Se ee tee ee 53 LSI oscillator characteristics sannana EE EE ES GE eee 53 RAM and hardware registers ie Ee eee 54 Flash program memory Rg rises rrak R RR tee eae 54 Program memory endurance and retention ie EE EE EE Ee ee ee eee 55 Data memory endurance and retention Ee EE Ee eee 55 VO static characteristi
56. ible in Run Wait and Active halt modes TouchSensing dedicated library available upon request Complete C source code library with firmware examples MISRA compliant Multifunction capability to combine capacitive sensing functions with traditional MCU features Compatible with proximity touchkey linear and rotary touch sensor implementation Configuration of all ProxSense parameters Extra filtering and calibration functions TouchSensing user interface through firmware API for status reporting and application configuration Compliance with Cosmic IAR and Raisonance C compilers DoclD022344 Rev 5 17 83 Pin description STM8TL52x4 STM8TL53x4 4 Pin description Figure 2 STM8TL53 48 pin UFQFPN package pinout PXS TX5 TIM2 CH2 PXS TX8 TIM3 TRIG PXS TX7 TIM3 CH2 PXS TX6 TIM3 CH1 PXS TX4 TIM2 CH1 PXS TX10 PXS TX9 TIM2 TRIG PXS TX13 PXS TX12 PXS TX11 Aa ZA FF zz a FR sz zx zx S I z2 2 2 cr EET Z C PB4 C PB3 N D e IN eo D a o o PXS TX14 HSJPB6 D1 BEEP SWIM HS PA0 02 TIM3 CH1 SPI NSS HS PA1 03 TIM3 CH2J USART CK SPI SCK HS PA2 D 4 I2C SDA USART TX SPI MISO HS PA3 05 I2C SCL USART RX SPI MOSI HSJPA4 D6 m UFQFPN PD3 HS PXS_TX3 PD2 HS PXS_TX2 PD1 HS PXS_TX1 PDO HS PXS TXO PXS RX9b PXS RX9a PXS RX8b Vss D8 PXS RX8a PXS VREG D9 PXS RX7b NRST HS PA5 010 PXS RX7a CLK CCOIPXS TRIG HS PA6 011 PXS RX6b PXS_RFIN HS PA7 012
57. ion with external devices e Maximum speed 8 Mbit s fsysc kj both for master and slave e Full duplex synchronous transfers e Simplex synchronous transfers on 2 lines with a possible bidirectional data line e Master or slave operation selectable by hardware or software e Hardware CRC calculation e Slave master selection input pin PC The I2C bus interface I2C provides multi master capability and controls all I C bus specific sequencing protocol arbitration and timing e Master slave and multi master capability e Dual addressing mode capability e Standard mode up to 100 kHz and fast speed modes up to 400 kHz e T bit and 10 bit addressing modes e Hardware CRC calculation I DoclD022344 Rev 5 STM8TL52x4 STM8TL53x4 Product overview 3 18 3 19 d ProxSense The ProxSense peripheral uses a charge transfer method to detect capacitance changes Up to 300 capacitive sensing channels composed of 15 transmitters and 20 receivers with up to 10 Rx channels acquired in parallel Fast acquisition with a typical scan time of 250 us for 10 Rx channels Configurable internal sampling capacitor Ca Electrode Parasitic Capacitance Compensation EPCC to ensure the best sensitivity in all user environments RF noise detection allowing to reject corrupted samples External trigger to de synchronize the acquisition from known noise Can be configured to return to low power mode between each conversion Acquisition poss
58. license express or implied to any intellectual property right is granted by ST herein Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product ST and the ST logo are trademarks of ST All other product or service names are the property of their respective owners Information in this document supersedes and replaces information previously supplied in any prior versions of this document 2015 STMicroelectronics All rights reserved d DoclD022344 Rev 5 83 83
59. ls Based on characterization results not tested The maximum value may be exceeded if negative current is injected on adjacent pins Rpy pull up equivalent resistor based on a resistive transistor corresponding Ipy current characteristics Data guaranteed by Design not tested in production D ov m o mw RS Figure 17 Typical pull up resistance Rpy vs Vpp with Vin Vss Pull up resistance KO VDD V MS30300V2 56 83 DocID022344 Rev 5 Ly STM8TL52x4 STM8TL53x4 Electrical parameters Figure 18 Typical Vj and Vjy Vs Vpp Vit and Vis V VDD V MS30301V2 d DoclD022344 Rev 5 57 83 Electrical parameters STM8TL52x4 STM8TL53x4 Output driving current Subject to general operating conditions for Vpp and Ta unless otherwise specified Table 32 Output driving current high sink ports VO type Standard Symbol Parameter Output low level voltage for an I O pin Conditions lio 2 mA Vpp 1 8V Min Max Unit 0 45 lio 2 MA Vpp 3 0V 0 45 lo 10 mA VpD 3 0V 0 7 Output high level voltage for an VO pin lio z 1 mA Vpp 1 8V Vpp 0 45 lio 1 mA Vpp 3 0V Vpp 0 45 lio 10 mA Vpp 3 0V Vpp 0 7 ProxSense VO VoH Output high level voltage for PXS_TX ProxSense O Output high level voltage for PXS RX ProxSense O Ipxs TX 0 2 mA IPxs RX 0 1 mA VnEG VREG
60. maximum Zi piv is the absolute sum of the positive and negative injected currents instantaneous values These results ar based on characterization With Xi jpjyj maximum current injection on four I O port pins of the device Table 15 Thermal characteristics Symbol Ratings Min Unit TsrG Storage temperature range 65 to 150 KG Ty Maximum junction temperature 150 Operating conditions Subject to general operating conditions for Vpp and Ta General operating conditions Table 16 General operating conditions Symbol Parameter Conditions Min Max Unit faster Master clock frequency 1 65 V lt Vpp lt 3 6 V 2 16 MHz Vpp Standard operating voltage 1 65 3 6 V UQFPN48 625 2 Power dissipation at Ta 85 E Po C for suffix 2 devices ak nee 290 myy TSSOP20 180 TA Temperature range 1 65 V lt Vpp lt 3 6 V 40 85 ja Ty Junction temperature range 40 C lt Ta lt 85 C 40 105 1 MASTER fopu 2 Tocalculate JA in table Thermal characteristics DoclD022344 Rev 5 Ppmax Ta use the formula given in thermal characteristics Ppmax Tymax TA O Ja with T jmax in this table and O 45 83 Electrical parameters STM8TL52x4 STM8TL53x4 9 3 2 9 3 3 46 83 Power supply Figure 10 Power supply scheme VDD VDDIO 100 nr Vssio Tf OUT HE IN VDD Voltage regulator 100 nF 1uF Level shifter Kernel logic CPU digi
61. moved Vo row with Conditions lj57 20 mA and Vpp 3 0 V from Table 31 VO static characteristics Updated ProxSense I O Conditions and Min values in Table 32 Output driving current high sink ports Added Section 3 13 General purpose and basic timers 07 Aug 2013 Updated OPTO default value in Table 10 Option bytes 18 Mar 2015 Updated Figure 27 SPI timing diagram slave mode and CPHA 0 Section 10 2 UFQFPN48 package information Section 10 3 UFQFPN28 package information Section 10 4 TSSOP20 package information Added Figure 33 UFQFPN48 marking example package top view Figure 36 UFQFPN28 marking example package top view Figure 39 TSSOP20 marking example package top view DocID022344 Rev 5 Ly STM8TL52x4 STM8TL53x4 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections enhancements modifications and improvements to ST products and or to this document at any time without notice Purchasers should obtain the latest relevant information on ST products before placing orders ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No
62. nal power Pyomax represents the maximum power dissipation on output pins where Pyomax Vo lo Vpp Vouy lou taking into account the actual Ve loi and Vou lou of the I Os at low and high level in the application Table 40 Thermal characteristics Symbol Parameter Value Unit Thermal resistance junction ambient 32 UFQFPN 48 7 x 7 mm Thermal resistance junction ambient 8 Osa UFQFPN 28 4 x 4 mm m add Thermal resistance junction ambient 410 TSSOP20 1 70 83 Thermal resistances are based on JEDEC JESD51 2 with 4 layer PCB in a natural convection environment d DoclD022344 Rev 5 STM8TL52x4 STM8TL53x4 Package information 10 Package information 10 1 ECOPACK In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark 10 2 UFQFPN48 package information Figure 31 UFQFPN48 48 lead 7x7 mm 0 5 mm pitch ultra thin fine pitch quad flat package outline Pin 1 identifier laser marking area D j A E E Seating lane A1 P L C 0 500x45 pin1 corner R 0 125 typ Detail Z A0B9 ME V3 1 Drawing is not to scale 2 Allleads pads should also be soldered to the PCB to improve the lead
63. nd cheaper power supplies e Low power consumption and advanced features Upto 16 MIPS at 16 MHz CPU clock frequency Less than 150 uA MHz 0 8 pA in Active halt mode with AWU and 0 3 pA in Halt mode Clock gated system and optimized power management e Short development cycles A Application scalability across a common family product architecture with compatible pinout memory map and modular peripherals Full documentation and a wide choice of development tools Product longevity Advanced core and peripherals made in a state of the art technology Product family operating from 1 65 V to 3 6 V supply ProxSense is a trademark of Azoteq Pty Ltd I DoclD022344 Rev 5 STM8TL52x4 STM8TL53x4 Description 2 I Description The STM8TL5xx4 devices feature the enhanced STM8 CPU core providing increased processing power up to 16 MIPS at 16 MHz while maintaining the advantages of a CISC architecture with improved code density a 24 bit linear addressing space and an optimized architecture for low power operations It uses a ProxSense charge transfer capacitive acquisition method that is capable of near range proximity detection The family includes an integrated debug module with a hardware interface SWIM which allows non intrusive in application debugging and ultrafast Flash programming All STM8TL5xx4 microcontrollers feature low power low voltage single supply program Flash memory The STM8T
64. ndard ports EES SES EE ES EE See ee 59 Typ Vpp Vou at Vpp 3 0 V standard ports ees SE SE ES EE See enn 60 Typ Vpp Vou at Vpp 1 8 V ProxSense TX ports ESE ESE ee 60 Typ Vpp Vou at Vpp 1 8V ProxSense RX ports ESE Se ee 61 Typical NRST pull up resistance Rpy vs VDD ESE SES ES lees 62 Recommended NRST pin configuration llle 63 SPI timing diagram slave mode and CPHA 20 2222 65 SPI timing diagram slave mode and CPHA MCCC 65 SPI timing diagram master Moda MERECE 66 Typical application with I C bus and timing diagram 11 68 UFQFPNAS 48 lead 7x7 mm 0 5 mm pitch ultra thin fine pitch quad flat package outline EE EE EE EE EE Ee ee ee Ee ee SE es 71 UFQFPNAS 48 lead 7x7 mm 0 5 mm pitch ultra thin fine pitch quad flat package recommended footprint llli 72 UFQFPN48 marking example package top view annsan aaaea 73 UFOFPN 28 28 lead 7x7 mm 0 5 mm pitch ultra thin fine pitch quad flat package o tlinie 4 14 vasset i rmi Ha Fa he Sie OE T paa VP 74 UFOFPN 28 28 lead 7x7 mm 0 5 mm pitch ultra thin fine pitch quad flat package recommended footprint EE EE EE EE EE EE Ee ee ee ee ee ee ee 75 UFQFPN28 marking example package top view is EE EE EE ee ee ee ee 75 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch package outline llis es 76 TSSOP20 20 lead thin shrink small outline 6
65. nk source capability ProxSense patented acquisition technology with up to 300 touch sensing channels 20 receiver transmitter channels and 15 transmitter channels supporting projected capacitive acquisition method suitable for proximity detection Timers Two 16 bit general purpose timers TIM2 and TIM3 with up and down counter and two channels used as IC OC PWM One 8 bit timer TIM4 with 7 bit prescaler Independent watchdog Window watchdog Auto wakeup unit Beeper timer with 1 2 or 4 kHz frequencies Communication interfaces SPI synchronous serial interface Fast IC Multimaster slave 400 kHz USART with fractional baud rate generator Development support Hardware single wire interface module SWIM In circuit emulation ICE Table 1 Device summary Reference Part number STM8TL52x4 STM8TL52F4 STM8TL52G4 STM8TL53x4 STM8TL53C4 STM8TL53F4 STM8TL53G4 March 2015 DoclD022344 Rev 5 1 83 This is information on a product in full production www st com Contents STM8TL52x4 STM8TL53x4 Contents 1 Introduction sie REO NAE PER To AKA AN TA 8 2 Description aci re RR EE N NR AKN PARAAN rg e N RN NR RC dee 9 3 Product overview xs s s x EER 223 PEERS RA ER e ae EA UR ERE e d 11 3 1 Central processing unit STM8 iii is EE EE EER a 12 3 2 Development tools EE EE EE SE EE EE EE ee seh 13 3 3 Single wire data interface SWIM and debug module 13 3
66. ns je Unit value Electrostatic discharge voltage 2 VESD HBM human body model 2000 Ty 25 C V V Electrostatic discharge voltage 1000 ESD CDM charge device model 1 Data based on characterization results not tested in production 2 Device sustained up to 3000 V during ESD trials Ly DoclD022344 Rev 5 69 83 Electrical parameters STM8TL52x4 STM8TL53x4 Static latch up LU 3 complementary static tests are required on 6 parts to assess the latch up performance A supply overvoltage applied to each power supply pin and a current injection applied to each input output and configurable I O pin are performed on each sample This test conforms to the EIA JESD 78 IC latch up standard For more details refer to application note AN1181 Table 39 Electrical sensitivities Symbol Parameter Class LU Static latch up class ll 9 4 Thermal characteristics The maximum chip junction temperature T max must never exceed the values given in Table 16 General operating conditions on page 45 The maximum chip junction temperature T max in degrees Celsius may be calculated using the following equation TJmax TAmax PDmax X Osa Where TAmax is the maximum ambient temperature in C Oya is the package junction to ambient thermal resistance in C W Ppmax is the sum of Pintmax and Pijomay PDmax Pintmax P omax Pintmax IS the product of Ipp and Vpp expressed in watts This is the maximum chip inter
67. ntrol register 1 0x00 0x00 5301 PXS CR2 ProxSense control register 2 0x00 0x00 5302 PXS CR3 ProxSense control register 3 0x04 0x00 5303 Reserved area 1 byte 0x00 5304 aie PXS_ISR ProxSense interrupt and status register 0x00 0x00 5305 Reserved area 1 byte 0x00 5306 PXS CKCR1 ProxSense clock control register 1 0x30 0x00 5307 PXS CKCR2 ProxSense clock control register 2 0x11 0x00 5308 PXS RXENRH ProxSense receiver enable register high 0x00 0x00 5309 PXS RXENRL ProxSense receiver enable register low 0x00 0x00 5310 to Reserved area 2 bytes 0x00 5311 0x00 530A PXS RXCR1H ProxSense receiver control register 1 high 0x00 0x00 530B PXS RXCR1L ProxSense receiver control register 1 low 0x00 0x00 530C PXS RXCR2H ProxSense receiver control register 2 high 0x00 0x00 530D ae PXS_RXCR2L ProxSense receiver control register 2 low 0x00 0x00 530E PXS_RXCR3H ProxSense receiver control register 3 high 0x00 0x00 530F PXS_RXCR3L ProxSense receiver control register 3 low 0x00 0x00 5312 PXS_RXINSRH ProxSense receiver inactive state register high 0x00 0x00 5313 PXS_RXINSRL ProxSense receiver inactive state register low 0x00 0x00 5314 to Reserved area 2 bytes 0x00 5315 0x00 5316 PXS_TXENRH ProxSense transmit enable register high 0x00 PXS 0x00 5317 PXS_TXENRL ProxSense transmit enable register low 0x00 0x00 5318 to Reserved area 2 bytes 0x00 5319 ky DoclD022344 Rev 5 33 83 Memory and register map STM8TL52x4 STM8TL53x4 Table 7 General hardware regi
68. p on page 28 addresses 0x00 50A0 to 0x00 50A5 for a list of external interrupt registers d DoclD022344 Rev 5 37 83 Interrupt vector mapping STM8TL52x4 STM8TL53x4 6 Interrupt vector mapping Table 9 Interrupt mapping Wakeup Wakeup Wakeup Wakeup IRQ Source Description from Halt from from Wait from Wait Vector No block P Active halt WFI WFE address mode 1 mode mode mode RESET Reset Yes Yes Yes Yes 0x00 8000 TRAP _ Software interrupt 0x00 8004 0 Reserved 0x00 8008 FLASH end of 1 FLASH Programing S Yes Yes 0x00 800C write attempted to protected page interrupt al pe ER EDE IUIS z Yes Yes Yes 0x00 8010 conversion completed 0x00 8011 3 Reserved 0x00 8017 4 AWU _ Auto wakeup from Halt Yes Yes Yes 0x00 8018 5 Reserved 0x00 801C 6 EXTIB External interrupt port B Yes Yes Yes Yes 0x00 8020 7 EXTID External interrupt port D Yes Yes Yes Yes 0x00 8024 8 EXTIO External interrupt 0 Yes Yes Yes Yes 0x00 8028 9 EXTM External interrupt 1 Yes Yes Yes Yes 0x00 802C 10 EXTI2 External interrupt 2 Yes Yes Yes Yes 0x00 8030 11 EXTI3 External interrupt 3 Yes Yes Yes Yes 0x00 8034 12 EXTIA External interrupt 4 Yes Yes Yes Yes 0x00 8038 13 EXTI5 External interrupt 5 Yes Yes Yes Yes 0x00 803C 14 EXTI6 External interrupt 6 Yes Yes Yes Yes 0x00 8040 15 EXTI7 External interrupt 7 Yes
69. power IDD HSI consumption l 7O 100 HA 1 Vpp 3V TA 40 to 125 C unless otherwise specified Figure 14 Typical HSI frequency vs Vpp HSI frequency MHz VDD V MS30308V2 DoclD022344 Rev 5 d STM8TL52x4 STM8TL53x4 Electrical parameters Figure 15 Typical HSI accuracy vs temperature VDD 3 V 3 5 3 0 2 5 2 0 1 5 1 0 0 5 0 0 01594 1 096 RC accuracy 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 3V min e 3V typical 3V max Temperature C High speed ProxSense RC oscillator Table 25 HSI PXS oscillator characteristics ai17021b Symbol Parameter Conditions Min Typ Max Unit fusi Pxs Frequency Vpp 3 0 V x 16 MHz 1 Vpp 3V Ta 40 to 85 C unless otherwise specified Low speed internal RC oscillator LSI Table 26 LSI oscillator characteristics 1 Symbol Parameter Conditions Min Typ Max Unit fis Frequency 26 38 56 kHz LSI oscillator frequenc A faris grin EIE 0 CET s 85 C 12 a 11 1 Vpp 1 65 V to 3 6 V Ta 40 to 85 C unless otherwise specified 2 Foreach individual part this value is the frequency drift from the initial measured frequency DoclD022344 Rev 5 53 83 d Electrical parameters STM8TL52x4 STM8TL53x4 Figure 16 Typical LSI frequency vs Vpp l e 0 9 e 9 9
70. production Table 30 Data memory endurance and retention Parameter Conditions Min Typ Max Unit Endurance Ta 40 to 85 C 300 1X2 S kcycles 30 Years Data retention 300 kcycles at Ta 85 1 Data based on characterization results not tested in production 2 Data based on characterization performed on the whole data memory 2 Kbytes DoclD022344 Rev 5 55 83 Electrical parameters STM8TL52x4 STM8TL53x4 9 3 8 O port pin characteristics General characteristics Subject to general operating conditions for Vpp and Ta unless otherwise specified All unused pins must be kept at a fixed voltage using the output mode of the VO for example or an external pull up or pull down resistor Table 31 VO static characteristics O Symbol Parameter Conditions Min Typ Max Unit ViL Input low level voltage Standard I Os Vss 0 3 0 3 x Vpp 7 Viu Input high level voltage Standard I Os 0 70 x Vpp Vppt0 3 Vhys Schmitt trigger voltage hysteresis Standard I Os 200 mV Vss x VIN lt Vpp 50 likg Input leakage current Vss lt Vin lt Vreg RX i i B6 nA Tx VOs Rpy Weak pull up equivalent resistor Vin Vss 30 45 60 kQ Cio VO pin capacitance 5 pF Vpp 3 0 V Ta 40 to 85 C unless otherwise specified Data based on characterization results not tested in production Hysteresis voltage between Schmitt trigger switching leve
71. r TIM4 16 bit general purpose timers The 16 bit timers consist of 16 bit up down auto reload counters driven by a programmable prescaler They perform a wide range of functions including e Timebase generation e Measuring the pulse lengths of input signals input capture e Generating output waveforms output compare PWM and One pulse mode e interrupt capability on various events capture compare overflow break trigger e Synchronization with other timers or external signals external clock reset trigger and enable 8 bit basic timer The 8 bit timer consists of an 8 bit up auto reload counter driven by a programmable prescaler It can be used for timebase generation with interrupt generation on timer overflow DoclD022344 Rev 5 15 83 Product overview STM8TL52x4 STM8TL53x4 3 14 3 15 3 16 3 17 16 83 Beeper STM8TL5xx4 devices include a beeper function used to generate a beep signal in the range of 1 2 or 4 kHz when the LSI clock is operating at a frequency of 38 kHz USART The USART interface USART allows full duplex asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format It offers a very wide range of baud rates e 1 Mbit s full duplex SCI e SPI emulation e High precision baud rate generator e Single wire half duplex mode SPI The serial peripheral interface SPI provides half full duplex synchronous serial communicat
72. r more details IWDG HW ndependent watchdog 0 Independent watchdog activated by software 1 Independent watchdog activated by hardware IWDG HALT independent window watchdog reset on Halt Active halt 0 Independent watchdog continues running in Halt Active halt mode 1 Independent watchdog stopped in Halt Active halt mode OPT4 WWDG HW Window watchdog 0 Window watchdog activated by software 1 Window watchdog activated by hardware WWDG HALT Window watchdog reset on Halt Active halt 0 Window watchdog stopped in Halt Active halt mode 1 Window watchdog continues running in Halt Active halt mode Caution After a device reset read access to the program memory is not guaranteed if address 0x4807 is not programmed to 0x00 d DoclD022344 Rev 5 41 83 Unique ID STM8TL52x4 STM8TL53x4 8 Unique ID STM8TL5xx4 devices feature a 96 bit unique device identifier which provides a reference number that is unique for any device and in any context The 96 bits of the identifier can never be altered by the user The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm The unique device identifier is ideally suited e For use as serial numbers e For use as security keys to increase the code security in the program memory while using and combining this unique ID with software cryptographic primitives and protocols before programming the internal memory e To activate secur
73. register low 0x00 0x00 528D TIM3 PSCR TIM3 prescaler register 0x00 0x00 528bE TIM3 ARRH TIM3 auto reload register high OxFF 0x00 528F TIM3 ARRL TIM3 auto reload register low OxFF 0x00 5290 TIM3 CCR1H TIM3 capture compare register 1 high 0x00 0x00 5291 TIM3 CCR1L TIM3 capture compare register 1 low 0x00 0x00 5292 TIM3 CCR2H TIM3 capture compare register 2 high 0x00 0x00 5293 TIM3 CCR2L TIM3 capture compare register 2 low 0x00 0x00 5294 TIM3 BKR TIM3 break register 0x00 0x00 5295 TIM3 OISR TIM3 output idle state register 0x00 0x00 5296 to Reserved area 74 bytes 0x00 52DF 0x00 52bE0 TIM4 CR1 TIM4 control register 1 0x00 0x00 52E1 TIM4 CR2 TIM4 control register 2 0x00 0x00 52E2 TIM4 SMCR TIM4 Slave mode control register 0x00 0x00 52bE3 TIM4 IER TIM4 interrupt enable register 0x00 0x00 52E4 TIM4 TIM4 SR1 TIM4 Status register 1 0x00 0x00 52E5 TIM4 EGR TIM4 event generation register 0x00 0x00 52E6 TIM4 CNTR TIM4 counter register 0x00 0x00 52E7 TIM4 PSCR TIM4 prescaler register 0x00 0x00 52bE8 TIM4 ARR TIM4 auto reload register low OxFF 32 83 DoclD022344 Rev 5 Ky STM8TL52x4 STM8TL53x4 Memory and register map Table 7 General hardware register map continued Address Block Register label Register name EEE status 0x00 52E9 to Reserved area 23 bytes 0x00 52FF 0x00 5300 PXS CR1 ProxSense co
74. rotocol Refer to Read out protection section in the STM8TL5xxx reference manual RM0312 for details OPT1 UBC 7 0 Size of the user boot code area 0x00 no UBC 0x01 0x02 UBC contains only the interrupt vectors 0x03 Page 0 and 1 reserved for the interrupt vectors Page 2 is available to store user boot code Memory is write protected OxFF Page 0 to 254 reserved for UBC memory is write protected Refer to User boot area UBC section in the STM8TL5xxx reference manual RM0312 for more details DoclD022344 Rev 5 d STM8TL52x4 STM8TL53x4 Option bytes Table 11 Option byte description continued Option byte number Description DATASIZE 7 0 Size of the data EEPROM area 0x00 no data EEPROM area 0x01 1 page reserved for data storage from OxBFCO to OxBFFF OPT 0x02 2 pages reserved for data storage from OxBF80 to OxBFFF 0x20 32 pages reserved for data storage from 0xB800 to OxBFFF Refer to Data EEPROM DATA section in the STM8TL5xxx reference manual RM0312 for more details PCODESIZE 7 0 Size of the proprietary code area 0x00 No proprietary code area 0x03 TRAP vector and page 2 0x8080 to Ox80BF reserved for the proprietary code and read write protected OPT3 ine OxFF TRAP vector and page 2 to 254 0x8080 to OxBFBF reserved for the proprietary code and read write protected Refer to Proprietary code area PCODE section in the STM8TLxxxx Programming Manual PM0212 fo
75. s to 20 mA high sink source capability Power supply pins must be correctly decoupled with capacitors near the pins Please refer to the power supply circuitry details in Section 9 3 2 Power supply on page 46 and the STM8TL5xxx reference manual RMO312 Section 6 Power supply DoclD022344 Rev 5 19 83 Pin description STM8TL52x4 STM8TL53x4 20 83 Figure 4 STM8TL52G4U6 28 pin UFQFPN package pinout TIM3 CH1 SPI_NSS SWIM BEEP TIM3 TRIG TIM3_CH2 TIM3_CH1 TIM2_CH2 TIM2_CH1 T xa a zx xx xa C PA1 HS CI PBO HS CAPD7 HS CI PD6 HS CA PD5 HS 00 N m BR N TIM3_CH2 USART_CK SPI_SCK HS PA2 1 21 PD3 HS I2C SDA USART TX SPI MISO HS PA3E22 20 PD2 HS I2C SCL USART RX SPI MOSI HS PA4E23 19 C PD1 HS PXS_TX1 Voo UFQFPN 18 C PDO HSY PXS TXO 17 CIPXS RX7a PXS_Vrec 6 16CIPXS RX6a NRST HS PA5 7 15 CJ PXS_RX5a LANN N H O e GO 0 0 O G lt lt O S N OK GC O X o X X x 6 o CC cr cm c Fou cer c s 299222 S ZA AA AN rr Lu E gt o o x ry O o x zl o MS30312V1 HS corresponds to 20 mA high sink source capability Power supply pins must be correctly decoupled with capacitors near the pins Please refer to the power supply circuitry details in Section 9 3 2 Power supply on page 46 and the STM8TL5xxx reference manual RM0312 Section 6 Power supply d DoclD022344 Rev 5 STM8TL52x4 STM8TL53x4 Pin description d
76. ster map continued Address Block Register label Register name ea 0X00 531A PXS MAXRH ProxSense maximum counter value register high OxFF 0x00 531B PXS MAXRL ProxSense maximum counter value register low OxFF 0x00 531C PXS MAXENRH ProxSense maximum counter enable register high 0x00 0x00 531D PXS MAXENRL ProxSense maximum counter enable register low 0x00 0x00 531E PXS RXSRH ProxSense receiver status register high 0x00 0x00 531F PXS PXS RXSRL ProxSense receiver status register low 0x00 0x00 5320 PXS RXOCNTRH ProxSense counter register receiver channel high 0x00 0x00 5321 PXS RXOCNTRL ProxSense counter register receiver channel low 0x00 0x00 5322 PXS RX1CNTRH ProxSense counter register receiver channel high 0x00 0x00 5323 PXS RX1CNTRL ProxSense counter register receiver channel low 0x00 0x00 5324 PXS RX2CNTRH ProxSense counter register receiver channel high 0x00 0x00 5325 PXS RX2CNTRL ProxSense counter register receiver channel low 0x00 0x00 5326 PXS RX3CNTRH ProxSense counter register receiver channel high 0x00 0x00 5327 PXS RX3CNTRL ProxSense counter register receiver channel low 0x00 0x00 5328 PXS RX4CNTRH ProxSense counter register receiver channel high 0x00 0x00 5329 PXS RX4CNTRL ProxSense counter register receiver channel low 0x00 0x00 532A PXS RX5CNTRH ProxSense counter register receiver channel high 0x
77. tal 8 RAM PXS analog block voltage PXS VREG N regulator 1 yr MS19607V2 1 Each power supply pair must be decoupled with filtering ceramic capacitors as shown above These capacitors must be placed as close as possible to or below the appropriate pins to ensure the correct functionality of the device The 1uF capacitor must be connected to the Vpp pin The 1uF ceramic capacitor connected to PXS VREG must be low ESR ESR lt 19 Power up power down operating conditions Table 17 Operating conditions at power up power down Symbol Parameter Conditions Min Typ Max Unit tyDD Vpp rise time rate 20 1300 us V trEMP Reset release delay Vpp rising 1 ms VPOR Power on reset threshold 1 440 1 65 V VppR Power down reset threshold 1 300 1 600 V 1 Tested in production 2 Data based on characterization results not tested in production d DoclD022344 Rev 5 STM8TL52x4 STM8TL53x4 Electrical parameters 9 3 4 ProxSense Regulator Voltage Table 18 ProxSense voltage regulator characteristics Symbol Parameter Conditions Min Typ Max Unit 1 Voltage regulator Creg decoupling capacitance ba 1 10 HF Vei Regulated voltage during l i 1 45 l V acquisition 1 The capacitor must be routed as close as PXS VREG as possible x 1cm 2 Equivalent serial resistor s 10
78. te the system clock SYSCLK to the core and the peripherals and to manage clock gating for low power modes This system clock is a 16 MHz High Speed Internal RC oscillator HSI RC followed by a programmable prescaler In addition a 38 kHz low speed internal RC oscillator is used by the Independent watchdog IWDG and Auto wakeup unit AWU I DoclD022344 Rev 5 STM8TL52x4 STM8TL53x4 Product overview 3 9 3 10 3 11 3 12 3 13 I System configuration controller The system configuration controller provides the capability to remap some alternate functions on different I O ports TIM3 channels can be remapped Independent watchdog The independent watchdog IWDG peripheral can be used to resolve processor malfunctions due to hardware or software failures It is clocked by the 38 kHz LSI internal RC clock source and thus stays active even in case of a CPU clock failure Window watchdog The window watchdog WWDG is based on a 7 bit downcounter that can be set as free running It can be used as a watchdog to reset the device when a problem occurs It is clocked from the main clock It has an early warning interrupt capability and the counter can be frozen in debug mode Auto wakeup counter The auto wakeup AWU counter is used to wakeup the device from Active halt mode General purpose and basic timers STM8TL5xx4 devices contain two 16 bit general purpose timers TIM2 and TIM3 and one 8 bit basic time
79. tools sslllsles 80 12 1 Software odla REEDE RR ROB RR de RE ER ADHA DE ere ee eee UR 80 12 1 1 STMBtoolset 2 80 DoclD022344 Rev 5 3 83 STM8TL52x4 STM8TL53x4 Contents 12 4 2 STM STUDIO kc wc eer aem dba dp ena 81 12 1 3 C and assembly toolchains eser 81 12 2 Programming tools de ER WE RR RE RR Rae DRR BR EER RR 81 13 Revision history 1 aca oar acim are QU RE M Nl Ee in re desi EG 82 I 4 83 DoclD022344 Rev 5 STM8TL52x4 STM8TL53x4 List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Ly Device sumtmaty c 2 22 ER PA BANAT Rma y OE EE OE OE OE EES 1 Device features EE EE EE EE Ee ee Ee ee ee ee ee es 10 Legends abbreviations e EE EE EE EG eee eee 22 STM8TL5xx4 pin description EE EE 000 cece ees 22 Flash and RAM boundary addresses EE cette eae 27 VO Port hardware register map EE EE Ee SE ee n 27 General hardware register map e rn 28 CPU SWIM debu
80. umes processing d ProxSense activated before executing HALT instruction DoclD022344 Rev 5 The device is woken up from Halt or Active halt mode only when the address received matches the interface address 39 83 Option bytes STM8TL52x4 STM8TL53x4 7 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device They are stored in a dedicated row of the memory All option bytes can be modified only in ICP mode with SWIM by accessing the EEPROM address See Table 10 for details on option byte addresses Refer to the STM8TL5xxx Flash programming manual PM0212 and STM8 SWIM and debug manual UM0470 for information on SWIM programming procedures Table 10 Option bytes Option Option bits Factory Addr Option name byte default No 7 6 5 4 3 2 1 0 setting Read out 0x4800 protection ROP OPTO ROP 7 0 OxAA 0x4801 Must be programmed to 0x00 0x00 User Boot code 0x4802 size UBC OPT1 UBC 7 0 0x00 0x4803 DATASIZE OPT2 DATASIZE 7 0 0x00 0x4807 PCODESIZE OPT3 PCODESIZE 7 0 0x00 Window watchdog OPT4 WWDG WWDG IWDG IWDG 0x4808 and independent 3 0 Reserved HALT HW HALT HW 0x00 window watchdog 40 83 Table 11 Option byte description OPTO Option byte number Description ROP 7 0 Memory readout protection ROP OxAA Readout protection disabled write access via SWIM p
81. up to 32 Kbytes of code is available STM8 toolset STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www st com This package includes ST Visual Develop STVD Full featured integrated development environment from ST featuring e Seamless integration of C and ASM toolsets e Full featured debugger e Project management e Syntax highlighting editor e Integrated programming interface ST Visual Programmer STVP Easy to use unlimited graphical interface allowing read write and verify of your STM8 microcontroller Flash program memory data EEPROM and option bytes STVP also offers project mode for saving programming configurations and automating programming sequences I DoclD022344 Rev 5 STM8TL52x4 STM8TL53x4 STM8 development tools 12 1 2 12 1 3 12 2 I STM STUDIO STM STUDIO helps debug and diagnose STM8 and STM32 applications while they are running by reading and displaying their variables in real time STM STUDIO perfectly complements traditional debugging tools to fine tune applications It is well suited for debugging applications which cannot be stopped such as TouchSensing applications Its easy to use graphical interface features e Non intrusive read on the fly variables from RAM while the application is running e Parse DWARF debugging information in the ELF application executable file e Possibility to log data into
82. ximum ratings electrical sensitivity on Vesp voltage page 69 1 All power Vpp Vppio and ground Vss Vssjo pins must always be connected to the external power supply Vin maximum must always be respected Refer to Table 14 for maximum allowed injected current values Current injection on these pins is not allowed d 44 83 DoclD022344 Rev 5 STM8TL52x4 STM8TL53x4 Electrical parameters 9 3 9 3 1 d Table 14 Current characteristics Symbol Ratings Max lypp Total current into Vpp power line source 80 lyss Total current out of Vss ground line sink 80 Output current sunk by any other I O and control pin 25 lo Output current source by any VOs and control pin 25 ngin Injected current on PA pins 5 lINJ PIN Injected current on PB pins 0 liNJ PIN Injected current on PD pins 0 lingen Total injected current sum of all VO and control pins 25 Unit mA 1 liny PIn must never be exceeded This is implicitly insured if Vin maximum is respected If Vin maximum cannot be respected the injection current must be limited externally to the li pin value A positive injection is induced by Vin gt Vpp while a negative injection is induced by Vin lt Vss For true open drain pads there is no positive injection current and the corresponding Viy maximum must always be respected 2 When several inputs are submitted to a current injection the

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