Compact Flash and 8260 Interface Design Guide System Solutions
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1. 31 0b000000 Machine address RAM address pointer for the command executed This field is incremented by 1 each time the UPM is accessed and the OP field is set to WRITE or READ Set when programming RAM array MPC8260 PowerQUICC II User s Manual 4 1999 Rev 0 MPC8260 PowerQUICC II Users Manual Errata 8 2000 Rev 1 14 4 0 Schematic VCC 3 3V Power On Reset 8260 RESET CS0 CS1 IORD IOWR A0 A2 A3 A10 D0 D15 INTRQ ATA SEL CSEL REG WE Compact Flash MPC8260 PowerQUICC II User s Manual 4 1999 Rev 0 MPC8260 PowerQUICC II Users Manual Errata 8 2000 Rev 1 15 5 0 Software Notes Although you could write your own IDE driver most real time operating systems like VxWorks already provide either an ATA or IDE driver The IDE driver sends the appropriate ATA commands to the CompactFlash Ideally no additional driver software needs to be written however it will be necessary to the base address from the primary IDE port 1FOh to the value associated with the chip select Software may want to take advantage of CompactFlash s INTRQ interrupt request to notify the 8260 processor when the CompactFlash is ready Alternatively one can poll the busy bit of the status register to determine when the CompactFlash is ready Please note When programming the RAM array for the UPM a single byte access is needed after loading each RAM value into the UPM 6 0 Conclusion CompactFlash cards are a w2. PC Card I O Mode In the PC Card I O mode the task file registers are mapped into I O address space There are 3 address range options e xxOh xxFh contiguous I O e 1FOh 1F7h primary IDE e 170h 177h secondary IDE The value in the card configuration option register address 200h in attribute memory space determines whether the task files are mapped to common memory space or one of the 3 I O ranges The default is to map the task files to common memory space True IDE Mode In the True IDE mode the task file registers are also mapped into I O address space The True IDE mode is selected if the OE pin also called ATA SEL is grounded by the host at power up In this mode neither the attribute memory nor the card configuration registers are accessible Only accesses to the task file registers is possible e Oh 7h main task file registers CE1 L e 6h alternate task file register CE2 L Which Mode to Choose Of the three interface methods which should you choose If your system requires hot insertion and removal i e insertion or removal of the card while the system is powered then you should have a PCMCIA controller in your system which will access the card in both PC card modes The PCMCIA controller will provide all the glue logic necessary to connect the host system bus to the CompactFlash card However if you want to connect your system bus directly to a CompactFlash card without using a PCMCIA controller or
3. Compact Flash and 8260 Design Guide is subject to change without prior notice at TAEC s sole discretion All trademarks trade names product and or brand names are the property of their respective holders Table of Contents Introduction Discussion of Operating Modes Hardware Notes 3 1 General Information 3 2 1 0 Signals 3 3 Timing Schematic Software Notes Conclusion References 7 1 Datasheets 7 2 Toshiba Website 7 3 Contact Information an son 16 16 16 16 16 16 This page left intentionally blank 1 0 Introduction The CompactFlash card is a small removable storage and I O card Invented by Sandisk the specifications are now determined by the CompactFlash Association CFA http Avww compactflash org a non profit corporation that promotes the adoption of CompactFlash The CompactFlash can be used in such applications as portable and desktop computers digital cameras handheld data collection scanners PDAs Pocket PCs handy terminals personal communicators advanced two way pagers audio recorders monitoring devices set top boxes and networking equipment Every embedded system is different This application note describes a possible interface between a CompactFlash Card and Motorola s MPC8260 microprocessor With minor variations the interface can be adapted to other microprocessors as long as the Compact Flash will not be removed or added while the system is on 2 0 Disc
4. 8260 s GPCM General Purpose Chip Select Machine would have been easier to use its timing violates Compact Flash timing A more flexible approach uses 8260 s UPM Universal Programmable Machine to generate the required timing 8260 s GPL1 and GPL2 were chosen to control CompactFlash s IORD and IOWR Connecting Compact Flash s INTRQ to an Interrupt Input on the 8260 is recommended although not required If it is found that polling the status register is inefficient an interrupt service routine could be implemented Any interrupt pin can be used 8260 s IRQO was chosen as an example CompactFlash s RESET line was directly connected to power on reset in order to guarantee a reset to the card for every power up If the CF RESET was tied to a port pin software to the 8260 must remember to reset the card Otherwise the default state of the port pin may be continuously resetting the card MPC8260 PowerQUICC II User s Manual 4 1999 Rev 0 MPC8260 PowerQUICC II Users Manual Errata 8 2000 Rev 1 7 3 2 LO Signals CompactFlash connection True IDE mode mments onnect to system power on reset onnect to chip select 0 nnect to chip select 1 onnect to GPL1 onnect to GPL2 onnect AO A2 ground A3 A10 onnect to data bus bits 0 15 optional interrupt request to host x O O O C C 0 D15 qata bits 0 15 NTRQ nterrupt request to host Enables True IDE Mode Connect to ground 16 bit transfer ot connected host a
5. bank is valid Indicates that the contents of the BRx and Orx pair are valid The CS signal does not assert until V is set The following contains the recommended values for OR x as described in Table 10 6 from the 8260 User s Manual page 10 20 Orx Table 10 6 Option Register UPM Mode pg 10 20 Bits Name __ Value___ Desoription C o 0 16 JAM jamlts Address mask 0b11111111111111111 are f 600 Reserved shoud be cleared 5 BCTLD Data buffer control disable 0b1 BCTLx is not asserted upon access to the current memory bank 10 2 7 Reserved should be cleared 2 B oo Burst inhibit Ob0 bank supports burst accesses 24 28 A 0b00000 Reserved should be cleared 29 30 EHTR 0b00 Extended hold time on read accesses No additional cycles are inserted between a read access from the current bank and the next access MPC8260 PowerQUICC II User s Manual 4 1999 Rev 0 MPC8260 PowerQUICC II Users Manual Errata 8 2000 Rev 1 10 Write Patterns into the RAM Array The following two tables shows how read and write timing was calculated for RAM Array True IDE Access Read AC Characteristics Data delay afer1ORD far ss 23 07 a Data hold folowing ORD n ORD of s o fORDwitime Moo faf Ins sasas O e Taos setup before IORD STORD 1 98019802 Address holi folowing ORO nA IORD 20 e Tsovtaeotal 2 CE sep before ORD suCE ORD o ns o o reel CE hold fo
6. glue logic then the True IDE mode will probably prove to be easier The main disadvantage is that hot insertion and removal will not be possible because of the probable disruption of signals on the system bus The main reason it will be easier to use the True IDE mode is because only CE1 needs to be asserted low to perform a 16 bit read or write to the data register In order to do a 16 bit read or write in a PC Card mode both CE1 and CE2 must be asserted low simultaneously which generally requires some custom glue logic AT Task Files True IDE mode CE2 CE1 Addr Read IORD L Write IOWR L 1 0 Oh Data Register 16 bit Data Register 16 bit th Error Register Feature Register Sector Count Register Sector Count Register Cylinder High Register C Drive Head Register Drive Head Register Status Register Command Register A D It Status Register evice Control Register rive Address Register ylinder High Register Since most RTOSes real time operating systems such as VxWorks have device drivers for ATA IDE drives the software integration effort is significantly reduced Ideally only the AT task file base address needs to be modified in a typical embedded system 3 0 Hardware Notes 3 1 General Information Please refer to Section 4 0 for the Schematic While the MPC8260 s core runs at 2 5V its I Os are at 3 3V which is compatible with the CompactFlash signals which can be at either 3 3V or 5V Although
7. Compact Flash and 8260 Interface Design Guide System Solutions from Toshiba America Electronic Components Inc Systems Application Engineering SAE Jean Chao Sr MTS Doug Wong Staff MTS Memory Business Unit Revision 1 1 August 2001 Prepared by Systems Application Engineering Team TOSHIBA AMERICA ELECTRONIC COMPONENTS INC Copyright 2001 by Toshiba America Electronic Components Inc All Rights Reserved This Compact Flash and 8260 Interface Design Guide and the information and know how it contains constitute the exclusive property and trade secrets of Toshiba America Electronic Components Inc TAEC and may not be reproduced or disclosed to others without the express prior written permission of TAEC Any permitted reproductions in whole or in part shall bear this notice The information in this Compact Flash and 8260 Design Guide has been checked and is believed to be reliable however the reader understands and agrees that TAEC MAKES NO WARRANTY WITH RESPECT TO THIS DESIGN GUIDE ITS CONTENTS OR THEIR ACCURACY AND EXCLUDES ALL EXPRESS AND IMPLIED WARRANTIES INCLUDING WARRANTIES OF FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR NON INFRINGEMENT The reader further understands that he or she is solely responsible for all use of the information contained within including but not limited to securing any necessary intellectual property rights however denominated All information in this
8. ICC II User s Manual 4 1999 Rev 0 MPC8260 PowerQUICC II Users Manual Errata 8 2000 Rev 1 12 en wid LLL UU UU 2294 Write Address CS0 R CS1 tsuCE IOWR U IhcE IOW twelOwW R IOWR GPL2 _ suA OWR lt HAIOWR gt tsu IOWR si lust o ol ol o o o MPC8260 PowerQUICC II User s Manual 4 1999 Rev 0 MPC8260 PowerQUICC II Users Manual Errata 8 2000 Rev 1 13 Program MxMR The following contains the recommended values for MxMR as described in Table 10 9 from the 8260 User s Manual page 10 27 MxMR Table 10 9 Machine x Mode Registers pg 10 27 Name Value Description BSEL Bus Select Assigns banks that select UPMx to the 60x or local bus 0b0 60x RFEN 0b0 Refresh enable 0b0 Refresh services are not required 2 3 0b00 Command opcode Determines command executed by UPMx when a memory access hits a UPM assigned bank 0b00 Normal operation a ooo Reserves should be cleared Address multiplex size See 10 6 4 2 ss Ds o Disable timer period a GOCLx 06000 General line 0 control GPLO is not used 3 GPLxAaDIS obo GPL_A4 output line disable These lines are not use 17 RLFx 0b0001 Read loop field Determines number of times a loop defined in the UPMx will be executed for a burst or single beat read pattern or when MxMR OP 11 0001 loop is executed 1 time Not used Write loop field See RLFx Not used 0b0001 Refresh loop field Doesn t matter
9. R thUOWR 30 Ins 19 2 JORD width time __ wdowWR _ 80 Ins 52 6 Address setup before IOWR tsuAGOWR 30 Ins 19 2 Address hold following thA IOWR 20 ns 13 2 IOWR CE setup before IOWR _ tsucElOWR of ins 15 CE hold following IOWR_ thCEGOWR of Is 15 ee Ri Pr address Fee a address In order to meet these timing requirements the UPM has to be programmed The details specific to the 8260 UPM are e Set up BRx Base Register and OR x e Write patterns into the RAM array e Program MxMR Machine Mode register Note MTPTR and L PSRT are needed because we do not need to refresh the Compact Flash MPC8260 PowerQUICC II User s Manual 4 1999 Rev 0 MPC8260 PowerQUICC II Users Manual Errata 8 2000 Rev 1 Setup BRx and ORx The following contains the recommended values for BRx as described in Table 10 3 from the 8260 User s Manual page 10 14 BRx Table 10 3 Base Register pg 10 14 Description Base address Used with Orx BSIZE Reserved should be cleared Specifies port size of memory region 10 16bit ire 0b00 Data error correction checking 0b00 no parity a Ww no Wt Protect 0 read and write accesses are allowed Machine Select 100 UPMA E EMEVG External MEMC enable 0b0 access are handled by the memory controller according to MSEL 10 2 10 2829 ATOM Atomic Operation 0b00 no atomic operations a mn o Data pipelining 0b0 no data pipelining is done Valid bit Ob1 this
10. idely available solution for systems requiring a compact solid state mass storage system Because they interpret standard ATA disk drive commands little or no software development is necessary because software drivers for ATA devices already exist for most operating systems The hardware interface for each system may need to be customized but as indicated in the example presented the chipset may already possess the capability to interface gluelessly to CompactFlash If a PCMCIA controller is not present in the system it will be easier to interface using the True IDE mode assuming hot insertion and removal is not a requirement 7 0 References 7 1 Datasheets THNCFxxxMAA Series Compact Flash Card datasheet 3 2001 MPC8260 PowerQUICC II User s Manual 4 1999 Rev 0 MPC8260 PowerQUICC II Users Manual Errata 8 2000 Rev 1 7 2 Toshiba Website ww toshiba com taec 7 3 Contact Information Toshiba welcomes your feedback on this document Please send any comments and ideas to TAEC eSupport at Tech Questions taec toshiba com MPC8260 PowerQUICC II User s Manual 4 1999 Rev 0 MPC8260 PowerQUICC II Users Manual Errata 8 2000 Rev 1 16
11. llowing IORD EO O bs C C l IOIS16 delay falling from address tdflOlISi6 ADR 35ns 2310234023 2 IOIS16 delay rising from address tdrlOIS16 ADR 35ns 2310234023 True IDE Access Write AC Characteristics Data setup before IOWR tsu IOWR 2 640264026 Data hold following IOWR th IOWR 1 98019802 IORD width time tw IOWR 80 Ins 5 280528053 6 Address setup before TOWR _ isuTOWA 30 ns 9809802 gt Address hold folowing OWR thAOWR 20 s T 2013205 2l CE setup before IOWR _ _ isuE OwR O pj GE hold ofowing owe ICE of ps 1 IOIS16 delay falling from address OSOASA 35 ns 2 310231023 IOIS16 delay rising from address tsflOIS16 ADR 35 ns 2 310231023 MPC8260 PowerQUICC II User s Manual 4 1999 Rev 0 MPC8260 PowerQUICC II Users Manual Errata 8 2000 Rev 1 11 The following two figures show the timing diagrams and the values which must be programmed into the RAM array These values allow the UPM to generate the required timing for the Compact Flash TRUE IDE ck Tart LE LE LI l T l l LIL Ll Read pees x x x x Address i i H CS0 amp CS1 x Kcen IORD GPL1 ja tsuA IDRD aor thCE IORD ADR tdflO1S16 Data 11 GOH 12 am 1 1 o o J o qas Gt q q 6 6 C C u 3 15 Gara 1 h h I _ 31 east o o o o Solo MPC8260 PowerQU
12. ssumes 16 bit transfer able select master slave Connect to ground enable card as master IORDY VO ready ot connected ot connected no slave drive ot connected no slave drive z O lt PDIAG Passed diagnostic ZIZ ASP drive active slave present D1 CD2 card detect ot connected hot insertion not supported S1 VS2 oltage sense ot connected NPACK input acknowledge ot connected REG ttribute memory enable ot used in True IDE mode connect to Vcc WE write enable ot used in True IDE mode connect to Vcc n I 8260 Pins Description Chip Select Chip Select 60x bus General Purpose line 1 RQ0 MPC8260 PowerQUICC II User s Manual 4 1999 Rev 0 MPC8260 PowerQUICC II Users Manual Errata 8 2000 Rev 1 8 3 3 Timing In order to interface to the CompactFlash it is necessary to meet the I O read and write timing requirements shown below True IDE Read Access AC Timing Parameter symbol Rounded Sd 0 Data delay after ORD__ tdIORDD Data hold following IORD_ th IORD 0 TORD w time 2 w oRD 80 3 Address hold following thA IORD IORD CE setup before IORD tsuCE IORD 0 ns 1 5 CE hold following IORD hCEIORD of ns 1 IOIS16 delay falling from tdflOISI6 ADR 35 ns 23 2 address True IDE Write Access AC Timing Parameter symbol min typ max Junit clock Rounded cycles up down Data setup before IOWR _ tsulOWR 40 Ins 26 3 Data hold following IOW
13. ussion of Operating Modes A CompactFlash card is essentially a small form factor card version of PCMCIA PC Card ATA AT Attachment specification and includes a True IDE Integrated Drive Electronics mode which is compatible with the ATA ATAPI 4 specification As such there are 3 distinct interface modes that a CompactFlash card can use e PC Card Memory Mode uses WE OE to access memory locations e PC Card I O Mode uses IOWR IORD to access I O locations e True IDE Mode uses IOWR IORD to access I O locations The CompactFlash card is essentially a solid state ATA disk drive To control an ATA disk drive one writes to the task file registers The values put into these task file registers control the drive the ANSI T13 committee defines these registers and the commands used to control all ATA IDE drives see These task file registers can be mapped into either memory or I O address space PC Card Memory Mode In the PC Card memory mode the task file registers are mapped into common memory space REG pin H When mapped to common memory space the task files appear at address e Oh Fh When the REG L the card s attribute memory is accessed This is where the card s configuration registers and CIS card information structure also known as metaformat is stored The CIS contains information about the type of card inserted and is used to configure a system to recognize different types of cards and load the correct drivers
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