EVBUM2265 - AD9945 Timing Generator Board User`s Manual
Contents
1. and supplied by ON Semiconductor Changes to the firmware are at the risk of the customer ORDERING INFORMATION Please address all inquiries and purchase orders to Truesense Imaging Inc 1964 Lake Avenue ON Semiconductor reserves the right to change any information contained herein without notice information furnished by ON Semiconductor is believed to Rochester New York 14615 be accurate Phone 585 784 5500 E mail info truesenseimaging com ON Semiconductor and the Q are registered trademarks of Semiconductor Components Industries LLC SCILLC or its subsidiaries in the United States and or other countries SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary2. over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT Literature Distribution Center for ON Semiconductor P O Box 5163 Denver Colorado 80217 USA Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Fax 303 675 2176 or
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4. EVBUM2265 D AD9945 Timing Generator Board User s Manual Timing Generator Board Description This Timing Generator Board is designed to be used as part of a two board set used in conjunction with a ON Semiconductor CCD Imager Evaluation Board ON Semiconductor offers a variety of CCD Imager Boards that have been designed to operate with this Timing Generator Board For more information on the available Imager Evaluation Boards see the ON Semiconductor contact information at the end of this document The Timing Generator Board generates the timing signals necessary to operate ON Semiconductor Imager Boards and also provides the power required by these Imager Boards via the board interface connector J6 In addition the Timing Generator Board performs the signal processing and digitization of the analog output of the Imager Board Up to two analog outputs of the Imager Board are connected to the Timing Generator Board via coaxial cables The KSC 1000 Timing Generator chip provides multiple pixel rate line rate and frame rate clocks and control signals to operate ON Semiconductor CCD image sensors The KSC 1000 is able to operate many different Interline Full Frame and Linear CCD image sensors ON Semiconductor http onsemi com EVAL BOARD USER S MANUAL The Timing Generator Board contains an Altera Programmable Logic Device PLD that can be In System Programmed ISP with code that is imager specif
5. d to their default settings via the three wire serial interface The default settings are specific to each CCD Imager Board configuration and are detailed in the associated Timing Specification document Timing Board PN Analog Devices PN Sampling Rate Bit Depth Auxiliary PLD functions The Altera PLD may provide auxiliary timing and control functions for a particular CCD Imager Board In addition to the Configuration switches Remote Digital Inputs and 3 wire Serial Interface the inputs to the PLD include timing signals from the 5 1000 The PLD outputs include PLD 2 0 auxiliary outputs which are routed to the Board Interface connector 75 HD TG and VD timing controls signals to KSC 1000 and ARSTZ an asynchronous reset to the KSC 1000 These inputs and outputs allow the Altera PLD to monitor the CCD timing and to control auxiliary functions as needed There are several PLD connections that are connected only to test points These may be configured as PLD outputs or inputs for extra monitoring or control Video Signal Processing Each of the two signal processing channels is designed to process an analog video signal input from a CCD Imager Board The analog video signal is buffered by an operational amplifier This amplifier is in non inverting configuration with a gain of 1 25 The output of the amplifier is then AC coupled into the input of the AFE chip Since the amplitude of AFE input is limited care mu
6. digital input control lines to the board are buffered a particular Evaluation Boardset and is detailed in the The input pins to the buffer IC s are weakly held low by pull associated Altera Code Timing Specification This is an down resistors to GND Therefore with no digital inputs the optional feature no external digital inputs are required for default level of the control lines is all zeros board operation http onsemi com 2 EVBUM2265 D A three wire serial interface is also provided on the J3 input connector The Altera PLD is programmed to decode the serial datastream and steers the datastream to the KSC 1000 and the AFE chips as necessary Therefore the 5 1000 and each of the two AFE chips may be adjusted independently of one another via the serial interface overriding the default settings stored in the Altera PLD This is an optional feature and is not required for board operation Configuration Switches There are four switches on the board that can be used to adjust the operating mode of the Timing Generator Board The function of the switches depends on how the Altera device is programmed for a particular Evaluation Boardset and is detailed in the associated Altera Code Timing Specification JTAG Header This 10 pin header J4 provides the user with the ability to reprogram the Altera PLD in place via Altera s BYTEBLASTER programming hardware Purchasers of a ON Semiconductor Evaluation Board Kit may at thei
7. e via the 100 pin SCSI output connector J9 using Low Voltage Differential Signaling LVDS drivers LVDS combines high speed connectivity with low noise and low power SCSI Digital Output Connector This 100 pin connector J9 provides digitized image data and synchronization timing signals to the computer Table 6 KSC 1000 REGISTERS frame grabber hardware The output connector interfaces directly to the National Instruments PCI 1424 frame grabber providing two channels of 12 bit output data in parallel in LVDS differential format The connector also provides the three necessary PCI 1424 frame grabber synchronization signals in LVDS differential format KSC 1000 Timing Generator The KSC 1000 controls the overall flow of the evaluation board operation The TG outputs include the CCD clocks signals AFE timing signals and Frame Grabber synchronization signals The KSC 1000 is configured by programming Registers Frame Tables and Line Tables Register Address e peon Te 3 asa A E o p meme 0 3 Signal Polarity Offset Wiath Frame Table Access Status See the KSC 1000 specification sheet Reference 3 for details http onsemi com 5 EVBUM2265 D CONNECTOR ASSIGNMENTS AND PINOUTS SMB Connectors J1 and J2 J1 Channel 1 and J2 Channel 2 allow connection of analog video signal s from the CCD Imager Boards through correctly terminated 75 2 coaxial cable Digital Inpu
8. ic This provides flexibility to operate many different Imager Boards with the same Timing Generator Board The Timing Generator Board has a digital Input interface to the Altera device that can be used to support various modes of operation depending on imager specific Altera code The digital input interface also includes a serial interface to the KSC 1000 and AFE parts on the Timing Generator Board so that adjustments may be made to their operation overriding the pre programmed default operating conditions Board Configuration de Power Connector onnector Reset Switches System 45V 5V 20V 20V witch Switc SWIS 0 Oscillator i 5 POWER_ON_DELAY 33V 33V 1 8V 8 m Analog Digital Analog seria amp o Regulator Regulator Regulator 8 Ne 5 5 10015 0 3 PLD QUTI19 0 a om INTEGRATE a 2 Altera PLD g 9 5 SHDx a 9 START 5 LINE VALID 9 FRAME VALID KSC 1000 a S AMPAEN Timing E 9 Generator c 3 VALID FRAME VALID DATACLK a gt CHANNEL 1 2 5 SLOAD AFE1 o D a gt 155 anag Line Receiver e 2 Front End E Channel 1 o Video In e o Analog Line Receiver a _ Front End Op Amp Integrate Channel 2 SLOAD AFE2 Video In Figure 1 3F5592 Timing Generator Board Block Diagram O Semiconductor Compo
9. n the board In this way the Altera device is programmed with imager specific code to operate the Imager Board to which the Timing Generator Board will be connected The code implemented in the Altera PLD is specific to each CCD Imager Board configuration and is detailed in the associated Timing Specification document At a minimum the Altera PLD must provide these functions Decode and steer serial input data to the correct device Program the KSC 1000 with default settings e Program the AFE chips with default settings In addition to these functions the Altera PLD may provide auxiliary timing and control functions for a particular CCD Imager Board Refer to the appropriate Timing Specification for details Serial Input Steering When the three wire serial input to the Timing Board is used the Altera PLD decodes the addressing of the serial input and steers the datastream to the correct device The serial input must be formatted so that the Altera PLD can correctly decode and steer the data to the correct device The first 3 bits in the datastream are the Device Select bits DS 2 0 sent MSB first as shown in Figure 2 The Device Select bits are decoded as shown in Table 3 010 AFE2 011 KSC 1000 Imager Board Dependent Imager Board Dependent Imager Board Dependent http onsemi com EVBUM2265 D The next bit in the datastream is the Read Write bit R W Only writing is supported the
10. nents Industries LLC 2014 1 Publication Order Number October 2014 Rev 2 EVBUM2265 D EVBUM2265 D TIMING GENERATOR BOARD INPUT REQUIREMENTS The input power may be supplied by standard linear guidelines for these requirements are shown in Table 1 refer benchtop power supplies as long as they meet the to the appropriate Timing Specification for the input power requirements of a particular Evaluation Boardset General requirements of a particular Evaluation Boardset Table 1 POWER SUPPLY INPUT REQUIREMENTS Power Supplies Minimum Typical EH NE Ml SS SSS E e DEN mA VPLUS Supply Imager Board Dependent VMINUS Supply 18 20 Imager Board Dependent TIMING GENERATOR BOARD ARCHITECTURE OVERVIEW The following sections describe the functional blocks of Power On Delay Board Reset the Timing Generator Board See Figure 1 for a block The POWER_ON_DELAY signal provides a reset signal diagram to the Altera Programmable Logic Device PLD on power up or when the BOARD RESET button S1 is Power Connector pressed The delay is generated by an RC network into The J7 power connector provides the necessary power a Schmitt trigger and is approximately 400 ms allowing supply inputs to the Timing Generator Board The connector power supply voltages to stabilize on the board When the also provides the VPLUS and VMINUS power supplies POWER ON DELAY signal goes high the PLD will These s
11. or J7 Table 11 POWER CONNECTOR J7 VMINUS 8 AGND Configuration Switches S2 Table 12 CONFIGURATION SWITCHES S2 Altera Code Dependent Altera Code Dependent Altera Code Dependent Altera Code Dependent Output Connector J9 Table 13 OUTPUT CONNECTOR J9 Signal Level AOUT3 LVDS AOUT4 LVDS AOUT5 LVDS AOUT6 LVDS AOUT7 LVDS AOUT8 LVDS MOE LVDS LVDS LVDS 20 22 24 6 2 http onsemi com 8 EVBUM2265 D Table 13 OUTPUT CONNECTOR J9 continued 39 N C 40 N C 41 FRAME LVDS 42 FRAME LVDS 43 LINE LVDS 44 LINE LVDS 45 N C 46 N C BOUT7 BOUT8 BOUT9 http onsemi com 9 EVBUM2265 D WARNINGS AND ADVISORIES ON Semiconductor is not responsible for customer damage to the Timing Board or Imager Board electronics The customer assumes responsibility and care must be taken when probing modifying or integrating ON Semiconductor Evaluation Board Kits When programming the Timing Board the Imager Board must be disconnected from the Timing Board before power is applied If the Imager Board is connected to the Timing Board during the reprogramming of the Altera PLD damage to the Imager Board will occur Purchasers of a ON Semiconductor Evaluation Board Kit may at their discretion make changes to the Timing Generator Board firmware ON Semiconductor can only support firmware developed by
12. r discretion make changes to the Altera code firmware ON Semiconductor Inc can only support firmware developed and supplied by ON Semiconductor Inc Changes to the Altera code firmware are at the risk of the customer When programming the Altera PLD via the JTAG interface the Imager Board must be disconnected from the Timing Board by removing the Board Interface Cable before power is applied If the Imager Board is connected to the Timing Board during the reprogramming of the Altera PLD damage to the Imager Board may occur Integrate Output Connector This output header J6 provides a signal that is high during the integration time period INTEGRATE can be used to synchronize an external shutter or LED light source with the integration time period Table 3 SERIAL INPUT DEVICE SELECT Device Select DS 2 0 Serial Device Image Sensor LVDS Drivers Timing signals are sent to the Imager Board via the board interface connector J5 using Low Voltage Differential Signaling LVDS drivers LVDS combines high speed connectivity with low noise and low power Board Interface Connector This 80 pin connector J5 provides both the timing signals and the necessary power to the CCD Imager Boards from the Timing Generator Board Altera PLD The Programmable Logic Device PLD is an Altera Flex 10K series part Paired with an EPC2 configuration EPROM the Altera device is In System Programmable ISP via a 10 pin JTAG header J4 located o
13. refore this bit is always LOW The definition of next four bits in the datastream depends on the device being addressed with the Device Select bits For the KSC 1000 device they are Register Address bits A 3 0 LSB first For the AD9945 AFE they are Register Address bits A 2 0 LSB first followed by a Test bit which 1s always set LOW The remaining bits in the bitstream are Data bits LSB first with as many bits as are required to fill the appropriate register Figure 2 Serial Input Timing The Altera PLD receives the serial datastream decodes the Device Select address contained in the first 3 bits and sets the appropriate SLOAD line LOW The remaining datastream is then read in real time by the selected device The Altera PLD does not do any checking of the datastream for correctness it merely steers the data to the appropriate device 5 1000 Default Programming Upon power up or whenever the BOARD_RESET button is pressed the Altera PLD automatically programs the registers of the KSC 1000 to their default settings via the Table 4 TIMING BOARD CONFIGURATION OPTIONS three wire serial interface The default settings are specific to each CCD Imager Board configuration and are detailed in the associated Timing Specification document AFE Default Programming Upon power up or whenever the BOARD RESET button is pressed the Altera PLD programs the registers of the two AFE chips on the AFE Timing Generator Boar
14. st be taken to adjust the gain of the Imager Board signal prior to the AFE input The Imager Board for a particular CCD image sensor has been designed to deliver a video signal with the correct amplitude to the Timing Board such that when the AFE is correctly configured optimum performance is achieved http onsemi com 4 EVBUM2265 D AD9945 Analog Front End AFE Device The Timing Generator Board has two analog input channels each consisting of an operational amplifier buffer and an Analog Front End AFE device The AFE chip processes the video signal then performs the A D conversion and outputs 12 bits of digital information per Table 5 AFE REGISTERS Register Address Register Description Operation pixel The Timing Generator Board supports the AD9945 AFE device offered by Analog Devices Inc Refer to the Analog Devices AD9945 Specification Sheet Reference 2 for details on the operation of this Analog Front End Control Clamp Level VGA Gain See the AD9945 specifications sheet Reference 2 for details The AFE registers can be adjusted by re programming the registers using the three wire serial interface provided on the Digital Input Connector Each AFE is independently addressable through the Altera PLD and therefore can be adjusted independently Digital Image Data LVDS Drivers Digitized image data and synchronization timing signals are sent to the computer frame grabber hardwar
15. t Connector J3 Table 7 DIGITAL INPUT CONNECTOR J3 Assignment Function Altera Code Dependent z z ziziz OJ o UO 2 Altera Code Dependent 2 Altera Code Dependent 2 Altera Code Dependent DIO10 Altera Code Dependent 10 2 10 2 U Altera Code Dependent wl n O O o0 o0 o0 o 2 2 2 1212 2 o ojoj U U U aln BLM Ol o A N oJ ojoj QO 2 U 2 Altera Code Dependent 2 2 Not Used m 9 11 13 15 35 37 39 JTAG Connector J4 Table 8 JTAG CONNECTOR http onsemi com 6 EVBUM2265 D Board Interface Connector J5 Table 9 BOARD INTERFACE CONNECTOR J5 Pin Assignment Pin Assignment TIMING OUTO 2 TIMING OUTO AGND AGND 3 AAA AA EA RT 11 13 15 17 19 1 4 4 AGND 47 49 23 AGND 2 AGND 25 TIMING_OUT6 26 TIMING OUT6 27 AGND 28 AGND 29 TIMING OUT7 3 TIMING OUT7 0 50 AGND 51 TIMING 0 12 52 TIMING OUT12 53 20 V IMG 55 57 59 61 63 65 67 71 73 75 77 79 5 20 V IMG 4 http onsemi com 7 EVBUM2265 D Integrate Sync Connector J6 Table 10 INTEGRATE SYNC CONNECTOR J6 Pin Assignment Function 1 INTEGRATE Signal is High during Integration Time Period 2 AGND Power Connect
16. upplies are not used by the Timing Generator Board perform its normal power up initialization sequence as but are needed by the CCD Imager Boards The Timing detailed in the applicable Timing Specification Generator Board simply routes these power supplies from the power connector to the board interface connector System Clock The System Clock is used to generate the pixel rate clocks Power Supply Filtering The pixel rate timing signals operate at a frequency that is Power supplied to the board is de coupled and filtered divided down from the System Clock frequency The exact with ferrite beads and capacitors in order to suppress noise pixel rate frequency is Altera code dependent but is limited For best noise performance linear power supplies should be to 1 2 the frequency of the System clock used to provide power to the boards Table 2 TIMING BOARD CLOCK RATES Timing Board PN System Clock Pixel Clock Max 3F5592 40 MHz 20 MHz Digital Input Connector The digital input connector 13 connects optional remote Any TTL compatible digital controls may be used to digital control signals to the evaluation board These control control these lines While it is recommended that these signals DIO 15 0 can be used to adjust the operating inputs range between 3 3 V HIGH and LOW mode of the evaluation board The function of the digital voltages up to 5 0 V are acceptable inputs depends on the Altera firmware programmed for The
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