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AD27uD|ADA2700 User`s Manual - RTD Embedded Technologies

1. 0000000 000000 00000000 00 2 ops 55 ws 82055 66 lt erm 999999 me US 0000000000 pe 2 2 00000000009 0000000000 Bue 1 CRA 5 O 2 5555509 5555801555555558 20060000000 m An Real Time Devices Inc State College Pa 16804 USA oo 9761 CI Fig 5 1 Board Layout 5 3 A D Calibration Two procedures are used to calibrate the A D converter for all input voltage ranges The first procedure cali brates the converter for the unipolar range 0 to 10 volts and the second procedure calibrates the bipolar ranges 5 110 volts Table 5 1 shows the ideal input voltage for each bit weight for the unipolar straight binary range and Table 5 2 shows the ideal voltage for each bit weight for the bipolar twos complement ranges Unipolar Calibration Two adjustments are made to calibrate the A D converter for the unipolar range of O to 10 volts One 18 the offset adjustment and the other is the full scale or gain adjustment Trimpot TR7 is used to make the offset adjustment and trimpot TR2 is used for gain adjustment This calibration procedure is performed with the board set up for a 0 to 10 volt input range Before making these adjustments make sure that the jumper on P3 is set for 10V and the jumpers on P4 and P15 are set for 4 Use analog input channel 1 and set it
2. 2 63 1 3 4 1 PA1 69 5 s 2 9 83 2 3 TRIGGER IN 65 ese OG res en 9 609 Pce TRIGGER OUT 65 EXT CLK 12 VOLTS 12 VOLTS 5 VOLTS 12 VOLTS DIGITAL GND 12 VOLTS 9 9 DIGITAL Fig 2 1 P2 VO Connector and P12 On board Connector Pin Assignments Connecting the Analog Input Pins The analog inputs on the 2700 can be set for single ended or differential operation NOTE It is good practice to connect all unused channels to ground as shown in the following diagrams Failure to do so may affect the accuracy of your results Single Ended When operating in the single ended mode connect the high side of the analog input to one of the analog input channels AIN1 through AIN16 and connect the low side to an ANALOG GND pins 18 and 20 22 on P2 Figure 2 2 shows how these connections are made Differential When operating in the differential mode twisted pair cable is recommended to reduce the effects of magnetic coupling at the inputs Your signal source may or may not have a Separate ground reference When using the differential mode you should install a 10 kilohm resistor pack at location RN7 on the board to provide a reference to ground for signal sources without a separate ground reference First connect the high side of the analog input to the selected analog input channel AIN1 through AIN8 and connect the low side of t
3. 5 143 intel 82 55 WAVEFORMS MODE 0 BASIC INPUT MODE 0 BASIC OUTPUT 231256 23 in a 3 144 intel 82C55A WAVEFORMS Continued MODE 1 STROBED INPUT INPUT FROM PERIPHERAL tes 231256 24 MODE 1 STROBED OUTPUT 231256 25 3 145 intel 82 55 WAVEFORMS Continued MODE 2 BIDIRECTIONAL DATA FROM 8080 TO 8255 2 2 1 PERIPHERAL sus DATA FROM DATA FROM PERIPHERAL TO 8265 6256 TO PERIPHERAL OATA FROM 8255 TO 9080 231256 26 Note Any sequence where WR occurs before ACK AND STB occurs before is permissible INTR IBF 5 MASK e STB gt MASK e WR READ TIMING WRITE TIMING HIGH IMPEDANCE 231256 28 A C TESTING INPUT OUTPUT WAVEFORM A C TESTING LOAD CIRCUIT 2 0 20 Porro lt C 180 pF 66 231256 29 Testing Inputs Are Driven At 2 4V For A Logic 1 And 0 45V For A Logic 0 Timing Measurements Are Made At 2 0V For Logic 1 And 0 8 A Logic 0 231256 30 Vexr Is Set At Various Voltages During Testing To Guarantee The Specification C Includes Jig Capacitance 3 146 APPENDIX D AAA CONFIGURING
4. 2 6 Connecting the Analog Outputs ADA2700 Only c sssssssssssessssossssssssssssssssecsseceneesusccsecssecseussasecsscstecsssesesssese 2 6 Connecting the Timer Counters and Digital 1 0 2 6 Running the 2700DIAG Diagnostics Program 2 6 CHAPTER 3 HARDWARE DESCRIPTION 3 1 AAA 3 3 Analog Inputs e o 3 3 PEE CONV E 2 ie 3 3 Data Transier a 3 4 00 eco di 3 4 A 3 4 Digital I O Programmable Peripheral Interface 3 5 E O 3 5 CHAPTER 4 BOARD OPERATION AND PROGRAMMING 4 1 Denning the O ta 4 3 0 Read Data Start Convert Read Wirite eee ettet tette 4 4 BA 2 Read Status Reset Read Write 4 4 4 Channel Gain Board Functions Select Read Write 4 5 Reserved cts tsa cnt veka 4 5 8 D A Converter 1 ADA2700 DACI Write Only 4 5 10 D A Converter 2 ADA2700 Write Only 4 5 BART a esc 4 5 ROSEIVER NR AN ANOS 4 5 16
5. D A Converter Bipolar Calibration Table ideal Output Voltage in millivolts a Timer Counters An 8254 programmable interval timer provides three 16 bit 8 MHz timer counters for timing and counting functions such as frequency measurement event counting and interrupts Two of the timer counters are cascaded and can be used for the pacer clock The remaining timer counter is available for your use Figure 4 3 shows the timer counter circuitry 2700 VO CONNECTOR P2 1 1 1 1 1 1 1 1 4 A D TRIGGER TIMER COUNTER TIMER COUNTER EXT GATE 2 PIN 441T C OUT 2 Fig 4 3 8254 Programmable Interval Timer Circuit Block Diagram 4 24 Each timer counter has two inputs CLK in and GATE in and one output timer counter OUT They can be programmed as binary or BCD down counters by writing the appropriate data to the command word as described in the I O map section at the beginning of this chapter One of two clock sources the on board 8 MHz crystal or the external clock 2 45 can be selected as the clock input to TCO or TC2 The diagram shows how these clock sources are connected to the timer counters Two gate sources are available at the I O connector 2 41 and P2 46 When a gate is disconnected an on board pull up resistor automatically pulls the gate high enabling the timer counter The output from Timer Counter 1 is avail
6. 99 Brno rin NN i NNNM NN 0000000000 8566555928555555555 6 4 Rami Time Devices inc State Caliege 18804 UBA Fig 1 17 Pull up Pull down Resistor Circuitry 1 12 5 PORT 113 PAO 7 1 N CL ares 0 BE PULL DOWN 4 7 Fig 1 18 Adding Pull ups and Pull downs to Digital O Lines Gm Gain Multiplier Circuitry The 2700 has software programmable binary gains of 1 2 4 and 8 A gain multiplier circuit Gm is provided so that you can easily configure special gain settings for a specific application Note that when you use this feature and set up the board for a gain of other than 1 all of the input channels will operate only at your custom gain setting In other words if you install circuitry which gives you a gain multiplier of 10 then the four programmable gains available are 10 20 40 and 80 Gm is derived by adding resistors and R2 trimpot and capacitor C46 all located in the upper part just to the right of center on the board The resistors and trimpot combine to set the gain as shown in the formula in Figure 1 19 Capacitor C46 is provided so that you can add low pass filtering in the gain circuit If your input signal is a slowly changing one and you do not need to measure it at a higher rate you may want to add a capacitor at C46 in order to reduce the input frequency range and in
7. AD2700 ADA2700 User s Manual 17227 Real Time Devices Inc Accessing the Analog World AD2700 ADA2700 User s Manual 17227 REAL TIME DEVICES INC 820 North University Drive Post Office Box 906 State College Pennsylvania 16804 USA Phone 814 234 8087 FAX 814 234 5218 Published by Real Time Devices Inc 820 N University Dr P O Box 906 State College PA 16804 USA Copyright O 1992 by Real Time Devices Inc All rights reserved Printed in U S A Rev G 9310 Table of Contents INTRODUCTION o 0 1 Analog to Digital CU rond 3 Digital to Analog Conversion ADA2700 Only 0 1 3 c i 3 Digtal V O M eR 1 4 What Comes With Your Board 1 4 A A I IE 1 4 Applications Software and Toolkit id i4 Hardware Accessories dana i 4 Deine This Manual e 1 4 When You Need Help A O O 14 CHAPTER 1 BOARD SETTINGS 2 77 7 Factory Configured Switch and Jumper Settings eese tette 1 3 Analog Input Voltage Range Factory Setting 10 7011 1 3 P4 Analog Input Voltage Polarity Factory Setting 1 3 PS DMA Request Channel Factory Setting Disabled eerte 1 4 DMA Acknowledge Channel Factory Setting Disabled rentes 1 5 P7 8254 Timer Counter
8. M MODE 0 x 1 LX s 1 Modes 1 o o modes 1011 o Binary Counter 16 bits 1 Binary Coded Decimal BCD Counter 4 Decades Figure 7 Control Word Format 3 87 intel 82054 Write Operations The programming procedure for the 82 54 is very flexible Only two conventions need to be bered 1 For each Counter the Control Word must be written before the initial count is written 2 The initial count must follow the count format specified in the Control Word least significant byte only most significant byte only or least sig nificant byte and then most significant byte Since the Control Word Register and the three Counters have separate addresses selected by the A1 inputs and each Control Word specifies the Counter it applies to 0 SC1 bits no special in p Control Word Counter 0 LSB of count Counter 0 MSB of count Counter 0 Control Word Counter 1 1 58 of count Counter 1 MSB of count Counter 1 Control Word Counter 2 LSB of count Counter 2 MSB of count Counter 2 2 00 00 200222002 Control Word Counter 0 Counter Word Counter 1 Control Word Counter 2 LSB of count Counter 2 LSB of count Counter 1 LSB of count Counter 0 MSB of count Counter 0 MSB of count Counter 1 MSB of count Counter 2 20000 a gt 0200202 NOTE struction
9. u au u 5 a 65 man Real Time Devices Inc State College Pa 16804 USA 000000 0000000 6761 Fig E 1 2700 Board Layout S1 Base Address ATLANTIS assumes that the base address of your 2700 is the factory setting of 300 hex see Chapter 1 If you changed this setting you must run the ATINST program and reset the base address NOTE The ATINST program requires the base address to be entered in decimal notation P7 8254 Timer Counter VO Configuration The 8254 must be configured with the three jumpers placed between the pins as shown in Figure E 2 This configuration is the same as the factory setting After setting the jumpers verify that each is in the proper location Any remaining jumpers must be removed from the P7 header connector v DN OSC EC1 OT1 Osc EC2 PCK ET CLK1 CLK2 Fig E 2 8254 Timer Counter Clock Source Jumpers P7 P8 Interrupts To select an IRQ channel and an interrupt source you must install three jumpers on this header connector To configure this header for ATLANTIS place one jumper across the pins of your desired IRQ channel place the second jumper across the pins labeled OT2 and place third jumper across the pins labeled G Make certain that there are no other jumpers on this connector Also make sure that the IRQ channel you have selected is not used by any other device in your system Figure E 3 shows you how to
10. Adding interrupts to your software is not as difficult as it may seem and what they add in terms of performance is often worth the effort Note however that although it is not that hard to use interrupts the smallest mistake will often lead to a system hang that requires a reboot This can be both frustrating and time consuming But after a few tries you ll get the bugs worked out and enjoy the benefits of properly executed interrupts In addition to reading the following paragraphs study the INTRPTS source code included on your 2700 program disk for a better understand ing of interrupt program development Writing an Interrupt Service Routine ISR The first step in adding interrupts to your software is to write the interrupt service routine ISR This is the routine that will automatically be executed each time an interrupt request occurs on the specified IRQ An ISR is different than standard routines that you write First on entrance the processor registers should be pushed onto the stack BEFORE you do anything else Second just before exiting your ISR you must clear the interrupt status of the 2700 and write an end of interrupt command to the 8259 controller s Since 8259B generates a request on IRQ2 which is handled by 8259A an EOI must be sent to both 8259A and 8259B for IRQ8 IRQ15 Finally when exiting the ISR in addition to popping all the registers you pushed on entrance you must use the IRET instruction and not a plain RET
11. The Counters are fully independent Each Counter may operate in a different Mode The Control Word Register is shown in the figure it is not part of the Counter itself but its contents de termine how the Counter operates CONTROL WORD REGISTER 231244 6 Figure 5 Internal Block Diagram of a Counter The status register shown in the Figure when latched contains the current contents of the Control Word Register and status of the output and null count flag See detailed explanation of the Read Back command The actual counter is labelled CE for Counting Ele ment It is a 16 bit presettable synchronous down counter OLm and OL are two 8 bit latches OL stands for Output Latch the subscripts M and L stand for Most significant byte and Least significant byte respectively Both are normally referred to as one unit and called just OL These latches normally fol low the CE but if a suitable Counter Latch Com mand is sent to the 82C54 the latches latch the present count until read by the CPU and then return to following the CE One latch at a time is enabled by the counter s Control Logic to drive the internal bus This is how the 16 bit Counter communicates over the 8 bit internal bus Note that the CE itself cannot be read whenever you read the count it is the OL that is being read Similarly there are two 8 bit registers called CRy and CR for Count Register Both
12. 6 programmable operating modes Counter External clock 8 MHz or on board 8 MHz clock Counter outputs Available externally used as PC interrupts Counter gate 50006 External gate or always enabled Miscellaneous Inputs Outputs PC bus sourced 5 volts 12 volts ground Current Requirements 185 mA 5 volts 44 mA 12 volts 42 mA 12 volts Connectors P2 50 pin right angle shrouded box header P12 20 pin box connector Size 4 2 H x 6 375 L 107mm x 162mm 4 APPENDIX P2 AND P12 CONNECTOR PIN ASSIGNMENTS P2 Connector OFF 5 AIN1 AIN2 AIN2 AIN3 AIN3 AIN4 AIN5 AINS AING AING AIN7 AIN7 AIN8 AING AQUT 1 AQUT 2 ANALOG GND PA7 PA6 5 2 PA1 TRIGGER IN EXT GATE 1 TRIGGER OUT EXT CLK 12 VOLTS 12 VOLTS P12 Connector PB4 PB5 PB6 PB7 12 VOLTS 12 VOLTS O 63 9 O 9 e 9 9 9 2 6 9 9 9 QOOHOOOOOOODODOOOOOOOOQOOOO 002 OJO OJO OJO OQ 303 309 309 209 6969 DIGITAL GND T C OUT 1 T C OUT 2 2 5 VOLTS DIGITAL GND PC1 2 4 5 PC6 5 VOLTS DIGITAL GND APPENDIX COMPONENT DA
13. Bit2 Bit1 MSB LSB UNIPOLAR DATA WORD iss valor ve ov 6 os 9 1 0 0 0 O Bit12 Bit11 8810 Bit9 Bit8 Bit7 86 Bits Bit4 82 Biti MSB LSB BA 2 Read Status Reset Read Write 8 bit operation A read provides the four status bits defined below The end of convert bit goes high when a conversion is complete and does not go low until the data is read useful information when using external triggering to start conversions The DMA done bit goes high when you are in the DMA mode and the DMA transfer is complete The IRQ status bit goes high when an interrupt has occurred and stays high until a reset command is sent 2 D3 shows the status of either the A D converter status signal or the external gate input for timer counter 2 depending on the setting of jumper P14 Unlike the EOC status at bit O the A D converter status goes low when a conversion starts and then goes high as soon as the conversion is completed When the input has been sampled and a conversion is in progress this line goes low At this time the analog input channel can be changed allowing maximum throughput for channel scanning write resets internal registers so that the board is ready to start conversions The data written is irrelevant the act of writing to this address clears the board A reset command resets the end of convert DMA done and IRQ status bits to 0 A D CONVERTER Status
14. Connects one of four interrupt sources to an interrupt Jumpers installed on G ground channel pulls tri state buffer to ground G for multiple for buffer amp OT2 interrupt interrupt applications channels disabled Sets the D A output voltage range for DAC 1 Sets the D A output voltage range for DAC 2 Single ended jumpers installed P13 Selects single ended or differential analog input type on three SE pins Selects the A D converter status or the external gate of timer counter 2 to be available for monitoring EOC A D converter status Sets the state of the top 4 bits the bits not used by Bipolar the 12 bit converter of the 16 bit A D output word must be the same as P4 Sets the base address 300 hex 768 decimal 52 Bypasses 8255 Port C buffers for Mode 1 operation Open buffers not bypassed P3 Analog Input Voltage Range Factory Setting 10 Volts This header connector shown in Figure 1 2 sets the analog input voltage range for 10 or 20 volts Note that if the jumper is installed on 20V then P4 can only be set for bipolar The input ranges allowed by the 2700 are 5 10 and O to 10 volts P3 20V 10V Fig 1 2 Analog Input Voltage Range Jumper P4 Analog Input Voltage Polarity Factory Setting This header connector shown in Figure 1 3 sets the analog input voltage polarity for unipolar 4 or bipolar If the jumper on P3 is installed on 20V then P4 can on
15. DMA Single Mask Register The DMA single mask register is used to enable or disable DMA on a specified DMA channel You should mask disable DMA on the DMA channel you will be using while programming the DMA controller After the 4 21 DMA controller has been programmed and the 2700 has been programmed to sample data you can enable DMA by clearing the mask bit for the DMA channel you are using You should manually disable DMA by setting the mask bit before exiting your program or if for some reason sampling is halted before the DMA controller has transferred all the data it was programmed to transfer If you leave DMA enabled and it has not transferred all the data it was programmed to transfer it will resume transfers the next time data appears at the A D converter This can spell disaster if your program has ended and the buffer has be reallocated to another application YO Port D4H Channel Select Mask Bit 00 Channel 4 O unmask 01 Channel 5 1 mask 10 Channel 6 11 Channel 7 Mode Register The DMA mode register is used to set parameters for the DMA channel you will be using The read write bits are self explanatory the read mode cannot be used with the 2700 Autoinitialization allows the DMA controller to automatically start over once it has transferred the requested number of words Decrement means the DMA control ler should decrement its offset counter after each transfer the default is incremen
16. I 20 1 INPUT MODE 2 AND MODE 1 OUTPUT MODE 2 AND MODE 1 INPUT CONTROL WORD gt CONTROL WORD D 0 D D 0 0 D 0 D 0 D O 0 0 0 0 o UL 231256 21 Figure 16 MODE Y Combinations 3 138 82 55 Mode Definition Summary Special Mode Combination Considerations There are several combinations of modes possible For any combination some or all of the Port C lines are used for control or status The remaining bits are either inputs or outputs as defined by a Set Mode command During a read of Port C the state of all the Port C lines except the ACK and STB lines will be placed on the data bus In place of the ACK and STB line states flag status will appear on the data bus in the PC2 PC4 and PC6 bit positions as illustrated by Figure 18 Through a Write Port C command only the Port C pins programmed as outputs in a Mode 0 group can be written No other pins can be affected by a Write Port C command nor can the interrupt enable flags be accessed To write to any Port C output pro grammed as an output in a Mode 1 group or to MODE 0 OR MODE 1 ONLY change an interrupt enable flag the Set Reset Port C Bit command must be used With Set Reset Port C Bit command any Port C line pe ammed as an output including INTR IBF and can be written or an interrupt enable flag can be either set or reset Port C lines pr
17. and then write the resulting value to the port In Pascal this is programmed as V Port PortAddress V V AND 223 Port PortAddress V To set a single bit in a port OR the current value of the port with the value b where b 2 Example Set bit 3 in a port Read in the current value of the port OR it with 8 8 23 and then write the resulting value to the port In Pascal this is programmed as V Port PortAddress V OR 8 Port PortAddress V Setting or clearing more than one bit at a time is accomplished just as easily To clear multiple bits in a port AND the current value of the port with the value b where b 255 the sum of the values of the bits to be cleared Note that the bits do not have to be consecutive Example Clear bits 2 4 and 6 in a port Read in the current value of the port AND it with 171 171 255 2 2 25 and then write the resulting value to the port In C this is programmed as v inportb port address amp 171 outportb port address v To set multiple bits in a port OR the current value of the port with the value b where b the sum of the individual bits to be set Note that the bits to be set do not have to be consecutive Example Setbits 3 5 and 7 in a port Read in the current value of the port OR it with 168 168 2 25 27 and then write the resulting value back to the port In C this is programmed as v inp
18. 0 0 D D CONTROL WORD 13 O 0 0 D D D D Operating Modes MODE 1 Strobed Input Output This functional configuration provides a means for transferring 1 data to or from a specified port in conjunction with strobes or handshaking signals mode 1 Port A and Port B use the lines on Port C to generate or accept these handshaking signals 3 133 CONTROL WORD 14 D 0 0 0 D D D CONTROL WORD 915 0 0 0 D D 0 231256 12 Mode 1 Basic functional Definitions Two Groups Group A and Group B Each group contains one 8 bit data port and one 4 bit control data port The 8 bit data port can be either input or output Both inputs and outputs are latched The 4 bit port is used for control and status of the 8 bit data port intel 82C55A Input Contro Signal Definition MODE 1 PORT A STB Strobe Input A low on this input loads data into the input latch CONTROL WORD Dy 0 D O 0 0 D D Y INPUT IBF Input Buffer Full F F A high on this output indicates that the data has been loaded into the input latch in essence an ac knowledgement IBF is set by STB input being low and is reset by the rising edge of the RD input INTR Interrupt Request MODE 1 PORT 8 A high on this output can be used to interrupt the CPU when an input device is requesting service INTR is set by the STB is a one
19. 2 osc o EC1 OT1 N X OSC 8 EC2 PCK ET Fig 1 6 8254 Timer Counter Clock Source Jumpers P7 2700 VO CONNECTOR P2 1 1 1 1 1 1 1 TO A D TRIGGER TIMER TIMER TIMER COUNTER CLK 2 GATE EXT GATE 2 PIN 44 T C OUT 2 OUT Fig 1 7 8254 Timer Counter Circuit Block Diagram P8 Interrupt Source and Channel Factory Setting Jumpers on OT2 amp G Interrupt Channels Disabled This header connector shown in Figure 1 8 lets you connect any one of the four interrupt sources to any of 11 interrupt channels IRQ9 highest priority channel through IRQ12 IRQ14 IRQ15 and then back to IRQ3 through P8 P8 OT2 OT2 ET ET EOC EOC Fig 1 8a xe Fig 1 8b Interrupt Source Factory Setting IRQ3 Connected to IRQ3 IRQ3 IRQ4 IRQ4 IRQ5 IRQ5 IRQ6 IRQ6 IRQ7 IRQ7 IRQS IRQ9 IRQ10 IRQ10 IRQ11 IRQ11 IRQ12 IRQ12 IRQ14 IRQ14 IRQ15 IRQ15 G G Fig 1 8 Interrupt Channel Jumper 8 1 6 IRQ7 lowest priority Chapter 4 explains interrupt channel prioritization in detail To activate a channel you must install a jumper horizontally across the desired IRQ channel Figure 1 8a shows the factory setting Figure 1 8b shows the interrupt source connected to IRQ3 At the top of the header you can select any one of four signal sources to generate an interrupt An interrupt source is chosen by placing a jumper across the desired pair of pins The
20. 2Vto 6 5V to absolute maximum rating conditions for Voltage on any Output GND 0 5V to 05 extended periods may affect device reliability Power Dissipation 1 Watt D C CHARACTERISTICS TA O C to 70 C 5 10 GND OV Ta 40 C to 85 for Extended Temperature Symbol _ Parameter Min Units TestConditions Vu ImuttowVolage 08 v ym potion votege f 2o vf tt M ETT High Voltage 25 lon 100 pA Input Load Current Vin Voc to OV Output Float Leakage Current Vour to 0 0V Voc Supply Current 8MHz 82C54 IccsB Voc Supply Current Standby CLK Freq DC TE 09 All inputs Data Bus All Outputs Floating 581 Voc Supply Current Standby CLK Freq DC CS Vcc All Other Inputs Pins Van Outputs Open Cw Input Capacitance 10 pF Cyo Capacitance 20 pF Unmeasuredpins Cour Output Capacitan 20 pr retumed to GND A C CHARACTERISTICS Ta 0 C to 70 C 5V 10 GND 0V Ta 40 C to 85 C for Extended Temperature BUS PARAMETERS Note 1 READ CYCLE Parameter A A 4 o 80 1 us 556968 9824 m 1 Actress Hol Time ater RBT 0 9 irn J 1611 85 11 2 Co bar
21. PPI Port A Digital YO Read Write 4 6 18 PPI Port B Digital Read Write essere tl 4 6 20 PPI Port C Digital YO Read Write eerte 4 6 BA 22 8255 PPI Control Word Write 4 6 24 8254 Timer Counter 0 Read Write esee a 4 8 BA 26 8254 Timer Counter 1 Read Write lll 4 8 BA 28 8254 Timer Counter 2 Read Write 4 8 BA 30 8254 Control Word Write Only cssssssssssssssssessescessssessuscucssssassssssssussessecsesesssussecsusencesssecsecsecees 4 8 Programming the 2700 55025455 aan a dali iie and salit s 4 9 Clearing and Setting Bits 4 9 Ae ri T 4 10 Initializing the Board Dres e ume e a 4 10 Selecting a Channel e A 4 11 Setting th G ll MR 4 11 Enabling and Disabling the External Trigger 4 11 Enabling and 4 11 Conversion Modes Triggering 4 4 11 Starting an A D Conversion ee 4 12 Monitoring Conversion Status Done or End of Convert 4 12 Reading 4 13 Programming the Pacer Clock 4 14 O 4 15 D
22. 4 11 4 5 psec Trigger End of Convert Read E Data 4 gt Read Fig 4 1 A D Conversion Timing Diagram Modes Internal vs External Triggering With internal triggering also called software triggering conversions are initiated by writing a value to the START CONVERT port at BA 0 on the board With external triggering conversions are initiated by applying a high TTL signal with a pulse duration of at least 100 nanoseconds to the external TRIGGER IN pin P2 39 Any TTL signal can be used as a trigger source In fact you can use the timer counter outputs as a trigger source Software trigger In this mode a single specified channel is sampled whenever a value is written to the START CONVERT port BA 0 The active channel is the one specified at port BA 4 This is the easiest of all triggering modes It can be used in a wide variety of applications such as sample every time a key is pressed on the keyboard sample with each iteration of a loop or watch the system clock and sample every five seconds See the SOFTTRIG sample program in C and Pascal Pacer Clock In this mode conversions are continuously performed at the pacer clock rate To use this mode you must program the pacer clock to run at the desired rate see the pacer clock discussion later in this chapter The PCK jumper on P7 must be installed to use the pacer clock This is the ide
23. 5 psec DIO res CMOS 82C55 AA A 24 Logic compatibility TTUCMOS Configurable with optional VO pull up pull down resistors High level output 4 2V min Low level output voltage 0 45V High level input voltage 2 2V min 5 5V max Low level input voltage 0 3V min 0 8V max High level output current Isource CMOS buffer 12 mA max TTL buffer 16 mA max Low level output current 15 CMOS buffer 24 mA max TTL buffer 64 mA max A 10 pA Input capacitance COIN ee 10 pF Output capacitance hi irs RO tg ree 20 pF D A Converter ADA2700 AD7237 Analog DUIDUIS 2 channels 12 bits Output 0 to 5 5 0 to 10 or 10 volts Relative aCCuUracy aea eae rad san lived 1 LSB max Full scale 7 5 LSB max NOM prece pM 1 58 puppi M RN essen Sehe na 10 usec max Timer COUNTETS TEC CMOS 82C54 Three 16 bit down counters 2 cascaded 1 independent
24. A D converter a 5 volt reference a clock and a digital interface to provide a complete A D conversion function on a single chip Its low power CMOS logic combined with a high precision low noise design give you accurate results Conversions are controlled through software internally triggered or by an external trigger brought onto the board through the I O connector An on board pacer clock can be used to control the conversion rate Conversion modes are described in Chapter 4 Board Operation and Programming 3 3 Data Transfer The converted data can be transferred through the PC data bus to PC memory in one of two ways by using the microprocessor or by using direct memory access DMA Data bus transfers take more processor time to execute They use polling and interrupts to determine when data has been acquired and is ready for transfer DMA places data directly into the PC s memory one byte at a time with minimal use of processor time DMA transfers are managed by the DMA controller as a background function of the PC letting you operate at higher throughput rates The maximum throughput rate of the 2700 is 150 kHz D A Converters ADA2700 Only Two independent 12 bit analog output channels are included on the ADA2700 The analog outputs are gener ated by two 12 bit D A converters with independent jumper selectable output ranges of 5 10 0 to 5 or 0 to 10 volts The 10 volt range has a resolution of 4 88 millivolts t
25. BA 16 Program Port digital output Read Port B digital input lines lines BA 18 Program Port C digital output 8255 PPI Port Read Port C digital input lines lines BA 20 8255 PPI Control Word Program PPI configuration 22 8254 Timer Counter 0 Used for pacer clock Read count value Load count register 24 8254 Timer Counter 1 Used for pacer clock Read count value Load count register BA 26 8254 Timer Counter 2 Available for external use Read count value Load count register BA 28 a 2 0 6 A 98 Bb 3 923 a 5 gt 00 0 gt a 0 0 o 0 Read Data Start Convert Read Write 16 bit operation A read provides the 12 bit A D converted data in a right justified format as shown below When jumpers on P4 and 15 are set for bipolar conversions the data word s four most significant bits match the MSB af the A D converted data bit 12 This is necessary to provide the correct twos complement representation of the converted data When P4 and 15 are set for unipolar conversions these top four bits are 0 write starts an A D conversion data written is irrelevant BIPOLAR DATA WORD iss ora 0111010 6 os os Bit 12 Bit 12 Bit 12 Bit 12 Bit 12 Bit 11 10 Bit9 Bit7 Bit6 Bit5 Bit4
26. C includes jig capacitance 3 99 Intel 82 55 Programmable Peripheral Interface Data Sheet Reprint intel 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE B Compatible with all Intel and Most Control Word Read Back Capability Omer Microprocessors Direct Bit Set Reset Capability High Speed Zero Wait State 2 Operation with 8 MHz 8086 88 and re ae Capabillty on all 1 0 80186 188 24 Programmable I O Pins Available in 40 DIP and 44 PLCC Available in EXPRESS Low Power CHMOS Standard Temperature Range Completely TTL Compatible Extended Temperature Range The Intel 82C55A is a high performance CHMOS version of the industry standard 8255A general purpose programmable 1 device which is designed for use with all Intel and most other microprocessors It provides 24 1 0 pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation The 82C55A is pin compatible with the NMOS 8255 and 8255 5 In MODE 0 each group of 12 1 pins may be programmed in sets of 4 and 8 to be inputs or outputs In MODE 1 each group may be programmed to have 8 lines of input or output 3 of the remaining 4 pins are used for handshaking and interrupt control signals MODE 2 is a strobed bi directional bus configuration The 820554 is fabricated on Intel s advanced CHMOS III technology which provides low power consumption w
27. P12 On board Connector Pin Assignments 2 4 Single Ended Input Connections ssssscssssssssssssssssesssvesssseecnuseonsscssnscsstscsssueessussessuessassasissconseceseccsescese 2 5 Differential 03114002111 410 2 5 Cascading Two Boards for Simultaneous Sampling eret 2 6 AD2700 ADA2700 Block Diagram esee ttn 3 3 8254 Timer Counter Circuit Block Diagram 3 4 A D Conversion Timing Diagram All 10668 4 12 Pacer Clock Block Diagram 1 4 14 8254 Timer Counter Circuit Block Diagram 4 24 Single Conversion Flow Diagram cssssssssssssssessesscsessssssssssssssssusessscssscesussssecsusesssesserssstssssssasecussenseseeee 4 27 MT 4 28 Interrupts Flow Diagram uns ea 4 29 D A Conversion Flow Diagram 4 30 Board TAY OE ae ts 5 3 INTRODUCTION The AD2700 and ADA2700 Advanced Industrial Control boards turn your IBM PC AT or compatible into a high speed high performance data acquisition and control system Installed within a single expansion slot in the computer each 2700 series board features 8 differential or 16 single ended analog input channels 12 bit 5 microsecond analog to digital converter with 150 kHz throughput 5
28. Startup with either DOS function 25H set interrupt vector or use the library routine supplied with your compiler Performing these two steps will guarantee that the interrupt status of your computer is the same after running your program as it was before your program started running Common Interrupt Mistakes Remember that hardware interrupts are numbered 8 through 15 for IRQO IRQ7 and 70H through 77H for IRQ8 IRQIS Two of the most common mistakes when writing an ISR are forgetting to clear the interrupt status of the 2700 and forgetting to issue the EOI command to the appropriate 8259 interrupt controller before exiting the ISR Data Transfers Using DMA Direct Memory Access DMA transfers data between a peripheral device and PC memory without using the Processor as an intermediate Bypassing the processor in this way allows very fast transfer rates All PCs contain the necessary hardware components for accomplishing DMA However software support for DMA is not included as part of the BIOS or DOS leaving you with the task of programming the DMA controller yourself With a little care such programming can be successfully and efficiently achieved The following discussion is based on using the DMA controller to get data from a peripheral device and write it to memory The opposite can also be done the DMA controller can read data from memory and pass it to a periph eral device There are a few minor differences mostly in programm
29. THE 2700 FOR SIGNAL MATH Jumper and Switch Settings When running SIGNAL MATH you may have to change some of the 270075 on board jumpers from their factory set positions Before using SIGNAL MATH on the 2700 board check the following switch and jumpers 51 Base address P7 8254 timer counter 1 configuration 8 Interrupts The board layout is shown in Figure D 1 lt 5 000000000000 oooon 9630 8 0000000000 0 00 0 ETC AT Dooooooooo us Salle 5 ene dl ADDRESS OF ar qa m mnm a oO 1 0090 oll o 00000000000000 8 oin 0000 o A 2 2 Dooooo la E 5 0 Abers 2 ERE gt oj 2 3 lo ogo lo ol 5 0 0 5 0 lo of logo 5 59 569 OOo jo o 46 gt v E olslo ooko 6 6 ollo 900 olojo oj jogo 580 6 74HCT244 000000 0000000 5 f PAL 0 24 amp nw 2500000000000 9 5000000 B ons LI J c 90000000 99 css 0000000 Ord gt 6 CLP c 4900000009 a 9000000000 P backs 9 74HCT244 7415244 SE 6 6 0 6 0 6 0 0 6 co us ur ola 9999999999 0 ca 0000000000 00000000 05
30. The act of writing to this port starts a D A conversion on channel 2 ose ox olor or os oe oT oe oiT oo X Bit12 Bit 11 Bit10 Bit9 Bit8 887 886 Bits 4 Birt MSB LSB BA 12 Reserved BA 14 Reserved 16 PPI Port A Digital I O Read Write 8 bit operation Transfers the 8 bit Port A digital input and digital output data between the board and an external device A read transfers data from the external device through P2 and into PPI Port A a write transfers the written data from Port A through P2 to an external device 18 PPI Port B Digital VO Read Write 8 bit operation Transfers the 8 bit Port B digital input and digital output data between the board and an external device A read transfers data from the external device through P12 the on board 20 pin connector and into PPI Port B a write transfers the written data from Port B through P12 to an external device 20 PPI Port C Digital I O Read Write 8 bit operation Transfers the two 4 bit Port C digital input and digital output data groups Port C Upper and Port C Lower between the board and an external device A read transfers data from the external device through P2 and P12 the on board 20 pin connector and into PPI Port C a write transfers the written data from Port C through P2 and P12 to an external device 22 8255 PPI Control Word Write Only 8 bit operation When bit 7
31. The IRET automatically pops the flags CS and IP that were pushed when the interrupt was called If you find yourself intimidated by these requirements take heart Most Pascal and C compilers allow you to identify a procedure function as an interrupt type and will automatically add these instructions to your ISR with one important exception most compilers do not automatically add the end of interrupt command to the procedure you must do this yourself Other than this and the few exceptions discussed below you can write your ISR just like any other routine It can call other functions and procedures in your program and it can access global data If you are writing your first ISR we recommend that you stick to the basics just something that will convince you that it works such as incrementing a global variable NOTE 1f youare writing an ISR using assembly language you are responsible for pushing and popping registers and using IRET instead of RET There are a few cautions you must consider when writing your ISR The most important is do not use any DOS functions or routines that call DOS functions from within an ISR DOS is not reentrant that is DOS function cannot call itself In typical programming this will not happen because of the way DOS is written But what about when using interrupts Then you could have a situation such as this in your program If DOS function X is being executed when an interrupt occurs and the interrupt routi
32. Triggered Strobe Retriggerable These modes are detailed in the 8254 Data Sheet reprinted from Intel in Appendix C Digital Programmable Peripheral Interface The programmable peripheral interface PPI is used for digital 1 0 functions This high performance TTL CMOS compatible chip has 24 digital 1 O lines divided into two groups of 12 lines each Group A Port A 8 lines and Port C Upper 4 lines Group Port 8 lines and Port Lower 4 lines Port A and Port C are available at the external O connector P2 Port B and Port C are available at the on board 20 pin connector P12 You can use these ports in one of two PPI operating modes Mode 0 or Mode 1 Do not try to use Mode 2 operation The 2700 does not support Mode 2 When operating in Mode 1 the on board buffers must be removed from the Port C lines This procedure is described in Chapter 1 in the S2 DIP switch discussion The 2700 operating modes are Mode 0 Basic input output Lets you use simple input and output operation for a port Data is written to or read from the specified port Mode 1 Strobed input output Lets you transfer I O data from Port A or Port B in conjunction with strobes or handshaking signals These modes are detailed in the 8255 Data Sheet reprinted from Intel in Appendix C The bidirectional buffers on the 8255 s I O lines monitor the 8255 control word to automatically set their direction Hardware changes to the buffer
33. WR signals RD and WR are ignored otherwise RD Read Control This input is low during CPU read operations 27 Write Control This input is low during CPU write operations 24 2 Power 5V power supply connection 1151525 NoConnect FUNCTIONAL DESCRIPTION sired delay After the desired delay the 82C54 will interrupt the CPU Software overhead is minimal and variable length delays can easily be accommodated h fenera Some of the other counter timer functions common The 82C54 is a programmable interval timer counter to microcomputers which can be implemented with designed for use with intel microcomputer systems the 82054 are It is a general purpose multi timing element that can be treated as an array of I O ports in the system software Real time clock Even counter Digital one shot Programmable rate generator Square wave generator Binary rate multiplier Complex waveform generator Complex motor controller The 82 54 solves one of the most common prob lems in any microcomputer system the generation of accurate time delays under software control in stead of setting up timing loops in software the pro grammer configures the 82C54 to match his require ments and programs one of the counters for the de 3 84 62654 Block Diagram DATA BUS BUFFER This 3 state bi directional 8 bit buffer is used to in terface the 82054 to the
34. are normally referred to as one unit and called just CR When a new count is written to the Counter the count is 3 86 stored in the CR and later transferred to the CE The Contro Logic allows one register at a time to be loaded from the internal bus Both bytes are trans ferred to the CE simultaneously and CR are cleared when the Counter is programmed In this way if the Counter has been programmed for one byte counts either most significant byte only or least significant byte only the other byte will be zero Note that the CE cannot be written into whenever a count is written it is written into the CR The Control Logic is also shown in the diagram CLK n GATE n and OUT n are all connected to the out side world through the Control Logic 82C54 SYSTEM INTERFACE The 82C54 is treated by the systems software as an array of peripheral 1 ports three are counters and the fourth is a control register for MODE program ming Basically the select inputs Ao A4 connect to the Ap A4 address bus signals of the CPU The CS can be derived directly from the address bus using a linear select method Or it can be connected to the output of a decoder such as an Intel 8205 for larger sys tems COUNTER o COUNTER 1 mn OUT GATE CLK OUT GATE CLK COUNTER 2 _ OUT GATE CLK 231244 7 Figure 6 82054 System interface intel OPERATIONAL DESCRIPTION General After power up the st
35. are the A D the D A the timer counters and the digital 1 lines This chapter also describes the hardware select able interrupts 3 1 The 2700 board has four major circuits the A D the D A ADA2700 only the timer counters and the digital lines Figure 3 1 shows the block diagram of the board This chapter describes the hardware which makes up the major circuits and hardware selectable interrupts 16 ANALOG INPUTS 8 DIFF 16 S E 5V TO 8V 0 TO 10V 10 TO 10V Fig 3 1 AD2700 ADA2700 Block Diagram A D Conversion Circuitry The 2700 performs analog to digital conversions on up to 8 differential or 16 single ended software selectable analog input channels The following paragraphs describe the A D circuitry Analog Inputs The input voltage range is jumper selectable for 5 to 5 volts 10 to 10 volts or O to 10 volts Software programmable binary gains of 1 2 4 and 8 let you amplify lower level signals to more closely match the board s input ranges These gains can be customized for even greater input control by adding a gain multiplying circuit as described in Chapter 1 Overvoltage protection to 35 volts is provided at the inputs A D Converter The AD678 12 bit successive approximation A D converter accurately digitizes dynamic input voltages in 5 microseconds for a maximum throughput rate of 200 kHz for the converter alone The AD678 contains a sample and hold amplifier a 12 bit
36. circuitry are required only when using Mode 1 where the Port C buffers must be removed as described in Chapter 1 Interrupts The 2700 has four jumper selectable interrupt sources end of convert DMA done the external trigger and the output of timer counter 2 The end of convert signal can be used to interrupt the computer when an A D conversion is completed The DMA done is used in the DMA mode to signal an interrupt whenever a DMA transfer is com pleted The external trigger at the I O connector can be used to generate an interrupt whenever the trigger line changes from low to high Or the output of timer counter 2 can generate an interrupt whenever the count reaches 0 Chapter 1 tells you how to set the jumpers on the interrupt header connector P8 and Chapter 4 describes how to program interrupts 3 5 4 ee BOARD OPERATION AND PROGRAMMING This chapter shows you how to program and use your 2700 board by writing to and reading from the AT bus in 8 or 16 bit words It provides a complete description of the I O map a de tailed description of programming operations and operating modes and flow diagrams to aid you in programming The example programs included on the disk in your board package are listed at the end of this chapter These programs written in Turbo C and Turbo Pascal include source code to simplify your applications programming Defining the VO Map The map f
37. configure P8 for IRQ channel 9 8 OT2 ET EOC DMA IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 G Fig E 3 Interrupts and Interrupt Channel Jumpers P8 4 F 1 APPENDIX F WARRANTY LIMITED WARRANTY Real Time Devices Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from REAL TIME DE VICES This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period REAL TIME DEVICES will repair or replace at its option any defective products or parts at no additional charge provided that the product is returned shipping prepaid to REAL TIME DEVICES All replaced parts and products become the property of REAL TIME DEVICES Before returning any product for repair customers are required to contact the factory for an RMA number THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY PRODUCTS WHICH HAVE BEEN DAM AGED AS A RESULT OF ACCIDENT MISUSE ABUSE such as use of incorrect input voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by REAL TIME DEVICES acts of God or other contingencies beyond the control of REAL TIME DEVICES OR AS A RESULT OF SERVICE OR MODIFICATION BY ANYONE OTHER THAN REAL TIME DEVICES EXCEPT AS EX PRESSLY SET FORTH
38. e inputs are not latched specified port 16 different Input Output configurations are pos sible in this Mode MODE 0 BASIC INPUT 231256 8 MODE 0 BASIC OUTPUT 231256 9 3 130 intel 82C55A MODE 0 Port Definition 0 o 0 o meur 4 ourPur oureur 1 s 7 2 1 1 1 3 o ourur meur oureur Lo oureur wer 7 wer 10 o o meu ourur s oureur o o 1 1 meu ourur 9 outeur 1 0 1 10 eur 10 input o 5 wer po o wer meur 12 ouro ouro Bee CONTROL WORD 0 O 0 0 0 D 0 D D D D D CONTROL WORD 1 CONTROL WORD 63 0 0 Dy D 0 D 0 D D 0 D D 3 PB PB 231256 10 3 131 82 55 MODE 0 Configurations Continued CONTROL WORD 4 0 0 D 0 O D CONTROL WORD 95 D 0 D D CONTROL WORD 06 0 De 0 D CONTROL WORD 97 0 0 0 0D D D 3 132 CONTROL WORD 6 D 0 D D D 0 D CONTROL WORD 09 0 0 Os Do 0 CONTROL WORD 610 0 0 D D D CONTROL WORD 611 O 0 D D D D 231256 11 82 55 MODE 0 Configurations Continued CONTROL WORD 012 D 0 D D
39. header does not have to be set the same as P10 and Polarity or on om oto swos ow MET own on 2 1 5 5 Fig 1 11 DAC 2 Output Voltage Range Jumper 11 P13 Single Ended Differential Analog Inputs Factory Setting Single Ended This header connector shown in Figure 1 12 configures the 2700 for 8 differential or 16 single ended analog input channels When operating in the single ended mode three jumpers must be installed across the SE pins When operating in the differential mode two jumpers must be installed across the D pins DO NOT install jumpers across both SE and D pins at the same time SE D SE D SE P13 Fig 1 12 Single Ended Differential Analog Input Signal Type Jumpers P13 1 8 14 A D Converter Status External Gate 2 Monitor Factory Setting EOC A D Converter Status This header connector shown in Figure 1 13 lets you select either the A D converter status or the external gate input of timer counter 2 to be available for monitoring at bit 3 of the status word BA 2 The A D converter status provides a direct read of the A D converter s availability for starting conversions This line goes low when a conversion starts then goes high when the conversion is completed Chapter 4 provides a more detailed explanation of this status signal P14 EG2 Fig 1 13 A D Converter Status External Gate 2 Monitor Ju
40. interrupt sources available are the the output of timer counter 2 OT2 external trigger ET A D end of convert EOC and DMA done DMA When jumpered the bottom pair of pins on 8 labeled connects a 1 kilohm pull down resistor to the output of a high impedance tri state driver which carries the interrupt request signal This pull down resistor drives the interrupt request line low whenever interrupts are not active Whenever an interrupt request is made the tri state buffer is enabled forcing the output high and generating an interrupt You can monitor the interrupt status through bit 2 in the status word I O address location BA 2 After the interrupt has been serviced the reset command returns the IRQ line low disabling the tri state buffer and pulling the output low again Figure 1 9 shows this circuit Because the interrupt request line is driven low only by the pull down resistor you can have two or more boards which share the same IRQ channel You can tell which board issued the interrupt request by monitoring each board s IRQ status bit NOTE When you use multiple boards that share the same interrupt only one board should have the G jumper installed The rest should be disconnected Whenever you operate a single board the G jumper should be installed INT IRQ STATUS SOURCE INTERRUPT REGISTER INTERRUPT CLR Fig 1 9 Pulling Down the Interrupt Request Line P10 DAC 1 Output Voltage Range Factory S
41. is easy to install in your PC AT or compatible computer This chapter tells you step by step how to install and connect the board After you have installed the board and made all of your con nections you can turn your system on and run the 2700DIAG board diagnostics program included on your example software disk to verify that your board is working Board Installation Keep the board in its antistatic bag until you are ready to install it in your computer When removing it from the bag hold the board at the edges and do not touch the components or connectors Before installing the board in your computer check the jumper and switch settings Chapter 1 reviews the factory settings and how to change them If you need to change any settings refer to the appropriate instructions in Chapter 1 Note that incompatible jumper settings can result in unpredictable board operation and erratic response To install the board 1 Turn OFF the power to your AT computer 2 Remove the top cover of the computer housing refer to your owner s manual if you do not already know how to do this 3 Select any unused expansion slot and remove the slot bracket 4 Touch the metal housing of the computer to discharge any static buildup and then remove the board from its antistatic bag 5 If you are using the 20 pin P12 connector for 8255 digital I O operations connect the mating connector to it before installing the board in the PC Note tha
42. is for IRQS bit 1 is for IRQ9 and so on See the paragraph entitled nterrupt Mask Register IMR earlier in this chapter for help in determining your IRQ s bit After setting the bit write the new value to I O port 21H IRQO IRQ7 or I O port A1H IRQ8 IRQ15 With the startup IMR saved and the interrupts on your IRQ temporarily disabled you can assign the interrupt vector to point to your ISR Again you can overwrite the appropriate entry in the vector table with a direct memory write but this is a bad practice Instead use either DOS function 25H set interrupt vector or if your compiler provides it the library routine for setting an interrupt vector Remember that vectors 8 15 are for IRQO IRQ7 and vectors 7011 7711 are for IRQ8 IRQ15 If you need to program the source of your interrupts do that next For example if you are using the program mable interval timer to generate interrupts you must program it to run in the proper mode and at the proper rate Finally clear the bit in the IMR for the IRQ you are using This enables interrupts on the IRQ Restoring the Startup IMR and Interrupt Vector Before exiting your program you must restore the interrupt mask register and interrupt vectors to the state they were in before your program started To restore the IMR write the value that was saved when your program started to port 21H for IRQO IRQ7 or I O port AIH IRQ8 IRQ15 Restore the interrupt vector that was saved at
43. long in your ISR it may be called again before you have completed handling the first run This often leads to a hang that requires a reboot Y our ISR should have this structure Push any processor registers used in your ISR Most C and Pascal interrupt routines automatically do this for you Put the body of your routine here Clear the interrupt bit on the 2700 by writing any value to BA 4 2 Issue the EOI command to the 8259 interrupt controller by writing 20H to port 20H and port AOH if you are using IRQ8 IRQ15 Pop all registers pushed on entrance Most C and Pascal interrupt routines automatically do this for you The following C and Pascal examples show what the shell of your ISR should be like In C void interrupt ISR void Your code goes here Do not use any DOS functions outportb BaseAddress 2 0 Clear 2700 interrupt outportb 0x20 0 20 Send EOI command to 8259A for all IRQs outportb 0x20 0 Send EOI command to 8259B if using IRQ8 15 In Pascal Procedure ISR Interrupt begin Your code goes here Do not use any DOS functions Port BaseAddress 2 0 Clear 2700 interrupt Port 20 20 Send EOI command to 8259A for all IRQs Port A0 20 Send EOI command to 8259B if using IRQ8 15 end Saving the Startup Interrupt Mask Register IMR and Interrupt Vector The next step after writing the ISR is to save the startup state of
44. on the next CLK pulse thus starting the one shot pulse An initial count of N will result in a one shot pulse N CLK cycles in dura tion The one shot is retriggerable hence OUT will remain low for N CLK pulses after any trigger The one shot pulse can be repeated without rewriting the same count into the counter GATE has no effect on OUT If a new count is written to the Counter during a one shot pulse the current one shot is not affected un less the Counter is retriggered In that case the Counter is loaded with the new count and the one shot pulse continues until the new count expires CW212 58 3 1515151515131 11151615131 CW 12 5843 181515418131 11131 1413 12 58 2 FE 4 3 231244 9 Figure 16 Mode 1 MODE 2 RATE GENERATOR This Mode functions like a divide by N counter It 5 typicially used to generate a Real Time Clock inter rupt OUT will initially be high When the initial count has decremented to 1 OUT goes low for one CLK pulse OUT then goes high again the Counter re loads the initial count and the process is repeated Mode 2 is periodic the same sequence is repeated indefinitely For an initial count of N the sequence repeats every N CLK cycles GATE 1 enables counting GATE 0 disables counting If GATE goes low during an output pulse OUT is set high immediately A trigger reloads the Counter with the initial count on the next CLK pulse OUT goes low N CLK
45. other counters remain latched until they are read If multiple count read back commands are issued to the same counter without reading the Intel 82C54 count all but the first are ignored i e the count which will be read is the count at the time the first read back command was issued The read back command may also be used to latch status information of selected counter s by setting STATUS bit D4 0 Status must be latched to be read status of a counter is accessed by a read from that counter The counter status format is shown in Figure 11 Bits 05 through DO contain the counter s programmed Mode exactly as written in the last Mode Control Word OUTPUT bit D7 contains the current state of the OUT pin This allows the user to monitor the counter s output via software possibly eliminating some hardware from a system 6 Ds 02 D D D 0 NULL sa lees 071 Out Pin is 1 0 Out Pin is 0 Dg 1 Null count Count available for reading Ds Do Counter Programmed Mode See Figure 7 Figure 11 Status Byte NULL COUNT bit D6 indicates when the last count written to the counter register CR has been loaded into the counting element CE The exact time this happens depends on the Mode ot the counter and is described in the Mode Definitions but until the count is loaded into the counting element CE it can t be read from the counter If the count is latched or read before this time the count va
46. program that DMA is done and any actions can be taken as needed Both methods are demonstrated in the sample C and Pascal programs the polling method in the program named DMA and the interrupt method in DMASTR Common DMA Problems sure that your buffer is large enough to hold all of the data you program the DMA controller to transfer Check to be sure that your buffer does not straddle a page boundary Remember that the value for the number of samples for the DMA controller to transfer 15 equal to the number of samples 1 This is because as the DMA controller counts down it transfers a sample when the count reaches 0 If you terminate sampling before the DMA controller has transferred the number of bytes it was programmed for be sure to disable DMA by setting the mask bit in the single mask register D A Conversions The two D A converters can be individually programmed to convert 12 bit digital words into a voltage in the range of 5 10 0 to 5 or 0 to 10 volts DACI is programmed by writing the 12 bit digital data word to BA 8 DAC2 is identical with the data word written to BA The following tables list the key digital codes and corresponding output voltages for the D A converters me mes 0 s a 9 O E 0 0000 0 0000 4 23
47. software you may have to change some of the 2700 s on board jumpers from their factory set positions Before using ATLANTIS on the 2700 board check the following switch and jumpers S1 Base address P7 8254 timer counter 1 O configuration P8 Interrupts Figure E 1 shows the board layout C ADDRESS PO EN e Be 87 a ar num mpm mm Made in USA o o_o ooon 8 302688 ol oll 0 gt Y 0 eme 676 a Ei 0000 6 ES 010 066 0 2 9 jo ol jo Bao Cfi 9 so 516 5 ajo o o 20612 89 8 55 5 6 oo 12 Odo lo 4 9115 9119 o 900000000000 Odo oj 020 lo PA DACE ol lo 000000000000 0000 ol lon 125 ODu 99 m 900000000054 0000000000 0000000000 O 2 0 0000000009 5000000000 8060000000 us dl go00000000000 0000000 0 74HCTOS 5 3 0700000500000 0600000 y 2 pa 000000550600 Y 00000 Orb Jo Good 055557 69000000000 0000000 6605 50000 en De i 29900000000 0000000000 9 171 5090000000003 000000040000600000 5000000000 0060000000 9 50000009u000000000 Iu000000000
48. system bus see Figure 3 231244 4 Figure 3 Block Diagram Showing Data Bus Buffer and Read Write Logic Functions READ WRITE LOGIC The Read Write Logic accepts inputs from the 5 5 tem bus and generates control signals tor the other functional blocks of the 82054 A and select one of the three counters or the Control Word Regis ter to be read from written into A low on the RD input tells the 82C54 that the CPU is reading one of the counters A low on the WR input tells the 82C54 that the CPU is writing either a Control Word or an initial count Both RD and WR are qualified by CS RD and WR are ignored unless the 82C54 has been selected by holding CS low 3 85 CONTROL WORD REGISTER The Control Word Register see Figure 4 is selected by the Read Write Logic when Ay Ag 11 If the CPU then does a write operation to the 82C54 the data is stored in the Control Word Register and is interpreted as a Control Word used to define the operation of the Counters The Control Word Register can only be written to status information is available with the Read Back Command DATA Bus BUFFER INTERNAL 805 231244 5 Figure 4 Block Diagram Showing Control Word Register and Counter Functions COUNTER 0 COUNTER 1 COUNTER 2 These three functional blocks are identical in tion so only a single Counter will be described The internal block diagram of a single counter is shown in Figure 5
49. the pin descriptions Figure 6 shows the control word format for both Read and Write operations When the contro word is read bit D7 will always be a logic 1 as this implies control word mode information Ports A B and C The 82 55 contains three 8 bit ports B and C All can be configured in a wide variety of functional characteristics by the system software but each has its own special features or personality to further enhance the power and flexibility of the 82C55A Port A One 8 bit data output latch buffer and one 8 bit input latch buffer Both pull up and pull down bus hold devices are present on Port A Port B One 8 bit data input output latch buffer Only pull up bus hold devices are present on Port B Port C One 8 bit data output latch buffer and one 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B Only pull up bus hold devices are present on Port C See Figure 4 for the bus hold circuit configuration for Port A B and C 3 126 intel 82C55A BIDIRECTIONAL DATA BUS 231256 3 INTERNAL DATA OUT INTERNAL DATA NOTE MN 231256 4 Port pins loaded with more than 20 pF capacitance may not have their logic level guaran teed following a hardware rese
50. then returns to what it was doing before it was interrupted Other common devices that use interrupts are modems disk drives and mice Your 2700 board can interrupt the processor when a variety of conditions are met such as DMA done timer countdown finished end of convert and external trigger By using these interrupts you can write software that effectively deals with real world events Interrupt Request Lines To allow different peripheral devices to generate interrupts on the same computer the AT bus has 16 different interrupt request IRQ lines A transition from low to high on one of these lines generates an interrupt request which is handled by one of the AT s two interrupt control chips One chip handles IRQO through IRQ7 and the other chip handles IRQ8 through IRQ15 The controller which handles IRQ8 IRQIS is chained to the first controller through the IRQ2 line When an IRQ line is brought high the interrupt controllers check to see if interrupts are to be acknowledged from that IRQ and if another interrupt is already in progress they decide if the new request should supersede the one in progress or if it has to wait until the one in progress is done This prioritizing allows an interrupt to be interrupted if the second request has a higher priority The priority level is determined by the number of the IRQ Because of the configuration of the two controllers with one chained to the other through IRQ2 the priority scheme is a li
51. 0 converting 1 not converting EXT GATE 2 Status monitors external gate 2 line End of Convert 0 EOC 1 conversion done DMA Done 0 DMA not done 1 DMA done IRQ Status 0 No IRQ 1 4 4 BA 4 Channel Gain Board Functions Select Read Write 8 bit operation Programs the analog input channel and gain and enables the IRQ and external trigger Reading this register shows you the current settings Analog Input Channel Select 0000 channel 1 0001 channel 2 0010 channel 3 0011 channel 4 0100 channel 5 0101 channel 6 0110 channel 7 0111 channel 8 1000 channel 9 1001 channel 10 1010 channel 11 1011 channel 2 1100 channel 13 1101 channel 14 1110 channel 15 1111 channel 16 IRQ Enable 0 IRQ disabled 1 enabled Channel Gain External Trigger Enable 00 x1 0 Disabled 01 2 1 Enabled 10 4 11 8 6 Reserved 8 D A Converter 1 ADA2700 DAC1 Write Only 16 bit operation Programs the 12 bit digital word for DACI in a right justified format as shown below The act of writing to this port starts a D A conversion on channel 1 prs ov pro 6 1 os 6 02101 oo X 8812 Bit11 8 10 Bit9 888 Bit7 886 Bits Bit4 882 Bit 5 LSB BA 10 D A Converter 2 ADA2700 DAC2 Write Only 16 bit operation Programs the 12 bit digital word for DAC2 in a right justified format as shown below
52. 10 or 0 to 10 volt input range Programmable gains of 1 2 4 and 8 with an on board gain multiplier circuit Three conversion modes DMA transfer Trigger in and trigger out for external triggering or cascading boards 16 bit AT bus compatibility 24 TTL CMOS buffered 8255 based digital I O lines with optional pull up or pull down resistors Three 16 bit timer counters two cascaded for pacer clock Two 12 bit digital to analog output channels with dedicated grounds ADA2700 only 5 10 0 to 5 or 0 to 10 volt analog output range ADA2700 only Turbo Pascal and Turbo source code diagnostics program The following paragraphs briefly describe the major functions of the board A more detailed discussion of board functions is included in Chapter 3 Hardware Operation and Chapter 4 Board Operation and Programming The board setup is described in Chapter 1 Board Settings Analog to Digital Conversion The analog to digital A D circuitry receives up to 8 differential or 16 single ended analog inputs and converts these inputs into 12 bit digital data words which can then be read and or transferred to PC memory The board is factory set for single ended input channels The analog input voltage range is jumper selectable for bipolar ranges of 5 to 5 volts or 10 to 10 volts or a unipolar range of O to 10 volts The board is factory set for 5 to 5 volts Overvoltage protection to 35 volts is provided at the inputs The hi
53. 151515131 1311111418 1 CWz A 1368 3 58 5 231244 13 20 5 3 94 Or Going Rising Low Disables Enables counting counting 1 Initiates counting 2 Resets output after next clock 1 Disables counting Initiates Enables 2 Sets output counting counting immediately high 1 Disables counting Initiates Enables 2 Sets output counting counting immediately high Disables Enables counting counting Initiates counting Figure 21 Gate Pin Operations Summary NOTE O is equivalent to 216 for binary counting and 104 for BCD counting Figure 22 Minimum and Maximum initial Counts 3 95 Operation Common to All Modes Programming When a Control Word is written to a Counter all Control Logic is immediately reset and OUT goes to a known initial state no CLK pulses are required for this GATE The GATE input is always sampled on the rising edge of CLK In Modes 0 2 3 and 4 the GATE input is level sensitive and the logic level is sampled on the rising edge of CLK In Modes 1 2 3 and 5 the GATE input is rising edge sensitive In these Modes a rising edge of GATE trigger sets an edge sensi tive flip flop in the Counter This flip flop is then sam pled on the next rising edge of CLK the flip flop is reset immediately after it is sampled in this way a trigger will be detected no matter w
54. 24 pin DIP and 28 pin plastic leaded chip carrier packages Oo zip cue 10 f ouT2 CLK 1 19 2 1 D u 5 8 n w LJ LI LJ L U LU A OUT 1 OUTO GATEO GNO OUTI CLK1 231244 3 PLASTIC LEADED CHIP CARRIER 55 2 REGISTER SATE 2 231244 1 Figure 1 82054 Block Diagram 231244 2 Diagrams are tor pin reference only Package sizes are not to scale Figure 2 82654 Pinout September 1989 3 83 Order Number 231244 005 intel 82C54 Table 1 Pin Description Sa a LE nm 25 EEE e connected to system data bus 9 1 Clock 0 Clock input of Counter 0 to 2 o Output 0 Output of Counter 0 3 Gate 0 Gate input of Counter 0 Ground Power supply connection gt Y m o 63 Out 1 Output of Counter 1 Gate 1 Gate input of Counter 1 Clock 1 Clock input of Counter 1 Gate 2 Gate input of Counter 2 Out 2 Output of Counter 2 Clock 2 Clock input of Counter 2 Address Used to select one of the three Counters or the Control Word Register for read or write operations Normally connected to the system address bus gt b 0 A Counter 0 Counter 1 Counter 2 Control Word Register Chip Select A low on this input enables the 82654 to respond to RD and
55. 4 D3 02 9 Do I 7 AA E DE GROUP A GROUP B Defined By Mode 0 or Mode 1 Selection Figure 17b MODE 2 Status Word Format Position Alternate Port C Pin Signal Mode Interrupt Enable Flag INTE B PC2 ACKg Output Mode 1 or STBg Input Mode 1 INTE A2 STB Input Mode 1 or Mode 2 1 2 Figure 18 Interrupt Enable Flags in Modes 1 and 2 INTE A1 3 140 intel 82 55 ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias 0 C to 70 Storage Temperature 65 to 150 Supply Voltage 0 5 to 80 Operating Voltage 4V to 7V Voltage on any Input GND 2V to 6 5V Voltage on any Output GND 0 5V to Voc 0 5V Power Dissipation 1 Watt D C CHARACTERISTICS 0 to 70 C 5V 10 GND OV TA 40 C to 85 0 for Extended Temperture Symbol Parameter min max Units Vu imputtowVoltage os os v Input High Voltage Output Low Voltage Vi Darlington Drive Current IPHLO Voc Supply Current IccsB Supply Current Standby NOTES 0 1 Pins Ay Ag CS WR RD Reset e 2 Data Bus Ports BC 3 Outputs open 4 Limit output current to 4 0 mA OH Output High Voltage 3 0 Voc 0 4 Input Leakage Current NEN Output F
56. 5 5000 0 7500 0 8750 0 9375 0 9687 5 9843 8 9921 9 9960 9 9980 5 9990 2 9995 1 10000 0 4921 9 4960 9 4980 5 4990 2 3 4995 1 4997 6 5000 0 5 7 APPENDIX AD2700 ADA2700 SPECIFICATIONS AD2700 ADA2700 Characteristics Typical 25 C Interface Switch selectable base address mapped Jumper selectable interrupts amp DMA channel Analog Input 8 differential or 16 single ended inputs Input impedance each gt 10 megohms Gains software selectable 1 2 4 amp 8 plus Gm gain multiplier Gain lilee T 05 typ 0 25 max A se ite Deo A 5 110 or O to 10 volts Guaranteed linearity across input ranges 5 9 5 and 0 to 9 5 volts Overvoltage protection A 35 Vdc Common mode input voltage 10 volts max Settling time gain 1 5 psec max PALO CONVOMMON Sc AD678 VD sa Successive approximation 16500 12 bits 2 44 mV 10V 4 88 mV 20V een comte 1 LSB typ Conversion speed dn 5 typ AA 150 kHz Pacer Clock Range using on board 8 MHz 1 9 minutes to
57. 5555555590 E 1 La m a an Real Time Devices Inc State College Pa 16804 USA Fig 0 1 2700 Board Layout S1 Base Address SIGNAL MATH assumes that the base address of your 2700 is the factory setting of 300 hex 768 decimal If you change this setting you must run the ADAINST program and reset the base address NOTE When using the ADAINST program you can enter the base address in decimal or hexadecimal notation When entering a hex value you must precede the number by a dollar sign for example 300 D 3 P7 8254 Timer Counter I O Configuration The 8254 must be configured with the three jumpers placed between the pins as shown in Figure D 2 This configuration is the same as the factory setting After setting the jumpers verify that each is in the proper location Any remaining jumpers must be removed from the P7 header connector P7 0 EC1 OT1 osc EC2 PCK ET CLK1 CLK2 Fig D 2 8254 Timer Counter Clock Source Jumpers P7 8 Interrupts To select an IRQ channel and an interrupt source you must install three jumpers on this header connector To configure this header for SIGNAL MATH place one jumper across the pins of your desired IRQ channel place the second jumper across the pins labeled EOC and place third jumper across the pins labeled Make certain that there are no other jumpers on this connector Also make su
58. ABOVE NO OTHER WARRANTIES ARE EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND REAL TIME DEVICES EXPRESSLY DISCLAIMS ALL WARRANTIES NOT STATED HEREIN ALL IMPLIED WARRANTIES INCLUDING IMPLIED WARRANTIES FOR MECHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE LIMITED TO THE DURATION OF THIS WARRANTY IN THE EVENT THE PRODUCT IS NOT FREE FROM DEFECTS AS WARRANTED ABOVE THE PURCHASER S SOLE REMEDY SHALL BE REPAIR OR REPLACEMENT AS PROVIDED ABOVE UNDER NO CIRCUMSTANCES WILL REAL TIME DEVICES BE LIABLE TO THE PURCHASER OR ANY USER FOR ANY DAMAGES INCLUDING ANY INCIDENTAL OR CONSEQUENTIAL DAM AGES EXPENSES LOST PROFITS LOST SAVINGS OR OTHER DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PRODUCT SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSE QUENTIAL DAMAGES FOR CONSUMER PRODUCTS AND SOME STATES DO NOT ALLOW LIMITA TIONS ON HOW LONG AN IMPLIED WARRANTY LASTS SO THE ABOVE LIMITATIONS OR EXCLU SIONS MAY NOT APPLY TO YOU THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS AND YOU MAY ALSO HAVE OTHER RIGHTS WHICH VARY FROM STATE TO STATE
59. AI AA e 4 15 Interrupt Request Lines A E san 4 15 8259 Programmable Interrupt Controllers sssssssesssssssssesssseessveesssecsssesssseecsuvecssecssscstuscsasecssossesescesscensees 4 15 Interrupt Mask Registers IMR 4 15 End of Interrupt EOI Command 7 7 7 cos 4 16 What Exactly Happens When an Interrupt Occurs 34 4 16 000 0 4 16 Writing an Interrupt Service Routine ISR 4 16 Saving the Startup Interrupt Mask Register IMR and Interrupt Vector 4 17 Restoring the Startup IMR and Interrupt Vector 334 ttt tette ttt 4 18 4 18 0 Data Transfers Using DMA e e a 4 18 Choosing 4 19 Allocating a DMA Buffer ad 4 19 4 19 Calculating the Page and Offset of a Buffer Setting the DMA Page RC 4 21 The DMA COM easi EU IIR pret etwa 4 21 ii DMA Single Mask Register russ 4 21 Mode ERS onen 4 22 Programming the DMA Controller ed 4 22 Programming the 2700 MA a el 4 22 Monitoring for DMA 4 23 Common DMA Pr
60. Clock Sources Factory Settings CLK1 OSC CLK2 OT1 1 5 P8 Interrupt Source and Channel Factory Setting Jumpers on OT2 amp Interrupt Chs Disabled 1 6 P10 DAC 1 Output Voltage Range Factory Setting 5 to 5 1 7 P11 DAC 2 Output Voltage Range Factory Setting 5 to 5 volts eerte 1 8 P13 Single Ended Differential Analog Inputs Factory Setting Single Ended 1 8 P14 A D Converter Status External Gate 2 Monitor Factory Setting EOC A D Converter Status 1 9 P15 A D Data Word Bit State Set Factory Setting 1 9 51 Base Address Factory Setting 300 hex 768 decimal 1 9 S2 Buffer Bypass Switch Factory Setting OPEN Not Bypassed 1 10 Pull up Pull down Resistors on Digital I O Lines 1 11 cas 1 13 CHAPTER 2 BOARD 5 0 2 1 Board Installation ae rein da 2 3 External VO COS Per rege 2 3 Connecting the Analog Input Pins eese 2 4 Connecting the Trigger In and Trigger Out Pins Cascading 5
61. Counter Latch Command is received This count is held in the latch until it is read by the CPU or until the Counter is reprogrammed The count is then unlatched automatically and the OL returns to following the counting element CE This allows reading the contents of the Counters on the fly without affecting counting in progress Multiple Counter Latch Commands may be used to latch more than one Counter Each latched Coun ter s OL holds its count until it is read Counter Latch Commands do not affect the programmed Mode of the Counter in any way Counter is latched and then some time later latched again before the count is read the second Counter Latch Command is ignored The count read will be the count at the time the first Counter Latch Command was issued With either method the count must be read accord ing to the programmed format specifically if the Counter is programmed for two byte counts two bytes must be read The two bytes do not have to be read one right after the other read or write or pro gramming operations of other Counters may be in serted between them Another feature of the 82C54 is that reads and writes of the same Counter may be interleaved for example if the Counter is programmed for two byte counts the following sequence is valid 1 Read least significant byte 2 Write new least significant byte 3 Read most significant byte 4 Write new most significant byte Co
62. GATE 1 enables counting GATE 0 disables counting If GATE goes low while OUT is low OUT is set high immediately no CLK pulse is required A trigger reloads the Counter with the initial count on the next CLK pulse Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This allows the Counter to be synchronized by software also Writing a new count while counting does not affect the current counting Sequence If a trigger is re ceived after writing a new count but before the end of the current half cycle of the Square wave the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count Otherwise the new count will be loaded at the end of the current half cycle Mode 3 is implemented as follows Even counts OUT is initially high The initial count is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses When the count expires OUT changes value and the Counter is re loaded with the initial count The above process is repeated indefinitely Odd counts OUT is initially high The initial count minus one an even number is loaded on one CLK pulse and then is decremented by two on succeed ing CLK pulses One CLK pulse after the count ex pires OUT goes low and the Counter is reloaded with the initial count minus one Succeeding CLK pulses decrement t
63. GND OV 40 C to 85 for Extended Temperature BUS PARAMETERS READ CYCLE Parameter A ms wn Address Stable Betor 0 AdoressHoldTmeAterAD 1 o tan RDPusewim tro DataDelaytromAD to toDetaFioating 200 Recovery Time between RD WR WRITE CYCLE Parameter 420542 E Max taw o tow Www Address Stable Before WR 4 HEN tm tow DataSetupTimeBetore 100 ruo Ports A amp B er pum ES ms ms 80 3 142 intel 82C55A OTHER TIMINGS Parameter 82055A 2 Units Conditions WR 1 to Output Peripheral Data Before R Peripheral Data After ACK Pulse Width STB Pulse Width Per Data Before STB High Per Data After STBHigh 0 to Output 1 to Output Float WR 1to0BF 0 0 to OBF 1 B Oto 1 110 8 0 RD 0toINTR 0 STB 1 to INTR 1 16 INTR 1 WR OtoINTR 0 ings _ Reset Pulse Width NOTE 1 INTR 7 may occur as early as WR 2 Pulse width of initial Reset pulse after power on must be at least 50 p Sec Subsequent Reset pulses may be 500 ns minimum 9 gt ST o e 5 Es taos 1 BE lt
64. IBF is a one and INTE is a one It is reset by the falling edge of 2 This procedure allows input device to re quest service from the CPU by simply strobing its data into the port CONTROL WORD INTE A Controlled by bit set reset of PC4 INTE B 231256 13 Controlled by bit set reset of PC Figure 8 MODE 1 Input INPUT FROM PERIPHERAL 231256 14 Figure 9 MODE 1 Strobed Input 3 134 intel 82C55A Output Control Signal Definition OBF Output Buffer Full F F The OBF output wili go low to indicate that the CPU has written data Out to the specified port The OBF F F will be set by the rising edge of the WR input and reset by ACK Input being low ACK Acknowledge Input A low on this input informs the 82C55A that the data from Port A or Port B has been accepted In essence a response from the peripheral device indicating that it has received the data output by the CPU INTR interrupt Request high on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU INTR is set when is a one OBF is a one and INTE is a one It is reset by the falling edge of WR INTE A Controlled by bit set reset of PCs INTE Controlled by bit set reset of MODE PORT A CONTROL WORD Dy Dg Dy D 0 D D D Pas te INPUT MODE 1 PORT 8 CONTROL W
65. MA Page Register Oddly enough you do not inform the DMA controller directly of the page to be used Instead you put the page to be used into the DMA page register with the least significant bit set to zero The DMA page register is separate from the DMA controller as shown in the table below DMA Channel Location of Page Register 2727 The DMA Controller The DMA controller is made up of two complex 8237 chips one for DMA channels 0 3 and one for channels 4 7 that occupy 32 contiguous bytes of the AT I O port space starting with port COH A complete discussion of how it operates is beyond the scope of this manual only relevant information is included here The DMA controller is programmed by writing to the DMA registers in your AT The table below lists these registers DMA Registers Address hex decimal 65 059 ENT CT 2122 D8 216 Byte Pointer Flip Flop If you are using DMA channel 5 write your page offset bits to port C4H and the count to C6H for channel 6 write the offset to C8H and the count to CAH for channel 7 write the offset to CCH and the count to CEH The page offset bits are the bits you calculated as shown above Count indicates the number of samples that you want the DMA controller to transfer The value that you write to the DMA controller is number of samples 1 The single mask register and mode register are described below
66. ORD D 0 D 0 D 0 D D 231256 16 Figure 11 MODE 1 Strobed Output 3 135 82 55 Combinations of MODE 1 Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed 1 0 applications CONTROL WORD D 0 D D D Dz 0 D DONADO 1 INPUT 0 OUTPUT PORT A STROBED INPUT PORT 8 STROBED OUTPUT CONTROL WORD D Ds D 0 0 0 D Ps 1 INPUT 0 OUTPUT PORT STROBED OUTPUT PORT 8 STROBED INPUT 231256 17 Figure 12 Combinations of MODE 1 Operating Modes MODE 2 Strobed Bidirectional Bus 1 O This functional configuration provides a means for com municating with a peripheral device or structure on a single 8 bit bus for both transmitting and receiving data bidirectional bus 1 0 Handshaking signals are provided to maintain proper bus flow discipline in a similar manner to MODE 1 interrupt generation and enable disable functions are also available MODE 2 Basic Functional Definitions e Used in Group A only e One 8 bit bi directional bus port Port A and a 5 bit control port Port Both inputs and outputs are latched e The 5 bit control port Port C is used for control and status for the 8 bit bi directional bus port Port A Bidirectional Bus Control Signal Definition INTR interrupt Request A high on this output can be used to interr
67. P2 I O connector labeled PA PB PCL and PCH PA and PB take 10 pin packs and PCL and PCH take 6 pin packs Figure 1 17 shows blowup of the PA PCL and PCH resistor pack locations PB is located to the left of P12 After the resistor packs are installed you must connect them into the circuit as pull ups or pull downs Locate the three hole pads on the board near the resistor packs They are labeled G for ground on one end and V for 5V on the other end The middle hole is common is for Port A PB is for Port B is for Port C Lower and PCH is for Port C Upper Figure 1 17 shows these pads To operate as pull ups solder a jumper wire between the common pin middle pin of the three and the V pin For pull downs solder a jumper wire between the common pin middle pin and the G pin Figure 1 18 shows Port A lines with pull ups Port C Lower with pull downs and Port C Upper with no resistors ar on 90000 ur 9000000000 0 99000000000 2 0000000060 99000060000 90006600000 6090000000000 A 0000000 0222388 1 0 0 74HCTO4 oo oo 900000000000 Y 6000055 ons oo QSooooooooooo 52 99 E 0 74HCT130 00000000 9 999666 a ou B 6 50 5598500 7 600000000 s 9000000000 0555500555000 1990000000900
68. Sampled not 100 tested TA 25 C 6 CLK present at Twc min then Count equals N 2 CLK pulses max equals Count N 1 CLK pulse Twc min to max count will be either 1 or N 2 CLK pulses 7 Modes 1 and 5 if GATE is present when writing a new Count value at min Counter will not be triggered at Two max Counter will be triggered 8 If CLK present when writing a Counter Latch or ReadBack Command at Tc min CLK will be reflected in count vaiue latched at Tc max CLK will not be reflected in the Count value latched Writing a Counter Latch or ReadBack Command between Tc min and Tw max will result in a latched Count vallue which is one least significant bit EXTENDED TEMPERATURE T A 40 C to 85 for Extended Temperature Parameter 82054 826542 MNT mcm wc 5 as 25 ae 6 Gate Delay for Sampling intel 8254 WAVEFORMS WRITE DATA 808 231244 14 DATA BUS 231244 15 RECOVERY 231244 16 3 98 intel 82054 CLOCK AND GATE tas twG ta too 1009 231244 17 Last byte of count being written A C TESTING LOAD CIRCUIT 231244 18 Testing Inputs are driven at 2 4V for a logic 1 and 0 45V for a logic 0 Timing measurements are made amp t 2 0V for a logic 1 and 0 8V for a logic 0 231244 19 CL 150 pF
69. Settings 4 Set P15 to the same polarity Fig 1 3 Analog Input Voltage Polarity Jumper P4 P5 DMA Request Channel Factory Setting Disabled This header connector shown in Figure 1 4 lets you select channel 5 6 or 7 for DMA transfers This line the DMA request line DRQ must be set to the same channel as the DACK line on P6 The factory setting is DMA disabled Note that if any other device in your system is already using your selected DMA channel channel conten tion will result causing erratic operation 5 5 DRQ6 DRQ7 Fig 1 4 DMA Request Channel Jumper P5 14 P6 DMA Acknowledge Channel Factory Setting Disabled This header connector shown in Figure 1 5 lets you select channel 5 6 or 7 for DMA transfers This line the DMA acknowledge line DACK must be set to the same channel as the DRQ line on PS The factory setting is DMA disabled Note that if any other device in your system is already using your selected DMA channel channel contention will result causing erratic operation P6 DACK5 DACK6 DACK7 Fig 1 5 DMA Acknowledge Channel Jumper P6 P7 8254 Timer Counter Clock Sources Factory Settings CLK1 OSC CLK2 0T1 This header connector shown in Figure 1 6 lets you select the clock sources for the 8254 timer counters TCO and TC2 TCO and TC1 are cascaded to form the pacer clock You must install two or three jumpers in order to pr
70. TA SHEETS Intel 82054 Programmable Interval Timer Data Sheet Reprint intel 82C54 CHMOS PROGRAMMABLE INTERVAL TIMER Compatible with all Intel and most Three independent 16 bit counters other microprocessors Low Power CHMOS B High Speed Zero Wait State lcc 10 mA e 8 MHz Count Operation with 8 MHz 8086 88 and frequency 80186 188 m Handles Inputs from DC to 8 MHz 10 MHz for 82C54 2 Six Programmable Counter Modes Available in EXPRESS Binary or BCD counting Standard Temperature Range Status Read Back Command Extended Temperature Range Available in 24 Pin DIP and 28 Pin PLCC The Intel 82C54 is a high performance CHMOS version of the industry standard 8254 counter timer which is designed to solve the timing contro problems common in microcomputer system design It provides three independent 16 bit counters each capable of handling clock inputs up to 10 MHz All modes are software programmable The 82C54 is pin compatible with the HMOS 8254 and is a superset of the 8253 B Completely TTL Compatible Six programmable timer modes allow the 82C54 to be used as an event counter elapsed time indicator programmable one shot and in many other applications The 82C54 is fabricated on Intel s advanced CHMOS technology which provides low power consumption with performance equal to or greater than the equivalent HMOS product The 82C54 is available in
71. a Delay nom tap Data Delay rom Ad ress 8 hor ROT wDataFioating s 9 5 6 iw Command RecoveryTime 30 1 n 1 AC timings measured at 2 0V O 8V 3 96 intel 82654 CHARACTERISTICS Continued WRITE CYCLE Parameter Address Stable Before WR CS Stable Before WR Address Hold Time After WR WR Pulse Width 5 gt gt ff Data Setup Time Before WR two Dale Hold Tina CIA Command Recovery Time 200 165 CLOCK AND GATE Parameter Clock Period High Pulse Width Low Pulse Width Clock Rise Time Clock Fall Time Gate Width High EE a 81 Gate Width Low 50 _ f w ame up Tene 10 ae Gate Hold Time After CLK f 51 06 Output Delay from CLK 4 Output Delay from Gate 100 LK Delay for Loading 4 Gate Delay for Sampling 4 UT Delay from Mode Write CLK Set Up for Count Latch ipwL liii ii teL NOTES 2 Modes 1 and 5 triggers are sampled on each rising clock edge A second trigger within 120 ns 70 ns for the 82 54 2 of the rising clock edge may not be detected 3 Low going glitches that violate tew may cause errors requiring counter reprogramming 4 Except for Extended Temp See Extended Temp A C Characteristics below 5
72. able at the OUT 1 pin P2 42 and Timer Counter 278 output is available at T C 2 OUT P2 44 where they can be used for interrupt generation as an A D trigger or for counting functions The timer counters can be programmed to operate in one of six modes depending on your application The following paragraphs briefly describe each mode Mode 0 Event Counter Interrupt on Terminal Count This mode is typically used for event counting While the timer counter counts down the output is low and when the count is complete it goes high The output stays high until a new Mode 0 control word is written to the timer counter Mode 1 Hardware Retriggerable One Shot The output is initially high and goes low on the clock pulse following a trigger to begin the one shot pulse The output remains low until the count reaches 0 and then goes high and remains high until the clock pulse after the next trigger Mode 2 Rate Generator This mode functions like a divide by N counter and is typically used to generate a real time clock interrupt The output is initially high and when the count decrements to 1 the output goes low for one clock pulse The output then goes high again the timer counter reloads the initial count and the process is repeated This sequence continues indefinitely Mode 3 Square Wave Mode Similar to Mode 2 except for the duty cycle output this mode is typically used for baud rate generation The output is initially high and w
73. about these accessories and for help in choosing the best items to support your board s application Application Software and Drivers Our custom application software packages provide excellent data acquisition and analysis support Use SIGNAL MATH for integrated data acquisition and sophisticated digital signal processing and analysis or ATLANTIS for real time monitoring and data acquisition rtdLinx and rtdLinx labLinx drivers provide full featured high level interfaces between the 2700 and custom or third party software including LABTECH NOTEBOOK XE and LT CONTROL rtdLinx source code is available for a one time fee Our Pascal and C Programmer s Toolkit provides routines with documented source code for custom programming Hardware Accessories Hardware accessories for the 2700 include the MX32 analog input expansion board which can expand a single input channel on your 2700 to 16 differential or 32 single ended input channels MR series mechanical relay output boards OP series optoisolated digital input boards the TS16 temperature sensor board the TB50 terminal board and XB50 prototype terminal board for easy signal access and prototype development the EX XT and EX AT extender boards for simplified testing and debugging of prototype circuitry and XT50 twisted pair wire flat ribbon cable assembly for external interfacing Using This Manual This manual is intended to help you install your new board and get it running quic
74. al mode for filling an array with data Triggering is automatic so your program is spared the chore of monitoring the pacer clock to determine when to sample See the MULTI sample program in C and Pascal External Trigger In this mode a single conversion is initiated by the rising edge of an external trigger pulse This mode is implemented when an external device is used to determine when to sample See the EXTTRIG sample program in C and Pascal Starting an A D Conversion Software triggered single conversions are started by writing to the START CONVERT port at BA 0 The value you write is irrelevant For single conversions you must write to this port to initiate every conversion Externally triggered single conversions and multiple conversions triggered by the pacer clock through the external trigger are started by the first pulse present after the external trigger has been enabled Monitoring Conversion Status DMA Done or End of Convert The A D conversion status can be monitored through the DMA done flag or through the end of convert EOC bit in the STATUS port at BA 2 When doing transfers you will want to monitor the done flag for a transition from low to high This tells you when a DMA transfer is complete and data has been placed in the PC s memory The EOC line is available for monitoring conversion status when performing single conversions not using DMA transfer When the EOC goes from low to high the A D conver
75. ate of the 820254 is undefined The Mode count value and output of all Counters are undefined How each Counter operates is determined when it is programmed Each Counter must be programmed before it can be used Unused counters need not be programmed Control Word Format Ay 11 CS 0 RD 1 D De Ds Dy Programming the 82C54 Counters are programmed by writing a Control Word and then an initial count The control word format is shown in Figure 7 Control Words are written into the Control Word Register which is selected when Ay Ag 11 The Control Word itself specifies which Counter is being programmed By contrast initial counts are written into the Coun ters not the Control Word Register The A4 Ag in puts are used to select the Counter to be written into The format of the initial count is determined by the Control Word used D3 92 D Do 561 sco nwo ve co SC Select Counter SC1 SCO 0 0 Select Counter 0 TA Select Counter 1 Select Counter 2 Read Back Command 1 4 See Read Operations RW Read Write RW1 RWO Counter Latch Command see Read Operations 011 Read Write least significant byte only Read Write most significant byte only 1 1 Read Write least significant byte first then most significant byte NOTE Don t care bits X should be O to insure compatibility with future Intel products
76. count and status of the selected counter s may be latched simultaneously by setting both COUNT and STATUS bits D5 D4 0 This is func tionally the same as issuing two separate read back commands at once and the above discussions ap ply here also Specifically if multiple count and or status read back commands are issued to the same counter s without any intervening reads all but the first are ignored This is illustrated in Figure 13 If both count and status of a counter are latched the first read operation of that counter will return latched status regardless of which was latched first The next one or two reads depending on whether the counter is programmed for one or two type counts return latched count Subsequent reads return un latched count Results Count and status latched for Counter 0 Figure 13 Read Back Command Example Write into Counter 1 Write into Counter 2 Write Control Word Read from Counter 0 Read from Counter 1 Read from Counter 2 No Operation 3 State No Operation 3 State 1 No Operation 3 State Figure 14 Read Write Operations Summary Mode Definitions The following are defined for use in describing the operation of the 82C54 CLK PULSE a rising edge then a falling edge in that order of a Counter s CLK input TRIGGER a rising edge of a Counter s GATE in put COUNTER LOADING the transfer of a count from the CR to the CE refer to the Fu
77. der of the switch numbers on the switch 1 through 4 before setting them When the switches are pulled forward they are OPEN or set to logic 1 as labeled on the DIP switch package When you set the base address for your board record the value in the table inside the back cover Figure 1 15 shows the DIP switch set for a base address of 300 hex 768 decimal Table 1 2 Base Address Switch Settings 1 Base Address Switch Setting Decimal Hex 4321 Decimal Hex 4321 512 200 1000 544 220 1001 szew 1010 1011 60 080 sse 1100 672 2A0 1101 74 000 95 80 1110 736 2E0 1111 0 closed 1 open Fig 1 15 Base Address Switch 1 S2 Buffer Bypass Switch Factory Setting OPEN Not Bypassed When operating the 8255 in Mode 1 the lines of Port C function as control lines some as outputs and some as inputs When using Mode 1 the Port C buffers must be removed and bypassed to allow the Port C lines to be individually set as inputs or outputs Figure 1 16 shows the Port C buffers and the following steps tell you how to configure the board for Mode 1 operation To remove buffering from Port C 1 Close DIP switches 1 through 8 on 2 2 Remove U8 from the board 3 Remove 09 from the board CAUTION Remember whenever you close the switches be sure to remove the buffers 08 and UO from the board Failure to do so may damage the b
78. e upper 4 bits are the page only the upper 3 bits D17 D18 and D19 are sent to what is called the page register The remaining bit for the page D16 is sent to the base address register of the DMA controller along with bits D1 through D15 Since the buffer sits on a word boundary bit DO must be zero and is ignored The following diagram shows you to which registers the components of the 20 bit linear address are sent 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Lo To 8237 base address MSB To 8237 base address LSB To page register The following examples show you how to calculate the linear address and break it into components to be sent to the various registers In Pascal Segment SEG Buffer Offset OFS Buffer LinearAddress Segment 16 Offset PageBits LinearAddress DIV 65536 AND SOE get segment of buffer get offset of buffer calculate linear address determine page corresponding to this linear address and clear least significant bit OffsetBits LinearAddress SHR 2 MOD 65536 shift linear address to ignore DO then extract bits D1 D16 In C segment FP SEG amp Buffer get segment of buffer offset FP OFS amp Buffer get offset of buffer linear address segment 16 offset calculate linear address pagebits linear address 65536 amp OxOE determine page corresponding to this linear address and cl
79. ear least significant bit offset bits linear address gt gt 2 5 65536 shift linear address to ignore DO then extract bits D1 D16 Beware There is one big catch when using page based addresses The 8237 DMA controller cannot write properly to a buffer that straddles a page boundary A buffer straddles a page boundary if one part of the buffer resides in one page of memory while another part resides in the following page The DMA controller cannot properly write to such a buffer because the DMA controller can only write to one page without reprogramming When it reaches the end of the current page it does not start writing to the next page Instead it starts writing back at the first byte of the current page This can be disastrous if the beginning of the page does not correspond to your buffer More often than not this location is being used by the code portion of your program or the operating system and writing data to it will almost always causes erratic behavior and an eventual system crash 4 20 You must check to see if your buffer straddles page boundary and if it does take action to prevent the DMA controller from trying to write to the portion that continues on the next page You can reduce the size of the buffer or try to reposition the buffer However this can be difficult when using large static data structures and often the only solution is to use dynamically allocated memory Setting the D
80. etting 5 to 5 volts This header connector shown in Figure 1 10 sets the output voltage range for DAC 1 at 0 to 5 5 0 to 10 or 10 volts Two jumpers must be installed one to select the range and one to select the multiplier The two rightmost jumpers select the range bipolar 5 or unipolar 5 The two leftmost jumpers select the multiplier X2 or X1 When a jumper is on the X2 multiplier pins the range values become 10 and 10 The table below shows the four possible combinations of jumper settings and the diagram shows the 5 volt bipolar setting This header does not have to be set the same as 11 9565 or ov 6 or on or on P10 DAC1 2 1 5 5 Fig 1 10 DAC 1 Output Voltage Range Jumper P10 P11 DAC 2 Output Voltage Range Factory Setting 5 to 5 volts This header connector shown in Figure 1 11 sets the output voltage range for DAC 2 at 0 to 5 5 0 to 10 or 10 volts Two jumpers must be installed one to select the range and one to select the multiplier The two rightmost jumpers select the range bipolar 5 or unipolar 5 The two leftmost jumpers select the multiplier X2 or X1 When a jumper is on the X2 multiplier pins the range values become 10 and 10 The table below shows the four possible combinations of jumper settings and the diagram shows the 5 volt bipolar setting This
81. for a gain of 1 while calibrating the board Connect your precision voltage source to channel 1 Set the voltage source to 1 22070 millivolts start a conversion and read the resulting data Adjust trimpot TR7 until it flickers between the values listed in the table at the top of the next page Next set the voltage to 49 49829 volts and repeat the procedure this time adjusting TR2 until the data flickers between the values in the table Note that the value used to adjust the full scale voltage is not the ideal full scale value for a O to 10 volt input range This value is used because it is the maximum value at which the A D converter is guaranteed to be linear and ensures accurate calibration results Table 5 1 A D Converter Bit Weights Unipolar Straight Binary Ideal Input Voltage millivolts A D Bit Weight 0 to 10 Volts 5 4 Data Values for Calibrating Unipolar 10 Volt Range 0 to 10 volts Offset TR7 Converter Gain TR2 Input Voltage 1 22070 mV Input Voltage 9 49829 V 0000 0000 0000 1111 0011 0010 A D Converted Data 0000 0000 0001 1111 0011 0011 Bipolar Calibration Bipolar Range Adjustments 5 to 5 Volts Two adjustments are made to calibrate the A D converter for the bipolar range of 5 to 5 volts One is the offset adjustment and the other 1 the full scale or gain adjustment Trimpot TR3 is used to make the offset adjustment and trimpot TR2 is u
82. ge the jumper on P3 so that it is installed across the 20 pins Leave the P4 and P15 jumpers at Then set the input voltage to 5 0000 volts and adjust TR1 until the output matches the data in the table below Data Value for Calibrating Bipolar 20 Volt Range 10 to 10 volts Input Voltage 5 0000V A D Converted Data 0100 0000 0000 D A Calibration ADA2700 The D A converter requires no calibration for the X1 ranges 0 to 5 and 5 volts The following paragraph describes the calibration procedure for the X2 multiplier ranges To calibrate for X2 0 to 10 or 10 volts set the DAC output voltage range to 0 to 10 volts jumpers on X2 and 5 on P10 AOUTI or P11 2 Then program the corresponding D A converter or DAC2 with the digital value 2048 The ideal DAC output for 2048 at X2 0 to 10 volt range is 5 0000 volts Adjust TRS for and TR6 for AOUT2 until 5 0000 volts is read at the output Table 5 3 lists the ideal output voltages per bit weight for unipolar ranges and Table 5 4 lists the ideal output voltages for bipolar ranges Table 5 3 D A Converter Unipolar Calibration Table D A Bit Weight 010 10 V ne 1958 9 7656 4 8828 Table 5 4 D A Converter Bipolar Calibration Table Ideal Output Voltage in millivolts D A Bit Weight 25 10 V 4095 Max Output 4997 6 9995 1 2048 4375 0 4687
83. gh performance A D converter supports fast settling software programmable gains of 1 2 4 and 8 with on board gain multiplier circuitry so that you can customize the input gain A D conversions are performed in 5 microseconds and the maximum throughput rate is 150 kHz Conversions are controlled through software by an on board pacer clock or by an external trigger brought onto the board through the I O connector The converted data can be transferred through the PC data bus to PC memory in one of two ways by using the microprocessor or by using direct memory access DMA The mode of transfer is software selectable and the DMA channel is chosen by jumper settings on the board The PC data bus is used to read and or transfer data to PC memory In the DMA transfer mode you can make continuous transfers directly to PC memory without going through the processor Digital to Analog Conversion ADA2700 Only The digital to analog D A circuitry on the ADA2700 features two independent 12 bit analog output channels with individually jumper selectable output ranges of 5 to 5 volts 10 to 10 volts O to 5 volts or O to 10 volts Data is programmed into the D A converter and a conversion is automatically triggered for a channel through a single write operation Access through DMA is not available 8254 Timer Counter An 8254 programmable interval timer contains three 16 bit 8 MHz timer counters to support a wide range of timing and counting fu
84. he 5 and 0 to 10 volt ranges have a resolution of 2 44 millivolts and the O to 5 volt range has a resolution of 1 22 millivolts Timer Counters An 8254 programmable interval timer provides three 16 bit 8 MHz timer counters to support a wide range of timing and counting functions Two of the timer counters TCO and TC1 are cascaded so that they can be used for the pacer clock The pacer clock is described in Chapter 4 You can use the remaining timer counter TC2 for counting applications or cascade it to TCO and 1 for timing applications Figure 3 2 shows the timer counter circuitry Each timer counter has two inputs CLK in and GATE in and one output timer counter OUT They can be programmed as binary or BCD down counters by writing the appropriate data to the command word as described in Chapter 4 The command word also lets you set up the mode of operation The six programmable modes are Mode 0 Event Counter Interrupt on Terminal Count Mode 1 Hardware Retriggerable One Shot Mode 2 Rate Generator Mode 3 Square Wave Mode 2700 CONNECTOR 2 t 1 1 1 4 TO A D l TRIGGER P7 CLK 1 PIN 45 EXT CLK Mhz COUNTER EXT GATE 1 TIMER COUNTER CLK TRIGGER IN 1 OUT 1 EXT GATE 2 PIN 441T C OUT 2 Fig 3 2 8254 Timer Counter Circuit Block Diagram 3 4 Mode 4 Software Triggered Strobe Mode 5 Hardware
85. he count by two When the count expires OUT goes high again and the Counter is reloaded with the initial count minus one The above process is repeated indefinitely So for odd counts CW 1 138 4 DOR BRUM DNE GATE M our 8844 GATE __ Our AA AA 31 121 Cwels 4 lA 231244 11 A GATE transition should not occur one clock prior to terminal count Figure 18 Mode 3 MODE 4 SOFTWARE TRIGGERED STROBE OUT will be initially high When the initial count ex pires OUT will go low for one CLK pulse and then go high again The counting sequence is triggered by writing the initial count GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low until 1 CLK pulses after the initial count is written If a new count is written during counting it will be loaded on the next CLK pulse and counting will con tinue from the new count If a two byte count is writ ten the following happens 3 93 204 1 Writing the first byte has no effect on counting 2 Writing the second byte allows the new count to be loaded on the next CLK pulse This allows the sequence to be ret
86. he input to the corresponding AIN pin Then for signal sources with a separate ground reference connect the ground from the signal source to an ANALOG GND pins 18 and 20 22 on P2 Figure 2 3 shows how these connections are made 2 4 2700 VO CONNECTOR 2 Fig 2 2 Single Ended Input Connections 2700 CONNECTOR 2 SIGNAL Fig 2 3 Differential Input Connections 2 5 Connecting the Trigger In and Trigger Out Pins Cascading Boards The 2700 board has an external trigger input P2 39 and output P2 43 so that conversions can be started based on external events or so that two or more boards can be cascaded and run synchronously in a master slave configuration By cascading two or more boards as shown in Figure 2 4 they can be triggered to start an A D conversion at the same time sampling uncertainty is less than 50 nanoseconds When you cascade boards be sure to set each board for a different base address see Chapter 1 or system contention will result NOTE When cascading boards the sampling uncertainty is less than 50 nanoseconds If this level of uncer tainty is too great for your application you can connect the trigger signal to the trigger input of each board In this configuration the boards are not cascaded but rather driven by the same trigger pulse at the same time and the sampling uncertainty is reduced to less than 5 nanoseconds If you apply an external t
87. he software included with your board make a backup copy of the disk You may make as many backups as you need C and Pascal Programs These programs are source code files so that you can easily develop your own custom software for your 2700 board In the C directory 2700 H and 2700 INC contain all the functions needed to implement the main C programs H defines the addresses and INC contains the routines called by the main programs In the Pascal directory 2700 PNC contains all of the procedures needed to implement the main Pascal programs Analog to Digital SOFTTRIG Demonstrates how to use the software trigger mode for acquiring data EXTTRIG Similar to SOFTTRIG except that an external trigger is used MULTI Shows how to fill an array with data using a software trigger Timer Counters TIMER A short program demonstrating how to program the 8254 for use as a timer Digital VO DIGITAL Simple program that shows how to read and write the digital I O lines Digital to Analog DAC Shows how to use the DACs Uses A D channel 1 to monitor the output 0 1 WAVES A more complex program that shows how to use the 8254 timer and the DACs as a waveform generator Interrupts INTRPTS Shows the bare essentials required for using interrupts INTSTRM A complete program showing interrupt based streaming to disk DMA DMA Demonstrates how to use DMA to transfer acquired data to a memory buffer Buffer can be written to disk and viewed with the incl
88. hen it occurs a high logic level does not have to be maintained until the next rising edge of CLK Note that in Modes 2 and 3 the GATE input is both edge and level sensi tive In Modes 2 and 3 if a CLK source other than the system clock is used GATE should be pulsed immediately following WR of a new count value COUNTER New counts are loaded and Counters are decre mented on the falling edge of CLK The largest possible initial count is 0 this is equiva lent to 216 for binary counting and 104 for BCD counting The Counter does not stop when it reaches zero In Modes 0 1 4 and 5 the Counter wraps around to the highest count either FFFF hex for binary count ing or 9999 for BCD counting and continues count ing Modes 2 and 3 are periodic the Counter reloads itself with the initial count and continues counting from there intel 82054 ABSOLUTE MAXIMUM RATINGS Notice Stresses above those listed under Abso lute Maximum Ratings may cause permanent dam Ambient Temperature Under 0 to 70 age to the device This is a stress rating only and Storage Temperature 65 to 150 C functional operation of the device at these or any Supply Voltage 0 5t0 8 0V other conditions above those indicated in the opera Operating Voltage 4Vto 7V tional sections of this specification is not implied Ex Voltage on any Input GND
89. hen the count decrements to one half its initial count the output goes low for the remainder of the count The timer counter reloads and the output goes high again This process repeats indefinitely Mode 4 Software Triggered Strobe The output is initially high When the initial count expires the output goes low for one clock pulse and then goes high again Counting is triggered by writing the initial count Mode 5 Hardware Triggered Strobe Retriggerable The output is initially high Counting is triggered by the rising edge of the gate input When the initial count has expired the output goes low for one clock pulse and then goes high again Digital VO The 24 8255 PPI based digital I O lines can be used to transfer data between the computer and external devices Because the lines are buffered only Mode 0 or Mode 1 operation can be used When using Mode 1 remove the Port C buffers as described in Chapter 1 The digital input lines can have pull up or pull down resistors installed as described in Chapter 1 4 25 Example Programs and Flow Diagrams Included with the 2700 is a set of example programs that demonstrate the use of many of the board s features These examples are written in C and Pascal Also included is an easy to use menu driven diagnostics program 2700DIAG which is especially helpful when you are first checking out your board after installation and when calibrating the board Chapter 5 Before using t
90. hich are external to the programmable gain amplifier If your gain multiplier circuit is set for a gain of 2 then you must tell SIGNAL MATH this setting by entering 2 for gain If your input signal is externally attenuated then you can adjust for this by setting a value other than 1 for loss Numbers must be entered as whole decimal values The factory default setting for gain and loss is 1 For a bipolar input range an X should be placed before Bipolar on the screen default setting For unipolar operation remove the X D A Parameters ADA2700 Only Six D A board parameters are listed resolution number of channels active DMA channel gain loss and input voltage polarity Resolution and number of channels are fixed For the ADA2700 DMA is not used and should be left blank Gain and loss are provided so that you can make adjustments for external gain or loss as described above for the A D parameters For a bipolar output range an X should be placed before Bipolar on the screen default setting For unipolar operation remove the X D 6 APPENDIX E CONFIGURING THE 2700 FOR ATLANTIS E 1 If you have purchased ATLANTIS data acquisition and real time monitoring application software for your 2700 please note that the ATLANTIS drivers for your board must be loaded from your example software disk into the same directory as the ATLANTIS EXE program When running the ATLANTIS data acquisition
91. howing Factory Configured Settings 1 4 Analog Input Voltage Range Jumper eerte tente 1 1 3 Analog Input Voltage Polarity Jumper 4 1 4 DMA Request Channel Jumper P5 1 4 DMA Acknowledge Channel Jumper P6 ssscssscssssssssssssesssssssssssssesssecsesssecsaseesesssasessscssssesuecenesensesosees 1 5 8254 Timer Counter Clock Source Jumpers PT 1 5 8254 Timer Counter Circuit Block Diagram 1 6 Interrupt Channel Jumper 1 6 Pulling Down the Interrupt Request Line 1 1 7 DAC 1 Output Voltage Range Jumper 1710 1 8 DAC 2 Output Voltage Range Jumper 1211 1 8 Single Ended Differential Analog Input Signal Type Jumpers P13 ere 1 8 A D Converter Status External Gate 2 Monitor Jumper 14 1 9 A D Data Word Bit State Set Jumper 15 1 9 Base Address Switch ST esee censent el dp De d 1 10 Port C Buffer CHUR nee 1 11 Pull up Pull down Resistor Circuitry sssscsssesssseessssssssssssssesssssssosssseassvessnscssnscesseeessesssuvsesansosussessnecee 1 12 Adding Pull ups and Pull downs to Digital YO 1 1065 1 13 Gain Circuitry and Formulas for Calculating Gm 1 14 Diagram for Removal of Solder Short 1 14 P2 Connector and
92. ing the Bit Set Reset operation just as if they were data output ports 3 128 intel 82C55A BIT SET RESET 16 SET BIT SELECT 011121314151617 lol sjo Joi 11011 8 6 6 1111819111115 lejo ofol1 vj 11184 BIT SET RESET FLAG 0 ACTIVE 231256 7 Figure 7 Bit Set Reset Format Interrupt Control Functions When the 82C55A is programmed to operate in mode 1 or mode 2 control signals are provided that can be used as interrupt request inputs to the CPU The interrupt request signals generated from port C can be inhibited or enabled by setting or resetting the associated INTE flip flop using the bit set reset function of port C This function allows the Programmer to disallow or allow a specific 1 O device to interrupt the CPU with out affecting any other device in the interrupt struc ture INTE flip flop definition BIT SET INTE is SET Interrupt enable BIT RESET INTE is RESET Interrupt disable Note Mask flip flops are automatically reset during mode selection and device Reset 3 129 intel 82C55A Operating Modes Mode 0 Basic Functional Definitions Two 8 bit ports and two 4 bit ports Mode 0 Basic Input Output This functional con figuration provides simple input and output opera e Any port can be input or output tions for each of the three ports No handshaking e Outputs are latched is required data is simply written to or read from a
93. ing the DMA controller but in general the process is the same The following steps are required when using DMA Choose a DMA channel Allocate a buffer Calculate the page and offset of the buffer Set the DMA page register Program the 8237 DMA controller Program device generating data 2700 Wait until DMA is complete Disable DMA Each step is detailed in the following paragraphs gt Ov tA B torn 4 18 Choosing a DMA Channel There are a number of DMA channels available on the PC for use by peripheral devices The 2700 can use DMA channel 5 6 or 7 The factory setting is DMA disabled You can arbitrarily choose any of these in most cases your choice will be fine Occasionally though you will have another peripheral device for example a tape backup or Bernoulli drive that also uses the DMA channel you have selected This will certainly cause erratic results and can be hard to detect The best approach to pinpoint this problem is to read the documentation for the other periph eral devices in your system and try to determine which DMA channel each uses Allocating a DMA Buffer When using DMA you must have a location in memory where the 8237 DMA controller will place the 16 bit data words which contain the 12 bit A D converted data from the 2700 board This buffer can be either static or dynamically allocated The buffer must start on a word boundary i e even numbered address You shou
94. is block enter the IRQ channel number which corresponds to your jumper setting on P8 Valid channels are IRQ9 through IRQ12 IRQ14 and IRQ15 Timer IT Timer Counter Interrupt This block is not used on the 2700 and should be left blank LabTech SW IT LABTECH NOTEBOOK Software Interrupt This sets the software interrupt address where LABTECH NOTEBOOK s labLINX driver is installed The factory setting is 60 This setting can be ignored when running SIGNAL MATH A D Parameters Six A D board parameters are listed resolution number of channels active DMA channel gain loss and input voltage polarity Resolution and number of channels are fixed by the program for your board End of Convert Timer Counter Interrupt Channel Interrupt Channel Base Address Software Interrupt Address A D DMA D A DMA Channel Channel Select Select External Gain External Gain amp Loss amp Loss A D Unipolar 1 Bipolar 5 Select D A Unipolar Bipolar Select Fig 0 4 ADAINST EXE Screen 5 If you are using DMA transfer you must enter the channel number which corresponds to the jumper settings in the DMA channel block Valid channels numbers are 5 6 and 7 The next two blocks gain and loss are provided so that you can make adjustments for external gain or loss other than the programmable gain settings available on the board For example on the 2700 you can set a gain multiplier circuit by adding some resistors w
95. is initial ized and ready to run Selecting a Channel To select a conversion channel you must assign values to bits 0 through 3 at BA 4 The table below shows you how to determine the bit settings Note that if you do not want to change the gain setting also programmed through BA 4 you must preserve it when you set the channel gt gt x m Setting the Gain You may choose among the various levels of programmable gain by setting bits 4 and 5 at BA 4 The table below shows you how to determine the bit settings for the gain you need If you have a gain multiplying resistor installed as described in Chapter 1 then our actual gain values will be those in the table multiplied by the gain multiplier s value Note that if you do not want to change the channel setting also programmed through BA 4 you must preserve it when you set the gain 1 1 1 Enabling and Disabling the External Trigger Any time you use the external trigger or the pacer clock this bit at port 4 must be set high to enable A D conversions Enabling and Disabling IRQ Any time you use interrupts this bit at port BA 4 must be set high to enable the on board interrupt circuitry Conversion Modes Triggering The 2700 has three triggering conversion modes Figure 4 1 shows the timing diagram for A D conversions This section describes the conversion modes
96. ith performance equal to or greater than the equivalent NMOS product The 82 55 is available in 40 pin DIP and 44 pin plastic leaded chip carrier PLCC packages 231256 1 Figure 1 82C55A Block Diagram 231256 2 Figure 2 82C55A Pinout Diagrams are for pin reference only Package sizes are not to scale September 1987 3 124 Order Number 231256 004 intel 82C55A Table 1 Pin Description Pin Number EN Dip Name and Function PORT A PINS 0 3 Lower nibble of an 8 bit data output latch buffer and an 8 bit data input latch READ CONTROL This input is low during CPU read operations CHIP SELECT A low on this input enables the 82C55A to respond to RD and WR signals RD and WR are ignored otherwise ADDRESS These input signals in conjunction RD and WA control the selection of one of the three ports or the control word registers Rb WR cs Input Operation Read po 0 Bus ofa 0 otB DeaBu 3 1 1 0 Cono Wor Data Bus Output Operation Write lo o DataBus PorA Lo pi fo 11 8800080 pt ts DaaBu Cowo Disable Function 009865 3 866 x 0 986 3 865 0 1 x 10 13 11 13 15 1 0 PORT C PINS 4 7 Upper nibble of an 8 bi
97. kly while also providing enough detail about the board and its functions so that you can enjoy maximum use of its features even in the most complex applications We assume that you already have an understanding of data acquisition principles and that you can customize the example software or write your own applications programs When You Need Help This manual and the example programs in the software package included with your board provide enough information to properly use all of the board s features If you have any problems installing or using this board contact our Technical Support Department 814 234 8087 during regular business hours eastern standard time or eastern daylight time or send a FAX requesting assistance to 814 234 5218 When sending a FAX request please include your company s name and address your name your telephone number and a brief description of the problem 14 1 BOARD SETTINGS The AD2700 and ADA2700 boards have jumper and switch settings you can change if necessary for your application The 2700 is factory configured with the most often used settings The factory settings are listed and shown on a diagram in the beginning of this chapter Should you need to change these settings use these easy to follow instructions before you install the board in your computer Note that DIP switch S2 is provided to bypass the Port C buffers and allow Mode 1 operation of the 8255 Also note that b
98. ld force your compiler to use word alignment for data Be sure that its location will not change while DMA is in progress The following code examples show how to allocate buffers for use with DMA In Pascal Var Buffer Array 1 10000 of Byte static allocation Var Buffer Byte dynamic allocation Buffer GetMem 10000 In C char Buffer 10000 static allocation char Buffer dynamic allocation Buffer calloc 10000 0 Calculating the Page and Offset of a Buffer Once you have a buffer into which to place your data you must inform the 8237 DMA controller of the location of this buffer This is a little more complex than it sounds because the DMA controller uses a page offset memory scheme while you are probably used to thinking about your computer s memory in terms of a segment offset Scheme Paged memory is simply memory that occupies contiguous non overlapping blocks of memory with each block being 64K one page in length The first page page 0 starts at the first byte of memory the second page page 1 starts at byte 65536 the third page page 2 at byte 131072 and so on A computer with 640K of memory has 10 pages of memory The DMA controller can write to or read from only one page without being reprogrammed This means that the DMA controller has access to only 64K of memory at a time If you program it to use page 3 it cannot use any other page until you reprogram it to do
99. lly no external logic is neces sary to interface peripheral devices or structures Data Bus Buffer This 3 state bidirectional 8 bit buffer is used to inter face the 82C55A to the system data bus Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU Control words and status information are also transferred through the data bus buffer Read Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words accepts inputs from the CPU Address and Control busses and in turn issues commands to both of the Control Groups Group A and Group B Controis The functional configuration of each port is pro grammed by the systems software In essence the CPU outputs a control word to the 82C55A The control word contains information such as mode set bit reset etc that initializes the func tional configuration of the 82C55A nern 4 men Each of the Control blocks Group and Group accepts commands from the Read Write Control Logic receives control words from the internal data bus and issues the proper commands to its as sociated ports Control Group Port A and Port C upper C7 C4 Control Group B Port B and Port C lower C3 CO The control word register can be both written and read as shown in the address decode table in
100. loat Leakage Current u IPHL Port Hold Low Leakage Current 50 300 pA Vout 1 0V Port A only nA Port Hold Low Overdrive Current 850 A enno Port Hoia High Overarve pA to m motes pA Notice Stresses above those listed under Abso lute Maximum Ratings may cause permanent dam age to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera tional sections of this specification is not implied posure to absolute maximum rating conditions for extended periods may affect device reliability Test Conditions 1 Vc V 25 loH 2 5 lt lt 100 uA Vin Vcc to OV 1 pA Note 1 10 pA Vin Voc to OV Note 2 mA 1 7 VouT 3 0V Ports A B C Vout 0 8V Vout 3 0V 5 5 Vin or GND Port Conditions If 1 P Open High Open Only With Data Bus High Low CS High Reset Low Pure inputs Low High 3 141 intel 82 55 CAPACITANCE 25 C GND OV Parameter Mm Input Capacitance 0 Cuyo NOTE 5 Sampled not 100 tested Unmeasured pins returned to GND fe 1 2 5 A C CHARACTERISTICS Ta 0 to 70 C 5V 10
101. lue will not reflect the new count just written The operation of Null Count is shown in Figure 12 Command D 56 05 54 03 02 0 Do 8 1 Description 111 Read back count and status of Counter 0 Eo A Oe 00 0 Read back status of Counter 1 Status latched for Counter 1 111 1 1 Read back status of Counters 2 1 Status latched for Counter 2 but not Counter 1 1 1 Read back count of Counter 2 Count latched for Counter 2 1 1 Read back count and status of Count latched tor Counter 1 Counter 1 but not status Read back status of Counter 1 Command ignored status already latched for Counter 1 THIS ACTION A Write to the control word 1 Write to the count register CR 12 C New count is loaded into CE CR CE CAUSES Null count 1 Null count 1 Null count 0 1 Only the counter specified by the control word will have its null count set to 1 Null count bits of other counters are unaffected 2 If the counter is programmed for two byte counts least significant byte then most significant byte null count goes to 1 when the second byte is written Figure 12 Null Count Operation If multiple status latch operations of the counter s are performed without reading the status all but the first are ignored i e the status that will be read is the status of the counter at the time the first status read back command was issued Both
102. ly be set for bipolar 4 The input ranges allowed by the 2700 are 5 10 and 0 to 10 volts NOTE P4 and P15 must be set the same for proper board operation 1 3 ADORE FO e DI 686 0 Eur 81 24 _ 00005 o 0678 0 6 slo ol 5122 eue 5 0 o 5 0 oi 5 6 39 8399938 SAS loo 0 R o lollo o 6 olo o Sa fone ol lo 900009280998 5 ol Jon C D GSDqoQ E y e ER 000 1 forces 8 080000000007 79000000000 99000000000 _ DATA ACQUISITION amp CONTROL SYSTEM 1 8090000090000 0000000 d 000000 8 5 3 oj 2jo 3900000000000 A 00000000 6 org 2 tm s i 9 1997987 BN 00000000 _ 999999 o OLIO 8 DE 6 t 5 8 2000909000 a 81219 5 5 CMM II 1 00000000000 00000000000 91055555555589 oj 00000 0 0 0 0 o o o OD 5 jo 9 10688 280000000009 95555591555555550 Real Time Devices lnc State College Pa 16804 USA Fig 1 1 Board Layout Showing Factory Configured
103. mper 14 P15 A D Data Word Bit State Set Factory Setting This header connector shown in Figure 1 14 sets the state of the unused four bits in the 16 bit A D data word This header ensures that these four topmost bits are set at O for unipolar conversions and at the same state as the MSB of the 12 bit A D converted data for bipolar conversions Chapter 4 BA 0 explains this in more detail NOTE 15 and P4 must be set the same for proper board operation P15 Set P4 to the same polarity Fig 1 14 A D Data Word Bit State Set Jumper P15 S1 Base Address Factory Setting 300 hex 768 decimal One of the most common causes of failure when you are first trying your board is address contention Some of your computer s I O space is already occupied by internal 1 and other peripherals When the 2700 board attempts to use I O address locations already used by another device contention results and the board does not work To avoid this problem the 2700 has an easily accessible four position DIP switch S1 which lets you select any one of 16 starting addresses in the computer s I O Should the factory setting of 300 hex 768 decimal be unsuitable for your system you can select a different base address simply by setting the switches to any one of the values listed in Table 1 2 The table shows the switch settings and their corresponding decimal and hexadecimal in parentheses values Make sure that you verify the or
104. n Program DMA Controller Enable DMA amp External Trigger Done 1 Yes Stop Program Fig 4 5 DMA Flow Diagram 4 28 Interrupts Flow Diagram Figure 4 6 This flow diagram shows you how to program an interrupt routine for your 2700 The diagram parallels the interrupts discussion included earlier in this chapter You can use this diagram in conjunction with the detailed text in this chapter to develop an interrupt program for your 2700 Clear Board Save startup IMR value Select IRQ source Save startup interrupt vector Clear IRQ bit in IMR Set IRQ bit in IMR Body of user program Vector new interrupt service Restore startup routine ISR interrupt vector Program interrupt Restore startup Fig 4 6 Interrupts Flow Diagram D A Conversion Flow Diagram ADA2700 Only Figure 4 7 This flow diagram shows you how to generate a voltage output through the D A converter on the ADA2700 A conversion is initiated each time the digital data is written to the D A converter Clear Board Write 12 bit digital data and updat DAC Continue Stop Program Fig 4 7 D A Conversion Flow Diagram 4 30 5 CALIBRATION This chapter tells you how to calibrate the 2700 using the 2700DIAG calibration program included in the example software package and six trimpots on the board These trimpots calibrate the A D c
105. n desirable to read the value of a Counter without disturbing the count in progress This is easi ly done in the 82C54 There are three possible methods for reading the counters a simple read operation the Counter 3 88 Latch Command and the Read Back Command Each is explained below The first method is to per form a simple read operation To read the Counter which is selected with the A1 AO inputs the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic Other wise the count may be in the process of changing when it is read giving an undefined result 2204 COUNTER LATCH COMMAND The second method uses the Counter Latch Com mand Like a Control Word this command is written to the Control Word Register which is selected when Ay 11 Also like a Control Word the SCO SC1 bits select one of the three Counters but two other bits D5 and DA distinguish this command from a Contro Word Ai 11 CS 0 RD 1 WR 0 D7 De Ds D3 D D 0 X TX SC1 500 specify counter to be latched 1 5 0 05 04 00 designates Counter Latch Command X don t care NOTE Don t care bits X should be 0 to insure compatibility with future intel products Figure 9 Counter Latching Command Format The selected Counter s output latch OL latches the count at the time the
106. nctional Descrip tion MODE 0 INTERRUPT ON TERMINAL COUNT Mode 0 is typically used for event counting After the Contro Word is written OUT is initially low and will remain low until the Counter reaches zero OUT then goes high and remains high until a new count or a new Mode 0 Control Word is written into the Coun ter GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT After the Contro Word and initial Count are written to a Counter the initial count will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of N OUT does not go high until N 1 CLK pulses after the initial count is written If a new count is written to the Counter it will be loaded on the next CLK pulse and counting will con tinue from the new count If a two byte count is writ ten the following happens 1 Writing the first byte disables counting OUT is set low immediately no clock pulse required 2 Writing the second byte allows the new count to be loaded on the next CLK pulse This allows the counting sequence to be synchroniz ed by software Again OUT does not go high until N 1 CLK pulses after the new count of is written If an initial count is written while 0 it will still be loaded on the next CLK pulse When GATE goes high OUT will go high CLK pulses later no CLK pulse is needed to load the Counter as this has already been do
107. nctions Two of the timer counters are cascaded and can be used internally for the pacer clock The third is available for counting applications or it can be cascaded to the other two timer counters Digital VO The 2700 has 24 TTL CMOS compatible digital I O lines which can be directly interfaced with external devices or signals to sense switch closures trigger digital events or activate solid state relays These lines are provided by the on board 8255 programmable peripheral interface chip The 8255 can be operated in one of two modes Mode 0 or Mode 1 To ensure high driving capacity CMOS buffers are installed TTL buffers are available on request Pads for installing and activating pull up or pull down resistors are included on the board Installation proce dures are given near the end of Chapter 1 Board Settings What Comes With Your Board You receive the following items in your 2700 package AD2700 ADA2700 interface board Software and diagnostics diskette with Turbo Pascal and Turbo source code User s manual If any item is missing or damaged please call Real Time Devices Customer Service Department at 814 234 8087 If you require service outside the U S contact your local distributor Board Accessories In addition to the items included in your 2700 package Real Time Devices offers a full line of software and hardware accessories Call your local distributor or our main office for more information
108. ne 60515 4 GATE 10 089 3 10 85 3 rer jj A 231244 8 18822 NOTE The Following Conventions Apply To Mode Timing Diagrams 1 Counters are programmed for binary not BCD Counting and for Reading Writing least significant byte LSB only 2 The counter is always selected CS always low 3 CW stands tor Control Word CW 10 means a control word of 10 hex is written to the counter 4 LSB stands for Least Significant Byte of count 5 Numbers below diagrams are count values The lower number is the least Significant byte The upper number is the most significant byte Since the counter is programmed to Read Write LSB only the most significant byte cannot be read stands for an undefined count Vertical lines show transitions between count values Figure 15 Mode 0 3 91 intel 82054 MODE 1 HARDWARE RETRIGGERABLE ONE SHOT OUT will be initially high OUT will go low on the CLK pulse following a trigger to begin the one shot pulse and will remain low until the Counter reaches zero OUT will then go high and remain high until the CLK pulse after the next trigger After writing the Control Word and initial count the Counter is armed A trigger results in loading the Counter and setting OUT low
109. ne makes a call to DOS function X then function X is essentially being called while it is already active Such a reentrancy attempt spells disaster because DOS functions are not written to support it This is a complex concept and you do not need to understand it Just make sure that you do not call any DOS functions from within your ISR The one wrinkle is that unfortunately it is not 4 16 obvious which library routines included with your compiler use DOS functions rule of thumb is that routines which write to the screen or check the status of or read the keyboard and any disk I O routines use DOS and should be avoided in your ISR The same problem of reentrancy exists for many floating point emulators as well meaning you may have to avoid floating point real math in your ISR Note that the problem of reentrancy exists no matter what programming language you are using Even if you are writing your ISR in assembly language DOS and many floating point emulators are not reentrant Of course there are ways around this problem such as those which involve checking to see if any DOS functions are currently active when your ISR 15 called but such solutions are well beyond the scope of this discussion The second major concern when writing your ISR is to make it as short as possible in terms of execution time Spending long periods of time in your ISR may mean that other important interrupts are being ignored Also if you spend too
110. nter 1 10 Counter 2 Read Load 11 read back setting Counter Mode Select 000 Mode 0 event count 001 Mode 1 programmable 1 shot 00 latching operation 010 Mode 2 rate generator 01 read load LSB only 011 Mode 3 square wave rate generator 10 MSB only 100 Mode 4 software triggered strobe 11 read load LSB then MSB 101 Mode 5 hardware triggered strobe Programming the 2700 This section gives you some general information about programming and the AD2700 and ADA2700 boards and then walks you through the major 2700 programming functions These descriptions will help you as you use the example programs included with the board and the programming flow diagrams at the end of this chapter All of the program descriptions in this section use decimal values unless otherwise specified The 2700 is programmed by writing to and reading from the correct 1 port locations on the board These ports were defined in the previous section Because the 2700 is bus compatible reading the A D converter data and writing the D A converter data is done in a 16 bit word format All other operations are done in an 8 bit word format High level languages such as Pascal C and C make it very easy to read write these ports The table below shows you how to read from and write to I O ports in Turbo C and Turbo Pascal Write 16 Bits Data inportb Address outportb Address Data Data inpo
111. o use the pacer clock for continuous A D conversions you must program the clock rate To find the value you must load into the clock to produce the desired rate you first have to calculate the value of Divider 1 Timer Counter 0 and Divider 2 Timer Counter 1 shown in the diagram The formulas for making this calculation are as follows Pacer clock frequency Clock Source Frequency Divider 1 x Divider 2 Divider 1 x Divider 2 Clock Source Frequency Pacer Clock Frequency To set the pacer clock frequency at 100 kHz using the on board 8 2 clock source this equation becomes Divider 1 x Divider 2 8 MHz 100 kHz gt 80 8 MHz 100 kHz After you determine the value of Divider 1 x Divider 2 you then divide the result by the least common denomi nator The least common denominator is the value that is loaded into Divider 1 and the result of the division the quotient is loaded into Divider 2 In our example above the least common denominator is 2 so Divider 1 equals 2 and Divider 2 equals 80 2 or 40 The table below lists some common pacer clock frequencies and the counter settings using the on board 8 MHz clock source After you calculate the decimal value of each divider you can convert the result to a hex value if it is easier for you when loading the count into the 16 bit counter To set up the pacer clock on the 2700 follow these steps 1 Select a clock source the 8 MHz on board clock or an external clock source 2 Pr
112. oard 2700 1 0 CONNECTOR P2 P12 us Es ER e emos f PING Fig 1 16 Port Butter Pull up Pull down Resistors on Digital I O Lines The 8255 programmable peripheral interface provides 24 TTL CMOS compatible digital I O lines which can be interfaced with external devices These lines are divided into four groups eight Port A lines eight Port B lines four Port C Lower lines and four Port C Upper lines You can install and connect pull up or pull down resistors for any or all of these four groups of lines You may want to pull lines up for connection to switches This will pull the line high when the switch is disconnected Or you may want to pull lines down for connection to relays which control turning motors on and off These motors tum on when the digital lines controlling them are high The Port A and Port B lines of the 8255 automatically power up as inputs which can float high during the few moments before the board is first initialized This can cause the external devices connected to these lines to operate erratically By pulling these lines down when the data acquisition system is first turned on the motors will not switch on before the 8255 is initialized To use the pull up pull down feature you must first install 10 kilohm resistor packs in any all of the four locations around the 20 pin P12 connector and near the bottom of the
113. oblems nn an 4 23 son ri Re n 4 23 4 24 Digital et a LAG 4 25 Example Programs and Flow Diagrams 0 4 26 C and Pascal Orden 4 26 A uu CA Eme du E E can ser 4 27 Single Convert Flow Diagram Figure 4 4 4 27 Flow Diagram Figure 4 5 ua hen ana 4 28 Interrupts Flow Diagram Figure 4 6 neseser tente ttt ttt 4 29 D A Conversion Flow Diagram ADA2700 Only Figure 4 1 4 30 CHAPTER 5 1 188 5 1 A ei ee OA 5 3 A O A 5 4 5 4 II A 7 5 5 Bipolar Range Adjustments 5 to 5 Volts eese ttt ttt 5 5 Bipolar Range Adjustments 10 to 10 Volts 5 6 D A Calibration ADA2700 A A 5 6 APPENDIX A AD2700 ADA2700 SPECIFICATIONS S APPENDIX B P2 AND P12 CONNECTOR PIN B 1 APPENDIX C COMPONENT Q C 1 APPENDIX D CONFIGURING THE 2700 FOR SIGNAL MATH APPENDIX CONFIGURING THE 2700 FOR ATLANTIS E 1 APPENDIX Bere WARRANTY susanne F 1 iii LIST ILLUSTRATIONS 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 10 1 11 1 12 1 13 1 14 1 15 1 16 1 17 1 18 1 19 1 20 2 1 2 2 2 3 2 4 3 1 3 2 4 1 4 2 4 3 4 4 4 5 4 6 4 7 5 1 Board Layout S
114. of this word is set to 1 a write programs the PPI configuration Bit 6 must always be set to 0 Mode 2 operation is not supported by the 2700 Mode Set Flag Port C Lower 1 active 0 output Mode Select 1 input 00 mode 0 01 mode 1 Port B 2 0 output 1 input Port A 0 output Mode Select 1 input mode 0 mode 1 Port Upper L E 85 1 0 output 1 Group A E er 4 6 The table below shows the control words for the 16 possible Mode 0 Port I O combinations 8255 Port I O Flow Direction and Control Words Mode 0 Group B Control Word Port C Port C Port A Upper Port B Lower Binary 7 METAN 18000088 1 18 opa ma 150901 ou 1009109 owe 10010011 147 10011000 10011001 e alo 5 10011010 54 10011011 155 Set Reset Bit Set Reset Function Bit 0 set bit to O 0 active Bit Select 1 set bit to 1 000 PCO 001 PC1 010 PC2 011 3 100 PC4 101 5 110 PC6 111 PC7 4 7 For example if you want to set Port C bit 0 to 1 you would set up the control word so that bit 7 is 0 bits 1 2 and 3 are 0 this selects PCO and bit 0 is 1 this sets PCO to 1 The control word is
115. ogram Timer Counter O for Mode 2 operation 3 Program Timer Counter 1 for Mode 2 operation 4 Load Divider 1 LSB 5 Load Divider 1 MSB 6 Load Divider 2 LSB 7 Load Divider 2 MSB The pacer clock starts running as soon as the last divider is loaded A D conversions can be started and stopped by enabling and disabling the external trigger Timer Counter 1 Divider 2 Timer Counter 0 Divider 1 8 MHz Pacer Clock Fig 4 2 Pacer Clock Block Diagram Dee eme Pacer Clock decimal hex decimal hex sone 06 69 059 19 4 14 Interrupts What Is an Interrupt An interrupt is an event that causes the processor in your computer to temporarily halt its current process and execute another routine Upon completion of the new routine control is retumed to the original routine at the point where its execution was interrupted Interrupts are very handy for dealing with asynchronous events events that occur at less than regular intervals Keyboard activity is a good example your computer cannot predict when you might press a key and it would be a waste of processor time for it to do nothing while waiting for a keystroke to occur Thus the interrupt scheme is used and the processor proceeds with other tasks Then when a keystroke does occur the keyboard interrupts the processor and the processor gets the keyboard data places it in memory and
116. ogrammed as inputs including and STB lines associated with Port C are not affected by a Set Reset Port C Bit command Writing to the corresponding Port C bit positions of the ACK and STB lines with the Set Reset Port C Bit command will affect the Group A and Group B interrupt enable flags as illus trated in Figure 18 Current Drive Capability Any output on Port A B or C can sink or source 2 5 mA This feature allows the 82C55A to directly drive Darlington type drivers and high voltage displays that require such sink or source current 3 139 intel 82C55A Reading Port C Status INPUT CONFIGURATION D De 05 Ds Dz D Do In Mode 0 Port C transfers data to or from the pe 0 INTEg IBFg INTA ripheral device When the 82 55 is programmed to GFA LINTEA PINTA INTR function in Modes 1 or 2 Port C generates or ac E ROUP 8 cepts hand shaking signals with the peripheral de ar vice Reading the contents of Port allows the pro OUTPUT CONFIGURATIONS grammer to test or verify the status of each pe D De 05 D D3 Do Do ripheral device and change the program flow ac 08F wrea vo vo wrra wres OBFs nTg het 00 INTR AE ESPN GROUP A GROUP There is no special instruction to read the status in formation from Port C A normal read operation of Figure 17a MODE 1 Status Word Format Port C is executed to perform this function De 05
117. onverter gain and offset and the D A X2 multiplier output This chapter tells you how to calibrate the A D converter gain and offset and the D A converter X2 multiplier ADA2700 only All A D and D A ranges are factory calibrated before shipping Any time you suspect inaccurate readings you can check the accuracy of your conversions using the procedure below and make adjustments as necessary Using the 2700DIAG diagnostics program is a convenient way to monitor conversions while you calibrate the board Calibration is done with the board installed in your system You can access the trimpots at the edge of the board Power up the system and let the board circuitry stabilize for 15 minutes before you start calibrating Required Equipment The following equipment is required for calibration Precision Voltage Source 10 to 10 volts Digital Voltmeter 5 1 2 digits Small Screwdriver for trimpot adjustment While not required the 2700DIAG diagnostics program included with example software is helpful when performing calibrations Figure 5 1 shows the board layout with the trimpots located along the top edge of the board TR7 at left followed by TR1 through TR6 AD678 un z le 519 jo 0 9900690065909 07247 000000000000 68 OD 6 UD aere 0000000000 000000000 00 0000000 00 0000 000000 00000000007 789000000000 2
118. operly use the timer counter features including the pacer clock Figure 1 7 shows a block diagram of the timer counter circuitry to help you in making these connections The clock source for TCO and TC1 is selected by placing a jumper on OSC or on the two pairs of pins at the top of the header OSC is the on board 8 MHz clock and 1 is an external clock Source you connect through the external I O connector P2 45 Below the CLK1 pins are three pairs of pins labeled CLK2 These pins are used to select the clock source for TC2 OTI connects the output of 101 to the clock pin of TC2 Installing a jumper here cascades all three timer counters a feature necessary when using SIGNAL MATH or ATLANTIS software see Appendixes D and E OSC is the on board 8 MHz clock and EC2 is connected to the same external clock source as P245 The last two pins on this header PCK and ET let you use the pacer clock PCK or an external trigger ET to trigger A D conversions A jumper must be placed on PCK in order to use the pacer clock output from TC1 Or you can place the jumper across ET and connect any external trigger to P2 39 to trigger the A D converter NOTES You must disconnect the pacer clock by removing the PCK jumper and install the jumper of ET whenever you use the external trigger line You must have one jumper installed on one of the two CLK selections and one jumper installed on one of the three CLK2 selections P7
119. or the AD2700 and ADA2700 is shown in Table 4 1 below As shown the 2700 occupies 32 consecutive I O port locations Because of the 16 bit structure of the AT bus every other address location is used Our programming structure uses the 16 bit command for reading the A D converted data and for programming the two ADA2700 D A convert ers All other read write operations are 8 bit operations The base address designated as BA can be selected using DIP switch S1 as described in Chapter 1 Board Settings This switch can be accessed without removing the board from the connector 1 is factory set at 300 hex 768 decimal The following sections describe the register contents of each address used in the I O map Table 4 1 AD2700 ADA2700 I O Map Address Register Description Read Function Decimal Read 12 bit A D converted Read Data Start Convert 0318 word Start A D conversion BA 0 Resets board so that it is Read Status Reset Read status word ready to start A D conversions 2 Program channel amp gain Channel Gain Board Read current channel amp gain external trigger enable IRQ Functions settings enable A 4 Reserved BA 6 D A Converter 1 Program 12 bit DAC1 and ADA2700 Only Not used start conversion 8 D A Converter 2 Program 12 bit DAC2 and ADA2700 Only Not used start conversion BA 10 Reserved BA 12 Reserved BA 14 Program Port A digital output 8255 PPI Port A Read Port A digital input lines lines
120. ortb port address 168 outportb port address v Often assigning a range of bits is a mixture of setting and clearing operations You can set or clear each bit individually or use a faster method of first clearing all the bits in the range then setting only those bits that must be set using the method shown above for setting multiple bits in a port The following example shows how this two step operation is done Example Assign bits 3 4 and 5 in a port to 101 bits 3 and 5 set bit 4 cleared First read in the port and clear bits 3 4 and 5 by ANDing them with 199 Then set bits 3 and 5 by ORing them with 40 and finally write the resulting value back to the port In C this is programmed as v inportb port address 199 40 outportb port address v A final note Don t be intimidated by the binary operators AND and OR and try to use operators for which you have a better intuition For instance if you are tempted to use addition and subtraction to set and clear bits in place of the methods shown above DON T Addition and subtraction may seem logical but they will not work if you try to clear a bit that is already clear or set a bit that is already set For example you might think that to set bit 5 of a port you simply need to read in the port add 32 25 to that value and then write the resulting value back to the port This works fine if bit 5 is not already set But what happens when bit 5 is al
121. pulses after the trigger Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse OUT goes low N CLK Pulses after the initial count is writ ten This allows the Counter to be synchronized by software also 14 15843 CW 14 15843 I 1 4132 231244 10 4 A GATE transition should not occur one clock prior to terminal count Figure 17 Mode 2 intel 82 54 OUT will be high for 1 2 counts and low for N 1 2 counts Writing a new count while counting does not affect the current counting sequence If a trigger is re ceived after writing a new count but before the end of the current period the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count Otherwise the new count will be loaded at the end of the current counting cycle In mode 2 a COUNT of 1 is illegal MODE 3 SQUARE WAVE MODE Mode 3 5 typically used for Baud rate generation Mode 3 is similar to Mode 2 except for the duty cycle of OUT OUT will initially be high When half the ini tial count has expired OUT goes low for the remain der of the count Mode 3 is periodic the sequence above is repeated indefinitely An initial count of N results in a square wave with a period of N CLK cycles
122. re that the IRQ channel you have selected is not used by any other device in your system Valid IRQ selections with SIGNAL MATH are 809 through IRQ12 IRQ14 and IRQ15 IRQ3 through IRQ7 cannot be used Figure D 3 shows you how to configure for IRQ channel 10 P8 OT2 ET EOC DMA IRQ4 IRQS IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 G Fig D 3 Interrupts and Interrupt Channel Jumpers P8 D 4 Running ADAINST After the jumpers and switch are set and the 2700 board is installed in the computer you are ready to configure SIGNAL MATH so that it is compatible with your board s settings This is done by running the ADAINST driver installation program After running the program open ADA2700 EXE from the Open a File menu You will see a screen similar to the screen shown in Figure D 4 below The factory default settings are shown in the illustration Your settings may or may not match the default settings depending on whether you have made changes to these settings before Base Address The board s base address setting is entered in the upper right block as shown in the diagram The factory setting for all Real Time Devices boards is 300 hex 768 decimal The base address can be entered as a decimal or hexadecimal value hex values must be preceded by a dollar sign for example 300 Refer to your board s manual if you need help in determining the correct value to enter EOC IT End of Convert Interrupt In th
123. ready set Bits 0 to 4 will be unaffected and we can t say for sure what happens to bits 6 and 7 but we can say for sure that bit 5 ends up cleared instead of being set A similar problem happens when you use subtraction to clear a bit in place of the method shown above Now that you know how to clear and set bits we are ready to look at the programming steps for the 2700 board functions A D Conversions The following paragraphs walk you through the programming steps for performing A D conversions Detailed information about the conversion modes is presented in this section You can follow these steps on the flow dia grams at the end of this chapter and in our example programs included with the board In this discussion BA refers to the base address Initializing the Board Start your program by resetting the 2700 board This is done by writing to the CLEAR port located at BA 2 The actual value you write to this port is irrelevant After resetting the board following power up take an A D 4 10 reading and throw it away to make sure the converter is initialized and contains unwanted data After the A D reading is taken send a second CLEAR command to BA 2 After clearing the board you may want to initialize the 8255 for Mode 0 or Mode 1 operation and configure your Refer to the 8255 control word description BA 22 presented earlier to determine the value of the word you write for initialization Now the board
124. rigger to the board s trigger in pin note that a jumper should be installed on ET on P7 see Chapter 1 The board is triggered on the positive edge of the pulse and the pulse duration should be at least 100 nanoseconds 2700 CONNECTOR 2 BOARD 1 MASTER PIN 4 3 TRIGGER OUT BOARD 2 SLAVE 1 1 t TRIGGER IN Fig 2 4 Cascading Two Boards for Simultaneous Sampling Connecting the Analog Outputs ADA2700 Only For each of the two D A outputs connect the high side of the device receiving the output to the AOUT channel P2 17 or P2 19 and connect the low side of the device to an ANALOG GND P2 18 or P2 20 Connecting the Timer Counters and Digital VO For all of these connections the high side of an external signal source or destination device is connected to the appropriate signal pin on the P2 I O connector or on P12 and the low side is connected to any DIGITAL GND Running the 2700DIAG Diagnostics Program Now that your board is ready to use you will want to try it out An easy to use menu driven diagnostics program 2700DIAG is included with your example software to help you verify your board s operation You can also use this program to make sure that your current base address setting does not contend with another device 3 HARDWARE DESCRIPTION This chapter describes the features of the 2700 hardware The major circuits
125. riggered by software OUT strobes low N 1 CLK pulses the new count of is written CW 18 158 3 WR our oj FF 15151 151312111 8 FE 16 15842 GATE 101010 pelele LEI o FF CWwals 1 158 2 1 1 1 1 ls 231244 12 Figure 19 Mode 4 MODE 5 HARDWARE TRIGGERED STROBE RETRIGGERABLE OUT will initially be high Counting is triggered by a rising edge of GATE When the initial count has ex pired OUT will go low for one CLK pulse and then go high again After writing the Control Word and initial count the counter will not be loaded until the CLK pulse after a trigger This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low until N 1 CLK pulses after a trigger A trigger results in the Counter being loaded with the initial count on the next CLK pulse The counting sequence is retriggerable OUT will not strobe low for N 1 CLK pulses after any trigger GATE has no effect on OUT If a new count is written during counting the current counting sequence will not be affected If a trigger occurs after the new count is written but before the current count expires the Counter will be loaded with the new count on the next CLK pulse and counting will continue from there 1 15843 1515151518131 11161613 1 158 3 151515
126. rrupt EOD Command After an interrupt service routine is complete the appropriate 8259 interrupt controller must be notified When using IRQO IRQ7 this is done by writing the value 20H to I O port 20H only when using IRQ8 IRQ15 you must write the value 20H to ports 20H and What Exactly Happens When an Interrupt Occurs Understanding the sequence of events when an interrupt is triggered is necessary to properly write software interrupt handlers When an interrupt request line is driven high by a peripheral device such as the 2700 the interrupt controllers check to see if interrupts are enabled for that IRQ and then check to see if other interrupts are active or requested and determine which interrupt has priority The interrupt controllers then interrupt the processor The current code segment CS instruction pointer IP and flags are pushed on the stack for storage and a new CS and IP are loaded from a table that exists in the lowest 1024 bytes of memory This table 15 referred to as the interrupt vector table and each entry is called an interrupt vector Once the new CS and IP are loaded from the interrupt vector table the processor begins executing the code located at CS IP When the interrupt routine is completed the CS and flags that were pushed on the stack when the interrupt occurred are now popped from the stack and execution resumes from the point where it was interrupted Using Interrupts in Your Programs
127. rt Address outport Address Data Turbo Pascal Data Port Address Port Address Data Data PortW Address PortW Address Data In addition to being able to read write the 1 O ports on the 2700 you must be able to perform a variety of operations that you might not normally use in your programming The table below shows you some of the operators discussed in this section with an example of how each is used with Pascal and 0 8 a b c a b c a b amp c MOD DIV AND OR a DIVc b 6 8 Many compilers have functions that can read write either 8 or 16 bits from to port For example Turbo Pascal uses Port for 8 bit port operations and PortW for 16 bits Turbo C uses inportb for an 8 bit read of a port and inport for a 16 bit read Be sure to use the correct function for 8 and 16 bit operations with the 2700 Clearing and Setting Bits in a Port When you clear or set one or more bits in a port you must be careful that you do not change the status of the other bits You can preserve the status of all bits you do not wish to change by proper use of the AND and OR binary operators Using AND and OR single or multiple bits can be easily cleared in one operation To clear a single bit in a port AND the current value of the port with the value b where b 255 2tit Example Clear bit 5 in a port Read in the current value of the port AND it with 223 223 255 25
128. sed for gain adjustment Before making these adjustments make sure that the jumper on P3 is set for 10V and the jumpers on P4 and P15 are set for Use analog input channel 1 and set it for a gain of 1 while calibrating the board Connect your precision voltage source to channel 1 Set the voltage source to 4 99878 volts start a conversion and read the resulting data Adjust trimpot TR3 until it flickers between the values listed in the table below Next set the voltage to 4 99634 volts and repeat the procedure this time adjusting TR2 until the data flickers between the values in the table Data Values for Calibrating Bipolar 10 Volt Range S to 5 volts Offset TR3 Converter Gain TR2 Input Voltage 4 99878V Input Voltage 4 99634V 1000 0000 0000 0111 1111 1110 A D Converted Data 1000 0000 0001 0111 1111 1 Table 5 2 A D Converter Bit Weights Bipolar Twos Complement Ideal Input Voltage millivolts A D Bit Weight 5 to 5 Volts 10 to 10 Voits 1111 1111 1111 244 4 88 1000 0000 0000 10000 00 0100 0000 0000 5000 00 0010 0000 0000 2500 00 0001 0000 0000 1250 00 0000 1000 0000 625 00 0000 0100 0000 312 50 0000 0010 0000 156 25 0000 0001 0000 78 13 0000 0000 1000 39 06 0000 0000 0100 19 53 0000 0000 0010 49 77 0000 0000 0001 44 88 0000 0000 0000 Bipolar Range Adjustments 10 to 10 Volts To adjust the bipolar 20 volt range 10 to 10 volts chan
129. sequence is required Any programming sequence that follows the conventions above is ac ceptable A new initial count may be written to a Counter at any time without affecting the Counters pro grammed Mode in any way Counting will be affected as described in the Mode definitions The new count must follow the programmed count format Counter is programmed to read write two byte counts the following precaution applies A program must not transfer control between writing the first and second byte to another routine which also writes into that same Counter Otherwise the Counter will be loaded with an incorrect count Control Word Counter 2 Control Word Counter 1 Control Word Counter 0 LSB of count Counter 2 MSB of count Counter 2 LSB of count Counter 1 MSB of count Counter 1 LSB of count Counter 0 MSB of count Counter 0 002200229 2 Control Word Counter 1 Control Word Counter 0 LSB of count Counter 1 Control Word Counter 2 LSB of count Counter 0 MSB of count Counter 1 LSB of count Counter 2 MSB of count Counter 0 MSB of count Counter 2 3 a gt In all four examples counters are programmed to read write two byte counts These are only four of many possible programming sequences Figure 8 A Few Possible Programming Sequences Read Operations lt is ofte
130. set up like this X don t care Set Reset Set PCO Function Bit Bit Seject 000 PCO BA 24 8254 Timer Counter 0 Read Write 8 bit operation A read shows the count in the counter and two write operations load the counter with a new 16 bit value in two 8 bit steps LSB followed by MSB The counter must be loaded in two 8 bit steps Counting begins as soon as the count is loaded This counter is cascaded with TC1 to form the 32 bit on board pacer clock BA 26 8254 Timer Counter 1 Read Write 8 bit operation A read shows the count in the counter and two write operations load the counter with a new 16 bit value in two 8 bit steps LSB followed by MSB The counter must be loaded in two 8 bit steps Counting begins as soon as the count is loaded This counter is cascaded with TCO to form the 32 bit on board pacer clock BA 28 8254 Timer Counter 2 Read Write 8 bit operation A read shows the count in the counter and two write operations load the counter with a new 16 bit value in two 8 bit steps LSB followed by MSB The counter must be loaded in two 8 bit steps Counting begins as soon as the count is loaded This counter can be cascaded and 1 or it can be used independently BA 30 8254 Control Word Write Only 8 bit operation Accesses the 8254 control register to directly control the three timer counters 0 1 BCD Counter Select 00 Counter 0 01 Cou
131. so When DMA is started the DMA controller is programmed to place data at a specified offset into a specified page for example start writing at word 512 of page 3 Each time a word of data is written by the controller the offset is automatically incremented so the next word will be placed in the next memory location The problem for you when programming these values is figuring out what the corresponding page and offset are for your buffer Most compilers contain macros or functions that allow you to directly determine the segment and offset of a data Structure but not the page and offset Therefore you must calculate the page number and offset yourself Probably the most intuitive way of doing this is to convert the segment offset address of your buffer to a linear address and then convert that linear address to a page offset address The table at the top of the next page shows functions macros for determining the segment and offset of a buffer 4 19 FP_SEG FP_OFF FP_SEG amp Buffer o FP_OFF amp Buffer Seg Ofs Seg Buffer O Ofs Buffer Once you ve determined the segment and offset multiply the segment by 16 and add the offset to give you the linear address Make sure you store this result as a long integer or DWORD or the results will be meaningless The linear address is a 20 bit value with the upper 4 bits representing the page and the lower 16 bits representing the offset into the page Even though th
132. t Figure 4 Port A B C Bus hold Configuration E 3 127 Es nn intel 82C55A 82C55A OPERATIONAL DESCRIPTION Mode Selection There are three basic modes of operation that can be selected by the system software Mode 0 Basic input output Mode 1 Strobed Input output Mode 2 Bi directional Bus When the reset input goes high all ports will be set to the input mode with all 24 port lines held at a logic one level by the internal bus hold devices see Figure 4 Note After the reset is removed the 82C55A can remain in the input mode with no addi tional initialization required This eliminates the need for pullup or pulldown devices in all CMOS de signs During the execution of the system program any of the other modes may be selected by using a single output instruction This allows single 82C55A to service a variety of peripheral devices with a simple software maintenance routine The modes for Port A and Port B can be separately defined while Port C is divided into two portions as required by the Port A and Port B definitions All of the output registers including the status flip flops will be reset whenever the mode is changed Modes may be combined so that their functional definition can be tailored to almost any 1 structure For instance Group B can be programmed in Mode 0 to monitor simple switch closings or display comp
133. t We recommend that you use either the demand or single transfer mode when transferring data Port D6H Transfer Mode Channel Select Autoinitialization 00 demand 00 4 01 single transfer 22 01 Channel 5 10 Snape 10 Channel 6 11 cascade 11 Channel 7 Offset Counter 0 increment Read Write 1 decrement 01 write 10 read not used with 2700 Programming the DMA Controller To program the DMA controller follow these steps 1 Disable DMA on the channel you are using 2 Write the DMA mode register to choose the DMA parameters 3 Write the page offset bits D1 D16 of your buffer 4 Write the number of samples to transfer 5 Enable DMA on the channel you are using Programming the 2700 for DMA Once you have set up the DMA controller you must program the 2700 for DMA The following steps list this procedure 1 Program the pacer clock if appropriate 2 Set the enable bit BA 4 3 Set the external trigger enable bit in BA 4 4 Monitor for DMA done 4 22 Monitoring for DMA Done There are two ways to monitor for DMA done The easiest is to poll the DMA done bit in the 2700 status register BA 2 While DMA is in progress the bit is clear 0 When DMA is complete the bit is set 1 The second way to check is to use the DMA done signal to generate an interrupt An interrupt can immediately notify your
134. t data output latch buffer and an 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports AandB 14 17 16 19 PORTC PINS 0 3 Lower nibble of Por C PBo 7 20 22 VO PORT B PINS 0 7 An 8 bit data output latch buffer and an 8 24 28 bit data input buffer 29 SYSTEMPOWER 5V Power Supply 07 0 27 34 DATA BUS Bi directional tri state data bus lines connected to system data bus RESET A high on this input clears the control register and all ports are set to the input mode WRITE CONTROL This input is low during CPU write Operations 37 40 41 44 PORT A PINS 4 7 Upper nibble of an 8 bit data output latch buffer and an 8 bit data input latch NC 1 1 2 No Connect 23 34 3 125 0 0 gt lt 8 2 9 3 v gt b intel 82 55 82 55 FUNCTIONAL DESCRIPTION General The 82 55 is a programmable peripheral interface device designed for use in Intel microcomputer sys tems lts function is that of a general purpose 1 component to interface peripheral equipment to the microcomputer system bus The functional configu ration of the 82C55A is programmed by the system software so that norma
135. t the P2 I O connector mounting bracket has an oversized cutout to allow space for running the cable to P12 through the same I O slot If you want to run both cables through the same slot you must make these connections before installing the board 6 Holding the board by its edges orient it so that its card edge bus connectors line up with the expansion slot connectors in the bottom of the selected expansion slot 7 After carefully positioning the board in the expansion slot so that the card edge connectors are resting on the computer s bus connectors gently and evenly press down on the board until it is secured in the slot NOTE Do not force the board into the slot If the board does not slide into place remove it and try again Wiggling the board or exerting too much pressure can result in damage to the board or to the computer 8 After the board is installed secure the slot bracket back into place and put the cover back on your computer The board is now ready to be connected via the external I O connector at the rear panel of your computer Be Sure to observe the keying when connecting your external cable to the I O connector External VO Connections Figure 2 1 shows the 2700 s P2 50 pin connector and P12 on board 20 pin connector pinouts Refer to these diagrams as you make your I O connections 2 3 22229999999899999999999989 ANALOG GND PA7 PAS PAS 2
136. ter has completed its conversion and the data is ready to read The EOC line stays high following a conversion until the data has been read Then the line goes back to low until the next conversion is complete 4 12 Reading the Converted Data A single read operation of port BA 0 provides the 12 bit A D conversion in the right justified format defined in the I O map section at the beginning of this chapter The output code and the resolution of the conversion vary depending on the input voltage range selected Bipolar conversions are in twos complement form and unipolar conversions are straight binary The key digital codes and their input voltage values are given for each range in the three tables which follow A D Bipolar Code Table 45V twos complement 44 998 volts 2 500 volts 00244 volts 1111 1111 1111 5 000 volts A D Bipolar Code Table 10V twos complement Input Voltage 49 995 volts 5 000 volts 00488 volts 10 000 volts 1 LSB 4 88 millivolts A D Unipolar Code Table 0 to 10V straight binary Input Voltage Output Code 9 99756 volts MSB 1111 1111 LSB 5 00000 volts 1000 0000 0000 0 volts 0000 0000 0000 1 LSB 2 44 millivolts 4 13 Programming the Pacer Clock Two of the three 16 bit timer counters in the 8254 programmable interval timer are cascaded to form the on board pacer clock shown in Figure 4 2 When you want t
137. the interrupt mask register and the interrupt vector that you will be using The IMR for IRQO IRQ7 is located at I O port 21H the IMR IRQ8 IRQ15 is located at I O port A1H The interrupt vector you will be using is located in the interrupt vector table which is simply an array of 256 four byte pointers and is located in the first 1024 bytes of memory Segment 0 Offset 0 You can read this value directly but it is a better practice to use DOS function 35H get interrupt vector Most C and Pascal compilers provide a library routine for reading the value of a vector The vectors for IRQO IRQ7 are vectors 8 through 15 where IRQO uses vector 8 uses vector 9 and so on The vectors IRQ8 IRQ15 are vectors 70H through 77H where IRQ8 uses vector 70H IRQ9 uses vector 71H and so on Thus if the 2700 will be using IRQ15 you should save the value of interrupt vector 77H 4 17 Before you install your ISR temporarily mask out the IRQ you will be using This prevents the from requesting an interrupt while you are installing and initializing your ISR To mask the IRQ read in the current IMR at I O port 21H for IRQO IRQ7 or at I O port A1H for IRQ8 IRQ15 and set the bit that corresponds to your IRQ remember setting a bit disables interrupts on that IRQ while clearing a bit enables them The IMR on 8259A is arranged so that bit 0 is for IRQO bit 1 is for IRQ1 and so on The IMR on 8259 is arranged so that bit 0
138. ttle unusual IRQO has the highest priority IRQ is second highest then priority jumps to IRQS IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 and IRQ15 and then following IRQ15 it jumps back to IRQ3 IRQ4 IRQS IRQ6 and finally the lowest priority IRQ7 This sequence makes sense if you consider that the controller that handles IRQ8 IRQ15 is routed through IRQ2 8259 Programmable Interrupt Controllers The chips responsible for handling interrupt requests in the PC are the 8259 Programmable Interrupt Control lers The 8259 that handles IRQO IRQ7 is referred to as 8259A and the 8259 that handles IRQ8 IRQ15 is referred to as 8259B To use interrupts you need to know how to read and set the 8259 interrupt mask registers IMR and how to send the end of interrupt EOT command to the 8259s Interrupt Mask Registers IMR Each bit in the interrupt mask register IMR contains the mask status of an IRQ line in 8259A bit 0 is for IRQO bit 1 is for IRQ1 and so on while in 8259B bit 0 is for IRQ8 bit 1 is for 1809 and so on If a bit is set equal to 1 then the corresponding IRQ is masked and it will not generate an interrupt If a bit is clear equal to 0 then the corresponding IRQ is unmasked and can generate interrupts The IMR for IRQO IRQ7 is programmed through port 21H and the IMR for IRQ8 IRQ15 is programmed through port ATH For ali bits 0 IRQ unmasked enabled 1 masked disabled 4 15 End of Inte
139. turn reduce the noise on your input signal The formula for setting the frequency is given in the diagram Figure 1 19 shows how the Gm circuitry is configured As shown in Figure 1 19 a solder short must be removed from the board to activate the Gm circuitry This short is located on the bottom side of the board under U27 AD712 IC Figure 1 20 shows the location of the solder short 1 13 Remove solder short see Figure 1 20 To calculate Gm Gm TR4 2 81 1 To calculate frequency f 1 2 46 2 TR4 Fig 1 19 Gain Circuitry and Formulas for Calculating Gm and f Remove Solder Short Between These 2 Pads on Bottom Side of Board i 00000000 00000000 3 0000000 00009 55 000000000000 Q 3 3 000000000000 96 a o C oD 828 0000000000 0000000000 8660660000 965066000006 58 0000000 y cC 00000000000 na 900000000000 9 25 55 000000 B on oo o fe 1 00000000 9000000000 ome 20000000000009 0000000000 gt 4 Rea Tene Deuce ins State Coinga Ps 18094 USA 00000000083 Fig 1 20 Diagram for Removal of Solder Short 1 14 2 E BOARD INSTALLATION The 2700 board
140. uded VIEWDAT program DMASTRM Demonstrates how to use DMA for disk streaming Very high continuous acquisition rates can be obtained 4 26 Flow Diagrams The following paragraphs provide descriptions and flow diagrams for some of the 270078 A D and D A conver sion functions These diagrams will help you to build your own custom applications programs Single Convert Flow Diagram Figure 4 4 This flow diagram shows you the steps for taking a single sample on a selected channel A sample is taken each time you send the Start Convert command All of the samples will be taken on the same channel and at the same gain until you change the value in port BA 4 Changing this value before each Start Convert command is issued lets you take the next reading from a different channel at a different gain Clear Registers Reset Select Channel amp Gain Start Conversion End of Convert 1 Change Channel or Gain Read 12 bit A D Data Stop Program Fig 4 4 Single Conversion Flow Diagram 4 27 DMA Flow Diagram Figure 4 5 This flow diagram shows you how to take samples and transfer the data directly into the computer s memory You can use DMA channel 5 6 or 7 to transfer data to the computer s memory The pacer clock can be used to set the sampling interval Clear Registers Reset Program 8254 TCO amp TC1 for desired transfer rates Select Channel amp Gai
141. unter is programmed to read write two byte counts the following precaution applies A program must not transfer control between reading the first and second byte to another routine which also reads from that same Counter Otherwise an incorrect count will be read READ BACK COMMAND The third method uses the Read Back command This command allows the user to check the count value programmed Mode and current state of the OUT pin and Null Count flag of the selected coun ter s The command is written into the Control Word Reg ister and has the format shown in Figure 10 The 3 89 command applies to the counters selected by set ting their corresponding bits D3 D2 D1 1 41 11 65 0 D Ds Ds D4 52 Dy Do 1 COUNT STATUS 2 1 cur o o Ds O Latch count of selected counter s D4 0 Latch status of selected counter s 03 1 Select counter 2 D2 1 Select counter 1 D4 1 Select counter 0 Reserved for future expansion must be 0 Figure 10 Read Back Command Format The read back command may be used to latch mutti ple counter output latches OL by setting the COUNT bit D5 0 and selecting the desired coun ter s This single command is functionally equiva lent to several counter latch commands one for each counter latched Each counter s latched count is held until it is read or the counter is repro grammed That counter is automatically unlatched when read but
142. upt the CPU for input or output oper ations Output Operations OBF Output Buffer Full The OBF output will go low to indicate that the CPU has written data out to port A Acknowledge A low on this input enables the tri state output buffer of Port A to send out the data Otherwise the output buffer will be in the high impedance state INTE 1 The INTE Flip Flop Associated with Controlled by bit set reset of 6 Input Operations STB Strobe Input A low on this input loads data into the input latch IBF Input Buffer Full F F A high on this output indicates that data has been loaded into the input latch INTE 2 The INTE Flip Flop Associated with IBF Controlled by bit set reset of 3 136 intel 82 55 CONTROL WORD O Dg 0 D D 0 D 0 PE DDD Tela 8 1 INPUT 0 OUTPUT PORT 8 1 INPUT 0 OUTPUT 231256 18 Figure 13 MODE Control Word 231256 19 Figure 14 MODE 2 ae PERIPHERAL Bus 231256 20 Figure 15 MODE 2 Bidirectional NOTE Any sequence where WR 1 occurs before and STB occurs before RD is permissible INTR IBF MASK e STE RD OBF e MASK e WR anne ne 3 137 inter 82 55 MODE 2 AND MODE 0 INPUT MODE 2 AND MODE 0 OUTPUT CONTROL WORD CONTROL WORD D D 0 D 0 D 0 D D 0 0 D 0 0 D 0 oo
143. uta tional results Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt driven basis IEC FC PCQ PP A vo vo CONTROL CONTRO PA UO A vo BIDIRECTIONAL Pa PA CONTROL 231256 5 Figure 5 Basic Mode Definitions and Bus Interface CONTROL WORD BOBBBEBE GROUP 8 PORT LOWER 1 INPUT 0 PORT 1 INPUT 0 OUTPUT MODE SELECTION 0 MODE 16 MODE 1 PORT C UPPEA 1 INPUT 0 OUTPUT MODE SELECTION 00 MODE 0 1X MODE 2 MODE SET FLAG 1 ACTIVE 231256 6 Figure 6 Mode Definition Format The mode definitions and possible mode combina tions may seem confusing at first but after a cursory review of the complete device operation a simple logical 1 approach will surface The design of the 82 55 has taken into account things such as effi cient PC board layout control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic Such design represents the maximum use of the available pins Single Bit Set Reset Feature Any of the eight bits of Port C can be Set or Reset using a single OUTput instruction This feature re duces software requirements in Control based appli cations When Port C is being used as status control for Port A or B these bits can be set or reset by us
144. y installing resistor packs at the four locations and soldering jump ers in the desired locations in the associated pads you can config ure your digital I O lines to be pulled up or pulled down This procedure is explained near the end of this chapter By installing components at R1 R2 TR4 and C46 you can add your own gain multiplier to the software programmable binary gains of 1 2 4 and 8 The gain multiplier circuitry is described at the end of this chapter 1 1 Factory Configured Switch and Jumper Settings Table 1 1 lists the factory settings of the user configurable jumpers and switch on the AD2700 and ADA2700 boards Figure 1 1 on the next page shows the board layout and the locations of the factory set jumpers The following paragraphs explain how to change the factory settings Pay special attention to the setting of S1 the base address switch to avoid address contention when you first use your board in your system Table 1 1 Factory Settings Switch Factory Settings Jumper Function Controlled Jumpers Installed Sets the analog input voltage range Bipolar 5 to 5 volts Sets the analog input voltage polarity must be the same as P15 Sets the DMA request DRQ channel Disabled Sets the DMA acknowledge DACK channel Disabled Sets the clock sources for the 8254 timer counters Jumpers installed on CLK1 OSC P7 TCO TC2 connects TC1 out to A D trigger CLK2 OT1 amp PCK

AD27uD|ADA2700 User`s Manual - RTD Embedded Technologies

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