8XC196MD INDUSTRIAL MOTOR CONTROL MICROCONTROLLER
Contents
1. 2 2 1 1 COMPO AD__DONE TOVF RSV RESERVED MUST WRITE AS 0 THIS BIT RESERVED ON 8XC196MC Figure 4 PTS Select and Service Registers THIS BIT RESERVED ON 8XC196MC Figure 5 Peripheral Interrupt Mask and Status Registers The bit in the INT PEND1 register is set if Waveform Generator event or Compare Module 5 event occurs and the corresponding bit is set For either of these events to cause an interrupt the PI bit in the INT MASK1 register and the corre sponding event bit in the MASK register must be set Similarly the TOVF bit in the INT PEND register is set if Timer 1 or Timer 2 overflow and the corre sponding bit in the register is set For ei ther of these two events to cause an interrupt the bit in the INT register and the corre sponding event bit in the must be set Upon a PI and or a TOVF interrupt it may be neces sary to check if the Compare Module 5 the Wave form Generator Timer 1 or Timer 2 event caused the interrupt The Pl will give this informa tion However it should be noted that reading the PI PEND register will clear the register So the indi vidual bits in the PEND register must be read by loading into another shadow register then checking the shadow2. 5 25 Z 6 ACH6 PMODE 2 41 O P0 7 ACH7 3 N N 2 w P6 4 WG3 Vss P6 2 W62 0 WG1 P6 1 WG1L P6 0 P6 3 we2 0 P1 5 ACH11 T1DIR P1 2 ACH10 T1CLK 6 5 631 P1 5 ACH13 C 1 4 12 C P1 1 ACH9 C P1 0 ACH8 272323 4 Figure 7 80 Lead Shrink EIAJQFP Quad Flat Pack PRELIMINARY intel 8XC196MD PIN DESCRIPTIONS Alphabetically Ordered Symbol Function 13 0 7 1 0 1 5 Analog inputs to the A D converter 7 share the input pins with 0 7 and ACH8 13 share pins with 1 0 5 If the A D is not used the port pins can be used as standard input ports ANGND Reference ground for the A D converter Must be held at nominally the same potential as Vss ALE ADV P5 0 Address Latch Enable or Address Valid output as selected by CCR Both options allow a latch to demultiplex the address data bus on the signal s falling edge When the pin is ADV it goes inactive high at the end of the bus cycle ALE ADV is active only during external memory accesses Can be used as standard I O when not used as ALE ADV BHE gt RH P5 5 Byte High Enable or Write High output as selected by the CCR BHE will go low for external writes to the high byte of the data bus WRH will go low for external writes where an odd byte is
3. register to see what event occurred PRELIMINARY intel 8XC196MD Table 3 Interrupt Sources Vectors and Priorities Interrupt Service PTS Service Interrupt Source Symbol Name Vector Priority Name Vector Priority 5 5 12 2038 12 PTS12 2058H 27 Compare4 COMP4 INT11 2036H 11 PTS11 2056H 26 Capture Compare4 CAPCOMP4 INT10 2034H 10 PTS10 2054H 25 Interrupt and PTS Vectors Port 7 The 8XC196MD has three new interrupt and PTS vectors which are Capture Compare5 Compare 4 and Capture Compare4 Table 3 shows these inter rupt vectors and priorities These are shown as re served vectors in the 8XC196MC User s Manual Frequency Generator The Frequency Generator FG Peripheral which was not available on the 8XC196MC device is avail able on the 8XC196MD device The FG outputs a programmable frequency 50 duty cycle waveform on the FREQOUT pin P7 7 There are two 8 bit reg isters which control the FG peripheral Frequency Generator Control Register at 1FB8h Frequency Generator Period Count Register FG COUNT at 1FBAh The can be read or written This register is loaded with a value which determines the number of counts necessary for toggling the output The fol lowing equation should be used to calculate the __ value 16 FG Frequency FG CON value where F
4. Auto and Slave Mode programming 150 pF AC EPROM PROGRAMMING CHARACTERISTICS SLAVE MODE Symbol Parameter Min Max Units TSHLL Reset High to First PALE Low 1100 Tosc TiLLH PALE Pulse Width 50 Tosc TAVLL Address Setup Time 0 Tosc TLLAX Address Hold Time 100 Tosc Low Word Dump Valid 50 Tosc Word Dump Data Hold 50 Tosc TpvPL Data Setup Time 0 Tosc TPLDX Data Hold Time 400 Tosc PROG Pulse Width 50 Tosc TPHLL PROG High to Next PALE Low 220 Tosc TLHPL PALE High to PROG Low 220 Tosc TPHPL PROG High to Next PROG Low 220 Tosc TPHIL PROG High to AINC Low 0 Tosc AINC Pulse Width 240 Tosc TiL vH PVER Hold after AINC Low 50 Tosc AINC Low to PROG Low 170 Tosc TPHVL PROG High to PVER Valid 220 Tosc NOTE 1 This specification is for the Word Dump Mode For programming pulses use the Modified Quick Pulse Algorithm 22 PRELIMINARY intel 8XC196MD DC EPROM PROGRAMMING CHARACTERISTICS Symbol Parameter Min Max Units Ipp Vpp Supply Current When Programming 100 mA NOTE Do not apply Vpp until Voc is stable and within specifications and the oscil damaged SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE ator clock has stabilized or the device may be RESET TAVLL PORTS 3 4 ADDR COMMAND TSHLL TLLAX PALE PROG PVER NOTE P3 0 must be high 1 DATA TLH
5. Burn in 272323 2 EXAMPLE N87C196MD is 84 Lead PLCC OTPROM 16 MHz For complete package dimensional data refer to the Intel Packaging Handbook Order Number 240800 NOTE EPROMs are available as One Time Programmable OTPROM only Figure 2 The 8XC196MD Family Nomenclature Table 1 Thermal Characteristics Package Type ja 35 C W 13 C W QFP 56 C W 12 C W All thermal impedance data is approximate for static air conditions at 1W of power dissipation Values will change depending on operation conditions and application See the Intel Packaging Handbook order number 240800 for a description of Intel s thermal impedance test methodology PRELIMINARY 8XC196MD Table 2 8XC196MD Memory Map Description Address External Memory or 1 0 OFFFFH 06000H Internal ROM EPROM or External 5FFFH Memory Determined by EA 2080H Reserved Must contain FFH 207FH Note 5 205EH PTS Vectors 205DH 2040H Upper Interrupt Vectors 203FH 2030H ROM EPROM Security Key 202FH 2020H Reserved Must contain FFH 201FH Note 5 201CH Reserved Must Contain 20H 201BH Note 5 CCB1 201AH Reserved Must Contain 20H 2019H Note 5 CCBO 2018H Reserved Must contain FFH 2017H Note 5 2014H Lower Interrupt Vectors 2013H 2000H SFR s 1FFFH 1F00H External Memory 1EFFH 0200H 488 Bytes Register RAM Note 1 01 001
6. ON CHIP 10 BIT 16 ND CPU CONVERTER INTERRUPT e 408 AU K CONTROLLER MEMORY PORTS ie ee BITE CONTROLLER REGISTER CONTROL FILE I QUEUE SIGNALS MICROCODE 2 SIH 24BYTES 2 PERIPHERAL CPUSFR s ENGINE TRANSACTION WATCH SERVER DOG LL LN PORT 3 ADo 7 AT TIMER s MUX PORT 4 16 AD8 15 PWM 0 TIMER PROCESSOR FREQUENCY ae PWM 1 TIMER2 ARRAY GENERATOR GENERATOR PORT 0 1 V ir ijs EXTINT JL A D AND PORT 0 1 PORT 2 EPA PORT 7 AND EPA PORT 6 14 ANALOG INPUTS 4 CAPTURE COMPARE 2 CAPTURE COMPARE WAVEFORM 2 DIGITAL ONLY INPUTS 4 COMPARE ONLY 2 COMPARE ONLY GENERATOR FREQUENCY GENERATOR 272323 1 Connections between the standard 1 ports and the bus are not shown Figure 1 87C196MD Block Diagram PRELIMINARY intel PROCESS INFORMATION This device is manufactured on 29 5 a CHMOS 11 process Additional process and reliability infor mation is available in Intel s Components Quality and Reliability Handbook Order Number 210997 L Device Speed No Mark 16 MHz MC Product Family CHMOS Technology Program Memory Options 7 Note 1 3 ROM Package Type Options N 84 lead PLCC S 80 lead QFP Temperature and Burn in Options No Mark 409 to 859C Ambient with Intel Standard
7. being written BHE WRH is activated only during external memory writes BUSWIDTH P5 7 Input for bus width selection If CCR bits 1 and 2 1 this pin dynamically controls the bus width of the bus cycle in progress If BUSWIDTH is low an 8 bit cycle occurs If it is high a 16 bit cycle occurs This pin can be used as standard I O when not used as BUSWIDTH 5 2 0 2 3 P7 0 P7 1 EPA Capture Compare pins 3 share the pins with 2 0 2 3 4 5 share the pins with P7 0 P7 1 If not used for the EPA they can be configured as standard 1 pins CLKOUT Output of the internal clock generator The frequency is 1 2 of the oscillator frequency It has a 50 duty cycle 5 2 4 2 7 7 2 7 3 The EPA Compare pins COMPAREO 3 share the pins with P2 4 P2 7 COMPARE4 5 share the pins with P7 2 P7 3 If not used for the EPA they can be configured as standard 1 pins EA External Access enable pin EA 0 causes all memory accesses to be external to the chip EA 1 causes memory accesses from location 2000H to to be from the on chip OTPROM ROM EA 12 5V causes execution to begin in the programming mode EA is latched at reset EXTINT A programmable input on this pin causes a maskable interrupt vector through memory location 203CH The input may be selected to be a positive ne
8. diagram be low shows the registers Notice that the COMPS bit is a reserved bit on the 8 196 The 8XC196MC Users Manual should be referenced for details about the Waveform Generator Compare Modules and Timers 1FBEH and PEND 1FBCH Read Only 7 6 5 4 3 2 1 0 RSV 5 RSV WG RSV TF2 RSV TFA RSV RESERVED BIT MUST WRITE AS 0 READ AS 1 INT 5 1 0031H and INT 1 0012H 7 6 5 4 3 2 1 0 RSV EXTINT RSV RESERVED BIT MUST WRITE AS 0 THIS BIT RESERVED ON 8XC196MC CAPCOMS COMP4 CAPCOM4 COMP3 Figure 3 Interrupt Mask and Status Registers PTSSRV and PTSSEL Register Similarly there are differences between 8XC196MC and 8XC196MD PTS registers The 8XC196MD PTS registers are shown below Notice the 5 COMPA and CAPCOMA bits are reserved bits on the 8XC196MC The PI bit in the PTSSRV will be set when a Waveform Generator or Compare Module 5 end of PTS interrupt occurs and the corresponding bit in the Pl MASK register is set The PI PTS vec tor can be used when the PI bit in the PTSSEL regis ter is set The 8XC196MC User s Manual should be referenced for details about the PTS PTSSEL 0004H and PTSSRV 0006H 15 14 13 12 11 10 9 8 RSV EXTINT PI capcom cours CAPCOM4 COMP3 CAPCOM3 7 6 5 4 3 2 1 0
9. pF AC TESTING INPUT OUTPUT WAVEFORMS 2 0 2 0 gt TEST POINTS 0 8 0 8 0 45 272323 11 AC Testing inputs are driven at 3 5V for a Logic 1 and 0 45V for a Logic 0 Timing measurements are made at 2 0V for a Logic 1 and 0 8V for a Logic 0 18 FLOAT WAVEFORMS Vi gAp 0 1 V Voy 70 1 V TIMING REFERENCE EDAD POINTS 79 1 V Voy 0 1V 272323 12 For Timing Purposes a Port Pin is no Longer Floating when a 100 mV change from Load Voltage Occurs and Begins to Float when 100 mV change from the Loaded Level occurs 15 mA PRELIMINARY intel A TO D CHARACTERISTICS The sample and conversion time of the A D convert er in the 8 bit or 10 bit modes is programmed by loading a byte into the AD TIME Special Function Register This allows optimizing the A D operation for specific applications The AD TIME register is functional for all possible values but the accuracy of the A D converter is only guaranteed for the times specificed in the operating conditions table The value loaded into AD TIME bits 5 6 7 deter mines the sample time Tsam and is calculated us ing the following formula _ TsAM X Fosc 2 8 SAM TsAM Sample time us Fosc Processor frequency MHz SAM Value loaded into TIME bits 5 6 7 SAM must be in the range 1 through 7 The value loaded into AD TIME bits 0 5 deter mines the conve
10. 16 0 MHz NOTES ANGND Vss should nominally be at the same potential 1 Vngr must be within 0 5V of Vcc 2 The value of AD TIME is selected to meet these specifications 10 BIT MODE A D CHARACTERISTICS Over Specified Operating Conditions Parameter Typical 1 Min Max Units Resolution 1024 1024 Levels 10 10 Bits Absolute Error 0 t4 LSBs Full Scale Error 0 25 0 5 LSBs Zero Offset Error 0 25 0 5 LSBs Non Linearity 1 0 52 0 4 LSBs Differential Non Linearity zv LSBs Channel to Channel Matching 0 1 1 0 LSBs Repeatability 0 25 LSBs Temperature Coefficients Offset 0 009 LSB C Full Scale 0 009 LSB C Differential Non Linearity 0 009 LSB C Off Isolation 60 3 Feedthrough 60 dB 2 Vcc Power Supply Rejection 60 dB 2 Input Series Resistance 750 2K 90 Voltage on Analog Input Pin ANGND 0 5 Vngr 0 5 6 Sampling Capacitor 3 pF DC Input Leakage t1 0 3 0 pA NOTES LSB as used here has a value of approximately 5 mV See Embedded Microcontrollers and Processors Handbook for A D glossary of terms DC to 100 KHz NOORONM 20 Multiplexer Break Before Make is guaranteed Resistance from device pin through internal MUX to sample capacitor These values may be exceeded if the pin current is limited to 2 mA Applying voltages beyond these specifications will degrade the accuracy of other channels being converted All conversions performed with proces
11. 2 AD02 0 5 5 1 P3 1 ADO 1L VREF P3 0 AD00 C AGND P1 7 C P0 6 ACH6 PMODE 2 A a a P6 0 Wc1L P1 5 T1DIR ACH 1 1 P1 2 T1CLK ACH10 C P6 4 WG3 0 P6 1 WG1E P1 5 AcH13 E P1 4 ACcH12 E P1 1 AcH9 P1 0 ACcH8 E P0 7 ACH7 5 C 272323 3 NOTE NC means No Connect Do not connect these pins Figure 6 84 Lead PLCC Package PRELIMINARY 7 8XC196MD P5 2 WR WRL E P5 7 BUSW P4 7 AD15 P4 6 AD14 P4 5 AD13 CLKOUT P4 4 AD12 P5 5 BHE WRH C P5 3 RD P5 6 READY 71 P5 1 INST 1 5 4 1EXTINT 1XTAL2 17 6 17 5 1 7 4 71 6 e m N a 1 P6 7 PWM 1 P2 6 COMPARE2 CPVER C P2 5 COMPARE1 PACT 1 P2 4 COMPAREO AINC P7 3 COMPARES P7 2 COMPARE4 2 7 P2 3 CAPCOMP3 onan OO WN P4 3 AD11 7 P2 2 CAPCOMP2 PROG P4 2 AD10 E 10 INTEL 7 P7 1 CAPCOMP5 P4 1 AD09 11 7 P7 0 CAPCOMP4 S8XC196MD 2 2 0 8 12 1 P2 1 CAPCOMP 1 PALE P3 7 AD07 E 15 Tep view looking 71P2 0 CAPCOMPO PVER P3 6 AD06 P3 5 AD05 P3 4 AD04 P3 3 AD03 P3 2 AD02 P3 1 ADO1 P3 0 AD00 m down en C P7 7 FREQOUT component side of 7 P0 0 ACHO PC board P0 1 ACH1 1P0 2 ACH2 P0 5 ACH3 7 P0 4 ACH4 PMODE O 1 P0 5 ACH5 PMODE 1 m wv Oo 1 7 RESET NMI EA K N
12. 2Tosc 2Tosc 27 ADDRESS OUT BUS DATA IN 2Tosc 2Tosc DATA OUT BUS ADDRESS OUT 272323 6 BUSWIDTH TIMINGS CLKOUT ALE MIN BUS ER X Tavey gt BUS 272323 7 PRELIMINARY 17 8XC196MD EXTERNAL CLOCK DRIVE Symbol Parameter Min Max Units 1 Oscillator Frequency 8 16 0 MHz TxLxL Oscillator Period 62 5 125 ns High Time 22 ns Low Time 22 ns TxLxH Rise Time 10 ns TXHXL Fall Time 10 ns EXTERNAL CRYSTAL CONNECTIONS EXTERNAL CLOCK CONNECTIONS EXTERNAL Vss 1 8XC196MD XTAL1 lock dri XTAL2 P Wy 8 196 0 no connect XTAL2 Quartz Crystal 272323 8 272323 9 Required if TTL driver used NOTE Not needed if CMOS driver is used Keep oscillator components close to chip and use short direct traces to XTAL1 XTAL2 and Vss When using crystals C1 20 pF C2 20 pF When using ceramic resonators consult manufacturer for recom mended circuitry EXTERNAL CLOCK DRIVE WAVEFORMS t 272323 10 An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts up This is due to interaction between the amplifier and its feedback capacitance Once the external signal meets the and specifications the capacitance will not exceed 20
13. 8 CPU SFR s Notes 1 3 0017H 0000H NOTES 1 Code executed in locations 0000H to O1FFH will be forced external 2 Reserved memory locations must contain OFFH unless noted 3 Reserved SFR bit locations must contain 0 4 Refer to 8XC196MC for SFR descriptions 5 WARNING Reserved memory locations must not be written or read The contents and or function of these lo cations may change with future revisions of the device Therefore program that relies on one or more of these locations may not function properly 8XC196MD 8XC196MC AND 8XC196MD DIFFERENCES INT_MASK1 INT_PEND1 Registers There are some differences between the 8XC196MC and 8XC196MD INT MASK1 INT PEND1 registers The 8XC196MD interrupt mask and pending registers are shown below No tice that the 5 COMP4 and CAPCOM4 bits are reserved bits on the 8XC196MC The PI bit of the INT PEND1 register will be set when a Waveform Generator or Compare Module 5 event occurs and the corresponding bit in the Pl MASK register is set The PI interrupt vector can be taken when the bit the INT MASK1 register is set The 8XC196MC User s Manual should be refer enced for details about the interrupts intel and PI PEND Registers The MASK PI PEND registers contain the bits for the Compare Module 5 COMP5 Waveform Gen erator WG Timer 1 Overflow TFI and Timer 2 Overflow TF2 mask status flag The
14. G Frequency is from 4 kHz to 1 MHz The FG COUNT is loaded with the reg ister value The FG COUNT register is decrement ed every eighth state time When it reaches 00 the FG COUNT register will send a signal to toggle the output pin and reload the FG COUNT register with the value in the FG CON register FG can only be read not written The FREQOUT pin P7 7 must be configured for a special function to use it for the Frequency Genera tor feature PRELIMINARY Port 7 is an additional bidirectional port that was not available on the 8XC196MC device Port 7 can be used as 1 or some of the pins have special func tions The pins are listed below followed by their special functions Table 4 Port 7 Special Function Pins Pin Special Function P7 0 CAPCOMP4 P7 1 5 7 2 CAPCOMP4 P7 3 5 7 4 7 5 7 6 7 7 FREQOUT The special functions of the pins are selected in the Port 7 SFRs The Port 2 Port section of the 8XC196MC User s Manual can be referenced when setting up the Port 7 SFRs Port 7 SFRs are located in the following locations Table 5 Port 7 Special Function Registers SFR Address P7 MODE 1FD1h P7 DIR 1FD3h P7 REG 1FD5h P7 PIN 1FD7h 8XC196MD Port 1 There are three additional Port 1 input pins 1 5 P1 7 that were not available on the 8XC196MC These
15. PL ADDR COMMAND P7 2723231 13 PRELIMINARY 23 8XC196MD intel SLAVE PROGRAMMING IN WORD DUMP WITH AUTO INCREMENT RESET ADDR ADDR 2 PORTS 374 ADDR COMMAND VER BITS WD DUMP VER BITS WD DUMP TSHLL TPLDv TPHDX PROG TPHPL AINC 272323 14 NOTE P3 0 must be low 0 SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM WITH REPEATED PROG PULSE AND AUTO INCREMENT RESET ADDR ADDR ADDR 2 3 4 PALE PROG VALID PVER VALID FOR P1 272323 15 PRELIMINARY intel 87C196MD DESIGN CONSIDERATIONS When an indirect shift during divide occurs the upper 3 bits of the shift count are not masked completely If the shift count register has the value 32 n where n 1 3 5 or 7 the operand will be shifted 32 times This should have resulted in no shift taking place 8XC196MC to 8XC196MD Design Considerations 8XC196MC and 8XC196MD are pin compatible However there were several pins that were not con nected NC on the 8XC196MC that are pins on PRELIMINARY 8XC196MD the 8XC196MD Port 7 is a bidirectional port added to the 8XC196MD Port 1 has one additional analog or digital input that was connected to Vss on the 8XC196MC Port 1 also has two additional digital in puts See 8XC196MC and 8XC196MD Differences Section of this data sheet DATA SHEET REVISION HISTORY This is th
16. ata Valid Tosc 22 ns TCLDV CLKOUT Low to Input Data Valid Tosc 50 ns TRHDZ End of RD to Input Data Float Tosc ns TRXDX Data Hold after RD Inactive 0 ns NOTES 1 If Max is exceeded additional wait states will occur 2 If wait states are used add 2 Tosc N where N number of wait states 3 Testing performed at 8 MHz However the device is static by design and will typically operate below 1 Hz 4 These timings are included for compatibility with older 90 and BH products They should not be used for newer high speed designs 14 PRELIMINARY intel AC ELECTRICAL CHARACTERISTICS Continued Test Conditions Capacitive load on all pins 100 pF Rise and fall times 10 ns Fosc 16 MHz The 87C196MD will meet the following timing specifications 8XC196MD Symbol Parameter Min Max Units Notes XTAL1 to CLKOUT High Low 30 110 ns CLKOUT Cycle Time 2 Tosc ns TCHCL CLKOUT High Period Tosc 10 Tosc 15 ns CLKOUT Falling Edge ALE Rising 5 15 ns TiLCH ALE Falling Edge to CLKOUT Rising 20 15 ns TLHLH ALE Cycle Time 4Tosc ns 3 TLHLL ALE High Period 10 Tosc 10 ns TAVLL Address Setup to ALE Falling Edge Tosc 15 ns TLLAX Address Hold after ALE Falling Tosc 40 ns TLLAL ALE Falling Edge to RD Falling Tosc 30 ns TRLCL RD Low to CLKOUT Falling E
17. de PRELIMINARY 13 8XC196MD intel Each symbol is two pairs of letters prefixed by T for time The characters in a pair indicate a signal and its condition respectively Symbols represent the time between the two signal condition points EXPLANATION OF AC SYMBOLS Conditions Signals H High A Address L ALE ADV L Low B BHE BR BREQ V Valid CLKOUT R RD X No Longer Valid D DATA W WR WRH WRL 2 Floating G Buswidth X XTAL1 H HOLD Y READY HA HLDA Q Data Out AC ELECTRICAL CHARACTERISTICS Over Specified Operating Conditions Test Conditions Capacitive load on all pins 100 pF Rise and fall times 10 ns Fosc 16 MHz The system must meet the following specifications to work with the 87C196MD Symbol Parameter Min Max Units Notes Frequency XTAL1 8 16 MHz 3 Tosc 1 FXxTAL 62 5 125 ns TAVYV Address Valid to READY Setup 2Tosc 75 ns TLLYV ALE Low to READY Setup Tosc 70 ns 4 TYLYH Not READY Time No Upper Limit ns READY Hold after CLKOUT Low 0 Tosc 30 ns 1 TLLYX READY Hold after ALE Low Tosc 15 2 Tosc 40 ns 1 TAVGV Address Valid to BUSWIDTH Setup 2Tosc 75 ns ALE Low to BUSWIDTH Setup Tosc 60 ns 4 Buswidth Hold after CLKOUT Low 0 ns TAVDV Address Valid to Input Data Valid 3 55 ns TRLDV RD Active to Input D
18. dge 4 30 ns TRLRH RD Low Period Tosc 5 Tosc 25 ns 3 TRHLH RD Rising Edge to ALE Rising Edge Tosc Tosc 25 ns 1 TRLAZ RD Low to Address Float 5 ns ALE Falling Edge to WR Falling Tosc 10 ns TCLWL CLKOUT Low to WR Falling Edge 0 25 ns TavwH Data Stable to WR Rising Edge Tosc 23 ns TCHWH CLKOUT High to WR Rising Edge 10 15 ns TwWLWH WR Low Period Tosc 30 ns 3 Data Hold after WR Rising Edge Tosc 25 ns TwHLH WR Rising Edge to ALE Rising Edge 10 15 ns 1 TwHBX BHE INST Hold after WR Rising Tosc 10 ns TWHAX AD8 15 Hold after WR Rising Tosc 30 ns 2 TRHBX BHE INST Hold after RD Rising Tosc 10 ns TRHAX AD8 15 Hold after RD Rising Tosc 30 ns 2 NOTES 1 Assuming back to back cycles 2 8 bit bus only 3 If wait states are used add 2 Tosc N where number of wait states PRELIMINARY 15 8XC196MD in SYSTEM BUS TIMINGS XTAL1 CLKOUT ALE Tire RD AVLL TLLax 15 07 TRLAZ BUS ADDRESS OUT DATA IN 2 TWLWH TWHLH gt gt e 5 BUS ADDRESS OUT ADDRESS OUT BHE INST AD8 15 ADDRESS OUT 272323 5 19 PRELIMINARY intel 8XC196MD READY TIMINGS One Wait State Tosc XTAL 1 CLKOUT 2Tosc ALE TLLYX MAX gt ToLyx MAX TLLYX MIN TeLyx MIN READY
19. e initial data sheet 272323 001 It is valid for devices with a B at the end of the topside tracking number Data sheets are changed as new device information becomes available Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devic es 25
20. e multiplexed address data bus which uses strong internal pullups PORT5 8 bit bidirectional I O port 7 of the pins are shared with bus control signals ALE INST WR RD BHE READY BUSWIDTH Can be used as standard 1 0 6 8 bit output port P6 6 and P6 7 output PWM the others are used as the Wave Form Generator outputs Can be used as standard output ports PORT 8 bit bidirectional I O port P7 0 P7 3 can be used as EPA I O pins 4 5 and 4 5 P7 7 can be used as FREQOUT output pin 7 4 7 6 are standard I O pins PWMO PWM1 Programmable duty cycle Programmable frequency Pulse Width Modulator P6 6 P6 7 pins The duty cycle has a resolution of 256 steps and the frequency can vary from 122 Hz to 31 KHz 16 MHz input clock Pins may be configured as standard output if PWM is not used RD P5 3 Read signal output to external memory RD is low only during external memory READY P5 6 reads be used as standard I O when not used as RD Ready input to lengthen external memory cycles If READY 0 the memory controller inserts wait states until the next positive transition of CLKOUT occurs with READY 1 Can be used as standard 1 when not used as READY RESET Reset input to and open drain output from the chip Held low for at least 16 state times to reset the chip Input high for normal operation RESET has an Ohmic internal pullup resistor T1CLK Timer 1 Clock inpu
21. e of approximately 20 mV See Embedded Microcontrollers and Processors Handbook for A D glossary of terms These values are expected for most parts at 25 C but are not tested or guaranteed DC to 100 KHz Multiplexer Break Before Make is guaranteed Resistance from device pin through internal MUX to sample capacitor These values may be exceeded if the pin current is limited to 2 mA Applying voltages beyond these specifications will degrade the accuracy of other channels being converted All conversions performed with processor in IDLE mode PRELIMINARY 21 8XC196MD EPROM SPECIFICATIONS OPERATING CONDITIONS DURING PROGRAMMING Symbol Description Min Max Units Ta Ambient Temperature during Programming 20 30 Vcc Supply Voltage during Programming 4 5 5 5 va VREF Reference Supply Voltage during Programming 4 5 5 5 va Vpp Programming Voltage 12 25 12 75 2 EA Pin Voltage 12 25 12 75 2 Fosc Oscillator Frequency during Auto 6 0 8 0 MHz and Slave Mode Programming Tosc Oscillator Frequency during 6 0 12 0 MHz Run Time Programming NOTES 1 Vcc and Vggr should nominally be at the same voltage during programming 2 Vpp and must never exceed the maximum specification or the device be damaged 3 Vss and ANGND should nominally be at the same potential OV 4 Load capacitance during
22. entary non overlapping PWM pulses with resolutions of 0 125 us edge trigger or 0 250 us centered The 8XC196MD has 16 Kbytes on chip OTPROM ROM and 488 bytes of on chip RAM It is available in two packages PLCC 84 L and EIAJ QFP 80 L Operational characteristics are guaranteed over the temperature range of 40 to 85 C The 87C196MD contains 16 Kbytes on chip OTPROM The 83C196MD contains 16 Kbytes on chip ROM All references to the 80C196MD also refers to the 83C196MD and 87C196MD unless noted OTPROM One Time Programmable Read Only Memory is the same as EPROM but it comes in an unwindowed package and cannot be erased It is user programmable Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1995 April 1994 Order Number 272323 002 8XC196MD In OPTIONAL 16K
23. gative edge or a high low level using WG__PROTECT 1FCEH FREQOUT Programmable frequency output pin The frequency can vary from 4 KHz to 1 MHz 16 MHz input clock It has a 5096 duty cycle Pin may be configured as standard 1 if FREQOUT is not used INST P5 1 INST is high during the instruction fetch from the external memory and throughout the bus cycle It is low otherwise This pin can be configured as standard 1 if not used as INST NMI PORTO A positive transition on this pin causes a non maskable interrupt which vectors to memory location 203EH If not used it should be tied to Vss May be used by Intel Evaluation boards 8 bit high impedance input only port Also used as A D converter inputs PortO pins should not be left floating These pins also used to select programming modes in the OTPROM devices PORT1 8 bit high impedance input only port 1 0 1 5 are also used as A D converter inputs In addition P1 2 and P1 3 can be used as Timer 1 clock input and direction select respectively 1 6 1 7 can be used as input only pins PRELIMINARY 8XC196MD intel PIN DESCRIPTIONS Alphabetically Ordered Continued Symbol Function PORT2 8 bit bidirectional I O port All of the Port2 pins are shared with the EPA I O pins CAPCOMPO 3 and 3 PORTS 8 bit bidirectional I O ports with open drain outputs These pins are shared PORTA with th
24. he Operating Conditions to Vss or ANGND 0 5V to 4 7 0V 1 Power Dissipation 1 5W 2 NOTES 1 This includes Vpp and EA on ROM or CPU only devices 2 Power dissipation is based on package heat transfer lim itations not device power consumption OPERATING CONDITIONS may affect device reliability Symbol Description Min Max Units TA Ambient Temperature Under Bias 40 85 Voc Digital Supply Voltage 4 50 5 50 V VREF Analog Supply Voltage 4 00 5 50 V Fosc Oscillator Frequency 8 16 MHz NOTE ANGND and should be nominally at the same potential Also and Vss4 must be at the same potential DC ELECTRICAL CHARACTERISTICS Over Specified Operating Conditions Symbol Parameter Min Max Units Test Conditions ViL Input Low Voltage 0 5 0 3 V Input High Voltage 0 7 Vcc Voc 0 5 V VoL Output Low Voltage 0 3 V lo 200 uA Port 2 5 and 7 P6 6 P6 7 0 45 V lo 3 2 mA CLKOUT 1 5 V lo 7 mA Vout Output Low Voltage on Port 3 4 1 0 V lo 15 mA VoL2 Output Low Voltage on 0 45 V lo 10 mA Port 6 0 6 5 Output High Voltage Voc 0 3 V 200 pA Voc 0 7 V lou 3 2 mA Voc 1 5 V lou 7 mA Vin Vih Hysteresis Voltage Width 0 2 V Typical RESET js PRELIMINARY intel 8XC196MD DC ELECTRICAL CHARACTERISTICS Over Specified Operati
25. i PRELIMINARY intel 8XC196MD INDUSTRIAL MOTOR CONTROL MICROCONTROLLER 87C196MD 16 Kbytes of On Chip OTPROM 87C196MD ROM 16 Kbytes of On Chip Factory Programmed OTPROM 80C196MD ROMless High Performance CHMOS 16 Bit CPU Programmable Frequency Generator W 16 Kbytes of On Chip OTPROM W Two 16 Bit Timers with Quadrature Factory Programmed OTPROM Counting Input W 488 bytes of On Chip Register RAM 3 Phase Complementary Waveform m Register to Register Architecture Generator 14 Channel 8 10 Bit A D with Sample to 641 0 Lines Hold with Zero Offset Adjustment H W Peripheral Transaction Server PTS with 17 Prioritized Sources W 18 Prioritized Interrupt Sources m Event Processor Array EPA W Flexible 8 16 Bit External Bus 6 High Speed Capture Compare W 1 75 us 16 x 16 Multiply Modules m 3 us 32 16 Divide 6 High Speed Compare Modules m and Power Down Modes Extended Temperature Standard The 8XC196MD is a 16 bit microcontroller designed primarily to control 3 phase AC induction and DC brush less motors The 8XC196MD is based on Intel s MCS 96 16 bit microcontroller architecture and is manufac tured with Intel s CHMOS process The 8XC196MD has a three phase waveform generator specifically designed for use in Inverter motor control applications This peripheral allows for pulse width modulation three phase sine wave generation with minimal CPU intervention It generates 3 complem
26. ng Conditions Continued Symbol Parameter Min Units Test Conditions lu Input Leakage Current on All Input 10 pA 0V lt Vin lt 0 3 in RESET Only Pins li Input Leakage Current on Porto 3 pA OV lt Vin lt VREF and Port1 lit Input Low Current on BD Ports pA Vin 0 3 Note 1 Input Low Current P5 4 mA 0 2 Vcc P2 6 during Reset Note 3 loH Output High Current on P5 4 and mA 0 7 P2 6 during Reset Note 4 lcc Active Mode Current in Reset 70 mA XTAL1 16 MHz Voc Vpp Vngr 5 5V IREF A D Conversion Reference Current 5 mA 30 mA Ipp Power Down Mode Current 50 Voc Vpp 5 5V RESET Pin Pullup Resistor Pin Capacitance Any Pin to Vss 10 pF Frest 1 0 MHz NOTES 1 BD Bidirectional ports include 2 0 2 7 except 2 6 0 7 4 0 4 7 5 0 5 3 5 5 5 7 P7 0 P7 7 2 During normal non transient conditions the following total current limits apply 6 0 6 5 40 mA lou 28 mA P3 90 42 mA 4 90 42 mA P5 CLKOUT loi 35 mA 35 mA 2 6 6 6 7 7 63 mA 63 mA 3 Maximum current that must be sunk by external device to ensure test mode entry 4 Do not exceed minimum current or device may enter test mo
27. orts 3 and 4 contain valid programming address command information input to slave PROG A falling edge in Slave Programming Mode begins programming A rising edge P2 2 ends programming PVER A high signal in Slave Programming Mode and Auto Configuration Byte P2 0 Programming Mode indicates the byte programmed correctly CPVER Cumulative Program Verification Pin is high if all locations since entering a P2 6 programming mode have programmed correctly AINC Auto Increment Active low input enables the auto increment mode Auto P2 4 increment will allow reading or writing of sequential EPROM locations without address transactions across the PBUS for each read or write PRELIMINARY 11 8XC196MD ABSOLUTE MAXIMUM Ambient Temperature Under Bias Storage Temperature Voltage from EA or Vpp to Ves or ANGND Voltage on Any Other Pin RATINGS 2 40 C to 85 C 65 C to 150 C 0 5V to 13 00V intel NOTICE This data sheet contains preliminary infor mation on new products in production The specifica tions are subject to change without notice Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design WARNING Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage These are stress ratings only Operation beyond the Operating Conditions is not recommended and ex tended exposure beyond t
28. pins are listed below followed by their func tion Table 6 New 8XC196MD Port 1 Pins Pin Description P1 5 Digital or Analog Input P1 6 Digital Input P1 7 Digital Input intel P1 5 was Vss on the 8XC196MC device P1 5 and P1 6 are not being used these pins can remain connected to Vss PRELIMINARY In 8XC196MD gt a o x 5 lt gt lt lt o lt a 2 lt lt gt N NNN 2 OH HH x DEER 8 ON Z gt gt Li gt x x n 1411 11 11 111 09 8 7 6 5 4 5 2 1 84 77 76 7 P4 7 AD15 P4 6 AD14 P2 5 COMPARE 1 PACT 2 4 COMPAREO AINC P7 3 COMPARES P4 5 AD13 C P7 2 COMPARE4 cLKouT C 2 7 P4 4 AD12 C 2 5 5 2 2 2 PROG P4 2 AD10 C INTEL 7 1 5 P4 1 AD09 C P7 0 CAPCOMP4 N8XC196MD iem P4 0 AD08 C P2 1 CAPCOMP 1 PALE NC C Top view looking down 2 0 PVER NC EJ on component side P7 7 FREQOUT P3 7 AD07 E of PC board P0 0 ACHO P3 6 AD06 1 ACH1 P3 5 AD05 2 2 P3 4 AD04 C 5 5 P3 3 ADO3 C P0 4 ACH4 PMODE O P3
29. rsion time Tcony and is calculated using the following formula _ Tconv X Foso 3 2B CONV 1 PRELIMINARY 8XC196MD Conversion time us Fosc Processor frequency MHz B 8 for 8 bit conversion B 10 for 10 bit conversion CONV Value loaded into AD__TIME bits 0 5 CONV must be in the range 2 through 31 The converter is ratiometric so absolute accuracy is dependent on the accuracy and stability of VREF Vngr must be close to Vcc since it supplies both the resistor ladder and the analog portion of the convert er and input port pins There is also an AD TEST SFR that allows for conversion on ANGND and Vngr as well as adjusting the zero offset The abso lute error listed is WITHOUT doing any adjustments A D CONVERTER SPECIFICATION The specifications given assume adherence to the operating conditions section of this data sheet Test ing is performed with 5 12V and 16 0 MHz operating frequency After a conversion is started the device is placed in the IDLE mode until the con version is complete 19 8XC196MD 10 BIT MODE A D OPERATING CONDITIONS Symbol Description Min Max Units Ta Ambient Temperature 40 85 Voc Digital Supply Voltage 4 50 5 50 V VREF Analog Supply Voltage 4 00 5 50 va TSAM Sample Time 1 0 ps Conversion Time 10 0 20 0 ps Fosc Oscillator Frequency 8 0
30. sor in IDLE mode These values are expected for most parts at 25 C but are not tested or guaranteed PRELIMINARY intel 8XC196MD 8 BIT MODE A D OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature 40 85 Voc Digital Supply Voltage 4 50 5 50 V VREF Analog Supply Voltage 4 00 5 50 va TSAM Sample Time 1 0 ps Conversion Time 7 0 20 0 ps Fosc Oscillator Frequency 8 0 16 0 MHz NOTES ANGND Vss should nominally be at the same potential 1 Vngr must be within 0 5V of 2 The value of AD TIME is selected to meet these specifications 8 BIT MODE A D CHARACTERISTICS Over the Above Operating Conditions Parameter Typical 1 Min Max Units Resolution 256 256 Level 8 8 Bits Absolute Error 0 t1 LSBs Full Scale Error 0 5 LSBs Zero Offset Error 0 5 LSBs Non Linearity 0 t1 LSBs Differential Non Linearity m 1 LSBs Channel to Channel Matching 0 1 0 LSBs Repeatability 0 25 LSBs Temperature Coefficients Offset 0 003 LSB C Full Scale 0 003 LSB C Differential Non Linearity 0 003 LSB C Off Isolation 60 dB 3 Feedthrough 60 dB 2 Vcc Power Supply Rejection 60 dB 2 Input Series Resistance 750 2K Q4 Voltage on Analog Input Pin Vss 0 5 Vngr 0 5 V6 6 Sampling Capacitor 3 pF DC Input Leakage t1 0 3 0 pA NOTES An LSB as used here has a valu
31. t This pin has two other alternate functions ACH10 and P1 2 P1 2 T1DIR Timer 1 Direction input This pin has two other alternate functions ACH11 and P1 3 P1 3 Vpp The programming voltage is applied to this pin It is also the timing pin for the return from Power Down circuit Connect this pin with a 1 uF capacitor to Vss and a 1 resistor to Vcc If the Power Down feature is not used connect the pin to Vcc WG1 WG3 WG1 WG3 P6 0 P6 5 3 phase output signals and their complements used in motor control applications The pins can also be configured as standard output pins WR WRL P5 2 Write and Write Low output to external memory WR will go low every external write WRL will go low only for external writes to an even byte Can be used as standard I O when not used as WR WRL XTAL1 Input of the oscillator inverter and the internal clock generator This pin should be used when using an external clock source XTAL2 Output of the oscillator inverter PMODE Determines the EPROM programming mode P0 4 7 PACT A low signal in Auto Programming mode indicates that programming is in P2 5 process A high signal indicates programming is complete 19 PRELIMINARY intel PIN DESCRIPTIONS Alphabetically Ordered Continued 8XC196MD Symbol Function PALE A falling edge in Slave Programming Mode and Auto Configuration Byte P2 1 Programming Mode indicates that p
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