QVGA TFT-LCD direct drive using the STM32F10xx FSMC peripheral
Contents
1. ADDSET 1 i DATAST 1 HCLK cycles HCLK cycles ai14721c The DMA channels are used to refresh images on the TFT LCD This offloads the CPU from data transfer tasks The DMA is configured with external SRAM memory as the source and the LCD as the destination DMA transfer complete interrupts are used to toggle the VSYNC and HSYNC synchronisation signals for a new frame transfer A timer TIM3 is used to control the display frame rate When the DMA writes data on the FSMC bus the FSMC generates the TFT enable signal TFT DCLK and data are written to the TFT RGB lines In this way the STM32 manages the complete image display for controller less TFT LCD modules Figure 7 and Figure 7 show the TFT LCD single frame and horizontal line display flow diagram ky Doc ID 17695 Rev 1 9 21 STM32 QVGA TFT LCD drive implementation AN3241 Note 10 21 Figure 7 TFT LCD single frame display flow diagram y Start new frame v Reset TFT LCD module v Set VSYNC signal low for vertical front porch v Write dummy data horizontal line for vertical front porch period v Set VSYNC signal high v Write 240 active data horizontal lines v Write dummy data horizontal lines for vertical back porch period Refer to the TFT LCD datasheet for the vertical front porch and back porch period values Doc ID 17695 Rev 1 A2. yr AN3241 y Application note GVGA TFT LCD direct drive using the STM32F10xx FSMC peripheral Introduction This application note describes a low cost solution for directly driving QVGA TFT LCD using any STM32F10xxx microcontroller which is not eguipped with an on chip LCD controller The powerful STM32F10xxx devices have an embedded FSMC flexible static memory controller which can be used together with the on chip DMA controller to implement a direct drive for TFT LCDs This low cost solution is ideal for applications such as digital photo frames stand alone information displays and static advertisement panels The application note describes how to use the STM32F10xx as LCD controller to drive a QVGA 3 5 TFT panel interfaced with the FSMC The optimization that can be achieved with this solution means that only 1 of CPU load is needed to display static images A firmware demonstration has been developed and tested on a CT05350DW0000T QVGA 3 5 LCD module with a resolution of 320x240 pixels July 2010 Doc ID 17695 Rev 1 1 21 www st com Contents AN3241 Contents 1 STM32 QVGA TFT LCD direct drive 3 1 1 STM32 QVGA TFT LCD direct drive principle anaana 3 2 STM32 QVGA TFT LCD drive implementation 6 2 1 QVGA TFT LCD signal interfacing with STM32F10xx FSMC 6 2 2 Image format and resolution cea 7 2 3 Image ari issu bes ca keet bon i Rak elk Kain pu d
3. CPU load amp frame rate Parameter Value DCLK pixel clock 3 6 MHz Maximum frame rate 19 Hz CPU load 51 The frame rate in Banner display mode is lower due to the SRAM frame buffer dynamic update for the animation The Frame buffer update is made after the display of one complete frame display The frame rate and CPU load measurements were done with high speed optimization using EWARM Toolchain V5 5 The CPU frequency is 72 MHz TFT LCD backlight control In both display modes the TFT backlight is also controlled via a Timer and an ADC channel The timer TIM4 is configured to generate 1 KHz PWM signal output on PB6 and can be used as a PWM enable signal for the TFT backlight controller The TFT LCD backlight control is implemented by varying the duty cycle of the PWM enable signal by rotating the RV1 potentiometer installed on the MB672 STM3210E EVAL evaluation board For more details on the potentiometer hardware please refer to the MB672 STM3210E EVAL evaluation board user manual Doc ID 17695 Rev 1 ky AN3241 Hardware reference design 3 Hardware reference design The STEVAL CCM002V1 evaluation board intended to be used as a daughter board for MB672 STM3210E EVAL Evaluation board The STEVAL CCM002V1 board has a GVGA TFT 3 5 CTO5350DWO000T thin film transistor liquid crystal display The table below provides description of the CT05350DW0000T TFT signals when interfacing with STM32F103Z
4. DFU image file are available for download from the STMicroelectronics website www st com How to configure the QVGA TFT LCD parameters The LCD driver can be customized to support other types of QVGA LCDs The QVGA LCD parameters that can be updated are the front porch back porch period or frame rate frequency as well as the I O pins used for VSYNC and HSYNC TFT power control and backlight These configurable parameters are defined in the Icd_driver h and backlight_control h header files The TFT LCD driver can be easily ported to other hardware Table 4 describes the configurable TFT LCD parameters Table 4 QVGA TFT LCD driver configurable parameters QVGA TFT LCD parameters Description define LCD_FRAME_FRONT_PORCH Frame Front Porch value define LCD_FRAME_BACK_PORCH Frame Back Porch value define LCD_LINE_FRONT_PORCH Line Front Porch value define LCD LINE BACK PORCH Line Back Porch value define SHAM IMAGE1 ADDR Address of first image in frame buffer define SRAM IMAGE2 ADDR Address of second image in frame buffer define FRAME RATE Frame rate frequency value can be 40 Hz or 19 Hz define SLIDESHOW TIME GAP Slide show time value in second define TFT VSYNC GPIO PIN GPIO Pin GPIO Pin 8 define TFT VSYNC GPIO PORT GPIO Port GPIOA define TFT HSYNC GPIO PIN GPIO Pin GPIO Pin 6 define TFT HSYNC GPIO PORT GPIO Port GPIOC define LCD BL GPIO PIN GPIO Pin GPIO Pin 6 define LCD BL
5. GPIO PORT GPIO Port GPIOB Doc ID 17695 Rev 1 ky AN3241 Conclusion 5 Conclusion The versatile capabilities of the STM32 peripherals have been put to good use in this case with the objective of simplifying and lowering the cost of a TFT LCD based application The STM32 with its powerful DMA controller and highly flexible FSMC peripheral combine to offer a cost effective solution for driving a QVGA TFT LCD with a CPU load of only 1 for static image display Doc ID 17695 Rev 1 19 21 Revision history AN3241 6 20 21 Revision history Table 5 Document revision history Date 16 Jul 2010 Revision i Initial release Changes Doc ID 17695 Rev 1 AN3241 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellec
6. ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2010 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com ky Doc ID 17695 Rev 1 21 21
7. TFT LCD direct drive principle Controller less TFT LCD panels have different data line configurations for example 16 bit 18 bit or 24 bit RGB lines A TFT LCD with a 16 bit data interface offers 565 format for each pixel The TFT LCD panel displays are managed as row and column structures Vertical scanning controls row data output and horizontal scanning controls column data output Apart from different data line configurations other data display management signals are common to all TFT LCD panels e The frame synchronization signal VSYNC manages vertical scanning and acts as an image frame update strobe e The line synchronization signal HSYNC manages horizontal line scanning and acts as line display strobe e Synchronization signals along with pixel data clock DCLK perform data output to TFT RGB data lines e The DCLK simply acts as the data valid signal for the TFT The TFT considers data as input only on the DCLK edge DCLK valid edge rising falling is mentioned in the TFT datasheet The horizontal scanning builds one line for display and the vertical scanning builds a complete frame The vertical and horizontal scanning of the image is carried out in a continous manner for multiple frames per second The TFT also needs a TFT enable signal that acts simply as a chip enable signal and TFT reset signal The TFT signals must be synchronized in accordance with the display timing constraints to ensure that the display has
8. 1 STM32 QVGA TFT LCD drive implementation AN3241 2 2 1 6 21 STM32 QVGA TFT LCD drive implementation The STM32 based TFT LCD drive is implemented using the FSMC 16 bit data bus The STM32 has two internal DMA controllers that are used to boost the display performance thereby enabling an increased display frame rate An external SRAM memory is used as frame buffer to allow a continuous image refresh process which can be controlled by a timer Figure 4 STM32 TFT LCD Drive VSYNC HSYNC 3 5 GPIOs C gt TFT LCD STM32F103ZE 320 x RGB x 240 E LE 64 KB SRAM 512 KB Flash FSMC o gt j RGB signal DCLK TFT Enable External SRAM Frame buffer ai18404 QVGA TFT LCD signal interfacing with STM32F10xx FSMC The TFT LCD synchronization signals VSYNC and HSYNC are managed through STM32 GPIOs The FSMC memory interface Write enable signal is used in inverted configuration as a DCLK pixel clock for the TFT and the FSMC chip select signal acts as a TFT enable signal When data is transferred to the FSMC bus the chip select is first asserted low to enable the TFT LCD Then the write enable signal is asserted low to allow 16 bit data transfer to the TFT RGB line on its low level which results in a single pixel display m TFT Enable FSMC chip select pin PG12 VSYNC GPIO pin PA8 HSYNC GPIO pin PC6 DCLK FSMC WE in inverted mode pin PD5 Data Bus FSMC DO D15 SPI1 used for LCD configur
9. 2F10x StdPeriph Driver e incsubfolder contains the Standard Peripheral library header files e src subfolder contains the Standard Peripheral library source files STM3210x LCDDrive Images contains the Image dfu file of the bitmap images Doc ID 17695 Rev 1 ky AN3241 Firmware package 4 1 EWARMv5 contains preconfigured projects for the EWARM toolchain ARM MDK contains preconfigured projects for the RVMDK toolchain HiTOP contains preconfigured projects for the HiTOP toolchain RIDE contains preconfigured projects for the RIDE toolchain TrueSTUDIO contains preconfigured projects for the attolic toolchain e inc subfolder contains the TFT LCD driver and the demonstration heard files lcd driver h contains the prototypes of the basic functions to drive a controller less TFT LCD It includes also the TFT LCD configurable parameters following the TFT specification _ backlight_control h contains the prototypes of the basic functions used to control the TFT backlight main h this file contains prototypes for the main c file stm32f10x it h contains the headers of the interrupt handler stm32f10x conf h the microcontroller library configuration file e src subfolder contains the TFT LCD driver and the demonstration source files Icd_driver c it contains basic routines to drive a controller less QVGA TFT LCD including the FSMC GPIO pins and DMA configurations backlight control
10. 7 0 U 0 PE14 LCD R3 PE15 LCD R4 PD8 LCD R5 4 PD9 LCD R6 PD10 LCD R7 R3 __PC6 6 HSYNC 6 VSYNC 8 DCLK R4 __PA8 40 A13 __3V3 3V3 6 PA4_SPI CS RI PD5 0 R14 GND 8 0 B 49 PA5 SPI CLK U 0 PA7 SPI DATA FSMC INV CLK PG12 LCD ENB TFT CONN54 LED ANODE LED CATHODE LCD SIGNAL CONN ai18410 Doc ID 17695 Rev 1 15 21 Firmware package AN3241 4 Libraries Project 16 21 Firmware package The firmware associated to this application note consists of a demonstration of a direct drive TFT CT05350DW0000T using the STM32F103ZE device The source code example is based on the STM32F10xxx standard peripheral library V3 3 0 The user may build any similar application using the same library and driver and different interfacing firmware hardware The firmware package installation folders are shown in Figure 11 Figure 11 Firmware package architecture Si STM32F10x_LCDDrive cy _htmresc B Libraries 3 Project lt STM32F104_LCDDrive C EWARMv5 33 HITOP C3 images E gt inc 53 MDK ARM RIDE C src 4 TrueSTUDIO B Utilities B STM32_EVAL E Common STM3210E EVAL The Libraries folder contains all the subdirectories and files that make up the core of the STM32F10xxx Standard Peripheral library V3 3 1 CMSIS e CM3iCoreSupport contains the Cortex Ma files e CM3 DeviceSupport ST STM32F 10x contains the STM32F10x CMSIS layers files STM3
11. 7 2 4 STM32 QVGA LCD TFT direct drive flow cc 7 2 4 1 Display modes eu ei er uml a a Bar a aa ee ma 11 25 TFT LCD backlight control eeen 12 3 Hardware reference design eee 13 4 Firmware package inte eneen ereen eee es 16 LIDrarles se eenen ta Gok it d Shame och oe hee ea AE oe eR Ao 16 ie RT IAR ec manden RIE ET YY ee on a ee 16 4 1 Firmware installation ci RR URL RODER YDA GU RD RE RE 17 4 2 How to configure the QVGA TFT LCD parameters 18 5 FCS I ah Yr da HOFF FACE ll ON 19 6 Revision history WR RR ca rd yd EORR UR ee a dd 20 2 21 Doc ID 17695 Rev 1 ky AN3241 STM32 QVGA TFT LCD direct drive 1 1 STM32 QVGA TFT LCD direct drive The STM32 microcontrollers have an embedded Flexible Static Memory Controller FSMC to interface with external memories such as NAND NOR SRAM and PSRAM memories The microcontroller also has a large number of general purpose I O port pins which together with the FSMC can act as a cost effective TFT LCD controller for low end displays e The 16 bit data bus of the FSMC peripheral can easily be interfaced with the 565 RGB format lines of a TFT LCD panel in 565 RGB format 5 bits are for red 6 bits for green and 5 bits for blue e An external memory can be used as the image source as well as a frame buffer for the TFT LCD refresh e The general purpose I O pins can provide the synchronization logic for the LCD STM32 QVGA
12. ET6 Table 3 STM32F103ZET6 signal interface with CT05350DW0000T LCD LCD signal STM32F103ZET6 signal Description LCD Reset GPIO PC 1 Used to reset TFT LCD LCD X1 X2 Y1 Y2 Connected to STMPE811 touchscreen controller device LCD touch screen signals LCD BO LCD B2 Do not connect LCD blue data lines 0 2 LCD B3 LCD B7 FSMC DO D4 LCD blue data lines 3 7 LCD GO LCD G1 Do not connect LCD green data lines 0 1 LCD G2 LCD G7 FSMC D5 D10 LCD green data lines 2 7 LCD RO LCD R2 Do not connect LCD red data lines 0 2 LCD R3 LCD R7 FSMC D11 D15 LCD red data lines 3 7 LCD horizontal synchronization LCD HSYNC GPIO PC6 signal LCD VSYNC GPIO PA8 MM synchronization LCD DCLK FSMC NWE Inverted LCD pixel clock signal LCD SPI CS SPH_CS PA4 LCD SPI chip select signal LCD SPI CLK SPI1_CLK PA5 LCD SPI clock signal LCD SPI DATA SPI1_ MOSI PA7 LCD SPI data signal LCD ENABLE FSMC NE4 LCD chip select signal Please refer to User manual UMO921 for a complete description of the STEVAL CCM002V1 daughter board The daughter board order code is STEVAL CCM002V1 Doc ID 17695 Rev 1 13 21 Har
13. J4 GND 2 PC6 GND 1 2 PC6 PC7 3 4 PC8 PC7 3 4 PC8 PC9 5 6__ PA8 PC9 5 PA8 PA9 1 8 PA10 PA9 T 8 PA10 PAO 9 10 GND PAO 29 GND 12 PAT lt 11 42 PAI PA12 3 14__ PA13 PA12 13 PA13 PA14 PA15 PA14 15 PA15 PC10 7 48_ PC11 PC10 17 PC11 GND 19 20 PC12 GND 20 PC12 PDO LCD B5 21 22 PD1 LCD B6 PDO LCD B5 21 22 PD1 LCD B6 PE2 23 24 PET PE2 23 24 PET PD2 25 26 PD3 PD2 25 26 PD3 PD4 27 28 PD5 PD4 27 28 PD5 PD6 29 30 GND PD6 29 30 GND PD7 31 32 PG9 PD7 31 32 PG9 PG10 33 34 PG11 PG10 34 PG11 PG12 LCD ENB 35 36__PG13 PG12 LCD ENB 35 36 PG13 PG14 37 38_ PG15 PG14 37 38 PG15 GND 39 40_ PB3 GND 39 40_ PB3 PB4 41 42 PB5 PB4 41 42 PB5 PB6 43 44 PB7 PB6 43 44 PB7 PB8 45 46_ PB9 PB8 45 46__PB9 PEO 47 48_ 3V3 O3V3 PEO AL 48 3V3 03V3 D5V 49 50__ GND D5V 49 50 GND PE4 51 52 PES PE4 51 52 PE3 PEG 53 54 PES PE6 53 54__PE5 PC14 55 56__ PC13 PC14 55 56 PC13 PEO 57 5g XPC15 PFO 57 58 PC15 GND 59 60 PFI GND 59 60 PFI PF2 61 62 PF3 PF2 61 62 PES PF4 63 64__PF5 PF4 63 64 PF5 PF6 65 66__PF7 PF6 65 66 PF7 PFS 67 68 PF9 PFS 67 68 PF9 3V30 3V3 69 z0 GND 3V30 3V3 69 z0 GND CON70A CON70A ai18409 14 21 Doc ID 17695 Rev 1 AN3241 Hardware reference design d Figure 10 TFT LCD 54 pin connector J5 2 _ LED CATHODE 4 LED ANODE PC1_LCD_RESET TSC_Y1 TSC X1 TSC_Y2 TSC_X2 PD14_LCD B3 PD15_LCD B4 PDO LCD B5 PD1 LCD B6 PE7 LCD B7 PE8 LCD G2 PE9 LCD G3 PE10 LCD G4 PE11 LCD G5 PE12 LCD G6 PE13 LCD G
14. N3241 STM32 QVGA TFT LCD drive implementation Note 2 4 1 Figure 8 TFT LCD single horizontal line display flow diagram v Start new horizontal line scan Y Set HSYNC signal low for horizontal line front porch period v Write dummy data pixels on TFT LCD RGB lines Y Set HSYNC signal high for active data write Vv Write 320 active data horizontal lines Y Write dummy data pixels for horizontal line front line back porch period Refer to the TFT LCD datasheet for the horizontal front porch and back porch period values Display modes Two display modes are provided and can be selected STM32 slide show display mode In this mode two static images in the SRAM buffers are displayed on the TFT LCD after a fixed time interval The user can configure more than 2 images as well as change the Frame buffer address location In this mode up to 40 frames per second can be displayed Table 1 STM32 slide show display CPU load amp frame rate Parameter Value DCLK pixel clock 3 6 MHz Maximum frame rate 40 Hz CPU load 1 STM32 banner display mode In this mode image buffers in SRAM are dynamically updated from NOR Flash memory to show an image animation For updating the image two DMA channels are used Doc ID 17695 Rev 1 11 21 STM32 QVGA TFT LCD drive implementation AN3241 Note 2 5 12 21 Table 2 STM32 slide show display
15. a continuous visual effect Figure 1 shows the horizontal and vertical scanning signals Doc ID 17695 Rev 1 3 21 STM32 QVGA TFT LCD direct drive AN3241 4 21 Figure 1 QVGA TFT LCD display scanning signals QVGA TFT LCD H G B Pixel 5 6 5 c I o o o E Nu LL T 2 o gt VSYNC scan signal Horizontal scan line 240 HSYNC signal for 1 line scan ai18401 The FSMC bus data width is 16 bit Hence if the TFT LCD panel has 24 bit RGB lines the MSBs of the LCD RGB data lines can be interfaced in 565 format Images must be displayed on the TFT LCD continuously this is easily managed by the STM32 microcontroller Figure 2 shows the TFT synchronization signals waveform Figure 2 Frame synchronization signal waveform Back porch Active data Front porch VcvcLE7 262 lines lygp 18 lt 4 VSYNC l 77 i Vpisp 240 lines i Keg ES ut VFP 4 gt i HSYNC a WU AHRRARIUUL TU LULU Doc ID 17695 Rev 1 ky AN3241 STM32 QVGA TFT LCD direct drive Figure 3 TFT Line synchronization signal waveform Back porch i Active data 1 Front porch N T Hoycie 408 f K EN i turp 20 tupp 68 Hpisp 320 HEP finnr nrnr fnr nnnr dE 11 2 T Pixel data Dummy DO D1 atnan Ipste pars D320 Dummy ai18403 Doc ID 17695 Rev 1 5 2
16. ation Doc ID 17695 Rev 1 ky AN3241 STM32 QVGA TFT LCD drive implementation 2 2 2 3 2 4 Image format and resolution The 16 bit data bus of the STM32 FSMC can drive a controller less 24 bit LCD module With only 16 data lines on the FMSC memory bus the interface is a 565 format RGB The remaining lines of the QVGA TFT LCD are left open The images are loaded in external SRAM memory in 565 format to avoid conversion overhead for the STM32 From a performance perspective converted image availability in memory offers the benefit of fast data transfer to the TFT interface So a faster image refresh rate can be supported e Pixel data size 16 bit 2 bytes e Image memory size for QVGA TFT 320 x 240 x 2 153600 Bytes Image source The 565 format images are programmed in NOR memory In a first step two images are transferred from NOR to external on Board SRAM External SRAM acts as frame refresh buffer for TFT LCD To implement an animated banner display the SRAM frame buffers are updated during run mode with new images from NOR memory This approach is used to maintain the exact working model of the TFT LCD controller The on board NOR memory contains the programmed images which are to be used for display on the LCD SRAM Double buffer management allows the source data to be updated in run mode STM32 QVGA LCD TFT direct drive flow To achieve a static image view on a controllerless TFT the image frame has to
17. be refreshed at a rate of at least 15 fps Vertical and horizontal scanning of one frame are performed as per the TFT LCD module specifications A QVGA LCD module single frame display needs 320x240 pixels of data 240 horizontal lines each of 320 pixels are scanned vertically on the TFT to display one frame Along with data scanning dummy data writes are required for the TFT to reach the required horizontal and vertical front and back porch values These values are available the TFT datasheet Dummy data writes are composed of writing zero data to the TFT RGB lines e DMA1 Channel is used for back porch data transfer e DMA1 Channel2 is used for active data transfer e DMA1 Channel3is used for front porch data transfer The FSMC is configured in asynchronous mode and operates in Mode1 which is the default mode selected when configuring the SRAM memory type Figure 5 and Figure 6 show the FSMC asynchronous read and write transactions in SRAM modei for one 16 bit data pixel Doc ID 17695 Rev 1 7 21 STM32 QVGA TFT LCD drive implementation AN3241 Figure 5 Mode 1 SRAM read accesses Memory transaction A 25 0 D 15 0 ADDSET 1 p a DATAST 1 HCLK cycles HCLK cycles Data sampled Data strobe ai14720c 4 8 21 Doc ID 17695 Rev 1 AN3241 STM32 QVGA TFT LCD drive implementation Figure 6 Mode1 SRAM write accesses Memory transaction A 25 0 NWE D 15 0 data driven by FSMC
18. c contains the basic functions used to control the TFT LCD backlight _ mainc c initializes the TFT LCD Drive demonstration stm32f10x it c contains all the peripheral interrupt service routines used in the LCD driver and provides templates for all exception handlers Utilities STM3210E EVAL contains the STM3210E EVAL board related drivers Firmware installation The firmware associated with this application note is built for the STM3210E EVAL Evaluation board and the STEVAL CCM002V1 daughter board After successful hardware setup and firmware programming a bitmap image starts displaying on the TFT LCD on the STEVAL CCMOO2V 1 evaluation board Banner display mode is selected by default Push the Key button connected to PB3 on the STM3210E EVAL Evaluation board to switch to slide show display mode Demonstration Images 16 bit Bitmap images are copied by the firmware from NOR memory to on board external SRAM during firmware initialization Then the image is refreshed on the TFT LCD from external SRAM only Doc ID 17695 Rev 1 17 21 Firmware package AN3241 4 2 18 21 These images are programmed by default in the NOR memory the MB672 STM3210E EVAL Evaluation board If the images are not available in NOR memory they can be easily programmed in the NOR memory using USB DFU firmware For more details on board and NOR programming refer the UM0549 user manual available on www st com The USB DFU firmware and
19. dware reference design AN3241 Figure 9 STM3210E EVAL board connector for TFT LCD J1 CN6 J2 GND 1 2 PG8 GND 1 2 PG8 PGT 3 4 PG6 PGT 3 4 PG6 PG5 5 6__PG4 PG5 5 6__PG4 PG3 7 8 PG2 PG3 L 8 PG2 PC13 9 10 GND PC13 9 10 GND RESET 11 12 PD13 RESETH 11 12 PD13 PD12 13 14__ PD11 PD12 PD11 PD10 LCD R7 15 16 PD9 LCD R6 PD10 LCD R7 15 16 PD9 LCD R6 PD8 LCD R5 1L 18 ___PB15 PD8 LCD R5 17 18 PB15 D5V 19 20 PB14 D5V 19 20 PB14 PB13 PB12 PB13 21 22 PB12 PB11 TSC SDAZ 23 24 PB10 TSC SCL2 PEI TSC SDAZ 23 24 PB10 TSC SCL PET5 LCD R4 25 26 _PE14 LCD R3 PETS LCD R4 25 26 PE14 LCD R3 PE13 LCD G7 27 28 PE12 LCD G6 PE13 LCD G7 27 28 PE12 LCD G6 PE11 LCD G5 29 30 GND PE11 LCD G5 29 GND PD15 LCD B4 3 32 PD14 LCD B3 PD15 LCD B4 31 32 PDi4 LCD B3_ PE9 LCD G3 33 34 PE10 LCD G4 PE9 LCD 63 33 34 PETO LCD G4 PE7 LCD B7 35 36 PE8 LCD G2 PET LCD B7 35 36 PE8 LCD G2 PG1 37 38 Pot 2 327 38 GND 39 40 PGO GND 39 40 PGO PF14 4 42 PF15 PF14 41 PF15 PF12 43 44 PF13 PF12 43 44 PF13 PB2 45 46 PF11 PB2 45 46 PF11 PB1 A7 48 PB1 A7 49 50 GND 49 GND PBO 51 52__PC5 PBO 51 PC5 PC4 53 54_ PAT SPI DATA PC4 53 54 PAT SPI DATA PA6 55 5g PAR SPI CLK PA6 56 PA5 SPI CLK PA4 SPI CS 57 58__PA3 PA4_SPI CS 57 58 PA3 GND 59 60__ PA2 GND 59 60__ PA2 PA1 61 62 PA1 61 62 PC3 TSC INT 63 64_ PC2 PC3 TSC INT 64 PC2 PCT LCD RESET 65 66 PCO PC1 LCD RESET 65 66__ PCO PF10 67 68 PF10 67 68 avao_ 3V3 69 70 GND 3V3 3V3 69 70 GND CON70A CON70A J3 CNS
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