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RPDL for RX62N Group User`s Manual

1. Configure SDRAM area R_BSC_SDRAM CreateArea PDL_BSC_SDRAM_WIDTH_32 PDL_BSC_SDRAM_8_BIT_SHIFT OxOFFFu RFC 4096 cycles 0x00u REFW 1 cycle 0x00u ARFI 3 cycles 0x02u ARFC 2 times 0x00u PRC 3 cycles 0x02u CL 2 cycles 0x01lu WR 2 cycles 0x00u RP 1 cycle 0x00u RCD 1 cycle 0x00u RAS 1 cycle R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 5 8 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Usage Examples 0x0220u if SDMOD 0x220u Configure the clocks and enable the BLCK output ICLK 96MHz PCLK 48MHz BCLK 12MHz SDCLK 12MHz R_CGC_Set 12E6 96E6 48E6 12E6 PDL_CGC_BCLK_DIV_1 PDL_CGC_SDCLK_ENABLE Perform SDRAM initialization R_BSC_Control PDL_BSC_SDRAM_INITIALIZATION Start Auto Refresh R_BSC_Control PDL_BSC_SDRAM A Enable SDRAM operation R_BSC_Control PDL_BSC_SDRAM_E EN write SDRAM for i 0 i lt 16 1024 1024 4 i 2 sdram_location_32 i OxAAAAAAAAu sdram_location_32 i 1 0x55555555u SELF_REFRESH_SELECT RRR RK KKK KR RK KK KK Entering Self Refresh FOKKER KK KK Disab
2. fect MHz fire 50 48 12 5 12 32 8 f 1 781 kbps to 750 kbps to 195 kbps to 187 5 kpbs to 500 kbps to 125 kbps to PET 25 0 Mbps 24 0 Mbps 6 25 Mbps 6 0 Mbps 16 0 Mbps 4 00 Mbps feck 2 391 kbps to 375 kbps to 97 7 kbps to 93 75 kbps to 250 kbps to 62 5 kbps to 12 5 Mbps 12 0 Mbps 3 13 Mbps 3 0 Mbps 8 00 Mbps 2 00 Mbps feck 4 195 kbps to 187 5 kbps to 48 8 kbps to 46 875 kbps to 125 kbps to 31 3 kbps to 6 25 Mbps 6 0 Mbps 1 56 Mbps 1 5 Mbps 4 00 Mbps 1 00 Mbps fpcik 8 97 7 kbps to 93 75 kbps to 24 4 kbps to 23 4 kbps to 62 5 kbps to 15 6 kbps to 3 13 Mbps 3 0 Mbps 781 kbps 750 kbps 2 00 Mbps 500 kbps fecik 16 48 8 kbps to 46 875 kbps to 12 2 kbps to 11 71 kbps to 31 3 kbps to 7 81 kbps to 1 56 Mbps 1 5 Mbps 391 kbps 375 kbps 1 00 Mbps 250 kbps fecik 32 24 4 kbps to 23 4 kbps to 6 10 kbps to 5 86 kbps to 15 6 kbps to 3 91 kbps to 781 kbps 750 kbps 195 kbps 187 5 kbps 500 kbps 125 kbps feck 64 12 2 kbps to 11 71 kbps to 3 05 kbps to 2 93 kbps to 7 81 kbps to 1 95 kbps to 391 kbps 375 kbps 97 7 kbps 93 75 kbps 250 kbps 62 5 kbps feck 128 6 10 kbps to 5 86 kbps to 1 53 kbps to 1 46 kbps to 3 91 kbps to 977 bps to 195 kbps 187 5 kbps 48 8 kbps 46 875 kbps 125 kbps 31 3 kbps The actual rise and fall times will not be zero Using the limits from the I C specification Rise time rate lt 100 kbps 1000 ns 100 kbps lt rate lt 400 kbps 300 ns 400 kbps lt rate lt 1 Mbps 120 ns F
3. R20UT0084EE0004 Rev 0 04 Aug 25 2010 7tENESAS Page 5 41 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group amp Weaga example ta_storage 5 1 PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA iic_rx_dmac_end_handler 7 Select I C mode at 100kHz 300ns rise time 200ns fall time R_IIC_Create 0 PDL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 0 0 0 0 100E3 300 lt lt 16 200 Enable the DMAC channels R_DMAC_Control PDL_DMAC_2 PDL _DMAC_3 __DMAC_ENABLE L_NO_DATA L_NO_PTR L_NO_PTR L_NO_DATA L_NO_PTR L_NO_PTR L_NO_DATA DG G UO G o Write the data into the EEPROM write_eeprom_data Prepare the next data for the EEPROM R_DMAC_Control PDL_DMAC_3 pP DL_DMAC_SUSPEND PDL_DMAC_ENABLE PDL_DMAC_UPDATE_SOURCE PDL_DMAC_UPDATE_COUNT PDL_DMAC_CL PDL_NO_DATA eprom_data_array_2 PDL_NO_PTR f DL_NO_PTR PDL_NO_PTR DL_NO_DATA Write the data into the EEPROM write_eeprom_data Clear the data storage area for i 0 i lt 20 i data_storage i 0x00 Reset the EEPROM sub address to 0 using polling R_IIC_MasterSend L_TIC_STOP_DISABLI PROM_ADDRESS eprom_data_array_l
4. Modify the operation of channel 3 R_MTU_ControlChannel 3 amp ch3_parameters R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 95 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 fabranyReterence 5 R_MTU_ControlUnit Synopsis Control a Multi function Timer Pulse Unit Prototype bool R_MTU_ControlUnit uint8_t data1 Unit selection R_MTU_ControlUnit_structure ptr A pointer to the structure R_MTU_ControlUnit_structure members uint32_t data2 Control selection uint32_t data3 Control selection uint16_tdata4 Control selection uint32_t data5 Control selection uint8_t data6 Register selection uinti6 _tdata7 Register value uinti6 tdata8 Register value uint16_tdata9 Register value Description 1 4 Modify a timer units registers data1 The unit number n where n 0 to 1 data2 The output control settings to be modified All settings are optional If multiple selections are required use to separate each selection e Output control Select one option for each output PDL_MTU_OUT_P_PHASE_1_ENABLE or For n 0 MTIOC3B PDL_MTU_OUT_P_PHASE_1_DISABLE For n 1 MTIOC9B PDL_MTU_OUT_N_PHASE_1_ENABLE or For n 0 MTIOC3D PDL_MTU_OUT_N_PHASE_1_DISABLE F
5. Return value True if all parameters are valid and exclusive otherwise false Functionality Low Power Consumption control registers References R_LPC_Control Remarks e None Program example RPDL definitions include r_pdl_lpc h RPDL device specific definitions include r_pdl_definitions h void func void Allow a falling edge on IRQO A to cancel deep software standby R_LPC_Create PDL_LPC_CANCEL_IRQO_FALLING PDL_LPC_STANDBY_64 PDL_LPC_DEEP STANDBY_1024 R20UT0084EE0004 Rev 0 04 Aug 25 2010 eeey RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 R_LPC Control Synopsis Select a low power consumption mode Prototype bool R_LPC_Control uint16_t data II Mode selection Description Transition to one of the low power modes data 4 Library Reference Mode selection The default settings are shown in bold e Mode selection PDL_LPC_MODE_SLEEP or PDL_LPC_MODE_SOFTWARE_STANDBY or PDL_LPC_MODE_DEEP_SOFTWARE_STANDBY PDL_LPC_MODE_ALL_MODULE_CLOCK_STOP or Select the mode to be entered e All module clock stop cancellation modification PDL_LPC_TMR_OFF or PDL_LPC_TMR_UNIT_0 or PDL_LPC_TMR_UNIT_1 or PDL_LPC_TMR_BOTH Select whether the TMR units can be used
6. Error flag control PDL_SCI_CLEAR_RECEIVE_ERROR_FLAGS Try to clear the receive error flags Manual SCK control PDL_SCI_GSM_SCK_STOP or Disable or enable the clock output can be used while GSM PDL_SCI_GSM_SCK_START mode is enabled True if all parameters are valid otherwise false SCI R_SCl_Send R_SCl_Receive R_SCl_GetStatus None R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 153 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Apiary E enes Program example RPDL definitions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h void func void Terminate SCI reception on channel 0 R_SCI_Control 0 PDL SCI STOP RX R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 154 RENESAS Under development Preliminary Specification RX62N Group RX621 Group 7 R_SCI_GetStatus Synopsis Prototype Specifications in this preliminary version are subject to change 4 Library Reference Check the status of an SCI channel bool R_SCI_ GetStatus uint8_t data1 uint8_t data2 uint8_t data3 uint16_t data4 uint16_t data5 II Channel selection II Status flags Last byte received II Bytes transmitted II Bytes received Descriptio
7. Description Write to the Backup registers bool R_LPC_WriteBackup uint8_t data1 Data pointer uint8_t data2 Data count Write data into the backup registers data1 The data to be written to the backup area data2 The number of bytes to be written to the backup area Valid from 1 to 32 Return value Functionality References Remarks Program example True if all parameters are valid otherwise false Low Power Consumption control registers R_LPC_ReadBackup RPDL definitions include r_pdl_lpc h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t data_to_save R_PDL_LPC_BACKUP_AREA_ SIZE Write data into the backup registers R_LPC_WriteBackup data_to_save R_PDL_LPC_BACKUP_AREA_ SIZE R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 46 4 Library Reference The definition R_ PDL_LPC_BACKUP_AREA_SIZE specifies the number of bytes that are available Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group A ibrar Reteenes 4 R_LPC_ReadBackup Synopsis Read from the Backup registers Prototype bool R_LPC_ReadBackup uint8_t data1 Data pointer uint8_t data2 Data count
8. PDL_MTU_OUT_P_PHASE_1_HIGH_LOW or For n 0 MTIOC3B PDL_MTU_OUT_P_PHASE_1_LOW_HIGH For n 1 MTIOC9B PDL_MTU_OUT_N_PHASE_1_HIGH_LOW or For n 0 MTIOC3D PDL_MTU_OUT_N_PHASE_1_LOW_HIGH For n 1 MTIOC9D PDL_MTU_OUT_P_PHASE_2_HIGH_LOW or For n 0 MTIOC4A PDL_MTU_OUT_P PHASE 2 LOW_HIGH For n 1 MTIOC10A PDL MTU OUT N PHASE 2 HIGH LOW or PDL_MTU_OUT_N PHASE 2 LOW_HIGH For n 0 MTIOC4C For n 1 MTIOC10C PDL_MTU_OUT_P_PHASE_3 HIGH LOW or PDL_MTU_OUT_P_ PHASE 3 LOW HIGH For n 0 MTIOC4B For n 1 MTIOC10B PDL_MTU_OUT_N_PHASE_3_HIGH_LOW or PDL_MTU_OUT_N_PHASE_3_LOW_HIGH For n 0 MTIOC4D For n 1 MTIOC10D Write access control PDL_MTU_OUT_LOCK_ENABLE Prevent further changes to the phase output control Toggle output control PDL_MTU_OUT_TOGGLE_ENABLE or PDL_MTU_OUT TOGGLE DISABLE Enable or disable toggle output synchronised with the PWM cycle data3 The buffer control settings to be modified All settings are optional If multiple selections are required use to separate each selection Output level buffer control Set the output control to be transferred to the output PDL_MTU_OUT_BUFFER_P_PHASE_1_LOW or PDL MTU OUT BUFFER _P_PHASE_1_HIGH For n 0 MTIOC3B For n 1 MTIOCS9B PDL MTU OUT BUFFER N PHASE 1 LOW or PDL MTU OUT BUFFER N PHASE 1 HIGH For n 0 MTIOC3D For n 1 M
9. Configure the Watchdog timer bool R_WDT_Create uint16_t data1 void func uint8_t data2 Set up and start the Watchdog timer data1 4 Library Reference II Configuration selection II Callback function Interrupt priority level Configure the timer To set multiple options at the same time use to separate each value The default settings are shown in bold Clock selection PDL WDT PCLK DIV_4 or PDL WDT PCLK DIV_64 or PDL WDT PCLK DIV_128 or PDL WDT PCLK DIV_512 or PDL WDT PCLK DIV_2048 or PDL WDT PCLK DIV_8192 or PDL WDT PCLK DIV_32768 or PDL_WDT_ PCLK_ DIV_131072 The division ratio for the internal clock signal PCLK MCU reset control PDL_WDT_RESET_DISABLE or PDL_WDT_RESET_ ENABLE Disable or enable reset of the MCU when the watchdog timer overflows with no callback function specified func The function to be called at the periodic interval Specify PDL_NO_FUNC to have the timer output a WDTOVF signal The MCU will also be reset if selected above data2 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false Watchdog Timer R20UT0084EE0004 Rev 0 04 Aug 25 201
10. Reference Remarks Read the status for an I C channel bool R_IIC_GetSitatus uint8_t data1 Channel selection uint32_t data2 Status flags uint16_t data3 Transmitted bytes uint16_t data4 Received bytes Read the status registers for the selected I C channel data1 Select channel IICn where n 0 or 1 data2 The status flags shall be stored in the format below Specify PDL_NO_PTR if this information is not required b31 b18 b17 b16 Buffer status 0 Transmit Receive 0 Full 0 Empty 1 Empty 1 Full b15 b14 b13 b12 b11 b10 b9 b8 Bus state Pin level Event detection 0 Not detected 1 detected 0 Idle Stop Start P 1 Busy SCL SDA NACK condition condition Arbitration lost Timeout b7 b6 b5 b4 b3 b2 bi b0 Transmission Mode Address detection 0 Not detected 1 detected 0 Active 0 Receive p Slave 1 Idle 1 Transmit SMBus host Device ID General call 5 1 0 data3 The address for storing the number of bytes that are have been transmitted in the current transfer Specify PDL_NO_PTR if this information is not required Te aes for storing for the number of bytes that are have been received in the current transfer Specify PDL_NO_PTR if this information is not required True if all parameters are valid otherwise false C R_IIC_Create e The flags are not modified by this
11. Multi Function Timer Pulse Unit R_MTU_Set Configure the Multi function Timer Pulse Units R_MTU_Create Configure a MTU channel R_MTU_Destroy Disable a Multi function Timer Pulse Unit R_MTU_ControlChannel Control an MTU channel R_MTU_ControlUnit Control a Multi function Timer Pulse Unit R_MTU_ReadChannel Read from MTU channel registers R_MTU_ReadUnit Read from MTU registers Port Output Enable R_PPG_Create Configure a PPG group R_PPG_Destroy Disable a PPG unit R_PPG_Control Control a PPG group Programmable Pulse Generator R_PPG_Create Configure a PPG group R_PPG_Destroy Disable a PPG unit R_PPG_Control Control a PPG group 8 bit Timer R_TMR Set Configure the optional TMR pins R_TMR_CreateChannel Configure a TMR timer channel R_TMR_CreateUnit Configure a TMR timer unit R_TMR_CreatePeriodic Select periodic operation R_TMR_CreateOneShot Configure and use a one shot timer R_TMR_Destroy Disable a TMR timer unit R_TMR_ControlChannel Write to timer channel registers R_TMR_ControlUnit CO OO Ni OD 01 B OO PO gt CO PO OO PO NI Om Oo AI WIN a Write to timer unit registers R_TMR_ControlPeriodic Control periodic operation 10 R_TMR_ReadChannel Read from
12. PDL_DMAC_ TRIGGER _USBO_DO or PDL_DMAC_TRIGGER USB1 DO or DOFIFO transfer request on USB port n n 0 to 1 PDL_DMAC_TRIGGER USB0 D1 or PDL_DMAC_TRIGGER_USB1_D1 or D1FIFO transfer request on USB port n n 0 to 1 PDL_DMAC TRIGGER SPIO_RX or PDL_DMAC_TRIGGER SPI1_RX or Receive buffer full on RSPI channel n n 0 to 1 PDL_DMAC_ TRIGGER SPIO_TX or PDL_DMAC_ TRIGGER SPI1_TX or Transmit buffer empty on RSPI channel n n 0 to 1 PDL_DMAC_TRIGGER_IRQO or PDL_DMAC_TRIGGER_IRQ1 or PDL_DMAC_TRIGGER_IRQ2 or PDL_DMAC_TRIGGER_IRQ3 or Valid edge detected on pin IRQn n 0 to 3 PDL_DMAC_TRIGGER ADC10_0or PDL_DMAC_TRIGGER ADC10_1 or Conversion completed on 10 bit ADC unit n n 0 to 1 PDL_DMAC_TRIGGER_ADC12 or Conversion completed on 12 bit ADC unit PDL_DMAC_TRIGGER_MTUO or PDL_DMAC_TRIGGER_MTU1 or PDL_DMAC_TRIGGER_MTU2 or PDL_DMAC_TRIGGER_MTU3 or PDL_DMAC_TRIGGER_MTU4 or PDL_DMAC_TRIGGER_MTU6 or PDL_DMAC_TRIGGER_MTU7 or PDL_DMAC_TRIGGER_MTU8 or PDL_DMAC_TRIGGER_MTU9 or PDL_DMAC_TRIGGER_MTU10 or Input capture or compare match on MTU channel n n 1 to 4 or 6 to 10 PDL_DMAC_TRIGGER_SCIO_RX or PDL_DMAC_TRIGGER_SCI1_RX or PDL_DMAC_ TRIGGER _SCI2_ RX or PDL_DMAC_ TRIGGER SCI3_RX or PDL_DMAC_TRIGGER_SCI5_RX or PDL_DMAC_ TRIGGER _SCI6 Rx or Receive buffer full on SCI c
13. PDL_INTC_CLEAR_OSD_FLAG Clear the Oscillation Stop detection flag Interrupt control True if all parameters are valid and exclusive otherwise false R_INTC_CreateExtInterrupt R_INTC_GetExtInterruptStatus The NMI pin was enabled during R_INTC_CreateExtInterrupt and cannot be disabled an MCU design feature When disabling an IRQn pin the Interrupt Request flag will be cleared automatically A callback function may be called once more if a valid event occurs just before the interrupt pin is disabled R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 20 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group E E Program example RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void Disable the IRQ1 interrupt pin and clear the flag R_INTC_ControlExtInterrupt PDL_INTC_IRQ1 PDL_INTC_DISABLE PDL_INTC_CLEAR_IR_FLAG R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 21 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group diban Rewrsnes 6 R_INTC_GetExtinterruptStatus Synopsis Read the external interrupt status Prototype bool R_INTC_GetExtinterruptStatus
14. Set Auto Refresh register PDL_BSC_SDRAM AUTO REFRESH ENABLE Start Auto Refresh Clear Auto Refresh register PDL_BSC_SDRAM_ AUTO REFRESH DISABLE Stop Auto Refresh Set Self Refresh register PDL_BSC_SDRAM_SELF_REFRESH_ENABLE Start Self Refresh Clear Self Refresh register PDL_BSC_SDRAM_SELF_REFRESH_ DISABLE Stop Self Refresh Enable SDRAM PDL_BSC_SDRAM_ENABLE Enable SDRAM operation Disable SDRAM PDL_BSC_SDRAM_DISABLE Disable SDRAM operation Disable bus error interrupt request PDL_BSC_DISABLE_BUSERR_IRQ Disable bus error interrupt request Return value Category Reference Remarks Program example 1 1 Bus Controller RPDL definitions nclude r_pdl_bsc h RPDL device specific definitions nclude r_pdl_definitions h void func void Clear the bus error signals R_BSC_Control PDL_BSC_ERROR_CLEAR i R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 60 True if success False if multiple selections or condition not right for register modification R_BSC_Create RBSC_SDRAM_CreateArea R_BSC_Destroy e This function can be called from the error handling function see R_BSC_Create e This function will clear the Interrupt Status Flag indirectly Under development Preliminary Specification Specifications in this preliminary
15. to separate each selection Stop generation PDL_IIC_STOP Issue a Stop condition e NACK generation PDL_IIC_NACK Set the Acknowledge bit to the NACK state Pin control PDL_lIC_SDA_LOW or PDL_IIC_SDA HI Z Set the SDA pin to low level or high impedance PDL_IIC_SCL_LOWor PDL_lIC_SCL_HI Z e Extra clock cycle generation Set the SCL pin to low level or high impedance PDL_IIC_CYCLE_SCL Generate an extra clock cycle on the SCL pin This can be used in Master mode to try and unlock a slave device that is holding the SDA signal low Reset control PDL_IIC_RESET Carry out an internal reset of the C module the settings are preserved True if all parameters are valid exclusive and achievable otherwise false PC R_IIC_Create None RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h void func void Issue a Stop condition on channel 0 R_IIC Control 0 PDL_IIC_STOP R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 175 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 9 R_IIC_GetStatus Synopsis Prototype Description Return value Category
16. PDL_BSC_A19_DISABLE Disable the output of the A19 signal PDL_BSC_A20_DISABLE Disable the output of the A20 signal PDL_BSC_A21 DISABLE Disable the output of the A21 signal PDL_BSC_A22_DISABLE Disable the output of the A22 signal PDL_BSC_A23_DISABLE Disable the output of the A23 signal e SDRAM output control PDL_BSC_SDRAM_PINS_DISABLE or PDL_BSC_SDRAM_ PINS ENABLE Enable or disable the SDRAM Pins except DQM1 pin PDL_BSC_SDRAM_DQM1_DISABLE or PDL_BSC_SDRAM_DQM1_ENABLE Enable or disable the DQM1 pin PDL_BSC_SDRAM_SDCLK_DISABLE or PDL_BSC_SDRAM_SDCLK_ENABLE Enable or disable the SDCLK output data3 e Error monitoring PDL_BSC_ERROR_ILLEGAL_ADDRESS_ENABLE or Enable or disable illegal address PDL_BSC_ERROR_ILLEGAL ADDRESS DISABLE access detection PDL_BSC_ERROR_TIME_OUT_ ENABLE or Enable or disable bus time out PDL_BSC_ERROR_TIME_OUT_ DISABLE detection func The function to be called when a bus error occurs Specify PDL_NO_FUNC if not required data4 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func Return value Category Bus Controller Reference R_BSC_CreateArea R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 51 True if all parameters are valid and exclu
17. PDL_TMR_OUTPUT_IGNORE_CM_Aor No change if a compare match A occurs PDL_TMR_OUTPUT_LOW_CM_Aor 0 is output if a compare match A occurs PDL_TMR_OUTPUT_HIGH_CM_Aor 1 is output if a compare match A occurs PDL_TMR_OUTPUT_INV_CM_A The output toggles if a compare match A occurs PDL_TMR_OUTPUT_IGNORE_CM_B or Nochange if a compare match B occurs PDL_TMR_OUTPUT_LOW_CM_B or 0 is output if a compare match B occurs PDL_TMR_OUTPUT_HIGH_CM_B or 1 is output if a compare match B occurs PDL_TMR_OUTPUT_INV_CM_B The output toggles if a compare match B occurs data4 The counter value data5 The compare match A value data6 The compare match B value func1 The function to be called when an overflow occurs Use PDL_NO_FUNC if not required func2 The function to be called when a Compare match A occurs Use PDL_NO_FUNC if not required func3 The function to be called when a Compare match B occurs Use PDL_NO_FUNC if not required data7 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func1 func2 and func3 Return value True if all parameters are valid and exclusive otherwise false Category Timer TMR Reference R_TMR_Destroy R_TMR_ControlChannel R_ TMR_ControlUnit R TMR_ReadChannel R_TM R_ReadUnit R_LTMR_Set Remarks e Ifan input pin TMCIn or TMRIn is se
18. R20UT0084EE0004 Rev 0 04 Aug 25 2010 Sates RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Apiary E enes Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Load the unit 1 counter and constants R_TMR_ControlUnit 1 PDL_TMR_COUNTER PDL_TMR_TIME_CONSTANT_A PDL_TMR_TIME_CONSTANT_B OxAAFF 0x100 0x5600 R20UT0084EE0004 Rev 0 04 Aug 25 2010 a 2 Page 4 125 a ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group dieing Resrenes 9 R_TMR_ControlPeriodic Synopsis Control periodic operation Prototype bool R_TMR_ControlPeriodic uint8_tdata1 8 bit channel or 16 bit unit selection uint32_t data2 Configuration selection float data3 The new period or frequency float data4 The new pulse width or duty cycle Description Modify a periodic timer operation data1 PDL_TMR_TMRO or PDL_TMR_TMR1 or PDL_TMR_TMR2 or The channel n n 0 1 2 or 3 or unit n 0 or 1 to be PDL_TMR_TMR3 or configured PDL_TMR_UNITO or PDL_TMR_UNIT 1 data2 Select the options to be modified Use to separate each s
19. b7 b6 b5 b3 b2 b1 bO Detection Count Underflow Overflow Input capture compare match direction U V 0 B A 0 down 1 up Forn 30r9 b7 b6 b5 b4 b3 b2 b1 bO 7 Detection Count Overflow Input capture compare match direction 0 V 0 D C B A sane 1 up Forn 4or 10 b7 b6 b5 b4 b3 b2 b1 bO Detection Overflow or Count und rf w Input capture compare match direction 0 V 0 D C B A oa down 1 up Forn 5or 11 b7 b3 b2 b1 bO f Detection Input capture compare match 0 Ww V U R20UT0084EE0004 Rev 0 04 Aug 25 2010 Saag RENESAS Under development Preliminary Specification Description 2 2 Return value Category Reference Remarks Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference data3 For n 0 to 4 or 6 to 10 A pointer to where the TNCT register value shall be stored For n 5 or 11 A pointer to where the TNCTU register value shall be stored Specify PDL_NO_PTR if it is not required data4 For n 0 to 4 or 6 to 10 A pointer to where the TGRA register value shall be stored For n 5 or 11 A pointer to where the TNCTV register value shall be stored Specify PDL_NO_PTR iff it is not required data5 For n 0 to 4 or 6 to 10 A pointer to where the TGRB register value shall be stored For n 5 or 11 A pointer to where the TNCTW register value shall be stored
20. data3 The one shot time period in seconds func The function to be called when the one shot period ends Specify PDL_NO_FUNC for this function to wait for the timer to complete before returning You should always specify a function if PDL_TMR_CPU_OFF is selected to ensure that an interrupt will re start the CPU data4 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func Return value Category Timer TMR Reference R_TMR_Destroy R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 120 True if all parameters are valid and exclusive otherwise false 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Remarks Program example 4 Library Reference Function R_CGC_Set must be called before any use of this function This function is an alternative to Error Not a valid result for table and R_TMR_CreateUnit This function stops the timer on completion so no other TMR function calls are required If an output pin TMOn is enabled this function will disable other output functions on that pin If a callback function is specified this function will enable the relevant interrupt Please see the notes on callback function usage in 6
21. data4 The number of bytes in the storage area func The function to be called when a A Stop condition is detected or b The master tries to read data from this slave Specify PDL_NO_FUNC for this function to wait until either event occurs data5 The interrupt priority level Select between 1 lowest priority and 7 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func Return value True if all parameters are valid exclusive and achievable otherwise false Category 2C Reference R_IIC_Create R_IIC_GetStatus R_IIC_SlaveSend R20UT0084EE0004 Rev 0 04 Aug 25 2010 Sangin RENESAS Under development Preliminary Specification Remarks Program example Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference If a callback function is specified interrupts are used Use R_IIC_GetStatus in the callback function to identify the activity that has occurred Please see the notes on callback function usage in 6 If no callback function is specified this function will read the status flags to monitor the bus activity Use R_IIC_GetStatus to identify the activity that has occurred If the 12C channel s control registers are directly modified by the user this function may lock up If the master sends more data than is expected and the DMAC DTC trigger is disabled thi
22. Counter clearing PDL_TMR_CLEAR_DISABLE or Clearing is disabled PDL_TMR_CLEAR_CM_Aor Cleared after a compare match A occurs PDL_TMR_CLEAR_CM_B or Cleared after a compare match B occurs PDL_TMR_CLEAR_RESET_RISING or Cleared by a rising edge on the external reset pin TMRIn PDL_TMR_CLEAR_RESET_HIGH Cleared when the external reset pin TMRIn is high ADC trigger control PDL_TMR_ADC_TRIGGER_DISABLE or PDL_TMR_ADC_TRIGGER_ENABLE Disable or enable ADC conversion start requests on a compare match A signal Only applicable for channels TMRO or TMR2 Compare Match A DTC trigger control PDL_TMR_CM_A_DTC_TRIGGER_DISABLE or PDL_TMR_CM_A DTC TRIGGER ENABLE Disable or enable activation of the DTC when a Compare Match A occurs Compare Match B DTC trigger control PDL_TMR_CM_B_DTC_TRIGGER_DISABLE or PDL_TMR_CM_B DTC TRIGGER _ENABLE Disable or enable activation of the DTC when a Compare Match B occurs 7tENESAS Under development RX62N Group RX621 Group Preliminary Specification Specifications in this preliminary version are subject to change 4 Library Reference Description 2 2 data3 Configure the output control If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Output control for pin TMOn
23. L_NO_FUNC R20UT0084EE0004 Rev 0 04 Aug 25 2010 a2 AS Page 5 42 KENES Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Weageexamplee Read data from the EEPROM on channel 1 using the DMAC read_eeprom_data j Prepare the next data R_DMAC_Control PDL _DMAC_2 L_DMAC_SUSPEND PDL_DMAC_ENABLE L_DMAC_UPDATE_DESTINATION PDL_DMAC_UPDATI L_NO_DATA L_NO_PTR ata_storage 5 f PDL_NO_PTR PDL_NO_PTR DL_NO_DATA Read data from the EEPROM on channel 1 using the DMAC read_eeprom_data static void write_eeprom_data void bus_busy true Send data to the EEPROM on channel 1 using the DMAC R_IIC_MasterSend 0 Pp DL_IIC_DMAC_TRIGG EEPROM_ADDRESS DL_NO_PTR PDL_NO_FUNC while bus_busy true Wait for 5ms while the EEPROM updates R_CMT_CreateOneShot 0 E 3 DL_NO_FUNC static void read_eeprom_data void bus_busy true Read data from the EEPROM on channel 1 using the DMAC R_IIC_MasterReceive 0 P DL_IIC_DMAC_TRIGG EEPROM_ADDRESS DL_NO_PTR PDL_NO_FUNC while bus_busy true void iic_tx_dmac_end_handler void uint32_t status_flags 0 Wait for the transmissi
24. R_IIC_MasterReceiveLast 1 amp data_array 4 3 R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 171 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group dban Rewrsnes 6 R_IIC_SlaveMonitor Synopsis Monitor the bus Prototype bool R_IIC_SlaveMonitor uint8_t data1 Channel selection uint16_tdata2 Channel configuration uint8_t data3 Receive data start address uint16_t data4 Receive threshold void func Callback function uint8_t data5 Interrupt priority level Description Monitor the bus until an address match occurs and store any data received Register the storage area and transfer method for data received on the selected I C channel data1 Select channel IICn where n 0 or 1 data2 Select the operation options The default setting is shown in bold Specify PDL_NO_DATA to use the default e DMAC DTC trigger control PDL_lIC_RX_DMAC_DTC_TRIGGER_DISABLE or PDL_lIC_RX_DMAC_TRIGGER_ENABLE or PDL_lIC_RX_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC when a byte is received PDL_lIC_TX_DMAC_DTC_TRIGGER_DISABLE or PDL_lIC_TX_DMAC_TRIGGER_ENABLE or PDL_lIC_TX_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC for data transmission data3 The start address of the storage area for any received data
25. 0 PDL_TMR_CLK_PCLK_DIV_1 PDL_TMR_CLEAR_CM_A 0 0 199 99 PDL_NO_FUNC PDL_NO_FUNC PDL_NO_FUNC 0 R20UT0084EE0004 Rev 0 04 Aug 25 2010 a 2 Page 4 116 a ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 R_TMR_CreatePeriodic Synopsis Select periodic operation Prototype bool R_TMR_CreatePeriodic 4 Library Reference uint8_t data1 8 bit channel or 16 bit unit selection uint32_t data2 Configuration selection float data3 II Period or frequency float data4 Pulse width or duty cycle void func1 Callback function void func2 Callback function uint8_t data5 Interrupt priority level Description 1 2 data1 Set up a TMR timer channel or unit for periodic operation and start the timer PDL_TMR_TMRO or PDL_TMR_TMR1 or PDL_TMR_TMR3 or configured PDL_TMR_UNITO or PDL_TMR_UNIT1 PDL_TMR_TMR2 or The channel n n 0 1 2 or 3 or unit n 0 or 1 to be data2 Configure the timer If multiple selections are required use to separate each selection The default settings are shown in bold e Period or frequency calculation PDL_TMR_PERIOD or The parameters data3 and data4 will contain either period PDL_TMR_FREQUENCY and pulse width or frequency and duty cycle e Output pin cont
26. MTIOCnB initial output low goes high at compare match MTIOCnB initial output low toggles at compare match MTIOCnB initial output high goes low at compare match MTIOCnB output high MTIOCnB initial output high toggles at compare match PDL_MTU_B_IC_RISING_EDGE or PDL_MTU_B_IC_FALLING EDGE or PDL_MTU_B_IC_BOTH EDGES or Input capture at MTIOCnB rising edge Input capture at MTIOCnB falling edge Input capture at MTIOCnB both edges PDL_MTU_B_IC_COUNT or Input capture at channel n 1 up count or down count Valid only for n 0 or 6 PDL_MTU_B_IC_CM_IC Input capture at channel n 1 TGRC compare match or input capture Valid only for n 1 or 7 e Cascade input capture control Valid in cascade mode for n 1 or 7 Channel n forms the higher 16 bits and channel n 1 forms the lower 16 bits PDL_MTU_CASCADE_AL_IC_INC_H PDL_MTU_CASCADE_AL_IC_EXC_Hor Exclude or include pin MTIOCnA or MTIOCnE in the TGRA input capture conditions for channel n 1 PDL_MTU_CASCADE_BL_IC_INC_H PDL_MTU_CASCADE_BL_IC_EXC_Hor Exclude or include pin MTIOCnB or MTIOCnF in the TGRB input capture conditions for channel n 1 PDL_MTU_CASCADE_AH_IC_INC_L PDL_MTU_CASCADE_AH_IC_EXC _L or Exclude or include pin MTIOC n 1 A or MTIOC n 1 E in the TGRA input capture conditions for channel n PDL_MTU_CASCADE_BH_IC_INC_L PDL_MTU_CASCADE_BH_IC_EXC _Lor Exclude or include pin MTIOC n 1 B
27. Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group A ibrar Reteenes 5 R_IO_PORT Write Synopsis Write data to an I O port Prototype bool R_IO_PORT_Write uint16_t data1 Port or port pin selection uint8_t data2 The data to be written to the I O port or port pin Description Write data to an I O port or I O port pin data1 Use either one of the following definition values from 4 2 3 One port definition or e One port pin definition data2 The value must be between 0x00 and OxFF for a port 0 or 1 for a pin Return value True if the parameters are valid otherwise false Functionality I O port References R_IO_PORT_Set R_IO_PORT_Read Remarks e Ifan invalid port or pin is specified the operation of the function cannot be guaranteed Program example RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Set the output of port pin P05 R_IO_PORT_Write PDL_IO_PORT_0_5 0 Set the output of port 6 R_IO_PORT_Write PDL_IO PORT 6 0x55 i R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 33 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621
28. Unit selection uint32_t data2 Configuration selection uint16_tdata3 Register value uint1i6_t data4 Register value uint16_t data5 Register value Description Modify a timer units counter and compare registers data1 The unit number n where n 0 or 1 data2 The channel settings to be modified If multiple selections are required use to separate each selection e Counter stop re start PDL_TMR_STOP or PDL_TMR START Disable or re enable the counter clock source e The counter or compare registers to be modified PDL_TMR_COUNTER Update the timer counter register TCNT PDL_TMR_TIME_CONSTANT_A Update the timer compare match A register TCORA PDL_TMR_TIME_CONSTANT_B Update the timer compare match B register TCORB data3 The 16 bit counter value This will be ignored if the register is not selected data4 The 16 bit compare match A value This will be ignored if the register is not selected data5 The 16 bit compare match B value This will be ignored if the register is not selected Return value True if all parameters are valid and exclusive otherwise false Category Timer TMR Reference R_TMR_CreateUnit R_ TMR_ReadUnit Remarks e For unit 0 the upper byte is the value for TMRO and the lower byte is the value for TMR1 For unit 1 the upper byte is the value for TMR2 and the lower byte is the value for TMR3
29. e Call this function once for each peripheral that will trigger a transfer and for each chained transfer e When all calls to this function are complete call R_DTC_Control to start the DTC R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 75 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Program example 4 Library Reference RPDL definitions include r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h Reserve 16 bytes full address mode for the CMTO triggered transfer data area Use a 32 bit type to make the address a multiple of 4 uint32_t dtc_cmt0O_transfer_data 4 void func void Configure the DTC for CMTO R_DTC_Create PDL_DTC_NORMAL PDL_DTC_SOURCE_ADDRESS_ FIXED PDL_DTC_DESTINATION_ADDRESS_PLUS PDL_DTC_SIZE_8 PDL_DTC_TRIGGER_CMTO dtc_cmt0O_transfer_data 0x0000AA00 0x0000BB00 100 0 R20UT0084EE0004 Rev 0 04 Aug 25 2010 ztENESAS Page 4 76 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 3 R_DTC_Destroy Synopsis Prototype Description Return value Category Reference Remarks
30. r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown SCI channel 1 R_SCI_Destroy 1 3 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Sagas RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 R_SCI_ Send Synopsis Prototype Description Return value Category Reference 4 Library Reference Transmit data on a SCI channel bool R_SCI_Send uint8_t data1 Channel selection uint16_t data2 Channel configuration and Target Station ID uint8_t data3 Data start address uint16 tdata4 Data count void func Callback function Transmit data on the specified serial channel data1 Select channel SClin where n 0 to 6 but not 4 data2 The lower 8 bit selects the DMAC DTC trigger control or specify the ID cycle for Multi processor mode The upper 8 bit is the Station ID which is only valid with the ID cycle DMAC DTC trigger control The default setting is shown in bold May also specify PDL_NO_DATA to use the defaults PDL_SCI_DMAC_DTC_TRIGGER_DISABLE or PDL_SCIl_DMAC_TRIGGER_ENABLE or PDL_SCI_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC when a data byte is transmitted ID cycle indication for Multi proce
31. 1 SDRAM mode Description 1 2 Set up SDRAM area data1 Configure the operation of SDRAM area 4 Library Reference II Configuration selection If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e SDRAM bus width PDL_BSC_SDRAM_WIDTH_16 or PDL_BSC_SDRAM_WIDTH_8 or PDL_BSC_SDRAM WIDTH 32 Select 16 bit 8 bit or 32 bit data bus width Endian mode PDL_BSC_SDRAM_ENDIAN_SAME or PDL_BSC_SDRAM_ENDIAN_OPPOSITE Set the bus endian mode to be the same or opposite to that of the CPU Continuous access mode PDL_BSC_SDRAM_CONT_ACCESS DISABLE or PDL_BSC_SDRAM_CONT ACCESS ENABLE Disable or enable Continuous Access e Address multiplex selection PDL_BSC_SDRAM_8 BIT_SHIFT or PDL_BSC_SDRAM_9 BIT_SHIFT or PDL_BSC_SDRAM_10_BIT_SHIFT or PDL_BSC_SDRAM_11_BIT_SHIFT Select the size of shift in address multiplexing 8 bit shift 9 bit shift 10 bit shift or 11 bit shift data2 The value to be set to RFC bits in SDRAM Refresh Control Register SDRFCR Valid between 0x0001 and OxOFFF Setting of 0x0000 is prohibited data3 The value to be set to REFW bits in SDRAM Refresh Control Register SDRFCR Valid between 0x00 and OxOF data4 The value to be set to ARFI bits in SDRAM Initialization Register SDIR Valid between 0x00 and OxO
32. 4 Library Reference Channel selection Channel configuration II Detection configuration Slave address Slave address Slave address Transfer rate control Rise and fall time correction PDL_lIC_MODE_IIC or PDL_IIC_MODE_IIC_FMP or PDL_lIC_MODE_SMBUS Choose between I C Bus IC Bus with Fast mode Plus for data rate gt 400 kbps or SMBus mode Internal reference clock PDL_lIC_INT_PCLK_DIV_1 or PDL_lIC_INT_PCLK_DIV_2 or PDL_lIC_INT_PCLK_DIV_4 or PDL_lIC_INT_PCLK_DIV_8 or PDL_lIC_INT_PCLK_DIV_16 or PDL_lIC_INT_PCLK_DIV_32 or PDL_lIC_INT_PCLK_DIV_64 or PDL_lIC_INT_PCLK_DIV_128 The reference clock source used inside the IC module Timeout detection control PDL_lIC_TIMEOUT_DISABLE or PDL_IIC_TIMEOUT_LOW or PDL_IIC_TIMEOUT_HIGH or PDL_lIC_TIMEOUT_BOTH Disable timeout detection or enable for SCL stuck at a low level high level or both low and high level Timeout mode PDL_IIC_TIMEOUT_LONG or PDL_lIC_TIMEOUT_SHORT Select 16 bit long or 14 bit short mode SDA output delay count PDL_lIC_SDA_DELAY_0 or PDL_lIC_SDA_DELAY_1 or PDL_lIC_SDA_DELAY_2 or PDL_lIC_SDA_DELAY_3 or PDL_lIC_SDA_DELAY_4 or PDL_lIC_SDA_DELAY_5 or PDL_lIC_SDA_DELAY_6 or PDL_lIC_SDA_DELAY_7 Select the number of cycles for the SDA output delay counter SDA output delay clock source PDL_lIC_SDA_DELAY_DIV_1or PDL_lIC_SDA_DELAY
33. PDL_DMAC_UPDATE_DESTINATION Destination address using parameter data4 PDL_DMAC_UPDATE_COUNT Transfer count using parameter data5 PDL_DMAC_UPDATE_SIZE Repeat or Block size using parameter data6 PDL_DMAC_UPDATE_OFFSET Address offset using parameter data7 PDL_DMAC_UPDATE_REPEAT_SOURCE Source address extended repeat area using parameter data8 PDL_DMAC_UPDATE_REPEAT_DESTINATION Destination address extended repeat area using parameter data9 data3 The new source address Specify PDL_NO_PTR if not required data4 The new destination address Specify PDL_NO_PTR if not required data5 The transfer count value Specify PDL_NO_DATA if not required data6 The repeat or block size for each transfer Valid between 0 and 1023 0 1024 units Ignored in normal mode Specify PDL_NO_DATA if not required 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group A tien Reteeies Description 2 2 data7 The address offset value The range is from 16 777 215 to 16 777 216 This value is ignored if the offset function is not selected Specify PDL_NO_DATA if not required data8 The source address extended repeat value The value can be any power of 2 from 2 to 2 Specify PDL_NO_DATA if not required data9 The destination address extended repeat value Th
34. PDL_PPG_PO4 PDL_PPG P06 PDL_PPG_TRIGGER_MTU2 0x15 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 R_PPG_Destroy Synopsis Prototype Description Disable PPG outputs bool R_PPG_Destroy Output pin selection uint32_t data data Select the outputs to be disabled Disable the pulse output on the selected pins 4 Library Reference If multiple selections are required use to separate each selection Select only outputs within one group Return value Category Reference Remarks Output pin selection PDL_PPG_POO PDL_PPG_PO1 PDL_PPG PO2 PDL_PPG PO3 Group 0 PDL_PPG_PO4 PDL_PPG_POS5 PDL_PPG_PO6 PDL_PPG_PO7 Group 1 PDL_PPG_PO8 PDL_PPG_PO9 PDL_PPG_ PO10 PDL_PPG_PO11 Group 2 PDL_PPG PO12 PDL_PPG PO13 PDL_PPG PO14 PDL_PPG PO15 Group 3 Unit 0 PDL_PPG PO16 PDL_PPG PO17 PDL_PPG PO18 PDL_PPG_PO19 Group 4 PDL_PPG PO20 PDL_PPG_PO21 PDL_PPG PO22 PDL_PPG_ PO23 Group 5 PDL_PPG PO24 PDL_PPG PO25 PDL_PPG PO26 PDL_PPG PO27 Group 6 PDL_PPG PO28 PDL_PPG_PO29 PDL_PPG PO30 PDL_PPG_PO31 Group 7 Unit 1 R
35. PDL_TMR_CLEAR_CM_A PDL_NO_DATA 0 199 99 PDL_NO_FUNC PDL_NO_FUNC PDL_NO_FUNC R20UT0084EE0004 Rev 0 04 Aug 25 2010 a 2 Page 4 113 a ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 3 R_TMR_CreateUnit Synopsis Configure a timer TMR unit Prototype bool R_TMR_CreateUnit uint8_t data1 Channel selection uint32_t data2 uint8_t data3 uint16_t data4 uint16_t data5 uint16_t data6 Output control Register value Register value Register value void func Callback function void func2 Callback function void func3 Callback function uint8_t data7 Description 1 2 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 114 data1 The unit number n where n 0 or 1 data2 Interrupt priority level Set up a timer TMR unit in 16 bit count mode 4 Library Reference II Configuration selection Configure the unit If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Counter clock source selection PDL_TMR_CLK_OFF or The clock input is disabled PDL_TMR_CLK_EXT_RISING or PDL_TMR_CLK_EXT_FALLING or PDL_TMR_CLK_EXT_BOTH or The external clock signal TMCIx x 0 or 2 for n 0 or 1 i
36. Program example Disable the Data Transfer Controller bool R_DTC_Desiroy void II No parameter is required Shutdown the Data Transfer Controller True Data Transfer Controller R_DTC_Control e This function will also shut down the DMAC Before calling this function i If another peripheral is being used to trigger a DTC transfer stop the triggers from that peripheral using Control or Destroy for that peripheral ii Use R_DTC_Control to stop the DTC iii Stop the DMAC RPDL definitions include r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown the DTC amp DMAC R_DTC_Destroy R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 77 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 4 R_DTC_Control Synopsis Prototype Description Return value Category Reference Remarks Control the Data Transfer Controller bool R_DTC_Control uint32_t data1 Control options uint32_t data2 Transfer data start address void data3 Source start address void data4 Destination start address uint16_t data5 Transfer count uint8_t data6 II Block size Modify the operation of the Data Transfer Controller
37. RX62N Group RX621 Group Description 2 2 data3 4 Library Reference Configure the output control If multiple selections are required use to separate each selection The default settings are shown in bold e Output control for pin TMOy y 0 or 2 for n 0 or 1 PDL_TMR_OUTPUT_LOW_CM_Aor 0 is output if a compare PDL_TMR_OUTPUT_HIGH_CM_Aor 1 is output if a compare PDL_TMR_OUTPUT_IGNORE_CM_A or No change if a compare match A occurs match A occurs match A occurs PDL_TMR_OUTPUT_INV_CM_A The output toggles if a compare match A occurs PDL_TMR_OUTPUT_IGNORE_CM_B or No change if a compare match B occurs PDL_TMR_OUTPUT_LOW_CM_B or 0 is output if a compare match B occurs PDL_TMR_OUTPUT_HIGH_CM_B or 1 is output if a compare match B occurs PDL_TMR_OUTPUT_INV_CM_B The output toggles if a compare match B occurs data4 The 16 bit counter value data5 The 16 bit compare match A value data6 The 16 bit compare match B value funct The function to be called when an overflow occurs Use PDL_NO_FUNC if not required func2 The function to be called when a Compare match A occurs Use PDL_NO_FUNC if not required func3 The function to be called when a Compare match B occurs Use PDL_NO_FUNC if not required data7 The interrupt priority level Select between 1 lowest priority and 15 hi ghest priority This parameter will be ignored if PDL_NO_FUNC
38. amp sdram_status R_BSC_Control PDL_BSC_ERROR_CLEAR while 1 void BSC_error_handler void Invert the port pin R_IO_PORT_Modify PDL_IO_PORT_0_3 PDL_IO_PORT_XOR 1 Clear the error signals R_BSC_Control PDL_BSC_ERROR_CLEAR void NMI_handler_lpc void nop Figure 5 4 Example of SDRAM Bus Controller use R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 5 11 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Weagekxamplez 5 4 DMA controller The following examples show the use of triggers by software IRQ pin edge detection and SCI transmission 1 Software and IRQ triggers Channel 0 will copy the string Renesas RX62N into the destination area when a falling edge occurs on pin IRQ3 B Channel 1 will copy the string Hello World into the destination area as soon as it is enabled PDL functions and definitions include r_pdl_dmac h include r_pdl_cgc h include r_pdl_intc h RPDL device specific definitions P include r_pdl_definitions h Required for this example qu p include lt string h gt Callback function prototype void DMACO_transfer_end_handler void Data source and destination declarations const char source_string_1 Renesas RX62N const char source_string_2 Hello
39. data Control the operation e Stop Start control PDL_DTC_STOP or PDL_DTC START Enable re enable or suspend DTC transfers e The registers to be modified using the selected parameters PDL_DTC_UPDATE_SOURCE The Source Address register using parameter data3 PDL_DTC_UPDATE_DESTINATION The Transfer Address register using parameter data4 PDL_DTC_UPDATE_COUNT The Transfer Count register using parameter data5 PDL_DTC_UPDATE_BLOCK_SIZE The Block Size register using parameter data6 e Transfer trigger control When the transfer count specified in R_DTC_Create is completed the DTC will ignore further interrupts from that trigger source If you require the interrupt to trigger another transfer specify the trigger used in the relevant call of R_DTC_Create data2 The start address of the transfer data area the same as that declared in R_DTC_Create Ignored if no registers are to be modified data3 The source start address The valid range depends on the address mode short or full data4 The destination start address The valid range depends on the address mode short or full data5 The number of transfers to take place For normal or block mode valid between 0 and 65535 0 65536 transfers For repeat mode valid between 0 and 255 0 256 transfers data6 The block size for each transfer Valid between 0 and 255 0 256 units Ignored in normal or repeat mode T
40. define NUM_DATA 50 volatile uint8_t data_received volatile uint8_t error_happen volatile uint8_t receive_data NUM_DATA void main void Lae i bool id_received for i 0 i lt NUM_DATA i receive_data i 0 Configure the clocks R_CGC_Set 12E6 96E6 48E6 0 PDL_CGC_BCLK_HIGH Configure the pin selection of SCI R_SCI_Set PDL_SCI_PIN_SCI2_A j Configure the RS232 port specify Async MP mode R_SCI_Create 2 PDL_SCI_8N1 PDL_SCI_ASYNC_MP 100E3 15 pe Ra Async MP mode data Reception by CPU ISR fe f data_received false error_happen false Wait by CPU ISR until receive matching Station ID 0x0A R_SCI_Receive 2 Ox0A00 PDL_SCI_MP_ID_ CYCLE PDL_NO_PTR 0 SCI1irx SCI1Er while data_received false data_received false Receive data ID 0x0A by CPU ISR R_SCI_Receive 2 PDL_NO_DATA receive_data 10 SCIlrx SCI1Er while data_received false ue Async MP mode data Reception by polling ws R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 5 32 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Usage Example id_received false Wait by polling until receive matching Station ID 0x01 id_received R_SCI_Receive 2 0x0100 PDL_SCI_MP_ID_CYCLE PDL_NO_PTR 0 PDL_NO_FUNC
41. 25 2010 RENESAS Page 5 14 Under development Preliminary Specification Specifications in this preliminary versi RX62N Group RX621 Group 2 SCI transmission trigger ion are subject to change DMAC Channel 3 will be used to transmit the string Renesas RX62N Then the string Hello World will be transmitted by polling PDL functions and definitions include include include include include ry _pdl_dmac h sro pal cgn ry pdl_intc h t pdl sci n r_pdl_definitions h Required for this example include lt string h gt Callback function prototype void DMAC3_transfer_end_handler void RPDL device specific definitions Data source and destination declarations const uint8_t source_string_1 Renesas RX62N const uint8_t source_string_2 Hello World Global flags volatile uint8_t sci_dma_transfer_complete volatile uint8_t break_required void main void Initialise the system clocks t E6 E6 r L_NO_DATA L_CGC_BCLK_DISABLI Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Configure the RS232 port R_SCI_Create 1 PDL_SCI_RX_DISCONNECTED PDL_SCI_8N1 115200 0 Configure channel 3 R_DMAC_Create 3 PDL_DMAC_BLOCK PDL_DMAC_SOURCE_ADDRESS_PLUS PDL_
42. CENESAS C T o T lt V 5 C D Renesas Peripheral Driver Library User s Manual Go NO RX62N RX621 Group Preliminary All information contained in these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp through various means including the Renesas Technology Corp website http www renesas com Renesas Electronics www renesas com Rev 0 04 August 2010 8 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is gra
43. PDL_SCI_PARITY_ODD Select even or odd parity bit Block transfer mode selection PDL_SCI_BLOCK_MODE_OFF or PDL_SCIl_BLOCK_MODE_ON Control Block transfer mode GSM mode selection PDL_SCI_GSM_MODE_OFF or PDL_SCl_GSM_MODE_ON Control GSM mode SCKn pin output control Normal mode GSM mode PDL_SCI_SCK_OUTPUT_OFF or I O pin Not applicable PDL_SCI_SCK_OUTPUT_LOW or Not applicable Fixed low PDL_SCIl_SCK_OUTPUT_ON or Outputs the bit clock PDL_SCI_SCK_OUTPUT_HIGH Not applicable Fixed high data3 The format must be either The transfer bit rate in bits per second If the on chip baud rate generator is selected the clock source and division values will be calculated using this value Or one selection from each of the following using to separate each selection e CKS selection PDL_SCI_PCLK_DIV_1 or PDL_SCI_PCLK_DIV_4 or PDL_SCI_PCLK_DIV_16 or PDL_SCI_PCLK_DIV_64 Select the internal clock signal PCLK 1 4 16 or 64 as the baud rate generator clock source e ABCS selection ignored for synchronous or smart card mode PDL_SCI_CYCLE_BIT_16 or PDL_SCI_CYCLE BIT 8 Select 16 or 8 base clock cycles for one bit period e b31 to b24 b23 to b8 b7 b0 0 the transfer bit rate A value between 0x100 and OxFFFFOO that is nearest to The BRR register value 7tENESAS Under development Preli
44. SCI1Er if id_received true Receive data ID 0x01 by polling R_SCI_Receive 2 PDL_NO_DATA receive_data 10 PDL_NO_FUNC SCI1Er void SCI1rx void data_received true void SCI1Er void error_happen true Figure 5 16 Example of SCI Reception code in Asynchronous Multi Processor mode R20UT0084EE0004 Rev 0 04 Aug 25 2010 Sauer RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Urago Exatiples 5 SCI Transmission in Asynchronous Multi Processor mode Figure 5 17 shows the setting of SCI channel 2 and the Multi Processor mode transmission of data using interrupts and polling PDL functions include r pdl sci h include r opdl cge n PDL device specific definitions include r pdl definitions n void SCI1tx void uint8_t send_data0 n rWelcome to the Renesas RX62N n r uint8_t send_data testing ASYNC MP mode uint32_t tx_end void main void Configure the clocks R_CGC_Set 12E6 96EH6 48E6 0 PDL_CGC_BCLK_HIGH Configure the pin selection of SCI R_SCI_Set PDL_SCI_PIN_SCI2_A Configure the RS232 port specify Async MP mode R_SCI_Create 2 PDL_SCI_8N1 PDL_SCI_ASYNC_MP 100E3 15 use SCI2 A ia a Async MP mode data Transmission by CPU ISR
45. This parameter will be ignored if PDL_NO_FUNC is specified for parameter func Return value True if all parameters are valid otherwise false Category SPI Reference R_SPI_Create Remarks The amount of data for each command must match the number of frames in a command transfer see parameter data3 in R_SPI_Create e Ifa callback function is specified transmission interrupts are used Please see the notes on callback function usage in 6 e Ifa callback function is specified avoid enabling activation of the DMAC or DTC for data transmission R20UT0084EE0004 Rev 0 04 Aug 25 2010 Sagan RENESAS Under development Preliminary Specification RX62N Group RX621 Group Program example R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 187 Specifications in this preliminary version are subject to change RPDL definitions include r_pdl_spi h RPDL device specific definitions include r_pdl_definitions h void func void uint uin uin uin uin uin uin uin teteatcetcaec co H H H OO H H H ct cat cc uint8_t command_0_tx_data_string 4 command_0O_data command_1_data command_2_ data command_3_ data command_4_data command_5_ data command_6_data command_7_data R_S Transmit 4 bytes PI_Transfer 0 12 times command_0_tx_data_string DL_NO_PT L_NO_PT L_NO_PT L_NO_PT L_NO_PT L_NO
46. data15 For n 0 or 6 The register TGRF value For n 4 or 10 The register TADCORA value Ignored for n 1 2 3 5 7 8 9 or 11 data16 The register TADCORB value ignored for n 4 or 10 data17 The register TADCOBRA value ignored for n 4 or 10 data18 The register TADCOBRB value ignored for n 4 or 10 func1 For n 0 to 4 or 6 to 10 The function to be called when a TGRA event occurs For n 5 or 11 The function to be called when a TGRU event occurs Specify PDL_NO_FUNC if not required func2 For n 0 to 4 or 6 to 10 The function to be called when a TGRB event occurs For n 5 or 11 The function to be called when a TGRV event occurs Specify PDL_NO_FUNC if not required func3 For n 0 3 4 6 9 or 10 The function to be called when a TGRC event occurs For n 5 or 11 The function to be called when a TGRW event occurs Specify PDL_NO_FUNC if not required func4 For n 0 3 4 6 9 or 10 The function to be called when a TGRD event occurs Specify PDL_NO_FUNC if not required data19 The interrupt priority level for TGR A to D or U to W events Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func 1 to 4 func5 For n 0 or 6 The function to be called when a TGRE event occurs Specify PDL_NO_FUNC if not required func6 For n 0 or 6 The function to be called when a TGRF even
47. fe ai Send Target Station ID 0x0A by internal polling R_SCI_Send 2 0x0A00 PDL_SCI_MP_ID_CYCLE PDL_NO_PTR 0 PDL_NO_FUNC tx_end false Send data to Target Station ID 0x0A by CPU ISR R_SCI_Send 2 PDL_NO_DATA send_data0O 0 SCI1tx while tx_end false hg oy Async MP mode data Transmission by polling F sy Send Target Station ID 0x01 by internal polling R_SCI_Send 2 0x0100 PDL_SCI_MP_ID_CYCLE PDL_NO_PTR 0 PDL_NO_FUNC Send data to Target Station ID 0x01 by polling R_SCI_Send 2 PDL_NO_DATA send_data 0 PDL_NO_FUNC void SCI1tx void tx_end true Figure 5 17 Example of SCI Transmission code in Asynchronous Multi Processor mode R20UT0084EE0004 Rev 0 04 Aug 25 2010 AS Page 5 34 KENES Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Weage Example 5 9 CRC calculator Figure 5 18 shows an example of CRC usage The payload and CRC checksum have been received from a remote unit The CRC calculator is used to check that the payload is correct Peripheral driver function prototypes include r_pdl_crc h RPDL device specific definitions include r_pdl_definitions h void main void uintl6_t cre result Configure the CRC to use the CCITT polynomial LSB first R_CRC_Create PDL_CRC_
48. highest priority This parameter will be ignored if PDL_NO_FUNC is specified for both parameters func1and func2 Return value Category Reference Remarks True if all parameters are valid and exclusive otherwise false Timer TMR R_TMR_Destroy Function R_CGC_Set must be called before any use of this function This function is an alternative to Error Not a valid result for table and R_TMR_CreateUnit If an output pin TMOn is enabled this function will disable other output functions on that pin If a callback function is specified this function will enable the relevant interrupt Please see the notes on callback function use in 6 The timing limits depend on the peripheral module clock PCLK feck MHz Equation 50 48 12 5 12 8 1 Timer resolution 20ns 20 8ns 80ns 83 3ns 125ns FS rctx 2 Periodmin TOE 40ns 41 7ns 160ns 166 7ns 250ns Srcux 2 Periodmax_cHANNEL 41 9ms 43 7ms 167 7ms 174 8ms 262ms Trog 9 Periodmax_unit 10 7s 11 2s 42 9s 44 7s 67 1s Jerar Widthmin Periodmin Widthmax_cHANNEL Periodmax CHANNEL Widthmax_unit Periodmax_ UNIT fmax frak 25 MHz 24MHz 6 25 MHz 6 MHz 4 MHz 2 MIN_CHANNEL Les 23 8 Hz 22 9Hz 5 96 Hz 5 7 Hz 3 81 Hz f From 0 0931 0 0894 0 0232 0 0224 0 0149 MINL UNIT 22 Hz Hz Hz Hz Hz If the requested period is not a multiple of the timer resolution the actual time pe
49. true Read the receive count R_DMAC_GetStatus 2 PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR amp Count 3 Count BUFFER_SIZE Count Which address was detected if status_flags amp 0x0001 0x0u for i 0 i lt Count i slave_data_storage_O slave_0O_ptr slave_data_received i slave_O_ptr if slave_O_ptr BUFFER_SIZE slave_0_ptr 0 status_flags amp 0x0002 0x0u i 0 i lt Count i slave_data_storage_l slave_l_ptr slave_data_received i slave_l_ptr if slave_l_ptr BUFFER_SIZE R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 5 53 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group amp Weagakexamplee slave_l_ptr 0 Reset the receive buffer DMAC channel R_DMAC_Control PDL_DMAC_2 DL_DMAC_SUSP D PDL_DMAC_ENABLE DL_DMAC_UPDATE_DESTINATION PDL_DMAC_UPDATI R P P PDL_DMAC_CLEAR_DREQ PDL_NO_DATA PDL_NO_ PTR sS B P P P lave_data_received UFFER_SIZE DL_NO_PTR DL_NO_PTR DL_NO_DATA reception_completed false Wait for the bus to become idle do R_IIC_GetStatus SLAVE_CHANNEL amp status_flags PDL_NO_PTR PDL_NO_PTR while status_flags amp 0x8000 Ox0u Re s
50. void Read 5 bytes from device O0xAA on channel 1 using polling R_IIC_MasterReceive 1 PDL_NO_DATA OxAA data_array 5 PDL_NO_FUNC 0 R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 170 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 5 R_IIC_MasterReceiveLast Synopsis Prototype Description Return value Category Reference Complete a DMAC or DTC based read process bool R_IIC_MasterReceiveLast uint8_t data1 Channel selection uint8_t data2 Data storage address Read one data byte with NACK and stop data1 Select channel IICn where n 0 or 1 data2 The storage location for the data byte True if all parameters are valid and the function completed otherwise false PC R_IIC_MasterReceive Remarks Program example e This function must only be used to terminate a Read process that has used the DMAC or DTC e Use R_IIC_GetStatus to determine if the transfer was successful e Please specify one byte less in Transfer Count when using with DMAC or DTC RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h volatile uint8_t data_array 5 void func void Read 1 byte on channel 1 and stop
51. 0 for 10ys operation Configure CMT channel 1 for 1kHz operation R_CMT r D E3 D Create L_CMT_FRE OouvurRTUrEH Configure CMT channel 2 using register values L_NO_FUNC R_CMT_Create 2 PD L_CMT_PCLK_DIV_32 QUE NCY Ox55AA PDI 0 L_NO_FUNC 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 2 R_CMT_CreateOneShot Synopsis Prototype Description Return value Category Reference Configure a CMT channel as a one shot event bool R_CMT_CreateOneShot uint8_t data1 Timer channel selection uint16_tdata2 Configuration selection float data3 II Period void func Callback function uint8_t data4 Interrupt priority level Set up a Compare Match Timer channel and start the timer data1 The channel number n where n 0 1 2 or 3 data2 Configure the timer The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Control the CPU during the one shot operation PDL_CMT_CPU_ON or Allow the CPU to run normally while the one shot operates Stop the CPU when the one shot timer starts PDE EMTZCRU OFF The CPU will re start when any valid interrupt occurs DMAC DTC trigger contr
52. 04 Aug 25 2010 Page 4 98 data4 4 Library Reference Brushless DC motor control settings All settings are optional If multiple selections are required use to separate each selection Brushless DC motor waveform control PDL_MTU_BDCM_ENABLE or PDL_MTU_BDCM_DISABLE Enable or disable brushless DC motor control PDL_MTU_BDCM_P_PHASE_ENABLE or PDL_MTU_BDCM_P_PHASE_DISABLE PDL MTU BDCM N_ PHASE ENABLE or PDL MTU _BDCM_N_PHASE_DISABLE Enable or disable PWM outputs on the positive phase output pins Enable or disable PWM outputs on the negative phase output pins PDL_MTU_BDCM_OPS_FB or Use input capture signals for output switch control or PDL_MTU_BDCM_OPS 000 or PDL_MTU_BDCM_OPS_001 or PDL_MTU_BDCM_OPS_010 or PDL_MTU_BDCM_OPS_011 or PDL_MTU_BDCM_OPS 100 or PDL_MTU_BDCM_OPS 101 or PDL_MTU_BDCM_OPS_110 or PDL_MTU_BDCM_OPS_ 111 Set the outputs according to table 17 41 in the hardware manual data5 General control settings All settings are optional If multiple selections are required use to separate each selection Interrupt skipping control PDL_MTU_INT_SKIP_TROUGH_DISABLE or PDL_MTU_INT_SKIP_TROUGH_1 or PDL_MTU_INT_SKIP_TROUGH_2 or PDL_MTU_INT_SKIP_TROUGH_3 or PDL_MTU_INT_SKIP_TROUGH_4 or PDL_MTU_INT_SKIP_TROUGH_5 or PDL_MTU_INT_SKIP_TROUGH 6 or PDL_MTU_INT_SKIP_TROUGH 7 Disable interrupt skipping or
53. 25 2010 Sane RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 10 Bus Controller Driver The driver functions support the control of the external bus providing the following operations 1 2 Configuration of the controller Configuration of the eight address space areas Disabling an area that is not required Controlling the bus controller Reading the status of the controller R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 2 10 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 11 DMA Controller Driver The driver functions support the control of the Direct Memory Access DMA controller providing the following operations 1 Configuration for use including e Access to all control bits e Automatic interrupt control 2 Disabling DMA channels that are no longer required and enabling low power mode 3 Control of one or more channels 4 Reading the status and operation registers of a channel R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 2 11 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 12 External DMA Controller Driver R20UT0084EE0004 Rev 0 04 Aug 25 2010 Saal
54. 3 or 5 to 6 PDL_DTC_TRIGGER_TXI5 or PDL_DTC_TRIGGER_TXI6 or PDL_DTC_TRIGGER_ICRXIO or PDL_DTC_TRIGGER_ICRXI1 or Receive buffer full on 1 C channel n n 0 to 1 PDL_DTC_TRIGGER_ICTXIO or PDL_DTC_TRIGGER_ICTXI1 Transmit buffer empty on I C channel n n 0 to 1 data2 The start address of the transfer data area It must be a multiple of 4 For short address mode 12 bytes are required to store the transfer data For full address mode 16 bytes are required data3 The source start address The valid range depends on the address mode short or full data4 The destination start address The valid range depends on the address mode short or full data5 The number of transfers to take place For normal or block mode valid between 0 and 65535 0 65536 transfers For repeat mode valid between 0 and 255 0 256 transfers data6 The block size for each transfer Valid between 0 and 255 0 256 units Ignored in normal or repeat mode True if all parameters are valid and exclusive otherwise false Category Data Transfer Controller Reference R_DTC_Set R_DTC_Control Remarks e If address increment or decrement is selected the address changes according to the number of bytes 1 2 or 4 in each transfer Before calling this function call RLDTC_Set e Call this function before configuring the peripherals that will be involved in the data transfer
55. 8or X X 4X41 PDL_CRC_POLY_CRC_16 or x4 x4 x72 44 PDL_CRC_ POLY CRC CCITT X6 X X5 1 Bit order PDL_CRC_LSB_FIRST or PDL_CRC_MSB_FIRST Select LSB or MSB first operation Return value True if all parameters are valid and exclusive otherwise false Functionality CRC References Remarks None Program example RPDL definitions include r_pdl_crc h RPDL device specific definitions include r_pdl_definitions h void func void Set up the CRC in 8 bit mode with LSB first R_CRC_Create PDL_CRC_POLY_CRC_8 PDL CRC GSB FIRST R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 157 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Laban Reierenc 2 R_CRC_Destroy Synopsis Shut down the CRC calculator Prototype bool R_CRC_Destroy void No parameter is required Description Put the CRC calculator into the Power down state with minimal power consumption Return value True Category CRC Reference R_CRC_Create Remarks e None Program example RPDL definitions include r_pdl_crc h RPDL device specific definitions include r_pdl_definitions h void func void Shut down the CRC R_CRC_Dest roy R20U
56. AN6 PDL_ADC_10 CHANNELS _OPTION_4 Single mode For unit 0 channel AN3 For unit 1 channel AN7 Scan mode For unit 0 channels ANO AN1 AN2 and AN3 For unit 1 channels AN4 AN5 AN6 and AN7 R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 190 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Description 2 2 e Trigger selection 4 Library Reference R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 191 PDL_ADC_10_TRIGGER_SOFTWARE or Software trigger PDL_ADC_10_TRIGGER_MTU0O_MTU4_CMIC_Aor Compare match input capture A signal from MTUO to MTU4 PDL_ADC_10_TRIGGER_TMRO_CM_A or Compare match A signal from TMR channel 0 PDL_ADC_10_TRIGGER_ADTRGO or PDL_ADC_10 TRIGGER_ADTRG1 or ADTRGO pin valid for unit 0 only ADTRG1 pin valid for unit 1 only PDL_ADC_10_TRIGGER_MTUO_CMIC or A signal from MTU channel 0 For unit 0 compare match input capture A For unit 1 compare match input capture B PDL_ADC_10_TRIGGER_MTU6_MTU10_CMIC_Aor Compare match input capture A signal from MTU6 to MTU10 PDL_ADC_10_ TRIGGER_MTU4_CM or PDL_ADC_10_ TRIGGER_MTU10_CM Compare match signal from MTU channel 4 Compare match signal from MTU channel 10 Data alignment selection PDL_ADC_10_DATA_ALIGNMENT_LEFT or PDL_ADC_10_DAT
57. Description Read data from the backup registers data1 The storage area for the data read from the backup area data2 The number of bytes to be read from the backup area Valid from 1 to 32 Return value True if all parameters are valid otherwise false Functionality Low Power Consumption control registers References R_LPC_WriteBackup Remarks rrul i R_PDL_LPC_BACKUP_AREA_SIZE specifies the number of bytes that are available Program example RPDL definitions include r_pdl_lpc h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t data_to_restore R_PDL_LPC_BACKUP_AREA SIZE Read data from the backup registers R_LPC_ReadBackup data_to_restore R_PDL_LPC_BACKUP_AREA_ SIZE R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 47 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 5 R_LPC_GetStatus Synopsis Prototype Description Return value Functionality References Remarks Program example Read the status flags bool R_LPC_GetStatus uint16_t data Data pointer Read the Deep Standby Interrupt Flag and Reset Status data The status flags shall be stor
58. E E E Program example RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h void func void Select I C mode at 100kHz 100ns rise and fall times R_IIC_Create 0 PDL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA 100E3 100 lt lt 16 100 Select I C mode with two slave addresses R_IIC_Create 1 PDL_IIC_MODE_IIC PDL_IIC_SLAVE_0O_ENABLE 7 PDL_IIC_SLAVE_1_ENABLE_7 0x0020 0x0056 PDL_NO_DATA 100E3 300 lt lt 16 200 R20UT0084EE0004 Rev 0 04 Aug 25 2010 a 2 Page 4 165 a ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 R_IIC_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Disable an C channel bool R_IIC_Destroy uint8_t data Channel selection Shut down the selected 1 C module data Select channel IICn where n 0 or 1 True if the parameter is valid otherwise false PC R_IIC_Create The IPC module is put into the power down state RPDL definitions include r_pdl_iic h RPDL device specific de
59. Group A ibrar Reteenes 6 R_lIO_PORT_Compare Synopsis Check the pin states on an I O port Prototype bool R_IO_PORT_Compare uint16_t data1 Input port or port pin selection uint8_t data2 Comparison value void func Function pointer Description Read the input state of an I O port or I O port pin and call a function if a match occurs data1 Use either one of the following definition values from 4 2 3 One port definition or e One port pin definition data2 The value to be compared with Between 0x00 and OxFF for a port 0 or 1 for a pin func The function to be called if a match occurs Return value True if the parameters are valid otherwise false Functionality I O port References R_IO_PORT_Set Remarks e Ifan invalid port or pin is specified the operation of the function cannot be guaranteed The input buffer for the specified port or pin must be switched on see R_IO_PORT_Set Program example RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void IoHandlerl void IoHandler2 void func void Call function IoHandlerl if port pin P05 is high R_IO_PORT_Compare PDL_IO_PORT_0_5 1 ToHandlerl i Call function IoHandler2 if port 6 reads as 0x55 R_IO_PORT_Compare PDL_IO_PORT_6 0x55 ToHandler2 i R20UT0084
60. Hinge line 5 39 3 Repeated Startec riein ieii inasinta NEAN KENAA ANENE E ENN AENEA NAE Ea A denen 5 40 5 10 2 Master mode with DMAC 0000 cceceeececcce cece ee eeee cee eeaeceeeee eee caacaeceeeeeegsneaeaeceeeeeseeeessnaeeeeeeeess 5 41 5 10 3 Master mode With DTC reniei aa ce aeee cece Ee E i a aaia aa aaa a a an 5 45 5 10 4 Slave Modein ae eae aa eaa a a a ade tan iaa duvide ee aa a a 5 49 5 10 5 Slave mod with DMAC coii a eap eaaa a aa a aiaa 5 51 5 11 10 bit Analog to Digital Converter cececcccecccceeeeeeeeeeceeeeeeeeeeeeaaeceeeeeeeeeesecaeaeseeeeesetennieaeeeeeeeeees 5 56 6 1 Interrupts and processor MOE ccceceeeeeeeecee cece cece eeeeeeaaeeeee ceed eecaaaeceeeeeeesecaaaaaeaeeeeeeeeesecnieeeeeeeeeees 6 1 6 2 Interrupts and DSP instructions cccceeecsece cece ee eeceeeae cece eeeeeeeeecaaeaeeeeeeesescaeaeeeeeeeeesecnieeeeeeeeeeess 6 1 Revision History Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 1 Introduction 1 Introduction The Renesas Peripheral Driver Library RPDL is a unified API for controlling the peripheral modules on the microcontrollers made by Renesas Electronics Renesas Peripheral Driver Library Peripherals supported by the RPDL Target MCU Figure 1 1 System configuration with all peripherals supported by RPDL User application Renesas Peripheral Dr
61. If no callback function is specified this function waits for the CMIB flag to indicate that the one shot time delay is complete If the timer s control registers are directly modified by the user this function may lock up A callback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed The timer period limits depend on the peripheral module clock PCLK fecik MHZ Equation 50 48 12 5 12 8 1 Tmin 20ns 20 83ns 80ns 83 3ns 125ns Jrcrx 9 Tmax_CHANNEL 41 9ms 43 7ms 167 7ms 174 8ms 262ms E roz 22 Tmax_uniT 10 7s 11 2s 42 9s 44 7s 67 1s Trax include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Output a pulse and wait for 40ms R_TMR_CreateOneShot PDL_TMR_TMRO PDL_TMR_OUTPUT_ON 40E 3 PDL_NO_FUNC 0 R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 121 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Grou P P 4 Library Reference 6 R_TMR_Destroy Synopsis Disable a TMR timer unit Prototype bool R_TMR_Destroy uint8_t data Unit selection Description Shut down a TMR timer unit data The timer unit n where n 0 or 1 Unit 0 comprises channels TMRO an
62. P4 PDL IO PORT 4 2 Portpin P42 PDL_IO_PORT_4 3 Port pin P43 PDL_IO PORT 44 Port pin P44 PDL_IO_PORT_4 5 Port pin P4s PDL_IO PORT_4 6 Portpin P4g PDL_IO_PORT_4 7 Port pin P4 PDL IO PORT 5 0 Portpin P5o PDL IO PORT 5 1 Port pin P54 PDL_IO_ PORT 5 2 Port pin P52 PDL_IO_PORT_5 3 Port pin P53 PDL_IO PORT 5 4 Port pin P54 PDL_IO_PORT_5 5 Port pin P5s PDL_IO PORT_5 6 Portpin P5g PDL_IO_PORT_5 7 Port pin P57 PDL_IO_PORT_6_0_ Port pin P6o PDL_IO_PORT 61 Port pin P6 PDL_IO_PORT_6 2 Portpin P62 PDL_IO_PORT_6 3 Port pin P63 PDL_IO PORT 6 4 Port pin P64 PDL_IO_PORT_6_5 Port pin P6s PDL_IO PORT 6 6 Portpin P65 PDL_IO_PORT_6_7 Port pin P67 PDL_IO_PORT_7_0_ Port pin P7o PDL_IO_PORT_7 1 Port pin P7 PDL_IO PORT 7 2 Portpin P72 PDL_IO_PORT_7_3 Port pin P73 PDL_IO_PORT_7 4 Port pin P74 PDL_IO_PORT_7_5 Port pin P75 PDL_IO PORT 76 Portpin P7 PDL_IO_PORT_7_7 Port pin P77 PDL_IO_ PORT 8 0 Portpin P8o PDL_IO_PORT_8 1 Port pin P84 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Sar RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference PDL_IO PORT 8 2 Portpin P82 PDL_IO PORT 8 3 Port pin P8 PDL_IO PORT_8 4 Portpin P84 PDL_IO_PORT_8 5 Port pin P8 PDL_IO
63. PDL_PPG_PO1 PDL_PPG_PO2 PDL_PPG_PO3 PDL_PPG_PO4 PDL_PPG_POS5 PDL_PPG_PO6 PDL_PPG_PO7 PDL_PPG_PO8 PDL_PPG_PO9 PDL_PPG PO10 PDL_PPG_PO11 PDL_PPG PO12 PDL_PPG PO13 PDL_PPG PO14 PDL_PPG_PO15 Group 0 Group 1 Unit 0 Group 2 Group 3 PDL_PPG PO16 PDL_PPG_PO17 PDL_PPG PO18 PDL_PPG_PO19 PDL_PPG PO20 PDL_PPG_PO21 PDL_PPG PO22 PDL_PPG PO23 PDL_PPG PO24 PDL_PPG PO25 PDL_PPG PO26 PDL_PPG_PO27 PDL_PPG PO28 PDL_PPG PO29 PDL_PPG_PO30 PDL_PPG_PO31 Group 4 Group 5 Unit 1 Group 6 Group 7 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Poe RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Description 2 2 data2 Operation control 4 Library Reference If multiple selections are required use to separate each selection e Output trigger selection PDL_PPG_TRIGGER_MTUO or PDL_PPG_TRIGGER_MTU1 or PDL_PPG_TRIGGER_MTU2 or PDL_PPG_TRIGGER_MTU3 or Select Compare Match on MTU channel 0 to 3 as the output trigger PDL_PPG_TRIGGER_MTU6 or PDL_PPG_TRIGGER_MTU7 or PDL_PPG_TRIGGER_MTU8 or PDL_PPG TRIGGER _MTU9 e Non overlap control Select Compare Match on MTU channel 6 to 9 as the output trigger valid only for groups 4 to 7 PDL_PPG_NORMAL or PDL_PPG_NON
64. PDL_SPI_DIV_8 Use the bit rate specified for R_SPl_Create 1 2 4 or 8 SSL assertion PDL_SPI_ASSERT_SSLO or PDL_SPI_ASSERT_SSL1 or PDL_SPI_ASSERT_SSL2 or PDL_SPI_ASSERT_SSL3 The SSL pin to be asserted during the frame transfer Ignored in Slave mode SSL negation PDL_SPI_SSL_NEGATE or PDL_SPI_SSL_KEEP Negate or retain the SSL signal after the frame transfer Ignored in Slave mode Frame data length PDL_SPI_LENGTH_8 or PDL_SPI_LENGTH_9 or PDL_SPI_LENGTH_10 or PDL_SPI_LENGTH_11 or PDL_SPI_LENGTH_12 or PDL_SPI_LENGTH_13 or PDL_SPI_LENGTH_14 or PDL_SPI_LENGTH_15 or PDL_SPI_LENGTH_16 or PDL_SPI_LENGTH_20 or PDL_SPI_LENGTH_24 or PDL_SPI_LENGTH 32 The number of bits in the frame transfer If a buffer size of 64 bits was selected when R_SPI_Create was called the number of bits must not exceed 16 Data transfer format PDL_SPI_MSB_FIRST or PDL_SPI_LSB_FIRST Select least or most significant bit first 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Description 2 2 data4 4 Library Reference Extended timing control If multiple selections are required use to separate each selection The default settings are shown in bold For Slave mode select PDL_NO_DATA Extended timing selection PDL_SPI_CLOCK_DELAY_1 or PDL_SPI_CLOCK_DELAY_EX
65. PORT 8 6 Portpin P8s PDL_IO PORT_9 0 Port pin P9 PDL_IO PORT_9 1 Port pin P94 PDL_IO PORT9 2 Portpin P92 PDL_IO PORT_9 3 Port pin P93 PDL_IO PORT 9 4 Port pin P94 PDL_IO_PORT_9 5 Port pin P9s PDL_IO PORT9 6 Port pin P PDL_IO PORT_9 7 Port pin P97 PDL_IO PORT_A_0 Port pin PAo PDL_IO PORT_A_1 Port pin PA PDL_IO PORTA 2 Port pin PAs PDL_IO_PORT_A 3 Port pin PA3 PDL_IO PORTA 4 Port pin PA PDL_IO PORT A 5 Port pin PAs PDL_IO PORT_A 6 Port pin PAs PDL_IO_PORT_A 7 Port pin PA7 PDL_IO PORT_B_O Port pin PBo PDL_IO PORT_B_1 Port pin PB PDL_IO PORT_B 2 Port pin PB2 PDL_IO PORT B 3 Port pin PBs PDL_IO PORT_B 4 Port pin PB PDL_IO PORT B_5 Port pin PBs PDL_IO PORT_B 6 Port pin PBe PDL_IO PORT _B 7 Port pin PB PDL_IO PORT_C_0 Port pin PCo PDL_IO_PORT_C_1 Port pin PC PDL_IO PORT_C 2 Port pin PC2 PDL_IO PORT_C 3 Port pin PC3 PDL_IO PORT_C 4 Port pin PC PDL_IO_PORT_C_5 Port pin PCs PDL_IO PORT_C 6 Port pin PCe PDL_IO_PORT_C_7 Port pin PC7 PDL_IO_PORT_D_0 Port pin PDo PDL_IO_PORT_D_1 Port pin PD PDL_IO PORT_D 2 Port pin PD PDL_IO PORT_D 3 Port pin PD PDL_IO PORT_D 4 Port pin PD PDL_IO_PORT_D_5 Port pin PDs PDL_IO PORT_D 6 Port pin PDs PDL_IO_PORT_D_7 Port pin PD7 PDL_IO PORT_E_0 Port pin PEo PDL_IO PORT _E_1 Port pin PE PDL_IO PORTE 2 Portpin PE PDL_IO_ PORT_E_ 3 Port pin PE PDL_IO PORTE 4 Portpin PE PDL_IO PORT_E_5 Port pin PEs PDL_IO PORTE 6 Port pin PEs
66. PSW register in their own code this function will lock up e For register select one of the registers listed in tables in section 4 2 2 e Write 1 to the SWINTR register to generate a software interrupt request RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void Set the IPL to 6 R_INTC_Write PDL_INTC_REG_IPL 6 Set the IR for IRQO to 0 R_INTC_Write PDL_INTC_REG_IR_ICU_IRQO 0 R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 24 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 9 R_INTC_Modify Synopsis Prototype Description Return value Category Reference Remarks Program example Modify an interrupt register bool R_INTC_Modify uint16 tdata1 Register selection uint8_t data2 Logical operation uint8_t data3 II Modification value Update the value in an interrupt register data1 e The register to be updated PDL_INTC_REG_IR_ register or Select the Interrupt Request register or PDL_INTC_REG_IER_ register or Interrupt Request Enable register or PDL_INTC_REG_IPR_ register Interrupt Priority register data2 e The logical operation to b
67. Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group A ibrar Reteenes 4 R_IO_PORT_Read Synopsis Read data from an I O port Prototype bool R_IO_PORT_Read uint16_t data1 Port or port pin selection uint8_t data2 Pointer to the variable in which the value shall be stored Description Gets the value of an I O port or I O port pin data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 The value will be between 0x00 and OxFF for a port 0 or 1 for a pin Return value If the I O port specification is incorrect false is returned otherwise true is returned Functionality I O port Reference R_IO_PORT_Set Remarks e Ifan invalid port or pin is specified the operation of the function cannot be guaranteed e The input buffer for the specified port or pin must be switched on see R_IO_PORT_Set Program example RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t data Get the value of port pin P12 R_IO_PORT_Read PDL_IO_PORT_1_2 amp data i Get the value of port 4 R_IO_PORT_Read PDL_IO_PORT_4 amp data i R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 32 RENESAS
68. RIO PORT MOGI ee eheee eden teas a eE dead Ashi eas E eA E E epee 4 35 8 RAO PORT Wait aar anaa ae eet aa e aa aer oa aie even ead aate 4 36 4 2 4 Port Function Controle sarsaran eei ee aE a a EE cua teen Aa eae AE e Neat 4 37 H HRIPE URCAG seman te oem rash e E Oa Sa aa Oa e ad eich A EE 4 38 2 R RRG WiO aaeeea s E Meccan AE a E a Daa EE E 4 39 3 AE E E sa AOAN ala L R A E ss Poe E E ch E E E E O 4 40 4 2 5 MCU Operation it stine e e AE aE a ee a e aaee aaa TaN a a aeaea 4 41 DE RIMCU CONTON irsana neat cahnee a a oe at easan a a a a aane a a eaa CEEE 4 41 27 RMC GetStatus a tricep hash m a e aeaa ae ad tas sae A oa ad e AAE aE AEEA ne AEAEE 4 42 4 2 6 Low Power Consumption ccccccececeeceeceeeeeeeeeceeeaeceeeeeeeseccaeceeeeeeeeseeecaeeeeeeeeeseeeeniseeeeeeeeeees 4 43 1 RME ERT ET vets ee eae Ae ote anes Ae Mad tes SR at ceeete es 4 43 2 r IRIEL PGs Gomtrolists 5 cccectes A A ee alas eae A ee eat as Sethe ck ee deel a 4 45 3 Re EPG Witte Backup iesis o c5 e e a teases cas a aa a ra Eana aE a a aae aa eaaa ia anaa 4 46 4 PME PC REAABACKUP AEE tes T E NA 4 47 a AS o A E OET EE EEA E E A T TAE A E TE 4 48 A2 Voltage Detection Crett resosi sira torta aa anA REEERE EEE AR IEEE AREETA 4 49 4 2 8 Bus Controller aE E ET E E A EE E gts 4 50 1 REOR ET C EE A AAE E A T O E E 4 50 2 RIBSC CreateAreas as a a aea a a raa AEE a aaa a dees ae a aE E aeaa aaa Eaa a ER Ea 4 53 3 R_BSC_SDRAM_CreateArea c
69. R_LPC_ReadBackup Read from the Backup registers O1 amp OO MO PO CO DY CO N OD O1 BY Co PO CO OO NO Or BR Ph gt 0 ho gt R_LPC_GetStatus Read the status flags Voltage Detection Circuit 1 R_BSC_Create Configure the external bus controller 2 R_BSC_CreateArea Configure an external bus area Bus Controller 3 R_BSC_SDRAM_CreateArea Configure the SDRAM area 4 R_BSC_Destroy Stop the Bus Controller 5 R_BSC_Control Modify the External Bus Controller operation 6 R_BSC_GetStatus Read the External Bus Controller status flags 1 R_DMAC Create Configure the DMA controller DMA Controller 2 R_DMAC_ Destroy Disable a DMA channel 3 R_DMAC_ Control Control the DMA controller 4 R_DMAC_GetStatus Check the status of the DMA channel External DMA Controller 1 R_DTC Set Set the Data Transfer Controller options Data Transfer 2 R_DTC_Create Configure the DTC for a transfer Controller 3 R_DTC_Destroy Shutdown the Data Transfer Controller 4 R_DTC_Control Control the Data Transfer Controller R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 2 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference R_DTC_GetStatus Check the status of the Data Transfer Controller
70. Read the channel and transfer status R_IIC_GetStatus 0 amp status_flags amp TxChars PDL_NO_PTR Review the flags and transmit count to decide on the next action R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 5 37 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group amp Weageexamplee else Wait for 5ms while the EEPROM updates R_CMT_CreateOneShot E 3 DL_NO_FUNC Figure 5 20 Configure the I C channel and write 3 data bytes to the first locations R20UT0084EE0004 Rev 0 04 Aug 25 2010 Sane RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Weagekexemples 2 Reception E a A 6am A Bom Oa F Figure 5 21 The bus activity showing 4 bytes being transmitted to the EEPROM Read data from the EEPROM using polling if R_IIC_MasterReceive 0 PDL_NO_DATA EEPROM_ADDRESS data_storage 4 PDL_NO_FUNC 0 false Read the channel and transfer status R_IIC_GetStatus 0 amp status_flags PDL_NO_PTR amp RxChars di Review the flags and transmit count to decide on the next action Figure 5 22 An example of reading data from the EEPROM eee om om om Alo Figure 5 23 The bus activity showing 4 bytes being transmit
71. Specify PDL_NO_PTR if it is not required data6 For n 0 3 4 6 9 or 10 A pointer to where the TGRC register value shall be stored For n 5 or 11 A pointer to where the TGRU register value shall be stored Specify PDL_NO_PTR if it is not required data7 For n 0 3 4 6 9 or 10 A pointer to where the TGRD register value shall be stored For n 5 or 11 A pointer to where the TGRV register value shall be stored Specify PDL_NO_PTR iff it is not required data8 For n 0 or 6 A pointer to where the TGRE register value shall be stored For n 5 or 11 A pointer to where the TGRW register value shall be stored Specify PDL_NO_PTR if it is not required data9 For n 0 or 6 A pointer to where the TGRF register value shall be stored Specify PDL_NO_PTR if it is not required True if all parameters are valid and exclusive otherwise false Multi function Timer Pulse Unit e Ifthe flags are read any detection flag that has been set to 1 shall be automatically cleared to 0 by this function R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 101 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group dieing Resrenes Program example RPDL definitions include r_pdl_mtu h RPDL device specific definitions include r_pdl_definitions h uint8_t Flags uint General_A uint1 Gene
72. Synchronous Maximit m 6 250 000 1 562 500 4 000 000 1 000 000 External 8 333 333 2 083 333 5 333 333 1 333 333 Smart card Internal Minimum 3 0 75 2 0 5 Maximum 781 250 195 313 500 000 125 000 Program example RPDL definitions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h void func void Configure SCIO for asynchronous 8N1 38400 baud R_SCI_Create 0 PDL_SCI_8N1 38400 1 Configure SCI1 for asynchronous 8N1 register values supplied R_SCI_Create 1 PDL_SCI_8N1 PDL_SCI_PCLK_DIV_1 PDL_SCI_CYCLE_BIT_16 115200 amp OxOOFFFOO 0x50 1 R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 147 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Dbia Reiben 3 R_SCI Destroy Synopsis Shut down a SCI channel Prototype bool R_SCI_Desiroy uint8_t data Channel selection Description Stop data flow and shutdown the selected SCI channel data Select channel SCIn where n 0 to 6 but not 4 Return value True if all parameters are valid otherwise false Category SCI Reference R_SCl_Create Remarks e The SCI channel is put into the power down state Program example RPDL definitions include
73. The value to be used for the modification Return value True if a valid register is specified otherwise false Functionality PFC registers References R_PFC_Read Remarks The PFC registers are modified by other driver functions Take care to not overwrite existing settings Program example RPDL definitions include r_pdl_pfc h RPDL device specific definitions include r_pdl_definitions h void func void Set bit 7 in PFDMTU to 1 R_PFC_Modify PDL_PFC_PFDMTU PDL_PFC_OR 0x80 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 40 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group A ibrar Reiereno 4 2 5 MCU operation 1 R_MCU_Control Synopsis Control the operation of the MCU Prototype bool R_MCU_Control uint8_tdata Control options Description Modify the MCU control registers data Select the operation states If multiple selections are required use to separate each selection Specify PDL_NO_DATA to use the defaults e On chip ROM control PDL_MCU_ROM_ENABLE or PDL_MCU_ROM_DISABLE Enable or disable the on chip ROM e On chip RAM control PDL_MCU_RAM_ENABLE or PDL_MCU_RAM_DISABLE Enable or disable the on chip RAM Return value True if a valid
74. Write data to a master device Interface R_IIC_Control C channel control R_IIC_GetStatus Read the status for an C channel R_SPI_Create Configure an SPI channel R_SPI_Destroy Shutdown an SPI channel Serial Peripheral R_SPI_Control Control an SPI channel R_SPl_Command Configure an SPI command R_SPI_Transfer Transfer data over an SPI channel OO O1 BH CO NO gt CO CO NJ OD O1 BY Co PO BY OO DO Ni OD On AI Go Po a R_SPI_GetStatus Check the status of an SPI channel 12 bit Analog to R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 3 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference Digital converter 10 bit Analog to Digital converter R_ADC_10_ Create Configure an ADC unit R_ADC_10_Destroy Shut down an ADC unit R_ADC_10_Control Start or stop an ADC unit R_ADC_ 10 Read Read the ADC conversion results 10 bit Digital to Analog converter R_DAC_10_Create Configure the 10 bit DAC module R_DAC_10_Destroy Disable a DAC channel WIM AVN gt R_DAC 10 Write Write data to a DAC channel R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 4 7tENESAS Under development Preliminary Specification Specifications i
75. acne cede eet adel ee del ei aed oleae i 4 9 4 2 2 Interrupt Control Unit fcssi ao i ties dee ei ee 4 10 1 R_INTC_CreateExtlnterrupt ii er a a a aa a E aeaa aa ae 4 12 2 R_INTC_CreateSoftwarelnterrupt 2 0 0 2 ccceceeececne cece ee eeeeceaececeeeeesecaaaeceeeeeeeeseseccueaeeeeeerseeeeaeees 4 14 3 R_INTC_CreateFastlnterrupt c ccccccccceceeccceceeeeeceeeeeaeeeceeeeeseseaeaeeeeeeeeesecqanaeceeeeeeeesensneaeees 4 15 4 R_INTC_CreateExceptionHandlerS cccccccceceeeeeeecceeceeeeeceeeeaneaeceeeeeeesessanaeceeeeeesseenineeeees 4 19 5 R2INT Cs Controle xtlnterruptsectacecses te aeae n a e acheter a cade adtee tht aasa aasa 4 20 6 RINT GCs GetExtintermuptStatusscrs 2 ssc ea dhe A a a aa aaa a aaa eaa aSa 4 22 T RINTC Read a aeaa a a a a aaa aa aaa aa aa a aa ae eaa EEA 4 23 8 RINE C Wie ai a ra tats hell a a a a de etd aa e aas 4 24 9 RAIN TEC Modify eara a a aaa a aa a a eaaa aaa aaae eaa aaa iaia 4 25 AD N VLE E 0 E A E AA A A E A E TE 4 26 1 RAO PORT Setit aeea aaia aa e e aa a bata a aa esa aa eaa eaae Ea 4 28 2yr RIO PORT ReadGontrolei Sasna aea a aaa a a aasa 4 29 3 gt RIO PORT Modify Controls h a a a a aa tac a a Aaa a peed RANA 4 30 4 RIO PORT Read ea etek aa a aa aa e a aE aa aa a a cache AA aeaaea aa 4 32 5 RAIOSPOR Te Write ent herne aee ap a eeter redea A Rae aare a aA E a EEE aaan aate 4 33 6 RIO PORT Compare reissen naa a iaae a eaea e aeea Aena a AR EEL Ara En ae TEAS 4 34 T
76. before any use of this function 4 Library Reference feck MHz Equation 50 48 12 5 12 32 8 8 Tmin Po 160ns 166 67ns 640ns 666 67ns 250ns 1us Soctx 9 Tmax 671ms 699ms 2 68s 2 79s 1 05s 4 19s Jre If the requested period is not a multiple of the minimum period the actual time period will be more than the requested time period Program example RPDL definitions include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h void func void Use CMT channel 0 for a lms pause R_CMT d r E 3 D owrool R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 134 CreateOneShot L_NO_FUNC 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Grou P P 4 Library Reference 3 R_CMT_Destroy Synopsis Disable a CMT unit Prototype bool R_CMT_Destroy uint8_t data Unit selection Description Shut down a CMT unit data The timer unit n where n 0 or 1 Unit 0 comprises channels CMTO and CMT1 Unit 1 comprises channels CMT2 and CMT3 Return value True if the unit selection is valid otherwise false Category Compare Match Timer Reference R_CMT_Create Remarks e The timer unit is put into the stop state to reduce power consum
77. before configuring any ADC unit R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 2 27 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 28 10 bit Digital to Analog Converter Driver The driver functions support the use of the DAC module providing the following operations 1 Configuring a channel for use including e Independent or linker operation e Data alignment 2 Disabling channels that are no longer required and enabling low power mode 3 Writing data to a channel R20UT0084EE0004 Rev 0 04 Aug 25 2010 Saas RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Airing Resrsnes 3 Types and definitions 3 1 Data types This section describes the data types used in this library For details about the setting values refer to the section 4 2 Description of Each API The header files stdint h and stdbool h are included with the Renesas RX compiler Table 1 Data types Type Defined in Description Range bool stdbool h Boolean 0 false to 1 true float C Floating point 32 bits to uint8_t Unsigned 8 bits 0 to 255 uint16_t saint h Unsigned 16 bits 0 to 2o int32_t i Signed 32 bits 2 gt to2 1 uint32_t Unsigned 32 bits O24 3 2 Genera
78. control PDL_LPC_IO_ SAME or Select whether IO port retention is cancelled when deep software PDL_LPC_IO_DELAY standby mode is ended or when CPU operation has resumed Deep software standby cancel control PDL_LPC_CANCEL_IRQO_DISABLE or PDL_LPC_CANCEL_IRQO_FALLING or PDL_LPC_CANCEL_IRQO_RISING Prevent or allow an edge on the IRQO A pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ1_DISABLE or PDL_LPC_CANCEL_IRQ1_FALLING or PDL_LPC_CANCEL_IRQ1_RISING Prevent or allow an edge on the IRQ1 A pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ2_DISABLE or PDL_LPC_CANCEL_IRQ2_FALLING or PDL_LPC_CANCEL_IRQ2 RISING Prevent or allow an edge on the IRQ2 A pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ3_DISABLE or PDL_LPC_CANCEL_IRQ3_FALLING or PDL_LPC_CANCEL_IRQ3_ RISING Prevent or allow an edge on the IRQ3 A pin to cancel deep software standby mode PDL_LPC_CANCEL_NMI_DISABLE or PDL_LPC_CANCEL_NMI_FALLING or PDL_LPC_CANCEL_NMI_RISING Prevent or allow an edge on the NMI pin to cancel deep software standby mode PDL_LPC_CANCEL_LVD_DISABLE or Prevent or allow the Voltage Detection Circuit to PDL_LPC_CANCEL_LVD_ENABLE cancel deep software standby mode PDL_LPC_CANCEL_RTC_DISABLE or Prevent or allow the Realtime Clock to cancel deep PDL_LPC_CANCEL_RTC_ENABLE software standby mode PDL_LPC_CANCEL_USB_DISABLE or Prevent or allow the USB Suspend Res
79. count Valid only for n 0 or 6 Input capture output compare control for register TGRD PDL_MTU_D_OC DISABLED or PDL_MTU_D_OC LOW or PDL_MTU_D_OC_LOW_CM HIGH or PDL_MTU_D_OC_LOW_CM_INV or PDL_MTU_D_OC_HIGH_CM_LOW or PDL_MTU_D_OC HIGH or PDL_MTU_D_OC_HIGH_CM_INV or MTIOCnD output disabled MTIOCnD output low MTIOCnD initial output low goes high at compare match MTIOCnD initial output low toggles at compare match MTIOCnD initial output high goes low at compare match MTIOCnD output high MTIOCnD initial output high toggles at compare match PDL_MTU_D_IC_RISING_EDGE or PDL_MTU_D_IC_FALLING EDGE or PDL_MTU_D_IC_BOTH EDGES or Input capture at MTIOCnD rising edge Input capture at MTIOCnD falling edge Input capture at MTIOCnD both edges PDL_MTU_D_IC_COUNT Input capture at channel n 1 up count or down count Valid only for n 0 or 6 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Description 7 8 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 89 data8 4 Library Reference Configure the input capture compare match control for general registers TGRU TRGV and TGRW Valid for n 5 or 11 The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Input capture compare match control for regist
80. count pointer Return status flags and current channel registers data1 The start address of the transfer data area Ignored if parameters data3 data4 and data5 are all PDL_NO_PTR data2 The status flags shall be stored in the following format Specify PDL_NO_PTR if the status flags are not required b15 b14 b8 b7 bO 0 Idle 1 A transfer is in progress 0 The trigger vector valid only when b15 1 data3 Where the current source address shall be stored Specify PDL_NO_PTR if it is not required data4 Where the current destination address shall be stored Specify PDL_NO_PTR if it is not required data5 Where the current transfer count shall be stored Specify PDL_NO_PTR if it is not required data6 Where the current block size count shall be stored Specify PDL_NO_PTR if it is not required True if all parameters are valid and exclusive otherwise false Data Transfer Controller R_DTC_Create e The start address of the transfer data area is the same as that declared in R_DTC_Create R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 80 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Jiban Rewrsnes Program example RPDL definitions include r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h Declared in the R_DTC_Crea
81. cs7_location_16 uintl6_t 0x01000000ul Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Configure the bus controller R_BSC_Create PDL BSC CS2 B 0 PDL_BSC_ERROR_ILLEGAL_ADDRESS__ E PDL BSC 5 Usage Examples ERROR_TIM BSC_error_handler 5 Configure area CS7 R_BSC_CreateArea 7 PDL BSC_WRITE_SINGL OP eS Oo fF oo eo 8 0 oO 6 6 i Configure area CS1 R_BSC_CreateArea R20UT0084EE0004 Rev 0 04 Aug 25 2010 7tENESAS Page 5 6 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Usage Example 1 PDL_BSC_WIDTH_8 PDL_BSC_WRITE 0 oOoOoroOoOO0O0OROO0OO0O0OO0OOOO Initialise the system clocks and enable the BCLK output R_CGC_Set 12 5E6 100E6 50E6 25E6 PDL_CGC_BCLK __ i Write to external areas cs7_location_16 OxAA55 csl_location_8 OxAA Disable area CS1 R_BSC_Destroy 1 Figure 5 3 Example of Bus Controller use R20UT0084EE0004 Rev 0 04 Aug 25 2010 2 ENESAS Page 5 7 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group
82. default setting is shown in bold May also specify PDL_NO_DATA to use the defaults PDL_SCI_DMAC_DTC_TRIGGER_DISABLE or PDL_SCIl_DMAC_TRIGGER_ENABLE or PDL_SCI_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC when a data byte is received e ID cycle indication for Multi processor mode Set this option only when user wants to receive ID in Multi processor mode For Data cycle in Multi processor mode do not set this option Specify that it is the ID cycle for PDL_SCI_MP_ID_CYCLE Multi processor mode The upper 8 bits will be used as ID e Station ID of the receiving device The valid range is from 0 to 255 Must be specified together with PDL_SCI_MP_ID_CYCLE Not required for Data cycle in Multi processor mode b15 b8 b7 b0 Station ID PDL_SCI_MP_ID_CYCLE data3 The start address of the storage area for the expected data Specify PDL_NO_PTR if no data shall be processed by this function e g if the DMAC or DTC shall be used to process the received data or for ID cycle in Multi processor mode data4 The number of bytes that must be received before the function completes or the callback function is called Specify 0 for ID cycle in Multi processor mode func1 The function to be called when the number of received bytes reaches the threshold number While the receive operation is in progress R_SCI_GetStatus can be used to find out how many bytes have been recei
83. ett heaeiestans tele aa aaa aa a aa aaaea aA 4 171 6 RallGs SIAVEMONMOR 2 te ea r a etic a aa a a aa a a aaa sitar a caste nac eens 4 172 T CRAC Sl veSend ean nei aaa a aaa ea aaa a a a a E a ENE 4 174 8 RoC CONT Ol aa a a r aa aae a a aa Aa aa a a A cobs Na 4 175 9 RoC Gets US e a tt eke a aaa aa a aa ea a aA a anaa ala 4 176 4 2 23 Serial Peripheral IntertaGe n re aaaea aa aaa a aa aa ae aa aaa aa anaE aiea 4 178 Wy RYSPISC Te E E E E E E E E E E E 4 178 A R SPFILEDESIO y ea E E E date 4 181 3 ROP COMO e acs a aE a aa a aa ae aAa A aa a aa aa a a aa 4 182 4 ReSPleCommands 4 3 23 en a a aa a aaa aa aaa ea aeS a Ea ea 4 183 5 EES ra E D E EE E A A E E E E ttbdsabtant hh edd aa oes 4 186 ST OES o EE mA EEE EE Ee O E E A E A E cud deesthassitel ahiterdabusttehs 4 188 4 2 24 12 bit Analog to Digital Converter eccceeeceeeeeeeeeeeeceeeeeeeeeeeeaeeeseeeaeeeseeeeeeeseeeaeeeeeeaaeees 4 189 4 2 25 10 bit Analog to Digital Converter ecceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeaeeeseneeeeseeeaeeeteeanees 4 190 1 READE 10 Create s irie eea ean neces idee ans aa a aae aaa EAE aa aa Ee aaa adaa Ea aaae e na 4 190 2 R ADC VO DesStOy eseme ere aaa eL ys p ee AEE Ea aaa aE E iael 4 194 3 RADC AO CONTON irona andaa rs ear a Aaaa E ea Gaa ae ae A Aea iea A aae a 4 195 4 RADC 10 Read nen a a Assent cartes ONENE Aae e ees a a A aan a Ee 4 196 4 2 26 10 bit Digital to Analog Converter seaesssesssssesssrresnrnesierrnesnnnn
84. ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid exclusive and achievable otherwise false PC R_IIC_Create R_IIC_GetStatus R_IIC_Control R_IIC_MasterReceiveLast R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 169 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Remarks Program example 1 i vo vo 4 Library Reference If a callback function is specified reception interrupts are used Please see the notes on callback function usage in 6 If the previous transfer did not issue a Stop condition a Repeated Start condition shall be generated The last byte to be read shall be completed with a NACK signal If no callback function is specified this function will operate in polling mode The status flags will be used to manage the data reception If the I C channel s control registers are directly modified by the user this function may lock up If an error occurs during this polling process the function will terminate Use R_IIC_GetStatus to determine if the transfer was successful False will be returned if the DMAC channel has not been allocated using R_DMAC_ Create RPDL definitions nclude r_pdl_iic h RPDL device specific definitions nclude r_pdl_definitions h latile uint8_t data_array 5 id func
85. or PDL_SPI_PARITY_ODD Disable or enable the addition of the parity bit data4 Extended timing control If multiple selections are required use to separate each selection All items are optional Specify PDL_NO_DATA if not required Extended clock delay PDL_SPI_CLOCK_DELAY_2 or PDL_SPI_CLOCK_DELAY_3 or PDL_SPI_CLOCK_DELAY_4 or PDL_SPI_CLOCK_DELAY_5 or PDL_SPI_CLOCK_DELAY_6 or PDL_SPI_CLOCK_DELAY_7 or PDL_SPI_CLOCK_DELAY 8 The number of bit clock periods between the assertion of the SSL pin and the start of RSPCK oscillation Ignored in Slave mode Extended SSL negation delay PDL_SPI_SSL_DELAY_2 or PDL_SPI_SSL_DELAY_3 or PDL_SPI_SSL_DELAY_4 or PDL_SPI_SSL_DELAY_5 or PDL_SPI_SSL_DELAY_6 or PDL_SPI_SSL_DELAY_7 or PDL_SPI_SSL_DELAY 8 The number of bit clock periods between the end of RSPCK oscillation and the negation of the active SSL pin Ignored in Slave mode Extended next access delay PDL_SPI_NEXT_DELAY_2 or PDL_SPI_NEXT_DELAY_3 or PDL_SPI_NEXT_DELAY_4 or PDL_SPI_NEXT_DELAY_5 or PDL_SPI_NEXT_DELAY_6 or PDL_SPI_NEXT_DELAY_7 or PDL_SPI_NEXT_DELAY_8 The number of bit clock periods plus two cycles of the peripheral clock between the end of one frame and the start of the next frame Ignored in Slave mode 7tENESAS Under development Preliminary Specification Specifications in this prelimi
86. preliminary version are subject to change RX62N Group RX621 Group 3 R_DMAC_Control Synopsis Prototype 3 Description 1 2 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 67 Control the DMA controller bool R_DMAC_Control Channel number Control options uint8_t data1 uint16_t data2 void data3 void data4 uint16_t data5 uint16_t data6 int32_t data7 uint32_t data8 uint32_t data9 Transfer count Address offset Change the state of a DMA controller channel data1 The channel number n where n 0 to 3 data2 Control the channel operation If multiple selections are required use to separate each selection Enable suspend control Source start address Destination start address Repeat or Block size 4 Library Reference II Source address extended repeat area Destination address extended repeat area PDL_DMAC_ENABLE Enable re enable DMA transfers PDL_DMAC_SUSPEND Suspend DMA transfers Software trigger control PDL_DMAC_START or PDL_DMAC_START_RUN Start a DMA transfer Start DMA transfers until stopped Transfer end interrupt flag control PDL_DMAC_CLEAR_DTIF Clear the Transfer End flag PDL_DMAC_CLEAR ESIF Clear the Transfer Escape End flag The values to be modified PDL_DMAC_UPDATE_SOURCE Source address using parameter data3
87. project s build environment you need to a Unzip the RPDL distribution b Copy the required source header and library files into your project folder c Include the required source files d Add the driver library file to the linked files list 1 1 1 Unzip the RPDL files Double click on the file RPDL_RX62N exe to unpack the files The default location is C Renesas RPDL_RX62N 1 1 2 Copy the files into your project area Navigate to where the RPDL files were unpacked fm C Renesas RPDL_RX62N aAA File Edit Yiew Favorites Tools Help ae gt Q Back wi Ss Search Address C Renesas RPDL_RX62N v Eco D Device specific S Copy_RPDL_RX62N bat 3objects 2 76 KB 9 My Computer Double click on Copy_RPDL_RX62N bat to start the copy process ct C WINDOWS system32 cmd exe Renesas RPDL for RK62N RRG621 copy utility Please enter a number to select the device package LFBGA 176 pins TFLGA 145 pins LQFP 100 pins is 2 3 LQFP 144 pins 4 5S TFLGA 85 pins Select the device package option by pressing a number and then press Enter R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 1 2 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 1 Introduction Type the full path to the folder where you wish RPDL to be copied to and then press Enter BEE Renesas RPDL for RX62N R8621 copy utility Plea
88. register selection Data to be written to the PFC register Write the value to a PFC register data1 One of the definition values from 4 2 4 data2 The value to be written to the register True if a valid register is specified otherwise false PFC reg isters R_PFC_Read R_PFC_Modify 4 Library Reference The PFC registers are modified by other driver functions Take care to not overwrite existing settings RPDI RPDI L definitions include r_pdl_pfc h L device specific definitions include r_pdl_definitions h void func void Write data to register PFICSS R_PFC_Write PDL_PFC_PFI1CSS OxFF R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 39 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group A ibrar Renee 3 R_PFC_Modify Synopsis Modify a PFC register Prototype bool R_PFC_Modify uint8_t data1 PFC register selection uint8_t data2 Logical operation uint8_t data3 Modification value Description Write the value to a PFC register data1 One of the definition values from 4 2 4 data2 e The logical operation to be applied to the register contents PDL_PFC_AND or PDL_PFC_OR or Select between AND amp OR or Exclusive OR PDL_PFC_XOR data3
89. rere Tree 4 82 RoiM TU Oeae e aar a a aa a a aa a a a a aa a Aae ia Oaa aa aa 4 83 RiMTU DESO a a aa a errs a a a a a aaae a aa t eee reer 4 92 RiMTU Contr lChannel arisini niare aeaa a aa a a cote Laas a aaa a a aa aiaa 4 93 RIMTU Control Aitstccistitett tet a aa a a a a aa shut aaaea dead a aE 4 96 R MTU ReadGhannel aeai er a aeaa aa ara aa aaa a a aaa a aa aaa aaae E aa aat 4 100 R MTU Read UN ites rentesi om ss teens ri aae aE eE ana aeaa tes EE bata Daea ea rE Tar a Aena sE ai Eana 4 103 Port Output Enables cis fenido oaee a ea teed nen tn adesnagvendet EEESC EE Aa EAE i 4 104 Programmable Pulse Generator siesseenssrresriirsrssrrnsiirrssiennssinntunsteunentantanianaannaaaadaeaaaanaa aa 4 105 T a a E E S ET E cess EE A A EA AAN E E N AE 4 105 R PPO Destroy eseteire e la E a A AE a AEEA A a A aE 4 107 R PPG CONTO diera Aee e Aea nach eaa a ds ences od eed Se a e a aaa ares 4 109 Bit TAMER A tesia Noa eea ea i e a e a E A a e aE aAa 4 110 RTIMR Seti Sarra e teal oka E EE ra E E a E e A saree oa Main eA 4 110 RATMR GreateC hannele omoara eara a a ae Aea R aa ae A fee a aaaea a aas eaa 4 111 R IMR GreateUNit iiaeia aa e a a E a DAEA e A eee r aa Aare ee Gans 4 114 R TMRGreateP enolic sonnin anea aaa tages tien eane ocean oy EA da ah Ee aa ea ae dana Paa eae 4 117 R_TMR_CreateOneShot 20 0 cece ceececccce cece ee eeee eee aeeeeeee eee nnanet cesses segeaeaeeeeeeesesageeeeinaeeeeeeeeseeees 4 120 Re EMR DIE KEN EAEE E Anata Akg Re e
90. s Urago Exage 2 External bus SDRAM area Figure 5 4 shows an example of SDRAM bus controller usage and the procedure for transition to and recovery from self refresh mode in deep software standby mode PDL functions indlud e r_pdl_bse h include r pdl 16 portan include r pdl cge include r padl pe bh includes r pdl _inte n PDL device specific definitions include r pdl definitions h define SELF_REFRESH_SELECT 1 void BSC error_handler void void NMI_handler_lpc void void main void uint32_t sdram location 32 uint8_t statusl sdram_status uintl6_t status2 volatile uint32_t temp uint32_t i bool rtn uintl6_t status_flags Point to respective external memory areas sdram_location_32 uint32_t 0x08000000ul1 Enable control of LEDI R_IO_PORT_Set PDL_IO_PORT_0_3 PDL_IO_PORT_OUTPUT Turn OFF LEDI R_IO_PORT_Write PDL_IO_PORT_0_3 1 Configure the bus controller Select pin B for CS1 CS7 enable SDRAM pins enable error monitoring R_BSC_Create PDL_BSC_CS1_B PDL_BSC_CS2_B PDL_BSC_CS3_B PDL_BSC_CS4_B PDL_BSC_CS5_B PDL_BSC_CS6_B PDL_BSC_CS7_B PDL_BSC_SDRAM_PINS_ENABLE PDL_BSC_SDRAM_DQM1 ENABLE PDL_BSC_SDRAM_SDCLK_ENABLE PDL_BSC_ERROR_ILLEGAL_ADDRESS_ENABLE R PDL BSC_ERROR_TIME OUT_ENABLE BSC_error_handler 5
91. selection uint32_t data2 uint8_t data3 uint8_t data4 uint8_t data5 uint8_t data6 Register value Register value Register value void func Callback function void func2 Callback function void func3 Callback function uint8_t data7 Set up an 8 bit timer TMR channel data1 The channel number n where n 0 1 2 or 3 data2 Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Counter clock source selection PDL_TMR_CLK_OFF or 4 Library Reference Configuration selection II Configuration selection Interrupt priority level The clock input is disabled PDL_TMR_CLK_EXT_RISING or PDL_TMR_CLK_EXT_FALLING or PDL_TMR_CLK_EXT_BOTH or The external clock signal TMCIn is used Select rising falling or both edges detected PDL_TMR_CLK_PCLK_DIV_1 or PDL_TMR_CLK_PCLK_DIV_2 or PDL_TMR_CLK_PCLK_DIV_8 or PDL_TMR_CLK_PCLK_DIV_32 or PDL_TMR_CLK_PCLK_DIV_64 or PDL_TMR_CLK_PCLK_DIV_1024 or PDL_TMR_CLK_PCLK_DIV_8192 or The internal clock signal PCLK 1 2 8 32 64 1024 or 8192 PDL TMR CLK TMR1 OVERFLOW or PDL_TMR_CLK_TMR3_OVERFLOW or The overflow signal from TMR n 1 Valid for n 0 or 2 PDL_TMR_CLK_TMRO_CM_Aor PDL_TMR_CLK_TMR2 CM_A The compare match A signal from TMR n 1 Valid for n 1 or 3
92. set the skip count between 1 and 7 PDL_MTU_INT_SKIP_CREST_DISABLE or PDL_MTU_INT_SKIP_CREST_1 or PDL_MTU_INT_SKIP_CREST_2 or PDL_MTU_INT_SKIP_CREST_3 or PDL_MTU_INT_SKIP_CREST_4 or PDL_MTU_INT_SKIP_CREST_5 or PDL_MTU_INT_SKIP_CREST_6 or PDL_MTU_INT_SKIP_CREST_7 Disable interrupt skipping or set the skip count between 1 and 7 Dead time generation control PDL_MTU_DEAD_TIME_DISABLE or PDL_MTU_DEAD_TIME_ENABLE Disable or enable dead time generation Waveform retention control PDL_MTU_WAVEFORM_RETAIN_DISABLE or PDL_MTU_WAVEFORM_RETAIN_ENABLE Disable or enable waveform output retention Compare match clearing control PDL_MTU_CNT_CLEAR_CM_A_DISABLE or PDL_MTU_CNT_CLEAR_CM_A_ENABLE Disable or enable counter clearing on TGRA compare match Register protection PDL_MTU_ACCESS_DISABLE or PDL_MTU_ACCESS_ENABLE Prevent or allow access to the registers and counters in channels 3 and 4 n 0 or 9 and 10 n 1 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group diban Rewrsnes Description 4 4 data6 The unit registers to be modified If multiple selections are required use to separate each selection e The registers to be modified PDL_MTU_REGISTER_DEAD_TIME Update
93. status2 amp sdram_status while sdram_status 0 Start Self Refresh R_BSC_Control PDL_BSC_SDRAM_S to release IO ports R_LPC_Control PDL_LPC_IO_RELEASE JAk KKK KKK KKK KK KK In Self Refresh mode KOK KK RK KK KK KK R20UT0084EE0004 Rev 0 04 Aug 25 2010 ztENESAS Page 5 10 Under development Preliminary Specification RX62N Group RX621 Group Specifications in this preliminary version are subject to change 5 Usage Examples read SDRAM should fail temp sdram_location_32 KKK KKK KR KKK KK KK KK Exiting Self Refresh KOK OK KK KK KK OK Check the status flags dof R_BSC_GetStatus amp statusl amp status2 amp sdram_status while sdram_status 0 Stop Self Refresh do rtn R_BSC_Control PDL_BSC_SDRAM_S H ESH_DISABL while rtn false Check the status flags do R_BSC_GetStatus amp statusl amp status2 amp sdram_status hile sdram_status 0 Enable SDRAM operation R_BSC_Control PDL_BSC_SDRAM_ENABLE KR KKK KK KKK KKK KKK Out of Self Refresh mode KKK OK KK KK KK endif read SDRAM for i 0 i lt 16 1024 1024 4 i 2 if sdram_location_32 i OxAAAAAAAAu while l1 if sdram_location_32 it 1l 0x55555555u while 1 Read the status flags R_BSC_GetStatus amp statusl amp status2
94. subject to change RX62N Group RX621 Group 5 Urago Exaile 5 10 5 Slave mode with DMAC In the following example data is received using DMAC channel 2 and transmitted using DMAC channel 3 The slave will respond to one 7 bit address and one 10 bit address The same EEPROM address locations are then read out in two bursts DMAC channel 2 is used to handle the data transfer Peripheral driver function prototypes include r_pdl_iic h include r_pdl_cgc h include r_pdl_dmac h RPDL device specific definitions include r_pdl_definitions h Callback prototype void slave_event_handler void IIC application definitions define SLAVE_CHANNEL 0 define MCU_ADDRESS_UPPER 0x0100 define MCU_ADDRESS_LOWER 0x12 define MCU_ADDRESS_0 0x12 define MCU_ADDRESS_1 0x0124 define BUFFER_SIZE 10 Global variables volatile bool transmission_completed volatile bool reception_completed volatile uint8_t slave_data_received BUFFER_SIZE 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 volatile uint8_t slave_data_storage_0 BUFFER_SIZE 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Ox00 0x00 Ox00 volatile uint8_t slave_data_storage_1 BUFFER_SIZE 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 void main void uint32_t status_flags 0 uint32_t Count 0 ints2 E i uint32_
95. to be applied to the control register PDL_IO_PORT_AND or PDL_IO_PORT_OR or Select between AND amp OR or Exclusive OR PDL_IO_PORT_XOR Sia E to be used for the modification Between 0x00 and OxFF for a port 0 or 1 for a pin Return value True if all parameters are valid and exclusive otherwise false Functionality I O port References R_IO_PORT_Set R_IO_PORT_ReadControl Remarks e Ensure that the specified functions are valid for the selected port pin The data direction and input buffer registers may be modified by other driver Create functions Take care to not overwrite existing settings R20UT0084EE0004 Rev 0 04 Aug 25 2010 a RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Program example R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 31 include RPDL definitions yr _ pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Set the lower 4 bits on port P1 to output R_IO_PORT_ModifyControl PDL_IO_PORT PDL_IO_POR Ox0F ri DIRECTION PDL_IO_PORT_OR Enable the pull up on pin PA3 R_IO_PORT_ModifyControl PDL_IO_PORT_A_3 PDL_IO_PORT_PULL_UP PDL_IO_PORT_OR 1 7tENESAS 4 Library Reference Under development
96. to exit from All module clock stop mode e 1 0 port retention cancellation PDL_LPC_IO_ RELEASE Cancel the retention of I O port pin states Return value Functionality Low Power Consumption control registers References R_LPC_Create Remarks True if all parameters are valid and exclusive otherwise false Sleep mode is utilised by some peripheral drivers to turn off the CPU when required The peripheral Create functions bring modules out of the clock stop state as required The peripheral Destroy functions put modules into the clock stop state as required When All Module Clock Stop mode is cancelled the peripherals that were active when that mode was entered will be re activated Program example RPDL definitions include r_pdl_lpc h RPDL device specific definitions include r_pdl_definitions h void func void Enter deep software standby mode R_LPC_Control PDL_LPC_MODE_DEEP_SOFTWARE_STANDBY void func void Clear I O port retention R_LPC_Control PDL_LPC_IO_RELEASE R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 45 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 3 R_LPC_WriteBackup Synopsis Prototype
97. to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e ADC conversion trigger control Valid for n 0 to 4 or 6 to 10 unless stated otherwise PDL_MTU_ADC_TRIG_TGRA_ENABLE PDL_MTU_ADC_TRIG_TGRA_DISABLE or Disable or enable ADC start requests on a TGRA compare match or input capture PDL_MTU_ADC_TRIG_TROUGH_DISABLE or PDL_MTU_ADC_TRIG_TROUGH_ENABLE Disable or enable ADC start requests on a TCNT underflow Valid for n 4 or 10 in complementary PWM mode e Control ADC trigger interrupt skipping Valid for n 4 or 10 in complementary PWM mode PDL_MTU_ADC_TRIG_A_TROUGH_INT_SKIP_DISABLE or PDL_MTU_ADC_TRIG_A_TROUGH_INT_SKIP_ENABLE Disable or link interrupt skipping to ADC trigger TRGnAN on a TCNT underflow PDL_MTU_ADC_TRIG_B TROUGH _INT_SKIP_DISABLE or PDL_MTU_ADC_TRIG_B_TROUGH_INT_SKIP_ENABLE Disable or link interrupt skipping to ADC trigger TRGnBN on a TCNT underflow PDL_MTU_ADC_TRIG_A_CREST_INT_SKIP_DISABLE or PDL_MTU_ADC_TRIG_A_CREST_INT_SKIP_ENABLE Disable or link interrupt skipping to ADC trigger TRGnAN on a TGRA compare match PDL_MTU_ADC_TRIG_B_CREST_INT_SKIP_DISABLE or PDL_MTU_ADC_TRIG_B_CREST_INT_SKIP_ENABLE Disable or link interrupt skipping to ADC trigger TRGnBN on a TGRA compare match Control ADC triggers Valid for n 4 or 10 in complementary PWM mode unless stated otherwis
98. uint16_t data2 Output value uint16_tdata3 Output value Description Enable the DAC module and set the operating conditions data1 Configuration options To set multiple options at the same time use to separate each value The default settings are shown in bold Channel enable PDL_DAC_10_CHANNEL_0 Enable channel 0 PDL_DAC_10_ CHANNEL 1 Enable channel 1 Data alignment selection The alignment of the 10 bit output data within the 16 bit PDL_DAC_10_ALIGN_LEFT or parameters data2 and data3 PDL_DAC_10_ALIGN_RIGHT Left padded at the MSB end Right padded at the LSB end Teale to be written to the channel 0 output register Ignored if the channel is not enabled data3 The value to be written to the channel 1 output register Ignored if the channel is not enabled Return value True if all parameters are valid and exclusive otherwise false Functionality DAC References R_DAC_10_Destroy R_DAC_10_Write Remarks e This function configures the relevant pin for DAC operation The port control settings for any DAC pins that subsequently become inactive are not modified e This function brings the converter module out of the power down state Program example RPDL definitions include r_pdl_dac_10 h RPDL device specific definitions include r_pdl_definitions h void func void Set up DAC ch
99. up the receive process no bus activity will occur R_SCI_Receive 3 PDL_NO_DATA Rx_Data transfer_size SCI3RxFunc R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 5 30 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Weage Examples PDL_NO_FUNC Send data which will also receive data at the same time R_SCI_Send 3 PDL_NO_DATA Tx_Data transfer_size PDL_NO_FUNC Ensure the receive interrupt has processed the last byte while data_received false Process the received data here SCI channel 3 receive complete handler void SCI3RxFunc void data_received true Figure 5 15 Example of Synchronous Transmission and Reception code R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae ENESAS Page 5 31 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Weagekxamplez 4 SCI Reception in Asynchronous Multi Processor mode Figure 5 16 shows the setting of SCI channel 2 and the Multi Processor mode reception of data using interrupts and polling PDL functions include r pal scinn include r pdl_cge h tinclude r_pdl_io_port h PDL device specific definitions include r_pdl_definitions h void SCI1rx void void SCI1Er void
100. version are subject to change RX62N Group RX621 Group 6 R_BSC_GetStatus Synopsis Read the status registers of External Bus amp SDRAM Controller Prototype bool R_BSC_GetStatus uint8_t data1 I1 A pointer to the data1 storage location uint16_t data2 A pointer to the data2 storage location uint8_t data3 I1 A pointer to the data3 storage location Description Read the status registers of Bus amp SDRAM Controller data1 4 Library Reference The status flags shall be stored according to register BERSR1 format as below Specify PDL_NO_PTR if this information is not required b7 b6 b4 b3 b2 b1 bO 0 0 0 CPU 0 Illegal address access not 011 DTC DMACA eg 0 Timeout not generated made 0 110 EDMAC 0 1 Timeout generated 1 Illegal address access 111 EXDMAC 9 ma i others Setting prohibited data2 The status flags shall be stored according to register BERSR2 format as below Specify PDL_NO_PTR if this information is not required R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 61 b15 b3 b2 b0 The upper 13 bits of an address that was accessed when a bus error occurred 0 in units of 512 Kbytes data3 The status flags shall be stored according to register SDSR format as below Specify PDL_NO_PTR if this information is not required b7 b5 b4 b3 b2 b1 bO 0 Transition reco
101. 0 Page 4 139 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group iprary E Remarks e Function R_CGC_Set should be called before any use of this function e Ifa callback function is specified this function will enable the relevant interrupt Please see the notes on callback function use in 6 e A callback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed The timing limits depend on the frequency of the peripheral module clock PCLK x Period a or Frequency frar Srcix nx 256 Where n 4 64 128 512 2048 8192 32768 or 131072 Examples for different values of feck are given below feck MHz 50 12 5 48 12 32 8 Periodpcik 4 20 5 us 81 9 us 21 3 us 85 3 us 32 0 us 128 us Periodpcik 64 328 us 1 31 ms 341us 1 37 ms 512 0 us 2 05 ms Periodpcik 128 655 us 2 62 ms 683 us 2 73 ms 1 02 ms 4 10 ms Periodpcik 512 2 62 ms 10 5 ms 2 73 ms 10 9 ms 4 10 ms 16 4 ms Periodpcik 2048 10 5 ms 41 9 ms 10 9 ms 43 7 ms 16 4 ms 65 5 ms Periodpcik 8192 41 9 ms 168 ms 43 7 ms 175 ms 65 5 ms 262 ms Periodpcik 32768 168 ms 671 ms 175 ms 699 ms 262 ms 1 05s Periodpcik 131072 671 ms 2 68 s 699 ms 2 85 1 05s 4 19s fpcLk 4 48 8 kHz 12 2 kHz 46 9 kHz 11 7 kHz 31 3 kHz 7 81 kHz fPeL
102. 0_CPU_ON Start ADC1 and wait for it to complete ADC_10_Control PDL_ADC_10_1_ON Fetch the result R_ADC_10_Read 1 amp result_adcl j Wait for ADCO to complete while adcO_complete false Fetch the result R_ADC_10_Read 0 amp result_adc0O Shutdown ADC unit 0 R_ADC_10_Destroy 0 while 1 void ADCO_callback void adcO_complete true R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 5 58 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 WeageExamplez Figure 5 31 Example of ADC Self Diagnostic function R20UT0084EE0004 Rev 0 04 Aug 25 2010 Begs es RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group A Rceneene otes 6 RX specific notes 6 1 Interrupts and processor mode The RX CPU has two processor modes supervisor and user The API driver functions will be executed by the CPU in user mode However any callback functions which are called by the API interrupt handlers will be executed by the CPU in supervisor mode This means that the privileged CPU instructions RTFI RTE and WAIT can be executed by the callback function and any function that is called by the callback function The user must 1 Avoid using the RTFI and RTE instruction
103. 1 Group 4 Libary Reien Description 3 3 PDL_INTC_VECTOR_CMIA1 Return value Category Reference Remarks PDL_INTC_VECTOR_CMIB1 PDL_INTC_ VECTOR OVI1 8 bit timer TMR channel 1 Compare match A Compare match B Overflow PDL_INTC_VECTOR_CMIA2 PDL_INTC_VECTOR_CMIB2 PDL_INTC_ VECTOR OVI2 8 bit timer TMR channel 2 Compare match A Compare match B Overflow PDL_INTC_VECTOR_CMIA3 PDL_INTC_VECTOR_CMIB3 PDL_INTC_ VECTOR OVI3 8 bit timer TMR channel 3 Compare match A Compare match B Overflow PDL_INTC_VECTOR_DMACOI PDL_INTC_VECTOR_DMAC1I PDL_INTC_VECTOR_DMAC2I PDL_INTC_VECTOR_DMAC3I Direct memory access controller Transfer complete or Transfer escape end PDL_INTC_VECTOR_EXDMACOI PDL_INTC_VECTOR_EXDMAC1I External DMAC Transfer complete or Transfer escape end PDL_INTC_VECTOR ERIO PDL_INTC_VECTOR RXIO Error in data received Data received PDL_INTC_VECTOR_TXIO SCI channel OT Start of next data transfer PDL_INTC_VECTOR_TEIO End of data transfer PDL_INTC_VECTOR_ERI1 Error in data received PDL_INTC_VECTOR_RXI1 SCI channel 1 Data received PDL_INTC_VECTOR_TXI1 Start of next data transfer PDL_INTC_VECTOR_
104. 2 void main void Put a null at the end result 1 0 Initialise the system clocks R_CGC_Set 12E6 96E6 48E6 0 PDL_CGC_BCLK_DISABL Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Set up SCI channel 0 Async 8N1 38400 baud R_SCI_Create 0 PDL_SCI_ASYNC PDL_SCI_8N1 38400 0 Set up SCI channel 1 Async 8N1 19200 baud R_SCI_Create 1 PDL_SCI_ASYNC PDL_SCI_8N1 19200 0 Wait for 1 character to be received on channel 1 R_SCI_Receive 1 PDL_NO_DATA result 1 PDL_NO_FUNC PDL_NO_FUNC Send a string on channel 0 wait for completion R_SCI_Send 0 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 5 28 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group amp Weagakexamplee PDL_NO_DATA Renesas RX 0 PDL_NO_FUNC Send another string on channel 0 R_SCI_Send 0 PDL_NO_DATA www renesas com 0 SCIOTxFunc Echo the character on channel 1 R_SCI_Send 1 PDL_NO_DATA result 0 PDL_NO_FUNC SCI channel 0 transmit complete handler void SCIOTxFunc void Shut down channel 0 R_SCI_Destroy 0 Figure 5 14 Example of SCI Transmission code R20UT0084EE0004 Rev 0 04 A
105. 2 AS Page 5 24 XENES Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Wage Example For full flexibility the R_TMR_CreateChannel function can be used In this example Timer channel 0 is configured to provide pulses on pin TMOO with a pulse width of 200 ticks of PCLK and a duty cycle of 50 Note that the output transitions and counter clearing occur after the compare match has occurred So the values for compare match A and compare match B should be 1 less than the required count Peripheral driver function prototypes include r_pdl_tmr h r_pdl_definitions h un include void main void Configure TMRO to clear on a compare match A output 1 at a compare match A and output O at a compare match B R_TMR_CreateChanneli 0 DL_TMR_CLK_PCLK_DIV_1 PDL_TMR_CLEAR_CM_A PDL_TMR_OUTPUT_HIGH_CM_A PDL_TMR_OUTPUT_LOW_CM_B L_NO_DATA L_NO_FUNC L_NO_FUNC L_NO_FUNC D 2 200 2 1 D D D Figure 5 11 Example of Pulse Output code Counter value Figure 5 12 Example of pulse output operation R20UT0084EE0004 Rev 0 04 Aug 25 2010 ee RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 WeageExamplez 5 8 Serial Communication Interface 1 SCI Reception
106. 2 b11 b10 b8 SPSSR 0 Error command 0 Command pointer b7 b6 b5 b4 b3 b2 b1 bO Sna RECEIVE arene Parity error Mode fault Bus state Overrun error buffer 0 buffer 0 0 Empty 0 Full 0 No error 0 No fault 0 Idle 0 No error 1 Full 1 Empty 1 Detected 1 Detected 1 Active 1 Detected data3 The storage location for the number of sequence loops that have been completed in the current transfer Specify PDL_NO_PTR if this information is not required Return value True if all parameters are valid otherwise false Category SPI Reference Remarks e Ifthe status flags are read and an error or fault flag is set to 1 the flag will be cleared to 0 by this function Program example RPDL definitions include r_pdl_spi h RPDL device specific definitions include r_pdl_definitions h void func void uintl6_t StatusValue Read the status of channel 0 R_SPI_GetStatus 0 amp StatusValue PDL_NO_PTR R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group EE E enes 4 2 24 12 bit Analog to Digital Converter R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae Page 4 189 a ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Gro
107. 20UT0084EE0004 Rev 0 04 Aug 25 2010 Sane RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 24 IC Bus Interface Driver The driver functions support the use of the two C modules providing the following operations 1 Configuration for use including e Automatic clock setting using transfer rate as an input e Automatic interrupt control e Automatic I O pin configuration 2 Disabling modules that are no longer required and enabling low power mode 3 Transmitting data in Master mode 4 Receiving data in Master mode 5 Monitoring the bus and handling the reception of data in Slave mode 6 Transmitting data in Slave mode 7 Control of one or more units including bus lock up recovery support 8 Reading the status of a module Note The Clock Generation Circuit must be configured before configuring any I C module R20UT0084EE0004 Rev 0 04 Aug 25 2010 iame RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 25 Serial Peripheral Interface Driver The driver functions support the use of the two SPI channels providing the following operations 1 Configuration for use including e Automatic clock setting using transfer rate as an input e Automatic I O pin configuration 2 Disabling channels that are no l
108. 26 12 bit Analog to Digital Converter Driver o oo cece eeeeeeeeeeeeeeeeeneeeeeteeeaeeeeeeeaeeeseeaaeeeseeaeeeeeeaees 2 26 2 27 10 bit Analog to Digital Converter Driver o oo eee eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeseeeaeeeeeeaaeeeeeeaeeeseeaees 2 27 2 28 10 bit Digital to Analog Converter Driver ccccecceeeeeeeeeeeeseeeeeeeeeeeaeeeseeeeeeeeeeeaeeesenaeeeeteeaeeeteeaees 2 28 3 hypes and definitions saz saan aad AE dan an ais Gane eae aie ae eee 3 1 3 1 Data typos ie ciciviecel anodes ipi i arii i i i aed dined iiai a veda dene dedi 3 1 3 2 Venera Gerinitions a a a a a aa e a a a a aaa eve nA 3 1 3 2 1 ADI ENNE a E OR EEEE A E E E T E O EIN 3 1 2227 OPON NO PTR 5 ata eet ee re Mer hee ata ee a a een aloes 3 1 32 35 PDLUNODATAS itt itn eet okra te eel ete ahah eet Stee Rees areca ee 3 1 32 45 PDL MEU GROUP ie tere sic ses itt a aed saa sat ete a a a loathe aa tise teas penne aaa 3 1 32 5 PDL VERSION aen ee i iad a ieee ae eel to ieee eterna 3 1 4 hibrany ReferenCe ss Aides ee aA NEE AE Seen Aa aetna ee E 4 2 Ai APLLIstiby Renipheral Function osina eaten ects ated ee tect ied de eet eta 4 2 4 2 Description oft Each AP Imation en hagienten dein ea ee 4 5 4 2 1 Clock Generation Circ it neatente eee eed ea ended devel cli dades aa a a anra eet 4 6 1 ROGO Seta e eerie peeved lie de vay ede ended eee tds fee aad ciendal vedo ane ieee eres 4 6 2 R CG6C Controlia aceite Meera E aie eae islands 4 8 3 R CGGC GetStatus
109. 4 Aug 25 2010 ae ENESAS Page 5 21 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Urago Example 5 6 Compare Match Timer Figure 5 9 shows an example of Compare Match Timer usage One channel is used to generate interrupts at regular intervals Peripheral driver function prototypes include r_pdl_cmt h include r_pdl_cgc h include r_pdl_io_port h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Callback function prototype void CMTO_handler void void main void Initialise the system clocks R_CGC_Set 12 0E6 96E6 48E6 24E6 PDL_CGC_BCLK_HIGH Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 dF Configure a port pin for output R_IO_PORT_Set PDL_IO_PORT_3_4 PDL_IO_PORT_OUTPUT Configure CMT channel 0 for 1kHz operation R_CMT_Create 0 L_CMT_FREQUENCY E3 rO_handler Change the frequency to 10kHz R_CMT_Control 0 PDL_CMT_FREQUENCY 10E3 void CMTO_handler void Invert the port pin R_IO_PORT_Modify PDL_IO_PORT_3_4 L_IO_PORT_XOR R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 5 22 RENESAS Under development Preliminary Specification Spe
110. 8 For ID cycle the DMAC DTC trigger control and the callback function will be ignored RPDL definitions nclude r_pdl_sci h RPDL device specific definitions nclude r_pdl_definitions h void func void uint8_t data_store 100 Send a string on channel 2 R_SCI_Send 2 PDL_NO_DATA Renesas RX 0 PDL_NO_FUNC Send 50 bytes of binary data on channel 1 R_SCI_Send 2 PDL_NO_DATA data_store 50 PDL_NO_FUNC R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 150 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 5 R_SCI_ Receive Synopsis Prototype Description Receive data on a SCI channel bool R_SCI_Receive uint8_t data1 Channel selection uint16_t data2 Channel configuration and Station ID of receiving device uint8_t data3 Data start address uint16_t data4 Receive threshold void func Callback function void func2 Callback function Enable SCI reception and acquire any incoming data data1 Select channel SCIn where n 0 to 6 but not 4 data2 The lower 8 bit selects the DMAC DTC trigger control or specify the ID cycle for Multi processor mode The upper 8 bit is the Station ID which is only valid with the ID cycle e DMAC DTC trigger control The
111. ABLE the transfer e DMAC DTC trigger control PDL_lIC_DMAC_DTC_TRIGGER_DISABLE or PDL_lIC_DMAC_TRIGGER_ENABLE or PDL_lIC_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC when a data byte is transmitted data3 The address of the slave device Ignored if the Start condition is disabled data4 The start address of the data to be sent data5 The number of bytes to be sent func The function to be called when bus activity has stopped Specify PDL_NO_FUNC for this function to wait until the transfer is complete or another event occurs data6 The interrupt priority level Select between 1 lowest priority and 7 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid exclusive and achievable and a normal transfer completed otherwise false C R_IIC_Create R_IIC_GetStatus R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 167 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Remarks Program example 1 1 co vo 4 Library Reference If a callback function is specified transmission interrupts are used Please see the notes on callback function usage in 6 If the Start condition is enabled and the previous transfer did not issue a Stop condit
112. A_ALIGNMENT_RIGHT The alignment of the 10 bit ADC conversion result within the 16 bit register Left padded at the MSB end Right padded at the LSB end e DMAC DTC trigger control PDL_ADC_10_DMAC_TRIGGER_ENABLE or PDL_ADC_10 DTC TRIGGER ENABLE PDL_ADC_10 DMAC_ DTC TRIGGER DISABLE or Disable or enable activation of the DMAC or DTC when a conversion or scan cycle completes Sampling time calculation PDL_ADC_10_ADSSTR_CALCULATE or PDL_ADC_10_ADSSTR_SPECIFY Select whether parameter data4 is used to calculate the ADSSTR value or contains the value to be stored in register ADSSTR e Pin selection required only if the pin is used PDL_ADC_10_PIN_ADTRGO_A or PDL_ADC_10 PIN ADTRGO_B Select the A or B pin for ADTRGO Self Diagnostic PDL_ADC_10_SELF_DIAGNOSTIC_DISABLE or PDL_ADC_10_SELF_DIAGNOSTIC_VREF_0 or PDL_ADC_10_SELF_DIAGNOSTIC_VREF_0_5or Disable or enable Self diagnostic function of Vref x 0 voltage value or Vref x 1 2 voltage value or PDL_ADC_10 SELF _DIAGNOSTIC_VREF_1 Vref x 1 voltage value data3 The desired frequency of the conversion clock ADCLK in Hertz data4 The data to be used for the sampling state register value calculations Data use The timer period in seconds or The value to be put in register ADSSTR func Parameter type float uint8_t The function to be called when the ADC conversion or sc
113. C trigger control PDL_INTC_DTC_SW_TRIGGER_DISABLE or Disable or enable activation of the DTC PDL_INTC_DTC_SW_TRIGGER_ENABLE when a software interrupt is generated func The function to be called when a valid condition is detected Specify PDL_NO_FUNC if no interrupt is required data2 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func Return value True if all parameters are valid otherwise false Category Interrupt control Reference R_INTC_Write Remarks e Please see the notes on callback function use in 6 Specifying PDL_NO_FUNC for the callback function allows the software interrupt to be used as a DTC trigger e Use R_INTC_Write to generate the software interrupt Program example RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Declaration of callback function void CallBackFunc void void func void Configure the software interrupt handler R_INTC_CreateSoftwarelInterrupt PDL_NO_DATA CallBackFunc 7 R20UT0084EE0004 Rev 0 04 Aug 25 2010 ee RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 bran Reterenee 3 R_INTC_CreateFas
114. Channel selection uint16_tdata2 Channel configuration uint16_tdata3 Slave address uint8_t data4 Data start address uint16_t data5 Receive threshold void func Callback function uint8_t data6 Interrupt priority level Read data over an lC channel and store it data1 Select channel IICn where n 0 or 1 data2 Configure the channel The default setting is shown in bold Specify PDL_NO_DATA to use the defaults e DMAC DTC trigger control PDL_lIC_DMAC_DTC_TRIGGER_DISABLE or PDL_lIC_DMAC_TRIGGER_ENABLE or PDL_lIC_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC when a data byte is received data3 The address of the slave device data4 The start address of the storage area for the expected data Specify PDL_NO_PTR if no data shall be processed by this function e g if the DMAC or DTC shall be used to process the received data data5 The number of bytes that must be received before the function completes or the callback function is called func The function to be called when bus activity has stopped While the receive operation is in progress R_IIC_GetStatus can be used to find out how many bytes have been received so far Specify PDL_NO_FUNC for this function to continue until the required number of bytes has been received data6 The interrupt priority level Select between 1 lowest priority and 7 highest priority This parameter will be
115. DL_DTC_SIZE_8 PDL_DTC_IRQ_ COMPLETE PDL_DTC_TRIGGER_IRQ3 dtc_irg3_transfer_data source_string_l destination_string_l 1 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 5 20 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group amp Weagakxamples uint8_t strlen char source_string_1 while 1 Enable the SW3 interrupt R_INTC_CreateExtInterruptAll PDL_INTC_IRQ3 PDL_INTC_FALLING PDL_INTC_B PDL_INTC_DTC_TRIGG IRQ3_handler 7 Start the DTC R_DTC_Control PDL_DTC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA void IRQ3_handler void uint8_t StatusValue uint32_t SourceAddr uint32_t DestAddr uint32_t TransferCount Read the status and current source address for the IRQ3 transfer R_DTC_Get Status dtc_irg3_transfer_data amp StatusValue amp SourceAddr amp DestAddr amp TransferCount PDL_NO_DATA Normal transfer if StatusValue 0x00 Invert the port pin R_IO_PORT_Modify PDL_IO_PORT_3_6 PDL_IO_PORT_XOR I Re enable IRQ3 as a DTC trigger R_DTC_Control PDL_DTC_TRIGGER_IRQ3 PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA Figure 5 8 Example of DTC use R20UT0084EE0004 Rev 0 0
116. DL_MTU_CLK_MTCLKC or MTCLKC pin input Valid for n 0 or 2 PDL_MTU_CLK_MTCLKD or MTCLKD pin input Valid for n 0 PDL_MTU_CLK_MTCLKE or MTCLKE pin input Valid for n 6 to 10 PDL_MTU_CLK_MTCLKF or MTCLKF pin input Valid for n 6 to 10 PDL_MTU_CLK_MTCLKG or MTCLKG pin input Valid for n 6 or 8 PDL_MTU_CLK_MTCLKH or MTCLKH pin input Valid for n 6 PDL_MTU_CLK_CASCADE The overflow underflow signal from MTU n 1 Valid for n 1 or 7 TCNT counter clock edge selection Valid for n 0 to 4 or 6 to 10 PDL_MTU_CLK_RISING or PDL_MTU_CLK_FALLING or PDL_MTU_CLK_BOTH The TCNT counter clock signal shall be counted on rising falling or both edges TCNT counter clearing Valid for n 0 to 4 or 6 to 10 unless stated otherwise PDL_MTU_CLEAR_DISABLE or Clearing is disabled PDL_MTU_CLEAR_TGRA or Cleared by TGRA compare match or input capture PDL_MTU_CLEAR_TGRB or Cleared by TGRB compare match or input capture PDL_MTU_CLEAR_SYNC Cleared by counter clearing on another channel configured for synchronous operation PDL_MTU_CLEAR_TGRC or Cleared by TGRC compare match or input capture Valid for n 0 3 4 6 9 and 10 PDL_MTU_CLEAR_TGRD or Cleared by TGRD compare match or input capture Valid for n 0 3 4 6 9 and 10 7tENESAS Under development Preliminary Specification Spec
117. DMAC_DESTINATION_ADDR ESS_FIXED PDL_DMAC_SIZ I PDL_DMAC_REQUEST_SCI1_TX source_string_l uint8_t amp SCI1 TDR 1 uint16_t strlen source_string_1 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 5 15 7tENESAS So 8 5 Usage Examples PDL_DMAC_IRQ_ Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 6 Weage Example DMAC3_transfer_end_handler 7 Enable channel 3 R_DMAC_Control 3 _ DMAC_ENABL L_NO_PTR L_NO_PTR L_NO_DATA L_NO_DATA L_NO_DATA L_NO_DATA L_NO_DAT OOOO Ooo U Initialise the flags sci_dma_transfer_complete false break_required false Enable the transmission using the DMAC R_SCI_Send 1 PDL_SCI_DMAC_TRIGG PDL_NO_PTR PDL_NO_DATA PDL_NO_FUNC Wait for the DMAC to complete the transfer while sci_dma_transfer_complete false Send the next string using polling mode R_SCI_Send 1 PDL_NO_DATA Source string 2 0 PDL_NO_FUNC void DMAC3_transfer_end_handler void uint8_t SCI_status Wait for the SCI transmission to end do R_SCI_Get Status 1 amp SCI_status PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR while SCI_status amp 0x04 0 if break_r
118. E0004 Rev 0 04 Aug 25 2010 RENESAS Page 5 19 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Weage Example 5 5 Data Transfer Controller Figure 5 8 shows an example of Data Transfer Controller usage Peripheral driver function prototypes include r_pdl_dtc h include r_pdl_cgc h include r_pdl_io_port h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Required for this example include lt string h gt Reserve an area for the DTC vector table pragma address dtc_vector_table 0x00015000 uint32_t dtc_vector_table 256 Reserve 16 bytes for the IRQ3 triggered transfer data area uint32_t dtc_irg3_transfer_data 4 void main void Initialise the system clocks R_CGC_Set 12 5E6 100E6 50E6 25E6 PDL_CGC_BCLK_DISABL Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Enable control of LEDO R_IO_PORT_Set DL_IO_PORT_3_6 DL_IO_PORT_OUTPUT i Set the DTC options R_DTC_Set PDL_NO_DATA dtc_vector_table Configure the DTC for IRQ3 if R_DTC_Create PDL_DTC_BLOCK PDL_DTC_DESTINATION PDL_DTC_SOURCE_ADDRESS_PLUS PDL_DTC_DESTINATION_ADDRESS_PLUS P
119. EE0004 Rev 0 04 Aug 25 2010 Page 4 34 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 7 RIO PORT_Modify Synopsis Prototype Description Return value Functionality References Remarks Program example Modify the pin states on an I O port bool R_IO_PORT_Modify uint16_tdata1 Output port or port pin selection uint8_t data2 Logical operation uint8_t data3 II Modification value Read the output state of an I O port or I O port pin modify the result and write it back to the port data1 Use either one of the following definition values from 4 2 3 One port definition or e One port pin definition data2 e The logical operation to be applied to the port or port pin PDL_IO_PORT_AND or PDL_IO_PORT_OR or Select between AND amp OR or Exclusive OR PDL_IO_PORT_XOR data3 The value to be used for the modification Between 0x00 and OxFF for a port O or 1 for a pin True if the parameters are valid otherwise false I O port R_IO_PORT_Set R_IO_PORT_Read R_IO_PORT_Write e Ifan invalid port or pin is specified the operation of the function cannot be guaranteed RPDL definitions include r_pdl_io_port h RPDL device specific definitions inclu
120. EG IR_TMR1_OVI PDL_INTC REG IR SCI5 RXI PDL_INTC_REG IR TMR2 CMIA PDL_INTC REG IR SCI5 TXI PDL_INTC_REG IR TMR2 CMIB PDL_INTC REG IR SCI5 TEI PDL_INTC REG IR_TMR2 OVI PDL_INTC REG IR SCI6 ERI PDL_INTC_REG IR_TMR3 CMIA PDL_INTC REG IR SCI6 RXI PDL_INTC_REG IR_TMR3 CMIB PDL_INTC REG IR SCI6 TXI PDL_INTC REG IR_TMR3 OVI PDL_INTC REG IR SCI6 TEI PDL_INTC_REG IR_DMACA_DMACOI PDL_INTC_REG IR_IICO_EEl PDL_INTC_REG IR _DMACA_DMAC1I PDL_INTC_ REG IR_IICO RXxI PDL_INTC_REG IR_DMACA_DMAC2I PDL_INTC_REG IR_IICO_TXI PDL_INTC_REG IR_DMACA_DMAC3I PDL_INTC_ REG IR_IICO TEI PDL_INTC_REG_IR_EXDMAC_EXDMACOI PDL_INTC_REG IR_IIC1_EEl PDL_INTC_REG_IR_EXDMAC_EXDMAC1I PDL_INTC_ REG _IR_IIC1_RXxI IER register definitions PDL_INTC_ REG IR_IIC1_TXI PDL_INTC_ REG IR_IIC1_TEI PDL_INTC_REG_IERO2 PDL_INTC_REG_IER10 PDL_INTC_REG _IERO3 PDL_INTC_REG IER11 PDL_INTC_REG_IER04 PDL_INTC_ REG IER12 PDL_INTC_REG _IERO5 PDL_INTC_ REG IER13 PDL_INTC_REG_IERO6 PDL_INTC_REG IER14 PDL_INTC_REG_IERO7 PDL_INTC REG IER15 PDL_INTC_REG IERO8 PDL_INTC_ REG IER16 PDL_INTC_REG IEROQ PDL_INTC_ REG IER17 PDL_INTC_REG IEROB PDL_INTC_ REG IER18 PDL_INTC_ REG IEROC PDL_INTC_REG IER19 PDL_INTC_REG IEROE PDL_INTC_REG IER1A PDL_INTC_REG_IEROF PDL_INTC_REG IER1B PDL_INTC_REG IER1IC
121. ER_DISABLE or PDL_MTU_TGRD DTC TRIGGER ENABLE TGRD compare match or input capture Valid for n 0 3 4 6 9 and 10 PDL_MTU_TCIV_DTC_TRIGGER_DISABLE or PDL_MTU_TCIV_DTC_TRIGGER_ENABLE Counter overflow or underflow Valid for n 4 or 10 DTC event trigger control Valid for n 5 or 11 PDL_MTU_TGRU_DTC_TRIGGER_DISABLE or PDL_MTU_TGRU_DTC_ TRIGGER ENABLE TGRU compare match or input capture PDL_MTU_TGRV_DTC_TRIGGER_DISABLE or PDL_MTU_TGRV_DTC_TRIGGER_ENABLE TGRV compare match or input capture PDL_MTU_TGRW_DTC_TRIGGER_ DISABLE or PDL_MTU_TGRW_DTC_TRIGGER_ENABLE TGRW compare match or input capture data3 Configure the counter operation If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults TCNT counter clock source selection Valid for n 0 to 4 or 6 to 10 unless stated otherwise PDL_MTU_CLK_PCLK_DIV_1 or PDL_MTU_CLK_PCLK_DIV_4 or PDL_MTU_CLK_PCLK_DIV_16 or PDL_MTU_CLK_PCLK_DIV_64 or The internal clock signal PCLK 1 4 16 or 64 PDL_MTU_CLK_PCLK_DIV_256 or PCLK 256 Valid for n 1 3 4 7 9 and 10 PDL_MTU_CLK_PCLK_DIV_1024 or PCLK 1024 Valid for n 2 3 4 8 9 and 10 PDL_MTU_CLK_MTCLKA or MTCLKA pin input Valid for n 0 to 4 PDL_MTU_CLK_MTCLKB or MTCLKB pin input Valid for n 0 to 4 P
122. Enable use of the software interrupt R_INTC_CreateFastInterrupt Assign handlers for the fixed vector interrupts R_INTC_CreateExceptionHandlers Enable faster interrupt processing for one interrupt R_INTC_ControlExtInterrupt External interrupt control R_INTC_GetExtInterruptStatus Read the external interrupt status R_INTC_Read Read an interrupt register R_INTC Write Update an interrupt register R_INTC_Modify Modify an interrupt register I O port R_IO_PORT_Set Configure an I O port R_IO_PORT_ReadControl Read an I O port s control registers IO PORT _ModifyControl Modify an I O port s control registers O_PORT_Read Read data from an I O port O_PORT Write Write data to an I O port Check the pin states on an I O port O_PORT Modify Modify the pin states on an I O port l l IO_PORT_Compare l l MCU operation R_ R_ R_ Ro R_ RL R R R_ R O_PORT Wait Wait for a match on an I O port Port F cti n PFC_Read Read a PFC register Control PFC_Write Write to a PFC register PFC_Modify Modify a PFC register MCU_Control Control the operation of the MCU R_MCU_GetStatus Read the MCU status Low Power Consumption R_LPC_Create Configure the MCU low power conditions R_LPC_Control Select a low power consumption mode R_LPC_WriteBackup Write to the Backup registers
123. F R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 56 RENESAS Under development Preliminary Specification Description 2 2 Return value Category Reference Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference data5 The value to be set to ARFC bits in SDRAM Initialization Register SDIR Valid between 0x01 and OxOF Setting of 0x00 is prohibited data6 The value to be set to PRC bits in SDRAM Initialization Register SDIR Valid between 0x00 and 0x07 data7 The value to be set to CL bits in SDRAM Timing Register SDTR Valid between 0x01 and 0x03 Setting of 0x00 or more than 0x03 is prohibited data8 The value to be set to WR bit in SDRAM Timing Register SDTR Valid between 0x00 and 0x01 data9 The value to be set to RP bits in SDRAM Timing Register SDTR Valid between 0x00 and 0x07 data10 The value to be set to RCD bits in SDRAM Timing Register SDTR Valid between 0x00 and 0x03 data11 The value to be set to RAS bits in SDRAM Timing Register SDTR Valid between 0x00 and 0x07 data12 The value to be written to the SDRAM mode register Only the lower 15 bits are valid Please refer to hardware manual for restriction on SDRAM mode setting True if all parameters are valid and exclusive otherwise false Bus Controller R_BSC_Create Remarks e Ensure that functi
124. Figure 5 13 shows the setting of SCI channels 0 and 1 and the reception of data using interrupts channel 0 and polling channel 1 Peripheral driver function prototypes include r_pdl_sci h include r_pdl_cgc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Callback function prototypes void System_failed void void System_reset void void SCIORxFunc void void SCI0OErrFunc uint8_t volatile char rx_string 10 void main void uint8_t result Initialise the system clocks R_CGC_Set 12E6 96E6 48E6 0 PDL_CGC_BCLK_DISABLE Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Set up SCI channel 0 Async 8N1 38400 baud R_SCI_Create 0 PDL_SCI_ASYNC PDL_SCI_8N1 38400 1 Set up SCI channel 1 Async 8N1 19200 baud R_SCI_Create 1 PDL_SCI_ASYNC PDL_SCI_8N1 19200 0 Start the interrupt based reception of 9 characters on channel 0 R_SCI_Receive 0 PDL_NO_DATA rx_string 9 SCIORxFunc SCIOErrFunc R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 5 26 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Urago Examples Wait for 1 character to be received on channel 1 R_
125. IR USB _USBR1 PDL_INTC_REG IR_MTU9 TGIB PDL_INTC_REG IR_RTC ALM PDL_INTC_REG IR MTU9 TGIC PDL_INTC_REG IR_WDT_WOVI PDL_INTC_REG IR_MTU9 TGID PDL_INTC_REG_IR_MTU9 TCIV R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 10 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference PDL_INTC_REG IR _MTU10 TGIA PDL_INTC_REG IR SCIO ERI PDL_INTC_REG IR MTU10_ TGIB PDL_INTC REG IR SCIO RXI PDL_INTC_REG IR MTU10 TGIC PDL_INTC REG IR SCIO TXI PDL_INTC_REG IR MTU10 TGID PDL_INTC REG IR SCIO TEI PDL_INTC_REG IR _MTU10_TCIV PDL_INTC_REG IR SCI1_ERI PDL_INTC_REG IR MTU11_TGIU PDL_INTC_ REG IR SCI1_RXI PDL_INTC_REG IR MTU11_TGIV PDL_INTC_REG IR SCI1_TXI PDL_INTC_REG IR MTU11_TGIW PDL_INTC_ REG IR SCI1 TEI PDL_INTC_REG IR POE _OEI1 PDL_INTC_REG IR SCI2 ERI PDL_INTC_REG IR POE OEI2 PDL_INTC_REG IR SCI2 RXI PDL_INTC_REG IR POE OEI3 PDL_INTC_ REG IR SCI2 TXI PDL_INTC_REG IR POE OEI4 PDL_INTC_ REG IR SCI2 TEI PDL_INTC_REG IR_TMRO CMIAO PDL_INTC_REG IR SCI3 ERI PDL_INTC_REG IR _TMRO CMIBO PDL_INTC REG IR SCI3 RXI PDL_INTC_REG IR_TMRO OVIO PDL_INTC REG IR SCI3 TXI PDL_INTC_REG IR_TMR1_CMIA PDL_INTC REG IR SCI3 TEI PDL_INTC_REG IR _TMR1_CMIB PDL_INTC REG IR SCI5 ERI PDL_INTC_R
126. I_PIN_SCI2 Aor PDL SCI PIN_SCI2_B Select the A or B pins for RxD2 SCK2 TxD2 PDL_SCI_PIN_SCI3 Aor PDL_SCI_PIN SCI3_B Select the A or B pins for RxD3 SCK3 TxD3 PDL_SCI_PIN_SCI6_A or PDL_SCI_PIN_SCI6_B Select the A or B pins for RxD6 SCK6 TxD6 True if all parameters are valid and exclusive otherwise false SCI R_SCl_Create e Before calling R_SCI_Create function if the selected device package offers A or B pins for SCI signals call this function once e Pins which are not used for the SCI functions may be omitted e Please refer to the Port Function Control Register F PFFSCI session in RX62N Hardware Manual for details of SCI pin selection include r_pdl_sci h void func void Configure the applicable SCI pins R_SCI_Set PDL_SCI_PIN_SCI2_A PDL_SCI_PIN_SCI6_B R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 144 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 fabranyReterence 2 R_SCI_Create Synopsis SCI channel setup Prototype bool R_SCI_Create uint8_t data1 Channel selection uint32_t data2 Channel configuration uint32_t data3 Bit rate or register value uint8_t data4 Interrupt priority level Description 1 3 Set up the selected SCI channel data1 Select channel SCIn where n 0 to 6 but
127. K 64 3 05 kHz 763 Hz 2 93 kHz 732 Hz 1 95 kHz 488 Hz fPeLK 128 1 53 kHz 381 Hz 1 46 kHz 366 Hz 977 Hz 244 Hz fecik 512 381 Hz 95 4 Hz 366 Hz 91 6 Hz 244 Hz 61 0 Hz fPeLK 2048 95 4 Hz 23 8 Hz 91 6 Hz 22 9 Hz 61 0 Hz 15 3 Hz fpcik 8192 23 8 Hz 5 96 Hz 22 9 Hz 5 72 Hz 15 3 Hz 3 81 Hz fPeLK 32768 5 96 Hz 1 49 Hz 5 72 Hz 1 43 Hz 3 81 Hz 0 954 Hz fpcik 131072 1 49 Hz 0 373 Hz 1 43 Hz 0 358 Hz 0 954 Hz 0 238 Hz Program example RPDL definitions include r_pdl_wdt h RPDL device specific definitions include r_pdl_definitions h void func void Configure the watchdog timer for PCLK 4 operation R_WDT_Create PDL_WDT_PCLK_DIV_4 WDT_handler 7 i Configure the watchdog timer for PCLK 131072 operation with output and reset enable R_WDT_Create 1 PDL _WDT_PCLK_DIV_131072 PDL_WDT_RESET ENABLE PDL_NO_FUNC 0 R20UT0084EE0004 Rev 0 04 Aug 25 2010 a RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 R_WDT Control Synopsis Prototype Description bool R_WDT_Control Control selection uint8_t data data Configure the timer channel To set multiple options at the same time use to separate each value Counter stop 4 Library Reference Control the Watch
128. KKK KKK kkk In Deep Software Standby mode KOK KKK KK KK OK kxxkKKKK Exiting Deep Software Standby mode By NMI x fERSXEXERAES Out Of Deep Software Standby mode x ex Find out what caused the exit from deep software standby R_LPC_GetStatus amp status_flags SELF_REFRESH_SELECT Enable SDCLK R_CGC_Control PDL_CGC_SDCLK_ENABLE Configure the bus controller Select pin B for CS1 CS7 enable SDRAM pins enable error monitoring R_BSC_Create PDL_BSC_CS1_B PDL_BSC_CS2_B PDL_BSC_CS3_B PDL_BSC_CS4_B PDL_BSC_CS5_B PDL_BSC_CS6_B PDL_BSC_CS7_B PDL_ BSC_SDRAM_PINS_ENABLE X PDL_BSC_SDRAM_DQM1_ENABLE PDL_ BSC_SDRAM_SDCLK_ENABLE PDL_BSC_ERROR_ILLEGAL_A ESS_ENABLE PDL_BSC_ERROR_TIME_OUT_E E BSC_error_handler 5 Configure SDRAM area R_BSC_SDRAM_ CreateArea PDL_BSC_SDRAM_WIDTH_32 PDL_BSC_SDRAM_8_BIT_SHIFT OxOFFFu RFC 4096 cycles 0x00u REFW 1 cycle Ox00u ARFI 3 cycles Ox02u ARFC 2 times Ox00u PRC 3 cycles Ox02u CL 2 cycles Ox0Olu WR 2 cycles 0x00u RP 1 cycle 0x00u RCD 1 cycle Ox00u RAS 1 cycle 0x0220u SDMOD 0x220u Start Auto Refresh R_BSC_Control PDL_BSC_SDRAM_AUTO_RE Check the status flags do R_BSC_GetStatus amp statusl amp
129. L_IO PORT 7 PortP7 PDL_IO PORT 8 Port P8 PDL_IO PORT 9 PortP9 PDL_IO PORTA Port PA PDL_IO PORT B Port PB PDL_IO_ PORT C Port PC PDLIO PORT D PortPD PDL_IO_PORT E Port PE PDL_IO PORT F PortPF PDL_IO PORT G Port PG Note Refer to the hardware manual for the ports which are available on the device that you have selected I O port pin definitions PDL_IO_PORT_0_0_ Port pin POo PDL_IO_PORT_0 1 Port pin PO PDL_IO PORT 0 2 Portpin P02 PDL_IO_PORT_0 3 Port pin PO PDL_IO_PORT_04 Port pin PO PDL_IO_PORT_0_5 Port pin POs PDL IO PORT 10 Portpin Pto PDL IO PORT 1 1 Port pin P1 PDL_IO_PORT_1_2 Portpin P12 PDL_IO_PORT_1_3 Port pin P13 PDL_IO_PORT_14 Portpin P14 PDL_IO_PORT_1_5 Port pin P15 PDL_IO_PORT_1 6 Portpin P1g PDL_IO_PORT_1_7 Port pin P17 PDL IO PORT 20 Portpin P2 PDL IO PORT 21 Port pin P2 PDL IO PORT 22 Portpin P22 PDL_IO_PORT_2 3 Port pin P23 PDL_IO PORT_2 4 Port pin P24 PDL_IO PORT 25 Port pin P25 PDL_IO_PORT_2 6 Port pin P2g PDL_IO_PORT_2 7 Port pin P27 PDL IO PORT 3 0 Portpin P3o PDL IO PORT 3 1 Port pin P34 PDL_IO_ PORT 32 Port pin P32 PDL_IO_PORT_3 3 Port pin P33 PDL_IO PORT 3 4 Port pin P34 PDL_IO_PORT_3 5 Port pin P35 PDL_IO PORT 3 6 Port pin P3 PDL_IO_PORT_3 7 Port pin P37 PDL IO PORT 40 Portpin P4o PDL IO PORT 41 Port pin
130. L_MTU_BUFFER_AC_ ENABLE Disable or enable buffer operation for registers TGRA and TGRC Valid for n 0 to 4 or 6 to 10 PDL_MTU_BUFFER_BD_DISABLE or PDL_MTU_BUFFER BD ENABLE Disable or enable buffer operation for registers TGRB and TGRD Valid for n 0 to 4 or 6 to 10 PDL_MTU_BUFFER_EF_DISABLE or PDL_MTU_BUFFER_ EF ENABLE Disable or enable buffer operation for registers TGRE and TGRF Valid for n 0 or 6 Buffer data transfer PDL_MTU_BUFFER_AC_CM_Aor PDL_MTU_BUFFER_AC_TCNT_CLR Transfer the data from TGRC to TGRA when a compare match A occurs or when TCNT is cleared in each channel Valid for n 0 3 4 6 9 or 10 PDL_MTU_BUFFER_BD_CM_B or PDL_MTU_BUFFER_BD_TCNT_CLR Transfer the data from TGRD to TGRB when a compare match B occurs or when TCNT is cleared in each channel Valid for n 0 3 4 6 9 or 10 PDL_MTU_BUFFER_EF_CM_Eor PDL_MTU_BUFFER_EF_TCNT_CLR Transfer the data from TGRF to TGRE when a compare match E occurs or when TCNT is cleared in either channel Valid for n 0 or 6 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Description 5 8 data6 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 87 4 Library Reference Configure the operation for general registers TGRA and TGRB Valid for n 0 to 4 or 6 to 10 If multiple selections ar
131. NO_FUNC 0 Enable the SW3 interrupt R_INTC_CreateExtInterruptA11 PDL_INTC_IRQ3 PDL_INTC_FALLING PDL_INTC_B PDL_INTC_DMAC_TRIGG PDL_NO_FUNC 0 Enable channel 0 R_DMAC_Control DL_DMAC_ENABL DL_NO_PTR DL_NO_PTR DL_NO_DAT DL_NO_DAT DL_NO_DAT DL_NO_DAT DL_NO_DAT T U ND O W W W Enable and start channel 1 R_DMAC_Control 1 DL_DMAC_ENABLE PDL_DMAC_START DL_NO_PTR DL_NO_PTR DL_NO_DAT DL_NO_DAT DL_NO_DAT DL_NO_DAT DL_NO_DAT Utd UU td tO DO ft Read the status for channel 0 R_DMAC_GetStatus 0 R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae ENESAS Page 5 13 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 WsageExamplee amp StatusValue amp SourceAddr amp DestAddr amp TransferCount amp SizeCount void DMACO_transfer_end_handler void Invert the port pin R_IO_PORT_Modify PDL_IO_PORT_3_6 PDL_IO_PORT_XOR J Stop all channels R_DMAC_Control PDL_DMAC_ALL PDL_DMAC_SUSPEND PDL_NO PTR PDL_NO PTR PDL_NO DATA PDL_NO DATA PDL_NO DATA PDL NO DATA PDL_NO DATA Stop channel 0 R_DMAC_Destroy 0 Figure 5 5 Two examples of DMAC use R20UT0084EE0004 Rev 0 04 Aug
132. NTC_VECTOR_TGIB9 PDL_INTC_VECTOR TGIC9 PDL_INTC_VECTOR TGID9 PDL_INTC_VECTOR_TCIV9 Multi function Timer Pulse Unit channel 9 Compare match or Input capture A Compare match or Input capture B Compare match or Input capture C Compare match or Input capture D Overflow PDL_INTC_VECTOR_TGIA10 PDL_INTC_VECTOR_TGIB10 PDL_INTC_VECTOR_TGIC10 PDL_INTC_VECTOR_TGID10 PDL_INTC_VECTOR_TCIV10 Multi function Timer Pulse Unit channel 10 Compare match or Input capture A Compare match or Input capture B Compare match or Input capture C Compare match or Input capture D Overflow PDL_INTC_VECTOR_TGIU11 PDL_INTC_VECTOR_TGIV11 PDL_INTC_VECTOR_TCIW11 Multi function Timer Pulse Unit channel 11 Compare match or Input capture U Compare match or Input capture V Compare match or Input capture W PDL_INTC_VECTOR OEI1 PDL_INTC_ VECTOR OEI2 PDL_INTC_ VECTOR OEI3 PDL_INTC_ VECTOR OEI4 Port Output Enable Input level sampling or output level comparison detection PDL_INTC_VECTOR CMIAO PDL_INTC_VECTOR_CMIBO 8 bit timer TMR Compare match A Compare match B PDL_INTC_VECTOR_OVIO channel o Overflow R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 16 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX62
133. PDL_INTC_REG IER1D PDL_INTC_REG IERIE PDL_INTC_REG IERIF R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 11 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 1 R_INTC_CreateExtinterrupt Synopsis Prototype Description Return value Configure an external interrupt pin bool R_INTC_CreateExtinterrupt uint8_t data1 Pin selection uint16_tdata2 Configuration void func Callback function uint8_t data3 Interrupt priority level Sets the specified external interrupt data1 Choose the interrupt pin to be configured PDL_INTC_IRQn n 0 to 15 or IRQn n 0 to 15 interrupt pin or PDL_INTC_NMI NMI interrupt pin data2 Choose the pin settings If multiple selections are required use to separate each selection The default settings are shown in bold Options which only apply to the IRQ pins e Input sense selection PDL_INTC_LOW or Select Low level PDL_INTC_FALLING or Falling edge PDL_INTC_RISING or Rising edge or PDL_INTC_BOTH Falling and rising edge detection Alternate pin selection PDL_INTC_Aor Select the IRQn A or IRQn B pin to be used PDL_INTC_B This is not required for IRQ12 and IRQ14 DMAC DTC trigger control Not enabled if low level detection is select
134. PDL_IO_PORT_E_7 Port pin PE PDL_IO PORT F O Port pin PFo PDL_IO PORT F1 Port pin PF PDL_IO PORT_F_2 Port pin PF2 PDL_IO PORT_F 3 Port pin PF PDL_IO PORT_F 4 Portpin PF PDL_IO PORT F_5 Portpin PFs PDL_IO PORT_F 6 Portpin PFs PDL_IO_PORT_G_0 Port pin PGo PDL_IO_PORT_G_1 Port pin PG PDL_IO PORT_G 2 Port pin PG PDL_IO_PORT_G_3 Port pin PGs PDL_IO PORT_G 4 Port pin PG PDL_IO_PORT_G_5 Port pin PGs PDL_IO PORT G6 Port pin PGs PDL_IO_PORT_G_7 Port pin PG R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 27 7tENESAS Note Refer to the hardware manual for the port pins which are available on the device that you have selected Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group dieing Resrenes 1 RIO PORT Set Synopsis Configure an I O port Prototype bool R_IO_PORT_Set uint16_tdata1 Port pin selection uint8_t data2 II Configuration Description Set the operating conditions for I O port pins data1 Select the port pins to be configured from 4 2 3 Do not use any whole port definitions Multiple pins on the same port may be specified using to separate each pin data2 Choose the pin settings Use to separate each selection If no selection is made the control setting will be left unchanged Direction control PDL_IO_PORT_INP
135. POLY_CRC_CCITT PDL_CRC_LSB_FIRST Write the payload data R_CRC_Write OxFO i Write the first half of the CRC checksum R_CRC_Write Ox8F Write the second half of the CRC checksum R_CRC_Write OxF7 Read the CRC calculation result R_CRC_Read PDL_NO_DATA amp Result i Shutdown the CRC unit R_CRC_Destroy Figure 5 18 Example of CRC calculation R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 5 35 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Weagekxemples 5 10 IC Bus Interface In the following examples the bus activity will be illustrated using the following format Sapa E Pa mT aa TE A Acknowledge SDA held low A Not Acknowledge SDA released high S Start condition P Stop condition Sr Repeated Start condition R Read SDA released high W Write SDA held low Figure 5 19 I C bus activity notation 5 10 1 Master mode In this example an EEPROM device has been connected to channel 0 The EEPROM responds to the 7 bit slave address 1010xxxb During a read process the bits xxx can be any value During a write process i The bits xxx represent the EEPROM memory address bits a10 a9 and a8 ii The first byte after the slave address is the EEPROM memory address bits a7 to a0 The EEPROM has a write cycl
136. Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group amp direction amp buffer pull_up amp output Read the direction for pin P03 R_IO_PORT_ReadControl PDL_IO PORI 0 3 amp direction PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR Set the lower 4 bits on port P1 to output R_IO_PORT_ModifyControl PDL_IO_PORT_1 PDL_IO PORT DIRECTION PDL_IO_PORT_OR Ox0F Enable the pull up on pin PA3 R_IO_PORT_ModifyControl PDL_IO PORT _A_3 PDL_IO_PORT_PULL_UP PDL_IO_PORT_OR Figure 5 2 Example of I O Port Operations R20UT0084EE0004 Rev 0 04 Aug 25 2010 2 ENESAS Page 5 5 5 Usage Examples Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 3 Bus Controller 1 External bus CS area Figure 5 3 shows an example of external bus controller usage Peripheral driver function prototypes include r_pdl_bsc h include r_pdl_cgc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void BSC_error_handler void Clear the error signals R_BSC_Control PDL_BSC_ERROR_CLEAR di void main void uint8_t csl_location_8 uintl6_t cs7_location_16 csl_location_8 uint8_t 0x07000000ul1
137. RA OTARA ESEE aii 1 8 CiT Build Me ProjeCl Saa aaea eaaa ae RT EEE AR aE ARSA ETARE SAE AR A AREER ete 1 8 T2 Document SUCO eaa A EA E 1 9 1 3 Acronyms and abbreviations 0 0 0 cccccceecee sence ee eeeeeeeeeeeeeeeeeeeeeeeeeeneaeeeeeeneaeeeseeeaeeeseeaeeeseeaeeeeeeaees 1 10 2 DUn e A e attest iti date teeta iti diese tides niet indi eee 2 1 Zale OVEINIGWHicn ett ties Aidt A tities hee nat ee ee eee 2 1 2 2 Control Functions summa oaia a ela eee eee dea eel aes 2 1 2 3 Clock Generation Circuit Driver iv cicscctececccesteececetteesceteheedevet iaria aiii nipi iaai eaa 2 3 2 4 Interrupt Control Driver a ra sone ocecezaseceahten chaesssenedspnecatcntacecnsateascugazsauee asbecatdaass teehee a e aLe 2 4 2 08 1 POPE DIVE AE E E ites see E PE hawt ted E thee eagle in date aie ete ee 2 5 26 Port Funcion tonto DAVePreccsetvostetccid cect tetetccet hgoitekentd E 2 6 2f MCU Operation Driveri eiee ener a a ea a E dee A a a inde eee ela 2 7 2 8 Low Power Consumption Driver cccccceceeeeccceceeeeeeeeeccaeaaeceeeeeeeseccaaaeceeeeeseseccnaecaeeeeeseseesnnaeeees 2 8 2 9 Voltage Detection Circuit Driver eee ttre retiree tees eee ARa RR E pa AA ARNA AA 2 9 210 Bus Controler Driver 2nn acy chcahilih nich hil eee alc elias ate eae 2 10 2 11 DMA Controller Drivers cccccscccocecceececttencndet tence ce teuciecen eiia ainia ane TA aerea EA a eE TANEC TAKERE ENEE 2 11 2 12 External DMA Controller Driver ssesssiesrierrin
138. RI1 PDL_INTC_ VECTOR SPTI1 RSPI channel 1 Error Receive buffer full Transmit buffer empty PDL_INTC_VECTOR_TXFO PDL_INTC_VECTOR RXMO PDL_INTC_VECTOR_TXMO CAN channel 0 PDL_INTC_ VECTOR SPII1 Idle PDL_INTC_VECTOR_ERSO Error PDL_INTC_VECTOR_RXFO Receive FIFO Transmit FIFO Reception complete Transmission complete PDL_INTC_ VECTOR PRD PDL_INTC_ VECTOR CUP PDL_INTC_VECTOR ALM Real time clock Periodic Carry Alarm PDL_INTC_VECTOR_IRQO PDL_INTC_VECTOR _IRQ1 PDL_INTC_VECTOR IRQ2 PDL_INTC_VECTOR _IRQ3 PDL_INTC_VECTOR IRQ4 PDL_INTC_VECTOR _IRQ5 PDL_INTC_VECTOR IRQ6 PDL_INTC_VECTOR _IRQ7 PDL_INTC_VECTOR _IRQ8 PDL_INTC_VECTOR _IRQQ PDL_INTC_VECTOR IRQ10 PDL_INTC_VECTOR IRQ11 PDL_INTC_VECTOR IRQ12 PDL_INTC_VECTOR IRQ13 PDL_INTC_VECTOR IRQ14 PDL_INTC_VECTOR IRQ15 External interrupt pin Valid edge or level detected PDL_INTC_VECTOR WOVI Watchdog timer Overflow PDL_INTC_VECTOR_ADIO PDL_INTC VECTOR ADI 10 bit ADC Conversion completed R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 15 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference Description 2 3 PDL_INTC_VECTOR_ADI12_0 12 bit ADC Conve
139. RX621 Group 2 Driver 2 15 Port Output Enable Driver R20UT0084EE0004 Rev 0 04 Aug 25 2010 Se RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 16 Programmable Pulse Generator Driver The driver functions support the use of the pulse generator providing the following operations 1 Configuring the generator for use 2 Disabling groups of outputs that are no longer required 3 Control of the generator during run time R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 2 16 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 17 8 bit Timer Driver The driver functions support the use of the four 8 bit timers providing the following operations 1 2 9 Configuring a channel for use using register values which have been determined elsewhere Configuring two channels as a 16 bit pair using register values which have been determined elsewhere Configuration for as a periodic timer including Automatic clock setting using frequency or period as an input Automatic pulse width setting using pulse width or duty cycle as an input Automatic interrupt control I O pin control Automatic I O pin configuration Configuration for as a one shot timer including Automatic clock setting using pu
140. R_TGIA4 or PDL_DTC_TRIGGER_TGIAG or PDL_DTC_TRIGGER_TGIA7 or PDL_DTC_TRIGGER_TGIA8 or PDL_DTC_TRIGGER_TGIAQ or PDL_DTC_TRIGGER_TGIA10 or Compare match or input capture Aon MTU channel n n 0 to 4 or 6 to 10 PDL_DTC_ TRIGGER _TGIBO or PDL_DTC_TRIGGER_TGIB1 or PDL_DTC TRIGGER _TGIB2 or PDL_DTC_TRIGGER_TGIB3 or PDL_DTC_ TRIGGER _TGIB4 or PDL_DTC TRIGGER _TGIB6 or PDL_DTC_ TRIGGER _TGIB7 or PDL_DTC_TRIGGER_TGIB8 or PDL_DTC_TRIGGER_TGIB9 or PDL_DTC_TRIGGER_TGIB10 or Compare match or input capture B on MTU channel n n 0 to 4 or 6 to 10 PDL_DTC_ TRIGGER _TGICO or PDL_DTC_TRIGGER_TGIC3 or PDL_DTC_ TRIGGER _TGIC4 or PDL_DTC_TRIGGER_TGIC6 or PDL_DTC_ TRIGGER _TGIC9 or PDL_DTC_TRIGGER_TGIC10 or Compare match or input capture C on MTU channel n n 0 3 4 6 9 or 10 PDL_DTC_ TRIGGER _TGIDO or PDL_DTC_ TRIGGER _TGID3 or PDL_DTC_ TRIGGER _TGID4 or PDL_DTC_ TRIGGER _TGID6 or PDL_DTC_ TRIGGER _TGID9 or PDL_DTC_TRIGGER_TGID10 or Compare match or input capture D on MTU channel n n 0 3 4 6 9 or 10 PDL_DTC_ TRIGGER _TGIU5 or PDL_DTC_TRIGGER_TGIU11 or Compare match or input capture U on MTU channel n n 5 or 11 PDL_DTC_TRIGGER_TGIV5 or PDL_DTC_TRIGGER_TGIV11 or Compare match or input capture V on MTU channel n n 5 or 11 PDL_DTC_TRIGGER_TGIW5 or PDL
141. R_WDT_Create Remarks e Ifthe flag is set to 1 it shall be automatically cleared to O by this function Program example RPDL definitions include r_pdl_wdt h RPDL device specific definitions include r_pdl_definitions h uint8_t Flags void func void Read the timer values R_WDT_Read amp Flags R20UT0084EE0004 Rev 0 04 Aug 25 2010 ieee E e RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group EE E enes 4 2 19 Independent Watchdog Timer R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae Page 4 143 E ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 4 2 20 Serial Communication Interface 1 R_SCI Set Synopsis Prototype Description Return value Category Reference Remarks Program example Configure the SCI pin selection bool R_SCI Set uint8_t data Configuration Set up the global SCI options data Configure the global options Use to separate each selection e Pin selection required only if the pins are used for the SCI function PDL_SCI_PIN_SCI1_A or F PDL_SCI_PIN_SCI1_B Select the A or B pins for RxD1 SCK1 TxD1 PDL_SC
142. Read Write and Modify functions use one of the following register definitions IR register definitions PDL_INTC_REG IR _BSC_BUSERR PDL_INTC_REG IR ADO ADI PDL_INTC_REG IR_FCU FIFER PDL_INTC_REG IR_AD1 ADI PDL_INTC_REG IR _FCU FRDY PDL_INTC_ REG IR_S12AD ADI PDL_INTC_REG IR_ICU_SWINT PDL_INTC_REG IR_MTUO TGIA PDL_INTC_REG IR CMTO CMI PDL_INTC_REG IR_MTUO TGIB PDL_INTC_REG IR_CMT1_CMI PDL_INTC_REG IR MTUO TGIC PDL_INTC_REG IR_CMT2 CMI PDL_INTC_REG IR_MTUO TGID PDL_INTC_REG IR CMT3 CMI PDL_INTC_REG_IR_MTUO TCIV PDL_INTC_REG IR ETHER EINT PDL_INTC_REG IR_MTUO TGIE PDL_INTC_REG IR _USBO_DOFIFO PDL_INTC_REG IR MTUO TGIF PDL_INTC_REG IR USBO_D1FIFO PDL_INTC_REG IR MTU1 TGIA PDL_INTC REG IR USBO USBI PDL_INTC_REG IR_MTU1 TGIB PDL_INTC_REG IR _USB1 DOFIFO PDL_INTC_REG_IR_MTU1_TCIV PDL_INTC_REG IR_USB1_D1FIFO PDL_INTC_REG IR _MTU1_TCIU PDL_INTC_REG IR _USB1 USBI PDL_INTC_REG IR_MTU2 TGIA PDL_INTC REG IR SPIO SPEI PDL_INTC_REG IR _MTU2 TGIB PDL_INTC_ REG IR SPIO SPRI PDL_INTC_REG IR MTU2 TCIV PDL_INTC REG IR SPIO SPTI PDL_INTC_REG_IR_MTU2 TCIU PDL_INTC_REG IR SPIO SPI PDL_INTC_REG IR_MTU3 TGIA PDL_INTC_REG IR SPI1_SPEI PDL_INTC_REG IR_MTU3 TGIB PDL_INTC_ REG IR _SPI1_ SPRI PDL_INTC_REG IR MTU3 TGIC PDL_INTC_REG IR SPI1_SPTI PDL_INTC_REG IR_MTU3 TGID PDL_INTC_REG IR_SPI1_SPIl PDL
143. SCI_Receive 1 PDL_NO_DATA amp result 1 PDL_NO_FUNC PDL_NO_FUNC Check that channel 0 has completed do R_SCI_GetStatus 0 amp result PDL_NO_PTR PDL_NO_PTR while result amp 0x10 0 Shut down channel 0 R_SCI_Destroy 0 3 SCI channel 0 receive data handler void SCIORxFunc void char str_ptr rx_string while str_ptr 0 Process the string contents SCI channel 0 error handler void SCIOErrFunc void uint8_t error_flags Read the status R_SCI_Get Status 0 amp error_flags PDL_NO_PTR PDL_NO_PTR Overrun error if error_flags amp 0x20 System_failed Figure 5 13 Example of SCI Reception code R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 5 27 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Weagekxamplez 2 SCI Transmission Figure 5 14 shows the configuration of SCI channels 0 and 1 and the transmission of data on channel 0 using polling and then interrupts Peripheral driver function prototypes include r_pdl_sci h include r_pdl_cgc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Callback function prototype void SCIOTxFunc void volatile char result
144. T0084EE0004 Rev 0 04 Aug 25 2010 ieee RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Apiary E enes 3 R_CRC Write Synopsis Write data into the CRC calculation register Prototype bool R_CRC_Write uint8_t data The data to be used for the calculation Description Write the data into the data input register data The data to be written into the register Return value True Category CRC Reference R_CRC_Create Remarks e None Program example RPDL definitions include r_crc h RPDL device specific definitions include r_pdl_definitions h void func void Write FOh into the CRC calculation register R_CRC_Write OxFO R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae Page 4 159 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group dieing Resrenes 4 R_CRC_Read Synopsis Read the CRC calculation result Prototype bool R_CRC_Read uint8_t data1 Control uint16_t data2 Data storage location 3 Description Reads and stores the CRC calculation result data1 Control the behaviour of the CRC unit The default setting is shown in bold Specify PDL_NO_DATA to use the default e Res
145. TC TRIGGER USB1 D1 or D1FIFO transfer request on USB port n n 0 to 1 PDL_DTC_ TRIGGER _SPIO_RX or PDL_DTC_TRIGGER_SPI1_RXor Receive buffer full on RSPI channel n n 0 to 1 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference Description 2 3 PDL_DTC_TRIGGER_SPIO_TX or R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 74 PDL_DTC_ TRIGGER_SPI1_TX or Transmit buffer empty on RSPI channel n n 0 to 1 PDL_DTC_TRIGGER_IRQO or PDL_DTC_ TRIGGER _IRQ1 or PDL_DTC_ TRIGGER _IRQ2 or PDL_DTC_TRIGGER_IRQ3 or PDL_DTC_TRIGGER_IRQ4 or PDL_DTC_TRIGGER_IRQ5 or PDL_DTC_ TRIGGER _IRQ6 or PDL_DTC_TRIGGER_IRQ7 or PDL_DTC_TRIGGER_IRQ8 or PDL_DTC_TRIGGER_IRQ9 or PDL_DTC_ TRIGGER _IRQ10 or PDL_DTC_TRIGGER_IRQ11 or PDL_DTC_TRIGGER_IRQ12 or PDL_DTC_ TRIGGER _IRQ13 or PDL_DTC_ TRIGGER _IRQ14 or PDL_DTC_ TRIGGER _IRQ15 or Valid edge detected on pin IRQn n 0 to 15 PDL_DTC_ TRIGGER _ADIO or PDL_DTC_TRIGGER_ADI1 or Conversion completed on 10 bit ADC unit n n 0 to 1 PDL_DTC_TRIGGER_ADC12 or Conversion completed on 12 bit ADC unit PDL_DTC_TRIGGER_TGIAO or PDL_DTC_ TRIGGER TGIA1 or PDL_DTC_ TRIGGER _TGIA2 or PDL_DTC_TRIGGER_TGIA3 or PDL_DTC_TRIGGE
146. TEI1 End of data transfer PDL_INTC_VECTOR_ERI2 Error in data received PDL_INTC_VECTOR_RXI2 SCI channel 2 Data received PDL_INTC_VECTOR_TXI2 Start of next data transfer PDL_INTC_VECTOR_TEI2 End of data transfer PDL_INTC_VECTOR_ERI3 Error in data received PDL_INTC_VECTOR_RXI3 SCI channel 3 Data received PDL_INTC_VECTOR_TXI3 Start of next data transfer PDL_INTC_VECTOR_TEI3 End of data transfer PDL_INTC_VECTOR_ERI5 Error in data received PDL_INTC_VECTOR_RXI5 SCI channel 5 Data received PDL_INTC_VECTOR_TXI5 i Start of next data transfer PDL_INTC_VECTOR_TEI5 End of data transfer PDL_INTC_VECTOR_ERI6 Error in data received PDL_INTC_VECTOR_RXI6 SCI channel 6 Data received PDL_INTC_VECTOR_TXI6 Start of next data transfer PDL_INTC_VECTOR_TEI6 End of data transfer PDL_INTC_VECTOR_ICEEI0 PC bus Transfer error or event generation PDL_INTC_VECTOR_ICRXI0O interface Data received PDL_INTC_VECTOR_ICTXIO channel 0 Start of next data transfer PDL_INTC_VECTOR_ICTEI0O End of data transfer PDL_INTC_VECTOR_ICEEI1 PC bus Transfer error or event generation PDL_INTC_VECTOR_ICRXI1 interfac Data received PDL_INTC_VECTOR_ICTXI1 channel 1 Start of next data transfer PDL_INTC_VECTOR_ICTEI1 End of data transfer True Interrupt control e The fast interrupt processing is allocated to only one interrupt handler Open the file r_pdl_user_definitions h and edit the definition FAST_INTC_VECTOR to give it the same value as the interrupt vector u
147. TENDED Select the minimum or extended delay between the assertion of the SSL pin and the start of RSPCK oscillation SSL negation delay PDL_SPI_SSL_DELAY_1 or PDL_SPI_SSL_DELAY_EXTENDED Select the minimum or extended delay between the end of RSPCK oscillation and the negation of the active SSL pin Next access delay PDL_SPI_NEXT_DELAY_1 or PDL_SPI_NEXT_DELAY_EXTENDED frame Select the minimum or extended delay between the end of one frame and the start of the next data5 Select the automatic data transfer options The default setting is shown in bold Specify PDL_NO_DATA to use the default Return value DMAC DTC trigger control PDL_SPI_TX_DMAC_DTC_TRIGGER_DISABLE or PDL_SPI_TX_DMAC_TRIGGER_ENABLE or PDL_SPI_TX_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC for data transmission PDL_SPI_RX_DMAC_DTC_TRIGGER_DISABLE or PDL_SPI_RX_DMAC_TRIGGER_ENABLE or PDL_SPI_RX_ DTC TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC when a reception transfer is complete True if all parameters are valid otherwise false Category SPI Reference R_SPI_Create Remarks e For Slave mode operation configure command 0 Avoid selecting mode 0 or mode 2 when Clock synchronous Slave mode is used R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 184 Under development Preliminary Specification Sp
148. TIOC9D PDL MTU OUT BUFFER P PHASE 2 LOW or PDL_MTU_OUT BUFFER _P_PHASE_2 HIGH For n 0 MTIOC4A For n 1 MTIOC10A PDL MTU OUT BUFFER N PHASE 2 LOW or PDL MTU OUT BUFFER N PHASE 2 HIGH For n 0 MTIOC4C For n 1 MTIOC10C PDL MTU OUT BUFFER P PHASE 3 LOW or PDL_MTU_OUT_BUFFER_P_PHASE_3 HIGH For n 0 MTIOC4B For n 1 MTIOC10B PDL MTU OUT BUFFER N PHASE 3 LOW or PDL MTU _OUT BUFFER _N PHASE 3 HIGH For n 0 MTIOC4D For n 1 MTIOC10D Set the transfer timing In complementary PWM mode PDL_MTU_OUT_BUFFER_TRANSFER_DISABLE or Disable or enable on detection of PDL_MTU_OUT_BUFFER_TRANSFER_CREST or crest PDL_MTU_OUT_BUFFER_TRANSFER_TROUGH or trough or PDL_MTU_OUT_BUFFER_TRANSFER_BOTH both In Reset synchronised PWM mode PDL_MTU_OUT_BUFFER_TRANSFER_DISABLE or PDL_MTU_OUT_ BUFFER _TRANSFER_CLEAR Disable or enable on counter clear Buffer transfer to temporary transfer control PDL_MTU_BUFFER_TRANSFER_DISABLE or PDL_MTU_BUFFER_TRANSFER_ENABLE or PDL_MTU_BUFFER_TRANSFER_LINK Disable transfers enable without linking to interrupt skipping or enable and link to interrupt skipping R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 97 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Description 3 4 R20UT0084EE0004 Rev 0
149. U registers R_MCU_Control None RPDL definitions include r_pdl_mcu h RPDL device specific definitions include r_pdl_definitions h void func void uintl6_t status Read the MCU status registers R_MCU_GetStatus amp status i 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 4 2 6 Low Power Consumption 1 R_LPC _ Create Synopsis Prototype Description 1 2 Configure the MCU low power conditions bool R_LPC_Create uint32_t data1 Configuration options uint32_t data2 Waiting times Load the registers that control module or CPU operation data1 Select the required settings If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Software and Deep Software Standby mode output port control PDL_LPC_EXT_BUS_ONor Leave the external bus address and control signals active or PDL_LPC EXT BUS HI Z set them to the high impedance state On chip RAM power USB resume detection control PDL_LPC_RAM_USB_DETECT_ON or Enable or disable power to the RAM from PDL_LPC_RAM_USB_DETECT_OFF 00000000h to OOOOFFFFh and USB resume detection function in deep software standby mode I O port retention
150. UT or PDL_1O_ PORT OUTPUT Input or output e Input buffer control PDL_IO_PORT_INPUT_BUFFER_ON or PDL_IO_PORT_INPUT_BUFFER_OFF On or off e Input pull up resistor control PDL_IO_PORT_PULL_UP_ON or PDL_IO PORT PULL_UP_OFF On or off Valid for ports 9 to E and G e Output type control PDL_IO_PORT_OPEN_DRAIN or NMOS open drain or CMOS push pull output PDL_IO_PORT_CMOS Valid for ports 0 to 3 and C Return value True if all parameters are valid and exclusive otherwise false Functionality I O port References R_IO_PORT_ModifyControl R_IO_PORT_ReadControl Remarks Ensure that the specified functions are valid for the selected port pin e The data direction and input buffer registers may be modified by other driver Create functions Take care to not overwrite existing settings Program example RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Set up port P93 as an input port with the pull resistor on R_IO_PORT_Set PDL_IO_PORT_9_3 PDL_IO_PORT_INPUT PDL_IO_PORT_INPUT_BUFFER_ON PDL_TO_PORT_PULL_UP_ON R20UT0084EE0004 Rev 0 04 Aug 25 2010 ieee RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Re
151. WeageExamplez 5 Usage Examples This chapter shows programming examples for each driver in this library R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 5 1 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 WeageExamplez 5 1 Interrupt control Figure 5 1 shows an example of external interrupt use Pin IRQO A is used to detect a falling edge and generates an interrupt Pin IRQ1 B is used to detect a falling edge and is polled Pin IRQ2 A is used to detect a low level signal and generates an interrupt Further interrupts are prevented until the signal has returned to the high level Peripheral driver function prototypes include r_pdl_intc h include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h volatile uint8_t switch_swl_pressed volatile uint8_t irgq2_low Callback function prototypes void IRQOHandler void void IRQOHandler void static void ReEnableIRQ2 void void main void uint8_t irq_status Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Configure the IRQO interrupt on pin IRQO A R_INTC_CreateExtInterrupt PDL_INTC_IRQO PDL_INTC_FALLING PDL_INTC_A 7 IRQOHandler di Configure the IRQ1 interrupt on pin IRQI B R_INTC_CreateExtInt
152. World volatile uint8_t destination_string_1 volatile uint8_t destination_string_2 void main void uint8_t StatusValue uint32_t SourceAddr uint32_t DestAddr uint16_t TransferCount uint16_t SizeCount Initialise the system clocks R_CGC_Set 12 5E6 100E6 50E6 PDL_NO_DATA PDL_CGC_BCLK_DISABLI Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Enable control of LEDO R_IO_PORT_Set PDL_IO_PORT_3_6 PDL_IO_PORT_OUTPUT 0 0 0 Configure channel 0 R_DMAC_Create 0 R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae ENESAS Page 5 12 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Usage Examples PDL_DMAC_BLOCK PDL_DMAC_SOURCE ESS_PLUS PDL_DMAC_DESTINATION_ADDRESS_PLUS PDL_DMAC_SIZE_8 PDL_DMAC_IRQ_ PDL_DMAC_TRIGGER_IRQ3 source_string_l destination_string_l 1 uintl6_t strlen source_string_l PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA DMACO_transfer_end_handler 7 Configure channel 1 R_DMAC_Create 1 PDL_DMAC_BLOCK PDL_DMAC_SOURC ESS PLUS PDL_DMAC_DESTINATION_ADDRESS_PLUS PDL_DMAC_SIZ PDL_DMAC_TRIGGER_SW source_string_2 destination_string_2 uintl6_t strlen source_string_2 1 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_
153. X621 Group 1 R_PFC_Read Synopsis Prototype Description Return value Functionality References Remarks Program example Read a PFC register bool R_PFC_Read uint8_t data1 uint8_t data2 II PFC register selection Get the value of a PFC register data1 One of the definition values from 4 2 4 data2 The value read from the register True if a valid register is specified otherwise false PFC reg isters R_PFC_Write None RPDI L definit ions include r_pdl_pfc h RPDI L device specific definitions include r_pdl_definitions h void func void uint8_t data Get th R_PFC_Read PDL_PFC_PFBTMR amp data R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 38 value of register PFBTMR 7tENESAS 4 Library Reference II Pointer to the variable where the PFC register s value shall be stored Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 R_PFC_Write Synopsis Prototype Description Return value Functionality References Remarks Program example Write to a PFC register bool R_PFC_Write uint8_t data1 uint8_t data2 II PFC
154. _ TCIV4 Multi function Timer Pulse Unit channel 4 Compare match or Input capture A Compare match or Input capture B Compare match or Input capture C Compare match or Input capture D Overflow PDL_INTC_VECTOR_TGIU5 PDL_INTC_VECTOR_TGIV5 PDL_INTC_VECTOR_TCIW5 Multi function Timer Pulse Unit channel 5 Compare match or Input capture U Compare match or Input capture V Compare match or Input capture W PDL_INTC_VECTOR_ TGIAG PDL_INTC_VECTOR TGIB6 PDL_INTC_ VECTOR TGIC6 PDL_INTC_ VECTOR TGID6 PDL_INTC_VECTOR_TCIV6 PDL_INTC_VECTOR TGIE6 PDL_INTC_VECTOR TGIF6 Multi function Timer Pulse Unit channel 6 Compare match or Input capture A Compare match or Input capture B Compare match or Input capture C Compare match or Input capture D Overflow Compare match E Compare match F PDL_INTC_VECTOR_TGIA7 PDL_INTC_VECTOR TGIB7 PDL_INTC_VECTOR_TCIV7 PDL_INTC_VECTOR_TCIU7 Multi function Timer Pulse Unit channel 7 Compare match or Input capture A Compare match or Input capture B Overflow Underflow PDL_INTC_VECTOR TGIA8 PDL_INTC_VECTOR TGIB8 PDL_INTC_VECTOR TCIV8 PDL_INTC_VECTOR_TCIU8 Multi function Timer Pulse Unit channel 8 Compare match or Input capture A Compare match or Input capture B Overflow Underflow PDL_INTC_VECTOR_TGIAQ PDL_I
155. _DIV_2 Select the clock source internal reference clock 1 or 2 for the SDA output delay counter R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 161 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 fabranyReterenee Description 2 3 e Noise filter control PDL_IIC_NF_DISABLE or PDL_IIC_NF_1 or PDL_IIC_NF_2 or Select the number of stages in the noise filter PDL_IIC_NF_3 or PDL_IIC_NF_4 data3 Detection settings Specify PDL_NO_DATA to use the defaults e NACK Transmission Arbitration Lost Detection control PDL_IIC_NTALD_DISABLE or Disable or enable arbitration to be lost when an ACK is PDL_IIC_NTALD_ENABLE detection during transmission of a NACK in receive mode e Slave Arbitration Lost Detection control PDL_IIC_SALD_DISABLE or Disable or enable arbitration to be lost when a mismatch PDL_IIC_SALD_ENABLE occurs during slave data transmission e Slave address detection control PDL_IIC_SLAVE_0 DISABLE or Disable or enable detection of slave address 0 in PDL_IIC_SLAVE_0_ ENABLE 7 or 7 bit or PDL_IIC_SLAVE 0 ENABLE 10 10 bit format PDL_IIC_SLAVE_1_DISABLE or Disable or enable detection of slave address 1 in PDL_IIC_SLAVE_1_ENABLE _7 or 7 bit or PDL_IIC_SLAVE_ 1 ENABLE 10 10 bit format PDL_IIC_SLAVE_2 DISABLE or Disable or enable detectio
156. _DTC_TRIGGER_TGIW11 or Compare match or input capture W on MTU channel n n 5 or 11 PDL_DTC TRIGGER _TCIV4 or PDL_DTC_TRIGGER_TCIV10 or Counter overflow or underflow on MTU channel n n 4 or 10 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference Description 3 3 PDL_DTC_TRIGGER_CMIAO or Return value PDL_DTC_TRIGGER_CMIA1 or PDL_DTC_TRIGGER_CMIA2 or PDL_DTC_ TRIGGER _CMIA3 or Compare match A on TMR channel n n 0 to 3 PDL_DTC_ TRIGGER _CMIBO or PDL_DTC_ TRIGGER _CMIB1 or PDL_DTC_ TRIGGER _CMIB2 or PDL_DTC_TRIGGER_CMIB3 or Compare match B on TMR channel n n 0 to 3 PDL_DTC_TRIGGER_DMACIO or PDL_DTC_TRIGGER_DMACI1 or PDL_DTC_TRIGGER_DMACI2 or PDL_DTC_TRIGGER_DMACI3 or Transfer complete on DMAC channel n n 0 to 3 PDL_DTC_TRIGGER_EXDMACIO or PDL_DTC_TRIGGER_EXDMACI1 or Transfer complete on EXDMAC channel n n 0 to 1 PDL_DTC_TRIGGER_RXIO or PDL_DTC_TRIGGER_RXI1 or PDL_DTC_TRIGGER_RXI2 or Receive buffer full on SCI channel n PDL_DTC_TRIGGER_RXI3 or n 0 to 3 or 5 to 6 PDL_DTC_TRIGGER_RXI5 or PDL_DTC_TRIGGER_RXI6 or PDL_DTC_TRIGGER_TXIO or PDL_DTC_TRIGGER_TXI1 or PDL_DTC_TRIGGER_TXI2 or Transmit buffer empty on SCI channel n PDL_DTC_TRIGGER_TXI3 or n 0 to
157. _IC_BOTH EDGES or Input capture at MTICnW rising edge Input capture at MTICnW falling edge Input capture at MTICnW both edges PDL_MTU_W_IC_PWM_LOW_TROUGH or PDL_MTU_W_IC_PWM_LOW_CREST or PDL_MTU_W_IC_PWM_LOW_BOTH or Input capture at trough crest or both for low pulse width measurement PDL_MTU_W_IC_PWM_HIGH_ TROUGH or PDL_MTU_W_IC_PWM_HIGH_CREST or PDL_MTU_W_IC_PWM_HIGH BOTH Input capture at trough crest or both for high pulse width measurement data9 For n 0 to 4 or 6 to 10 The timer counter TCNT For n 5 or 11 The timer counter TCNTU value data10 value For n 0 to 4 or 6 to 10 The register TGRA value For n 5 or 11 The timer counter TCNTV value data11 For n 0 to 4 or 6 to 10 The register TGRB value For n 5 or 11 The timer counter TCNTW value data12 For n 0 3 4 6 9 or 10 The register TGRC value For n 5 or 11 The register TGRU value Ignored for n 1 2 7 or 8 data13 For n 0 3 4 6 9 or 10 The register TGRD value For n 5 or 11 The register TGRV value Ignored for n 1 2 7 or 8 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Apiary E enes Description 8 8 data14 For n 0 or 6 The register TGRE value For n 5 or 11 The register TGRW value Ignored for n 1 2 3 4 7 8 9 or 10
158. _INTC_REG_IR_MTU3 TCIV PDL_INTC_REG IR CANO ERS PDL_INTC_REG IR MTU4 TGIA PDL_INTC_REG IR CANO RXF PDL_INTC_REG IR MTU4 TGIB PDL_INTC_REG IR_CANO TXF PDL_INTC_REG IR _MTU4 TGIC PDL_INTC_REG_IR_CANO _RXM PDL_INTC_REG IR_MTU4 TGID PDL_INTC_REG IR_CANO TXM PDL_INTC_REG IR_MTU4 TCIV PDL_INTC_REG IR RTC PRD PDL_INTC_REG IR MTU5 TGIU PDL_INTC_REG IR RTC CUP PDL_INTC_REG IR MTU5 TGIV PDL_INTC_REG IR_ICU_IRQO PDL_INTC_REG IR MTU5 TGIW PDL_INTC_REG IR_ICU_IRQ1 PDL_INTC_REG IR_MTU6 TGIA PDL_INTC_REG IR_ICU_IRQ2 PDL_INTC_REG IR_MTU6 TGIB PDL_INTC_REG IR_ICU_IRQ3 PDL_INTC_REG IR MTU6 TGIC PDL_INTC REG IR ICU _IRQ4 PDL_INTC_REG IR_MTU6 TGID PDL_INTC_REG IR_ICU_IRQ5 PDL_INTC_REG IR _MTU6 _TCIV PDL_INTC_REG IR_ICU_IRQ6 PDL_INTC_REG IR MTU6 TGIE PDL_INTC_REG IR_ICU_IRQ7 PDL_INTC_REG IR MTU6 TGIF PDL_INTC_REG IR_ICU_IRQ8 PDL_INTC_REG IR_MTU7 TGIA PDL_INTC_REG IR_ICU_IRQQ PDL_INTC_REG IR_MTU7 TGIB PDL_INTC_ REG IR_ICU_IRQ10 PDL_INTC_REG IR _MTU7_TCIV PDL_INTC_ REG IR_ICU_IRQ11 PDL_INTC_REG IR _MTU7_TCIU PDL_INTC_REG IR_ICU_IRQ12 PDL_INTC_REG IR_MTU8 TGIA PDL_INTC REG IR_ICU_IRQ13 PDL_INTC_REG IR _MTU8 TGIB PDL_INTC_ REG IR_ICU_IRQ14 PDL_INTC_REG IR _MTU8 TCIV PDL_INTC_REG IR_ICU_IRQ15 PDL_INTC_REG IR MTU8 TCIU PDL_INTC_REG IR USB _USBRO PDL_INTC_REG IR_MTU9 TGIA PDL_INTC_REG
159. _MasterReceive 0 P DL_IIC_DTC_TRIGG EPROM_ADDRESS DL_NO_PTR PDL_NO_FUNC di while bus_busy true void iic_tx_dtc_end_handler void uint32_t status_flags 0 Wait for the transmission to complete R20UT0084EE0004 Rev 0 04 Aug 25 2010 Lays 7tENESAS 5 Usage Examples Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group amp Weagakexamplee R_IIC_GetStatus 0 amp status_flags PDL_NO_PTR PDL_NO_PTR while status_flags amp 0x00000080ul 0x0u Issue a Stop condition on channel 1 R_IIC_Control 0 PDL_IIC_STOP bus_busy false void iic_rx_dtc_end_handler void uint32_t DestAddr 0 Read the next destination address for the current transfer R_DTC_GetStatus dtc_iicl_rx_transfer_data PDL_NO_PTR PDL_NO_PTR amp DestAddr PDL_NO_PTR PDL_NO_PTR Read one more byte with NACK condition on channel 1 and stop R_IIC_MasterReceiveLast 0 uint8_t DestAddr bus_busy false Figure 5 27 An example of write data to and reading data from an EEPROM using two DMAC channels R20UT0084EE0004 Rev 0 04 Aug 25 2010 AS Page 5 48 KENES Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Grou
160. _OVERLAP Select overlapping Compare Match A or non overlapping Compare Match A or B operation Invert control PDL_PPG_DIRECT or PDL_PPG_INVERT Select direct or inverted output Return value Category Reference data3 The initial and next output values for the enabled pins using the following format b7 b6 b5 b4 b3 b2 b1 bO Group Next pulse output values Initial output values 0 PO3 PO2 PO1 POO PO3 PO2 PO1 POO 1 PO7 PO6 PO5 PO4 PO7 PO6 PO5 PO4 2 PO11 PO10 PO9 PO8 PO11 PO10 PO9 PO8 3 PO15 PO14 PO13 PO12 PO15 PO14 PO13 PO12 4 PO19 PO18 PO17 PO16 PO19 PO18 PO17 PO16 5 PO23 PO22 PO21 PO20 PO23 PO22 PO21 PO20 6 PO27 PO26 PO25 PO24 PO27 PO26 PO25 PO24 7 PO31 PO30 PO29 PO28 PO31 PO30 PO29 PO28 True if all parameters are valid and exclusive otherwise false Programmable Pulse Generator R_PPG_Control Remarks Program example R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 106 If more than one group must be configured use multiple calls of this function The applicable PPG unit 0 or 1 is brought out of the stop state e This function disables the alternative modes on each PO pin that is enabled v include r_pdl_ppg h void func void Configure PPG outputs PO4 and PO6 group 1 R_PPG_Create
161. _PPG_Create True if the unit selection is valid otherwise false Programmable Pulse Generator If all the outputs in a unit become disabled that unit will be put into the stop state to reduce power consumption R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 107 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Grou P P 4 Library Reference Program example include r_pdl_ppg h void func void Disable outputs PO24 and PO26 R_PPG_Dest roy PDL_PPG_PO24 PDL_PPG_PO26 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 108 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group dieing Resrenes 3 R_PPG_Control Synopsis Control a PPG group Prototype bool R_PPG_Control uint32_t data1 Group selection uint8_t data2 Next output values 3 Description Set the next output for a PPG group data1 Select the group s to be modified If multiple selections are required use to separate each selection e Group selection PDL_PPG_GROUP_0 or PDL_PPG_GROUP_1 or PDL_PPG_GROUP_2 or PDL_PPG_GROUP_3 or If a pair of groups 0 1 2 3 4 5 or 6 7 is using the same output PDL_PPG_GROUP_4 or trigger both groups may be selected PDL_PPG_GROUP_5 or PDL
162. _PPG_GROUP_6 or PDL_PPG_GROUP_7 data2 The next output values either for a single group or a pair of groups using the format Group 1 3 5 or 7 Group 0 2 4 or 6 Group pair b7 b6 b5 b4 b3 b2 b1 bO 1 amp 0 PO7 PO6 PO5 PO4 PO3 PO2 PO1 POO 3 amp 2 PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 5 amp 4 PO23 PO22 PO21 PO20 PO19 PO18 PO17 PO16 7 amp 6 PO31_ PO30 PO29 PO28 PO27 PO26 PO25 PO24 Return value True if all parameters are valid and exclusive otherwise false Category Programmable Pulse Generator Reference R_PPG_Create Remarks e None Program example RPDL definitions include r_pdl_ppg h RPDL device specific definitions include r_pdl_definitions h void func void Load the next output values on group 6 R_PPG_Control PDL_PPG_GROUP_6 0x07 i R20UT0084EE0004 Rev 0 04 Aug 25 2010 Seater RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Airing Resrsnes 4 2 15 8 bit Timer 1 R_TMR Set Synopsis Configure the optional TMR pins Prototype bool R_TMR_Sei uint8_t data Configuration Description Set up the global TMR options data Configure the global options Use to separate each selection e Pin selec
163. _PT L_NO_PT L_NO_PT L_NO_PT L_NO_PT L_NO_PT L_NO_PT L_NO_PT L_NO_PT L_NO_PT oN NN aa oN ON ONONOUS DADA DDADADWDWADD DD x x f L_NO_FU D P UV UGUO UQ GO GLU GODU O O W he wy yY y w yY y w w wi Dy Z Q 4 Library Reference Transmit all data once and replace it with the data received R_S PI_Transfer 0 amp command_0_data amp command_0_data amp command_1_data amp command_1_data amp command_2_ data amp command_2_ data amp command_3_data amp command_3_ data amp command_4 data amp command_4 data amp command_5_ data amp command_5_ data amp command_6_data amp command_6_data amp command_7_data amp command_7_data 1 PDL_NO_FUNC 0 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group dieing Resrenes 6 R_SPI_GetStatus Synopsis Check the status of an SPI channel Prototype bool R_SPI_GetStatus uint8_t data1 Channel selection uint16_t data2 Status flags uint16_t data3 Sequence count Description Acquires the SPI channel status data1 Select channel SPIn where n 0 to 1 data2 The status flags shall be stored in the format below Specify PDL_NO_PTR if this information is not required b15 b14 b1
164. _PTR L_NO_PTR L_ NO_DATA L_NO_PTR L_NO_PTR L_NO_DATA transmission_completed false reception_completed false while 1 Any bus activity if transmission_completed true reception_completed true Read the status flags R_IIC_GetStatus SLAVE_CHANNEL amp status_flags PDL_NO_PTR PDL_NO_PTR transmission_completed true Which address was detected if status_flags amp 0x0001 0x0u Prepare the next data for the Master R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 5 52 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Weageexamplee R_DMAC_Control PDL_DMAC_3 PDL_DMAC_SUSPEND PDL_DMAC_ENABLE PDL_DMAC_UPDATE_SOURCE PDL_DMAC_UPDAT L_DMAC_CLEAR_DREQ L_NO_DATA L_NO_DATA else if status_flags amp 0x0002 0x0u Prepare the next data for the Master R_DMAC_Control PDL_DMAC_3 PDL_DMAC_SUSPEND PDL_DMAC_ ENABLE L DMAC_UPDATE_SOURCE PDL_DMAC_UPDAT L DMAC_CLEAR_DREQ L NO DATA Bi p p pP D D D D lave_data_storage_l D U D D D PDL_NO_DATA transmission_completed false else if reception_completed
165. _TRIGGER_IRQO OxOOOOAAO0O 0x0000BB00 10 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_FUNC 0 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 65 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 aban Reierenc 2 R_DMAC_ Destroy Synopsis Disable the DMA controller Prototype bool R_DMAC_Destroy uint8_t data Channel number Description Shutdown the DMAC module data The channel number n where n 0 to 3 Return value True if the shutdown succeeded otherwise false Category DMA controller Reference R_DMAC_Create R_LDMAC_Control Remarks e If all channels have been suspended the DMAC module will be shut down Disabling the DMAC module will also shut down the DTC e If another peripheral is being used to trigger a DMA transfer stop the triggers from that peripheral using Control or Destroy for that peripheral before calling this function Program example RPDL definitions include r_pdl_dmac h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown channel 2 R_DMAC_Destroy 2 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 66 RENESAS Under development Preliminary Specification Specifications in this
166. _array_2 PDL_NO_PTR 8 PDL_NO_DATA dF Write the data into the EEPROM write_eeprom_data Clear the data storage area for i 0 i lt 20 i data_storage i 0x00 Reset the EEPROM sub address to 0 using polling R_IIC_MasterSend 0 PDL_IIC_STOP_DISABL EPROM_ADDRESS eeprom_data_array_l R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 5 46 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 1 PDL_NO_FUNC 0 Read data from the EEPROM on channel 1 using the DTC read_eeprom_data Prepare the next data R_DTC_Control PDL_DTC_UPDATE_DESTINATION PDL_DTC_UPDAT dtc_iicl_rx_transfer_data PDL_NO_PTR amp data_storage 5 5 PDL_NO_DATA Read data from the EEPROM on channel 1 using the DTC read_eeprom_data static void write_eeprom_data void bus_busy true Send data to the EEPROM on channel 1 using the DTC R_IIC_MasterSend 0 PDL_IIC_DTC_TRIGG EEPROM_ADDRESS PDL_NO_PTR 0 PDL_NO_FUNC 0 dF while bus_busy true Wait for 5ms while the EEPROM updates R_CMT_CreateOneShot 0 r E 3 DL_NO_FUNC static void read_eeprom_data void bus_busy true Read data from the EEPROM on channel 1 using the DTC R_IIC
167. able direct loopback mode R_SPI_Control 0 PDL_SPI_LOOPBACK_DIRECT R20UT0084EE0004 Rev 0 04 Aug 25 2010 Sanger RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Synopsis Prototype Description 1 2 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 183 R_SPI_Command Configure an SPI command bool R_SPI_Create uint8_t data1 uint8_t data2 uint32_t data3 uint8_t data4 uint8_t data5 Select the options for a command data1 Select channel SPIn where n 0 to 1 data2 Select command n where n 0 to 7 data3 Select the command options If multiple selections are required use to separate each selection The default settings are shown in bold Clock phase and polarity 4 Library Reference Channel selection Command selection I Command options II Extended timing control II DMAC DTC control PDL_SPI_CLOCK_MODE_0 or PDL_SCI_CLOCK_MODE_1 or PDL SCI CLOCK MODE 2 or PDL_SCI CLOCK MODE 3 Clock is low when idle data is sampled on the rising edge Clock is low when idle data is sampled on the falling edge Clock is high when idle data is sampled on the falling edge Clock is high when idle data is sampled on the rising edge Clock division PDL_SPI_DIV_1 or PDL_SPI_DIV_2 or PDL_SPI_DIV_4 or
168. age 1 5 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 1 Introduction 1 1 5 Avoid conflicts with standard project files If the files intprg c or vecttbl c are included in the project remove or exclude them 1 Removal Use the key sequence Alt P R to open the Remove Project Files window Select the files and click on Remove Remove Project Files Project files OK C WorkSpace rpe C WorkSpace rpe Cancel C workSpace rpe C WorkSpace pe Remove C WorkSpace rpe C WorkSpace rpe C workS pace rpe Remove All C WorkSpace rpe C WorkSpace rpe C WorkSpace rpe C WorkSpace rpe C WworkSpace ipd C WorkSpace rpe C workSpace rpe C WorkSpace rpe C WorkSpace rp R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae ENESAS Page 1 6 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 1 Introduction 2 Exclusion Select the two files and use the key sequence Alt B to exclude them 3 rpdl_lib_test High performance Embedded Workshop File Edit View Project Build Debug Setup Tools Test Window Help source file 2 dbsctc Interrupt _ADC_10 c Interrupt_BSC c Interrupt_CMT c Interrupt DMAC c Interrupt_INTC c Interrupt_not_RPDL c Interrupt_SCl c Interrupt_TMF c Interrupt_TPU c Interr
169. al Interrupt R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae ENESAS Page 5 3 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Weagekxamplee 5 2 I O Port Figure 5 2 shows examples of I O port configuration reading and writing Peripheral driver function prototypes include r_pdl_io_port h include r_pdl_pfc h RPDL device specific definitions include r_pdl_definitions h void main void uint8_t result Configure port 4 as an input R_IO_PORT_Set PDL_IO_PORT_4 PDL_IO_PORT_INPU PDL_IO_PORT_INPU 0 0 Configure port pin P21 as an open drain output R_IO_PORT_Set PDL_IO_PORT_2_1 PDL_IO_PORT_OUTPUT 0 0 L_IO_POR EN_DRAIN Write 0x44 to register PFC2 R_PFC_Write 2 0x44 Read the value of all the pins on port 4 R_IO_PORT_Read PDL_IO_PORT_4 result Set pin P21 to output high R_IO_PORT_Write PDL_IO_PORT_2_1 1 Invert pin P21 R_IO_PORT_Modify PDL_IO_PORT_2_1 PDL_IO_PORT_XOR 1 And the value on port 4 with 55h R_IO_PORT_Modify PDL_IO_PORT_4 PDL_IO_PORT_AND 0x55 Read the control registers for port PC R_IO_PORT_ReadControli PDL_IO_PORT_1 R20UT0084EE0004 Rev 0 04 Aug 25 2010 7tENESAS Page 5 4 Under development
170. all time rate lt 400 kbps 300 ns 400 kbps lt rate lt 1 Mbps 120 ns Maximum rate 1 Mbps The achievable transfer rates are fect MHz IRC 50 48 12 5 12 32 8 PCLK 1 658 kbps to 1 635 6 kbps to 175 kbps to 1 168 5 kbps to 446 kbps to 1 116 kbps to 1 Mbps 1 Mbps Mbps 1 Mbps Mbps Mbps PCLK 2 316 kbps to 1 306 kbps to 1 86 7 kbps to 1 83 6 kbps to 1 217 kbps to 1 57 8 kbps to 1 Mbps Mbps Mbps Mbps Mbps Mbps PCLK 4 175 kbps to 1 168 5 kbps to 45 9kbpsto1 44 2 kbps to 1 116 kbps to 1 30 0 kbps to Mbps 1 Mbps Mbps Mbps Mbps 806 kbps PCLK 8 86 7 kbps to 1 83 6 kbps to 1 23 7 kbps to 22 7 kbps to 57 8 kbps to 1 15 3 kbps to Mbps Mbps 658 kbps 635 6 kbps Mbps 446 kbps PCLK 16 45 9 kbps to 1 44 2 kbps to 1 12 0 kbps to 11 5 kbps to 30 0 kbps to 7 73 kbps to Mbps Mbps 316 kbps 306 1 kbps 806 kbps 217 kbps PCLK 32 23 7 kbps to 22 7 kbps to 6 06 kbps to 5 8 kbps to 15 3 kbps to 3 89 kbps to 658 kbps 635 6 kbps 175 kbps 168 5 kbps 446 kbps 116 kbps PCLK 64 12 0 kbps to 11 5 kbps to 3 04 kbps to 2 9 kbps to 7 73 kbps to 1 95 kbps to 316 kbps 306 1 kbps 86 7 kbps 83 6 kbps 217 kbps 57 8 kbps PCLK 128 6 06 kbps to 5 82 kbps to 1 52 kbps to 1 5 kpbs to 3 89 kbps to 975 bps to 175 kbps 168 5 kbps 45 9 kbps 44 2 kbps 116 kbps 30 0 kbps R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 164 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group
171. an cycle is complete Specify PDL_NO_FUNC if no callback function is required data5 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Grou P P 4 Library Reference Return value True if all parameters are valid and exclusive otherwise false Functionality ADC References R_ADC_10_Destroy R_ADC_10_Control RLADC_10_Read Remarks e This function configures the selected pin s for ADC operation by setting the direction to input and turning off the input buffer The port control settings for any ADC pins that subsequently become inactive are not modified e This function brings the selected converter unit out of the power down state e Interrupts are enabled automatically if a callback function is specified Please see the notes on callback function usage in 6 e A callback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed e Function R_CGC_Set must be called before any use of this function e The available values for the conversion clock are PCLK 8 4 2 or 1 If the desired frequency is not an exact match the actual frequency will be the ne
172. aninnnasnnnnannenadannnnaneanaaatannnnnna 4 197 1 RADAG 210 Creates arera eee e Ea e a aE EASES Ae DA aR a A aea Taaa 4 197 20 gt RaDAGs V0 DeStOy sb ee fare aeaaea n a aa ea eea a Aaa e Eaa a AE aA EES Game aena diee 4 198 3V OR DAC AOS Witte e arhe a r a a a e a a aaa e aae Tana ann eats 4 199 Usage Exa Mple Sareen aerie Tel ed ee ETA A eee 5 1 5i Intermrupt CONTO rere eee eae eae Pe al aaa 5 2 DiZa gt VIVO UPOM ste 8 ote iee 8 ela E Re tara Hi bet E hae Hs cent tala Renate vaca Tet bee de sad ns 5 4 5 32 BUS CONTO bs zucree woius deccd tote e ea oe ont dae ag eed ie eet Sees s a titer eed enact 5 6 S4 DMA controller tcs2 es chietiken a a ie teh glia A a a E te 5 12 5 5 Data Transfer Controller oieri ee ate ender 5 20 5 6 Compare Match Timer ccceceeeecee cece cece eeceneaeeeeeeeeeceeaaeaeeeeeeeeeesecacaeeeeeeeseseccaeaeeeeeeesesecsaesaeeseeeeees 5 22 Dif sO Dit TIMERS cs steA steadied ied a ae a Roses eae E eA eA ea A stared alah A Aone dette 5 24 5 8 Serial Communication Nier ACE aii sicccec pected las cake a a a aa a ag ectadhd a aaa tet eE E a eee 5 26 5 9 CRG Calculator rtnn n a WA e a a ra e a a ede 5 35 5 10 FC Bustera te a a a a dete tat a a pak ade Pac tenatets 5 36 5 10 1 MaStenimOde a a a e a a aa a a a aae nd 5 36 1 Configuration and transmission ccc eeeeee ee eeenneeeeeeaeeeeeeeaaeeeeeeaaeeeeeeaeeeeeeaeeeeeeenaeeeeeas 5 37 2 RROCOPUOM E E A A N lddecel vid ceeedagen
173. annel 0 with default operation mid voltage R_DAC_10_Create PDL_DAC_10_CHANNEL_0O 1024 2 0 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Sanger RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 R_DAC_10_ Destroy Synopsis Disable a DAC channel Prototype bool R_DAC_10_Destroy uint8_tdata Channel selection Description Disable the channel output data1 4 Library Reference Disable selection To set multiple options at the same time use to separate each value PDL_DAC_10_CHANNEL_0 Disable channel 0 PDL_DAC_10_CHANNEL_1 Disable channel 1 Return value Category DAC Reference R_DAC_10_Create Remarks Program example R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 198 RPDL definitions include r_pdl_dac_10 h True if the parameter is valid otherwise false RPDL device specific definitions include r_pdl_definitions h void func void Shut down both DAC channels R_DAC_10_Destroy PDL_DAC_10_CHANNEL_0O PDL_DAC_10_CHANNI 7tENESAS EL 1 Once both channels are disabled the module is put into the power down state Under development Preliminary Specification Specifications in this preliminary version
174. annel SPIn where n 0 to 1 Return value True if all parameters are valid otherwise false Category SPI Reference R_SPI_Create Remarks The SPI channel is put into the power down state Program example RPDL definitions include r_pdl_spi h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown SPI channel 1 R_SPI_Destroy 1 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Sangre RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group dieing Resrenes 3 R_SPI_Conitrol Synopsis Control an SPI channel Prototype bool R_SPI_Control uint8_t data1 Channel selection uint8_t data2 Control options Description Modify the operation of the selected SPI channel data1 Select channel SPIn where n 0 to 1 data2 Control the channel e Loopback control PDL_SPI_LOOPBACK_DISABLE or PDL_SPI_LOOPBACK_DIRECT or Disable or enable loopback in direct or reversed mode PDL_SPI_LOOPBACK_REVERSED Return value True if all parameters are valid otherwise false Category SPI Reference Remarks None Program example RPDL definitions include r_pdl_spi h RPDL device specific definitions include r_pdl_definitions h void func void En
175. are subject to change RX62N Group RX621 Group 4 Library Reference 3 R_DAC_10_Write Synopsis Write data to a DAC channel Prototype bool R_DAC_10_Control uint8_t data1 Channel selection uint16_tdata2 Output value uint16_t data3 Output value Description Write data to the selected DAC channel s data1 Select the DAC channel output to be modified PDL_DAC_10_CHANNEL_0 Select channel 0 PDL_DAC_10_CHANNEL_1 Select channel 1 data2 The value to be written to the channel 0 output register Ignored if the channel is not selected data3 The value to be written to the channel 0 output register Ignored if the channel is not selected Return value True if all parameters are valid otherwise false Category DAC Reference R_DAC_10_Create Remarks Refer to the data alignment that was selected when R_DAC_10_Create was called Program example RPDL definitions include r_pdl_dac_10 h RPDL device specific definitions include r_pdl_definitions h void func void Write new data to DAC channel 0 R_DAC_10_Write PDL _DAC_10_CHANNEL_0 100 0 R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 199 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5
176. as Electronics Corporation R20UT0084EE0004
177. ata4 Where the compare match A value shall be stored Specify PDL_NO_PTR if it is not required data5 Where the compare match B value shall be stored Specify PDL_NO_PTR if it is not required True if all parameters are valid and exclusive otherwise false Timer TMR R_TMR_CreateChannel R_TMR_ControlChannel e Ifthe status flags are read any flag that has been set to 1 shall be automatically cleared to 0 by this function include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h uint8_t Flags uint8_t Counter uint8_t CompareMatchA uint8_t CompareMatchB void func void Read the status flags and registers for TMRO R_TMR_ReadChannel 0 amp Flags amp Counter amp CompareMatchA amp CompareMatchB R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 128 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 11 R_TMR_ReadUnit Synopsis Prototype Description Return value Category Reference Remarks Read from timer unit registers bool R_TMR_Readunit uint8_t data1 Unit selection uint8_t data2 A pointer to the data storage location uint16_t data3 A pointer to the data storage location uint16_t data4 A pointer to the data storage location uint16_t da
178. ation If the transfer rate is specified in bits per second the high level and low level durations can be adjusted to allow for application dependent rise and fall times If unsure use 0 b31 b16 b15 bO The SCL rise time in nanoseconds The SCL fall time in nanoseconds Valid from 0 to 65535 Valid from 0 to 65535 Return value True if all parameters are valid exclusive and achievable otherwise false Category C Reference R_IIC_Destroy R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae Page 4 163 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group aiban Releet Remarks e Function R_CGC_Set must be called before any use of this function e This function configures each I C pin that is required for operation It also disables the alternative modes on those pins The 7 or 10 bit slave addresses should use the format b15 b8 b7 b1 bO 7 bit address b15 b11 b10 b1 bO 10 bit address The timing limits depend on the frequency of the internal reference clock IRC Transfer _ rate 1 Live t an UCBRA M tige UCBRL It re The maximum transfer rate is given when ICBRH ICBRL 0 the minimum when ICBRH ICBRL 31 The absolute limits with zero rise and fall times are
179. ation selection II Trigger selection Source start address Destination start address Repeat or Block size 4 Library Reference Source address extended repeat area uint32_t data10 Destination address extended repeat area void func uint8_t data11 Set up a DMA channel data1 The channel number n where n 0 to 3 data2 Configure the operation of channel DMAn Callback function Interrupt priority level If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Transfer mode selection PDL_DMAC_NORMAL or Normal or PDL_DMAC_REPEAT or Repeat or PDL_DMAC_BLOCK Block mode PDL_DMAC_SOURCE or PDL_DMAC_DESTINATION If Repeat or Block mode is selected the source or destination side can be selected as the Repeat or Block area Address direction selection PDL_DMAC_SOURCE_ADDRESS_FIXED or PDL_DMAC_SOURCE_ADDRESS_PLUS or PDL_DMAC_SOURCE_ADDRESS_MINUS or PDL_DMAC_SOURCE_ADDRESS_OFFSET Leave the source address unchanged increment it decrement it or modify it by the value specified in parameter data7 Address offset is valid only for n 0 PDL_DMAC_DESTINATION_ADDRESS_FIXED or PDL_DMAC_DESTINATION_ADDRESS_PLUS or PDL_DMAC_DESTINATION_ADDRESS_MINUS or PDL_DMAC_DESTINATION_ADDRESS_OFFSET Leave the destination address unchanged increment it decrement
180. ations in this preliminary version are subject to change RX62N Group RX621 Group 4 ibay Reena 6 R_MTU_ReadChannel Synopsis Read from MTU channel registers Prototype bool R_MTU_ReadChannel uint8_t data1 Channel selection R_MTU_ReadChannel_structure ptr A pointer to the structure R_MTU_ReadChannel_structure members uint8_t data2 A pointer to the data storage location uint16_t data3 A pointer to the data storage location uint16_t data4 A pointer to the data storage location uint16_t data5 A pointer to the data storage location uint16_t data6 A pointer to the data storage location uint16_t data7 A pointer to the data storage location uint16_t data8 A pointer to the data storage location uint16_t data9 A pointer to the data storage location Description 1 2 Read any of the timer s counter compare or status flag registers data1 The channel number n where n 0 to 11 data2 The status flags shall be stored in the format below The input capture compare match flags will be set to1 if the condition has been detected Specify PDL_NO_PTR if the flags are not to be read Forn Oor6 b7 b6 b5 b4 b3 b2 b1 bO Detection Count Overflow Input capture compare match direction v F E o c B A 0 down 1 up Forn 1 2 70r8
181. be the Repeat or Block area Address direction selection PDL_DTC_SOURCE_ADDRESS FIXED or PDL_DTC_SOURCE_ADDRESS PLUS or PDL_DTC_ SOURCE ADDRESS MINUS After a data transfer leave the source address unchanged increment it or decrement it PDL_DTC_DESTINATION_ADDRESS_FIXED or PDL_DTC_DESTINATION_ADDRESS_PLUS or PDL_DTC_DESTINATION_ADDRESS_MINUS After a data transfer leave the destination address unchanged increment it or decrement it Transfer data size PDL_DTC SIZE 8 or PDL_DTC_SIZE_16 or PDL_DTC SIZE 32 Select 1 2 or 4 bytes to be transferred in one operation e Chain transfer control PDL_DTC_CHAIN_DISABLE or PDL_DTC_CHAIN_CONTINUOUS or PDL_DTC_CHAIN_0 Disable Enable continuous or Enable only when the transfer counter is 0 e Interrupt generation PDL_DTC_IRQ_COMPLETE or PDL_DTC_IRQ_ TRANSFER Select interrupt request generation when the transfer sequence completes or for every transfer e Trigger selection Name Trigger cause PDL_DTC_TRIGGER_CHAIN Chain transfer PDL_DTC_TRIGGER_SW or By software PDL_DTC_TRIGGER_CMTO or PDL_DTC_TRIGGER_CMT1 or PDL_DTC_TRIGGER_CMT2 or PDL_DTC_TRIGGER_CMT3 or Compare match on channel CMTn n 0 to 3 PDL_DTC_TRIGGER_USBO_DO0 or PDL_DTC_ TRIGGER USB1 DO or DOFIFO transfer request on USB port n n 0 to 1 PDL_DTC_TRIGGER_USBO_D1 or PDL_D
182. ble interrupts and register the callback function R_BSC_Create PDL_BSC_CS2_B 0 PDL_BSC_ERROR_ILLEGAL_ADDRESS_ENABLE PDL_BSC_ERROR_TIME_OUT_ENABLE BusErrorFunc 5 i R20UT0084EE0004 Rev 0 04 Aug 25 2010 Sage RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 R_BSC_CreateArea Synopsis Configure an external bus area Prototype bool R_BSC_CreateArea uint8_t data1 Area selection uint16_t data2 uint8_t data3 II RRCV cycles uint8_t data4 1 WRCV cycles uint8_t data5 I CSPRWAIT cycles uint8_t data6 II CSPWWAIT cycles uint8_t data7 I CSRWAIT cycles uint8_t data8 I CSWWAIT cycles uint8_t data9 II CSROFF cycles uint8_t data10 CSWOFF cycles uint8_t data11 WDOFF cycles uint8_t data12 uint8_t data13 uint8_t data14 uint8_t data15 II RDON cycles 1 WRON cycles II WDON cycles II CSON cycles Description 1 2 Set up an external bus area R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 53 data1 The address area n where n 0 to 7 data2 Configure the operation of area CSn 4 Library Reference II Configuration selection If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defa
183. ccccecccecccecceeeeeeeceeanaeceeeeeeescaanaeseeeeeeeeseccanaeeeseessssenniaeeees 4 56 A RB SE DE SNOY Saana E A A N AN A E A OA 4 59 5 iN No ROMNAOTARWNANWNHANNA DG RWONANOBRWNHANN EA WD B a Sk ee et ae eet er ee ee et ee ee ey i ae et CO eS x 4 2 19 4 2 20 1 OQORAR UN 7 4 2 21 Oo D Pw g R BSG Controlnr denenen ao tee ee a nes Bee ae 4 60 R BSC GetStatus eiaeia eie a ie hee a e es eee ae 4 61 DMA Controle rises sein tcc eee e ates ea a ee ed ev a nee cede i 4 63 RiiDMAC Cre atte wi c2 tected fates ae e ties ee dg ee edhe alias ee 4 63 RoiDMAC Destroy cc ecsied anes te dak itadel dese dade Ae ee ibe ed al lee 4 66 RoDMAC Controls tec tates aenar eels nase eR ed ae le A 4 67 R DMAC4GetStatu enii eana estaba Weenie Ana a riaa ded eine nee 4 69 External DMA Controller onionenn ea enes esa ated Ae abe E a eee ade ae eels 4 71 Data Transfer Controller 2 cc c csceneades ieena aae iae eia i e e a 4 72 RDTG Sefo aena a a aana aaa ea aa a aaa e a a aasa A a 4 72 R DTC Creates a fabian E a a a aa deadbeat ta a a a aaa aaa i hele aaa 4 73 R DTO DASO te a dikes th i cke aar aude A a E eaaa a eM aabutaeth A Aa 4 77 R DTC CORFO a aiaa a a a a a aaae aa err aaa a a a ere 4 78 RDTC GetSt t S neis a a e a aa a aa a A aa aa N a 4 80 Multi Function Timer P lse Unit esson araa areena a aaa aaa thay deed aia aaa 4 82 RiMTU Sete eee ee ceri aa A reer rer A a Oa aaa a e aa iea a
184. ce address data10 2 The destination address extended repeat value The value can be any power of 2 from 2 to 2 Set this value to 0 if the extended repeat function is not required for the destination address func The function to be called when a DMA transfer completes Specify PDL_NO_FUNC if not required data11 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func Return value True if all parameters are valid and exclusive otherwise false Category DMA controller Reference R_DMAC_Destroy RLDMAC_Control RLDMAC_GetStatus Remarks e If another peripheral will be used to trigger a DMA transfer call this function before calling the Create function for the peripheral Some peripheral channels are not available on some device packages Please check the hardware manual Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed Program example RPDL definitions include r_pdl_dmac h RPDL device specific definitions include r_pdl_definitions h void func void Configure DMA channel 2 R_DMAC_Create 2 PDL_DMAC_NORMAL PDL_DMAC_SOURCE_ADDRESS_PLUS PDL_DMAC_DESTINATION_ADDRESS_PLUS PDL_DMAC_SIZE_8 PDL_DMAC
185. certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electr
186. chip select pins and handling any bus errors 8 DMA Controller These driver functions are used for configuring and controlling the transfer of data within the address space 9 Data Transfer Controller These driver functions are used for configuring and controlling the transfer of data triggered by peripheral interrupts 10 Timer Pulse Unit These driver functions are used for configuring and controlling the timers 11 Programmable Pulse Generator These driver functions are used for configuring and controlling the pulse generator outputs 12 8 bit Timer These driver functions are used for configuring and controlling the timers 13 Compare Match Timer These driver functions are used for configuring and controlling the timers 14 Watchdog Timer These driver functions are used for configuring and controlling the timer 15 Serial Communication Interface These driver functions are used to configure the serial channels and manage the transmission and or R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 2 1 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver reception of data across them 16 CRC calculator These driver functions are used for controlling the calculator 17 PC Bus Interface These driver functions are used for controlling the I C bus channels 18 Analog to Digital Converter These driver f
187. cifications in this preliminary version are subject to change RX62N Group RX621 Group 5 WeageExamplez Figure 5 9 Example of Compare Match Timer use R20UT0084EE0004 Rev 0 04 Aug 25 2010 Sage RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 WeageExamples 5 7 8 bit Timer 1 Periodic operation Timer channel 0 is configured to provide pulses on pin TMOO with a pulse width of 500us and an on time of 200us Peripheral driver function prototypes include r_pdl_tmr h include r_pdl_cgc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void main void Initialise the system clocks R_CGC_Set 12 0E6 96E6 48E6 24E6 PDL_CGC_BCLK_HIGH Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Configure TMRO for 500us pulse width 200us on time R_TMR_CreatePeriodic PDL_TMR_TMRO PDL_TMR_PERIOD PDL_TMR_OUTPUT_ON 500E 6 200E 6 PDL_NO_FUNC PDL_NO_FUNC 0 di The same operation using frequency and duty cycle R_TMR_CreatePeriodic PDL_TMR_TMRO _TMR_FREQUENCY PDL_TMR_OUTPUT_ON L_NO_FUNC L_NO_FUNC Figure 5 10 Example of Pulse Output code R20UT0084EE0004 Rev 0 04 Aug 25 2010 a
188. d R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 5 49 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group uint32_t status_flags 0 uintl6_t tx count 0 uintl6_t rx_count 0 Read the channel status R_IIC_GetStatus 0 amp status_flags amp tx_count amp xrx_count Slave address 0 detected with a Read if status_flags amp 0x00000047 0x0041 Assign 5 bytes to be read by a master R_IIC_SlaveSend 0 mcu_data_array 5 Slave address 1 detected with a Read else if status_flags amp 0x00000047 0x0042 Assign 5 bytes to be read by a master R_IIC_SlaveSend 0 slave_data_storage 5 NACK and Stop detected else if status_flags amp 0x00001800 0x1800 all_data_sent true Stop detected else if status_flags amp 0x00001800 0x0800 all_data_read true do R_IIC_GetStatus 0 amp status_flags PDL_NO_PTR PDL_NO_PTR while status_flags amp 0x00008000 0x0u else Process any other conditions here 5 Usage Examples Figure 5 28 Configure the I C channel and write 3 data bytes to the first locations R20UT0084EE0004 Rev 0 04 Aug 25 2010 ztENESAS Page 5 50 Under development Preliminary Specification Specifications in this preliminary version are
189. d TMR1 Unit 1 comprises channels TMR2 and TMR3 Return value True if the unit selection is valid otherwise false Category Timer TMR Reference R_TMR_CreateChannel R_TMR_CreateUnit R_TMR_CreatePeriodic Remarks e The timer unit is put into the stop state to reduce power consumption Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown channels 0 and 1 R_TMR_Destroy 0 de R20UT0084EE0004 Rev 0 04 Aug 25 2010 Sangin RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 7 R_TMR_ControlChannel Synopsis Prototype Description Write to timer channel registers bool R_TMR_ControlChannel 4 Library Reference uint8_t data1 Channel selection uint32_t data2 Configuration selection uint8_t data3 Register value uint8_t data4 Register value uint8_t data5 Register value data1 The channel number n where n 0 1 2 or 3 data2 The channel settings to be modified Modify a timer channel s operation counter and compare registers If multiple selections are required use to separate each selection Counter stop re start PDL_TMR_STOP or PDL_TMR_START Disable or re enable the count
190. d by the MDE pin low little endian high big endian e Port Function Control registers PFOCSE and PF5BUS are modified by this function e The cycle count parameters are not checked for validity Use the hardware manual to check these values R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 54 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Apiary E enes Program example RPDL definitions include r_pdl_bsc h RPDL device specific definitions include r_pdl_definitions h void func void Configure CS2 8 bit width no wait cycles R_BSC_CreateArea 2 PDL_BSC_WIDTH_8 0 0 0 0 0 0 0 0 1 0 0 1 0 R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae AS Page 4 55 KENES Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 3 R_BSC_SDRAM_CreateArea Synopsis Configure the SDRAM area bool R_BSC_SDRAM_CreaieArea uint16_t data1 uint16_t data2 uint8_t data3 uint8_t data4 Prototype II RFC cycles II REFW cycles I ARFI cycles uint8_t data5 ARFC count uint8_t data6 PRC cycles uint8_t data7 CL cycles uint8_t data8 WR cycles uint8_t data9 RP cycles uint8_t data10 uint8_t data11 uint16_t data12 1 RCD cycles II RAS cycles
191. d exclusive otherwise false Category Multi function Timer Pulse Unit Reference Remarks e None Program example RPDL definitions include r_pdl_mtu h RPDL device specific definitions include r_pdl_definitions h uintl6_t Sub_count uintl6_t Skip_count void func void Read the counter registers for unit 0 R_MTU_ReaduUnit 0 amp Sub_count amp Skip_count i R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae Page 4 103 E ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group EE E enes 4 2 13 Port Output Enable R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae Page 4 104 E ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 fabranyRererence 4 2 14 Programmable Pulse Generator 1 R_PPG_Create Synopsis Configure a PPG group Prototype bool R_PPG_Create uint32_t data1 Output pin selection uint16_t data2 Configuration selection uint8_t data3 Output values Description 1 2 Set up a 4 bit PPG group data1 Select the outputs to be enabled If multiple selections are required use to separate each selection Select only outputs within one group e Output pin selection Outputs are disabled by default PDL_PPG_ POO
192. de r_pdl_cmt h include r_pdl_dmac h RPDL device specific definitions include r_pdl_definitions h static void write_eeprom_data void static void read_eeprom_data void void iic_tx_dmac_end_handler void void iic_rx_dmac_end_handler void define EEPROM MEMORY _ADDRESS_UPPER 0x00 define EEPROM MEMORY ADDRESS LOWER 0x00 define EEPROM_ADDRESS 0x00A0 EEPROM MEMORY _ADDRESS_UPPER volatile uint8_t bus_busy volatile uint8_t data_storage 20 void main void const uint8_t eeprom_data_array_1 EEPROM _MEMORY_ADDRESS_LOWER 0x01 0x02 0x03 0x04 0x05 const uint8_t eeprom_data_array_2 EEPROM_MEMORY_ADDRESS_LOWER 5 0x06 0x07 0x08 0x09 0x0A 0x0B Ox0C 0x0D 0x0E 0x0F uint8_t i Configure the clocks R_CGC_Set 12 0E6 96E6 48E6 PDL_NO_DATA PDL_CGC_BCLK_DISABLE Set up a DMAC channel for IIC transmission R_DMAC_Create 3 PDL_DMAC_SINGLE PDL_DMAC_SOURCE_ADDRESS_PLUS PDL_DMAC_REQUEST_IIC1_TX eeprom_data_array_l uint8_t amp RIIC1 ICDRT 6 PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA lic_tx_dmac_end_handler 7 Set up a DMAC channel for IIC reception R_DMAC_Create 2 PDL_DMAC_SINGLE PDL_DMAC_DESTINATION_ADDRESS_PLUS PDL_DMAC_REQUEST_IIC1_RX uint8_t amp RIIC1 ICDRR
193. de r_pdl_definitions h void func void Invert port pin P05 R_IO_PORT_Modify PDL_IO_PORT_0_5 PDL_IO_PORT_XOR 1 i And the value port 6 with 0x55 R_IO_PORT_Modify PDL_IO_PORT_6 PDL _IO_PORT_AND 0x55 di R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 35 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group A ibrar Reteenes 8 R_IO_PORT Wait Synopsis Wait for a match on an I O port Prototype bool R_IO_PORT_Wait uint16_tdata1 Output port or port pin selection uint8_t data2 II Comparison value Description Loop until an I O port or I O port pin matches the comparison value data1 Use either one of the following definition values from 4 2 3 One port definition or e One port pin definition Sea to be compared with Between 0x00 and OxFF for a port O or 1 for a pin Return value True if the parameters are valid otherwise false Functionality I O port References R_IO_PORT_Set R_IO_PORT_Read Remarks e Ifan invalid port or pin is specified the operation of the function cannot be guaranteed e This function waits for the I O port or port pin value to match the comparison data If the I O port s control registers are directly modified by the user this function may lock up e The input buffer for the s
194. de r_pdl_definitions h void func void Change timer TMR1 to 600ns period 100ns pulse width R_TMR_ControlPeriodic PDL_TMR_TMR1 PDL_TMR_PERIOD 600E 9 100E 9 R20UT0084EE0004 Rev 0 04 Aug 25 2010 a 2 Page 4 127 a ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 10 R_TMR_ReadChannel Synopsis Prototype Description Return value Category Reference Remarks Program example Read from timer channel registers bool R_TMR_ReadChannel uint8_t data1 Channel selection uint8_t data2 A pointer to the data storage location uint8_t data3 A pointer to the data storage location uint8_t data4 A pointer to the data storage location uint8_t data5 A pointer to the data storage location Read any of the timer s counter compare or status flag registers data1 The channel number n where n 0 1 2 or 3 data2 The status flags shall be stored in the format below The flag will be set to 1 if the condition has been detected Specify PDL_NO_PTR if the flags are not to be read b7 b3 b2 b1 bO Overflow Compare match B Compare match A data3 A pointer to where the counter value shall be stored Specify PDL_NO_PTR if it is not required d
195. directory v Cancel Sub Directory RPDL Click on OK to close the window Click on the Add button In the Add include file directory window enter the details as shown Add include file directory Relative to Project directory v Sub Directory aaa Click on OK to close the window Click on OK to return to the main HEW window R20UT0084EE0004 Rev 0 04 Aug 25 2010 7tENESAS Page 1 4 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 1 Introduction 1 1 4 Include the new source files Use the key sequence Alt P A to open the Add files to project lt your project gt window Double click on the RPDL folder From the Files of type drop down list select C source file C Select all of the files as shown below Add files to project RX62N_library Look in RPDL e ek EJ B Interrupt _ADC_10 c Interrupt_not_RPDL c Interrupt_BSC c Interrupt_SCTI c Interrupt_CMT c Interrupt_TMR c Interrupt_DMAC c Interrupt_WDT c Interrupt_IIC c Interrupt_INTC c File name Interrupt WDT c Interrupt_ADC_10 c Inter Add Files of type C source file C 7 Cancel V Relative Path I Hide Project Files Click on Add Click on OK to return to the main HEW window R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae ENESAS P
196. dl_dtc h RPDL device specific definitions include r_pdl_definitions h Reserve an area for the DTC vector table pragma address dtc_vector_table uint32_t dtc_vector_table 256 void func void 0x00015000 Configure the controller R_DTC_Set PDL_DTC_ADDRESS_SHORT dtc_vector_table 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 R_DTC Create Synopsis Prototype Description 1 3 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 73 4 Library Reference Configure the Data Transfer Controller for a transfer bool R_DTC_Create uint32_t data1 uint32_t data2 void data3 void data4 uint16_t data5 uint8_t data6 II Block size II Configuration selection Transfer data start address Source start address Destination start address Transfer count Configure DTC activation for one trigger source data1 Configuration selections If multiple selections are required use to separate each selection The default settings are shown in bold Transfer mode selection PDL_DTC_NORMAL or PDL_DTC_REPEAT or PDL_DTC_ BLOCK Normal or Repeat or Block mode PDL_DTC_SOURCE or PDL_DTC_DESTINATION If Repeat or Block mode is selected select the source or destination side to
197. dog operation Modify the operation of the Watchdog timer PDL_WDT_STOP Disable the counter clock source Counter update PDL_WDT_RESET_COUNTER_ Reset the counter Return value Category Reference Remarks Program example vo Watchdog Timer R_WDT_Create True if all parameters are valid and exclusive otherwise false R_WDT_Create must be first be used to configure the timer RPDL definitions include r_pdl_wdt h RPDL device specific definitions include r_pdl_definitions h id func void Prevent the watchdog timer from overflowing R_WDT_Control PDL_WDT_RESET_COUNTER R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 141 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group A ibrar Renee 3 R_WDT Read Synopsis Read the Watchdog timer status and registers Prototype bool R_WDT_Read uint8_t data A pointer to the data storage location Description Read and store the status flags data The timer status shall be stored in the following format b7 b1 bO 0 0 Not overflowed 1 Overflow has occurred Return value True if all parameters are valid otherwise false Category Watchdog Timer Reference
198. e PDL_MTU_ADC_TRIG_A_DOWN_DISABLE or PDL_MTU_ADC TRIG_A DOWN ENABLE Disable or enable ADC trigger TRGnAN requests during down count operation PDL_MTU_ADC_TRIG_B DOWN DISABLE or PDL_MTU_ADC TRIG_B_DOWN ENABLE Disable or enable ADC trigger TRGnBN requests during down count operation PDL_MTU_ADC_TRIG_A_UP_DISABLE or PDL_MTU_ADC_TRIG_A_UP_ENABLE Disable or enable ADC trigger TRGnAN requests during up count operation This option can be selected in other modes PDL_MTU_ADC_TRIG_B_UP_DISABLE or PDL_MTU_ADC_TRIG_B_UP_ENABLE Disable or enable ADC trigger TRGnBN requests during up count operation 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Description 4 8 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 86 data5 Configure the buffer operation If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults 4 Library Reference Control the cycle set buffer transfer timing Valid for n 4 or 10 PDL_MTU_CSB_DISABLE or PDL_MTU_CSB_CREST or PDL_MTU_CSB_TROUGH or PDL_MTU_CSB_BOTH Select no transfer transfer on crest detection transfer on trough detection or transfer on crest and trough detection Buffer operation PDL_MTU_BUFFER_AC_DISABLE or PD
199. e RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 13 Data Transfer Controller Driver The driver functions support the control of the Data Transfer Controller providing the following operations 1 Setting the central options 2 Configuration for use including support for chain transfers 3 Disabling the controller 4 Starting or stopping the controller 5 Reading the status flags and data transfer registers R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 2 13 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 14 Multi Function Timer Pulse Unit Driver The driver functions support the use of the twelve 16 bit timers providing the following operations 1 Configuration for use including e Access to all control bits e Automatic interrupt control e Automatic I O pin configuration 2 Disabling channels that are no longer required and enabling low power mode 3 Control of a timer 4 Reading the status and registers of a timer Note The Clock Generation Circuit must be configured before configuring any timer channel R20UT0084EE0004 Rev 0 04 Aug 25 2010 Pame RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group
200. e applied to the register contents PDL_INTC_AND or PDL_INTC_OR or Select between AND amp OR or Exclusive OR PDL_INTC_XOR data3 The value to be used by the logical operation True if the parameter is within range otherwise false Interrupt control R_INTC_Read R_INTC_Write e This function uses an interrupt routine to modify the IPL bits If the user has disabled interrupts cleared the I bit in the PSW register in their own code this function will lock up e For register select one of the registers listed in tables in section 4 2 2 RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void Set bits 6 and 4 in IERO9 to 1 R_INTC_Modify PDL_INTC_REG_IERO9 PDL_INTC_OR 0x50 R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 25 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Abban Retence 4 2 3 VO Port I O Port functions may operate on a complete port or on individual port pins The available definitions are listed below I O port definitions PDL_IO PORT_0 Port PO PDL_IO PORT_1 Port P1 PDL_IO PORT 2 Port P2 PDL_IO PORT 3 PortP3 PDL_IO PORT 4 Port P4 PDL_IO PORT 5 PortP5 PDL_IO PORT 6 Port P6 PD
201. e equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under
202. e required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Input capture output compare control for register TGRA PDL_MTU_A_OC DISABLED or PDL_MTU_A_OC_LOW or PDL_MTU_A_OC_LOW_CM HIGH or PDL_MTU_A_OC_LOW_CM_INV or PDL_MTU_A_OC_HIGH_CM_LOW or PDL_MTU_A_OC_HIGH or PDL_MTU_A_OC_HIGH_CM_INV or MTIOCnA output disabled MTIOCnA output low MTIOCnA initial output low goes high at compare match MTIOCnA initial output low toggles at compare match MTIOCnA initial output high goes low at compare match MTIOCnA output high MTIOCnA initial output high toggles at compare match PDL_MTU_A_IC_RISING_EDGE or PDL_MTU_A_IC_FALLING EDGE or PDL_MTU_A_IC_BOTH EDGES or Input capture at MTIOCnA rising edge Input capture at MTIOCnA falling edge Input capture at MTIOCnA both edges PDL_MTU_A_IC_COUNT or Input capture at channel n 1 up count or down count Valid only for n 0 or 6 PDL_MTU_A_IC_CM_IC Input capture at channel n 1 TGRA compare match or input capture Valid only for n 1 4 7 and 10 e Input capture output compare control for register TGRB PDL_MTU_B_OC_ DISABLED or PDL_MTU_B_OC_LOWor PDL_MTU_B_OC_LOW_CM HIGH or PDL_MTU_B_OC_LOW_CM_INV or PDL_MTU_B_OC_HIGH_CM_LOW or PDL_MTU_B_OC_HIGH or PDL_MTU_B_OC_HIGH_CM_INV or MTIOCnB output disabled MTIOCnB output low
203. e time of 5 ms The following examples illustrate the use of Master mode R20UT0084EE0004 Rev 0 04 Aug 25 2010 Seer RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group amp Weagekxemples 1 Configuration and transmission Peripheral driver function prototypes include r_pdl_iic h include r_pdl_cgc h include r_pdl_intc h include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h define EEPROM_ADDRESS 0xA0 void main void const uint8_t eeprom_data_array_1 5 0x00 0x01 0x02 0x03 0x04 uint32_t status_flags 0 uint1l6_t TxChars uint1l6_t RxChars Initialise the system clocks R_CGC_Set 12 0E6 96E6 48E6 PDL_NO_DATA PDL_CGC_BCLK_HIGH Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Select I C mode at 100kHz 300ns rise time 200ns fall time R_IIC_Create 0 PDL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA 100E3 300 lt lt 16 200 Send the lower address and 3 bytes to the EEPROM using polling if R_IIC_MasterSend 0 PDL_NO_DATA EEPROM_ADDRESS eprom_data_array_l r DL_NO_FUNC e 4 P 0 false
204. e tt aR es tlh ee Soaks 4 122 R_TMR_ControlChannnel 2 00 02 ecccccceccccceceeeeeeeee ance a a cece a aa Ea aAa pe Aaaa Aaa a EAEE AAEE 4 123 ReTEMR gt ControlU nit a a ae aaa Aa E tees sa a a aE 4 124 RETMR ControlPeriodiC aeie arannana kar a aar aaen Kae naaa ae a a ae aa aaan aea iaaa anaia 4 126 R_TMR_ReadChannnell a e ea aa e a a a aaee a a aaaeeeceeeeecageaeaeaeeeeeeesessecanaeeeeeeeeseeees 4 128 Re EMR Read Unit vie cig sik a a aa oe A aa Aa a E 4 129 Compare Match Timet ccccceceeeeeeeeceececeeeeeeeeeaeaececeeecesecaaeaeceeeeesesecaeeaeeeeeeeseeseennaeess 4 131 R amp ECMT Create scectts E asad oe RT E EA EE cages eeunetee anes ies 4 131 R_CMT_CreateOneShot 20 0 22 ceceecccecce cece ee eee cee eeee cece eee eeaeaneeeeeeeesageaeaeeeeeeesesegeeneiaeeeeeeeeeeeees 4 133 RE CMT I DOSttoy iA cs aceite Met cena Seth tees etter A E A E E 4 135 R CMT CONTON ieena aie oat iia Me ae A ee ld 4 136 Ro CMT RedArt ne ian end ae a ea ae 4 137 Real time COCK wiici niece a leeches eid aie a a edd le eda edd 4 138 Watchdog TIMER iscsiincceect cate acl a landever anda anes ai ee aE NE E Ea de digesta anaes 4 139 Ro WDT Create idinon aniani niceties nace e eee ered ee ee eee 4 139 R WDT Conttol wicscceanige obeeteeiaeiileran aed adie au ree a ea 4 141 R WDT Read sid scien tied heel ae Aire cate ea eee ee ee eee ed 4 142 Independent Watchdog Timer eecceccceeceeeeeeeeeeeeeeeeeeeeeeeeeeeeseeeaeeeseeeaeeeseeeaaeeeseeaeee
205. e value can be any power of 2 from 2 to 2 Specify PDL_NO_DATA if not required Return value True if all parameters are valid and exclusive otherwise false Category DMA controller Reference R_DMAC_Create Remarks The Software trigger control is valid only if the Software trigger option has been selected e This function must be called in order to start the DMAC The Suspend Enable and Start control is executed at the end of the function If a channel has completed a transfer parameters may be changed and the channel re enabled in one function call Program example RPDL definitions include r_pdl_dmac h RPDL device specific definitions include r_pdl_definitions h include lt string h gt const char source_string_1 Renesas RX62N volatile char destination_string_l J 2 gt void func void Re enable transfers on channel 2 R_DMAC_Control 2 PDL_DMAC_ENABLE PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA Reload and trigger channel 1 R_DMAC_Control 1 PDL_DMAC_ENABLE PDL_DMAC_START PDL_DMAC_UPDATE_SOURCE PDL_DMAC_UPDATE_ DESTINATION PDL_DMAC_UPDATE_COUNT PDL_DMAC_UPDATE_ SIZE source_string_l destination_string_l 1 uint16_t strlen source_str
206. ecifications in this preliminary version are subject to change RX62N Group RX621 Group Apiary E enes Program example RPDL definitions include r_pdl_spi h RPDL device specific definitions include r_pdl_definitions h void func void Configure SPI channel 0 commands 0 and 1 R_SPI_Command 0 0 PDL_SPI_CLOCK_MODE_0 PDL_SPI_ASSERT_SSLO PDL_SPI_LENGTH_8 PDL_SPI_MSB_ FIRST PDL_NO_DATA PDL_NO_DATA R_SPI_Command 0 1 PDL_SPI_CLOCK_MODE_1 PDL_SPI_ASSERT_SSL1 PDL_SPI_LENGTH_8 PDL_SPI_LSB_FIRST PDL_NO_DATA PDL_NO_DATA R20UT0084EE0004 Rev 0 04 Aug 25 2010 a 2 Page 4 185 a ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group diban Res enes 5 R_SPI_ Transfer Synopsis Transfer data over an SPI channel Prototype bool R_SPI_Transfer uint8_t data1 Channel selection void data2 Command 0 transmit data start address void data3 Command 0 receive data start address void data4 Command 1 transmit data start address void data5 Command 1 receive data start address void data6 Command 2 transmit data start address void data7 Command 2 receive data start address void data8 Command 3 transmit data start address void data9 Command 3
207. ection 4 Section 5 provides usage examples Section 6 provides details which are specific to the RX CPU R20UT0084EE0004 Rev 0 04 Aug 25 2010 Sau RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 1 3 Acronyms and abbreviations ADC API BCD Bit BSC CAN CMT CGC CPU CRC DAC DC DMA DMAC DSP DTC EEPROM FIFO GSM HEW C INTC 1 0 kB LPC R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 1 10 Analog to Digital Converter Application Programming Interface Binary Coded Decimal Binary digit Bus State Controller Controller Area Network Compare Match Timer Clock Generation Circuit Central Processing Unit Cyclic Redundancy Check Digital to Analog Converter Direct Current Direct Memory Access DMA Controller Digital Signal Processing Data Transfer Controller Electrically Eraseable and Programmable ROM First In First Out Global System for Mobile communications High performance Embedded Workbench Inter Integrated Circuit Interrupt Controller Input Output Kilo Byte 1024 bytes Low Power Consumption Least Significant Bit Microcontroller Unit Multi function Timer pulse Unit Non Maskable Interrupt Most Significant Bit Peripheral Driver Generator Port Function Control Programmable Pulse Generator Pulse Width Modulation Random Access Memory Read Only Memory Renesas Peripheral Driver Library Rene
208. ection register for port PC R_IO_PORT_ReadControl PDL_ITO_PORT_C PDL_IO_PORT_DIRECTION amp direction Read the output type for pin P03 R_IO_PORT_ReadControl PDL_IO_PORT_0_3 PDL_IO_PORT_TYPE amp output R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 29 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group dieing Resrenes 3 R_IO_PORT_ModifyControl Synopsis Modify an I O port s control registers Prototype bool R_IO_PORT_ModifyConirol uint16_t data1 Port or port pin selection uint8_t data2 Control register and logical operation selection uint8_t data3 II Modification value Description Modifying the operation of an I O port or I O port pin data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 Select the register to be modified and the logical operation using to separate the selections e The control register to be modified PDL_IO_PORT_DIRECTION or Data direction register PDL_IO_PORT_INPUT_BUFFER or Input buffer control register PDL IO PORT PULL UP or ae MOS control register Applicable for ports 9 to E Open drain control register Applicable for ports 0 to 3 PDL_IO_PORT_TYPE ee The logical operation
209. ed PDL_INTC_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_INTC_DMAC_TRIGGER_ENABLE or DMAC or DTC when a valid edge PDL_INTC_DTC_TRIGGER_ENABLE transition is detected on an IRQn pin Options which only apply to the NMI e Input sense selection PDL_INTC_FALLING or PDL_INTC_RISING Falling or rising edge detection Additional detection control PDL_INTC_LVD_DISABLE or Disable or enable the NMI when a low voltage detection PDL_INTC_LVD_ENABLE interrupt occurs PDL_INTC_OSD_DISABLE or Disable or enable the NMI when the oscillation stop PDL_INTC_OSD_ENABLE detection interrupt occurs func The function to be called when a valid condition is detected Specify PDL_NO_FUNC if no IRQn interrupt is required A function must be specified for the NMI pin data3 The IRQn interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func This value does not apply to the NMI pin and is ignored True if all parameters are valid and exclusive otherwise false R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 12 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group EE E Category Interrupt control Reference R_INTC_ControlExtInterrupt R_INTC_GetExtlnterruptStatu
210. ed data5 Where the current transfer count shall be stored Specify PDL_NO_PTR if it is not required data6 Where the current repeat or block size count shall be stored Specify PDL_NO_PTR if it is not required True if all parameters are valid and exclusive otherwise false Category DMA controller Reference R_DMAC _ Create Remarks R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 69 Ifthe Interrupt request flag is set to 1 the flag will be cleared to O by this function 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Grou P P 4 Library Reference Program example RPDL definitions include r_pdl_dmac h RPDL device specific definitions include r_pdl_definitions h void func void uintl6_t StatusValue uint32_t SourceAddr Read the status and current source address for channel 2 R_DMAC_GetStatus 2 amp StatusValue amp SourceAddr PDL_NO_PTR PDL_NO_PTR R20UTO084EE0004 Rev 0 04 Aug 25 2010 z AS Page 4 70 KENES Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group EE E enes 4 2 10 External DMA Controller R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 71 Under development Preliminary Specification Specifications in this pr
211. ed in the format below b15 b14 b11 b10 b9 b8 Event detection flags 0 not detected 1 detected An interrupt has caused an exit from deep software 0 LVD2 LvD1 Power on standby mode followed by an internal reset reset b7 b6 b5 b4 b3 b2 b1 bO Deep Software Standby cancel request detection 0 No activity 1 The exit ffom deep software standby was caused by one of the following signals USB NMI suspend RTC LVD IRQ3 A IRQ2 A IRQ1 A IRQ0 A resume True Low Power Consumption control registers R_LPC_Create R_LPC_Control Ifa flag is set to 1 it shall be automatically cleared to 0 by this function RPDL definitions include r_pdl_lpc h RPDL device specific definitions include r_pdl_definitions h void func void uintl6_t status_flags Find out what caused the exit from deep software standby R_LPC_GetStatus amp status_flags i R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 48 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group EE E enes 4 2 7 Voltage Detection Circuit R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 49 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 2 8 Bus Controller 1 R_BSC_Create 3 Proto
212. efinitions include r_pdl_definitions h void func void Stop the sub clock oscilla R_CGC_Control PDL_CGC_SUB_CLOCK_DISABLE tor 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 3 R_CGC_GetStatus Synopsis Configure the clock generation circuit Prototype bool R_CGC_GetStatus uint8_t data 4 Library Reference Pointer to the variable where the status value shall be stored Description Read the clock status register data The status flags shall be stored in the format below b7 b1 bO 7 0 The main clock oscillator is operating normally 1 The main clock oscillator has stopped Return value True Functionality Clock generation circuit References None Remarks e None Program example RPDL definitions include r_pdl_cgc h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t Status_flags R_CGC_GetStatusSet amp Status_flags R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 9 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 2 2 Interrupt Control Unit 4 Library Reference The INTC
213. election e Period or frequency calculation PDL_TMR_PERIOD or The parameters data3 and data4 will contain either period PDL_TMR_FREQUENCY and pulse width or frequency and duty cycle e Output pin control PDL_TMR_OUTPUT_ENABLE or Enable or disable the periodic output on pin TMOn PDL_TMR_OUTPUT_DISABLE For 16 bit operation the pin shall be TMO2 when n 1 e ADC trigger control Disable or enable periodic ADC conversion start PDL_TMR_ADC_TRIGGER_OFF or requests PDL_TMR_ADC_TRIGGER_ON Applicable only for channels TMRO or TMR2 or units 0 or 1 e Counter stop start PDL_TMR_STOP or PDL_TMR_START Disable or re enable the counter clock source nee period or frequency This will be ignored if a timing change is not requested data4 The new pulse width or duty cycle This will be ignored if a timing change is not requested Return value True if all parameters are valid and exclusive otherwise false Category Timer TMR Reference R_TMR_CreatePeriodic Remarks e See the remarks for R_TMR_CreatePeriodic R20UT0084EE0004 Rev 0 04 Aug 25 2010 See RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Grou P P 4 Library Reference Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions inclu
214. eliminary version are subject to change RX62N Group RX621 Group 4 2 11 Data Transfer Controller 1 R_DTC Set Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 72 Set the Data Transfer Controller options bool R_DTC_Set 4 Library Reference uint8_t data1 II Configuration options uint32_t data2 Vector table base address Set the global options for the Data Transfer Controller data1 Configuration selections If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Read skip control PDL_DTC_READ_SKIP_DISABLE or PDL_DTC_READ_SKIP_ENABLE Disable or enable skipping of transfer data read when the vector numbers match Address size control PDL_DTC_ADDRESS FULL or PDL_DTC_ADDRESS SHORT Select 32 bit full or 24 bit short address mode data2 The first address of the area of on chip RAM where the DTC vector table shall be stored The address must be on a 4 kB boundary i e have the format xxxxx000h True if all parameters are valid and exclusive otherwise false Data Transfer Controller R_DTC_Create Before calling R_DTC_Create call this function once RPDL definitions include r_p
215. equired true Stop the SCI to allow the break signal to be output R_SCI_Control 1 PDL_SCI_STOP_TX PDL_SCI_OUTPUT_SPAC R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae ENESAS Page 5 16 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group amp Weagaexemplee Stop the SCI R_SCI_Controli 1 PDL_SCI_STOP_TX PDL_SCI_OUTPUT_MARK sci_dma_transfer_complete true Figure 5 6 An example of using the DMAC for serial port transmission R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 5 17 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Weagekxamplez 3 SCI reception trigger DMAC channel 2 will transfer 5 received characters into the assigned storage area and then call the callback function PDL functions and definitions include r_pdl_dmac h include r_pdl_cgc h include r_pdl_intc h include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h Callback function prototype void DMAC2 transfer_end_handler void Data destination area volatile uint8_t destination_string_1l void main void Initialise the system clocks t E6 E6 d L_NO_DATA L_CGC_BCLK_DISABLI Set the CPU s Interrup
216. er TGRU PDL_MTU_U_CMor Compare match PDL_MTU_U_IC_RISING_EDGE or PDL_MTU_U_IC_FALLING EDGE or PDL_MTU_U_IC_BOTH EDGES or Input capture at MTICnU rising edge Input capture at MTICnU falling edge Input capture at MTICnU both edges PDL_MTU_U_IC_PWM_LOW_TROUGH or PDL_MTU_U_IC_PWM_LOW_CREST or PDL_MTU_U_IC_PWM LOW BOTH or Input capture at trough crest or both for low pulse width measurement PDL_MTU_U_IC_PWM_HIGH_TROUGH or PDL_MTU_U_IC_PWM_HIGH_CREST or PDL_MTU_U_IC_PWM_HIGH_BOTH Input capture at trough crest or both for high pulse width measurement Input capture compare match control for regis ter TGRV PDL_MTU_V_CMor Compare match PDL_MTU_V_IC_RISING_EDGE or PDL_MTU_V_IC_FALLING EDGE or PDL_MTU_V_IC_BOTH EDGES or Input capture at MTICnV rising edge Input capture at MTICnV falling edge Input capture at MTICnV both edges PDL_MTU_V_IC_PWM_LOW_TROUGH or PDL_MTU_V_IC_PWM_LOW_CREST or PDL_MTU_V_IC_PWM_LOW_BOTH or Input capture at trough crest or both for low pulse width measurement PDL_MTU_V_IC_PWM_HIGH_ TROUGH or PDL_MTU_V_IC_PWM_HIGH_CREST or PDL_MTU_V_IC_PWM_HIGH BOTH Input capture at trough crest or both for high pulse width measurement PDL_MTU_W_CMor Input capture compare match control for register TGRW Compare match PDL_MTU_W_IC_RISING_EDGE or PDL_MTU_W_IC_FALLING EDGE or PDL_MTU_W
217. er clock source The counter or compare registers to be modified PDL_TMR_COUNTER Update the timer counter register TCNT PDL_TMR_TIME_CONSTANT_A Update the timer compare match A register TCORA PDL_TMR_TIME_CONSTANT_B Update the timer compare match B register TCORB data3 The counter value This will be ignored if the register is not selected data4 The compare match A value This will be ignored if the register is not selected data5 The compare match B value This will be ignored if the register is not selected Return value Category Reference Remarks Program example Timer TMR None RPDL definitions include r_pdl_tmr h include r_pdl_definitions h True if all parameters are valid and exclusive otherwise false R_TMR_CreateChannel R_TMR_ReadChannel RPDL device specific definitions void func void Load the counter on channel TMRO R_TMR_ControlChanneli 0 PDL_TMR_COUNTER OxFF PDL_NO_DATA PDL_NO_DATA R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 123 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group dieing Resrenes 8 R_TMR_Controlunit Synopsis Write to timer unit registers Prototype bool R_TMR_ControlUnit uint8_t data1
218. er value and status flag data1 The channel number n where n 0 1 2 or 3 data2 The compare match status flag shall be stored in the following format Specify PDL_NO_PTR if the flag is not to be read b7 b1 bO 0 0 Idle 1 Compare match condition detected data3 A pointer to where the counter value shall be stored Specify PDL_NO_PTR if it is not required True if all parameters are valid otherwise false Compare Match Timer R_CMT_Create e Ifthe flag is read and is set to 1 it shall be automatically cleared to O by this function RPDL definitions include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h uint8_t Flags uintl6_t Counter void func void Read the channel 2 values R_CMT_Read 2 amp Flags amp Counter R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 137 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group EE E enes 4 2 17 Real time Clock R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae Page 4 138 a ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 2 18 Watchdog Timer 1 R_WDT_Create Synopsis Prototype Description Return value Category Reference
219. eral register B PDL_MTU_REGISTER_TGRC General register C Valid for n 0 3 4 6 9 or 10 PDL_MTU_REGISTER_TGRD General register D Valid for n 0 3 4 6 9 or 10 PDL_MTU_REGISTER_TGRE General register E Valid for n 0 or 6 PDL_MTU_REGISTER_TGRF General register F Valid for n 0 or 6 Forn 5or 11 PDL_MTU_REGISTER_COUNTER_U Timer counter U register TCNTU PDL_MTU_REGISTER_COUNTER_V Timer counter V register TCNTV PDL_MTU_REGISTER_COUNTER_W_ Timer counter W register TCNTW PDL_MTU_REGISTER_TGRU General register U PDL_MTU_REGISTER_TGRV General register V PDL_MTU_REGISTER_TGRW General register W R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 03 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Apiary E enes Description 2 2 data4 For n 0 to 4 or 6 to 10 The timer counter TCNT value For n 5 or 11 The timer counter TCNTU value This will be ignored if the register is not selected data5 For n 0 to 4 or 6 to 10 The register TGRA value For n 5 or 11 The timer counter TCNTV value This will be ignored if the register is not selected data6 For n 0 to 4 or 6 to 10 The register TGRB value For n 5 or 11 The timer counter TCNTW value This will be ignored if the register is not selected data7 For n 0 3 4 6 9
220. errirrsrnrrdsiirrisrrrrnetrdnnaniaadiinuadannianeiednnanaiaadanwaaii nanna 2 12 213 Data Transfer Controler Driver siasii or nran aE EREET EAEE TEAR saneebeatedecsaateeeetauscieesdai dee 2 13 2 14 Multi Function Timer Pulse Unit Driver cece eeeeee ee eeeeeeeeeeeeeeeseeeaeeeseeeaeeeseeeaeeeeneaeeeseeaaeees 2 14 215 Port Qutpub Enable Driver visit eeraa ra a a gceebandd dean ra araa aea a aa iaaa 2 15 2 16 Programmable Pulse Generator Driver eccccceeeeeeeeeceeeeeeeneeeeeeaeeeeeeaeeeseeaeeeseesaeeeseeneeeeeeaaes 2 16 2AT S bIt TIMeN DNVG ia a A A a A A 2 17 2 18 Compare Match Timer Driver c cccccecceeceeeeecncee cece ee ceeeeeaececeeeeessecaanaeceeeeeseeecqaeaeeeeeeeeeeeesiseeees 2 18 2 19 Real time Clock DVG cscai ide etat at hin eta indiana inkl estate 2 19 2 20 Watchdog Timer Driver eriroriiioipennieiia iieri aneii adeir anei iia eii eA E iiiaae 2 20 2 21 Independent Watchdog Timer DIivel ccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeaeeeeeeeeeeeseeeaeeeseeeaeeeeseeaeeeeeenaes 2 21 2 22 Serial Communication Interface Driver ccc ee cence eeeeeeeeeeenneeeeeeeaeeeeeeaeeeeeeaeeeeeenaeeeeeeneeeeeeeaes 2 22 2 23 GRE Calculator DNE o a E eeecaneeniccelinticcia E E AEE 2 23 22A FO Bus Interface DIVO orei eepieelnnbhcdean obhaetatane cot eemicelachitcan chy tates 2 24 2 25 Serial Peripheral Interface Driver 0 ccccccececeeccececeeeeeceecaecaeeeeeeesecqeaaeceeeeeeesecceaecaeeeeeeesesseaeeeeees 2 25 2
221. errupt PDL_INTC_IROQI PDL_INTC_FALLING PDL_INTC_B 0 PDL_NO_FUNC i Configure the IRQ2 interrupt on pin IRQ2 A R_INTC_CreateExtInterrupt PDL_INTC_IRQ2 PDL_INTC_LOW PDL_INTC_A 7 TRQ2Handler irq2_low false while 1 Poll the IRQ1 flag R_INTC_GetExtInterruptStatus PDL_INTC_IROQ1 amp irq_ status R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae ENESAS Page 5 2 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group S Weagakxamples irq status amp 0x01 0 Disable IRQ1 R_INTC_ControlExtInterrupt PDL_INTC_IRQ1 PDL_INT_DISABLE Has IRQ2 triggered if irq2_low true Re enable the interrupt if the signal has returned to the high level R_IO_PORT_Compare L_IO_PORT_3_2 EnableIRQ2 void IRQOHandler void Process the IRQO event here the flag is cleared automatically switch_swl_pressed true void IRQ2Handler void Disable the level triggered interrupt R_INTC_ControlExtInterrupt PDL_INTC_IRQ2 PDL_INTC_DISABLI irq2_low true static void ReEnableIRQ2 void Re enable the interrupt and try to clear it R_INTC_ControlExtInterrupt PDL_INTC_IRQ2 PDL_INTC_ENABLE PDL_INTC_CLEAR_IR_FLAG i Figure 5 1 Example of Extern
222. f internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock s
223. f this information is not required True if all parameters are valid and the operation completed false if a parameter was out of range SCl R_SCl_Send R_SCI_Receive e The error flags are not modified by this function They are cleared when a new reception process is started 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Apiary E enes Program example RPDL definitions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h uint8_t StatusValue uintl6_t TxChars uintl6_t RxChars void func void Read the status of SCI channel 0 R_SCI_Get Status 0 amp StatusValue PDL_NO_PTR amp TxChars amp RxChars R20UT0084EE0004 Rev 0 04 Aug 25 2010 a 2 Page 4 156 a ENESAS Under development RX62N Group RX621 Group Preliminary Specification Specifications in this preliminary version are subject to change 4 Library Reference 4 2 21 CRC calculator 1 R_CRC_Create Synopsis Configure the CRC calculator Prototype bool R_CRC_Create uint8_t data II Configuration Description Enable the CRC and set the operating conditions data Calculation options To set multiple options at the same time use to separate each value e Polynomial selection PDL_CRC_ POLY CRC
224. ference 2 R_IO_PORT_ReadConirol Synopsis Prototype Description Return value Functionality References Remarks Program example Read an I O port s control registers bool R_IO_PORT_ReadConirol uint16_tdata1 Port or port pin selection uint8_t data2 Control register selection uint8_t data3 Data storage location Read an I O port pin control setting data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 e Select the register to be read PDL_IO_PORT_DIRECTION or Data direction register PDL_IO_PORT_INPUT_BUFFER or Input buffer control register PDL_IO_PORT_PULL_UP or Pull up control register Valid for ports 9 to E and G PDL_IO_PORT_TYPE Open drain control register Valid for ports 0 to 3 and C data3 The address to where the register value shall be stored The value will be between 0x00 and OxFF for a port 0 or 1 for a pin True if all parameters are valid and exclusive otherwise false I O port R_IO_PORT_Set R_IO_PORT_ModifyControl e Ensure that the specified register is valid for the selected port pin RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t direction uint8_t output Read the dir
225. finitions include r_pdl_definitions h void func void Shutdown IIC channel 1 R_IIC_Destroy 1 R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 166 4 Library Reference Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 3 R_IIC_MasterSend Synopsis Prototype Description Return value Category Reference Write data to a slave device bool R_IIC_MasterSend uint8_t data1 Channel selection uint16_tdata2 Channel configuration uint16_t data3 Slave address uint8_t data4 Data start address uint16_tdata5 Data count void func Callback function uint8_t data6 Interrupt priority level Transmit data on the specified channel data1 Select channel IICn where n 0 or 1 data2 Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Start Repeated Start condition control PDL_IIC_START_ENABLE or Choose whether or not to issue a Start or Repeated Start PDL_IIC_START_DISABLE condition at the beginning of the transfer Stop condition control PDL_IIC_STOP_ENABLE or Choose whether or not to issue a Stop condition at the end of PDL_IIC_STOP_DIS
226. function The event detection flags are cleared when a new transfer is started R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 176 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Apiary E enes Program example RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h void func void uint32_t status_flags uintl6_t tx_count Read the status of channel 0 R_IIC_GetStatus 0 amp status_flags tx_count PDL_NO_PTR R20UT0084EE0004 Rev 0 04 Aug 25 2010 a 2 Page 4 177 a ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 2 23 Serial Peripheral Interface 1 R_SPI_Create Synopsis Configure an SPI channel Prototype bool R_SPI_Create uint8_t data1 Channel selection uint32_t data2 uint32_t data3 uint32_t data4 uint32_t data5 Data format Description 1 3 Set up the selected SPI channel R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 178 data1 Select channel SPIn where n 0 to 1 data2 Channel configuration II Extended timing control Bit rate or register value 4 Library Reference Configure the channel mode and connect
227. hange RX62N Group RX621 Group 4 Dbia Reiben Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h uint8_t Flags uintl6_t Counter uintl6_t CompareMatchA uintl6_t CompareMatchB void func void Read the status flags and registers for TMR unit 0 R_TMR_ReaduUnit 0 amp Flags amp Counter amp CompareMatchA amp CompareMatchB R20UT0084EE0004 Rev 0 04 Aug 25 2010 a 2 Page 4 130 a ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 4 2 16 Compare Match Timer 1 R_CMT_Create Synopsis Prototype Description Configure a CMT channel bool R_CMT_Create uint8_t data1 Timer channel selection uint16_t data2 Configuration selection float data3 II Period frequency or register data void func II Callback function uint8_t data4 Interrupt priority level Set up a Compare Match Timer channel and start the timer data1 The channel number n where n 0 1 2 or 3 data2 Configure the timer To set multiple options at the same time use to separate each value The default settings are shown in bold Clock calculation The parameter data3 will specify the timer period PDL_CMT_PERIOD or The counte
228. hannel n n 0 to 3 or 5 to 6 PDL_DMAC TRIGGER SCIO TX or PDL_DMAC_ TRIGGER SCI1_TXor PDL_DMAC TRIGGER SCI2 TX or PDL_DMAC TRIGGER SCI3_TX or PDL_DMAC TRIGGER SCI5 TX or PDL_DMAC TRIGGER SCI6 TX or Transmit buffer empty on SCI channel n n 0 to 3 or 5 to 6 PDL_DMAC_TRIGGER_IICO_RX or PDL_DMAC_TRIGGER_IIC1_RX or Receive buffer full on I C channel n n 0 to 1 PDL_DMAC_TRIGGER_IICO_TX or PDL_DMAC_TRIGGER_IIC1_TX Transmit buffer empty on I C channel n n 0 to 1 data4 The source start address data5 The destination start address data6 The number of transfers to take place For normal mode valid between 0 and 65535 0 free running mode For repeat and block mode valid between 0 and 1023 0 1024 transfers 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group A ibrar Referenc Description 3 3 data7 The repeat or block size for each transfer Valid between 0 and 1023 0 1024 units Ignored in normal mode data8 The address offset value The range is from 16 777 215 to 16 777 216 This value is ignored if the offset function is not selected data9 The source address extended repeat value The value can be any power of 2 from 2 to 2 Set this value to 0 if the extended repeat function is not required for the sour
229. high or disabled for signal SSL2 PDL SPI _PIN_SSL3 LOW or PDL SPI PIN SSL3_ HIGH or PDL_SPI_PIN SSL3_DISABLE Select active low active high or disabled for signal SSL3 PDL_SPI_PIN_MOSI_IDLE_LAST or PDL_SPI_PIN_MOSI_IDLE_LOW or PDL_SPI_PIN_MOSI_IDLE_HIGH The MOSI output state when no SSLn pin is active 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Description 2 3 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 179 data3 4 Library Reference Configure the data format If multiple selections are required use to separate each selection The default settings are shown in bold Buffer size PDL_SPI_BUFFER_64 or PDL_SPI_BUFFER_128 Select a buffer size of 64 bits up to four 16 bit frames or 128 bits up to four 32 bit frames Frame configuration selection see figure 32 2 in the hardware manual Selection Number of frames in a Number of commands command transfer PDL_SPI_FRAME_1_1 or PDL_SPI_FRAME_1_2 or PDL_SPI_FRAME_1_3 or PDL_SPI_FRAME_1_4 or PDL_SPI FRAME 2 1 or PDL_SPI FRAME 2 2or PDL_SPI_FRAME_3 or PDL_SPI_FRAME_4 or PDL_SPI_FRAME_5 or PDL_SPI FRAME 6 or PDL_SPI FRAME 7 or PDL_SPI FRAME 8 ONDOARWNDND A aaa ONDOARWANBRWDND Parity bit control PDL_SPI_PARITY_NONE or PDL_SPI_PARITY_EVEN
230. ifications in this preliminary version are subject to change RX62N Group RX621 Group Description 3 8 4 Library Reference e Counter clock source selection Valid for n 5 or 11 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 85 PDL_MTU_CLKU_PCLK_DIV_1 or PDL_MTU_CLKU_PCLK_DIV_4 or PDL_MTU_CLKU_PCLK_DIV_16 or PDL_MTU_CLKU_PCLK_DIV_64 or Counter TCNTU is supplied by the internal clock signal PCLK 1 4 16 or 64 PDL_MTU_CLKV_PCLK_DIV_1 or PDL_MTU_CLKV_PCLK_DIV_4 or PDL_MTU_CLKV_PCLK_DIV_16 or PDL_MTU_CLKV_PCLK DIV _64 or Counter TCNTV is supplied by the internal clock signal PCLK 1 4 16 or 64 PDL_MTU_CLKW_PCLK_DIV_1 or PDL_MTU_CLKW_PCLK_DIV_4 or PDL_MTU_CLKW_PCLK_DIV_16 or PDL_MTU_CLKW_PCLK_DIV_64 or Counter TCNTW is supplied by the internal clock signal PCLK 1 4 16 or 64 e Counter clearing U V and W counters Valid for n 5 or 11 PDL_MTU_CLEAR_TGRU_DISABLE or PDL_MTU_CLEAR_TGRU_ENABLE Disable or enable clearing of TCNTU by TGRU compare match or input capture PDL_MTU_CLEAR_TGRV_DISABLE or PDL_MTU_CLEAR_TGRV_ENABLE Disable or enable clearing of TCNTV by TGRV compare match or input capture PDL_MTU_CLEAR_TGRW_DISABLE or PDL_MTU_CLEAR_TGRW_ENABLE Disable or enable clearing of TCNTW by TGRW compare match or input capture data4 Configure the ADC trigger operation If multiple selections are required use
231. ignal is stable 5 Differences between Products Before changing from one product to another i e to one with a different part number confirm that the change will not lead to problems The characteristics of MPU MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern When changing to products of different part numbers implement a system evaluation test for each of the products Table of Contents Table of Contents 04 0 1 eee Ae ete ee eee ee ee 1 1 Mss WMtrOGUGHON ENEE E E A T E E E E A E ied E A E E E eae 1 1 1 1 Using the library within your project amea E E A E EE 1 2 1 1 1 Unzip the RPDIEHIES eas nente aeaea eaa Aa ra Aeae aED Ae ae E aeaa EINER ILa sats 1 2 1 1 2 Copy the files into your project area sesssesssrrsssrrrrnssrresrirrestsnnesrirsnnisnneaatinasatannaanaaaani anaana 1 2 1 1 3 mMelude the tew directory eera iarria edsin I AREE REAR ATAA ARANEAE EARE E EATUR AAA E PARRAK ARAR A 1 4 1 1 4 Include the new source files lt i c ee eccacseecsestieneccacaveebsnacaedensaisenensaceevenssedisesanetenessnesedensaerebeneaees 1 5 1 1 5 Avoid conflicts with standard project files eeseeeeeeseseeeseerneseerresterrssttnrrnsttnnssttnnnsttnnnstennnnenn 1 6 EE E ET AE E E E T S EE E EE A A TT E E T E AT 1 6 AD EXCISION oane ae AAE REA EAE ARE R E AEE RRE A EAA 1 7 16s Add the library Mepal srai artat REE aA ARAE AA aE TA
232. iminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 6 R_SCI_Control Synopsis Prototype Description Return value Category Reference Remarks Control the SCI channel bool R_SCI_Conitrol uint8_t data1 Channel selection uint8_t data2 Channel control Stops SCI transmission or reception data1 Select channel SClin where n 0 to 6 but not 4 data2 Control the channel If multiple selections are required use to separate each selection e Select the process to be stopped Stop the transmission process PDL_SCI_STOP_TX If areception process is active the transmit output will not become idle until the reception process has stopped Stop the reception process If a transmission process is active the receive error flags may be set erroneously These can be ignored and will be cleared when a new reception process is started PDL_SCI_STOP_RX The option PDL_SCI_STOP_TX_AND_RxX can be used to select both processes If both processes are selected transmission and reception will stop immediately e Generate a Space or Mark signal when idle Set the idle output to Space logic 0 EDI SCOP TPOTSFACe This can be used to generate a Break condition PDL_SCIl_OUTPUT_MARK Set the idle output to Mark logic 1
233. in 6 A callback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed If the channel is configured for phase counting mode the counter clock source setting is ignored If buffer operation is selected for registers TGRA and TGRC input capture output compare is not valid for register TGRC If buffer operation is selected for registers TGRB and TGRD input capture output compare is not valid for register TGRD If synchronous mode is required at least two channels must be enabled for synchronous operation A companion function R_LMTU_Create_load_defaults can be used to load the default values into the structure RPDL definitions nclude r_pdl_mtu h RPDL device specific definitions nclude r_pdl_definitions h id func void Allocate a copy of the structure for the selected channel R_MTU_Create_structure ch4_parameters Load the defaults R_MTU_Create_load_defaults amp ch4_parameters Set the non default options for channel 4 ch4_parameters data2 PDL_MTU_SYNC_ENABLE PDL_MTU_TGRA_DTC_TRIGGER_ENABLE ch4_parameters data3 PDL_MTU_CLK_PCLK_DIV_4 ch4_parameters data5 PDL_MTU_BUFFER_AC_CM_A ch4_parameters data7 PDL_MTU_C_OC_HIGH_CM_LOW ch4_parameters data9 0 ch4_parameters datal0O 199 ch4_parameters datall 99 ch4_pa
234. ing_3 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 68 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 4 R_DMAC_ GetStatus Synopsis Prototype Description Return value Check the status of a DMA channel bool R_DMAC_GetStatus uint8_t data1 Channel number uint8_t data2 Status flags pointer uint32_t data3 Current source address pointer uint32_t data4 Current destination address pointer uint16_t data5 Current transfer count pointer uint16_t data6 Current Repeat or Block size count pointer Return status flags and current channel registers data1 The channel number n where n 0 to 3 data2 The status flags shall be stored in the following format Specify PDL_NO_PTR if the flags are not to be read b7 b5 b4 b3 b2 b1 bO Interrupt Transfer Escape Transfer End Status Transfer request End interrupt ESIF interrupt DTIF ACT enable DTE IR 0 Idle 0 Idle 0 Idle 0 Disabled 1 Generated 1 Generated 1 Operating 1 Enabled data3 Where the current source address shall be stored Specify PDL_NO_PTR if it is not required data4 Where the current destination address shall be stored Specify PDL_NO_PTR if it is not requir
235. ion void ADClIntFunc void void func void Set up ADC 1 at 50 MHz in single mode using AN1 with 0 6ys sampling time R_ADC_10_Create 1 PDL_ADC_10_CHANNELS_OPTION_2 50E6 6 ADClIntFunc 2 Set up ADC 1 at 50 MHz in single mode using AN1 R_ADC_10_Create 1 PDL_ADC_10_CHANNELS_OPTION_2 PDL_ADC_10_ADSSTR_SPECIFY 50E6 0x40 ADC1IntFunc 2 R20UT0084EE0004 Rev 0 04 Aug 25 2010 a 2 Page 4 193 a ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 2 R_ADC_10 Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Shut down an ADC unit bool R_ADC_10_Destroy uint8_tdata ADC unit selection Put the ADC into the Power down state with minimal power consumption data Select the ADC unit 0 or 1 to be shut down True if a valid unit is selected otherwise false ADC R_ADC_10_Create e This function waits for the ADST flag to indicate that the converter has stopped If the ADC unit s control registers are directly modified by the user this function may lock up RPDL definitions include r_pdl_adc_10 h RPDL device specific definitions include r_pdl_definitions h void f
236. ion a Repeated Start condition shall be generated If the Start condition is disabled the slave address will not be transmitted If no callback function is specified for transmission completion this function will monitor the status flags to manage the data transmission If the I C channel s registers are modified directly by the user this function may lock up If false is returned use R_IIC_GetStatus to check if an unexpected event on I C bus was the cause of the failure If the transfer has ended prematurely use R_IIC_Control to issue a Stop condition False will be returned if the DMAC channel has not been allocated using R_DMAC_Create RPDL definitions nclude r_pdl_iic h RPDL device specific definitions nclude r_pdl_definitions h nst uint8_t data_array 5 0x23 0x48 0x59 0x60 OxFE id func void Send 5 bytes to device 0x0A0 on channel 1 using polling R_IIC_MasterSend 1 PDL_NO_DATA Ox0AO data_array 5 PDL_NO_FUNC 0 R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 168 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 4 R_IIC_MasterReceive Synopsis Prototype Description Return value Category Reference Read data from a slave device bool R_IIC_MasterReceive uint8_t data1
237. ion Circuit must be configured before configuring any timer channel R20UT0084EE0004 Rev 0 04 Aug 25 2010 Seeger RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 19 Real time Clock Driver R20UT0084EE0004 Rev 0 04 Aug 25 2010 ee RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 20 Watchdog Timer Driver The driver functions support the use of the watchdog timer providing the following operations 1 Configuring the timer for use including Automatic clock setting using frequency or period as an input Internal timer mode Watchdog timer mode MCU reset generation while in watchdog timer mode Automatic interrupt control 2 Control of the timer including e Stopping the timer e Counter refresh to prevent overflow 3 Reading the timer status and counter register Note The Clock Generation Circuit should be configured before configuring this timer R20UT0084EE0004 Rev 0 04 Aug 25 2010 sae RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 21 Independent Watchdog Timer Driver R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 2 21 Under development Preliminary Specifica
238. ion settings If multiple selections are required use to separate each selection The default settings are shown in bold Connection mode PDL_SPI_MODE_SPI_MASTER or PDL_SPI_MODE_SPI_SLAVE or PDL_SCI_LMODE_SYNC_MASTER or PDL_SCl_MODE_SYNC_SLAVE PDL_SPI_MODE_SPI_MULTI_MASTER or The required SPI four wire or Clock synchronous three wire operation connection type e Reception control PDL_SPI_FULL_DUPLEX or PDL_SPI_TRANSMIT_ONLY Enable or disable reception operations e Pin selection and control PDL_SPI_PIN_CMOS or PDL_SPI_PIN_OPEN_ DRAIN Select CMOS or Open drain output type PDL_SPI_PIN Aor PDL_SPI_PIN B Select the A or B pins for signals MISO MOSI RSPCK SSLO SSL1 SSL2 and SSL3 PDL_SPI_PIN_RSPCK_ENABLE or PDL_SPI_PIN_RSPCK_DISABLE Enable or disable signal RSPCK PDL_SPI_PIN_MOSI_ENABLE or PDL_SPI_PIN_MOSI_DISABLE Enable or disable signal MOSI PDL_SPI_PIN_MISO_ ENABLE or PDL_SPI_PIN_MISO_DISABLE Enable or disable signal MISO PDL_SPI_PIN_SSLO_LOWor PDL_SPI_PIN_SSLO_HIGH or PDL_SPI_PIN SSLO_ DISABLE Select active low active high or disabled for signal SSLO PDL_SPI_PIN_SSL1_LOWor PDL_SPI_PIN_SSL1_HIGH or PDL_SPI_PIN SSL1_DISABLE Select active low active high or disabled for signal SSL1 PDL SPI PIN_SSL2_LOW or PDL SPI PIN SSL2_ HIGH or PDL_SPI_PIN_SSL2_DISABLE Select active low active
239. is set to high impedance e Data length PDL_SCI_8_BIT_LENGTH or PDL_SCI_7 BIT_LENGTH 8 or 7 bit data length e Parity mode PDL_SCI_PARITY_NONE or No parity bit even parity bit or odd parity bit PDL_SCI_PARITY_EVEN or Note Do not set parity bit for Multi Processor PDL_SCI_PARITY_ODD Asynchronous mode Stop bit length PDL_SCI_STOP_1 or PDL_SCI_STOP 2 One or two stop bits R20UT0084EE0004 Rev 0 04 Aug 25 2010 e RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Description 2 3 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 146 4 Library Reference The option PDL_SCI_8N1 can be used to select 8 bit data length no parity and one stop bit Options which are available in Clock Synchronous mode Data clock source selection PDL_SCI_CLK_INT_OUT or Select the On chip baud rate generator The SCKn pin outputs the bit clock PDL_SCI_CLK_EXT Input the clock to the SCKn pin Options which are available in Smart Card Interface mode e Base clock pulse cycle count PDL_SCI_BCP_32 or PDL_SCI_BCP_64 or PDL_SCI_BCP_93 or PDL_SCI_BCP_128 or PDL_SCI_BCP_186 or PDL_SCI_BCP_256 or PDL_SCI_BCP_372 or PDL_SCI_BCP 512 The number of base clock cycles in a 1 bit data transfer period Parity selection PDL_SCI_PARITY_EVEN or
240. is specified for all parameters func1 func2 and funcs Return value True if all parameters are valid and exclusive otherwise false Category Timer TMR Reference R_TMR_Destroy R_TMR_ControlChannel R_ TMR_ControlUnit R TMR_ReadChannel R_TM R_ReadUnit R_LTMR_Set Remarks e Ifan input pin TMCIx or TMRIy is selected this function will configure the direction and input buffer control for that pin Please use R_TMR_Set to select source A B of the input signals if needed The default source selection is based on value after MCU reset e If the output pin TMOy is made active this function will disable other output functions on that pin e Ifa callback function is specified this function will enable the relevant interrupt Please see the notes on callback function usage in 6 e A callback function is executed by the interrupt processing function interrupt can be processed until the callback function has completed R20UT0084EE0004 Rev 0 04 Aug 25 2010 Saag i RENESAS This means that no other Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Grou P P 4 Library Reference Program example include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Configure TMR unit 0 PCLK clear after a compare match A R_TMR_CreateUnit
241. it or modify it by the value specified in parameter data7 Address offset is valid only for n 0 Transfer data size PDL_DMAC_SIZE_8 or PDL_DMAC_SIZE_16 or PDL_DMAC_SIZE_32 Select 8 16 or 32 bits for the data to be transferred e Interrupt generation PDL_DMAC_IRQ_END Transfer completion PDL_DMAC_IRQ_ESCAPE_END Escape end PDL_DMAC_IRQ REPEAT SIZE_END 1 repeat size or 1 block data transfer completion PDL_DMAC_IRQ EXT_SOURCE Extended repeat area overflow on the source PDL_DMAC_IRQ_EXT_DESTINATION Extended repeat area overflow on the destination e Start trigger forwarding PDL_DMAC_TRIGGER_CLEAR or PDL_DMAC_TRIGGER FORWARD When the DMAC transfer is complete clear the DMAC activation trigger or pass it on to the CPU R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 63 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Description 2 3 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 64 data3 Select the activation source for channel DMAn Trigger selection 4 Library Reference Name Trigger cause PDL_DMAC_TRIGGER_SW or By software PDL_DMAC_TRIGGER_CMTO or PDL_DMAC_TRIGGER_CMT1 or PDL_DMAC_TRIGGER_CMT2 or PDL_DMAC_TRIGGER_CMT3 or Compare match on channel CMTn n 0 to 3
242. ity the return value is not checked in the examples used in this manual R20UT0084EE0004 Rev 0 04 Aug 25 2010 Seg RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group dieing Resrenes 4 2 1 Clock Generation Circuit 1 R_CGC _ Set Synopsis Configure the clock generation circuit Prototype bool R_CGC_Set uint32_t data1 Input frequency uint32_t data2 System clock frequency uint32_t data3 Peripheral module clock frequency uint32_t data4 External bus clock frequency uint16_tdata5 Configuration options Description Set the clock output frequencies and options data1 The frequency of the main clock oscillator in Hertz data2 The desired frequency of the System clock ICLK in Hertz data3 The desired frequency of the Peripheral module clock PCLK in Hertz data4 The desired frequency of the External Bus clock BCLK in Hertz Specify 0 if the value is not important data5 Configuration options If multiple selections are required use to separate each selection The default settings are shown in bold BCLK pin output control PDL_CGC_BCLK_DIV_1 or Output the external bus clock BCLK PDL_CGC_BCLK_DIV_2 or BCLK 2 PDL_CGC_BCLK_DISABLE or leave the pin as an input PDL_CGC_BCLK_HIGH or fix the pin high e SDCLK pin output con
243. iver Library Peripherals supported by the RPDL Target MCU Figure 1 2 System configuration with middleware taking direct control of some peripherals The library is packaged as a Abinary file containing all of the peripheral driver functions b Header files containing the information that the user needs to call any of the functions from their own application code and c Interrupt handlers supplied as source code For best use of this library It is required that the user will have the following documents as a minimum i The schematic ii The MCU hardware manual iii This RPDL API User s manual The binary file is produced using the Renesas RX C compiler It should be usable by another linker that conforms to the Renesas Application Binary Interface The coding standards and naming conventions are specified by Renesas The driver source code is tested for compliance with the MISRA C 2004 guidelines R20UT0084EE0004 Rev 0 04 Aug 25 2010 ape RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 1 Introduction 1 1 Using the library within your project The driver library can be used 1 Via the PDG graphical utility PDG can be downloaded from www renesas com pdg The directions for use of the PDG utility are given in the PDG manual 2 Or added to a project by the user and used stand alone To add the driver library to your
244. l R_BSC_Destroy uint8_t data Area selection Description Disable an external bus area data Select the external bus area CSn where n 0 to 7 to be disabled Return value True Category Bus Controller Reference R_BSC_CreateArea Remarks be nee error interrupt request will not be disabled by this function Use R_BSC_Control to isable it e Port Function Control registers PFOCSE are modified by this function Program example RPDL definitions include r_pdl_bsc h RPDL device specific definitions include r_pdl_definitions h void func void Disable the CS4 area R_BSC_Destroy 4 i R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 59 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 R_BSC_Control Synopsis Prototype Description Modify the External Bus amp SDRAM Controller operation bool R_BSC_Control uint16_t data Control options Control the BSC amp SDRAM operation data Control the BSC amp SDRAM operation Only one control operation is allowed at one time Error clearing 4 Library Reference PDL_BSC_ERROR_CLEAR Clear the bus error status registers SDRAM initialization PDL_BSC_SDRAM_INITIALIZATION Perform SDRAM initialization
245. l definitions 3 2 1 PDL_NO_ FUNC Used as a parameter when there is no applicable function 3 2 2 PDL_NO PTR Used as a parameter when there is no applicable data location 3 2 3 _PDL_NO_ DATA Used as a parameter when there is no applicable data value 3 2 4 PDL_MCU_GROUP The family supported by this build of the driver library It is defined as RX62N A usage example is if PDL_MCU_GROUP RX62N error Wrong RPDL endif 3 2 5 PDL_VERSION The version number of the RPDL library The number is stored in BCD format xx xx For example 0100h is v1 00 A usage example is const uintl 6_t rpdl_version_number PDL_VERSION R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 3 1 Under development Preliminary Specification 4 Library Reference 4 1 API List by Peripheral Function Table 4 1 lists the Renesas Embedded APIs by peripheral function Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference Table 4 1 Renesas Embedded API List Category Number Name Description Clock Generation Circuit R CGC Set Configure the clock generation circuit R_CGC_Control Modify the clock generation circuit operation R_CGC_GetStatus Read the clock status register Interrupt control unit R_INTC_CreateExtInterrupt Configure an external interrupt pin R_INTC_CreateSoftwarelnterrupt
246. le SDRAM operation R_BSC_Control PDL_BSC_SDRAM DISABLE Check the status flags do R_BSC_GetStatus amp statusl amp status2 amp sdram_status while sdram_status 0 Start Self Refresh R_BSC_Control PDL_BSC_SDRAM_SELF_ REFRESH ENABLE RRR KKK KK KKK KK KK T Self Refresh mode ROR KK OK KK KK endif rrtt Entering Deep Software Standby mode 4e Find out what caused the exit from deep software standby R_LPC_GetStatus amp status_flags Configure the NMI pin P35 ensure NMIER BIT NMIEN 1 R_INTC_CreateExtInterrupt PDL_INTC_NMI PDL_INTC_FALLING NMI_handler_lpc 7 Allow a falling edge on NMI to cancel deep software standby to ensure uninitialized data e g B section are retained SBYCR OPE 1 DPSBYCR IOKEEP 1 R_LPC_Create PDL_LPC_CANCEL_NMI_FALLING PDL_LPC_RAM USB_DETECT_ON PDL_LPC_EXT_BUS_ON PDL_LPC_IO_DELAY PC_STANDBY_64 PDL_LPC_DEEP_STANDBY_1024 i Enter deep software standby mode An internal reset will occur R_LPC_Control PDL_LPC_MODE_DEEP_SOFTWARE_STANDBY R20UT0084EE0004 Rev 0 04 Aug 25 2010 ztENESAS Page 5 9 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Weage Examples RR KKK
247. lected this function will configure the direction and input buffer control for that pin Please use R_TMR_Set to select source A B of the input signals if needed The default source selection is based on value after MCU reset e If the output pin TMOn is made active this function will disable other output functions on that pin A closed clock loop will be created if The overflow signal from TMR1 is selected for TMRO and the compare match A signal from TMRO is selected for TMR1 or The overflow signal from TMR3 is selected for TMR2 and the compare match A signal from TMRz2 is selected for TMR3 Either case should be avoided e Ifa callback function is specified this function will enable the relevant interrupt Please see the notes on callback function usage in 6 e A callback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 112 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Apiary E enes Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Configure TMRO PCLK clear after a compare match A R_TMR_CreateChanneli 0 PDL_TMR_CLK_PCLK_DIV_1
248. lse width as an input Automatic interrupt control CPU sleep option I O pin control Automatic I O pin configuration Automatic support for using two channels as a single 16 bit timer Disabling channels that are no longer required and enabling low power mode Control of a single timer channel Control of two timer channels when configured as one 16 bit channel Control of channels in periodic mode enabling pulse width modulation PWM output Reading the registers of a single timer channel 10 Reading the registers of a 16 bit timer channel pair Note The Clock Generation Circuit must be configured before configuring any timer channel R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 2 17 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 18 Compare Match Timer Driver The driver functions support the use of the four 16 bit timers providing the following operations 1 Configuration for use including e Automatic clock setting using frequency or period as an input e Manual clock setting using register values as inputs e Automatic interrupt control 2 Configuration for use as a one shot timer 3 Disabling channels that are no longer required and enabling low power mode 4 Control of a timer including constant register updates 5 Control of a timer including change of frequency Note The Clock Generat
249. lude r_pdl_definitions h void func void Configure operation using a 12 5 MHz input clock ICLK 100 MHz PCLK 50 MHz BCLK 25 MHz R_CGC_Set 12 5E6 100E6 50E6 25E6 PDL_CGC_BCLK_ENABL R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 7 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 R_CGC _ Control Synopsis Modify the clock generation circuit operation Prototype bool R_CGC_Conirol uint16_t data Control options Description Modify the clock control registers data 4 Library Reference Control options If multiple selections are required use to separate each selection e SDCLK pin output control PDL_CGC_SDCLK_ENABLE or PDL_CGC_SDCLK_DISABLE Enable or disable the SDRAM clock SDCLK output e Sub clock oscillator control PDL_CGC_SUB_CLOCK_ENABLE or PDL_CGC_SUB_CLOCK_DISABLE Enable or disable the sub clock oscillator Return value Functionality Clock generation circuit References None Remarks None Program example R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 8 RPDL definitions include r_pdl_cgc h True if all parameters are valid and exclusive otherwise false RPDL device specific d
250. minary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Description 3 3 data4 The interrupt priority level Select between 1 lowest priority and 15 highest priority 4 Library Reference This parameter will be ignored if PDL_NO_FUNC is specified for parameter func in functions R_SCI_Send or R_SCI_Receive Return value Category Reference Remarks SCI Function R_CGC_Set must be called before any use of this function R_SCI_Set R_SCI_Destroy R_SCI_Send R_SCI_Receive True if all parameters are valid exclusive and achievable otherwise false This function configures each SCI pin that is required for operation It also disables the alternative modes on those pins Some SCI pins are multiplexed with other peripheral pins please refer to I O Ports session in RX62N Hardware Manual to ensure that the conflicting peripheral pins are not being used at the same time The wait time of 1 data bit period that is required during configuration is handled within this function The range of achievable bit rates is listed below Data clock cea feck meee source Erne 50 MHz 12 5 MHz 32MHz 8 MHz i teinal Minimum 95 24 61 15 Asynchronous Maximtm 3 125 000 781 250 2 000 000 500 000 External 1 562 500 390 625 1 000 000 250 000 internal Minimum 763 191 488 122
251. mplete when a stop condition is detected Category C Reference R_IIC_SlaveMonitor Remarks Use this function in conjunction with R_IIC_SlaveMonitor e If the master requires more data than is supplied and polling or interrupt based transfers are used this function shall loop back to the start of the data The transmitted byte count will also be reset to 0 Program example RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h const uint8_t data_array 5 0x23 0x48 0x59 0x60 OxFE void func void Assign 5 bytes to be read by a master on channel 0 R_IIC_SlaveSend 0 data_array 5 i R20UT0084EE0004 Rev 0 04 Aug 25 2010 imee RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 8 R_IIC_Control Synopsis Prototype Description Return value Category Reference Remarks Program example Group C channel control bool R_IIC_Control 4 Library Reference uint8_t data1 Channel selection uint8_t data2 Control options Modify the operation of the selected I C channel data1 Select channel IICn where n 0 or 1 data2 Control the channel If multiple selections are required use
252. n Return value Category Reference Remarks R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 155 Acquires the channel status and the byte counts data1 Select channel SCIn where n 0 to 6 but not 4 data2 The status flags shall be stored in the format Asynchronous or Synchronous mode b7 b6 b5 b4 b3 b2 b1 bO Buffer status Reception error detection Transmit RxD pin Transmit Receive Overrun Framing Parity status 0 level 0 Full 0 Empty 0 No error 0 No error 0 Noerror 0 Active 0 Low 1 Empty 1 Full 1 Detected 1 Detected 1 Detected 1 Idle 1 High Smart card mode b7 b6 b5 b4 b3 b2 b1 bO Buffer status Error detection Transmit RxD pin Transmit Receive Overrun Error signal Parity status 0 level 0 Full 0 Empty 0 No error 0 No error 0 No error 0 Active 0 Low 1 Empty 1 Full 1 Detected 1 Detected 1 Detected 1 Idle 1 High data3 The storage location for the last byte that was received Specify PDL_NO_PTR if this information is not required data4 The storage location for the number of characters that are have been transmitted in the current transmission Specify PDL_NO_PTR if this information is not required data5 The storage location for the number of characters that are have been received in the current reception process Specify PDL_NO_PTR i
253. n R_DTC_Create PDL_DTC_NORMAL PDL_DTC_SOURCE_ADDRESS_PLUS PDL_DTC_DESTINATION_ADDR PDL C_SIZE_8 PDL_DTC_IRQ COMPLETE PDL_DTC_TRIGGER_ICTXI1 __D1 _D _ D1 2D R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 5 45 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group amp Weagakexamplee dtc_iicl_tx_transfer_data eeprom_data_array_l uint8_t amp RIIC1 ICDRT 6 PDL_NO_DATA Set up a DTC channel for IIC reception R_DTC_Create PDL_DTC_NORMAL PDL_DTC_SOURCE_ADDRESS_ FIXED PDL_DTC_DESTINATION_ADDRESS PLUS PDL _DTC_SIZE_8 PDL_DTC_IROQ_COMPLETE PDL_DTC_TRIGGER_ICRXI1 dtc_iicl_rx_transfer_data uint8_t amp RIIC1 ICDRR data_storage 4 PDL_NO_DATA Select I C mode at 100kHz 300ns rise time 200ns fall time R_IIC_Create 0 PDL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 0 0 0 0 100E3 300 lt lt 16 200 Enable the DTC R_DTC_Control PDL_DTC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA Write the data into the EEPROM write_eeprom_data Prepare the next data for the EEPROM R_DTC_Control PDL_DTC_UPDATE_ SOURCE PDL_DTC_UPDATE_COUNT dtc_iicl_tx_transfer_data eeprom_data
254. n of slave address 2 in PDL_IIC_SLAVE_2 ENABLE 7 or 7 bit or PDL_IIC_SLAVE_ 2 ENABLE 10 10 bit format PDL_IIC_SLAVE_GCA_DISABLE or Disable or enable detection of the General Call PDL_IIC_SLAVE_GCA_ ENABLE address Device ID detection control PDL_lIC_DEVICE_ID_DISABLE or Disable or enable detection of the Device ID address PDL_IIC_DEVICE_ID_ ENABLE 1111 100b Host Address detection control PDL_IIC_HOST_ADDRESS_DISABLE or Disable or enable detection of the SMBus host PDL_IIC_HOST_ADDRESS_ENABLE address data4 Slave address 0 Ignored if slave address 0 detection is disabled data5 Slave address 1 Ignored if slave address 1 detection is disabled data6 Slave address 2 Ignored if slave address 2 detection is disabled data7 Transfer rate control Either The maximum bit rate in bits per second For Master mode the clock division values will be calculated using a 50 duty cycle For Slave mode the rate will be used to calculate the clock stretching period Or b31 b30 b13 b12 b8 b7 b5 b4 bO 1 Bit rate high level register _ Bit rate low level register ICBRH value ICBRL value R20UT0084EE0004 Rev 0 04 Aug 25 2010 Sagi RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Jiban Repsrenes Description 3 3 data8 Rise and fall time compens
255. n this preliminary version are subject to change RX62N Group RX621 Grou P P 4 Library Reference 4 2 Description of Each API This section describes each API and explains how to use them showing a program example for each The description of each API is divided into the following items Synopsis Summarises processing by the API function Prototype The function format and a brief explanation of the arguments Description Explains how to use the API function and shows assignable parameters separating each argument with argumen Return value Describes the returned value of the API function Category Indicates the category of the API function Reference Indicates the API functions to be referred Remark Describes notes to use the API function Program example Represents how to use the API function by a program example Two examples of return value checking are shown below RPDL definitions include r_pdl_pfc h include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h void func void bool result Write OxFF to register PFC1 result R_PFC_Write 1 OxFF if result false Handle th rror here Keep trying to send a string if the channel is busy do result R_SCI_Send 2 Renesas RX NULL PDL_NO_FUNC i whil result false For clar
256. nary version are subject to change RX62N Group RX621 Group Description 3 3 The format must be either data5 The maximum required bit rate If only Slave mode will be used specify PDL_NO_DATA Or Return value Category Reference Remarks Program example b31 b30 to b8 4 Library Reference b7 b0 1 0 The SPBR register value True if all parameters are valid otherwise false SPI e Function R_ CGC_Set must be called before any use of this function e Aor B pin selection is not available on the 85 pin package RPDI L definitions include r_pdl_spi h RPDI L device specific definitions include r_pdl_definitions h void func void Configure SPI channel 0 R_SPI_Create 0 PDL_SPI_MODE_SPI_MASTER PDL_SPI_PIN_SSLO_LOW PDL_SPI_PIN_A PDL_SPI_FRAME_1_1 PDL_NO_DATA 24E6 R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 180 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Laban Reierenc 2 R_SPI_Destroy Synopsis Shutdown an SPI channel Prototype bool R_SPI_Destroy uint8_t data Channel selection Description Shutdown the selected SPI channel data Select ch
257. nary version are subject to change RX62N Group RX621 Group 5 sage Examples Shutdown unit 2 R_ADC_10_Destroy 0 void ADC1Handler void R_ADC_10_Read 1 adcl_result Figure 5 30 Example of ADC Conversion R20UT0084EE0004 Rev 0 04 Aug 25 2010 Saree RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Weagekxamplez 2 ADC Self Diagnostic function Figure 5 31 shows a usage example of ADC Self Diagnostic function ADC unit 0 is set to get the A D conversion of Vref x 1 voltage value ADC unit 1 is set to get the A D conversion of Vref x 0 voltage value PDL functions include r_pdl_adc_10 h finelude e pdl_ ege h include r_pdl_intc h PDL device specific definitions include r_pdl_definitions h void ADCO callback void volatile uint8_t adcO_complete uintl6_t result_adc0O uintl6_t result_adcl void main void Configure the clocks R_CGC_Set 12E6 96E6 48E6 0 PDL_CGC_BCLK_HIGH Configure ADC unit 0 R_ADC_10_Create 0 PDL_ADC_10_SELF_DIAGNOSTIC_VR 12E6 20E 6 ADCO_callback 7 Configure ADC unit 1 R_ADC_10_Create 1 PDL_ADC_10_SELF_DIAGNOSTIC_VR 48E6 0 5E 6 PDL_NO_FUNC 0 adcO_complete false Start ADCO R_ADC_10_Control PDL_ADC_10_0_ON PDL_ADC_1
258. nesas Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 49 211 65030 Fax 49 211 6503 1327 Renesas Electronics China Co Ltd 7th Floor Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100083 P R China Tel 86 10 8235 1155 Fax 86 10 8235 7679 Renesas Electronics Shanghai Co Ltd Unit 204 205 AZIA Center No 1233 Lujiazui Ring Rd Pudong District Shanghai 200120 China Tel 86 21 5877 1818 Fax 86 21 6887 7858 7898 Renesas Electronics Hong Kong Limited Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 852 2886 9318 Fax 852 2886 9022 9044 Renesas Electronics Taiwan Co Ltd 7F No 363 Fu Shing North Road Taipei Taiwan Tel 886 2 8175 9600 Fax 886 2 8175 9670 Renesas Electronics Singapore Pte Ltd 1 harbourFront Avenue 06 10 keppel Bay Tower Singapore 098632 Tel 65 6213 0200 Fax 65 6278 8001 Renesas Electronics Malaysia Sdn Bhd Unit 906 Block B Menara Amcorp Amcorp Trade Centre No 18 Jin Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel 60 3 7955 9390 Fax 60 3 7955 9510 Renesas Electronics Korea Co Ltd 11F Samik Lavied or Bldg 720 2 Yeoksam Dong Kangnam Ku Seoul 135 080 Korea Tel 82 2 558 3737 Fax 82 2 558 5141 2010 Renesas Electronics Corporation All rights reserved Colophon 1 0 RX62N RX621 Group 2rCENESAS Renes
259. nge RX62N Group RX621 Group 5 Synopsis Prototype Description R_INTC_ControlExtinterrupt External interrupt control bool R_INTC_ConitrolExitinterrupt II Pin selection uint8_t data1 uint16 tdata2 Control data1 Choose the interrupt pin to be controlled 4 Library Reference Modifies the specified external interrupt PDL_INTC_IRQn n 0 to 15 or PDL_INTC_NMI IRQn interrupt pin or NMI interrupt pin data2 Select the controls If multiple selections are required use to separate each selection Return value Category Reference Remarks Enable or disable the interrupt pin for the IRQ pins PDL_INTC_ENABLE or PDL_INTC_DISABLE Enable or disable the IRQn interrupt pin Detection sense selection for the RQ pins PDL_INTC_LOW or Low level detection PDL_INTC_FALLING or Falling edge detection PDL_INTC_RISING or Rising edge detection PDL_INTC_BOTH Falling and rising edge detection Interrupt request clearing PDL_INTC_CLEAR_IR_FLAG Clear the Interrupt Request flag This is not required if e Acallback function has been specified e The interrupt priority level is higher than 0 e The processor interrupt priority level is lower than the interrupt priority level This operation should not be applied when low level detection is used
260. nit 0 or 1 to be read data2 Specify a pointer to a variable or array where the results shall be stored True if a valid unit is selected otherwise false ADC R_ADC_10_Create R ADC_10_Control e Between 1 and 4 conversion results will be read and stored The number depends on the settings for Input channel selection and Scan mode when R_LADC_10_Create is used to configure the ADC unit e The 10 bit data alignment is controlled using the R ADC_10_Create function e Ensure that the buffer is big enough for the requested number of values e If no callback function is used this function waits for the ADI flag to indicate that conversion is complete before reading the results If the ADC unit s control registers are directly modified by the user this function may lock up RPDL definitions include r_pdl_adc_10 h RPDL device specific definitions include r_pdl_definitions h void func void uint1l6_t ADCresult 2 Read the ADC values for unit 2 R_ADC_10_Read 2 ADCresult 3 R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 196 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group dieing Resrenes 4 2 26 10 bit Digital to Analog Converter 1 R_DAC_10 Create Synopsis Configure the 10 bit DAC module Prototype bool R_DAC_10_Create uint8_t data1 Configuration
261. not 4 data2 Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold Operation mode PDL_SCI_ASYNC or Choose between Asynchronous PDL_SCI_SYNC or Clock synchronous PDL_SCI_SMART or Smart Card Interface or PDL_SCI_ASYNC_MP Multi Processor Asynchronous operation e Data transfer format PDL_SCI_LSB_FIRST or Select least or most significant bit first PDL_SCI_MSB_FIRST In 7 bit mode the format is fixed to LSB first Data inversion PDL_SCI_INVERSION_OFF or PDL_SCI_INVERSION_ON Control data inversion transmission and reception Transmit Receive connections PDL_SCI_TX_CONNECTED or PDL_SCI_TX DISCONNECTED or The TXDn output is required not required PDL_SCI_RX_CONNECTED or PDL_SCI_RX DISCONNECTED The RXDn input is required not required Options which are available in Asynchronous mode or Multi Processor Asynchronous mode Data clock source selection PDL_SCI_CLK_INT lO or Select the on chip The SCKn pin functions as an I O pin PDL_SCI_CLK_INT_OUT or baud rate generator The SCKn pin outputs the bit clock PDL_SCI_CLK_EXT_DIV_8 or Input a clock of 8 or 16 times the desired bit rate to the PDL_SCI_CLK_EXT_DIV_16 or SCKn pin For SCI5 select Timer output TMO0 SCKS is set to high impedance PDL SGI CLKIMR For SCI6 select Timer output TMO2 SCK6
262. ns include r_pdl_definitions h void func void uint8_t ipl Read the IPL bits R_INTC_Read PDL_INTC_REG_IPL amp ipl R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 23 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 8 R_INTC Write Synopsis Prototype Description Return value Category Reference Remarks Program example Update an interrupt register bool R_INTC_Write uint16 tdata1 Register selection uint8_t data2 II Register value Write the new value to an interrupt register data1 e The register to be updated PDL_INTC_REG_IPL or Select the current CPU interrupt priority level or PDL_INTC_REG_IR_ register or Interrupt Request register or PDL_INTC_REG_IER_ register or Interrupt Request Enable register or PDL_INTC_REG_IPR_ register or Interrupt Priority register or PDL_INTC_REG_SWINTR Software interrupt activation register data2 The value to be written to the register True if the parameter is within range otherwise false Interrupt control R_INTC_Read R_INTC_Modify R_INTC_CreateSoftwarelnterrupt e This function uses an interrupt routine to modify the IPL bits If the user has disabled interrupts cleared the f bit in the
263. nted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document bu
264. odifying a PFC register R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 2 6 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 7 MCU Operation Driver The driver functions support access to the registers which select the mode of operation for the microcontroller These functions support 1 Controlling the on chip ROM and RAM 2 Reading the MCU status flags R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 2 7 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 8 Low Power Consumption Driver The driver functions support access to the registers which select the lower power modes of operation for the microcontroller These functions support 1 Configuring the state while in standby mode and the activity that can be used to resume operation Selecting one of the low power modes Writing data to the backup memory area Reading data from the backup memory area Determining the cause of the exit from the lowest power mode R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 2 8 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 9 Voltage Detection Circuit Driver R20UT0084EE0004 Rev 0 04 Aug
265. ol PDL_CMT_DMAC_DTC_TRIGGER_DISABLE or PDL_CMT_DMAC_TRIGGER_ENABLE or PDL CMT DTC TRIGGER ENABLE Disable or enable activation of the DMAC when a compare match occurs data3 The one shot time period in seconds func The function to be called when the one shot period ends If you specify PDL_NO_FUNC this function will wait for the timer to complete before returning You should always specify a function if PDL_CMT_CPU_OFF is selected to ensure that an interrupt will re start the CPU data4 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false Compare Match Timer None R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 133 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Remarks e Function R_CMT_Create is not required e Ifa callback function is specified this function will enable the relevant interrupt Please see the notes on callback function use in 6 e A callback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed The timing limits depend on the peripheral module clock PCLK e Function R_CGC_Set must be called
266. on R_BSC_Create is called once before using this function The endian mode of the CPU is selected by the MDE pin low little endian high big endian e Port Function Control registers PF5BUS are modified by this function e The cycle count parameters are not checked for validity Use the hardware manual to check these values The exact values in parameters data2 to data11 are to be set to respective bit field in SDRAM registers For the corresponding cycle count value please refer to hardware manual R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 57 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group EE E snes Program example RPDL definitions include r_pdl_bsc h RPDL device specific definitions include r_pdl_definitions h void func void Configure SDSRAM 8 bit width 10 bit address shift R_BSC_SDRAM_CreateArea PDL_BSC_SDRAM WIDTH_32 PDL_BSC_SDRAM_8_BIT_SHIFT OxOFFFu 0x00u 0x00u 0x02u 0x00u 0x02u 0x0lu 0x00u 0x00u 0x00u 0x0220u R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae AS Page 4 58 KENES Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group A ibrar Reteenes 4 R_BSC_Destroy Synopsis Stop the External Bus Controller Prototype boo
267. on to complete do R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 5 43 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 sage Examples R_IIC_GetStatus 0 amp status_flags PDL_NO_PTR PDL_NO_PTR while status_flags amp 0x00000080ul 0x0u Issue a Stop condition on channel 1 R_IIC_Control 0 PDL_IIC_STOP bus_busy false void iic_rx_dmac_end_handler void uint32_t DestAddr 0 Read the next destination address for the current transfer R_DMAC_GetStatus 2 PDL_NO_PTR PDL_NO_PTR amp DestAddr PDL_NO_PTR Read one more byte with NACK condition on channel 1 and stop R_IIC_MasterReceiveLast 0 uint8_t DestAddr bus_busy false Figure 5 26 An example of write data to and reading data from an EEPROM using two DMAC channels R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 5 44 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Weagekxamplez 5 10 3 Master mode with DTC In the following example data is written to an EEPROM in two bursts The DTC is used to handle the data transfer The same EEPROM address locations are then read out in two bursts The DTC is used to handle the data transfer Peripheral driver function prototy
268. onger required and enabling low power mode 3 Control of special modes such as loopback 4 Configuration of command sequence settings 5 Managing the transfer of data on the interface including e Automatic interrupt control e Automatic DMAC DTC control 6 Reading the status of a module Note The Clock Generation Circuit must be configured before configuring any SPI channel R20UT0084EE0004 Rev 0 04 Aug 25 2010 Senger RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 26 12 bit Analog to Digital Converter Driver R20UT0084EE0004 Rev 0 04 Aug 25 2010 Sane RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 27 10 bit Analog to Digital Converter Driver The driver functions support the use of the four ADC units providing the following operations 1 4 Configuration for use including e Automatic clock setting using sampling time as an input e Automatic interrupt control e Automatic I O pin configuration Disabling units that are no longer required and enabling low power mode Control of one or more units including e CPU sleep option Reading the conversion results of one or more units with support for polling or interrupts Note The Clock Generation Circuit must be configured
269. onics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this manual refer to the relevant sections of the manual If the descriptions under General Precautions in the Handling of MPU MCU Products and in the body of the manual differ from each other the description in the body of the manual takes precedence 1 Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states o
270. or MTIOC n 1 F in the TGRB input capture conditions for channel n 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Description 6 8 data7 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 88 4 Library Reference Configure the operation for general registers TGRC and TGRD Valid for n 0 3 4 6 9 and 10 If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Input capture output compare control for register TGRC PDL_MTU_C_OC_ DISABLED or PDL_MTU_C_OC LOWor PDL_MTU_C_OC_LOW_CM HIGH or PDL_MTU_C_OC_LOW_CM_INV or PDL_MTU_C_OC_HIGH_CM_LOW or PDL_MTU_C_OC HIGH or PDL_MTU_C_OC_HIGH_CM_INV or MTIOCnC output disabled MTIOCnC output low MTIOCnC initial output low goes high at compare match MTIOCnC initial output low toggles at compare match MTIOCnC initial output high goes low at compare match MTIOCnC output high MTIOCnC initial output high toggles at compare match PDL_MTU_C_IC_RISING_EDGE or PDL_MTU_C_IC_FALLING EDGE or PDL_MTU_C_IC_BOTH EDGES or Input capture at MTIOCnC rising edge Input capture at MTIOCnC falling edge Input capture at MTIOCnC both edges PDL_MTU_C_IC_COUNT Input capture at channel n 1 up count or down
271. or 10 The register TGRC value For n 5 or 11 The register TGRU value This will be ignored if the register is not selected data8 For n 0 3 4 6 9 or 10 The register TGRD value For n 5 or 11 The register TGRV value This will be ignored if the register is not selected data9 For n 0 or 6 The register TGRE value For n 5 or 11 The register TGRW value This will be ignored if the register is not selected data10 For n 0 or 6 The general register TGRF value This will be ignored if the register is not selected Return value True if the channel number is valid otherwise false Category Multi function Timer Pulse Unit Reference Remarks e None R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 94 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Apiary E enes Program example RPDL definitions include r_pdl_mtu h RPDL device specific definitions include r_pdl_definitions h void func void Allocate a copy of the structure for the selected channel R_MTU_ControlChannel_structure ch3_parameters Set the control options for channel 3 ch3_parameters data2 PDL_MTU_START ch3_parameters data3 PDL_MTU_REGISTER_COUNTER PDL_MTU_REGISTER_TGRB ch3_parameters data4 OxFFDD ch3_parameters data6 0x0020
272. or n 1 MTIOC9D PDL_MTU_OUT_P_PHASE_2_ ENABLE or For n 0 MTIOC4A PDL_MTU_OUT_P_PHASE_2_DISABLE For n 1 MTIOC10A PDL_MTU_OUT_N_PHASE_2_ENABLE or For n 0 MTIOC4C PDL_MTU_OUT_N_ PHASE _2_ DISABLE For n 1 MTIOC10C PDL_MTU_OUT_P_PHASE_3_ENABLE or For n 0 MTIOC4B PDL_MTU_OUT_P_PHASE_3_ DISABLE For n 1 MTIOC10B PDL_MTU_OUT_N_PHASE_3_ENABLE or For n 0 MTIOC4D PDL_MTU_OUT_N_PHASE_3_ DISABLE For n 1 MTIOC10D Or all six phase outputs can be controlled together by selecting one of each PDL_MTU_OUT_P_PHASE_ALL_ENABLE or All P phase outputs PDL_MTU_OUT_P_PHASE_ALL_ DISABLE i PDL_MTU_OUT_N_PHASE_ALL_ENABLE or All N phase outputs PDL_MTU_OUT_N_PHASE_ALL_DISABLE Output inversion control Each phase output can be configured for a initial high level active low level or b initial low level active high level All six phase outputs can be controlled together by selecting one of each PDL_MTU_OUT_P_PHASE_ALL_HIGH_LOW or PDL_MTU_OUT_P_PHASE_ALL_LOW_HIGH PDL_MTU_OUT_N_PHASE_ALL_HIGH_LOW or PDL_MTU_OUT_N_PHASE_ALL_LOW_HIGH Positive phase outputs Negative phase outputs R20UT0084EE0004 Rev 0 04 Aug 25 2010 Segue RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Description 2 4 4 Library Reference Or independently by selecting one option for each required output
273. p 5 WeageExemplez 5 10 4 Slave mode In this example the MCU behaves as a slave device on channel 0 It will respond to 7 bit address 0001001b or 10 bit address 0010010010b Peripheral driver function prototypes include r_pdl_iic h include r_pdl_cgc h include r_pdl_intc h include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h void slave_event_handler void const uint8_t mcu_data_array 10 0x00 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 Ox5A volatile bool all_data_read volatile bool all_data_sent volatile uint8_t slave_data_storage 10 void main void Initialise the system clocks R_CGC_Set 12 0E6 96E6 48E6 PDL_NO_DATA PDL_CGC_BCLK_DISABL Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 i Select I C mode at 100kHz 300ns rise time 200ns fall time R_IIC_Create 0 PDL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 PDL_IIC_SLAVE_O_ENABLE_7 PDL_IIC_SLAVE_1 0x12 0x0124 PDL_NO_DATA 100E3 300 lt lt 16 200 all_data_read false Monitor the channel Any data received will be stored in the receive buffer R_IIC_SlaveMonitor 0 PDL_NO_DATA slave_data_storage 10 slave_event_handler 7 while all_data_read false void slave_event_handler voi
274. pecific definitions include r_pdl_definitions h void func void uint8_t irq_status Read the IR flag and pin state for IRQ5 R_INTC_GetExtInterruptStatus PDL_INTC_IRQ5 amp irg_status R20UT0084EE0004 Rev 0 04 Aug 25 2010 Sayer RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Librai Reierenc 7 R_INTC_Read Synopsis Read an interrupt register Prototype bool R_INTC_Read uint1i6_t data1 Register selection uint8_t data2 Data storage location 3 Description Read an interrupt register and store the value data1 e The register to be read PDL_INTC_REG_IPL or Select the current CPU interrupt priority level or PDL_INTC_REG_IR_ register or Interrupt Request register or PDL_INTC_REG_IER_ register or Interrupt Request Enable register or PDL_INTC_REG_IPR_ register Interrupt Priority register data2 The location where the register s value shall be stored Return value True if all parameters are valid and exclusive otherwise false Category Interrupt control Reference R_INTC_Write R_INTC_Modify Remarks e For register select one of the registers listed in tables in section 4 2 2 Program example RPDL definitions include r_pdl_intc h RPDL device specific definitio
275. pecified port or pin must be switched on see R_IO_PORT_Set Program example RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Wait until pin P05 reads as 0 R_IO_PORT_Wait PDL_IO_PORT_0_5 0 i Wait until port 6 reads as 0x55 R_IO PORT Wait PDL_IO_PORT_6 0x55 i R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 36 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 abranyiReter nee 4 2 4 Port Function Control Each I O Port function can operate on a complete port or on individual port pins The definitions available to functions are listed below PFC register definitions PDL_PFC_PFOCSE PDL_PFC_PF1CSS PDL_PFC_PF2CSS PDL_PFC_PF3BUS PDL_PFC_PF4BUS PDL_PFC_PF5BUS PDL_PFC_PF6BUS PDL_PFC_PF7DMA PDL_PFC_PF8IRQ PDL_PFC_PF9IRQ PDL_PFC_PFAADC PDL_PFC_PFBTMR PDL_PFC_PFCMTU PDL_PFC_PFDMTU PDL_PFC_PFENET PDL_PFC_PFFSCI PDL_PFC_PFGSPI PDL_PFC_PFHSPI PDL_PFC_PFJCAN PDL_PFC_PFKUSB PDL_PFC_PFLUSB PDL_PFC_PFMPOE PDL_PFC_PFNPOE R20UT0084EE0004 Rev 0 04 Aug 25 2010 Sage RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group R
276. pes include r_pdl_iic h include r_pdl_cgc h include r_pdl_cmt h include r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h static void write_eeprom_data void static void read_eeprom_data void void iic_tx_dmac_end_handler void void iic_rx_dmac_end_handler void define EEPROM MEMORY _ADDRESS_UPPER 0x00 define EEPROM MEMORY ADDRESS LOWER 0x00 define EEPROM_ADDRESS 0x00A0 EEPROM MEMORY _ADDRESS_UPPER volatile uint8_t bus_busy volatile uint8_t data_storage 20 Reserve an area for the DTC vector table pragma address dtc_vector_table 0x00001000 uint32_t dtc_vector_table 256 Reserve 16 bytes full address mode for the transfer data areas uint32_t dtc_iicl_tx_transfer_data 4 uint32_t dtc_iicl_rx_transfer_data 4 void main void const uint8_t eeprom_data_array_1 EEPROM _MEMORY_ADDRESS_LOWER 0x01 0x02 0x03 0x04 0x05 const uint8_t eeprom_data_array_2 EEPROM_MEMORY_ADDRESS_LOWER 5 0x06 0x07 0x08 0x09 0x0A Ox0B Ox0C Ox0D 0x0E Ox0F uint8_t i Configure the clocks R_CGC_Set 12 0E6 96E6 48E6 PDL _NO_DATA PDL_CGC_BCLK_DISABLE Configure the DTC controller R_DTC_Set PDL_DTC_ADDRESS_FULL dtc_vector_table Set up a DTC channel for IIC transmissio
277. pt processing function This means that no other interrupt can be processed until a callback function has completed In Multi processor mode R_SCI_Receive is to be called in pair the first one is to receive ID ID cycle the second one is to receive data Data cycle For ID reception it could be done by reception interrupt by specifying func7 or by internal polling operation without specifying func1 For Data reception it will be the same as normal Asynchronous mode For usage example of Multi processor mode please refer to Section 5 8 e For ID cycle the DMAC DTC trigger control will be ignored Program example PDL functions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h volatile uint8_t gSCI1lReceiveBuffer 10 SCI channel 1 receive data handler void SCI1RxFunc void SCI channel 1 error handler void SCI1ErrFunc void void func void uint8_t temp Put a Null character at the end of the string gSCI1lReceiveBuffer 10 NULL Wait for 1 character to be received on channel 0 R_SCI_Receive 0 PDL_NO_DATA amp temp 1 PDL_NO_FUNC PDL_NO_FUNC Start the reception of 9 characters on channel 1 R_SCI_Receive 1 PDL_NO_DATA gSCilReceiveBuffer 9 SCI1RxFunc SCI1ErrFunc R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 152 Under development Prel
278. ption Program example RPDL definitions include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown channels 0 and 1 R_CMT_Destroy 0 R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae Page 4 135 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group dieing Resrenes 4 R_CMT Control Synopsis Control CMT operation Prototype bool R_CMT_Control uint8_t data1 Channel selection uint16_tdata2 Configuration selection float data3 II Period frequency or register data Description Modify the operation of a CMT channel data1 The channel number n where n 0 1 2 or 3 data2 Configure the timer channel To set multiple options at the same time use to separate each value e Counter stop re start PDL_CMT_STOP Disable the counter clock source PDL_CMT_START Enable the counter clock source Value change request PDL_CMT_PERIOD or The parameter data3 will contain the new period PDL_CMT_FREQUENCY or frequency PDL_CMT_CONSTANT or constant register CMCOR or PDL_CMT_COUNTER counter register CMCNT value data3 The new period frequency or register value This will be ignored if a timing change is not requested Data use Parameter
279. quence CSPRWAIT Valid between 0 and 7 data6 The number of wait cycles used for second and subsequent accesses during a page write sequence CSPWWAIT Valid between 0 and 7 data7 The number of wait cycles for the first access during a normal or page read sequence CSRWAIT Valid between 0 and 31 data8 The number of wait cycles for the first access during a normal or page write sequence CSWWAIT Valid between 0 and 31 data9 The number of cycles that the CS signal is left asserted after the read strobe is negated CSROFF Valid between 0 and 7 data10 The number of cycles that the CS signal is left asserted after the write strobe is negated CSWOFF Valid between 0 and 7 data11 The number of cycles that the data output is left asserted after the write strobe is negated WDOFF Valid between 1 and 7 data12 The number of cycles before the read strobe is asserted RDON Valid between 0 and 7 data13 The number of cycles before the write strobe is asserted WRON Valid between 0 and 7 data14 The number of cycles before the write data is output WDON Valid between 1 and 7 data15 The number of cycles before the chip select is asserted CSON Valid between 0 and 7 True if all parameters are valid and exclusive otherwise false Bus Controller R_BSC_Create R_BSC_Destroy e Ensure that function R_BSC_Create is called once before using this function The endian mode of the CPU is selecte
280. r B pins for MTIC5U MTIC5V and MTIC5W PDL_MTU_PIN CLKABCD B and MTCLKD PDL_MTU_PIN_CLKABCD_Aor Select the A or B pins for MTCLKA MTCLKB MTCLKD PDL_MTU_PIN_11UVW_B MTIC11W PDL_MTU_PIN_11UVW_Aor Select the A or B pins for MTIC11U MTIC11V and PDL_MTU_PIN_CLKEFGH_B and MTCLKH PDL_MTU_PIN_CLKEFGH_Aor Select the A or B pins for MTCLKE MTCLKF MTCLKG True if all parameters are valid and exclusive otherwise false Multi function Timer Pulse Unit R_MTU_Create e Before calling R MTU_Create call this function once include r_pdl_mtu h void func void Configure the MTU pins R_MTU_Set PDL_MTU_PIN_3C_A PDL MTU PIN 3BD_A PDL_MTU_PIN_4AC_B PDL_MTU_PIN_4BD_A PDL R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 82 N PDL_MTU_PIN_5UVW_B PDL_MTU_PIN_CLKABCD_B MTU_PIN_11UVW_A PDL_MTU_PIN_CLKEFGH_A Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 R_MTU Create Synopsis Configure an MTU channel Prototype bool R_MTU_Create uint8_t data1 R_MTU_Create_structure ptr Channel selection R_MTU_Create_structure members II Configuration selection Configuration selection II Configuration selection II Configuration selection II Configuration selection II Configuration selection II Configuration selec
281. r clock source and compare match value will be calculated by this function The parameter data3 will specify the timer frequency PDL_CMT_FREQUENCY or The counter clock source and compare match value will be calculated by this function PDL_CMT_PCLK_DIV_8 or PDL_CMT_PCLK_DIV_32 or PDL_CMT_PCLK_DIV_128 or PDL_CMT_PCLK_DIV_512 Select the internal clock signal PCLK 8 32 128 or 512 as the counter clock source The parameter data3 will be the register CMCOR value DMAC DTC trigger control PDL_CMT_DMAC_DTC_TRIGGER_DISABLE or PDL_CMT_DMAC_TRIGGER_ENABLE or PDL_CMT_DTC_ TRIGGER _ENABLE Disable or enable activation of the DMAC or DTC when a compare match occurs data3 The data to be used for the register value calculations Data use Parameter type The timer period in seconds or float The timer frequency in Hz or float The value to be put in register CMCOR uint16_t func The function to be called at the periodic interval Specify PDL_NO_FUNC if not required data4 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func Return value Category Reference True if all parameters are valid and exclusive otherwise false Compare Match Timer R_CMT_Destroy R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 131 Under development P
282. r n 0 1 2 6 7 and 8 PDL_MTU_MODE_PHASE 1 or PDL_MTU_MODE_PHASE2 or PDL_MTU_MODE_PHASE3 or PDL_MTU_MODE_PHASE4 or Phase counting mode 1 2 3 or 4 Valid for n 1 2 7 and 8 PDL_MTU_MODE_PWM_RS or Reset synchronised PWM mode Valid for n 3 or 9 PDL_MTU_MODE_PWM_COMP1 or PDL_MTU_MODE_PWM_COMP2 or PDL_MTU_MODE_PWM_COMP3 Complementary PWM mode 1 2 or 3 Valid for n 3 or 9 e Synchronous mode Valid for n 0 to 4 or 6 to 10 PDL_MTU_SYNC_DISABLE or PDL_MTU_SYNC ENABLE Disable or enable synchronous presetting clearing R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 83 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Description 2 8 4 Library Reference DMAC DTC event trigger control Valid for n 0 to 4 or 6 to 10 unless stated otherwise R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 84 PDL_MTU_TGRA_DMAC_DTC_TRIGGER_DISABLE or PDL_MTU_TGRA_DMAC_TRIGGER_ENABLE or PDL_MTU_TGRA DTC _TRIGGER_ENABLE TGRA compare match or input capture PDL_MTU_TGRB_DTC_ TRIGGER DISABLE or PDL_MTU_TGRB_ DTC TRIGGER ENABLE TGRB compare match or input capture PDL_MTU_TGRC_DTC_TRIGGER_DISABLE or PDL_MTU_TGRC_DTC_ TRIGGER ENABLE TGRC compare match or input capture Valid for n 0 3 4 6 9 and 10 PDL_MTU_TGRD_DTC_TRIGG
283. ral_D L6_t L6_t void func void Allocate a copy of the structure for the selected channel R_MTU_ReadChannel_structure ch3_parameters Load the defaults R_MTU_ReadChannel_load_defaults amp ch3_parameters Set the non default options for channel 3 ch3_parameters data2 amp Flags ch3_parameters data4 amp General_A ch3_parameters data7 amp General_D Read the status flags and registers of channel 3 R_MTU_ReadChannel 3 amp ch3_parameters R20UT0084EE0004 Rev 0 04 Aug 25 2010 a 2 Page 4 102 a ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group A ibrar Reteenes 7 R_MTU_ReadUnit Synopsis Read from MTU registers Prototype bool R_MTU_Readunit uint8_t data1 Unit selection uint16_t data2 A pointer to the data storage location uint16_t data3 A pointer to the data storage location Description Read any of the timer units s counter registers data1 The unit number n where n 0 to 1 data2 A pointer to where the Timer Subcounter register TCNTS value shall be stored Specify PDL_NO_PTR iff it is not required data3 Where the Timer Interrupt Skipping Counter register TITCNT value shall be stored Specify PDL_NO_PTR if it is not required Return value True if all parameters are valid an
284. rameters datal2 50 ch4_parameters datal3 100 ch4_parameters datal4 0 ch4_parameters datal5 0 R_MTU_Create 4 amp ch4_ parameters R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 91 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Grou P P 4 Library Reference 3 R_MTU_Destroy Synopsis Disable a Multi function Timer Pulse Unit Prototype bool R_MTU_Destroy uint8_t data Unit selection Description Shut down a timer pulse unit data The muti function timer pulse unit n where n 0 or 1 Unit 0 comprises channels MTUO to MTUS5 Unit 1 comprises channels MTU6 to MTU11 Return value True if the unit selection is valid otherwise false Category Multi function Timer Pulse Unit Reference Remarks e The unit is put into the stop state to reduce power consumption Program example include r_pdl_mtu h void func void Shutdown MTU channels 0 to 5 R_MTU_Destroy 0 di R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 92 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 R_MTU_ConitrolChannel Synopsis Prototype uint8_t data1 R_MTU_ControlChannel_structure ptr 3 R_MTU_ControlChannel_str
285. rary Reference Synopsis Configure and use a one shot timer Prototype bool R_TMR_CreateOneShot uint8_t data1 8 bit channel or 16 bit unit timer selection uint32_t data2 Configuration selection float data3 Period void func Callback function uint8_t data4 II Interrupt priority level Description Set up a TMR timer channel or unit for one shot operation and start the timer PDL_TMR_TMRO or PDL_TMR_TMR1 or PDL_TMR_TMR2 or PDL_TMR_TMR3 or PDL_TMR_UNITO or PDL_TMR_UNIT1 The channel n n 0 1 2 or 3 or unit n n 0 or 1 to be configured data2 Configure the timer Use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Output pin control PDL_TMR_OUTPUT_HIGH or PDL_TMR_OUTPUT_LOW or PDL_TMR_OUTPUT_OFF For the duration of the one shot period generate a high level output low level output or no output on pin TMOn For 16 bit operation the pin shall be TMO2 when n 1 e DTC trigger control PDL_TMR_PULSE_DTC_TRIGGER_DISABLE or Disable or enable activation of the DTC PDL_TMR_PULSE_DTC_TRIGGER_ENABLE when the one shot period ends Control the CPU during the one shot operation PDL_TMR_CPU_ONor Allow the CPU to run normally while the one shot operates PDL_TMR_CPU_OFF Stop the CPU when the one shot timer starts The CPU will re start when any valid interrupt occurs
286. receive data start address void data10 Command 4 transmit data start address void data11 Command 4 receive data start address void data12 Command 5 transmit data start address void data13 Command 5 receive data start address void data14 Command 6 transmit data start address void data15 Command 6 receive data start address void data16 Command 7 transmit data start address void data17 Command 7 receive data start address uint16_t data18 Sequence loop count void func Callback function uint8_t data19 Interrupt priority level Description In Master mode transfer the data to and or from the Slave device In Slave mode monitor the bus and transfer the data under control of the Master device data1 Select channel SPIn where n 0 to 1 data2 data4 data6 data8 data10 data12 data14 data16 The start address of the data to be sent Specify PDL_NO_PTR if no data is to be sent data3 data5 data7 data9 data11 data13 data15 data17 The start address of the data to be received Specify PDL_NO_PTR if no data is to be received data18 The number of times that the command sequence will be executed func The function to be called when all data has been transferred or an error occurs Specify PDL_NO_FUNC for this function to wait until either event occurs data19 The interrupt priority level Select between 1 lowest priority and 15 highest priority
287. register is specified otherwise false Functionality MCU registers References R_MCU_GetStatus Remarks e None Program example RPDL definitions include r_pdl_mcu h RPDL device specific definitions include r_pdl_definitions h void func void Modify the MCU operation R_MCU_Control PDL_MCU_ROM_DISABLE R20UT0084EE0004 Rev 0 04 Aug 25 2010 imed RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 2 R_MCU_GetStatus Synopsis Prototype Description Return value Functionality References Remarks Program example R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 42 Read the MCU status bool R_MCU_GetStatus uint16_t data Pointer to the variable where the status value shall be stored Read the status registers for the MCU data The status flags shall be stored in the format below b15 b14 b13 b12 b11 b10 b9 b8 Start up states USB boot Boot mode External bus On chip ROM 0 0 Other mode 0 0 Other mode 00 16 bit 0 Disabled 0 Disabled 1 USB Boot mode 1 Boot mode 10 8 bit 1 Enabled 1 Enabled b7 b6 b2 b1 bO Endian Pin states 0 Little 0 1 Big MD1 MDO True MC
288. reliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Remarks Program example 1 E i 4 Library Reference The compiler adds a null character to the end of string constants If a callback function is specified transmission interrupts are used Please see the notes on callback function usage in 6 If a callback function is specified avoid enabling activation of the DMAC or DTC for data transmission If no callback function func is specified this function will operate in polling mode The TXI and TEND flags will be used to manage the data transmission If the SCI channel s control registers are directly modified by the user this function may lock up The maximum number of characters to be transmitted is 65535 A callback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed If reception is enabled and receive errors occur transmission will be blocked until the errors are cleared In Multi processor mode R_SCI_Send is to be called in pair the first one is to send ID ID cycle the second one is to send data Data cycle For ID transmission it will be sent by internal polling operation For Data transmission it will be the same as normal Asynchronous mode For usage example of Multi processor mode please refer to Section 5
289. reliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Remarks Program example R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 132 4 Library Reference Function R_CGC_Set must be called before any use of this function If a callback function is specified this function will enable the relevant interrupt Please see the notes on callback function use in 6 A callback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed The timing limits depend on the frequency of the peripheral module clock PCLK feck MHz Equation 50 48 12 5 12 32 8 8 Periodmin 160ns 166 67ns 640ns 666 67ns 250ns 1 0us frctk 2 Periodmax 671ms 699ms 2 68s 2 79s 1 05s 4 19s frcr focux 6 25 1 56 fmax 3 MHz 6 MHz MHz 1 5 MHz 4 0 MHz 1 0 MHz fmin dei 1 49 Hz 1 43 Hz 0 37 Hz 0 357 Hz 0 95 Hz 0 24 Hz If the requested period is not a multiple of the minimum period the actual time period will be more than the requested time period RPDL definitions include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h void func void Configure C R_CMT_Create 0 PD _CMT_PERIO 10E 6 PDI 0 i L_NO_FUNC D T channel
290. riod will be more than the requested time period The actual duty cycle will be less than the requested duty cycle if the resulting pulse width is not a multiple of the timer resolution A callback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 118 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group dban Rewrsnes Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Configure pin TMO1 for 500ns period 200ns pulse width R_TMR_CreatePeriodic PDL_TMR_TMR1 PDL_TMR_PERIOD PDL_TMR_OUTPUT_HIGH 500E 9 200E 9 PDL_NO_FUNC PDL_NO_FUNC 0 eo Me S i Configure pin TMO1 for 5MHz frequency 60 duty cycle R_TMR_CreatePeriodic PDL_TMR_TMR1 PDL_TMR FREQUENCY PDL_TMR_OUTPUT_HIGH 5E6 60 PDL_NO_FUNC PDL_NO_FUNC 0 R20UT0084EE0004 Rev 0 04 Aug 25 2010 AS Page 4 119 KENES Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 R_TMR_CreateOneShot data1 4 Lib
291. rol PDL_TMR_OUTPUT_HIGH or Start with a high level or PDL_TMR_OUTPUT_LOW or low level output or PDL_TMR_OUTPUT_OFF no output on pin TMOn For 16 bit operation the pin shall be TMO2 when n 1 e ADC trigger control PDL_TMR_ADC_TRIGGER_OFF or requests TMR unit Disable or enable TMR triggered ADC conversion start PDL_TMR_ADC_TRIGGER_ON Applicable only for channels TMRO or TMR2 or either e Pulse DTC trigger control PDL_TMR_PULSE_DTC_TRIGGER_DISABLE or PDL_TMR_PULSE_DTC_TRIGGER_ENABLE Disable or enable activation of the DTC at the pulse width interval e Period DTC trigger control PDL_TMR_PERIOD DTC_TRIGGER_DISABLE or PDL_TMR_ PERIOD DTC _TRIGGER_ENABLE Disable or enable activation of the DTC at the periodic interval data3 The period in seconds or frequency in Hz data4 The pulse width in seconds or duty cycle funct The function to be called at the pulse width interval Use PDL_NO_FUNC if not required func2 The function to be called at the periodic interval Use PDL_NO_FUNC if not required R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 117 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Description 2 2 4 Library Reference data5 The interrupt priority level Select between 1 lowest priority and 15
292. rsion Figure 5 30 shows an example of ADC usage ADC unit 0 is polled until the conversion is complete Interrupts are enabled for ADC unit 1 which operates in the one cycle scan mode Peripheral driver function prototypes include r_pdl_adc_10 h include r_pdl_cgc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h volatile uint8_t adcl result volatile uint8_t adcl_result 4 void ADC3Handler void void main void Initialise the system clocks R_CGC_Set 12E6 96E6 48E6 0 PDL_CGC_BCLK_DISABLE Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Configure ADC unit 0 for single scan on pin AN1 polled R_ADC_10_Create 0 PDL_ADC_10_MODE_SINGLE PDL_ADC_10_CHANNELS_OPTION_2 48E6 0 5E 6 PDL_NO_FUNC 0 Configure ADC unit 1 for one cycle scan on pins AN4 to AN7 interrupts R_ADC_10_Create 1 PDL_ADC_10_MOD E SCAN PDL_ADC_10_CHANNELS_OPTION_4 48E6 0 5E 6 ADClHandler 6 Start conversions on ADC units 0 and 1 R_ADC_10_Control PDL_ADC_10_0_ON PDL_ADC_10_1 ON Read the level on AN1 R_ADC_10_Read 0 amp adc0_result R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 5 56 RENESAS Under development Preliminary Specification Specifications in this prelimi
293. rsion completed PDL_INTC_VECTOR TGIAO PDL_INTC_VECTOR TGIBO PDL_INTC_VECTOR_ TGICO PDL_INTC_VECTOR TGIDO PDL_INTC_VECTOR_TCIVO PDL_INTC_VECTOR TGIEO PDL_INTC_VECTOR_TGIFO Multi function Timer Pulse Unit channel 0 Compare match or Input capture A Compare match or Input capture B Compare match or Input capture C Compare match or Input capture D Overflow Compare match E Compare match F PDL_INTC_VECTOR TGIA1 PDL_INTC_VECTOR_TGIB1 PDL_INTC_VECTOR_TCIV1 PDL_INTC_VECTOR_TCIU1 Multi function Timer Pulse Unit channel 1 Compare match or Input capture A Compare match or Input capture B Overflow Underflow PDL_INTC_VECTOR TGIA2 PDL_INTC_VECTOR TGIB2 PDL_INTC_VECTOR_TCIV2 PDL_INTC_VECTOR TCIU2 Multi function Timer Pulse Unit channel 2 Compare match or Input capture A Compare match or Input capture B Overflow Underflow PDL_INTC_VECTOR TGIA3 PDL_INTC_VECTOR TGIB3 PDL_INTC_ VECTOR TGIC3 PDL_INTC_VECTOR_TGID3 PDL_INTC_VECTOR_ TCIV3 Multi function Timer Pulse Unit channel 3 Compare match or Input capture A Compare match or Input capture B Compare match or Input capture C Compare match or Input capture D Overflow PDL_INTC_VECTOR TGIA4 PDL_INTC_VECTOR TGIB4 PDL_INTC_ VECTOR TGIC4 PDL_INTC_VECTOR TGID4 PDL_INTC_VECTOR
294. rue if all parameters are valid and exclusive otherwise false Data Transfer Controller R_DTC_Create This function must be called in order to start the DTC R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 78 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Dbia Reiben Program example RPDL definitions include r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h void func void Start the controller R_DTC_Control PDL_DTC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA R20UT0084EE0004 Rev 0 04 Aug 25 2010 z AS Page 4 79 KENES Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 5 R_DTC_GetStatus Synopsis Prototype Description Return value Category Reference Remarks Check the status of the Data Transfer Controller bool R_DTC_GetSiatus uint32_t data1 Transfer data start address uint16_t data2 Status flags pointer uint32_t data3 Current source address pointer uint32_t data4 Current destination address pointer uint16_t data5 Current transfer count pointer uint8_t data6 II Current block size
295. s These instructions are issued by the API interrupt handlers so there should be no need for the user s code to use these instructions 2 Use the wait intrinsic function with caution This instruction is used by some API functions as part of power management so there should be no need for the user s code to use this instruction More information on the processor modes can be found in 1 4 of the RX Family software manual 6 2 Interrupts and DSP instructions The accumulator ACC register is modified by the following instructions i DSP MACHI MACLO MULHI MULLO MVTACHI MVTACLO and RACW ii Multiply and multiply and accumulate EMUL EMULU FMUL MUL and RMPA The accumulator ACC register is not pushed onto the stack by the API interrupt handlers If DSP instructions are being utilised in the users code callback functions which are called by the API interrupt handlers should either a Avoid using instructions which modify the ACC register b Take a copy of the ACC register and restore it before exiting the callback function R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 6 1 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Revision History Revision History RX62N Group User s Manual 0 01 0 02 0 03 Date May 27 2010 Jun 22 2010 Jul 23 2010 Aug 25 2010 Page Description Summary Firs
296. s A23 A16 pin selection PDL_BSC_A23_A16_ Aor PDL_BSC_A23_A16_B Select pins A23 A to A16 A or A23 B to A16 B WAIT pin selection PDL_BSC_WAIT_Aor PDL_BSC_WAIT_B or PDL_BSC_WAIT_C or PDL_BSC_WAIT_D Select pin WAIT A WAIT B WAIT C or WAIT D d ata2 Address output control The signals are enabled by default Specify 0 for no change PDL_BSC_A9 AO DISABLE Disable the output of the A9 to AO signals PDL_BSC_AQ A4 DISABLE Disable the output of the A9 to A4 signals PDL_BSC_AQ A8 DISABLE Disable the output of the A9 to A8 signals PDL_BSC_A10_ DISABLE Disable the output of the A10 signal PDL_BSC_A11_DISABLE Disable the output of the A11 signal PDL_BSC_A12 DISABLE Disable the output of the A12 signal PDL_BSC_A13_ DISABLE Disable the output of the A13 signal R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 50 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference Description 2 2 PDL_BSC_A14 DISABLE Disable the output of the A14 signal PDL_BSC_A15 DISABLE Disable the output of the A15 signal PDL_BSC_A16_DISABLE Disable the output of the A16 signal PDL_BSC_A17 DISABLE Disable the output of the A17 signal PDL_BSC_A18_DISABLE Disable the output of the A18 signal
297. s Remarks e The selected interrupt pin is enabled automatically Port Function Control registers PF8IRQ or PF9IRQ are modified to select the IRQn pin The appropriate I O port ICR and DDR registers are modified Please see the notes on callback function use in 6 The NMI callback function should not return It should stop operation or reset the system If the NMI interrupt fails to initialise this function will return false Program example RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Declaration of callback function void CallBackFunc void void func void Configure the IRQO interrupt on pin IRQO A R_INTC_CreateExtInterrupt PDL_INTC_IRQO PDL_INTC_FALLING PDL_INTC_A CallBackFunc 7 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Saas RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group A ibrar Reteenes 2 R_INTC_CreateSoftwarelnterrupt Synopsis Enable use of the software interrupt Prototype bool R_INTC_CreateSoftwarelnierrupt uint8_t data1 Configuration void func Callback function uint8_t data2 Interrupt priority level Description Configure and enable the software interrupt data1 Choose the pin settings The default setting is shown in bold e DT
298. s function will issue a NACK to the master When a Stop condition is detected if the DMAC or DTC is used for transferring data use R_DMAC_Control or R_DTC_Control to re set the address and count before the next transfer begins False will be returned if the DMAC channel has not been allocated using R_DMAC_Create RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h volatile uint8_t data_array 5 void func void Monitor channel 0 using polling R_IIC_SlaveMonitor 0 PDL_NO_DATA data_array 5 PDL_NO_FUNC 0 R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 173 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group dieing Resrenes 7 R_IIC_SlaveSend Synopsis Write data to a master device Prototype bool R_IIC_SlaveSend uint8_t data1 Channel selection uint8_t data2 Data start address uinti6_t data3 Data count Description Transmit data on the specified channel data1 Select channel IICn where n 0 or 1 data2 The start address of the data to be sent data3 The number of bytes available to be sent Return value True if all parameters are valid exclusive and achievable otherwise false If this function is not called from the R_IIC_SlaveMonitor callback function it will co
299. s used with rising falling or both edges detected PDL_TMR_CLK_PCLK_DIV_1 or PDL_TMR_CLK_PCLK_DIV_2 or PDL_TMR_CLK_PCLK_DIV_8 or PDL_TMR_CLK_PCLK_DIV_32 or PDL_TMR_CLK_PCLK_DIV_64 or PDL_TMR_CLK_PCLK_DIV_1024 or PDL_TMR_CLK_PCLK_DIV_8192 The internal clock signal PCLK 1 2 8 32 64 1024 or 8192 e Counter clearing PDL_TMR_CLEAR_DISABLE or Clearing is disabled PDL_TMR_CLEAR_CM_Aor Cleared after a compare match A occurs PDL_TMR_CLEAR_CM_B or Cleared after a compare match B occurs PDL_TMR_CLEAR_RESET_RISING or Cleared by a rising edge on the external reset pin TMRIn PDL_TMR_CLEAR_RESET_HIGH Cleared when the external reset pin TMRIx x 0 or 2 for n 0 or 1 is high e ADC trigger control PDL_TMR_ADC_TRIGGER_DISABLE or PDL_TMR_ADC_TRIGGER ENABLE Disable or enable ADC conversion start requests on a compare match A signal Compare Match A DTC trigger control PDL_TMR_CM_A_DTC_TRIGGER_DISABLE or PDL_TMR_CM_A DTC TRIGGER ENABLE Disable or enable activation of the DTC when a Compare Match A occurs e Compare Match B DTC trigger control PDL_TMR_CM_B_DTC_TRIGGER_DISABLE or PDL_TMR_CM_B DTC TRIGGER ENABLE Disable or enable activation of the DTC when a Compare Match B occurs 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change
300. sas SPI Serial Communications Interface Synchronous Dynamic RAM System Management Bus Serial Peripheral Interface Universal Serial Bus Watchdog Timer 7tENESAS 1 Introduction Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 Driver 2 1 Overview This library provides a set of peripheral function control programs peripheral drivers for Renesas microcontrollers and allows the peripheral driver to be built into a user program 2 2 Control Functions summary This library has the following control functions available as peripheral drivers 1 Clock Generation Circuit These driver functions are used to configure the multiple internal clock signals 2 Interrupt These driver functions are used for configuring the external interrupt pins handling fixed interrupts and controlling the interrupt priority 3 I O Port These driver functions are used to configure the I O pins and provide data read write compare and modify operations 4 Port Function These driver functions are used for configuring the I O pin optional functions 5 MCU Operation These driver functions are used for configuring the MCU operation 6 Low Power Consumption These driver functions are used for selecting lower power consumption 7 Bus Controller These driver functions are used for configuring the external address bus data bus and
301. se enter a number to select the device package LFBGA 176 pins TFLGA 145 pins LQFP 144 pins LQFP 100 pins TFLGA 85 pins 1 2 3 4 5 i Please enter the path where you wish RPDL for RX62N to be installed ci my_project_folder The utility will create a folder in the location that you specified and copy the files into the new folder BEE Renesas RPDL for R amp X62N R8621 copy utility Please enter a number to select the device package LFBGA 176 pins TFLGA 145 pins LQFP 144 pins LQFP 100 pins TFLGA 85 pins o OLA GN Please enter the path where you wish RPDL for RX62N to be installed ci my_project_folder Creating the destination directory c my_project_folderNRPDL Copying the generic files Copying the files for the LFBGA176 package Finished Press any key to continue Press any key to close the window R20UT0084EE0004 Rev 0 04 Aug 25 2010 SEN Page 1 3 eal Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 1 Introduction 1 1 3 Include the new directory Use the key sequence Alt B R to open the RX Standard Toolchain window Select the C C tab Use the key sequence S to show the included file directories Click on the Add button In the Add include file directory window enter the details as shown Add include file directory Relative to Project
302. sed in parameter data1 For example define FAST_INTC_VECTOR PDL_INTC_VECTOR_ADIO This will direct the compiler to generate the instructions required for a fast interrupt vector e This function uses an interrupt routine to modify the FINTV register If the user has disabled interrupts cleared the I bit in the PSW register in their own code this function will lock up R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 17 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group A ibrar Reteenes Program example RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void Assign the fast interrupt to the handler for pin IRQ3 R_INTC_CreateFastInterrupt PDL_INTC_VECTOR_IRQ3 Remember to edit r_pdl_user_definitions h see remark 2 R20UT0084EE0004 Rev 0 04 Aug 25 2010 ztENESAS Page 4 18 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 4 R_INTC_CreateExceptionHandlers Synopsis Prototype Description Return value Category Reference Remarks Program example Assign handlers for the fixed vec
303. seeaaees 4 143 Serial Communication Interface ccccccceeeeeeeeececeeceeeeeeeseccanaeeeeeeesesecsaesaeeeeeeeeeseeseaeees 4 144 ROC Setare nee e a ae sii eb ees te oe eee ee eee 4 144 RSC Creates pnei oath alee eri wall aie Hite Sire eee 4 145 RSC Destroy ini henin ein ee eee eee oe es ee A 4 148 RSSGI SOR et ste tae tie seas a aad edeiaad thnk daa teat aren tet aguante ca sees llans 4 149 RS CIRECSIVG nea tis acute s ty ada eat aces vanticcce venta terval e e A cede sa a deh E dere wees 4 151 RSC Controlec tis eter ele rt ccs ete alta aah telat edi ad eta yaa aon Ja 4 153 RISC G6tStat S A vate crvacen a a dae teeta bead sae tee ra Meee and adt cece a cate a eaneee 4 155 CRG calctilatotecd a a a igi teect dan hii eaten iti 4 157 5 6 1 R CRC Create siiv c cand acto enle ini Reread eee Ee eee 4 157 2 R2CRC Destroy o oeaiei rii E AE E AEE AN EE E EAE EAA 4 158 3 RRC Witara ee a a a dean eae ee ti eae ee teen 4 159 A ReCRCU Read oden r aed ee a a E A A ie a 4 160 4 2 22 IFC Bus Interface nrnna a a a ee ee ee ee eee 4 161 1P RMG Create a a a ee ae eee es aided ee ees Meade tee eal ade eed 4 161 2 RAC Destoy viet eee ee ea ad A ee EOR A iA 4 166 3 R IC M sterSend imenska oats Meare nas ee ee eee ee es dope 4 167 4 RNC MasterRe ceive ticec cccscsneccteedslesrinee sda vageatenvandeeeavadslecies iaeia iea eadi aia aiia 4 169 5 RallG MasterReceive laste essiccc ct cchadisccielescceetani hele Ladictebaata
304. sive otherwise false Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 fabranyReterence Remarks e Multiple chip select signals can be output from one I O pin P24 TT o desec S P25 oo So So o essc Pze o So So Se Pez o So So To So fo esre Peo csoa J J T f J T Per pesiaj J I T J 1 Peze Jesz J J 1 pes Jesa J T Pea Jo Jo Jo o fessa ees o o To o So o o fessa peg I To J T J fesa eer o So So To fo fo SA e74 csi J T J 1 P72 Jes J J I e73 o S Jesas dt o d P74 oo So y y ezs o So So o fese y P76 o So So To f fese ezz o Tf S78 peaj d Jesse J J T pcs Jeszce 1 J T Pee Jesc J 1 1 J T Pezjesoa J I I Port Function Control registers PF1CSS to PF6BUS are modified by this function The external bus is enabled by this function Call this function before using function R_BSC_CreateArea A callback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed Program example RPDL definitions include r_pdl_bsc h RPDL device specific definitions include r_pdl_definitions h Bus error handler void BusErrorFunc void void func void Select CS2 B all address signals ena
305. ssor mode Set this option only when user wants to send ID in Multi processor mode For Data cycle in Multi processor mode do not set this option Specify that it is the ID cycle for PDL_SCI_MP_ID_CYCLE Multi processor mode The upper 8 bits will be used as ID e Target Station ID The valid range is from 0 to 255 Must be specified together with PDL_SCI_MP_ID_CYCLE Not required for Data cycle in Multi processor mode b15 b8 b7 b0 Station ID PDL_SCI_MP_ID_CYCLE data3 The start address of the data to be sent Specify PDL_NO_PTR for ID cycle in Multi processor mode data4 For sending binary data set this to the number of bytes to be sent The valid range is 1 65535 Set this to 0 for transmission of null terminated character string or for ID cycle in Multi processor mode func The function to be called when the last byte has been sent Use R_SCI_Control to terminate this operation early R_SClI_GetStatus can be used to find out how many characters have been transmitted Specify PDL_NO_FUNC for this function to wait until the last byte has been sent True if all parameters are valid and the operation completed without errors False if a parameter was out of range or if the channel was already transmitting or if an error occurred during transmission SCl R_SCI_Create R_SCI_Control R_SCI_GetStatus R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 149 Under development P
306. t Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Configure the RS232 port R_SCI_Create 1 PDL_SCI_TX_DISCONN ED PDL_SCI_8N1 115200 0 Configure channel 2 R_DMAC_Create 2 PDL_DMAC_ BLOCK PDL_DMAC_SOURCE_ADDRESS_ PLUS PDL _DMAC DESTINATION _ADDRESS FIXED PDL_DMAC SIZE _8 PDL_DMAC_IRQ_ PDL_DMAC_TRIGGER_SCI1_RX uint8_t amp SCI1 RDR destination_string_l 1 5 L_NO_DATA PDL_NO_DATA PDL_NO_DATA DMAC2_transfer_end_handler 7 Enable channel 2 R_DMAC_Control 2 PDL_DMAC_ENABLE R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae ENESAS Page 5 18 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 lisage Examples L_NO_PTR L_NO_PTR L_NO_DATA L_NO_DATA L_NO_DATA L_NO_DATA L_NO_DATA Initiate reception triggering the DMAC when data is received R_SCI_Receive 1 PDL_SCI_DMAC_TRIGG PDL_NO_PTR PDL_NO_DATA PDL_NO_FUNC PDL_NO_FUNC void DMAC2_transfer_end_handler void Disable channel 2 R_DMAC_Control 2 L_DMAC_SUSPEND L_NO_PTR L_NO_PTR L_NO_DATA L_NO_DATA L_NO_DATA L_NO_DATA L_NO_DATA O Ooo Oo Figure 5 7 An example of using the DMAC for serial port reception R20UT0084E
307. t Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers offic
308. t draft Re designed the I O parameters Modified DMAC DTC PPG SCI and CRC functions Modified CGC IO_PORT DTC MTU TMR and CMT Improved ADC and DAC comments Modified the description for IR flag clear control Reversed parameters 2 and 3 Modified the description for parameters Added transfer trigger re set control Merged the TGRF and TADCORA parameters Separated the enable and inversion options Added the transmit and receive buffer status bits Added the transmit and receive buffer status bits Created SPI API functions Added an example of SDRAM bus control R20UT0084EE0004 Rev 0 04 Aug 25 2010 Revision History 1 RENESAS Renesas Peripheral Driver Library User s Manual RX62N RX621 Group Publication Date Rev 0 02 June 22 2010 Rev 0 03 July 23 2010 Rev 0 04 August 25 2010 Published by Renesas Electronics Corporation CENESAS SALES OFFICES Renesas Electronics Corporation http www renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2880 Scott Boulevard Santa Clara CA 95050 2554 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 1101 Nicholson Road Newmarket Ontario L3Y 9C3 Canada Tel 1 905 898 5441 Fax 1 905 898 3220 Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 585 100 Fax 44 1628 585 900 Re
309. t occurs Specify PDL_NO_FUNC if not required func7 For n 0 to 3 or 6 to 9 The function to be called when an overflow occurs For n 4 or 10 The function to be called when an overflow or underflow occurs Specify PDL_NO_FUNC if not required func8 Forn 1 2 7 or 8 The function to be called when an underflow occurs Specify PDL_NO_FUNC if not required data20 The interrupt priority level for TGRE TGRF overflow or underflow events Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func 5 to 8 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 90 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Return value 4 Library Reference True if all parameters are valid and exclusive otherwise false Category Multi function Timer Pulse Unit Reference R_MTU_Set Remarks e Ifan external clock input pin MTCLKx or I O pin MTIOCnx is made active this function will Program example 1 E i vo configure that pin for input or output and disable other functions on that pin The alternative pins are assigned using function R_MTU_Set If a callback function is specified this function will enable the relevant CPU interrupt Please see the notes on callback function usage
310. t slave_0_ptr 0 uint32_t slave_l_ptr 0 Configure the clocks R_CGC_Set 12 0E6 96E6 48E6 PDL_NO_DATA PDL_CGC_BCLK_DISABLE Set up a DMAC channel for IIC reception R_DMAC_Create 2 PDL_DMAC_SINGLE PDL_DMAC_DESTINATION_ADDRESS_PLUS PDL_DMAC_REQUEST_IICO_RX uint8_t amp RIICO ICDRR slave_data_received BUFFER_SIZE PDL_NO_PTR R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae ENESAS Page 5 51 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group amp Weagakexamplee L_NO_PTR L_NO_DATA L_NO_FUNC Set up a DMAC channel for IIC transmission R_DMAC_Create 3 PDL_DMAC_SINGLE PDL_DMAC_SOURCE_ADDRESS_PLUS PDL_DMAC_REQUEST_IICO_TX slave_data_storage_0 uint8_t amp RIICO ICDRI BUFFER_SIZE PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_FUNC 0 Select I C mode at 100kHz 300ns rise time 200ns fall time R_IIC_Create SLAVE_CHANNEL PDL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 PDL_IIC_SLAVE_OQ_ENABLE 7 PDL_IIC_SLAVE_1 MCU_ADDRESS_0 MCU_ADDRESS_1 PDL_NO_DATA 100E3 300 lt lt 16 200 Enable the DMAC channels R_DMAC_Control PDL_DMAC_2 PDL_DMAC_3 __DMAC_ENABLE L_NO_DATA L_NO
311. ta5 A pointer to the data storage location Read any of the timer s counter compare or status flag registers data1 The unit number n where n 0 or 1 data2 The status flags shall be stored in the format below A flag will be set to 1 if the condition has been detected Specify PDL_NO_PTR if the flags are not to be read The unit 0 status flags shall be stored in the format b7 b6 b5 b4 b3 b2 b1 bO TMRO TMR1 0 Compare Compare 0 Compare Compare Overtl w match B match A Overflow match B match A The unit 1 status flags shall be stored in the format b7 b6 b5 b4 b3 b2 b1 bO TMR2 TMR3 0 Compare Compare 0 Compare Compare Oyerow match B match A Overow match B match A data3 Where the counter value shall be stored Specify PDL_NO_PTR if it is not required data4 Where the compare match A value shall be stored Specify PDL_NO_PTR if it is not required data5 Where the compare match B value shall be stored Specify PDL_NO_PTR if it is not required True if all parameters are valid and exclusive otherwise false Timer TMR R_TMR_CreateUnit R_ TMR_ControlUnit Ifthe status flags are read any flag that has been set to 1 shall be automatically cleared to 0 by this function R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 129 Under development Preliminary Specification Specifications in this preliminary version are subject to c
312. tart monitoring the channel R_IIC_SlaveMonitor SLAVE_CHANNEL PDL_IIC_RX_DMAC_TRIGGER__ E PDL _IIC_TX _DMAC_TRIGG PDL_NO_PTR PDL_NO_DATA slave_event_handler 7 void slave_event_handler void uint32_t status_flags 0 R_IIC_Get Status SLAVE_CHANNEL amp status_flags PDL_NO_PTR PDL_NO_PTR NACK and Stop detected end of transmission to the master if status_flags amp 0x1800 0x1800 if transmission_completed false transmission_completed true else The main loop has failed to process the last transfer in time R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 5 54 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group siage Examples Stop detected else if status_flags amp 0x1800 0x0800 if reception_completed false reception_completed true else The main loop has failed to process the last transfer in time nop Figure 5 29 An example of IIC Slave operation using two DMAC channels R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 5 55 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Urago Exatiples 5 11 10 bit Analog to Digital Converter 1 ADC Conve
313. te example extern uint32_t dtc_cmt0O_transfer_data void func void uintl6_t StatusValue uint32_t SourceAddr Read the status and current source address for the CMTO transfer R_DTC_GetStatus dtc_cmt0O_transfer_data amp StatusValue amp SourceAddr PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR R20UT0084EE0004 Rev 0 04 Aug 25 2010 ztENESAS Page 4 81 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 4 2 12 Multi Function Timer Pulse Unit 1 R_MTU Set Synopsis Prototype Description Return value Category Reference Remarks Program example Configure the Multi function Timer Pulse Units bool R_MTU_Sei uint16_t data II Configuration Set up the global MTU options data Configure the global options Use to separate each selection e Pin selection PDL_MTU_PIN_3C Aor PDL_MTU_PIN 3C B Select the A or B pin for MTIOC3C PDL_MTU_PIN_3BD_Aor PDL_MTU_PIN 3BD_B Select the A or B pins for MTIOC3B and MTIOC3D PDL_MTU_PIN_4AC Aor PDL_MTU_PIN_4AC B Select the A or B pins for MTIOC4A and MTIOC4C PDL_MTU_PIN_4BD_ Aor PDL_MTU_PIN_ 4BD B Select the A or B pins for MTIOC4B and MTIOC4D PDL_MTU_PIN_5UVW_Aor PDL_MTU_PIN 5UVW_B Select the A o
314. ted by the EEPROM R20UT0084EE0004 Rev 0 04 Aug 25 2010 Sa RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Grou P p 5 Usage Examples 3 Repeated Start Send 1 byte to the EEPROM to update the lower address bits and do not stop R_IIC_MasterSend 0 PDL_IIC_STOP_DISABLE EEPROM_ADDRESS 0x37 1 PDL_NO_FUNC 0 Read data from the EEPROM A repeated start will R_IIC_MasterReceive 0 PDL_NO_DATA EPROM_ADDRESS data_storage 2 PDL_NO_FUNC 0 Figure 5 24 Set the lower address to 37h and then read 2 bytes Slave address Memory address Slave address PR A roe aL AT Figure 5 25 The bus activity showing the Repeated Start condition when switching to the Read process R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 5 40 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Weagekxamplez 5 10 2 Master mode with DMAC In the following example data is written to an EEPROM in two bursts DMAC channel 3 is used to handle the data transfer The same EEPROM address locations are then read out in two bursts DMAC channel 2 is used to handle the data transfer Peripheral driver function prototypes include r_pdl_iic h include r_pdl_cgc h inclu
315. terrupt input Reading the status of an external interrupt Reading an interrupt register Writing to an interrupt register Modifying an interrupt register R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 2 4 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 5 VO Port Driver The driver functions support the use of the I O port pins providing the following operations 1 2 Configuration for use Reading the pin or port configuration Modifying the pin or port configuration Reading a pin or 8 bit port value Writing to a pin or 8 bit port Comparing a pin or 8 bit port with a supplied value Modifying a pin or 8 bit port using a logical operation Waiting until a pin or 8 bit port matches a supplied value R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 2 5 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 6 Port Function Control Driver The driver functions support access to the Port Function Control PFC registers which select the mode of operation for some I O pins The other driver functions modify the PFC registers automatically For peripherals that are not supported by the driver library these functions support 1 Reading from a PFC register 2 Writing to a PFC register 3 M
316. the dead time data register TDDR PDL_MTU_REGISTER_CYCLE_DATA Update the cycle data register TCDR PDL_MTU_REGISTER_CYCLE_BUFFER Update the cycle buffer register TCBR data7 The dead time data register value This will be ignored if the register is not selected data8 The cycle data register value This will be ignored if the register is not selected data9 The cycle buffer register value This will be ignored if the register is not selected Return value True if all parameters are valid and exclusive otherwise false Category Multi function Timer Pulse Unit Reference Remarks e None Program example RPDL definitions include r_pdl_mtu h RPDL device specific definitions include r_pdl_definitions h void func void Allocate a copy of the structure for the selected channel R_MTU_ControlUnit_structure unit0O_parameters Set the control options for unit 0 unitO_parameters data2 PDL_MTU_OUT_P_PHASE_ALL_HIGH_LOW unitO_parameters data5 PDL_MTU_DEAD_TIME_ENABLE unitO_parameters data6 PDL_MTU_REGISTER_DEAD_TIME PDL_MTU_REGISTER_CYCLE_DATA unitO_parameters data7 OxFFDD unitO_parameters data8 0x0100 Modify the operation of unit 0 R_MTU_ControlUnit 0 amp unit0_parameters R20UT0084EE0004 Rev 0 04 Aug 25 2010 Eaa RENESAS Under development Preliminary Specification Specific
317. tically when the conversion is complete The time delay between starting conversions on multiple units is minimised but has to use separate instructions This function minimises the delay between starts by using an interrupt to prevent other interrupts from occurring during the start sequence If the user has disabled interrupts cleared the I bit in the PSW register in their own code this function will lock up For true simultaneous starting of ADC units select an appropriate hardware trigger e g timer TMR RPDL definitions include r_pdl_adc_10 h RPDL device specific definitions include r_pdl_definitions h void func void Stop ADC unit 0 and start ADC unit 1 R_ADC_10_Control PDL_ADC_10_0_OFF PDL_ADC_10_1_ON R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 195 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 4 R_ADC_10 Read Synopsis Prototype Description Return value Category Reference Remarks Program example Read the ADC conversion results bool R_ADC_10_Read uint8_t data1 ADC unit selection uint16_t data2 Pointer to the buffer where the converted values are to be stored Reads the conversion values for an ADC unit data1 Select the ADC u
318. timer channel registers 11 R_TMR_ReadUnit Read from timer unit registers 1 R_CMT Create Configure a CMT channel Compare Match 2 R_CMT_CreateOneShot Configure a CMT channel as a one shot event Timer 3 R_CMT_Destroy Disable a CMT unit 4 R_CMT_Control Control CMT operation 5 R_CMT_Read Read CMT channel status and registers 1 R_WDT_Create Configure the Watchdog timer Watchdog Timer 2 R_WDT_Cortrol Control the Watchdog operation 3 R_WDT_Read Read the Watchdog timer status and registers Independent Watchdog Timer R_SCI_Set Configure the SCI pin selection R_SCl_Create SCI channel setup Serial R_SCI_Destroy Shut down a SCI channel Communication R_SClI_Send Send a string of characters Interface R_SCI_Receive Receive a string of characters R_SCI_Control Control the SCI channel R_SCl_GetStatus Check the status of a SCI channel CRC calculator R_CRC_Create Configure the CRC calculator R_CRC_Destroy Shut down the CRC calculator C bus interface R_CRC Write Write data into the CRC calculation register R_CRC_Read Read the CRC calculation result R_IIC_Create C channel setup R_IIC_Destroy Disable an C channel R_IIC_MasterSend Write data to a slave device R_IIC_MasterReceive Read data from a slave device R_IIC_MasterReceiveLast Complete a DMAC or DTC based read process R_IIC_SlaveMonitor Monitor the bus and receive data from a master R_IIC_SlaveSend
319. tinterrupt Synopsis Enable faster interrupt processing for one interrupt Prototype bool R_INTC_CreateFastInterrupt uint8_t data The interrupt to be selected Description 1 3 data Choose the interrupt vector to be processed using the fast interrupt process Name Module Interrupt cause PDL_INTC_VECTOR_BUSERR External bus Error illegal access or timeout PDL_INTC_VECTOR_FIFERR PDL_INTC_VECTOR FRDYI Flash memory Error Ready PDL_INTC_VECTOR_SWINT Interrupt control Software interrupt PDL_INTC_VECTOR CMTO PDL_INTC_VECTOR_CMT1 PDL_INTC_VECTOR_CMT2 PDL_INTC_VECTOR_CMT3 Compare match timer Compare match PDL_INTC_VECTOR EINT Ethernet control Event detection PDL_INTC_VECTOR_DOFIFOO PDL_INTC_VECTOR_D1FIFOO DOFIFO transfer request D1FIFO transfer request PDL_INTC_VECTOR USBI1 PDL_INTC_VECTOR USBR1 PDL_INTC_VECTOR USBIO USB port 0 Event detection PDL_INTC_VECTOR_USBRO Resume PDL_INTC_VECTOR_DOFIFO1 DOFIFO transfer request PDL_INTC_VECTOR_D1FIFO1 D1FIFO transfer request USB port 1 Event detection Resume PDL_INTC_VECTOR SPEIO PDL_INTC_VECTOR SPRIO PDL_INTC_VECTOR SPTIO PDL_INTC_VECTOR _SPIIO RSPI channel 0 Error Receive buffer full Transmit buffer empty Idle PDL_INTC_VECTOR_SPEI PDL_INTC_VECTOR_ SP
320. tion Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 22 Serial Communication Interface Driver The driver functions support the use of the six serial communication channels SCIO SCI3 SCI5 SCI6 providing the following operations 1 2 Selection of the SCI pins for use Configuration for use including e Automatic baud rate clock calculations e Automatic interrupt control e Automatic I O pin configuration Disabling channels that are no longer required and enabling low power mode Transmitting data with polling or interrupt mode automatically selected Receiving data with polling or interrupt mode automatically selected Control the channel operation Reading the status flags Note The Clock Generation Circuit must be configured before configuring any serial channel R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 2 22 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 23 CRC Calculator Driver The driver functions support the CRC calculator providing the following operations 1 Configuration for use including e Polynomial selection e Bit order selection e Preparation for a new calculation 2 Disabling the calculator and enabling low power mode 3 Writing data to be used for the calculation 4 Reading the calculation result R
321. tion uint32_t data2 uint32_t data3 uint32_t data4 uint16_t data5 uint32_t data6 uint32_t data7 uint32_t data8 uint16_t data9 uint16_t data10 uint16_t data11 uint16_t data12 uint16_t data13 uint16_t data14 uint16_t data15 uint16_t data16 uint16_t data17 uint16_t data18 Register value Register value Register value Register value Register value Register value Register value Register value Register value Register value A pointer to the structure 4 Library Reference void func1 Callback function void func2 Callback function void func3 Callback function void func4 Callback function uint8_t data19 Interrupt priority level void func5 Callback function void func6 Callback function void func7 Callback function void func8 Callback function uint8_t data20 Interrupt priority level Description 1 8 Set up a 16 bit MTU channel data1 The channel number n where n 0 to 11 data2 Configure the channel mode If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Operation mode Valid for n 0 to 4 or 6 to 10 unless stated otherwise PDL_MTU_ MODE NORMAL or Normal operation PDL_MTU_MODE_PWM1 or Pulse Width Modulation PWM mode 1 PDL_MTU_MODE_PWN2 or Pulse Width Modulation PWM mode 2 Valid fo
322. tion required only if the pin is used for the timer function PDL_TMR_PIN_TMRO_A or F PDL_TMR PIN TMRO_B Select the A or B pins for TMCIO and TMRIO PDL_TMR_PIN_TMR1_Aor PDL_TMR_PIN_TMR1_B Select the A or B pin for TMCI1 PDL_TMR_PIN_TMR2_A or PDL_TMR_PIN_TMR2 B Select the A or B pin for TMCI2 PDL_TMR_PIN_TMR3_A or PDL_TMR_PIN_TMR3_B Select the A or B pins for TMCI3 and TMRIS3 Return value True if all parameters are valid and exclusive otherwise false Category Timer TUR Reference R_TMR_CreateChannel R_TMR_CreateUnit Remarks Before calling any R_TMR_Create function if the selected device package offers A or B pins for TMR signals call this function once e Pins which are not used for the TMR functions may be omitted Program example include r_pdl_tmr h void func void Configure the applicable TMR pins R_TMR_Set PDL_TMR_PIN_TMRO_A PDL_TMR_PIN_TMR1_B PDL_TMR_PIN_TMR2_B R20UT0084EE0004 Rev 0 04 Aug 25 2010 a RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 R_TMR_CreateChannel Synopsis Prototype Description 1 2 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Page 4 111 Configure a timer TMR channel bool R_TMR_CreateChannel uint8_t data1 Channel
323. tor interrupts bool R_INTC_CreateExceptionHandlers void func1 Callback function void func2 Callback function void func3 Callback function Register the user functions to be called by the fixed vector and software interrupts func1 The function to be called when a privileged instruction is detected while in user mode Specify PDL_NO_FUNC if no callback function is required func2 The function to be called when an undefined instruction is detected Specify PDL_NO_FUNC if no callback function is required func3 The function to be called when a floating point exception is detected Specify PDL_NO_FUNC if no callback function is required True Interrupt control e Please see the notes on callback function use in 6 A callback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Declaration of callback function void CallBackFunc void void func void Add a function to manage floating point errors R_INTC_CreateExceptionHandlers PDL_NO_FUNC PDL_NO_FUNC FloatingPointFunc R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 19 Under development Preliminary Specification Specifications in this preliminary version are subject to cha
324. trol PDL_CGC_SDCLK_ENABLE or Output the SDRAM clock SDCLKk PDL_CGC_SDCLK_DISABLE or leave the SDCLK pin as a port pin e Oscillation Stop Detection control PDL_CGC_OSC_STOP_ENABLE or Enable or disable the oscillation stop detection PDL_CGC_OSC_STOP_DISABLE function e Sub clock oscillator control PDL_CGC_SUB_CLOCK_ENABLE or PDL_CGC_ SUB CLOCK DISABLE Enable or disable the sub clock oscillator Return value True if all parameters are valid and exclusive otherwise false For RX62N the following rules shall be checked e Main clock oscillator frequency 8 to 14 MHz e ficLk 8 to 100 MHz e feck 8 to 50 MHz e feck 8 to 100 MHz e fick 2 fpcik and fictk 2 facik e fictk fPc k and feck are achievable main clock oscillator x 8 1 2 4 or 8 Functionality Clock generation circuit References None R20UT0084EE0004 Rev 0 04 Aug 25 2010 San RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group dban Reena Remarks e This function must be called before configuring clock dependent modules e This function modifies the BCLK and SDCLK pins for input or output The maximum output frequency on the BCLK pin is 50 MHz Program example RPDL definitions include r_pdl_cgc h RPDL device specific definitions inc
325. type The timer period in seconds or float The timer frequency in Hz or float The value to be put in the register uint16_t Return value True if all parameters are valid and exclusive otherwise false Category Compare Match Timer Reference R_CMT_Create Remarks e R_CMT_Create must be first be used to configure the channel e The Stop operation is executed at the start of this function The Start operation is executed at the end Therefore both options can be selected together with a value change in one function call Program example RPDL definitions include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h void func void Change channel 2 to Ims period R_CMT_Control HUNI F DL_CMT_PERIOD E 3 R20UT0084EE0004 Rev 0 04 Aug 25 2010 Sanger RENESAS Under development Preliminary Specification 5 R_CMT_Read Synopsis Prototype Description Return value Category Reference Remarks Program example Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference Read CMT channel status and registers bool R_CMT_Read uint8_t data1 Channel selection uint8_t data2 A pointer to the data storage location uint16_t data3 A pointer to the data storage location Read and store the count
326. type bool R_BSC_Create 4 Library Reference Synopsis Configure the external bus controller uint32_t data1 Configuration pin select control uint32_t data2 Configuration2 output enable control uint8_t data3 Configuration3 error control void func Callback function uint8_t data4 Interrupt priority level Control the external bus controller If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults d ata1 Description 1 2 Configure the I O pins error detection and register the callback function Chip select pin selection only required for each external memory area that is enabled PDL_BSC_CSO Aor PDL_BSC_CSO B Select pin CSO A or CSO B PDL_BSC_CS1 Aor PDL_BSC_CS1_Bor PDL BSC CS1_C Select pin CS1 A CS1 B or CS1 C PDL_BSC_CS2_A or PDL_BSC_CS2_B or PDL_BSC_CS2_C Select pin CS2 A CS2 B or CS2 C PDL_BSC_CS3 Aor PDL_BSC_CS3_B or PDL_BSC_CS3_C Select pin CS3 A CS3 B or CS3 C PDL_BSC_CS4 Aor PDL_BSC_CS4 Bor PDL_BSC_CS4_C Select pin CS4 A CS4 B or CS4 C PDL_BSC_CS5 Aor PDL_BSC_CS5_Bor PDL_BSC_CS5 C Select pin CS5 A CS5 B or CS5 C PDL_BSC_CS6 Aor PDL_BSC_CS6 Bor PDL_BSC_CS6_C Select pin CS6 A CS6 B or CS6 C PDL_BSC_CS7_ Aor PDL_BSC_CS7_Bor PDL_BSC_CS7_C Select pin CS7 A CS7 B or CS7 C Addres
327. ucture members uint8_t data2 uint8_t data3 uint16_t data4 uint16_t data5 uint16_t data6 uint16_t data7 uint16_t data8 uint16_t data9 uint16_t data10 Control an MTU channel bool R_MTU_ControlChannel Control settings II Register selection Register value II Register value Register value Register value Register value II Register value Register value 4 Library Reference Channel selection A pointer to the structure Description 1 2 Modify a timer channel s registers data1 The channel number n where n 0 to 11 data2 The channel settings to be modified If multiple selections are required use to separate each selection e Counter stop re start Valid for n 0 to 4 or 6 to 10 PDL_MTU_STOP Disable the counter clock source PDL_MTU_START Re enable the counter clock source e Counter stop re start Valid for n 5 or 11 PDL_MTU_STOP_U PDL MTU STOP V PDL MTU STOP W PDL MTU START U PDL MTU START V PDL_MTU START W Disable the counter clock source Re enable the counter clock source data3 The channel registers to be modified If multiple selections are required use to separate each selection e The registers to be modified For n 0 to 4 or 6 to 10 PDL_MTU_REGISTER_COUNTER Timer counter register TCNT PDL_MTU_REGISTER_TGRA General register A PDL_MTU_REGISTER_TGRB Gen
328. ug 25 2010 Page 5 29 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 5 Weagekxamplez 3 Synchronous Transmission and Reception Figure 5 15 shows the configuration of SCI channel 3 as the clock master followed by the simultaneous transmission and reception of data The Receive function call uses interrupts while the Transmit function uses polling Peripheral driver function prototypes include r_pdl_sci h include r_pdl_cgc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Callback function prototype void SCI3RxFunc void volatile uint8_t data_received define BUFFER_SIZE 10 void main void uint8_t Tx _Data BUFFER_SIZ uint8_t Rx_Data BUFFER_SIZ uint8_t transfer_size 8 uint8_t i Configure the system clocks R_CGC_Set 12E6 96E6 48E6 0 PDL_CGC_BCLK_DISABLI Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Set up SCI channel 3 Sync MSb first 2 Mbps R_SCI_Create 3 PDL_SCI_SYNC PDL_SCI_MSB_FIRST 2E6 1 Load the required data into the transmit buffer for i 0 i lt BUFFER_SIZE i Tx_Data i uint8_t i 1 data_received false Set
329. uint8_t data1 Pin selection uint8_t data2 A pointer to the buffer where the status data shall be stored J Description Acquire the status for the specified external interrupt data1 Choose the interrupt pin to be checked PDL_INTC_IRQn n 0 to 15 or IRQn n 0 to 15 interrupt pin or PDL_INTC_NMI NMI interrupt pin data2 The status flags shall be stored in the following format For an IRQ pin b7 b4 b3 b2 b1 bO Input detection condition Pin level Input detection status 00b Low level 0 01b Falling edge 0 Low 0 Not detected 10b Rising edge 1 High 1 Detected 11b Both edges For the NMI pin b7 b4 b3 b2 b1 bO Oscillation stop Low voltage Input detection Input detection 0 interrupt request interrupt request condition status 0 Not detected 0 Not detected 0 Falling edge 0 Not detected 1 Detected 1 Detected 1 Rising edge 1 Detected Return value True if all parameters are valid and exclusive otherwise false Category Interrupt control Reference R_INTC_CreateExtInterrupt R_INTC_ControlExtInterrupt Remarks I O port register PF8IRQ or PF9IRQ is checked to determine which pin is used for IRQn e If this function is called from within a callback function the input detection status will be 0 Program example RPDL definitions include r_pdl_intc h RPDL device s
330. ult register clearing PDL_CRC_CLEAR_RESULT or PDL_CRC_RETAIN RESULT Clear or retain the value in the result register data2 The address of the location where the result shall be stored For the 8 bit polynomial the results are stored in the lower order byte Return value True Category CRC Reference R_CRC_Create R_CRC_Write Remarks e None Program example RPDL definitions include r_crc h RPDL device specific definitions include r_pdl_definitions h void func void uint16_t CRCresult Read the CRC result and clear it R_CRC_Read PDL_CRC_RETAIN_RESULT amp CRCresult R20UT0084EE0004 Rev 0 04 Aug 25 2010 Pea RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 2 22 1 R_IIiC_Create Synopsis Prototype Description 1 3 C Bus Interface C channel setup bool R_IIC_Create uint8_t data1 uint32_t data2 uint32_t data3 uint16_t data4 uint16_t data5 uint16_t data6 uint32_t data7 uint32_t data8 Set up the selected I C channel data1 Select channel IICn where n 0 or 1 data2 Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold Bus mode selection
331. ults External bus width PDL_BSC_WIDTH_16 or PDL_BSC_WIDTH_8 or PDL_BSC_WIDTH 32 Select 16 bit 8 bit or 32 bit data bus width Endian mode PDL_BSC_ENDIAN_SAME or PDL_BSC_ENDIAN_OPPOSITE Set the bus endian mode to be the same or opposite to that of the CPU e Write access mode PDL_BSC_WRITE_BYTE or PDL_BSC_WRITE_SINGLE Select byte strobe or single write strobe mode External wait control PDL_BSC_WAIT_DISABLE or PDL_BSC_WAIT_ENABLE Disable or enable external wait control using the WAIT pin e Page access control PDL_BSC_PAGE_READ_DISABLE or PDL_BSC_PAGE_READ_NORMAL or PDL_BSC_PAGE_READ_ CONTINUOUS Disable or enable page read accesses using normal access compatible mode or continuous assertion mode PDL_BSC_PAGE_WRITE_DISABLE or PDL_BSC_PAGE_WRITE_ENABLE Disable or enable page write accesses data3 The number of read recovery cycles RRCV Valid between 0 and 15 data4 The number of write recovery cycles WRCV Valid between 0 and 15 7tENESAS Under development Preliminary Specification Description 2 2 Return value Category Reference Remarks Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference data5 The number of wait cycles used for second and subsequent accesses during a page read se
332. ume to PDL_LPC_CANCEL_USB_ENABLE cancel deep software standby mode R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 43 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group A Aiprahy E Description 2 2 data2 Select the waiting times If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Software Standby waiting time PDL_LPC_STANDBY_64 or PDL_LPC_STANDBY_512 or PDL_LPC_STANDBY_1024 or PDL_LPC_STANDBY_2048 or PDL_LPC_STANDBY_4096 or Select the number of PCLK cycles that will elapse PDL_LPC_STANDBY_ 16384 or before the CPU resumes after exiting from PDL_LPC_STANDBY_ 32768 or software standby mode PDL_LPC_STANDBY_ 65536 or PDL_LPC_STANDBY_ 131072 or PDL_LPC_STANDBY_262144 or PDL_LPC_STANDBY_ 524288 Deep Software Standby waiting time PDL_LPC_DEEP_STANDBY_64 or PDL_LPC_DEEP_STANDBY_512 or PDL_LPC_DEEP_STANDBY_ 1024 or PDL_LPC_DEEP_STANDBY_ 2048 or PDL_LPC_DEEP_STANDBY_4096 or Select the number of PCLK cycles that will elapse PDL_LPC_DEEP_STANDBY_ 16384 or before the CPU resumes after exiting from deep PDL_LPC_DEEP_STANDBY_ 32768 or software standby mode PDL_LPC_DEEP_STANDBY_ 65536 or PDL_LPC_DEEP_STANDBY_ 131072 or PDL_LPC_DEEP_STANDBY_ 262144 or PDL_LPC_DEEP_STANDBY_524288
333. unc void Shut down ADC unit 1 R_ADC_10_Destroy 1 R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 194 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 Library Reference 3 R_ADC_10_Control Synopsis Prototype Description Return value Category Reference Remarks Program example Start or stop an ADC unit bool R_ADC_10_Control uint16_tdata Conversion unit control Controls start stop operation of the specified ADC data To select multiple units at the same time use to separate each value On off control PDL_ADC_10_0 ONor PDL_ADC_10_0 OFF Start or stop ADC unit 0 conversion PDL_ADC_10 1 ON or PDL_ADC_10_1_OFF Start or stop ADC unit 1 conversion e Control the CPU during the ADC conversion The default setting is shown in bold PDL_ADC_10 CPU _ONor Allow the CPU to run normally during the conversion Stop the CPU when the conversion starts PDE ARG EPR CORT The CPU will re start when any valid interrupt occurs True if all parameters are valid and exclusive otherwise false ADC R_ADC_10_Create R LADC_10_ Read e Use this API function only when the software trigger option is selected e For single or one cycle scan modes the ADC will stop automa
334. unctions are used for configuring the ADC units controlling the units and reading the conversion results 19 Digital to Analog converter These driver functions are used for configuring the DAC module and setting the output voltages R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 2 2 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 3 Clock Generation Circuit Driver The driver functions support the control of the internal clock generator providing the following operations 1 Configuration of the multiple clock outputs for system peripheral and external bus operation 2 Reading the Clock generator status flags Note Configuring the Clock Generation Circuit also provides information on clock frequencies that will be used by the integrated drivers for other peripherals R20UT0084EE0004 Rev 0 04 Aug 25 2010 Sans RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 2 Driver 2 4 Interrupt Control Driver The driver functions support the use of the interrupt controller providing the following operations 1 2 Configuration an external interrupt pin for use Assigning an interrupt to be processed using the Fast Interrupt route Assigning handlers for the fixed exception interrupts Controlling an external in
335. up 4 2 25 10 bit Analog to Digital Converter 1 R_ADC_10 Create Synopsis Configure an ADC unit Prototype bool R_ADC_10_Create uint8_t data1 ADC unit selection uint32_t data2 ADC configuration 4 Library Reference uint32_t data3 ADC conversion clock frequency float data4 ADC input sampling time void func Callback function uint8_t datad Interrupt priority level Description 1 2 Set the ADC s mode and operating condition data1 Select the ADC unit 0 or 1 to be configured data2 Conversion options To set multiple options at the same time use to separate each value The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Scan mode PDL_ADC_10_MODE_SINGLE or Select Single mode PDL_ADC_10_MODE_CONTINUOUS_SCAN or Continuous scan mode or PDL_ADC_10 MODE_ONE_CYCLE_SCAN One cycle scan mode Input channel selection PDL_ADC_10 CHANNELS OPTION_1 or Any mode For unit 0 channel ANO For unit 1 channel AN4 PDL_ADC_10_CHANNELS_OPTION_2 or Single mode For unit 0 channel AN1 For unit 1 channel AN5 Scan mode For unit 0 channels ANO and AN1 For unit 1 channels AN4 and AN5 PDL_ADC_10_CHANNELS_OPTION_3 or Single mode For unit 0 channel AN2 For unit 1 channel AN6 Scan mode For unit 0 channels ANO AN1 and AN2 For unit 1 channels AN4 AN5 and
336. upt WDT c intprg c Ied c resetprg c sbrk c Ej P P E P P lt a a o nels Ls ts Le Ls Lis La Dependencies fF E2 E EA Default desktop 4 Figure 1 3 intprg c and vecttbl c have been excluded R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae ENESAS Page 1 7 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 1 Introduction 1 1 6 Add the library file path The library file is added to the list used by the linker application Use the key sequence Alt B R to open the RX Standard Toolchain window Select the Link Library tab From the Show entries for drop down menu select Library files Click on the Add button In the Add library file window enter the details as shown Add library file Relative to Project directory h Cancel File path RPDLSRX62N_library Click on OK to close the window Click on OK to return to the main HEW window 1 1 7 Build the project No further configuration should be required Simply build the project R20UT0084EE0004 Rev 0 04 Aug 25 2010 ae ENESAS Page 1 8 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 1 Introduction 1 2 Document structure The drivers are summarised in section 2 and explained in detail in s
337. ved so far R_SCIl_Control can be used to terminate the reception early Specify PDL_NO_FUNC for this function to continue until the required number of bytes has been received func2 The function to be called if a receive error occurs Specify PDL_NO_FUNC to ignore errors R20UT0084EE0004 Rev 0 04 Aug 25 2010 RENESAS Page 4 151 Under development RX62N Group RX621 Group Preliminary Specification Specifications in this preliminary version are subject to change 4 Library Reference Return value True if all parameters are valid and the operation completed False if a parameter was out of range Category SCI Reference R_SCl_Create R_SCl_Control R_SCl_GetStatus Remarks The maximum number of characters to be received is 65535 e Wait until a transmission on the same channel is complete before calling this function If callback function func is specified reception interrupts are used Please see the notes on callback function usage in 6 e If no callback function func is specified this function will operate in polling mode The RXI flag will be used to manage the data reception If the SCI channel s control registers are directly modified by the user this function may lock up e If no error callback function func2 is specified the error flags are cleared automatically to allow the reception process to complete e Callback functions are executed by the interru
338. very 0 Initialization sequence 0 Mode register setting not in 0 not in progress not in progress 0 progress 1 Transition recovery 1 Initialization sequence 1 Mode register setting in in progress in progress progress Return value True Category Bus Controller Reference R_BSC_Create R_BSC_Control Remarks e User shall call R_BSC_Control to clear the status registers after reading the status Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group E E Program example RPDL definitions include r_pdl_bsc h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t statusl status3 uintl6_t status2 Read the flags R_BSC_GetStatus amp statusl amp status2 amp status3 R20UT0084EE0004 Rev 0 04 Aug 25 2010 z AS Page 4 62 KENES Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group 4 2 9 DMA Controller 1 R_DMAC_Create Synopsis Prototype Description 1 3 Configure the DMA controller bool R_DMAC_Creaite uint8_t data1 uint32_t data2 uint8_t data3 void data4 void data5 uint16_t data6 uint16_t data7 int32_t data8 uint32_t data9 Transfer count Address offset Channel selection II Configur
339. xt highest frequency The timing limits depend on the peripheral module clock PCLK e The 12 bit ADC and 10 bit ADC must be used exclusively If 12 bit ADC is already in use this function will return false e If any of Self Diagnostic enabled options is selected please do not select the Scan mode Input channel selection and Trigger selection Their default settings will be used User is expected to call RLADC_10_Control and R_LADC_10_Read to get the conversion result Please refer to Section 5 11 for usage example Pk fPeLk MHz Parameter Limit Equation 50 12 5 32 8 Conversion clock Minimum feck 8 4 2 1 24 0 6 25 MHz 6 25 MHz 4 0 MHz 4 0 MHz ADCLK Maximum feck 50 00 MHz 12 50 MHz 32 00 MHz 8 00 MHz wo ae Maximum 2 4 0us 4 0us 6 25us 6 25us Conversion time Minimum id ADOR 0 5us 2us 0 78145 3 13u5 Semaine tin Minimum 0 5us ping Maximum 255 ADCLK e g 5 1ys at 50 MHz Total oa Conversion time sanversion time Minimum sampling time 1 0us 2 5us 1 28us 3 63us R20UT0084EE0004 Rev 0 04 Aug 25 2010 Sangre RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX62N Group RX621 Group Jiban Resrenes Program example RPDL definitions include r_pdl_adc_10 h RPDL device specific definitions include r_pdl_definitions h ADC unit 1 callback funct

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