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Intel386™ EX Embedded Microprocessor User`s Manual

1. D 21 DMASRR DMA Software Request read format Expanded Addr F009H DMASRR ISA Addr 0009H Reset State 00H 7 0 SR1 SRO Bit Bit Number Mnemonic Function 7 2 Reserved These bits are undefined for compatibility with future devices do not modify these bits 1 SR1 Software Request 1 When set this bit indicates that channel 1 has a software request pending 0 SRO Software Request 0 When set this bit indicates that channel 0 has a software request pending DMA Software Request write format Expanded Addr 009 DMASRR ISA Addr 0009H Reset State 00H 7 0 SR 0 CS Bit Bit Number Mnemonic Function 7 3 Reserved These bits are undefined for compatibility with future devices do not modify these bits 2 SR Software Request Setting this bit generates a software request for the channel specified by bit 0 When the channel s buffer transfer completes this bit is cleared 1 0 Must be 0 for correct operation 0 CS Channel Select 0 The selection for bit 2 affects channel 0 1 The selection for bit 2 affects channel 1 D 26 intel SYSTEM REGISTER QUICK REFERENCE D 22 DMASTS DMA Status Expanded Addr 008 DMASTS ISA Addr 0008H read only Reset State 00H 7 0 R1 RO
2. Clock Count Notes Real Pro Real Pro Ad tected Ad tected i dress Virtual dress Virtual Instruction Format Mode Ad Mode Ad or dress or dress Virtual Mode Virtual Mode 8086 8086 Mode Mode SUB Subtract register from register 001010dw modreg r m 2 2 register from memory 0010100w modreg r m qu du b h memory from register 0010101w modreg r m 6 6 b h immediate from 2 7 2 7 b h register memory 100000sw mod 101 r m immediate data immediate from accu 9 9 49440w immediate data 2 mulator short form SBB Subtract with borrow register from register 000110dw modreg r m 2 2 register from memory 0001100w mod reg 75 b h memory from register 0001101w modreg r m 6 6 b h immediate from 100000sw 1 1 r m immediate data eu emt b n register memory immediate from acct 0001110w immediate data 2 2 mulator short form DEC Decrement register memory 1111111w reg00 1 r m 2 6 2 6 b h register short form 01001 reg 2 2 CMP Compare register with register 001110dw modreg r m 2 2 memory with register 0011100w mod reg 5 5 b h register with memory 00 101w modreg r m 6 6 b h immediate with 100000sw mod 111r m immediate 2 5 2 5 b h register memory data immediate with accu 00 110w immediate 2 2 mulator short form data NEG Change sign 11 0 1 1 2 6 2 6 b h AAA ASCII adjust for
3. Baud rate Count Down Expanded Addr F48AH SSIOCTR ISA Addr read only Reset State 00H 7 0 BSTAT CV6 CV5 CV4 CV2 CV1 CVO Bit Bit Number Mnemonic Function 7 BSTAT Baud rate Generator Status 0 The baud rate generator is disabled 1 The baud rate generator is enabled 6 0 CV6 0 Current Value These bits indicate the current value of the baud rate down counter D 62 SSIORBUF Receive Holding Buffer Expanded Addr F482H SSIORBUF ISA Addr read only Reset State 0000H 15 8 15 14 RB13 RB12 RB11 RB10 RB9 RB8 7 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RBO Bit Bit i Number Mnemonic Runerien 15 0 RB15 0 Receive Buffer Bits This register contains the last word received The receive shift register shifts bits in with the rising edge of the receiver clock pin Data is shifted in starting with the most significant bit The control logic then transfers the received word from the receive shift register to SSIORBUF D 61 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL D 63 SSIOTBUF Transmit Holding Buffer Expanded Addr F480H SSIOTBUF ISA Addr read write Reset State 0000H 15 8 15 TB14 TB13 TB12 TB11 TB10 TB9 TB8 7 0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TBO Bit Bit i Number Mnemonic Function 15 0 TB15 0 Transmit Buffer Bits
4. 10 15 Mode 4 Basic 10 16 Mode 4 Disabling the eee emnes 10 17 Mode 4 Writing a New eene emen 10 17 Mode 5 Basic nnns 10 18 Mode 5 Retriggering the Strobe sse mm0 19 Mode 5 Writing a New Count emen 10 19 Timer Configuration Register 10 21 Port Configuration Register PSCFQG seem 10 22 Pin Configuration Register eme ems 10 23 Timer Control Register TMRCON Control Word 10 25 Timer n Register TMRn Write 10 26 Timer Control Register TMRCON Counter latch 10 28 Timer n Register TMRn Read 10 29 Timer Control Register TMRCON Read back Format 10 30 Timer n Register TMRn Status 10 32 Serial Unit 1 11 2 SIOn Baud rate Generator Clock Sources eeeeeeens 11 4 SIOn Transmlitter ere ee pev eet BERE PR E ER rns 11 7 SIOn Data Transmission Process Flow essen 11 8 SIOn Receiver entes dag SIOn Dat
5. D 55 RFSCON Refresh Control Expanded Addr F4A4H RFSCON ISA Addr read write Reset State 0000H 15 8 CV9 CV8 7 0 CV7 CV6 CV5 CV4 CV2 CV1 CVO Bit Bit Function Number Mnemonic unctio 15 REN Refresh Control Unit Enable This bit enables or disables the refresh control unit 0 Disables refresh control unit 1 Enables refresh control unit 14 10 Reserved These bits are undefined for compatibility with future devices do not modify these bits 9 0 CV9 0 Counter Value These read only bits represent the current value of the interval counter Write operations to these bits have no effect D 55 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel D 56 SCRn Scratch Pad SCRO SCR1 SCRO SCR1 Expanded Addr FAFFH F8FFH read write ISA Addr O3FFH 02FFH Reset State XXH XXH 7 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SPO Bit Bit 5 Number Mnemonic Function 7 0 SP7 0 Writing and reading this register has no effect on SIOn operation D 56 intel SYSTEM REGISTER QUICK REFERENCE D 57 SIOCFG SIO and SSIO Configuration Expanded Addr F836H SIOCFG ISA Addr read write Reset State 00H 7 0 S1M SOM SSBSRC S1BSRC SOBSRC Bit Bit Functi Number Mnemonic Menon 7 S1M SIO1 Modem Sign
6. DMAGRPMSK ISA Addr 000FH read write Reset State 03H 7 0 HRM1 HRMO Bit Bit Number Mnemonic Function 7 2 Reserved These bits are undefined for compatibility with future devices do not modify these bits 1 HRM1 Hardware Request Mask 1 0 Channel 1 s hardware requests are not masked 1 Masks disables channel 1 s hardware requests When this bit is set channel 1 can still receive software requests 0 HRMO Hardware Request Mask 0 0 Channel 0 s hardware requests are not masked 1 Masks disables channel 0 s hardware requests When this bit is set channel 0 can still receive software requests intel D 14 DMAIEN SYSTEM REGISTER QUICK REFERENCE DMA Interrupt Enable DMAIEN Expanded Addr ISA F01CH Addr read write Reset State 00H 7 0 EE TC1 TCO Bit Bit Number Mnemonic Function 7 2 Reserved These bits are undefined for compatibility with future devices do not modify these bits 1 TC1 Transfer Complete 1 0 Disables Transfer Complete interrupts 1 Connects channel 1 s transfer complete signal to the interrupt control unit s DMAINT input Note When channel 1 is in chaining mode DMACHR 2 1 and DMACHR 0 1 this bitis a don t care 0 TCO Transfer Complete 0 0 Disables Transfer Complete interrupts 1 Connects channel 0 s
7. FaxBack Service et rete pet tle acted Bulletin Board System BBS eese eee CompuServe Forums essem World Wide Web TEGENIGAL SUPPOBRT incitat eyes di ee Renten PRODUCT enn enne CHAPTER 2 ARCHITECTURAL OVERVIEW 2 1 2 2 Intel386 EX EMBEDDED PROCESSOR CORE INTEGRATED PERIPHERALS 5 rettet CHAPTER 3 CORE OVERVIEW 3 1 3 1 1 3 1 2 3 2 3 2 1 3 2 2 3 2 3 3 2 4 3 2 5 3 2 6 3 3 Intel886 CX PROCESSOR System Management Additional Address Lines Intel386 CX PROCESSOR INTERNAL ARCHITECTURE Core Bus esee oct ertet toutes ute Instruction Prefetch Unit Instruction Decode Unit Execution Unit ecce een ee Segmentation UNIT cz aot ser t oder e t og deat Paging Unit ze ew eee es CORE Intel386 EX PROCESSOR CHAPTER 4 SYSTEM REGISTER ORGANIZATION 4 1 4 1 1 4 1 2 4 2 4 3 4 4 4 5 4 5 1 OVERVIEW teh Intel386 Processor Core Architecture Registers Intel38
8. 12 2 3 Starting DMA Transfers eene eene enne 12 9 viii intel CONTENTS 12 2 4 Bus Control Arbitration cesi ec rr rere Fere Pra 12 9 12 2 5 Ending DMA Transfers 12 10 12 2 6 Buffer transfer 12 12 12 2 6 1 Single Buffer Transfer Mode sese eee 12 12 12 2 6 2 Autoinitialize Buffer Transfer Mode 2 12 12 12 2 6 3 Chaining Buffer Transfer Mode sse eene 12 12 12 2 7 Data transfer Modes eme e eee 12 13 12 2 7 1 Single Data transfer Mode 12 14 12 2 7 2 Block Data transfer Mode 2 12 18 12 2 7 3 Demand Data transfer 12 21 12 2 8 Cascade ModE ssi eec ccr are te feet cra ie d e 12 25 12 2 9 DMA Interrupts e er e eee i rr la ee eer evt 12 26 12 2 10 82374 Compatibility i titer e ep reta tete hed tel Ee et 12 27 123 REGISTER 12 28 12 3 1 Pin Configuration Register PINCFG sm 12 31 12 3 2 Configuration Register DMACFG 2 12 32 12 3 8 Channel Registers 12 33 12 3 4 Overflow Enable Register 12 34 12 3 5 Command 1 Register 12 35 12 3 6 Status Register DMASTS 12 36 12 3 7 Command 2 Register
9. 15 14 15 6 1 Refresh Control Unit Example Code 15 14 CHAPTER 16 INPUT OUTPUT PORTS 1621 1 Port F nctionality denti it eet rn iter t 16 2 16 2 REGISTER meme 10 6 16 2 1 Pin Configuration soncni narma aderit ic t eed treu 16 7 16 2 2 Initialization Sequence 16 10 16 3 DESIGN emm 16 10 16 3 1 Pin Status During and After Reset sss eme 16 10 16 4 PROGRAMMING 16 11 16 4 1 WO Ports Code Example 16 11 CHAPTER 17 WATCHDOG TIMER UNIT 17 1 1 WDT Signals cr 17 2 WATCHDOG TIMER UNIT OPERATION EE 17 3 17 2 1 Idle and Powerdown modes sse emen mene enne 17 4 17 2 2 General purpose Timer Mode seem eee emn 4 17 2 8 Software Watchdog Mode sese eem 17 5 17 24 Bus Monitor Mode nne ei e eee ete ied d i Lgs iei eoe 17 5 17 3 DISABLING THE WDT i eere rr erede ttd cr ni cee 17 6 17 4 REGISTER DEFINITIONS prre teret reuerti eene tineis 17 5 DESIGN D712 17 6 PROGRAMMING 17 12 17 6 1 Writing to the WDT Reload Registers WDTRLDH and WDTRLDL 17 12 17 6 2 Minimu
10. Operation Command Word 2 master slave OCW2 master and slave Expanded Addr F020H write only ISA Addr 0020H Reset State XXH XXH 7 0 R SL EOI RSEL1 RSELO L2 L1 LO Bit Bit i Number Mnemonic Function 7 R The Rotate R Specific Level SL and End of Interrupt EOI Bits SL These bits change the priority structure and or send an EOI command EOI R SLEOI Command 000 Cancel automatic rotation 001 Send a nonspecific EOI command 010 No operation 0 1 1 Send a specific EOI command 100 Enable automatic rotation 1 0 1 Enable automatic rotation and send a nonspecific EOI 110 Initiate specific rotation 1 1 1 Initiate specific rotation and send a specific EOI These cases allow you to change the priority structure while the 82C59A is operating in the automatic EOI mode The L2 0 bits see below specify the specific level for these cases 4 3 RSEL1 0 Register Select Bits ICW1 OCW2 and OCWS are accessed through the same addresses The states of RSEL1 0 determine which register is accessed Write 00 to these bits to access OCW2 RSEL1 RSELO 0 0 OCW2 0 1 OCWS 1 X ICW1 2 0 L2 0 IR Level When you program bits 7 5 to initiate specific rotation these bits specify the IR signal that is assigned the lowest level When you program bits 7 5 to send a specific command these bits specify the IR signal that receives the EOI command If SL 0 then these bits have no effect
11. D 40 P1CFG Port 1 Configuration Expanded Addr F820H P1CFG ISA Addr read write Reset State 00H 7 0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PMO Bit Bit Functi Number Mnemonic enon 7 PM7 Pin Mode 0 Selects P1 7 at the package pin 1 Selects HLDA at the package pin 6 PM6 Pin Mode 0 Selects P1 6 at the package pin 1 Selects HOLD at the package pin 5 PM5 Pin Mode 0 Selects P1 5 at the package pin 1 Selects LOCK at the package pin 4 PM4 Pin Mode 0 Selects P1 4 at the package pin 1 Selects RIO at the package pin 3 PM3 Pin Mode 0 Selects P1 3 at the package pin 1 Selects DSRO at the package pin 2 PM2 Pin Mode 0 Selects P1 2 at the package pin 1 Selects DTRO at the package pin 1 PM1 Pin Mode 0 Selects P1 1 at the package pin 1 Selects RTSO at the package pin 0 PMO Pin Mode 0 Selects P1 0 at the package pin 1 Selects DCDO at the package pin D 43 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL D 41 P2CFG Port 2 Configuration Expanded Addr F822H P2CFG ISA Addr read write Reset State 00H 7 0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PMO Bit Bit Functi Number Mnemonic enon 7 PM7 Pin Mode 0 Selects P2 7 at the package pin 1 Selects CTSO at the package pin 6 PM6 Pin Mode 0 Selects P2 6 at the package pin 1 Selects TXDO at the package pin 5 PM5 Pin Mode 0
12. DMA Command 1 Expanded Addr 008 DMACMD1 ISA Addr 0008H write only Reset State 00H 7 0 PRE CE Bit Bit i Number Mnemonic F nction 7 5 Reserved for compatibility with future devices write zeros to these bits 4 PRE Priority Rotation Enable 0 Priority is fixed based on value in DMACMD2 1 Enables the rotation method for changing the bus control priority structure That is after the external bus master or one of the DMA channels is given bus control it is assigned to the lowest priority level Reserved for compatibility with future devices write zero to this bit 2 CE Channel Enable 0 Enables channel 0 and 1 1 Disables the channels 1 0 Reserved for compatibility with future devices write zeros to these bits Figure 12 22 DMA Command 1 Register DMACMD1 12 35 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL In 12 3 6 Status Register DMASTS Use DMASTS to check the status of the channels individually The DMA sets bits in this register to indicate that a channel has a hardware request pending or that a channel s byte count has ex pired DMA Status Expanded Addr 008 DMASTS ISA Addr 0008H read only Reset State 00H 7 R1 RO TC1 TCO Bit Bit Number unctio 7 6 Reserved These
13. Identification Code Register 2027 0013H 3V IDCODE Reset State 2827 0013H 5V 31 24 0 0 1 0 0 3V 0 0 0 1 5V 23 16 0 0 1 0 0 1 1 1 15 8 0 0 0 0 0 0 0 0 7 0 0 0 0 1 0 0 1 1 Bit Bit i Number Mnemonic Funcuon 31 28 V3 0 Device version number 27 12 PN15 0 Device part number 11 1 MFR10 0 Manufacturer identification compressed JEDEC106 A code 0 IDP Identification Present Always true for this device This is the first data bit shifted out of the device during a data scan immediately following an exit from the test logic reset state A one indicates that an IDCODE register is present A zero originates from the BYPASS register and indicates that the device being interrogated has no IDCODE register Figure 18 4 Identification Code Register IDCODE 18 8 intel The boundary scan register BOUND holds data to be applied to the pins or data observed at the pins Each bit corresponds to a specific pin Table 18 5 JTAG TEST LOGIC UNIT Table 18 5 Boundary scan Register Bit Assignments Bit Pin Bit Pin Bit Pin Bit Pin 0 M lO 25 A15 50 TMROUT2 75 P2 2 1 D C 26 A16 CASO 51 TMRGATE2 76 P2 3 2 W R 27 A17 CAS1 52 INT4 TMRCLKO 77 P2 4 3 READY 28 A18 CAS2 53 INTS TMRGATEO 78 DACKO 4 BS8 29 A19 54 INT6 TMRCLK1 79 P2 5 RXDO 5 RD 30 A20 55 INT7 TMRGATE1 80 P2 6 TXDO 6 WR 3
14. nata 6340 6 6 4 Paged DRAM Interface 2 6 43 6 6 5 Non Paged DRAM Interface 2 6 44 CHAPTER 7 SYSTEM MANAGEMENT MODE 7 1 SYSTEM MANAGEMENT MODE OVERVIEW esee 7 1 7 2 SMM HARDWARE INTERFACE essent nennen nennen 7 1 7 2 1 System Management Interrupt Input 2 7 1 7 2 2 SMM Active Output SMIACTH 2 7 2 7 2 3 System Management RAM SMRAM nM Usu 2 7 3 SYSTEM MANAGEMENT MODE PROGRAMMING AND CONFIGURATION PEE 7 3 7 8 1 Register Status During SMM 7 8 7 3 2 System Management 7 4 7 3 2 1 SMI Priority sevens cee 7 3 2 2 System Management Interrupt During HALT Rude eU d 7 8 7 3 2 9 HALT Restart iret etre eR cam ge es ede Re 7 9 7 3 2 4 System Management Interrupt During I O Instruction 7 9 JE OS ac mE 7 10 7 3 3 SMM Handler Interruption 7 10 7 3 3 1 Interrupt During SMM Handler seem menn 7 10 7 3 3 2 During SMM Handler 2 nte etse eut eet eere 7 3 3 3 Mode and Powerdown Mode During SMM m 7 12 7 3 8 8 SMI During SMM Operation 2 meme l2 T34 SMRAM Programming rrt eer etr aeree ied Te e E DE FER Ec ens 7 12 7 3 4 1 Chip select Unit Support for SMRAM 7 12 Intel386 EX MICROPROCESSOR USER S MANUAL
15. est D 4 1 5 CPU Only Reset zio t ete citri Pa de ae hee e ded B 4 B 1 7 Pott Be B 2 SOFTWARE CONSIDERATIONS FOR A PC AT SYSTEM ARCHITECTURE B 5 B 2 1 Embedded Basic Input Output System BIOS BOO B 2 2 Embedded Disk Operating System DOS sess BOO B 2 3 Microsoft WindOoWS etie onte dte dtd eic ae d te ede BOO APPENDIX C EXAMPLE CODE HEADER FILES C 1 REGISTER DEFINITIONS FOR CODE EXAMPLES C 1 C 2 EXAMPLE CODE DEFINES eer tee cene ere ettet dane itera C 6 xii intel APPENDIX D SYSTEM REGISTER QUICK REFERENCE D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 D 12 D 13 D 14 D 15 D 16 D 17 D 18 D 19 D 20 D 21 D 22 D 23 D 24 D 25 D 26 D 27 D 28 D 29 D 30 D 31 D 32 D 33 D 34 D 35 D 36 PERIPHERAL REGISTER TAPS GU Sd ee A A E su oc eer ee etos Dri tee Em GSDABISQOSADI sae Ge E d CSnMSKH UCSMSKE ae tates cete c tlie Nes plo e GSIMISKLQUGSMSKIS EE ea chats t eos oa pue ume a oL eT r DRAN Miata
16. poris Parise NEM Register Name Reset Value F424H Word CS4MSKL 0000H F426H Word CS4MSKH 0000H F428H Word CS5ADL 0000H F42AH Word CS5ADH 0000H F42CH Word CS5MSKL 0000H F42EH Word CS5MSKH 0000H F430H Word CS6ADL 0000H F432H Word CS6ADH 0000H F434H Word CS6MSKL 0000H F436H Word CS6MSKH 0000H F438H Word UCSADL FF6FH F43AH Word UCSADH FFFFH F43CH Word UCSMSKL FFFFH F43EH Word UCSMSKH FFFFH Synchronous Serial I O Unit F480H Word SSIOTBUF 0000H F482H Word SSIORBUF 0000H F484H Byte SSIOBAUD 00H F486H Byte SSIOCON1 COH F488H Byte SSIOCON2 00H F48AH Byte SSIOCTR 00H Refresh Control Unit F4A0H Word RFSBAD 0000H F4A2H Word RFSCIR 0000H F4A4H Word RFSCON 0000H F4A6H Word RFSADD OOFFH Watchdog Timer Unit F4COH Word WDTRLDH 003FH F4C2H Word WDTRLDL FFFFH F4C4H Word WDTCNTH 003FH F4C6H Word WDTCNTL FFFFH F4C8H Word WDTCLR Not a register NOTES 1 Byte pointer in flip flop in DMA determines which register is accessed 2 Shaded rows indicate reserved areas intel SYSTEM REGISTER ORGANIZATION Table 4 2 Peripheral Register Addresses Sheet 5 of 6 pois Nim SENE Register Name Reset Value FACAH Byte WDTSTATUS 00H Asynchronous Serial I O Channel 0 1 FAF8H 03F8H Byte RBRO TBRO DLLO XX XX 02H FAF9H 03F9H Byte IERO DLHO 00H 00H FAFAH Byte IIRO 01H F4FBH 03FBH Byte LCRO 00H F4FCH
17. ae 10320 10 3 1 Configuring the Input and Output Signals T 10 20 10 3 1 1 Hardware Control of GATEN eee neni 10 20 10 3 1 2 Software Control of GATEN 10 20 10 9 2 lnitializing the Counters irent a ee 10 24 10 3 8 Writing the Counters siini a an nd ero a erede rtis 10 26 10 3 4 Reading the Counler er nee itti tee ne dee ret ni 10 27 10 3 4 1 Simple Read n ica n e nr eer ec icing e ER 10 27 10 3 4 2 Counter latch Command sss eee nnne 10 27 10 3 4 3 Read back Command sess eene emen 10 30 10 4 PROGRAMMING 10 33 10 4 1 Timer Counter Unit Code Examples eee mmmIIOl 0 94 vii Intel386 EX MICROPROCESSOR USER S MANUAL intel CHAPTER 11 ASYNCHRONOUS SERIAL UNIT TTA IGM ALS x si itr E tete ER 11 2 1 Baud rate Generator 11 2 2 SION TT1 2 3 Receiver zer ere REM DIR 11 2 4 Modem Control 11 2 5 Diagnostic Mode 11 2 6 SIO Interrupt DMA Soureee EE 11 2 6 1 SIO Interrupt Sources sees rene 1 11 2 6 SIO DMA sources 11 2 7 External UART Support 2 1 11 8 REGISTER DEFINITIONS 11 3 1 Pin and Port Go lia ratio
18. Initialization Command Word 3 Expanded Addr FOA1H ICW3 slave ISA Addr 00A1H write only Reset State XXH 7 0 0 0 0 o o 0 1 Function 7 2 Clear these bits to guarantee device operation 1 Set this bit to guarantee device operation 0 Clear this bit to guarantee device operation Figure 9 11 Initialization Command Word 3 Register ICW3 Slave 9 23 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL 9 3 6 Use ICWA to select the special fully nested mode or the fully nested mode and to enable the au tomatic EOI mode intel Initialization Command Word 4 ICW4 Initialization Command Word 4 master slave ICWA master and slave Expanded Addr F021H FOA1H write only ISA Addr 0021H 00 1 Reset State XXH XXH 7 0 0 0 0 SFNM 0 1 Bit Bit z Number Mnemonic Function 7 5 Write zero to these bits to guarantee device operation 4 SFNM Special fully Nested Mode 0 Selects fully nested mode 1 Selects special fully nested mode Only the master 82C59A can operate in special fully nested mode 3 2 Write zero to these bits to guarantee device operation 1 Automatic Mode 0 Disables automatic EOI mode 1 Enables automatic EOI mode Only the master 82C59A can operate in automatic EOI mode 0 Write one to this bit to guarantee device operation 9 24 Figu
19. fo OMACHA A MEL DN M D ELM MULA DMACMDIS d Mate on 2 DEL LER e OE DE A DMAMSK DMAnBYCn DMAnREQn AND DMATTARn tee DMADVEE GO e a ph UL aM UE D E s A Ria lie a UL ML DIAS SS Un es e rio cte la rae at ICW1 MASTER AND SLAVE ces ICW2 MASTER AND SLAVE ces ICW3 MASTERY ext cama ena sera aa o ETT ae thea agen ICW4 MASTER AND SLAVE ces DODE se et lobe nal Et be HA Ic e Lue MCCC C M goce ae IR CONTENTS xiii Intel386 EX MICROPROCESSOR USER S MANUAL D 37 D 38 D 39 D 40 D 41 D 42 D 43 D 44 D 45 D 46 D 47 D 48 D 49 D 50 D 51 D 52 D 53 D 54 D 55 D 56 D 57 D 58 D 59 D 60 D 61 D 62 D 63 D 64 D 65 D 66 D 67 D 68 D 69 D 70 D 71 D 72 D 73 D 74 xiv POLL MASTER AND SLAVE itii eren tee tee xe spen de ell p SIOGEQ M rd MM LATE SSIOTBUE ten tee e deer endete te tua c TR E 5 PC UC
20. 12 4 DESIGN CONSIDERATIONS EOP requires an external pull up resistor To determine the maximum value the rise time must be less than three bus cycles To determine the minimum value use the Ip specification from the Intel3861M EX Embedded Microprocessor datasheet order number 272420 12 5 PROGRAMMING CONSIDERATIONS Consider the following when programming the DMA The DMA transfers data between a requester and a target The transfer direction is programmable and determines whether the requester or the target is the source or destination of a transfer The two cycle data transfer bus cycle option uses a four byte temporary buffer During a buffer transfer the channel fills the temporary buffer from the source before writing any data to the destination Therefore the number of bus cycles that it takes to transfer data from the source to the destination depends on the amount of data to transfer and the source and destination data bus widths Each channel contains a 26 bit requester address 26 bit target address and 24 bit byte count These values are programmed through the use of 8 bit registers some of which are multiplexed at the same addresses A byte pointer BP controls the access to these multiplexed registers After you write or read a register that requires a byte pointer specification the channel toggles the byte pointer For example writing to DMAOTARO 12 50 intel DMA CONTROLLER with BP 0 cause
21. MCRO 00H FAFDH O3FDH Byte LSRO 60H FAFEH O3FEH Byte MSRO FAFFH O3FFH Byte SCRO XX Clock Generation and Power Management F800H Byte PWRCON 00H F804H Word CLKPRS 0000H Device Configuration Registers F820H Byte P1CFG 00H F822H Byte P2CFG 00H F824H Byte P3CFG 00H F826H Byte PINCFG 00H F830H Byte DMACFG 00H F832H Byte INTCFG 00H F834H Byte TMRCFG 00H F836H Byte SIOCFG 00H Parallel I O Ports F860H Byte P1PIN XX F862H Byte P1LTC FFH F864H Byte P1DIR FFH F868H Byte P2PIN XX F86AH Byte P2LTC FFH F86CH Byte P2DIR FFH F870H Byte P3PIN XX F872H Byte P3LTC FFH F874H Byte P3DIR FFH NOTES 1 Byte pointer in flip flop in DMA determines which register is accessed 2 Shaded rows indicate reserved areas 4 19 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Table 4 2 Peripheral Register Addresses Sheet 6 of 6 intel pinnis NEM Register Name Reset Value Asynchronous Serial I O Channel 1 COM2 F8F8H 02F8H Byte RBR1 TBR1 DLL1 XX XX 02H F8F9H 02F9H Byte IER1 DLH1 00H 00H F8FAH 02FAH Byte IR 1 01H F8FBH 02FBH Byte LCR1 00H F8FCH 02FCH Byte MCR1 00H F8FDH 02FDH Byte LSR1 60H F8FEH 02 MSR1 F8FFH 02 Byte SCR1 XX NOTES 1 Byte pointer in flip flop in DMA determines which register is accessed 2 Shaded rows indicate reserved areas 4 20 intel DEVICE CONFIGURATION CHAPTER 5 DEVICE CONFIGURATION The Intel386
22. Figure 14 8 Chip select High Mask Registers CSnMSKH UCSMSKH 14 19 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL In tel Chip select Low Mask Expanded Addr F404H F40CH CSnMSKL n 0 6 UCSMSKL F414H F41CH read write F424H F42CH F434H F43CH ISA Addr Reset State 0000H CSnMSKL FFFFH UCSMSKL 15 8 CM5 CM4 CM3 CM2 CM1 CMSMM 7 0 ER m CSEN Bit Bit Number Mnemonic Function 15 11 CM5 1 Chip select Mask Value Lower Bits Defines the lower 5 bits of the channel s 15 bit mask The mask bits CM5 1 and the address bits CA5 1 form a masked address that is compared to memory address bits A15 11 or I O address bits A5 1 10 CMSMM SMM Mask Bit 0 The SMM address bit is not masked 1 Masks the SMM address bit in the channel s Chip Select Low Address register When the SMM address bit is masked an address match activates the chip select regardless of whether the processor is in SMM 9 1 Reserved for compatibility with future devices write zeros to these bits 0 CSEN Chip select Enable 0 Disables the chip select channel 1 Enables the chip select channel Figure 14 9 Chip select Low Mask Registers CSnMSKL UCSMSKL 14 20 intel CHIP SELECT UNIT 14 5 DESIGN CONSIDERATIONS When designing with the CSU consider the following Upon reset UCS is configured as a 16 bit chip select sig
23. D 41 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 0 39 OCW3 MASTER AND SLAVE Operation Command Word 3 master slave OCW3 master and slave Expanded Addr F020H FOAOH write only ISA Addr 0020H OOAOH Reset State XXH XXH 7 0 0 ESMM SMM RSEL1 RSELO POLL ENRR RDSEL Bit Bit Function Number Mnemonic Clear this bit to guarantee device operation ESMM Enable Special Mask Mode ESMM and Special Mask Mode SMM SMM Use these bits to enable or disable special mask mode ESMM SMM 0 0 No action 0 1 No action 1 0 Disable special mask mode 1 1 Enable special mask mode 4 3 RSEL1 0 Register Select ICW1 OCW2 and OCWS are accessed through the same addresses The states of RSEL1 0 determine which register is accessed Write 01 to these bits to access OCW3 RSEL1 RSELO 0 0 OCW2 0 1 OCWS 1 X ICW1 2 POLL Poll Command Set this bit to issue a poll command thus initiating the polling process 1 ENRR Enable Register Read Select ENRR and Read Register Select RDSEL 0 RDSEL These bits select which register is read during the next FO20H FOAOH or PC AT address 0020 00 read access ENRR RDSEL Register Read on Next Read Pulse 0 0 No action 0 1 No action 1 0 Interrupt Request Register 1 1 In service Register D 42 intel SYSTEM REGISTER QUICK REFERENCE
24. Pac od 5 SEB ___ 8580 2 o _ 2 A EL amp ort amp 5 a F o is 4 CLK2 CLKOUT A25 1 BLE D Cst Valid 4 Valid 2 Valid 1 M IO REFRESH W R WR RD ADS NA READY LBA BS8 LOCK D15 0 A2305 02 Figure 6 1 Basic External Bus Cycles 6 6 intel BUS INTERFACE UNIT 6 2 4 Bus States The processor uses a double frequency clock input CLK2 This clock is internally divided by two and synchronized to the falling edge of RESET see Figure 8 2 in Chapter 8 to generate the internal processor clock signal Each processor clock cycle is two CLK2 cycles wide Each bus cycle is composed of at least two bus states T1 and T2 Each bus state in turn consists of two CLK2 cycles which can be thought of as Phase 1 PH1 and Phase 2 PH2 of the bus state External circuitry can use the CLKOUT signal generated by the processor to synchronize itself with the processor This signal is a replica of the PHIP clock which is the PHI clock that is used by the internal peripherals For more information refer to Chapter 8 CLOCK AND POWER MANAGEMENT UNIT The CLKOUT signal is used as a phase status indicator for external circuitry All device inputs are sampled and outputs are activated at CLK2 rising edges This makes synchronous circuit design easy through the use of rising edge triggered
25. ES gt A gt E B B go P 5 og gt v 230m 8 lt lt o T Valid 2 LOCK 75 01 c c ait z 1 amp L 5 j 10 12 t ai eJ ee 2 O t a Figure 6 13 16 bit Cycles to 8 bit Devices Using BS8 6 33 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 64 BUSLOCK Inasystem in which more than one device a bus master may control the local bus locked cycles are used to make sequential bus cycles indivisible Otherwise the cycles may be separated by a cycle from another bus master Any bus cycles that must be performed back to back without any intervening bus cycles by other bus masters must be locked The use of a semaphore is one example of this concept The value of a semaphore indicates a condition such as the availability of a device If the CPU reads a sema phore to determine that a device is available then writes a new value to the semaphore to indicate that it intends to take control of the device the read cycle and write cycle should be locked to prevent another bus master from reading from or writing to the semaphore in between the two cycles The LOCK output indicates to the other bus masters that they may not gain control of the bus In addition when LOCK is asserted the processor does not recognize HOLD request from an other bus master
26. 12 23 Demand Data transfer Mode with Chaining Buffer transfer Mode 12 24 Cascade Mode nece ee uade ette ete E 12 26 Pin Configuration Register eem emm 12 31 DMA Configuration Register DMACFG eee eee 12 32 DMA Channel Address and Byte Count Registers DMAnREQn DMAnTARn DMAnBYOn sese 12 33 DMA Overflow Enable Register 12 34 DMA Command 1 Register em 12 35 DMA Status Register 12 36 DMA Command 2 Register em eene 12 37 DMA Mode 1 Register 1 12 39 DMA Mode 2 Register DMAMOD2 12 41 DMA Software Request Register DMASRR write format 12 42 DMA Software Request Register DMASRR read format 12 43 DMA Channel Mask Register 12 44 DMA Group Channel Mask Register DMAGRPMSK 12 45 DMA Bus Size Register 12 46 DMA Chaining Register 12 47 DMA Interrupt Enable Register 12 48
27. Figure 14 1 Channel Address Comparison Logic The lower address bits are excluded from address comparisons only 15 bits are compared For memory addresses which have 26 bit addresses the minimum channel address block size is 2 Kbytes for I O addresses with 16 bit addresses the minimum channel address block size is 2 bytes NOTE The starting address of any channel address block must be a multiple of the block size For example a 256 Kbyte block can only start at an address that is a multiple of 256 Kbytes 0H 4000H 8000H etc Because you can set ones in the channel mask to exclude certain address bits from comparisons you can increase the size of a channel s address block by powers of 2 in Kbytes for memory ad dresses and by powers of 2 in bytes for I O addresses Figure 14 2 illustrates how memory ad dress block sizes are determined from the channel s mask the concept is the same for I O address block sizes replace Kbyte with byte As shown in Figure 14 2 the bit location of the right most zero in the channel mask determines the channel s active address block size 14 3 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 15 bit Channel Mask Block Size 15 1 2 2 koyte EXIXTXIXIXTXTXTXIXTXTXTXTXTo T1 7 4 Kbyte EXIXPXIXIXTXIXTXIXTXIXNTXTOTE T 2 21 32768 kbyte 16 2 65536 Kbyte A2534 01 Figure 14 2 Determining a Cha
28. 5 25 5 17 Port 2 Configuration Register P2CFQG sse ene 5 26 5 18 Port Configuration Register nen ene 5 27 6 1 Basic External Bus Cycles 66 6 2 Simplified Bus State Diagram Does Not Include Address Pipelining c or r Hold states 6 8 6 3 Ready LOGIC tre e rep tee etl RAE ERE Seiad acne 6 11 6 4 Basic Internal and External Bus 0 12 6 5 Nonpipelined Address Read Cycles sese 6 15 6 6 Nonpipelined Address Write 6 18 6 7 Complete Bus States Including Pipelined 6 20 6 8 Pipelined Address 6 21 6 9 Interrupt Acknowledge 6 25 6 10 tret aed 6 27 6 11 Basic Refresh Cycle sed tib eere A AE er 6 29 6 12 Refresh Cycle During 6 30 6 13 16 bit Cycles to 8 bit Devices Using 8 6 33 6 14 LOCK Signal During Address Pipelining 0 85 6 15 Intel386 EX Processor to Intel387 SX Math Coprocessor 6 39 xvi intel CONTENTS Figure 6 16 6 17 6 18 6 19 7 1 7 8 7
29. TC1 TCO Bit Number Bit Mnemonic Function 7 6 Reserved These bits are undefined 5 R1 Request 1 When set this bit indicates that channel 1 has a hardware request pending When the request is removed this bit is cleared 4 RO Request 0 When set this bit indicates that channel 0 has a hardware request pending When the request is removed this bit is cleared 3 2 Reserved These bits are undefined 1 TC1 Transfer Complete 1 When set this bit indicates that channel 1 has completed a buffer transfer either its byte count expired or it received an input Reading this register clears this bit and clears TC1 in DMAIS 0 TCO Transfer Complete 0 When set this bit indicates that channel 0 has completed a buffer transfer either its byte count expired or it received an EOP input Reading this register clears this bit and clears TCO in DMAIS D 27 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel D 23 ICW1 MASTER AND SLAVE Initialization Command Word 1 master slave ICW1 master and slave Expanded Addr F020H write only ISA Addr 0020H OOAOH Reset State XXH XXH 7 0 0 0 0 RSEL1 LS 0 0 1 Bit Bit Number Mnemonic Function 7 5 Clear these bits to guarantee device operation 4 RSEL1 Register Select 1 Also see OCW2 and OCW3 ICW1 OCW2 and OCW3 are accessed through the same addresses 0 OCW2 or OCWS is a
30. 7 3 Reserved These bits are undefined for compatibility with future devices do not modify these bits 2 AUTOTXM Automatic Transmit off mode for master mode 0 Clearing this bit puts the TEN bit into normal operation 1 Setting this bit and the TXMM bit causes TEN to be ignored Every time a word is loaded into the transmit shift register from the transmit holding buffer it is transmitted out and then stops 1 TXMM Transmit Master Mode 0 Clearing this bit puts the transmitter in slave mode In slave mode an external device controls the transmit serial communications An input on the STXCLK pin clocks the transmitter 1 Setting this bit puts the transmitter in master mode In master mode the internal baud rate generator controls the transmit serial communications The baud rate generator s output clocks the internal transmitter and appears on the STXCLK pin 0 RXMM Receive Master Mode 0 Clearing this bit puts the receiver in slave mode In slave mode an external device controls the receive serial communications An input on the SRXCLK pin clocks the receiver 1 Setting this bit puts the receiver in master mode In master mode the internal baud rate generator controls the receive serial communications The baud rate generator s output clocks the internal receiver and appears on the SRXCLK pin D 60 intel D 61 SSIOCTR SYSTEM REGISTER QUICK REFERENCE
31. 15 REN Refresh Control Unit Enable This bit enables or disables the refresh control unit 0 Disables refresh control unit 1 Enables refresh control unit 14 10 Reserved These bits are undefined for compatibility with future devices do not modify these bits 9 0 CV9 0 Counter Value These read only bits represent the current value of the interval counter Write operations to these bits have no effect Figure 15 3 Refresh Control Register RFSCON 15 8 intel REFRESH CONTROL UNIT 15 4 3 Refresh Base Address Register RFSBAD Use RFSBAD to set up the memory region that needs refreshing The value written to this register forms the upper bits A25 14 of the refresh address The RFSBAD register can be used in con junction with the Chip Select Unit CSU to generate a chip select for the DRAM region during refresh cycles If the address in the RFSBAD matches the region programmed in the CSU for DRAM then the DRAM chip select is generated for both access and refresh cycles By programming two separate regions in the CSU one for DRAM access cycles and the other for DRAM refresh cycles separate chip selects can be generated for the two types of cycles In this case the RFSBAD needs to be programmed with an address that matches the CSU region that is programmed for the refresh cycle chip select Refresh Base Address Expanded Addr F4A0H RFSBAD I
32. DMA Software Request read format Expanded Addr 009 DMASRR ISA Addr 0009H Reset State 00H 7 0 SR1 SRO Bit Bit Number Mnemonic Runerion 7 2 Reserved These bits are undefined for compatibility with future devices do not modify these bits 1 SR1 Software Request 1 When set this bit indicates that channel 1 has a software request pending 0 SRO Software Request 0 When set this bit indicates that channel 0 has a software request pending Figure 12 28 DMA Software Request Register DMASRR read format 12 43 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 12 3 11 Channel Mask and Group Mask Registers DMAMSK and DMAGRPMSK Use the DMAMSK and DMAGRPMSK registers to disable mask or enable channel hardware requests DMAMSK allows you to disable or enable hardware requests for only one channel at a time while DMAGRPMSK allows you to disable or enable hardware requests for both channels at once NOTE Each mask bit is set when its associated channel produces an End of Process if the channel is not programmed for Autoinitialize Software must then clear the appropriate mask bit to allow further DREQn requests from initiating transfers DMA Individual Channel Mask Expanded Addr DMAMSK ISA Addr 000AH write only Reset State 04H 7 0 HRM 0 CS Bit Bit Number Mnemonic Function 7 3
33. If 0 using PSCLK therefore set PreScale if GetEXRegByte SIOCFG amp BIT2MSK 0 _SetEXRegByte CLKPRS PreScale 13 27 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Init Baud Rate Generator _SetEXRegByte SSIOBAUD BaudValue SetEXRegByte SSIOCON1 Mode _SetEXRegByte SSIOCON2 MasterTxRx 1 1 5 5 0 BRK IK KK IKK IK IRR KIA ARR IRR IRR IR IR IRR A AIR II I k k k k k k k SSerialReadWord Description Is a Polled serial port read function that will wait forever or until a character has been received from the serial port Parameters MasterSlave Defines if receiver is in Master or Slave mode Returns Word read from serial port Assumptions In Slave Mode receiver must be enabled prior to this function call Syntax define SSIO RX MASTR 0x1 define SSIO_RX_SLAVE 0x0 WORD character character SSerialReadWord SSIO_RX_MASTR Real Protected Mode No changes required eK RR A A RR RRA RR IR AIA ARR IR AA WORD SSerialReadWord BYTE MasterSlave register BYTE SSControl if MasterSlave SSIO RX MASTR Save Control Register SSControl _GetEXRegByte SSIOCON1 Get Control Register Ready to disable SSControl amp SSIO_RX_ENAB Clear the bit Enable Receiver _SetEXRegByte SSIOCON1 SSControl SSIO_RX_ENAB Wait until Receive Holding Buffer is Full while GetEXRegByte SSIOCON1 amp SSIO RHBF
34. Reserved for compatibility with future devices write zero to this bit 2 CE Channel Enable 0 Enables channel 0 and 1 1 Disables the channels 1 0 Reserved for compatibility with future devices write zeros to these bits intel SYSTEM REGISTER QUICK REFERENCE D 12 DMACMD2 DMA Command 2 Expanded Addr F01AH DMACMD2 ISA Addr write only Reset State 08H 7 0 PL1 PLO ES DS Bit Bit Number Mnemonic Function 7 4 Reserved for compatibility with future devices write zeros to these bits 3 2 PL1 0 Low Priority Level Set Use these bits to assign a particular bus request to the lowest priority level in fixed priority mode 00 Assigns channel 0 s request DREQO to the lowest priority level 01 Assigns channel 1 s request DREQ1 to the lowest priority level 10 Assigns the external bus master request HOLD to the lowest priority level 11 Reserved 1 ES EOP Sampling 0 Causes the DMA to sample the EOP input asynchronously 1 Causes the DMA to sample the end of process EOP input synchronously 0 DS DREQn Sampling 0 Causes the DMA to sample the DREQn inputs asynchronously 1 Causes the DMA to sample the channel request DREQn inputs synchronously Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel D 13 DMAGRPMSK DMA Group Channel Mask Expanded Addr FOOFH
35. S1R SOR ISR IMR DR TR Bit Bit i Number Mnemonic Function 15 ESE 0 Disables expanded I O space 1 Enables expanded I O space 14 7 Reserved 6 S1R 0 Makes serial channel 1 COM2 accessible in both DOS I O space and expanded I O space 1 Remaps serial channel 1 COM2 address into expanded I O space 5 SOR 0 Makes serial channel 0 COM1 accessible in both DOS I O space and expanded I O space 1 Remaps serial channel 0 COM1 address into expanded I O space 4 ISR 0 Makes the slave 82C59A interrupt controller accessible in both DOS space and expanded I O space 1 Remaps slave 82C59A interrupt controller address into expanded space 3 IMR 0 Makes the master 82C59A interrupt controller accessible in both DOS I O space and expanded I O space 1 Remaps master 82C59A interrupt controller address into expanded space 2 DR 0 Makes the DMA address accessible in both DOS I O space and expanded I O space 1 Remaps DMA address into expanded I O space 1 Reserved 0 TR 0 Makes the timer control unit accessible in both DOS I O space and expanded I O space 1 Remaps timer control unit address into expanded I O space Figure 4 3 Address Configuration Register REMAPCFG Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 4 5 2 Enabling and Disabling the Expanded I O Space The Intel386 EX processor s expanded I O space is enabled by a specific write sequence to I O addresses 22H
36. Transmit Holding Buffer SSIOTBUF Expanded Addr F480H ISA Addr read write Reset State 0000H 15 8 15 14 TB13 TB12 TB11 TB10 TB9 TB8 7 0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TBO Bit Bit Number Mnemonic Function 15 0 15 0 Transmit Buffer Bits These bits make up the next data word to be transmitted The control logic loads this word into the transmit shift register The transmit shift register shifts the bits out on the falling edge of the tranmitter clock pin The word is transmitted out starting with the most significant bit TB15 13 24 Figure 13 22 SSIO Transmit Holding Buffer SSIOTBUF intel SYNCHRONOUS SERIAL I O UNIT 13 3 9 SSIO Receive Holding Buffer SSIORBUF Read SSIORBUF to obtain the last data word received Use the interrupt controller DMA unit or polling read SSIOCONI to determine when to read the receive buffer Receive Holding Buffer Expanded Addr F482H SSIORBUF ISA Addr read only Reset State 0000H 15 8 15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 7 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RBO Bit Bit Number Mnemonic Function 15 0 RB15 0 Receive Buffer Bits This register contains the last word received The receive shift register shifts bits in with the rising edge of the receiver clock pin Data is shifted in starting with the most significant bit The control logic then transfe
37. read write Reset State 00H 7 0 WDTRDY HSREADY PC1 PCO Bit Bit Number Mnemonic Function 7 4 Reserved These bits are undefined for compatibility with future devices do not modify these bits 3 WDTRDY Watch Dog Timer Ready 0 An external READY must be generated to terminate the cycle when the WDT times out in Bus Monitor Mode 1 Internal logic generates READY to terminate the cycle when the WDT times out in Bus Monitor Mode 2 HSREADY Halt Shutdown Ready 0 An external ready must be generated to terminate HALT Shutdown cycle 1 Internal logic generates READY to terminate a HALT Shutdown cycle 1 0 PC1 0 Power Control Program these bits then execute a HALT instruction The device enters the programmed mode when READY internal or external terminates the halt bus cycle When these bits have equal values the HALT instruction causes a normal halt and the device remains in active mode PC1 PCO 0 0 active mode 1 0 idle mode 0 1 powerdown mode 1 1 active mode Figure 17 5 Power Control Register 17 11 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 17 5 DESIGN CONSIDERATIONS This section outlines design considerations for the watchdog timer unit Depending on the system configuration a WDT timeout can cause a maskable interrupt a non maskable interrupt or a system reset Maskable interrupt The WDT timeout signal is
38. 0 PMO Pin Mode 0 Selects P2 0 at the package pin 1 Selects CSO at the package pin Figure 11 9 Port 2 Configuration Register P2CFG 11 19 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Use P3CFG bit 7 to connect the COMCLK pin to the package pin Port 3 Configuration Expanded Addr F824H P3CFG ISA Addr read write Reset State 00H 7 PM7 PM6 5 2 1 Bit Bit Number Mnemonic Function 7 PM7 Pin Mode 0 Selects P3 7 at the package pin 1 Selects COMCLK at the package pin 6 6 Pin Mode 0 Selects P3 6 at the package pin 1 Selects PWRDOWN at the package pin 5 PM5 Pin Mode 0 Selects P3 5 at the package pin 1 Connects master IR7 to the package pin INT3 4 PM4 Pin Mode 0 Selects P3 4 at the package pin 1 Connects master IR6 to the package pin INT2 3 PM3 Pin Mode 0 Selects P3 3 at the package pin 1 Connects master IR5 to the package pin INT1 2 PM2 Pin Mode 0 Selects P3 2 at the package pin 1 Connects master IR1 to the package pin INTO 1 PM1 Pin Mode See Table 5 1 on page 5 8 for all the PM1 configuration options 0 PMO Pin Mode See Table 5 1 on page 5 8 for all the PMO configuration options 11 20 Figure 11 10 Port 3 Configuration Register P3CFG intel ASYNCHRONOUS SERIAL UNIT 11 3 2 S
39. Bit Bit Number Mnemonic 7 TMRDIS Timer Disable 0 Enables the CLKINn signals 1 Disables the CLKINn signals 6 SWGTEN Software GATEn Enable 0 Connects GATEn to either the Voc pin or the TMRGATEn pin 1 Enables GT2CON GT1CON and GTOCON to control the connections to GATE2 GATE1 and GATEO respectively Function 5 GT2CON Gate 2 Connection SWGTEN GT2CON 0 0 Connects GATE2 to 0 1 Connects GATE2 to the TMRGATE2 pin 1 0 Turns GATE2 off 1 1 Turns GATE2 on 4 CK2CON Clock 2 Connection 0 Connects CLKIN2 to the internal PSCLK signal 1 Connects CLKIN2 to the TMRCLK pin 3 GT1CON Gate 1 Connection SWGTEN GT1CON 0 0 Connects GATE1 to Vec 0 1 Connects GATE1 to the TMRGATE1 pin 1 0 Turns GATE1 off 1 1 Turns GATE1 on 2 CK1CON Clock 1 Connection 0 Connects CLKIN1 to the internal PSCLK signal 1 Connects CLKIN1 to the TMRCLK1 pin 1 GTOCON Gate 0 Connection SWGTEN GTOCON 0 0 Connects GATEO to Voc 0 1 Connects GATEO to the TMRGATE1 pin 1 0 Turns GATEO off 1 1 Turns GATEO on 0 CKOCON Clock 0 Connection 0 Connects CLKINO to the internal PSCLK signal 1 Connects CLKINO to the TMRCLKO pin Figure 10 22 Timer Configuration Register TMRCFG 10 21 Intel386 EX EMBEDDED PROCESSOR USER S MANUAL intel The peripheral pin selection registers P3CFG and PINCFG determine whether each counter s OUTn signal is connected to its TMROUT p
40. A single multiplexer can be used instead of the separate row and column address buffers Row Row Address Upper Address Addr ss EER Buffer OE_ROW REFRESH Adress seen ears gt RAS Paged Intel3867M EX di DRAM Embedded Processor CAS OE_COL Address Lower Address Buffer Column Address Note A single mux can be used in place of the row and column address buffers A3264 02 Figure 6 18 Intel386 EX Processor to Paged DRAM Interface 6 43 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 6 6 5 DRAM Interface This interface is similar to the Paged DRAM Interface except that in this case the lower address bits are routed to the Row Address Buffer and the higher address bits to the Column Address Buffer This is done to simplify the RAS Only Refresh logic The PLD in this case enables the Row Address Buffer and asserts the RAS signal shaded sections in the figure during a Refresh Cycle Refer to Chapter 15 REFRESH CONTROL UNIT for more information A single multiplexer can be used instead of the separate row and column address buffers Row Lower Address Row Address Address Buffer OE ROW REFRESH gt RAS Non paged Intelg86 EX x DRAM Embedded Processor CAS gt OE_COL Upper Address Column Address Note A single mux can be used in place of
41. Bit Number Bit Mnemonic Function 7 TMRDIS Timer Disable 0 Enables the CLKINn signals 1 Disables the CLKINn signals SWGTEN Software GATEn Enable 0 Connects GATEn to either the Voc pin or the TMRGATEn pin 1 Enables GT2CON GT1CON and GTOCON to control the connections to GATE2 GATE1 and GATEO respectively GT2CON Gate 2 Connection SWGTEN GT2CON 0 0 Connects GATE2 to 0 1 Connects GATE2 to the TMRGATE2 pin 1 0 Turns GATE2 off 1 1 Turns GATE2 on CK2CON Clock 2 Connection 0 Connects CLKIN2 to the internal PSCLK signal 1 Connects CLKIN2 to the TMRCLK pin GT1CON Gate 1 Connection SWGTEN GT1CON 0 0 Connects GATE1 to Voc 0 1 Connects GATE1 to the TMRGATE1 pin 1 0 Turns GATE1 off 1 1 Turns GATE1 on CK1CON Clock 1 Connection 0 Connects CLKIN1 to the internal PSCLK signal 1 Connects CLKIN1 to the TMRCLK1 pin GTOCON Gate 0 Connection SWGTEN GTOCON 0 0 Connects GATE to Voc 0 1 Connects GATEO to the TMRGATE1 pin 1 0 Turns GATEO off 1 1 Turns GATEO on CKOCON Clock 0 Connection 0 Connects CLKINO to the internal PSCLK signal 1 Connects CLKINO to the TMRCLKO pin Figure 5 7 Timer Configuration Register TMRCFG 5 13 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 5 2 4 Asynchronous Serial I O Configuration Figures 5 8 and 5 9 show the asynchronous seria
42. EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 12 3 9 Mode 2 Register DMAMOD2 Use DMAMOD2 to select the data transfer bus cycle option specify whether the requester and target are in memory or I O and determine whether the DMA modifies the target and requester addresses If you set up the DMA to modify the requester address use DMAMOD2 to determine whether the DMA increments or decrements the requester address during a buffer transfer 12 40 intel DMA CONTROLLER DMA Mode 2 Expanded Addr F01BH DMAMOD2 ISA Addr write only Reset State 00H 7 0 BCO RD TD RH RI TH 0 CS Bit Bit i Number Mnemonic Function 7 BCO Bus Cycle Option 0 Selects the fly by data transfer bus cycle option for the channel specified by bit 0 1 Selects the two cycle data transfer bus cycle option for the channel specified by bit 0 6 RD Requester Device Type 0 Clear this bit when the requester for the channel specified by bit 0 is in memory space 1 Setthis bit when the requester for the channel specified by bit 0 is in I O space This bit is ignored if BCO is cleared 5 TD Target Device Type 0 Clear this bit when the target for the channel specified by bit 0 is in memory space 1 Setthis bit when the target for the channel specified by bit 0 is in space 4 RH Requester Address Hold 0 Causes the address to be modified incremented or decremented depending on DMAMO
43. Figure 6 6 Nonpipelined Address Write Cycles 6 18 intel BUS INTERFACE UNIT 6 3 8 Pipelined Cycle The pipelining feature of the processor is normally used to achieve zero wait state memory sub systems using devices that are slower than those in a zero wait state non pipelined system Pipe lining allows bus cycles to be overlapped increasing the amount of time available for the memory or I O device to respond The next address NA input controls pipelining NA is generated by logic in the system to indicate that the address and status buses are no longer needed by the sys tem When pipelining is not desired in a system the NA input should be tied inactive During any particular bus cycle NA is sampled only after the address and status have been valid for one T state the T1P state of pipelined cycles or the first T2 state of nonpipelined cycles and is continuously sampled in each subsequent T state until it is found active or the bus cycle is ter minated In particular NA is sampled at the rising CLK2 edge in the middle of the T state rising edge of Phase 2 When the system is designed to assert NA pipelining may be dynamically requested on a cycle by cycle basis by asserting NA Typically only some devices in a system are pipelined NOTE Asserting the NA pin is a request for pipelining Asserting NA during a bus cycle does not guarantee that the next cycle is pipelined NA is ignored during I O cycles and mus
44. LOOPZ LOOPE loop LUN 114m 114m r with zero equal 1100001 8 bit displacemen LOOPNZ LOOPNE zd 114m 114m f loop while not zero 1100000 8 bit displacemen CONDITIONAL BYTE SET Note Times are register memory SETO set byte on overflow register memory 0000 0010000 mod000r m 4 5 4 5 h SETNO set byte on not overflow register memory 0000 0010001 mod 0 0 0 r m 4 5 4 5 h SETB SETNAE set byte on below not above or equal register memory 0000 0010010 mod000r m 4 5 4 5 h SETNB set byte on below above or equal register memory 0000 0010011 mod 000 r m 4 5 4 5 h SETE SETZ set byte on equal zero register memory 0000 0010100 4000 4 5 4 5 SETNE SETNZ set byte on not equal not zero register memory 0000 0010101 mod 00 0 r m 4 5 4 5 h E 14 intel INSTRUCTION SET SUMMARY Table E 1 Instruction Set Summary Sheet 14 of 19 Clock Count Notes Real Pro Real Pro dress Virtual dress Viral Instruction Format Mode Ad Mode Ad or dress or dress Virtual Mode Virtual Mode 8086 8086 Mode Mode SETBE SETNA set byte on below or equal not above register memory 0000 0010110 mod00 0 r m 4 5 4 5 SETNBE SETA set byte on n
45. Refresh Cascaded cycle is device performed deasserts Refresh 2 DRON Ves request relinquishing bus control Figure 12 17 Cascade Mode 12 2 9 DMA Interrupts Each channel contains two interrupt causing signals chaining status and transfer complete When a channel is configured for the chaining buffer transfer mode the chaining status signal indicates that the channel has started its buffer transfer and new transfer information can be written without affecting the current buffer transfer Once activated the chaining status signal remains active until the most significant byte of the base target address is written or resetting the chaining enable bit The transfer complete status signal indicates that the channel has finished a buffer transfer either the channel s byte count has expired or the buffer transfer was terminated by an EOP input DMACLRTC clears the DMAINT signal going to the Interrupt Control Unit DMACLRTC is executed by writing to location the data written to the location is immaterial writing any data to the location causes the DMA to deactivate the transfer complete status signal 12 26 intel DMA CONTROLLER The four interrupt source signals two per channel are internally connected ORed to the inter rupt request output DMAINT When an interrupt from DMAINT is detected you can determine which signal caused the request by reading the DMA interrupt status registe
46. Syntax Enter Idle Mode Real Protected Mode intel CLOCK AND POWER MANAGEMENT UNIT No changes required eK RR AR IRR KARR IR AA ARR IIR AA Kk void Enter_Idle_Mode void BYTE pwrcon 0x00 pwrcon GetEXRegByte PWRCON clear lowest two bits of pwrcon pwrcon pwrcon amp Oxfc Set mode to idle SetEXRegByte PWRCON pwrcon IDLE call HALT instruction to execute IDLE mode asm HLT Enter Idle Mode IR AR IRR Kk k k Kk Ck kk k kk k k k k k k k k k eek Enter Powerdown Mode Description This function programs the 386EX for Powerdown mode This freezes both the core and peripheral clocks Parameters None Returns None Assumptions None Syntax Enter Powerdown Mode Real Protected Mode No changes required kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk void Enter_Powerdown_Mode void BYTE pwrcon 0x00 pwrcon _GetEXRegByte PWRCON 8 15 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel clear lowest two bits of pwrcon pwrcon pwrcon amp Oxfc Set mode to powerdown SetEXRegByte PWRCON pwrcon PWDWN call HALT instruction to execute POWERDOWN mode asm HLT Enter Powerdown Mode Mode Setting To Active Description This function returns the 386EX to Active mode Thus the next HALT instruction will
47. TIMER COUNTER UNIT 10 1 1 TCU Signals and Registers Table 10 1 and Table 10 2 lists the signals and registers associated with the TCU Table 10 1 TCU Signals Device Pin or Signal Internal Signal Description PSCLK Internal signal Prescaled Clock This is one of the two possible connections for the counter s CLKINn signal PSCLK is an internal signal that is a prescaled value of the processor internal clock The clock and power management unit contains a programmable divider that determines the PSCLK frequency See Controlling the PSCLK Frequency on page 8 7 for information on how to program PSCLK s frequency TMRCLKO Device pin Timer Clock Input TMRCLK1 This is one of the two possible connections for the counter s CLKINn TMRCLK2 signal You can drive a counter with an external clock source by connecting the clock source to the counter s TMRCLKn pin TMRGATEO Device pin Timer Gate Input TMRGATE1 This input can be connected to the counter s GATEn input to control the TMRGATE2 counter s operation In some of the counter s operating modes a high level on GATEn enables or resumes counting while a low level disables or suspends counting In other modes a rising edge on GATEn loads a new count value TMROUTO Device pin Timer Output TMROUT1 The counter s OUT signal can be connected to this pin The operation TMROUT2 and consequently the waveform of the output depends on the counter s
48. TSS via task gate 411 ah kt From Intel386 SX CPU task to virtual 8086 mode via Task Gate 328 g j k r From virtual 8086 mode to 286 TSS via Task Gate 389 g j k r From virtual 8086 mode to Intel 386 SX CPU TSS via task gate 416 g j K r From virtual 8086 mode to privilege level 0 via trap gate or interrupt gate 223 E 16 intel INSTRUCTION SET SUMMARY Table E 1 Instruction Set Summary Sheet 16 of 19 Clock Count Notes Real Pro Real Pro dress Virtual dress Viral Instruction Format Mode Ad Mode Ad or dress or dress Virtual Mode Virtual Mode 8086 8086 Mode Mode INTO Via interrupt or Trap Gate 71 9 To same privilege level Via Interrupt or Trap Gate 111 gj To different privilege level From 286 task to 286 TSS via Task Gate 384 gj kr From 286 task to Intel 386 SX CPU TSS via Task Gate 411 g jkr From 286 task to virtual 8086 mode via Task Gate 328 9 From Intel386 SX CPU task to 286 TSS via Task Gate rd gjkr From Intel386 SX CPU task to Intel 386 SX CPU TSS via task gate 413 g hkr From Intel386 SX CPU task to virtual 8086 mode via Task Gate 329 g jkr From virtual 8086 mode to 286 TSS via Task Gate 391 gj From virtual 8086 mode to Intel 386 SX CPU TSS via task gate 418 g jkr From virtual 8086 mode to privilege level 0 via trap gate or interrupt gate 223 BOUND Via interrupt or Trap Gate 7i 9 To same privilege level Via Interrupt or Trap Gate 1
49. Ye S DMA channel is reprogrammed with the original addresses and byte count A2332 02 Figure 12 9 Single Data transfer Mode with Autoinitialize Buffer transfer Mode 12 16 intel DMA CONTROLLER After initialization the DMA channel is programmed with the requester and target addresses and a byte count DREQn active DMA gains bus control transfers one byte or word of data decrements byte count and then relinquishes bus control Is there Write new requester and a new process target addresses and a to set up new byte count Byte count FFFFFFH or active DMA is programmed Was the i channel set up with the new addresses f and byte count or a new process No new transfer information so channel becomes idle A2335 02 Figure 12 10 Single Data transfer Mode with Chaining Buffer transfer Mode 12 17 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 12 2 7 2 Block Data transfer Mode In block data transfer mode a channel request initiates a buffer transfer The channel gains bus control then transfers the entire buffer of data The DRQn signal only needs to be held active until DACKni is active NOTE Block mode unlike the single mode only gives up control of the bus for DRAM refresh cycles As with single mode the channel s buffer transfer mode determines whether the channel be comes idle or is reprogrammed after the buffer trans
50. 13 28 intel SYNCHRONOUS SERIAL I O UNIT Disable Receiver _SetEXRegByte SSIOCON1 SSControl else Slave Receiver Receiver MUST already be Enabled Wait until Receive Holding Buffer is Full while GetEXRegByte SSIOCON1 amp SSIO RHBF return WORD GetEXRegWord SSIORBUF SSerialReadWord RRR RK KKK IK KK I Ck CIC A IA IRR kk ko kk KC CK k k Kk k k Kk k k Kk KC IA k k k k k k k k kk I kk k k k kk k k k SSerialWriteWord Description Is a Polled serial port write function that will wait forever or until a character has been written to the serial port Parameters Ch Word to be written out to serial port MasterSlave Defines whether transmitter is Master or Slave Returns None Assumptions If transmitter is in Slave mode it must already be enabled Syntax define SSIO TX MASTR 0x2 define SSIO TX SLAVE 0x0 char Ch SSerialWriteWord WORD Ch SSIO TX MASTR Real Protected Mode No changes required OKCKCkCKCKCKCKCKCkCkCKCKCkCk Ck CkCkCKCkCICkCk IIA AA Kk Ck IR AIA void SSerialWriteWord WORD Ch BYTE MasterSlave register BYTE SSControl unsigned int i if MasterSlave 55 0 TX MASTR Save Control Register SSControl GetEXRegByte SSIOCON1 13 29 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Get Control Register Ready to disable SSControl amp 55 TX ENAB Clear the bit Set Buffer to C
51. 9911 31 Scratch Pad Register 5 11 32 DMA Unit Block 12 2 DMA Temporary Buffer Operation for Read 12 8 DMA Temporary Buffer Operation for A Write 12 8 Start of a Two cycle DMA Transfer Initiated by 12 9 Changing the Priority of the DMA Channel and External Bus Requests 12 10 Buffer Transfer Ended by an Expired Byte 12 11 Buffer Transfer Ended by the EOP 12 11 Single Data transfer Mode with Single Buffer transfer Mode 12 15 Single Data transfer Mode with Autoinitialize Buffer transfer Mode 12 16 Single Data transfer Mode with Chaining Buffer transfer Mode 12 17 Block Data transfer Mode with Single Buffer transfer Mode 12 19 Block Data transfer Mode with Autoinitialize Buffer transfer Mode 12 20 Buffer Transfer Suspended by the Deactivation of 12 21 Demand Data transfer Mode with Single Buffer transfer Mode 12 22 Demand Data transfer Mode with Autoinitialize Buffer transfer Mode
52. FeFe FeFo A2315 01 Figure 10 16 Mode 4 Basic Operation 10 16 intel TIMER COUNTER UNIT Figure 10 17 shows suspending the counting sequence A low level on GATEn causes the counter to suspend counting both the state of OUTn and the count remain unchanged A high level on GATEn resumes counting Control Word 18H Count 3 Writes to Counter n CLKINn GATEn OUTA 1 1 1 1 1 1 Count 0001 A2402 01 Figure 10 17 Mode 4 Disabling the Count Figure 10 18 shows writing a new count On the CLKINn pulse following the new count write the counter loads the new count and counting continues from the new count Control Count 2 18 oe Writes to 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CLKINn 1 1 LN PE f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Count 0003 0002 0001 0002 0001 0000 FFFF A2403 01 Figure 10 18 Mode 4 Writing a New Count 10 17 Intel386 EX EMBEDDED PROCESSOR USER S MANUAL intel 10 2 6 Mode 5 Hardware triggered Strobe Initializing a counter for mode 5 sets the counter s OUTn signal starting the counting sequence A gate trigger loads the programmed count When the counter reaches zero OUTn strobes low for one clock pulse The counter then rolls over and continues counting but OUTn does not strobe
53. Intel386 EX MICROPROCESSOR USER S MANUAL 19 2 9 Recel isi vei roce na en eder rece ree 13 3 REGISTER DEFINITIONS 13 3 1 Pin Configuration Register 13 3 2 510 and SSIO Configuration Register SIOCFG 13 3 3 Prescale Clock Register CLKPRS 13 3 4 SSIO Baud rate Control Register SSIOBAUD 13 3 5 SSIO Baud rate Count Down Register SSIOCTR 13 3 6 SSIO Control 1 Register SSIOCON1 13 3 7 SSIO Control 2 Register SSIOCONO 13 3 8 SSIO Transmit Holding Buffer SSIOTBUF see 13 3 9 SSIO Receive Holding Buffer SSIORBUF sse 13 4 DESIGN CONSIDERATIONS puo E Heb ta eaae esee nated 13 5 PROGRAMMING 13 5 1 SSIO Example Code eese CHAPTER 14 CHIP SELECT UNIT 14 3 tere rip rte enge dens 14 3 1 Defining a Channel s Address Block 14 3 2 System Management Mode Support 14 3 8 Bus Cycle Length 14 3 4 Bus Size Control rt et e eveniret 14 3 5 Overlapping Regions 14 4 REGISTER DEFINIT IONS e t reinen n
54. PnPIN n 1 3 ISA Addr read only Reset State XXH 7 0 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PSO Bit Bit Number Mnemonic Function 7 0 PS7 0 Pin State Reading a PS bit returns the logic state present on the associated port pin Figure 16 6 Port Pin State Register PnPIN 16 9 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 16 2 2 Initialization Sequence After a device reset a weak pull up or pull down resistor holds each pin high or low until user software writes to the PnCFG register The pins are configured as inputs in I O port mode To en sure that the pins are initialized correctly and that the weak resistors are turned off follow this suggested initialization sequence NOTE Even if you want to use the entire port as I O its default configuration after reset you must write to PnCFG to turn off the weak pull up and pull down resistors 1 Write to PnLTC to specify the pin value Writing to before PnDIR ensures that output pins initialize to known values e Foran output pin write the data that is to be driven by the pin to its PnLTC bit e Foran input pin set its PnLTC bit 2 Write to Pn DIR to specify the pin direction e To configure a pin as a complementary output clear its PnDIR bit e To configure a pin as an input or open drain output set its PnDIR bit 3 Write to PnCFG to turn off the weak resistors and select either I O or peripheral mode e To configure a pi
55. RBFDMA1 5101 TXEDMAO SIO0 SSRBF SSIO OUT TCU RBFDMAO 5100 SIO1 SSTBE SSIO DRQO DCD1 9T DACKO 55 J pra RXD1 DMACFG 7 amp o PINCFG 2 DACK DMAACK1 From 5101 gt 0 TXD1 DMAINT To ICU PINCFG 3 End of Process From SIO1 39 CTS1 4 P1CFG 6 HOLD m HOLD To From I O Port 1 0 P1 6 Bus Arbiter 1 P1CFG 7 HLDA ee HLDA To From I O Port 1 0 1 7 Alternate pin signals are in parentheses E A2531 02 Figure 12 1 DMA Unit Block Diagram 12 2 intel DMA CONTROLLER 12 1 1 Terminology This section provides a definition of some of the terms used in this chapter to describe the DMA controller DMA Process Buffer Buffer Transfer Data Transfer Bus Cycle Requester Target Source Destination A DMA process is the execution of a programmed DMA task from beginning to end Each DMA process requires initial programming by the Inte1386 EX processor A contiguous block of data The action required by the DMA to transfer an entire buffer The DMA action in which a group of bytes or words are moved between devices by the DMA controller A data transfer operation may involve movement of one or many bytes Access by the DMA to a single byte or word The Requester is the device which requests service by the DMA controller of the control signals which the monitors or
56. Read RBRn to obtain the last data word received Use the interrupt control or DMA units or poll the serial line status register LSRz to determine whether the receive buffer is full Receive Buffer RBRO RBR1 RBRO RBR1 Expanded Addr F4F8H F8F8H read only ISA Addr 03F8H 02F8H Reset State XXH XXH 7 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RBO Bit Bit Function Number Mnemonic 7 0 RB7 0 Receive Buffer Bits These bits make up the last word received The receiver shifts bits in starting with the least significant bit The receiver then strips off the asynchronous bits start parity and stop and transfers the received data bits from the receive shift register to the receive buffer NOTE The receive buffer register shares an address port with other SIO registers Bit 7 DLAB of the LCRn must be cleared in order to read the receive buffer register Figure 11 14 Receive Buffer Register RBRn 11 24 intel ASYNCHRONOUS SERIAL I O UNIT 11 3 6 Serial Line Control Register LCRn Use LCRn to provide access to the multiplexed registers send a break condition and determine the data frame for receptions and transmissions Serial Line Control LCRO LCR1 LCRO LCR1 Expanded Addr F4FBH F8FBH read write ISA Addr OS3FBH 02 Reset State 00H 00H 7 0 DLAB SB SP EPS PEN STB WLS1 WLSO Bit Bit Number Mnemonic Functio
57. SRXCLK NIE NN f T 1 1 1 1 1 1 1 1 1 1 1 2446 01 Figure 13 14 Receiver Master Mode Single Word Transfer Operation in receiver slave mode is similar to master mode except the receiver is clocked from the SRXCLK pin When the receiver is enabled any time during the SRXCLK clock cycle data on the SSIORX pin is latched into the shift register at the next rising edge of SRXCLK The SRX CLK and SSIORX pins are three stated 13 15 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 13 3 REGISTER DEFINITIONS Table 13 3 list the registers associated with the SSIO and the following sections contain bit de scriptions for each register Table 13 3 SSIO Registers Expanded i Function Register Address unctio PINCFG F826H Pin Configuration read write Connects the serial receive clock signal SRXCLK and the transmit serial data signal SSIOTX to the package pin SIOCFG F836H SIO and SSIO Configuration read write Selects the baud rate generator s clock source SERCLK or PSCLK CLKPRS F804H Clock Prescale read write Controls the frequency of PSCLK SSIOBAUD F484H SSIO Baud rate Control read write Enables the baud rate generator and determines its baud rate In master mode the transmitter and receiver are clocked by the baud rate generator SSIOCTR F48AH SSIO Baud rate Count Down read only Indicates whether the baud rate generator is enabled and re
58. These bits make up the next data word to be transmitted The control logic loads this word into the transmit shift register The transmit shift register shifts the bits out on the falling edge of the tranmitter clock pin The word is transmitted out starting with the most significant bit TB15 D 64 TBRn Transmit Buffer TBRO TBR1 TBRO TBR1 Expanded Addr FAF8H F8F8H write only ISA Addr O3F8H 02 8 Reset State XXH XXH 7 0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TBO Bt BI Function Number Mnemonic 7 0 TB7 0 Transmit Buffer Bits These bits make up the next data word to be transmitted The transmitter loads this word into the transmit shift register The transmit shift register then shifts the bits out along with the asynchronous communication bits start stop and parity The data bits are shifted out least significant bit TBO first NOTE The transmit buffer register shares an address port with other SIO registers You must clear bit 7 DLAB of LCRn before you can write to the transmit buffer register D 62 intel SYSTEM REGISTER QUICK REFERENCE D 65 TMRCFG Timer Configuration Expanded Addr F834H TMRCFG ISA Addr read write Reset State 00H 7 0 TMRDIS SWGTEN GT2CON CK2CON GT1CON CK1CON GTOCON CKOCON Bit Bit Function Number Mnemonic unctio 7 TMRDIS Timer Disable 0 Enables the CLKINn signals 1 Disables the CLKINn signals 6 SWGTEN Software GATEn E
59. When this signal is high the Transmitter Holding Register is empty transmit data has been loaded into the Transmit Shift Register RBFDMAn Internal Signal Receiver Full When high this signal indicates that the Receive Buffer has been loaded with data from the Receive Shift Register 11 2 SIO OPERATION The following sections describe the operation of the baud rate generator transmitter and receiver and discusses the modem control logic SIO diagnostic mode and SIO interrupt sources 11 2 1 Baud rate Generator Each SIO channel s baud rate generator provides the clocking source for the channel s transmitter and receiver The baud rate generator can divide its input BCLKIN by any divisor from 1 to 216 1 The output frequency is 16 times the desired bit time The transmitter shifts data out on the rising edge of BCLKIN The receiver samples input data in the middle of a bit time The internal serial clock SERCLK signal or the COMCLK pin can be connected to the baud rate generator s BCLKIN signal Figure 11 2 The SIO configuration register SIOCFG selects one of these sources Baud rate SERCLK Generator Baud Rate CLK2 BCLKIN Generator Output Frequency COMCLK pin mux A2524 02 Figure 11 2 SIOn Baud rate Generator Clock Sources SERCLK provides a baud rate input frequency BCLKIN of CLK2 4 The COMCLK pin allows an external source with a maximum frequency of CLK2 4 to provide the baud rate gene
60. i a a a a S Due to refresh pending i READY LOCK Figure 6 12 Refresh Cycle During HOLD HLDA 6 30 intel BUS INTERFACE UNIT 6 3 7 58 Cycle BS8 cycle allows external logic to dynamically switch between an 8 bit data bus size and a 16 bit data bus size by using the BS8 signal Figure 6 13 shows a word access to an 8 bit pe ripheral To use the dynamic 8 bit bus sizing an external memory or I O should connect to the lower eight bits of the data bus D7 0 use the BLE as address bit 0 and assert BS8 at the BS8 pin in 2 of a memory or I O access A 8 cycle can also be generated by the internal chip select unit Refer to Chapter 14 CHIP SELECT UNIT In this case the Chip Select Unit generates the BS8 signal internally Depending upon the current bus access width and address and the state of the BS8 signal the processor performs the actions described in the next two sections 6 3 7 1 Write Cycles Ifthe current bus cycle is a byte write with BHE active and BLE inactive the processor copies the upper eight bits of the data bus D15 8 to the lower eight bits of the data bus D7 0 i e the byte appears on both the upper and lower data buses Ifthe current bus cycle is a byte write with BHE inactive and BLE active the processor ignores the state of the BS8 signal Ifthe current bus cycle is a word write with both BHE and BLE active and the processor samples the BS
61. 0 DMAOTARS DMAOTAR2 DMAOTAR1 DMAOTARO F086H F087H 16 F000H BP 1 8 F000H BP 0 0 DMAOBYC2 DMAOBYC1 DMAOBYCO F098H DMA Channel 1 24 16 F001H BP 1 8 F001H BP 0 0 DMA1REQ3 DMA1REQ2 DMA1REQ1 DMA1REQO F013H BP 1 24 F013H BP 0 16 F012H BP 1 8 F012H BP 0 0 DMA1TAR3 DMA1TAR2 l DMA1TAR1 DMA1TARO F085H F083H 16 F002H BP 1 8 F002H BP 0 0 DMA1BYC2 DMA1BYC1 DMA1BYCO F099H F003H BP 1 F003H BP 0 Figure 12 20 DMA Channel Address and Byte Count Registers DMAnREQn DMAnTARn DMAnBYCn 12 33 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL In NOTE The value you write to the byte count register must be one less than the number of bytes to be transferred To transfer one byte write zero to the byte count register byte count 2 number of bytes 1 To transfer one word write one byte to the byte count register byte count number of words X 2 1 12 3 4 Overflow Enable Register DMAOVFE Use DMAOVFE to specify whether all 26 bits or only the lower 16 bits of the target and requester addresses are incremented or decremented during buffer transfers and to determine whether all 24 bits of the byte count or only the lower 16 bits of the byte count are decremented during buffer
62. 6 2 2 Pipelining The processor can control the address and status outputs so that the outputs for the next bus cycle become valid before the end of the present bus cycle This technique allowing bus cycles to over lap is called pipelining Pipelining increases bus throughput without decreasing allowable memory or I O access time thus allowing high bandwidth with relatively slow inexpensive components In addition using pipelining to address slower devices can yield the same throughput as addressing faster devices with no pipelining With pipelining a device operating at 33 MHz CLK2 66 MHz can transfer data at 33 Mbytes per second while requiring a device with access time of approximately 3 T states 90 ns at 33 MHz neglecting signal delays Without address pipelining the access time has to be approximately 2 T states 60 ns at 25 MHz Therefore when pipelining is used slower devices can be used in the system to achieve performance similar to a faster device in a non pipe lined system Pipelining is not supported during I O bus cycles and BS8 cycles 16 bit accesses to 8 bit devic es NOTE During I O cycles NA is ignored NA must be kept deasserted blocked externally during the T2 states of BS8 memory cycles 6 8 intel BUS INTERFACE UNIT NOTE Pipelining is also supported during memory cycles initiated by the two integrated DMA units Refer to Pipelined Cycle on page 6 19 for a description of pipelined
63. 6 6 basic internal and external bus cycles 6 12 basic refresh cycle 6 29 BS8 cycle 6 33 counter mode 0 10 7 counter mode 1 10 9 10 10 Index 10 intel counter mode 2 10 11 10 12 counter mode 3 10 13 10 14 10 15 counter mode 4 10 16 10 17 counter mode 5 10 18 10 19 DMA transfer 12 9 12 11 12 21 entering and leaving idle mode 8 9 entering and leaving powerdown mode 8 11 HALT cycle 6 27 interrupt acknowledge cycle 6 25 9 29 JTAG test logic unit 18 12 18 13 LOCK signal during pipelining 6 35 nonpipelined read cycle 6 15 nonpipelined write cycle 6 18 pipelined cycles 6 21 refresh cycle during HOLD HLDA 6 30 SSIO receiver 13 15 SSIO transmitter 13 11 U Units of measure defined 1 3 V Virtual 86 mode 9 8 Watchdog timer unit 17 1 17 16 block diagram 17 2 design considerations 17 12 disabling the WDT 17 6 lockout sequence 17 4 operation 17 3 17 4 during idle mode 8 5 overview 17 1 17 2 programming 17 5 17 6 bus monitor mode 17 5 general purpose timer mode 17 4 software watchdog mode 17 5 WDTCNTH 17 8 D 67 WDTCNTL 17 8 D 67 WDTRLDH 17 10 D 68 WDTRLDL 17 10 D 68 WDTSTATUS 17 9 D 69 register addresses 4 18 D 4 intel registers 17 7 WDTCLR 17 7 WDTCNTH 17 7 WDTCNTL 17 7 WDTRLDH 17 7 WDTRLDL 17 7 WDTSTATUS 17 7 reload event 17 4 signals 17 3 WDT See Watchdog timer unit Worksheets peripheral configuration 5 34 pin configuration 5
64. DMA Interrupt Status Register DMAIS seem d2 49 Transmitter and Receiver in Master Mode sse men 13 2 Transmitter in Master Mode Receiver in Slave 13 2 Transmitter in Slave Mode Receiver in Master 13 3 Transmitter and Receiver in Slave 13 3 Clock Sources for the Baud rate Generator sese 13 5 SSIO Transmitter with Autotransmit Mode Xix Intel386 EX MICROPROCESSOR USER S MANUAL Figure 19 7 13 8 13 9 13 10 13 11 13 12 13 13 13 14 13 15 13 16 13 17 13 18 13 19 13 20 13 21 13 22 13 23 14 1 14 2 14 3 14 4 14 5 14 6 14 7 14 8 14 9 15 1 15 2 15 3 15 4 15 5 15 6 15 7 15 8 16 1 16 2 16 3 16 4 16 5 16 6 17 1 17 2 17 3 FIGURES Page SSIO Transmitter with Autotransmit Mode 13 8 Transmit Data by Polling ER 19 9 Interrupt Service Routine for Transmitting Data Using Interrupts end e 13 10 Transmitter Master Mode Single Word Transfer Enabled when Clock is High 13 11 Transmitter Master Mode Single Word Transfer Enabled when Clock is Low 13 11 Receive Data by Polling tci te tbe tuae 13 13 Interrupt Service Routine
65. DMAMSK ISA Addr 000AH write only Reset State 04H 7 0 HRM 0 CS Bit Bit i Number Mnemonic Punctien 7 3 Reserved for compatibility with future devices write zeros to these bits 2 HRM Hardware Request Mask 0 Unmasks enables hardware requests for the channel specified by bit 0 1 Masks disables hardware requests for the channel specified by bit 0 NOTE When this bit is set the channel can still receive software requests 1 0 Must be 0 for correct operation 0 CS Channel Select 0 The selection for bit 2 affects channel 0 1 The selection for bit 2 affects channel 1 D 23 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL D 19 DMAnBYCn DMAnREQn AND DMAnTARn DMA Channel 0 Requester Address Target Address Byte Count Requester Address Target Address Byte Count D 24 24 16 8 0 DMAOREQ3 DMAOREQ2 DMAOREQ1 DMAOREQO F011H BP 1 24 F011H BP 0 16 F010H BP 1 8 F010H BP 0 0 DMAOTARS DMAOTAR2 DMAOTAR1 DMAOTARO F086H F087H 16 FOOOH BP 1 8 FOOOH BP 0 0 DMAOBYC2 DMAOBYC1 DMAOBYCO F098H DMA Channel 1 24 16 F001H BP 1 8 F001H BP 0 0 DMA1REQ3 DMA1REQ2 DMA1REQ1 DMA1REQO F013H BP 1 24 F013H BP 0 16 F012H BP 1 8 F012
66. Figure 11 5 SIOn Receiver Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel The receiver contains a receive buffer full RBF flag and flags for each of the error conditions described above At reset RBF and each of the error flags PE FE OE and BI are clear indi cating that the receive buffer is empty and no error has occurred When a character is received the receiver checks for parity framing or break errors and sets the appropriate bits if necessary It then shifts the data into the receive buffer sets the OE bit if an overrun occurs and then sets the RBF flag Reading the receive buffer clears the RBF flag and any error flags in the LSR that may have been set except for the OE bit The OE bit is cleared by reading the LSR High speed serial transfers may require using the DMA to eliminate interrupt latency time in ser vicing the SIO Since the SIO unit clears the error bits in the line status register each time the re ceive buffer register is read it would be impossible to detect an error using DMA Because of this two RBF signals are used One RBF signal RBFDMA goes directly to the DMA unit This signal is blocked when an error parity overrun break or framing occurs This prevents a DMA request from being generated by the RBF The other RBF signal RBFINT goes directly to the interrupt priority logic and out on SIOINT if enabled in the Interrupt Enable Register When the Interrupt Enable Register i
67. INTCFG The ICU receives requests from eight internal sources Three outputs from the timer counter unit OUT2 0 An output from each of the serial I O units SIOINT1 0 Anoutput from the synchronous serial I O unit SSIOINT Anoutput from the DMA unit DMAINT An output from the WDT unit WDTOUT In addition the ICU controls the interrupt sources on ten external pins NT3 0 multiplexed with I O port signals P3 5 2 are enabled or disabled by the P3CFG register see Figure 5 18 e INT7 4 share their package pins with four TCU inputs TMRCLKI TMRGATEO and TMRCLKO These signal pairs are not multiplexed however the pin inputs are enabled or disabled by the INTCFG register INT9 8 share their pins with TMROUTI TMROUTO P3 1 P3 0 The three cascade outputs CAS2 0 should be enabled when an external 82C59A module is con nected to one of the INT9 8 or INT3 0 signals The cascade outputs are ORed with address lines A18 16 See Interrupt Acknowledge Cycle on page 6 23 for details Use Tables 5 1 and 5 2 to configure the functionality of the master 82C59A s IR3 IRA inputs and the associated external pins 5 7 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Table 5 1 Master s IR3 Connections Function INTCFG 6 MCR1 3 P3CFG 1 IR3 connected to SIOINT 1 0 X 0 1 selected at pin P3 1 IR3 connected to SIOINT 1 0 X 1 OUT1 connected to pin TMROUT1 IR3 i Ily d
68. OCW1S _SetEXRegByte OCW1S Mask amp SlaveMask Enable8259Interrupt RRR IKK KKK IKK IK e k RK IA A KR IR AIR k k k k IA k k k k k k k k k k k k kk k k k k k k k ke kk ko k k k k k SetIROVector Description Loads the interrupt vector table with the address of the interrupt routine The vector table entry number is determined by the vector number Parameters InterProc Address of interrupt function will be loaded into the interrupt table Hardware Interrupt request number 0 15 ISR Type Specifies if the interrupt function should be treated as a TRAP ISR or an INTERRUPT ISR Real Mode only 9 38 intel INTERRUPT CONTROL UNIT supports INTERRUPT ISR parameter is ignored Protected mode supports both Returns Error Code E INVALID VECTOR An IRQ of greater than 15 was passed E BADVECTOR IRQ is used for cascading to a slave interrupt controller E OK Initialized OK No error Assumptions Compiler supports far and interrupt keywords ICU must be configured before this function is call for it to operate properly IRQ SlaveBase IRQ MstrBase CascadeBits are set before function is called These are initialized in the InitICU functions supplied in this source Syntax int error code error code SetIRQVector wdtISR 155 Slave IR s are offset by 8 in Nector Table INTERRUPT ISR Real Protected Mode No changes required Uses SetInterruptVector which is mode dep
69. Reserved for compatibility with future devices write zeros to these bits 2 HRM Hardware Request Mask 0 Unmasks enables hardware requests for the channel specified by bit 0 1 Masks disables hardware requests for the channel specified by bit 0 NOTE When this bit is set the channel can still receive software requests 1 0 Must be 0 for correct operation 0 CS Channel Select 0 The selection for bit 2 affects channel 0 1 The selection for bit 2 affects channel 1 12 44 Figure 12 29 DMA Channel Mask Register DMAMSK intel DMA CONTROLLER DMA Group Channel Mask Expanded Addr FOOFH DMAGRPMSK ISA Addr 000FH read write Reset State 03H 7 0 HRM1 HRMO Bit Bit Number Mnemonic Function 7 2 Reserved These bits are undefined for compatibility with future devices do not modify these bits 1 HRM1 Hardware Request Mask 1 0 Channel 1 s hardware requests are not masked 1 Masks disables channel 1 s hardware requests When this bit is set channel 1 can still receive software requests 0 HRMO Hardware Request Mask 0 0 Channel 0 s hardware requests are not masked 1 Masks disables channel 0 s hardware requests When this bit is set channel 0 can still receive software requests Figure 12 30 DMA Group Channel Mask Register DMAGRPMSK 12 45 Intel386 EX EMBEDDED MICRO
70. SIOO TXEDMAt 5101 SSTBE SSIO DMACFG 7 o PINCFG 2 DACK1 DMAACK 1 From 5101 gt 0 TXD1 DMAINT To ICU 0 PINCFG 3 End of Process EOP From SIO1 3 9 CTS1 4 P1CFG 6 HOLD A U HOLD To From I O Port 1 0 P1 6 Bus Arbiter 1 P1CFG 7 HLDA 9 HLDA To From I O Port 1 0 1 7 Refresh Unit 1 PINCFG 6 5 rl 5 HLDA From CSU 0 56 t Alternate pin signals are in parentheses A2516 02 Figure 5 2 Configuration of DMA Bus Arbiter and Refresh Unit Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel DMA Configuration DMACFG read write 7 Expanded Addr F830H ISA Addr Reset State 00H 0 D1MSK D1REQ2 D1REQ1 D1REQO DOMSK DOREQ2 DOREQ1 DOREQO Bit Number Bit Mnemonic Function 7 D1MSK DMA Acknowledge 1 Mask 0 channel 1 s acknowledge DMAACK1 signal is not masked 1 Masks DMA channel 1 s acknowledge DMAACK1 signal Useful when channel 1 s request DREQ1 input is connected to an internal peripheral 6 4 D1REQ2 0 DMA Channel 1 Request Connection Connects one of the eight possible hardware sources to channel 1 s request input DREQ1 000 DRQ1 pin external peripheral 001 SIO channel 1 s receive buffer full signal RBFDMA1 010 SIO channel 0 s transmit buffer empty signal 011 SSIO receive
71. SIOPortBase Unit 5 1 BASE 5100 BASE Initialized Serial Port registers Calculate the baud divisor value WORD BaudClkIn BaudDivisor based on baud clocking 16 BaudRate Turn on access to baud divisor register _SetEXRegByte SIOPortBase Set the baud rate divisor _SetEXRegByte SIOPortBase _SetEXRegByte SIOPortBase Set Serial Line control SetEXRegByte SIOPortBase Set modem control bits LCR 0x80 High byte first register DLH BaudDivisor DLL LOBYTE BaudDivisor register LCR Mode Sets Mode and reset the Divisor latch _SetEXRegByte SIOPortBase MCR ModemCntrl return E_OK i InitSIO ROKK IK KKK kk RK e e e AE e Ck e k IRR IR AR IRR IR AR IRR Kk e IR IR IA k k k k k k k k k SerialReadStr Description Is a Polled serial port read function that waits forever or until count characters are read Parameters Unit Unit number of the serial port from the serial port 0 for SIO port 0 I for SiO port 1 str count Returns Error Code E OK or Error code status Assumptions Address of where to place the input data Number of characters to read before returning value of Line Status Register LSR REMAPCFG register has Expanded I O space access enabled ESE bit set The processor Port pin are initialized separately Syntax 11 35 Intel386 EX EMBEDDED MICR
72. SetEXRegByte TBRO trans buffer Tbuffer index Tbuffer else Disable TBE interrupts SetEXRegByte IERO 0x00 Service TBE ROKK KK kk Ck Ck I KK Kk Ck KK Ck Kk kk KC kk Ck Kk k kk Ck ke kk ko k k kk ke Example code to show how to set up for a Serial Port interrupt This example is for an interrupt on SIO 0 sourced by the Receive Buffer Full Signal The source code for the functions SetIRQVector and Disable8259Interrupt is included in the Interrupt Control Unit chapter SetIRQVector Serial0_ISR 4 INTERRUPT ISR Set vector for Interrupt on Master line 4 Disable8259Interrupt IR1 IR5 IR6 IR7 IRO IR1 IR2 1IR3 1IR4 IR5 IR6 IR7 Enable8259Interrupt IR2 IR4 0 Enable slave interrupt to master IR2 Enable SIO 0 IR4 enable Enable Interrupts SetEXRegByte IERO 0x01 Enable interrupt on RBF signal BORK IKK KKK IK KK CK RK Kk k k k k k Kk Ck k Kk k Kk k Kk k k Kk k k k k k Kk Ck k kk k ko kk ke kk k kkk ke ke ke ke ek 11 45 intel 12 DMA CONTROLLER 12 CONTROLLER The DMA controller improves system performance by allowing external or internal peripherals to directly transfer information to or from the system The DMA controller can transfer data be tween any combination of memory and I O with any combination of data path widths 8 or 16 bits It contains two identical channels The DMA c
73. Sheet 9 of 19 In tel Clock Count Notes Real Pro Real Pro Ad tected Ad tected i dress Virtual dress Virtual Instruction Format Mode Ad Mode Ad or dress or dress Virtual Mode Virtual Mode 8086 8086 Mode Mode regis ler memory 0000 0100011 mod reg r m 3 12 3 12 b h register BTC test bit and complement register memory immed 6 8 6 8 b h immediate 0000 0111010 mod11 1 r m 8 bit data regis ler memory 0000 0111011 mod reg 6 13 6 13 b h register BTR test bit and reset register memory immed 6 8 6 8 b h immediate 0000 0111010 4110 8 bit data regis 0000 0110011 mod reg 6 13 6 13 b h register BTS test bit and set register memory immed 6 8 6 8 b h immediate 0000 0111010 mod10 1r m 8 bit data regis 0000 0101011 mod reg r m 6 13 6 13 b h register CONTROL TRANSFER CALL Call direct within segment 11101000 full displacement 74m 94m b r reg memory indirect 74m 9 m b hr within segment Vtt ees 10 12 m direct intersegment 10011010 unsigned full offset selector 17 m 42 b jkr Protected mode only direct intersegment Via call gate to same privilege level 644m hjikr Via call gate to different privilege level no parameters 98 m h j K r Via call gate to different privilege level x
74. When the Core Bus Unit is not performing bus cycles to execute an instruction the Instruction Prefetch Unit uses the Core Bus Unit to fetch sequentially along the instruction byte stream These prefetched instructions are stored in the Instruction Queue to await processing by the Instruction Decode Unit Instruction prefetches are given a lower priority than data transfers assuming zero wait state memory access prefetch activity never delays execution On the other hand when there is no data transfer requested prefetching uses bus cycles that would otherwise be idle 3 2 3 Instruction Decode Unit The Instruction Decode Unit takes instruction stream bytes from the Prefetch Queue and trans lates them into microcode The decoded instructions are then stored in a three deep Instruction Queue FIFO to await processing by the Execution Unit Immediate data and opcode offsets are also taken from the Prefetch Queue The decode unit works in parallel with the other units and begins decoding when there is a free slot in the FIFO and there are bytes in the prefetch queue Opcodes can be decoded at a rate of one byte per clock Immediate data and offsets can be decod ed in one clock regardless of their length 3 4 intel CORE OVERVIEW 3 2 4 Execution Unit The Execution Unit executes the instructions from the Instruction Queue and therefore commu nicates with all other units required to complete the instruction The functions of its three subun
75. baud rate generator 56 Chip selects REFRESH CSS Activated when the address of a memory or I O bus cycle is DACKO T within the address region programmed by the user 52 2 2 51 2 1 50 2 0 2 intel SIGNAL DESCRIPTIONS Table A 2 Description of Signals Available at the Device Pins Sheet 2 of 6 Multiplexed With Signal Type Name and Description Alternate Function 51 Clear to Send 50 Indicates that the modem or data set is ready to exchange P2 7 data with the SIO channel D15 0 Data Bus Inputs data during memory read I O read and interrupt acknowledge cycles outputs data during memory write and I O write cycles During reads data is latched during the falling edge of phase 2 of T2 T2P or T2i During writes this bus is driven during phase 2 of T1 and remains active until phase 2 of the next T1 T1P or Ti DACK1 Channel Acknowledge TXD1 DACKO Indicates that the DMA channel is ready to service the 55 requesting device An external device uses the DRQn pin to request DMA service the DMA uses the DACKn pin to indicate that the request is being serviced D C Data Control Indicates whether the current bus cycle is a data cycle memory or I O read or write or a control cycle interrupt acknowledge halt shutdown or code fetch DCD1 Data Carrier Detect DRQO DCDO Indicates that the modem or data
76. buffer transfer modes 12 12 bus control arbitration 12 9 bus cycle options for data transfers 12 5 12 8 cascade mode 12 25 12 26 changing priority of DMA channel and external bus requests 12 10 data transfer modes block 12 18 12 20 demand 12 21 12 24 single 12 14 12 17 DMA transfers 12 5 ending DMA transfers 12 10 starting DMA transfers 12 9 overview 12 1 12 4 INDEX programming 12 28 12 51 address and byte count registers 12 33 channel registers 12 33 considerations 12 50 DMAOBYCn 12 33 D 24 DMAOREQn 12 33 D 24 DMAOTARn 12 33 D 24 DMAIBYCn 12 33 D 24 DMAIREQn 12 33 D 24 DMAITARn 12 33 D 24 DMABSR register 12 46 DMACFG 5 6 12 32 D 14 DMACFG register 12 32 DMACHR 12 47 D 15 DMACHR register 12 47 DMACMDI 12 35 D 16 DMACMDI register 12 35 DMACMD2 12 37 D 17 DMACMD 2 register 12 37 DMAGRPMSK 12 45 D 18 DMAIEN 12 48 D 19 DMAIEN register 12 48 DMAIS 12 49 D 20 DMAIS register 12 49 DMAMODI 12 39 D 21 DMAMODI register 12 38 DMAMOD2 12 41 0 22 DMAMOD2 register 12 40 12 41 DMAMSK 12 44 D 23 DMAOVFE register 12 34 DMASRR 12 43 D 26 DMASRR register 12 42 12 43 DMASTS 12 36 D 27 DMASTS register 12 36 PINCFG register 12 28 12 31 register addresses 4 15 D 1 registers 12 28 signals 12 4 using with external devices 5 3 Documents related 1 5 DOS Address defined 1 4 Index 3 INTEL386 EX MICROPROCESSOR USER S MANUAL DOS compatibility departu
77. counter latch commands without reading the counter only the first counter latch command latch es the count value After issuing counter latch command you can read the counter s TMRz register When reading the counter s TMR7 register you must follow the counter s programmed read selection least sig nificant byte only most significant byte only or least significant byte followed by the most sig nificant byte If the counter is programmed for two byte counts you must read two bytes You need not read the two bytes consecutively you may insert read write or programming operations between the byte reads 10 28 intel TIMER COUNTER UNIT You can interleave reads and writes of the same counter for example if the counter is pro grammed for the two byte read write selection the following sequence is valid l 2 3 4 Read least significant byte Write new least significant byte Read most significant byte Write new most significant byte Timer n Read Format Expanded Addr F040H F041H TMRn n 0 2 F042H ISA Addr 0040H 0041H 0042H Reset State XXH 7 0 CV7 CV6 CV5 CV4 CV2 CV1 CVO Bit Bit Number Mnemonic Function 7 0 CV7 0 Count Value These bits contain the counter s count value When reading the counter s count value follow the read selection specified in the counter s control word Figure 10 28 Timer n Register TMRn
78. counts as one component the entire immediate data if any counts as one component and all other bytes of the instruction and prefix es of each count as one component Misaligned or 32 bit operand accesses When instructions access a misaligned 16 bit operand or 32 bit operand on even address add 2 clocks for read or write add 4 clocks for read and write When instructions access a 32 bit operand on odd address add 4 clocks for read or write add 8 clocks for read and write E 1 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Wait states In Wait states add 1 clock per wait state to instruction execution for each data access tel Table E 1 lists the instructions with their formats and execution times The description of the notes for Table E 1 begins on page E 20 See Instruction Encoding on page E 22 for the defi nition of the terms used in this table Table E 1 Instruction Set Summary Sheet 1 of 19 Clock Count Notes Real Pro Real Pro Ad tected Ad tected Instruction Format dress Virtual dress Virtual Mode Ad Mode Ad or dress or dress Virtual Mode Virtual Mode 8086 8086 Mode Mode GENERAL DATA TRANSFER MOV Move register to 2 2 2 2 b h register memory 000100w mod reg register memory to 2 4 2 4 b h register 000101w mod reg immediate to 100011w 4000
79. dress Virtual Mode Ad Mode Ad or dress or dress Virtual Mode Virtual Mode 8086 8086 Mode Mode BOUND Interrupt 5 if Detect value out of range 01100010 mod reg r m If out of range 44 b e e g h j kr If in range 10 10 b e e g h j kr Protected Mode Only INT INT Type Specified Via interrupt or Trap Gate 71 gj To same privilege level Via Interrupt or Trap Gate 111 gj To different privilege level From 286 task to 286 TSS via Task Gate 438 gj kr From 286 task to Intel 386 SX CPU TSS via Task Gate 465 9 From 286 task to virtual 8086 mode via Task Gate 382 g hkr From Intel386 SX CPU task to 286 TSS via Task Gate 440 9 From Intel386 SX CPU task to Intel 386 SX TSS via task gate 467 g j K r From Intel386 SX CPU task to virtual 8086 mode via Task Gate 384 g jkr From virtual 8086 mode to 286 TSS via Task Gate 445 9 From virtual 8086 mode to Intel 386 SX CPU TSS via task gate 472 g j K r From virtual 8086 mode to privilege level 0 via trap gate or interrupt gate 275 gj k r INT TYPE 3 Via interrupt or Trap Gate 71 gj kr To same privilege level Via Interrupt or Trap Gate 111 gj To different privilege level From 286 task to 286 TSS via Task Gate 382 gj From 286 task to Intel 386 SX CPU TSS via Task Gate 409 g jkr From 286 task to virtual 8086 mode via Task Gate 326 g hkr From Intel386 SX CPU task to 286 TSS via Task Gate 384 9 From Intel386 SX CPU task to Intel 386 SX
80. generates for specific channels are logically related to the requester Only the requester is considered capable of initiating or terminating a DMA process The requester may be either I O or memory and may be the Source or the Destination of the transfer or neither The Target is the device with which the Requester wishes to communicate As far as the DMA process is concerned the Target is a slave which is incapable of control over the process The Target may be either I O or memory and may be either the Source or the Destination of the transfer The Source is the memory or I O from which data is being read The Destination is the memory or I O to which data is being written 12 3 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 12 1 2 DMA Signals Table 12 1 describes the DMA signals Table 12 1 DMA Signals drain output Device Pin Signal or Internal Description Signal DRQO Device pin DMA Channel 0 Requests input The SIO channel 0 receiver SIO channel 0 transmitter SIO0 RBFDMAO TXEDMAO Internal SIO channel 1 receiver SIO channel 1 transmitter SSIO SIO1 TXEDMA1 RBFDMA1 signals transmitter SSIO receiver TCU counter 1 output or an SSIO Transmitter Receiver external device can request DMA channel 0 service TCU Counter 1 These sources are referred to as channel 0 hardware requests You can also issue channel 0 software requests by writing to the DMA software request register DRQ
81. internally NOTE Since LB A may be used as an output enable by both the internal and external READ Y buffers care must be taken in selecting the external READY buffer to minimize contention on the READY signal caused by differences in buffer characteristics 6 10 intel BUS INTERFACE UNIT LBA r READY To Internal Units lt Chip Boundary A2485 01 Figure 6 3 Ready Logic When an internal cycle occurs the LBA signal becomes active in Phase 1 of the first T2 state It then stays active until the rising edge of PHI of the first T2 T21 or T2P state of the next bus cycle that requires external READ Y to terminate the bus cycle For example the processor may start an internal bus cycle go through a few idle states perform another internal cycle then a cy cle in which the Chip select Unit generates READY run through a few more idle states and then finally do a cycle in which READY needs to be generated by external logic LBA goes active in the first T2 state of the first internal cycle and stay active through the next two cycles even during all the idle states in between and go inactive at the rising edge of PHI in the first T2 21 or state of the final cycle the one that requires an external READ Y to terminate NOTE LBA is deasserted during HOLD cycles Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Figure 6 4 shows internal and external bus cycles Idle Id
82. signal when the activates its REFRESH signal This causes the controller to drive the refresh address gen erated by the RCU onto the DRAM address inputs refreshing the specified DRAM row With this method the controller need not assert the CAS signal whenever the REFRESH signal is active The CAS before RAS method requires that the DRAM device contain an internal counter to determine the DRAM row addresses To perform a refresh cycle using the CAS before RAS method the controller must generate a CAS signal followed by a RAS signal when the RCU activates its REFRESH signal With this method the DRAM device generates its own refresh addresses and the RCU provides the REFRESH signal If the CS6 REFRESH pin is being used for its CS6 function another way of identifying a re fresh cycle is to look at the states of the bus status signals M IO D C and W R shown in Table 6 2 on page 6 5 and the byte enable signals BHE and BLE and D C t are high W R is low and both BHE and BLE are inactive during a refresh cycle These signals can be used by the DRAM controller to initiate a DRAM refresh cycle 15 2 REFRESH CONTROL UNIT OVERVIEW The RCU includes an interval timer unit a control unit and an address generation unit Figure 15 1 The interval timer unit uses a refresh clock interval register and a 10 bit interval counter to create a periodic signal timeout The control unit uses this signal to initiate p
83. when channel 1 s request DREQ1 input is connected to an internal peripheral 6 4 D1REQ2 0 DMA Channel 1 Request Connection Connects one of the eight possible hardware sources to channel 1 s request input DREQ1 000 DRQ1 pin external peripheral 001 SIO channel 1 s receive buffer full signal RBFDMA1 010 SIO channel 0 s transmit buffer empty signal 011 SSIO receive holding buffer full signal SSRBF 100 TCU counter 2 s output signal OUT2 101 SIO channel 0 s receive buffer full signal RBFDMAO 110 SIO channel 1 s transmit buffer empty signal TXEDMA1 111 SSIO transmit holding buffer empty signal SSTBE DOMSK DMA Acknowledge 0 Mask 0 DMA channel 0 acknowledge DMAACKO signal is not masked 1 Masks DMA channel 0 s acknowledge DMAACKO signal Useful when channel 0 s request DREQO input is connected to an internal peripheral 2 0 DOREQ2 0 DMA Channel 0 Request Connection Connects one of the eight possible hardware sources to channel 0 s request input DREQO 000 DRQO pin external peripheral 001 SIO channel 0 s receive buffer full signal RBFDMAO 010 SIO channel 1 s transmit buffer empty signal TXEDMA1 011 SSIO transmit holding buffer empty signal SSTBE 100 TCU counter 1 s output signal OUT1 101 SIO channel 1 s receive buffer full signal RBFDMA1 110 SIO channel 0 s transmit buffer empty signal TXEDMA
84. 0 rb control amp Oxdf if TimerO 0 rb control 0x02 if Timerl 0 rb control 0x04 if Timer2 0 rb control 0x08 SetEXRegByte TMRCON rb control SetUp ReadBack BRK KK KKK I KK IK e e RR A KKK Kk kk kk Ck Kk Ck kk Ck Kk k KK Ck Ck kk k k Kk Ck k k k ke kk ko I kk k ke kk OK CounterLatch Description This function invokes a counter latch command for the specified timer and returns the latched counter value Parameters Timer Unit number of timer whose counter value is to be latched 10 37 Intel386 EX EMBEDDED PROCESSOR USER S MANUAL intel Returns Counter Value of specified timer Assumptions This function assumes that the R W format is configured to be LSB first then MSB Syntax WORD Counter Value Counter Value CounterLatch TMR 1 Real Protected Mode No changes required eK RR AR I KR A ARR AIA WORD CounterLatch BYTE Timer BYTE control_word 0 BYTE CounterL CounterH WORD Counter control_word Timer lt lt 6 control word amp 0xc0 SetEXRegByte TMRCON control word Select which counter switch Timer case TMR 0 CounterL GetEXRegByte TMRO CounterH GetEXRegByte TMRO break case _ CounterL GetEXRegByte TMR1 CounterH GetEXRegByte TMR1 break case TMR 2 CounterL GetEXRegByte TMR2 CounterH GetEXRegByte TMR2 break Counter W
85. 0 P20 0 0 0 P3 0 0 1 DCDO 1 CSO 1 mux Bit PINCFG Value Pins w o Muxes Pins w o Muxes X 7 Reserved R DRQO X TMRCLKO 6 0 CS6 0 DCD1 INT4 X 1 REFRESH DRQt1 TMRGATEO 5 0 Coprocessor Sigs 0 RXD1 X INT5 X 1 TMR2 Signals DSR1 TMRCLK1 4 0 DACKO 1 STXCLK X INT6 X 12 CS5 RI1 TMRGATE1 3 0 EOP 1 SSIORX X INT7 X 1 2 CTS1 2 0 DACK1 1 1 TXD1 NOTES 1 0 SRXCLK 1 1 PEREQ BUSY ERROR 1 DTR1 2 TMROUT2 TMRCLK2 TMRGATE2 0 0 SSIOTX 1 1 RTS1 5 30 Table 5 4 Example Pin Configuration Registers intel DEVICE CONFIGURATION Bit 4 DMACFG Value 7 0 Enables DACK1 at chip pin 1 12 Disables DACK1 at chip pin 6 4 000 DRQ1 pin external peripheral connected to DREQ1 000 001 SIO channel 1 s receive buffer full signal RBFDMA1 connected to DREQ1 010 SIO channel 0 s transmit buffer empty signal TXEDMAO to DREQ1 011 SSIO receive holding buffer full signal SSRBF to DREQ1 100 TCU counter 2 s output signal OUT2 to DREQ1 101 SIO channel 0 s receive buffer full signal RBFDMAO to DREQ1 110 SIO channel 1 s transmit buffer empty signal TXEDMA1 to DREQ1 111 5510 transmit holding buffer empty signal SSTBE to DREQ1 3 0 Enables DACKO at chip pin 1 1 Disables DACKO at chip 2 0 000 DRQ O pin external peripheral connected to DREQO 000 001 SIO channel 0 s receive buffer full signal RBF
86. 0 fine CS5 0x10 fine DACKO 0 fine TIMER2 0x20 fine COPROC 0 fine REFRESH 0x40 fine CS6 0 Port I O Function Definitions BYTE Porti BYTE PortDir2 BYTE PortLtc2 ern void Init IOPorts Pin configuration defines Timer configuration fine TMR 0 0 fine TMR 1 fine TMR 2 2 fine TMRO IRQ 0 fine TMR1 IRQ 10 fine TMR2 IRQ 11 Timer Modes fine TMR TERMCNT 0 fine TMR 1SHOT 1 1 fine TMR RATEGEN 2 1 fine TMR SQWAVE 3 1 fine TMR SW TRIGGER 4 lt lt 1 fine HW TRIGGER 5 1 Count Type fine TMR CLK BCD i fine TMR CLK BIN 0 Timer Pin Configuration fine TMR CLK INTRN 0 fine TMR CLK EXTRN 0 1 0 BYTE Port2 EXAMPLE CODE HEADER FILES BYTE Port3 BYTE PortDirl BYTE PortDir3 BYTE PortLtcl BYTE PortLtc3 defines OKO IK ke ke ke ke ke e e X ek 4 Master IRQO IRQ Slave IRQ2 IRQ Slave IRQ3 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel define TMR GATE EXTRN 0x2 define TMR OUT ENABLE 0x1 define TMR_OUT_DISABLE 0 define TMR ENABLE 1 define TMR DISABLE 0 Timer Macros Definitions define DisableTimer SetEXRegByte TMRCFG GetEXRegByte TMRCFG 0x80 define EnableTimer _SetEXRegByte TMRCFG GetEXRegByte TMRCFG amp 0x7f Timer Function Definitions extern int InitTimer int Unit WORD Mode BYTE Inputs
87. 10 32 b s t h m from DX port OL OT LOW LODS Load byte word 5 5 b h to AL AX EAX OT OW MOVS Move byte word 010010w 7 Yd b h OUTS Output 0110 131 18 11 33 b s t h m byte word to DX port SCAS Scan byte word 010 1w 7 7 b h STOS Store byte word 4 4 b h from AL AX EX VOLO Tw XLAT Translate String 1010111 5 5 h REPEATED STRING MANIPULATION Repeated by count in CX or ECX REPE CMPS Compare string find non match 11110011 1010011w CIk Count 5 9n 5 9n b h Virtual find match 10010 1010011w 8086 Mode 2 9n 5 9n b h INS Input string 11110010 0110110w TOTEEN irre ens b s t h m 324 6n REP LODS Load string 10010 1010110w 5 6n 5 6n b h REP MOVS Move 0010 1010010w 7 4n 744n b h string REP OUTS Output 0010 0110 W 130 8 16 8 10 8n b s t h m string 31 8n REPE SCAS Scan 5 8n 5 8n b h string 0011 1010 w Find non AL AX EAX REPNE SCAS Scan 5 8n 5 8n b h string 0010 1010 Find AL AX EAX REP STOS Store 0010 1010101w 5 5n 5 5n b h string BIT MANIPULATION BSF scan bit forward 00001111 10111100 mod reg r m 10 10 3n b h BSR scan bit reverse 00001111 10111101 mod reg r m 10 3n 10 3 b h BT test bit register memory 00001111 10111010 mod 100 r m immed 3 6 3 6 b h immediate 8 bit data E 9 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Table E 1 Instruction Set Summary
88. 11 Clock management register addresses 4 19 D 5 Clock synchronization 8 3 Code Prefetch Unit 3 4 CompuServe forums 1 7 Configuration bus arbiter 5 3 5 5 core 5 21 5 22 device 5 1 5 37 DMA controller 5 3 example 5 28 5 33 I O ports 5 23 5 25 5 26 5 27 9 18 10 22 11 18 11 19 11 20 14 16 D 43 D 44 D 45 interrupt control unit 5 7 pins 5 23 5 27 Port92 5 22 procedure 5 28 refresh control unit 5 3 serial I O unit 5 14 serial synchronous I O unit 5 18 timer counter unit 5 11 worksheets 5 34 5 37 Core configuring 5 21 5 22 Core architecture 2 1 Core overview CX enhancements 3 1 Internal architecture 3 2 CPU only reset 5 22 B 4 CSU See Chip select unit Customer service 1 6 CX internal architecture 3 2 Deassert defined 1 4 Decoding techniques I O address 4 6 Design considerations clock and power management unit 8 11 input output ports 16 10 interrupt control unit 9 29 9 30 JTAG test logic unit 18 14 refresh control unit 15 11 synchronous serial I O unit 13 25 Device configuration 5 1 5 37 procedure 5 28 register addresses 4 19 D 5 worksheets 5 34 5 37 DMA controller 12 1 12 61 block diagram 12 2 configuring 5 3 departures from PC AT architecture B 1 B 3 DMACLR command 12 50 DMACLRBP command 12 50 DMACLRMSK command 12 50 DMACLRTC command 12 50 interrupts 12 26 12 27 operation 12 5 12 27 8237A compatibility 12 27 basic refresh cycle 15 5
89. 11 TMRCFG Register Design 0 96 5 12 INTCFG Register Design em ene 5 37 5 13 SIOCFG Register Design 5 37 6 1 Bus Interface Unit Signals diving een dtc med ret ever rd deu 6 3 6 2 Bus Stat s Definitions tent rere a tete nde e e e e quada 6 5 6 3 Sequence of Nonaligned Bus Transfers sess 6 10 7 1 CRO Bits Cleared Upon Entering 7 3 7 2 SMM Processor State Initialization em 7 4 7 8 Relative Priority of Exceptions and Interrupts sese 7 7 8 1 Clock and Power Management Registers 8 6 8 2 Clock and Power Management Signals see 8 6 9 1 82C59A Master and Slave Interrupt 9 5 9 2 ICU Registers eee Ere ic e P De nro 9 16 10 1 TCU Signals T HERR ERG 10 2 TCU Associated Registers e seite eee teet Sin Pre tre she dd RU etude Get e ER Pte EU 10 4 10 3 Operations Caused by GATEn rite ett e e a 10 6 10 4 GATEn Connection 10 20 10 5 Minimum and Maximum Initial Counts puni O 10 6 Results of Multiple Read back Commands Without Reads 10 33 11 1 SIO Signals ie endete p
90. 1111011w 000 immediate data 2 5 5 h register memory immediate data and 2 2 accumulator short 1010100w form cia OR register to register 000010dw modreg r m 2 2 register to memory 0000100w modreg r m rY 7 b h memory to register 0000101w modreg r m 6 6 b h immediate t 1000000w mod 00 1 r m immediate data e d 2 h register memory immediate to accumu 9 9991 40w immediate data 2 lator short form XOR Exclusive or register to register 001100dw modreg r m 2 2 register to memory 0011000w modreg r m Td b h memory to register 0011001w modreg r m 6 6 b h immediate to 1000000w 41101 immediate data BTS SH j h register memory immediate to accumu 9 9 4 4910w immediate data 2 2 lator short form NOT Invert 1111011w mod0 10 rm 28 b h register memory E 8 intel INSTRUCTION SET SUMMARY Table E 1 Instruction Set Summary Sheet 8 of 19 Clock Count Notes Real Pro Real Pro Ad tected Ad tected i ress Virtual dress Virtual Instruction Format d Mode Ad Mode Ad or dress or dress Virtual Mode Virtual Mode 8086 8086 Mode Mode STRING MANIPULATION INSTRUCTIONS CIk Count Virtual CMPS Compare 8086 Mode 10 10 b h byte word 010011w INS Input byte word 130 17
91. 13 25 D 60 Index 7 INTEL386 EX MICROPROCESSOR USER S MANUAL SSIOTBUF 13 16 13 24 D 61 TBRn 11 15 11 23 D 61 5 13 10 4 10 21 D 62 TMRCON 10 4 10 25 10 28 10 30 D 63 TMRn 10 4 10 26 10 29 10 32 D 64 D 65 UCSADH 14 14 14 17 D 8 UCSADL 14 14 14 18 D 9 UCSMSKH 14 14 14 19 D 10 UCSMSKL 14 14 14 20 D 11 WDTCLR 17 7 WDTCNTH 17 7 17 8 D 67 WDTCNTL 17 7 17 8 D 67 WDTRLDH 17 7 17 10 0 68 WDTRLDL 17 7 17 10 D 68 WDTSTATUS 17 7 17 9 D 69 reload event 17 4 Reserved bits defined 1 5 Reset considerations 8 11 CPU only B 4 Resume instruction RSM 7 15 RSM See Resume instruction S Scratch pad registers SCRz 11 32 D 56 Segment Descriptor Cache 3 5 Segmentation Unit 3 4 3 5 SERCLK 8 1 8 2 11 1 11 4 11 21 13 1 13 5 13 18 Serial I O unit 11 1 11 45 block diagram 11 2 configuring 5 14 departure from PC AT architecture B 3 DMA service 5 3 5 5 operation 11 4 11 14 baud rate generator 11 4 11 5 data transmission process flow 11 8 diagnostic mode 11 12 interrupt sources 11 13 modem control 11 12 receiver 11 9 11 10 transmitter 1 1 6 11 8 overview 11 1 11 3 Index 8 intel programming accessing multiplexed registers 11 16 considerations 11 32 DLHn register 11 22 DLLz register 11 22 register 11 27 register 11 28 LCRn 11 25 D 36 LCRz register 11 25 LSRn 11 26 D 37 LSRn register 11 26 MCRn 11 30 D 38
92. 2 emen enne 12 37 12 3 8 Mode 1 Register 12 38 12 3 9 Mode 2 Register 2 12 40 12 3 10 Software Request Register DMASRR sese 12 42 12 3 11 Channel Mask and Group Mask Registers DMAMSK and DMAGRPMSK 12 44 12 3 12 Bus Size Register DMABSR sssseee eene em eene rennen 12 46 12 3 18 Chaining Register DMACHR seem emm ei 12 47 12 3 14 Interrupt Enable Register DMAIEN seem 12 48 12 3 15 Interrupt Status Register 5 12 49 12 3 16 Software Commands enne emeret rre 12 50 12 4 DESIGN 7 12 50 12 5 PROGRAMMING 12 50 12 5 1 DMA Controller Code Examples eene em emen 12 51 CHAPTER 13 SYNCHRONOUS SERIAL I O UNIT 13 1 1 SSO Signals 5i nete 1322 5 5 tete cm xn rn ast ng iei 1 O79 13 2 1 Baud rate Generator 2 13 5 19 2 2 TRANSMIS otro b te Fea ep t pin 13 2 2 1 Transmit Mode using Enable Bit seem DOOD 19 2 2 2 Autotransmit MOde it ioo vot ep voe ve ra vere o Fe eie S YER ue 13 12 13 2 2 3 Slave ere eee ciet rea ro reis dr re TE c dea sva 19 12
93. 34 World Wide Web 1 7 INDEX Index 11
94. 4 1 1 Intel386 Processor Core Architecture Registers These registers are a superset of the 8086 and 80286 processor registers All 16 bit 8086 and 80286 registers are contained within the 32 bit Intel386 processor core registers A detailed de scription of the Intel386 processor architecture base registers can be found in the Intel386 SX Microprocessor Programmer 5 Reference Manual order number 240331 4 1 2 Intel386 EX Processor Peripheral Registers The Intel386 EX processor contains some peripherals that are common and compatible with the PC AT system architecture and others that are useful for embedded applications The peripheral registers control access to these peripherals and enable you to configure on chip system resources such as timer counters power management chip selects and watchdog timer All peripheral registers reside physically in the expanded I O address space addresses 0 000 OFFFFH Peripherals that are compatible with PC AT system architecture can also be mapped into DOS 1 0 address space addresses 10 bit decode The following rules apply for accessing peripheral registers after a system reset Registers within the DOS I O address space are accessible Registers within the expanded I O address space are accessible only after the expanded I O address space is enabled 4 2 ADDRESS SPACE FOR PC AT SYSTEMS The Intel386 EX processor s I O address space is 64 Kbytes On PC AT plat
95. 5 4 15 Peripherals summary 2 3 Physical address space 3 1 Pin configuration 5 23 PINCFG 5 24 10 23 11 17 12 31 13 17 14 15 D 46 Pin descriptions 1 10 Pin states after reset and during idle powerdown and hold A 9 Pipelined instructions defined 3 2 Port configuration 5 25 11 18 D 43 P2CFG 5 26 11 19 14 16 D 44 P3CFG 5 27 9 18 10 22 11 20 D 45 PnCFG 16 7 PnDIR 16 8 D 47 PnLTC 16 8 D 48 PnPIN 16 9 D 48 PORT92 5 22 D 50 PORT92 register addresses 4 17 D 3 Power management controlling modes 8 8 17 4 17 6 logic 8 3 8 7 programming PWRCON 8 8 17 11 D 51 register addresses 4 19 D 5 See also Idle mode powerdown mode system management mode Powerdown mode considerations 8 13 SMM interaction with 8 5 timing diagram 8 11 Powerup Built in self test 8 12 reset 8 12 Prefetch Queue 3 4 Priority of exceptions and interrupts 7 7 Programmed operating mode 9 8 Programming chip select unit 14 13 14 20 clock and power management unit 8 7 8 10 DMA controller 12 28 12 51 ESE bit 4 8 Index 6 interrupt control unit 9 32 RCU 15 6 15 10 REMAPCFG example 4 8 serial I O unit 11 15 11 32 SSIO 13 17 13 25 timer counter unit 10 20 10 33 watchdog timer unit 17 7 17 12 Programming considerations chip select unit 14 22 DMA controller 12 50 serial I O unit 11 32 timer counter unit 10 33 Protected mode 9 8 Protection Test Unit 3 5 PSCLK 8 1 8 2 8 7 1
96. BYTE Output WORD InitCount int Enable extern void SetUp ReadBack BYTE Timer0 BYTE Timerl BYTE Timer2 BYTE GetStatus BYTE GetCount extern WORD CounterLatch BYTE Timer extern WORD ReadCounter BYTE Timer void interrupt far TimerISR void RR KKK KK KR ke e e e k SSIO configuration defines Ok kk kk ke ke ke ke e e e e KKK define SSIO TUE 0x80 Transmit Underflow Error define SSIO THBE 0x40 Transmit Holding Buffer Empty define SSIO TX IE 0x20 Transmit Interrupt Enable define SSIO TX ENAB 0x10 Transmitter Enable define SSIO_ROE 0x08 Receive Overflow Error define SSIO_RHBF 0x04 Receive Holding Buffer Full define SSIO_RX_IE 0x02 Receive Interrupt Enable define SSIO_RX_ENAB 0x01 Receiver Enable define SSIO TX MASTR 0x02 Transmit Master Mode define SSIO RX MASTR 0x01 Receive Master Mode define SSIO TX SLAVE 0 define SSIO RX SLAVE 0 define SSIO CLK SERCLK 0 01 Baud Rate Clocking Source SERCLK CLK2 4 define SSIO CLK PSCLK 0x00 Baud Rate Clocking Source PSCLK CLK2 2 CLKPRS 2 define SSIO BAUD ENAB 0x80 Enable Baud Rate Generator SSIO Function Definitions extern void InitSSIO BYTE Mode BYTE MasterTxRx BYTE BaudValue intel EXAMPLE CODE HEADER FILES BYTE PreScale extern WORD SSerialReadWord BYTE MasterSlave extern void SSerialWriteWord WORD Ch BYTE MasterSlave void interrupt far SSIO_ISR void
97. Bit Number Mnemonic Function 7 5 Reserved for compatibility with future devices write zeros to these bits 4 LOOP Loop Back Test Mode 0 Normal mode 1 Setting this bit puts the SlOn into diagnostic or loop back test mode This causes the SIO channel to setits transmit serial output TXDn disconnect its receive serial input RXDn from the package pin loop back the transmitter shift register s output to the receive shift register s input disconnect the modem control inputs CTSn DSRn Rin and DCDn from the package pins force modem control outputs RTS and DTRn to their inactive states connects MCRn bits to MSRn bits 3 2 OUT2 1 Test Bits In diagnostic mode bit 4 1 these bits control the ring indicator RIn and data carrier detect DCDn modem inputs Setting OUT1 activates the internal RIn bit clearing OUT1 deactivates the internal Rin bit Setting OUT2 activates the internal DCDn bit clear OUT2 deactivates the internal DCDn bit In normal user mode bit 4 0 OUT1 has no effect and OUT2 in conjunction with INTCFG 5 6 selects internal SIO interrupt or external interrupt See Table 5 1 on page 5 8 for the configuration options 1 RTS Ready to Send The function of this bit depends on whether the SIOn is in diagnostic mode MCRn 4 1 internal connection mode or standard mode In diagnostic mode setting this bit activates the internal CTS n bit clearing this bit deactivates the intern
98. Chapter 8 Interrupt Control Unit explains how to do this 17 2 WATCHDOG TIMER UNIT OPERATION After a device reset the WDT begins counting down in general purpose timer mode Unless you change the mode change the reload value or disable it the WDT times out and asserts WDTOUT after 4 million 222 processor clock cycles PH1 or CLKOUT cycles The 32 bit down counter decrements on every processor clock cycle When the down counter reaches zero the 8 state binary counter drives the WDTOUT pin high for eight processor clock cycles 16 CLK2 cycles to signal the timeout An internal signal carries the inverted value of the WDTOUT pin to the interrupt control unit the slave s IR7 line A WDT timeout can reset the system or generate an interrupt request depending on how WDTOUT is used in your system 17 3 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel The reload registers hold a user defined value that reloads the down counter when one of the fol lowing reload events occurs In watchdog mode when system software executes a specific instruction sequence called lockout sequence to the WDTCLR location nbus monitor mode when the bus interface unit asserts ADS nall modes when the down counter reaches zero Software can read the status register to determine the mode of the WDT and can read the count registers to determine the current value of the down counter 17 2 1 Idle and Powerdown modes I
99. Count 2406 01 Figure 10 15 Mode 3 Writing New Count Without a Trigger 10 15 Intel386 EX EMBEDDED PROCESSOR USER S MANUAL intel 10 2 5 Mode 4 Software triggered Strobe Initializing a counter for mode 4 drives the counter s OUT signal high and initiates counting A count is loaded the CLKINn pulse following a count write When the counter reaches zero OUTn strobes low for one clock pulse The counter rolls over and continues counting but does not strobe low when it reaches zero again The counter strobes low only the first time it reaches zero after a count write A high level on a counter s GATEn signal enables counting a low level on a counter s GATEn signal disables counting Mode 4 s basic operation is outlined below and shown in Figure 10 16 1 Aftera control word write OUTn is driven high 2 the CLKINz pulse following the count write the count is loaded 3 Oneach succeeding CLKIN pulse the count is decremented 4 When the count reaches zero OUTn is driven low 5 On the following CLKINn pulse OUTn is driven high NOTE Writing a count of N causes to strobe low in N 1 CLKINz pulses provided GATEn remains high OUTn remains low for one CLKINnz pulse then goes high Control Word 18H Count 3 Writes to C ee CLKINn GATEn OUTn no cut 9 2 2 0000 rrrr
100. DMACLRMSK OxFOOE define DMAGRPMSK OxFOOF define DMAOREOL OxF010 define DMAOREQH OxF011 define DMAlREOL 0 012 define DMA1REQH OxF013 define DMABSR OxF018 define DMACHR OxF019 define DMAIS OxF019 define DMACMD2 OxF01A define DMAMOD2 0 01 define DMAIEN OxFO1C define DMAOVFE 0 01 define DMACLRTC OxFO1E define DMAITARPL OxF083 define DMAILTARPH OxF085 define DMAOTARPH OxF086 define DMAOTARPL OxF087 define DMAOBYCH OxF098 define DMAIBYCH OxF099 DMA UNIT REG define DMAOTARDOS 0x0000 define DMAOBYCDOS 0 0001 define DMAITARDOS 0 0002 define DMAIBYCDOS 0 0003 define DMACMD1DOS 0x0008 define DMASTSDOS 0x0008 define DMASRRDOS 0x0009 define DMAMSKDOS 0x000A define DMAMOD1DOS 0x000B define DMACLRBPDOS 0x000C define DMACLRDOS 0x000D define DMACLRMSKDOS 0x000E define DMAGRPMSKDOS 0x000F define DMAITARPLDOS 0x0083 define DMAOTARPLDOS 0x0087 define PORT92 OxF092 define PORT92DOS 0x0092 EXAMPLE CODE HEADER FILES C 5 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel C 2 EXAMPLE CODE DEFINES BOR KR RK ke kk ke ke kk ke ke ke ke e ke ke ee Global typedef 5 kk ko ke kk G typedef typedef typedef unsigned char BYTE 8 bit value unsigned short WORD 16 bit value unsigned long DWORD 32 bit value KKK KK kk kk kk kk e e Global Used defines CK Ck ck ckok ko A Error Flags define define define define define define define define define define defin
101. DS ES FS GS not present If the SS register is loaded and a stack segment not present is detected an exception 12 stack segment limit violation or not present occurs All segment descriptor accesses in the GDT or LDT made by this instruction will automatically assert LOCK to maintain descriptor integrity in multiprocessor systems JMP CALL INT RET and IRET instructions referring to another code segment will cause an exception 13 general protection violation if an applicable privilege rule is violated An exception 13 fault occurs if CPL is greater than 0 0 is the most privileged level An exception 13 fault occurs if CPL is greater than IOPL The IF bit of the flag register is not updated if CPL is greater than IOPL The IOPL and VM fields of the flag register are updated only if CPL 0 The PE bit of the MSW CRO cannot be reset by this instruction Use MOV into CRO when resetting the PE bit Any violation of privilege rules as applied to the selector operand does not cause a protection exception rather the zero flag is cleared If the coprocessor s memory operand violates a segment limit or segment access rights an exception 13 fault general protection exception will occur before the ESC instruction is executed An exception 12 fault stack segment limit violation or not present will occur if the stack limit is violated by the operand s starting address The destination of a JMP CALL INT RET or IRET must be in the
102. EX processor provides many possible signal to pin connections as well as periph eral to peripheral connections This chapter describes the available configurations and how to configure them This chapter is organized as follows ntroduction see below Peripheral Configuration page 5 3 Pin Configuration page 5 23 Device Configuration Procedure page 5 28 Configuration Example page 5 28 5 1 INTRODUCTION Device configuration is the process of setting up the microprocessor s on chip peripherals for a particular system design Specifically device configuration consists of programming registers to connect peripheral signals to the package pins and interconnect the peripherals The peripherals include the following DMA Controller DMA Interrupt Control Unit ICU Timer counter Unit TCU Asynchronous Serial I O Units 5100 SIO1 Synchronous Serial I O Unit SSIO Refresh Control Unit RCU Chip select Unit CSU Watchdog Timer Unit WDT In addition the pin configuration registers control connections from the coprocessor to the core and pin connections to the bus arbiter In this chapter the terms peripheral and on chip peripheral are used interchangeably An off chip peripheral is external to the Intel386 EX processor 5 1 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Figure 5 1 shows Peripheral A and its connections to other peripherals and the packa
103. FOOFH 000FH Byte DMAGRPMSK 03H F010H Byte DMAOREQO 1 XX F011H Byte DMAOREQ2 3 XX F012H Byte DMA1REQO0 1 XX F013H Byte DMA1REQ2 3 XX F014H Reserved F015H Reserved F016H Reserved F017H Reserved NOTES 1 Byte pointer in flip flop in DMA determines which register is accessed 2 Shaded rows indicate reserved areas 4 15 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Table 4 2 Peripheral Register Addresses Sheet 2 of 6 intel pi sith be a Parise NEM Register Name Reset Value F018H Byte DMABSR X1X10000B F019H Byte DMACHR DMAIS 00H F01AH Byte DMACMD2 08H F01BH Byte DMAMOD2 00H F01CH Byte DMAIEN 00H F01DH Byte DMAOVFE OAH F01EH Byte DMACLRTC Not a register Master Interrupt Controller FO20H 0020H Byte ICW1m IRRm ISRm XX OCW2m OCW3m F021H 0021H Byte ICW2m ICW3m ICW4m XX OCW1m POLLm Address Configuration Register 0022H 0022H Word REMAPCFG 0000H Timer counter Unit F040H 0040H Byte TMRO XX F041H 0041H Byte TMR1 XX F042H 0042H Byte TMR2 XX F043H 0043H Byte TMRCON XX DMA Page Registers F080H Reserved F081H 0081H Reserved F082H 0082H Reserved F083H 0083H Byte DMA1TAR2 XX F084H Reserved F085H Byte DMA1TAR3 XX F086H Byte DMAOTAR3 XX F087H 0087H Byte DMAOTAR2 XX F088H Reserved F089H 0089H Reserved F08AH 008AH Reserved F08BH 008BH Reserved F08CH Reserved NOTES 1 Byte pointer in flip flop in DMA de
104. Get RCUCounterValue Real Protected Mode No changes required eK RR AR IR RAR RR kk AA ARR Kk Ck Kk extern WORD Get_RCUCounterValue void WORD Counter Value Counter Value _GetEXRegWord RFSCON amp Ox3ff Counter value contained in bits RFSCON9 0 return Counter Value Get RCUCounterValue 15 16 intel 1 6 INPUT OUTPUT PORTS 16 INPUT OUTPUT PORTS Input Output I O ports allow you to transfer information between the processor and the sur rounding system circuitry I O ports are typically used to read system status monitor system op eration output device status configure system options and generate control signals The Intel386 EX processor s I O port pins are multiplexed with peripheral pin functions With this multiplexed arrangement you can use just those peripheral functions required for your design and use any remaining pins for general purpose I O For example this device offers eight chip select lines five of which CSO CS4 are multiplexed with I O port pins If your design does not need all eight chip selects you can use up to five pins 2 0 2 4 for I O This chapter describes the I O ports and explains how to configure them The information is ar ranged as follows Overview see below Register Definitions page 16 6 Design Considerations page 16 10 Programming Considerations page 16 11 16 1 OVERVIEW The Intel386 EX process
105. HALT restart slot in the SMM State Dump area the SMM handler can redirect the instruc tion pointer past the HALT instruction nude 2 State Save Figure 7 3 SMI During HALT 1 2508 01 7 8 intel SYSTEM MANAGEMENT MODE 7 3 2 3 HALT Restart It is possible for SMI to break into the HALT state In some cases the application might want to return to the HALT state after RSM The SMM architecture provides the option of restarting the HALT instruction after RSM The word at address 03FF02H is the HALT restart slot The processor sets bit 0 of this location when the processor is in the HALT state while the SMI occurred If the SMM driver leaves this bit set then the processor re enters the HALT state when it exits from SMM When the driver clears this bit the processor continues execution with the instruction just after the interrupted HALT instruction 7 3 2 4 System Management Interrupt During I O Instruction Like the HALT restart feature the processor allows restarting I O cycles which have been inter rupted by an SMI This gives the system designer the option of performing a hardware I O cycle restart without having to modify either application operating system or BIOS software See Fig ure 7 4 When a SMI occurs during an I O cycle it then becomes the responsibility of the SMM handler to determine the source of the SMI If for example the source is the powered down I O devic
106. IR6 Connection 0 Connects Vss to the slave IR6 signal 1 Connects the INT7 pin to the slave IR6 signal 2 IR5 IR4 Internal Slave IR4 or IR5 Connection These depend on whether INTCFG 4 is set or clear 0 Connects Va to the slave IR5 signal 1 Connects either the INT6 pin or DMAINT to the slave IR5 signal 1 IR1 Internal Slave IR1 Connection 0 Connects the SSIO interrupt signal SSIOINT to the slave IR1 signal 1 Connects the INT5 pin to the slave IR1 signal 0 IRO Internal Slave IRO Connection 0 Connects Vas to the slave IRO signal 1 Connects the INT4 pin to the slave IRO signal D 34 intel D 32 IR SYSTEM REGISTER QUICK REFERENCE Instruction Register Reset State IR Using TRST 02H 2 0 INST3 INST2 INST1 INSTO Bit Bit Number Mnemonic Function 3 0 INST3 0 Instruction opcode At reset using TRST or after 5 TCK cycles with TMS held low this field is loaded with 0010 the opcode for the IDCODE instruction Instructions are shifted into this field serially through the TDI pin Table 18 4 lists the valid instruction opcodes D 35 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel D 33 LCRn Serial Line Control LCRO LCR1 LCRO LCR1 Expanded Addr F4FBH F8FBH read write ISA Addr 0 02FBH Reset State 00H 00H 7 0 DLAB SB SP EPS PEN STB WLS1
107. In service Register Figure 9 15 Operation Command Word 3 OCW3 9 27 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 9 3 10 Interrupt Request Register IRR This 8 bit read only register contains the levels requesting an interrupt to be acknowledged It is accessed using OCW3 see Figure 9 15 The highest request level is reset from the IRR when an interrupt is acknowledged Bits 7 0 of this register are the pending bits respectively of interrupt requests IR7 0 9 3 11 In Service Register ISR This 8 bit read only register contains the priority levels that are being serviced It is accessed us ing OCW3 see Figure 9 15 The ISR is updated when an End of Interrupt command is issued Bits 7 0 of this register are the in service bits respectively of interrupt requests IR7 0 9 3 12 Poll Status Byte POLL Read the poll status byte after issuing a poll command to determine whether any of the devices connected to the 82C59A require servicing Once the polling bit is set in OCW3 the Poll Status Byte of a particular 82C59A can be read by doing an access to any of the four addresses of that 82 59 Poll Status Byte master slave POLL master and slave Expanded Addr F020H FOAOH read only ISA Addr 0020H Reset State XXH XXH 7 0 INT L2 L1 10 PIC Function Number Mnemonic 7 INT Interrupt Pending 0 No request pending 1
108. Indicates that a device attached to the 82C59A requires servicing 6 3 Reserved These bits are undefined 2 0 L2 0 Interrupt Request Level When bit 7 is set these bits indicate the highest priority IR signal that requires servicing When bit 7 is clear i e no request is pending these bits are indeterminate Figure 9 16 Poll Status Byte POLL 9 28 intel INTERRUPT CONTROL UNIT 9 4 DESIGN CONSIDERATIONS The following sections discuss some design considerations 9 4 1 Interrupt Acknowledge Cycle When the core receives an interrupt request from the master it completes the instruction in progress and any succeeding locked instructions then initiates an interrupt acknowledge cycle The interrupt acknowledge cycle generates an internal interrupt acknowledge INTA signal that consists of two locked pulses Figure 9 17 This INTA signal is connected to the internal 82 59 interrupt acknowledge inputs On the falling edge of the second INTA the 82 59 sets its interrupt in service bit It then clears its interrupt pending bit on the rising edge of the second INTA On the second INTA falling edge the addressed 82C59A determined by the master s cascade signals also drives the interrupt vector number on the data bus INTA Vector Number Figure 9 17 Interrupt Acknowledge Cycle A2430 01 9 4 2 Interrupt Detection The processing of an interrupt begins with
109. Interrupt service routine 6 23 Interrupts and exceptions relative priority 7 7 J JTAG reset 8 12 JTAG test logic unit 18 1 18 14 block diagram 18 2 design considerations 18 14 operation 18 3 18 9 boundary scan register 18 9 bypass register 18 8 identification code register 18 8 instruction register 18 7 test access port controller 18 4 18 6 instructions 18 7 18 8 state diagram 18 6 INDEX overview 18 1 18 2 Resetting upon power up 18 3 testing 18 10 18 11 bypassing devices on a board 18 10 disabling the output drivers 18 11 identifying the device 18 10 sampling device operation and preloading data 18 10 testing the interconnections 18 10 timing information 18 12 18 13 L Literature 1 8 Literature ordering 1 5 1 8 LOCK 6 34 6 35 lockout sequence 17 4 Manual contents summary 1 1 1 2 Measurements defined 1 3 Misaligned data transfers 6 9 Mode 12 22 N Naming conventions 1 3 1 4 Non page mode 15 13 Nonspecific EOI command 9 14 Notational conventions 1 3 1 4 Numbers conventions 1 3 O Operand alignment aligned 6 9 misaligned 6 9 Operating mode 9 8 P Page mode 15 12 Paging Unit 3 4 3 5 PC AT Address defined 1 4 PC AT system architecture departures from B 1 Performance 2 1 Peripherals internal configuring 5 3 5 37 DOS compatible 4 2 embedded application specific 4 2 Index 5 INTEL386 EX MICROPROCESSOR USER S MANUAL register locations 4
110. LSRO for i 0 i lt count Wait until buffer is empty while GetEXRegByte StatusPortAddr amp SIO TX BUF EMPTY Write Character SetEXRegByte TransmitPortAddr mem i 11 40 intel ASYNCHRONOUS SERIAL UNIT SerialWriteMem BORK IK KKK IK KK IKK IA I KR IR AIR IRR IR ARR IRR IA IRR k k k IA k k k k k k k SerialO0 ISR Description Template Interrupt Service Routine for Serial Port0O interrupts This function identifies the cause of the interrupt and branches to the corresponding action Parameters None Not called by user Returns None Assumptions None Syntax Not a user function Real Protected Mode No changes required eK RR AA IRR KARR IIR AIA IRR kk Ck kk Ck void interrupt far Serial0_ISR void BYTE 0 15 0 msr0 iir0 GetEXRegByte IIRO switch iir0 amp 0x06 1 case 0 modem status signal msrO0 _GetEXRegByte MSRO if msr0 amp 0x08 amp amp msr0 amp 0x80 data carrier detect has been set 11 41 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel if msrO amp 0x04 amp amp msrO amp 0 40 ring indicator if msrO0 amp 0x02 amp amp msrO amp 0x20 data set ready bit has been set if msrO0 amp 0x01 amp amp msrO amp 0x10 clear to send signal has been set break case 1 Service TBE Routine for Interr
111. Mnemonic Function 7 4 Reserved for compatibility with future devices write zeros to these bits 3 2 PL1 0 Low Priority Level Set Use these bits to assign a particular bus request to the lowest priority level in fixed priority mode 00 Assigns channel 0 s request DREQO to the lowest priority level 01 Assigns channel 1 s request DREQ1 to the lowest priority level 10 Assigns the external bus master request HOLD to the lowest priority level Reserved 11 Sampling 0 Causes the DMA to sample the EOP input asynchronously 1 Causes the DMA to sample the end of process EOP input synchronously DREQn Sampling 0 Causes the DMA to sample the DREQn inputs asynchronously 1 Causes the DMA to sample the channel request DREQn inputs synchronously Figure 12 24 DMA Command 2 Register DMACMD2 12 37 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 12 3 8 Mode 1 Register DMAMOD1 Use DMAMODI to select a particular channel s data transfer mode and transfer direction and to enable the channel s auto initialize buffer transfer mode You can configure the DMA to modify the target address during a buffer transfer by clearing 2 2 then use DMAMODI 5 to specify how the channel modifies the address 12 38 intel DMA CONTROLLER DMA Mode 1 Expanded Addr DMAMOD1 ISA Addr 000BH
112. Mode Ad Mode Ad or dress or dress Virtual Mode Virtual Mode 8086 8086 Mode Mode CLD Clear direction 2 2 flag 11 00 CLI Clear interrupt 11 010 8 8 m enable flag CLTS Clear task 5 5 switched flag 0000 11 00000110 CMC Complement 1110101 2 2 carry flag LAHF Load AH into 00 11 2 2 flag POPF Pop flags 00 01 5 5 b h n PUSHF Push flags 00 00 4 4 b h SAHF Store AH into 3 3 flags 99 1 0 STC Set carry flag 11 001 2 2 STD Set direction flag 1111101 STI Set interrupt 11 011 8 8 enable flag ARITHMETIC INSTRUCTIONS ADD Add register to register 000000dw modreg r m 2 2 register to memory 0000000w modreg r m TS Te b h memory to register 0000001w modreg r m 6 6 b h immediate to 1 2 7 2 7 b h register memory 100000sw mod000r m immediate data immediate to accumu 2 2 lator short form 0000010w immediate data ADC Add with carry register to register 000100dw modreg r m 2 2 register to memory 0001000w modreg r m JU T b h memory to register 0001001w modreg r m 6 6 b h immediate to 2 7 2 7 b h register memory 100000sw mod010r m immediate data immediate to accumu x 2 2 lator short form 0001010w immediate data INC Increment register memory 1111111w mod000r m 2 6 2 6 b h register short form 01000 reg 2 2 4 intel Table E 1 Instruction Set Summary Sheet 4 of 19 INSTRUCTION SET SUMMARY
113. Mode Select These bits select an operating mode for the counter specified by bits 7 6 000 mode 0 001 mode 1 X10 mode 2 X11 mode 3 100 2 mode 4 101 2 mode 5 X is a don t care 0 CNTFMT Count Format This bit selects the count format for the counter specified by bits 7 6 0 binary 16 bits 1 binary coded decimal 4 decades Figure 10 25 Timer Control Register TMRCON Control Word Format 10 25 Intel386 EX EMBEDDED PROCESSOR USER S MANUAL 10 3 3 Writing the Counters intel Use the write format of a counter s Timer n register TMRn to specify a counter s count The count must conform to the write selection specified in the control word least significant byte only most significant byte only or least significant byte followed by the most significant byte You can write a new count to a counter without affecting the counter s programmed operating mode New counts must also conform to the specified write selection Timer n Write Format Expanded Addr F040H F041H TMRn n 0 2 F042H ISA Addr 0040H 0041H 0042H Reset State XXH 7 0 CV6 CV5 2 cvi cvo En Bit Function Number Mnemonic 7 0 CV7 0 Count Value Write a count value for the counter to these bits When writing the counter s count value follow the write selection specified in the counter s control word Figure 10 26 Timer n Registe
114. OKCKCkCKCkCkCkCKCkCk IRR A Kk Rok AA ARR IR k k k k k k k k void SetInterruptVector void far interrupt IntrProc void int Vector int IntrType void IntrType Reference to avoid compiler warning unsigned long far 0 Vector unsigned long IntrProc SetInterruptVector BRK KK KKK kk ke Ke Kk Ck Kk Ck Kk Ck KK Ck Ck Kk Ck AR kk k kk kk kk ko ke kc OK 9 40 intel INTERRUPT CONTROL UNIT Poll Command Description This routine issues a poll command which reads the poll status byte of the ICU Parameters Master or Slave Specifies which interrupt controller is polled Returns Current value of poll status byte Assumptions None Syntax in poll status poll status Poll Command Real Protected Mode No changes required IR AA ARR Kk AIA AR int Poll_Command int Master_or_Slave int poll_status if Master_or_Slave Master _SetEXRegByte OCW3M 0x0c Initiate polling sequence poll status GetEXRegByte ICW2M else SetEXRegByte OCW3S 0x0c Initiate polling sequence poll status _GetEXRegByte ICW2S return poll status Poll Command 9 41 intel 10 TIMER COUNTER UNIT 10 TIMER COUNTER UNIT The Timer counter Unit TCU has the same basic functionality as the industry standard 82C54 counter timer It contains three independent 16 bit down counters which can be driven by a pr
115. PCO 0 0 active mode 1 0 idle mode 0 1 powerdown mode 1 1 active mode D 51 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL D 50 RBRn Receive Buffer RBRO RBR1 RBRO RBR1 Expanded Addr F4F8H F8F8H read only ISA Addr 03F8H 02 8 Reset State XXH XXH 7 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RBO Bit Bit Functi Number Mnemonic uncuon 7 0 RB7 0 Receive Buffer Bits These bits make up the last word received The receiver shifts bits in starting with the least significant bit The receiver then strips off the asynchronous bits start parity and stop and transfers the received data bits from the receive shift register to the receive buffer NOTE The receive buffer register shares an address port with other SIO registers Bit 7 DLAB of the LCRn must be cleared in order to read the receive buffer register D 52 intel SYSTEM REGISTER QUICK REFERENCE D 51 REMAPCFG Address Configuration Register Expanded Addr 0022 REMAPCFG PC AT Address 0022 Reset State 0000H 15 8 ESE 7 0 S1R SOR ISR IMR DR TR Bit Bit i Number Mnemonic Function 15 ESE 0 Disables expanded I O space 1 Enables expanded I O space 14 7 Reserved 6 S1R 0 Makes serial channel 1 COM2 accessible in both DOS I O space and expanded I O space 1 Remaps serial channel 1 COM2
116. PSRAM devices have an interface that is similar to SRAM devices They are also pin compatible in many cases The two major differences between PSRAM and SRAM devices are PSRAM devices require a precharge inactive time between access cycles Since the Intel386 EX processor does not guarantee a minimum inactive time on it s CSn signals control logic is required to satisfy the PSRAM device s CE precharge time PSRAM devices have a RFSH input pin This signal activates an internal refresh cycle The REFRESH output of the Inte1386 EX processor can be connected directly to the PSRAM device s pin Intel386 EX Embedded Address Processor Logic RD WR REFRESH Note Control logic is necessary to satisfy the precharge time for the CE signal of the PSRAM The precharge time is specified by the PSRAM manufacturer A2854 02 Figure 6 17 Intel386 EX Processor to PSRAM Interface 6 42 intel BUS INTERFACE UNIT 6 6 4 Paged DRAM Interface External logic is required to interface the Intel386 EX processor to DRAM devices as shown in Figure 6 18 The PLD generates the RAS and CAS signals If RAS Only Refresh is being performed using the Refresh Control Unit of the processor then during a Refresh Cycle the PLD enables the Column Address Buffer and asserts the RAS signal shaded sections in the figure Refer to Chapter 6 BUS INTERFACE UNIT for more infor mation
117. RWmode WORD Count SetUp ReadBack 0 0 1 1 1 Configure Read Back command for timer2 latching both status and count Status ll GetEXRegByte TMR2 RWmode Status amp 0x30 Mask off bits that correspond to the Read Write Mode switch RWmode Read Counter Value according to configured R W format case 0x10 Read Write least significant byte only Count GetEXRegByte TMR2 break case 0x20 Read Write most significant byte only CountH GetEXRegByte TMR2 Count WORD CountH lt lt 8 break case 0x30 Read Write LSB first then MSB CountL GetEXRegByte TMR2 CountH GetEXRegByte TMR2 Count WORD CountH lt lt 8 CountL break eK RR AR RRR IRR AA KK CkCk IR AR IRR 10 41 intel 11 ASYNCHRONOUS SERIAL I O UNIT 11 ASYNCHRONOUS SERIAL I O UNIT The asynchronous serial I O SIO unit provides a means for the system to communicate with ex ternal peripheral devices and modems The SIO unit performs serial to parallel conversions on data characters received from a peripheral device or modem and parallel to serial conversions on data characters received from the CPU The SIO unit consists of two independent SIO channels each of which is compatible with National Semiconductor s NS16C450 This chapter is organized as follows Overview see below SIO Operation page 11 4 Register Definitions page 11 15 Programming Considerations page
118. Returns None Assumptions None Syntax Not called by user Real Protected Mode No changes required eR RR AA IR RR KARR IIR AIA ARR IRR IA ARR IRR IA void Service_THBE void Ime 2252 if value lt 79 13 32 intel SYNCHRONOUS SERIAL UNIT SetEXRegWord SSIOTBUF value valuett else Disable Transmitter and Transmitter interrupts for i 0 i lt 4000 i Delay so transmit begins before disable asm nop _SetEXRegByte SSIOCON1 _GetEXRegByte SSIOCON1 amp Oxcf Clear TEN TIE Service_THBE BRK KK KKK IKK IK I KKK I KR IR A IRR IR IR IRR IR k k k k k k k k k k k k k k Example Code showing SSIO transfer in which the transmitter is interrupt driven and the receiver is polled InitSSIO SSIO RX ENAB SSIO TX ENAB SSIO TX IE SSIO TX MASTR SSIO RX SLAVE 0 0 0 Setup SSIO interrupts SetEXRegByte INTCFG GetEXRegByte INTCFG amp Oxfd Slave IR1 is multiplexed SetIRQVector SSIO ISR 9 INTERRUPT ISR SSIO IR will be generated on Slave IR1 Disable8259Interrupt IR1 IR3 IR4 IR5 IR6 IR7 IRO IR2 IR3 IR4 IR5 IR6 1R7 Enable8259Interrupt IR2 IR1 Enable slave interrupt to master IR2 Enable slave IR1 enable Enable Interrupts Initialize SSIO Ports _SetEXRegByte PINCFG _GetEXRegByte PINCFG amp Oxfc SetEXRegByte SIOCFG GetEXRegByte SIOCFG amp Oxfb Fill up transmit buffer with first ch
119. SSIOCTR OxF48A CHIP SELECT UNIT Registers define CSOADL 0 400 define CSOADH OxF402 define CSOMSKL OxF404 define CSOMSKH OxF406 define CS1ADL OxF408 define CS1ADH OxF40A define CS1MSKL OxF40C define 51 5 OxF40E define CS2ADL OxF410 define CS2ADH 0 412 define CS2MSKL OxF414 define CS2MSKH OxF416 define CS3ADL OxF418 define CS3ADH OxF41A define CS3MSKL OxF41C define CS3MSKH OxF41E define CS4ADL OxF420 define CS4ADH 0 422 define CS4MSKL OxF424 define CS4MSKH OxF426 define CS5ADL OxF428 define CS5ADH OxF42A define CS5MSKL OxF42C define CS5MSKH OxF42E define CS6ADL OxF430 define CS6ADH OxF432 define CS6MSKL OxF434 define CS6MSKH OxF436 define UCSADL OxF438 define UCSADH OxF43A define UCSMSKL OxF43C define UCSMSKH OxF43E REFRESH CONTROL UNIT Registers define RFSBAD OxF4A0 define RFSCIR OxF4A2 define RFSCON OxF4A4 define RFSADD 0 4 6 POWER MANAGEMENT CONTROL Registers define PWRCON OxF800 define CLKPRS OxF804 DMA UNIT REGISTERS SLOT 15 ADDRESSES define DMAOTAR 0 000 define DMAOBYC OxF001 define DMAITAR 0 002 define DMA1BYC 0 003 4 tel ISTERS SLOT 0 ADDRESSES A20GATE AND FAST CPU RESET SLOT 15 ADDRESS A20GATE AND FAST CPU RESET SLOT 0 ADDRESS define DMACMD1 OxF008 define DMASTS OxF008 define DMASRR 0 009 define DMAMSK OxF00A define DMAMOD1 0 00 define DMACLRBP 0 00 define DMACLR OxFOOD define
120. SYSTEM REGISTER QUICK REFERENCE D 1 PERIPHERAL REGISTER ADDRESSES APPENDIX D SYSTEM REGISTER QUICK REFERENCE Table D 1 Peripheral Register Addresses Sheet 1 of 6 pecia UN EOM Register Name Reset Value DMA Controller and Bus Arbiter FOOOH 0000H Byte DMAOTARO Note 1 XX F001H 0001H Byte DMAOBYCO Note 1 XX F002H 0002H Byte DMA1TARO 1 Note 1 XX F003H 0003H Byte DMA1BYCO Note 1 XX F004H 0004H Reserved F005H 0005H Reserved F006H 0006H Reserved F007H 0007H Reserved F008H 0008H Byte DMACMD1 DMASTS 00H F009H 0009H Byte DMASRR 00H FOOAH 000AH Byte DMAMSK 04H FOOBH 000BH Byte DMAMOD 1 00H F00CH 000CH Byte DMACLRBP Not a register FOODH 000DH Byte DMACLR Not a register FOOEH 000EH Byte DMACLRMSK Not a register FOOFH 000FH Byte DMAGRPMSK 03H F010H Byte DMAOREQO 1 XX F011H Byte DMAOREQ2 3 XX F012H Byte DMA1REQO0 1 XX F013H Byte DMA1REQ2 3 XX F014H Reserved F015H Reserved F016H Reserved F017H Reserved F018H Byte DMABSR X1X10000B NOTES 1 Byte pointer in flip flop in DMA determines which register is accessed 2 Shaded rows indicate reserved areas D 1 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Table D 1 Peripheral Register Addresses Sheet 2 of 6 intel p Adis bs 5 PAE ena Register Nam
121. Sioto 3K General Slot I O Sot 0800 2k General Slot I O 0400H 1K General Slot I O ISA Platform 1 0000H 0K 2499 02 Figure 4 2 Expanded I O Address Space 16 bit Decode 4 4 intel SYSTEM REGISTER ORGANIZATION The Intel386 EX processor uses slot 15 for the registers needed for integrated peripherals Using this slot avoids conflicts with other devices in an EISA system since EISA systems typically do not use slot 15 4 4 ORGANIZATION OF PERIPHERAL REGISTERS The registers associated with the integrated peripherals are physically located in slot 15 of the I O space There are sixteen 4 Kbyte address slots in I O space Slot 0 refers to OH OFFFH slot 15 refers to OF000H 0FFFFH Table 4 1 shows the address map for the peripheral registers in slot 15 Note that the I O addresses fall in address ranges OF000H 0FOFFH OF400H OF4FFH and OF800H OF8FFH utilizing the unique sets of 256 I O addresses in Slot 15 Table 4 1 Peripheral Register I O Address in Slot 15 Register Description Address Range DMA Controller 1 OFOOOH OFO1FH Master Interrupt Controller OF020H OFO3FH Programmable Interval Timer OF040H 5 DMA Page Registers OF080H OFO9FH Slave Interrupt Controller OFOAOH OFOBFH Math Coprocessor OFOFOH OFOFFH Chip Select Unit OF400H OF47FH Synchronous Serial I O Unit OF480H OF49FH DRAM Refresh Control Unit OFAA0H OF4BFH Watchdo
122. WDT unit can function as a general purpose timer a software watchdog timer or a bus monitor or it can be disabled This chapter is organized as follows Overview see below Watchdog Timer Unit Operation page 17 3 Disabling the WDT page 17 6 Register Definitions page 17 7 Design Considerations page 17 12 Programming Considerations page 17 12 17 1 OVERVIEW The watchdog timer unit Figure 17 1 includes a 32 bit reload register a 32 bit down counter an 8 state binary counter a readable counter value register and a status register The watchdog timer can operate in three modes General purpose 32 bit timer counter mode default mode Watchdog mode Bus monitor mode Only a single mode can be active at one time If you have no need for any of its functions you can disable the unit entirely Watchdog mode protects systems from software upsets In watchdog mode system software must reload the down counter at regular intervals If it fails to do so the timer expires and asserts WDTOUT For example the watchdog times out if the software goes into an endless loop Some possible uses of this feature include Connecting WDTOUT to the NMI pin to generate a non maskable interrupt Connecting the WDTOUT signal to the RESET pin to reset the processor and possibly the entire system In watchdog mode only idle mode stops the down counter Since no software can execute while the CPU is idle a software watc
123. _GetEXRegByte LSRO define GetSIOlStatus _GetEXRegByte LSR1 define GetSIO0InterruptID _GetEXRegByte IIRO define GetSIOlInterruptID _GetEXRegByte IIR1 define GetSIO0ModemStatus _GetEXRegByte 5 0 define GetSIOlModemsStatus _GetEXRegByte MSR1 define GetSIOO0Char _GetEXRegByte RBRO define GetSIOlChar _GetEXRegByte RBR1 define ChangeSIO0IntrSrc src _SetEXRegByte IERO src define ChangeSIOlIntrSrc src SetEXRegByte IER1 src define ChangeSIO0Mode Mode _SetEXRegByte LCRO Mode define ChangeSIOlMode Mode _SetEXRegByte LCR1 Mode define DisableSIO0OInterrupt src SetEXRegByte 0 GetEXRegByte IERO 6 src define DisableSIOlInterrupt src _SetEXRegByte IER1 _GetEXRegByte IER1 amp src SIO Function Definitions extern int InitSIO int Unit BYTE Mode BYTE ModemCntrl DWORD BaudRate DWORD BaudClkIn extern BYTE SerialReadChar int Unit extern int SerialReadStr int Unit char far str int count extern void SerialWriteChar int Unit BYTE ch extern void SerialWriteStr int Unit const char far str extern void SerialWriteMem int Unit const char far mem int count void interrupt far Serial0 ISR void extern void Service RBF void extern void SerialWriteStr Int int Unit const char far str extern void Service TBE void RR KKK ke e ke ke e e e KKK DMA configuration defines Ok kk kk koe ke ke KKK C 9 Intel386 EX EMBEDDED MICROPROCESSOR USER
124. a refresh bus cycle has two components address bits A25 14 from the refresh base address register and address bits A13 1 from the 13 bit address counter 15 4 intel REFRESH CONTROL UNIT The 13 bit address counter is a combination of a binary counter and a 7 bit linear feedback shift register The binary counter produces address bits A13 8 and the linear feedback shift register produces address bits A7 1 The shift register nonsequentially produces all 128 27 possible com binations Each time the lower seven bits cycle through all 128 combinations the binary counter increments the upper 6 bits This continues until the 13 bit address counter cycles through 8192 213 address combinations The counter then rolls over to its original value and the process re peats 15 2 4 Bus Arbitration Because the two DMA channels an external device via the HOLD pin and the refresh control unit can all request bus control bus control priority must be arbitrated Refresh requests always have the highest priority Control Arbitration on page 12 9 discusses the priority structure of the other bus control requests When a refresh occurs while a DMA channel is performing a transfer the RCU steals a bus cy cle to perform a refresh An external device can gain bus control through either the HOLD signal or the DMA cascade mode In this case a refresh request causes HLDA or DMACKn signal to be deasserted When this happens the e
125. address into expanded I O space 5 SOR 0 Makes serial channel 0 COM1 accessible in both DOS I O space and expanded I O space 1 Remaps serial channel 0 COM1 address into expanded I O space 4 ISR 0 Makes the slave 82C59A interrupt controller accessible in both DOS space and expanded I O space 1 Remaps slave 82C59A interrupt controller address into expanded space 3 IMR 0 Makes the master 82C59A interrupt controller accessible in both DOS I O space and expanded I O space 1 Remaps master 82C59A interrupt controller address into expanded space 2 DR 0 Makes the DMA address accessible in both DOS I O space and expanded I O space 1 Remaps DMA address into expanded I O space 1 Reserved 0 TR 0 Makes the timer control unit accessible in both DOS I O space and expanded I O space 1 Remaps timer control unit address into expanded I O space D 53 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL D 52 RFSADD Refresh Address Expanded Addr F4A6H RFSADD ISA Addr read write Reset State 00 15 RA13 RA12 RA11 RA10 RA9 RA8 7 0 RA7 RA6 RA5 RA4 RA3 RA2 RA1 1 Bit Bit Number Mnemonic Function 15 14 Reserved These bits are undefined for compatibility with future devices do not modify these bits 13 1 RA13 1 Refresh Address Bits These bits comprise A13 1 of the refre
126. affect channel 1 SetEXRegByte DMAMOD2 OxD1 DMAMOD2 7 1 Select 2 cycle data xfer DMAMOD2 6 1 Requester is in I O space DMAMOD2 5 0 Target is in memory space DMAMOD2 4 1 Requester is held constant thru xfer DMAMOD2 3 x Req Inc Dec see fR DMAMOD2 4 DMAMOD2 2 0 Target address is modified see DMAMOD1 5 DMAMOD2 1 0 reserved DMAMOD2 0 1 selections for bits 7 2 affect channel 1 12 59 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel SetEXRegByte DMABSR 0x51 DMABSR 7 0 reserved DMABSR 6 1 sets req s bus size to 8 bit DMABSR 5 0 reserved DMABSR 4 1 sets tar s bus size to 8 bit DMABSR 3 2 0 reserved DMABSR 0 1 selections for bits 7 2 pe affect channel 1 _SetEXRegByte DMACHR 0 1 DMACHR 7 DMACHR 2 mode DMACHR 1 0 reserved DMACHR 0 1 selections for bits 7 2 affect JE channel 1 0 reserved 0 disable chaining buffer xfer regDMAIE GetEXRegByte DMAIEN amp 0 1 SetEXRegByte DMAIEN regDMAIE DMAIE 7 2 untouched reserved DMAIE 1 0 masks channel 1 s transfer complete signal from interrupt controller DMAIE 0 untouched channel 0 setting regDMAOvfE GetEXRegByte DMAOVFE OxC _SetEXRegByte DMAOVFE regDMAOvfE DMAOVFE 7 4 untouched reserved DMAOVFE 3 1 all bits of channel 1 req address ar
127. and 23H Figure 4 4 Once the expanded I O space is enabled internal peripher als timers DMA interrupt controllers and serial communication channels can be mapped out of DOS I O space using the REMAPCEG register and registers associated with other internal peripherals such as the chip select unit power management unit watchdog timer can be access ed 4 5 2 1 Programming REMAPCFG Example The expanded I O space enable ESE bit in the REMAPCFG register can be set only by three sequential write operations to I O addresses 22H and 23H as described in Figure 4 4 Once ESE is set REMAPCFG and all the on chip registers in the expanded I O address range 0 000 OFFFFH can be accessed The remap bits in REMAPCFG are still in effect even after the ESE bit is cleared Gisable interrupts CLI Enable expanded I O space of Intel386 tm EX processor for peripheral initialization MOV AX 08000H Enable expanded I O space OUT 23H AL and unlock the re map bits XCHG AL AH OUT 22H AL OUT 22H AX at this point PC AT peripherals can be mapped out For example Map out the on chip channels from the DOS I O space slot 0 MOV AL 04H OUT 22H AL Disables expanded I O space MOV AL 00H OUT 23H AL Re enable Interrupts STI Figure 4 4 Setting the ESE Bit Code Example The REMAPCFG register is write protected until the expanded I O space is enabled When the enabling write sequence is executed it sets the ESE
128. and clearing the hardware request mask for this DMA channel Parameters None Returns None Assumptions InitDMA has been called to enable the peripheral Syntax static char lpsz Hello World InitDMA Initialize DMA peripheral InitDMAlForSerialXmitter Initialize DMA channel 1 12 58 intel DMA CONTROLLER SetDMATargMemAddr DMA_Channell lpsz Set target memory address Set transfer count SetDMAXferCount DMA Channell strlen lpsz EnableDMAHWRequests DMA 11 Begin transfer at SIO request Real Protected Mode No changes required Ck k k Kk k k k k k void InitDMAlForSerialXmitter void BYTE regDMACfg BYTE regDMAIE BYTE regDMAOvfE DisableDMAHWRequests Channell Disable channel 1 Hardware requests regDMACfg GetEXRegByte DMACFG amp OxOF 0 0 _SetEXRegByte DMACFG regDMACfg DMACFG 7 1 mask DMA Acknowledge for p channel 1 DMACFG 6 4 3 set channel request to pe SIO s channel 0 s transmit buffer empty signal DMAMSK 3 0 unmodified channel 0 ys settings SetEXRegByte DMAMOD1 0x9 DMAMOD1 7 6 0 set to demand data xfer mode DMAMOD1 5 0 increment target DMAMOD1 4 0 disable autoinitialize buffer xfer mode DMAMOD1 3 2 2 data is xfer d from targ to DMAMOD1 1 0 reserved DMAMOD1 0 1 selections for bits 7 2
129. and timer control units are internally connected to the DMA request inputs You must connect an external I O source to the DMA DRQn when you are using fly by mode you must also connect an external I O source to the DACKn signals In addition memory mapped I O peripherals may use DRQn DACKn DACKni is active during the entire fly by mode transfer but during a two cycle mode transfer it is only active during the access to the requester These sources make up the DMA hardware request sources The DMA unit also contains a software request register that allows you to generate software DMA requests This allows memory to memory transfers Figure 12 4 shows the timing for the start of a DMA transfer CLKOUT DRQn 25 1 BHE BLE M IOst DACKn ADS READY x Cycle Transition to DMACycle Cycle i 2480 02 Figure 12 4 Start of Two cycle Transfer Initiated by DRQn 12 2 4 Bus Control Arbitration The bus arbiter services bus control requests from the two DMA channels an external device and the refresh control unit The DMA channels interface with the bus arbiter through its DMA chan nel request signals DREQn and its DMA channel acknowledge signals DMAACKn Other external bus masters interface with the bus arbiter through similar request and acknowledge sig nals the HOLD and HOLDA signals respectively The refresh control unit gains bus control through an internal Refresh re
130. and using the Autotransmit mode is recommended The SSIO interrupt line is multiplexed with INT5 When configuring your system for SSIO generated interrupts you must clear INTCFG 1 to connect the SSIO interrupt signal to the ICU The serial receive clock SRXCLK and transmit serial data SSIOTX pins are multiplexed with other functions Use PINCFG bits 0 and 1 to select the pin functions e No register programming is required for the shared signal pairs RI1 SSIORX and DSR1 STXCLK Both do not have multiplexers since one of the shared signals is a dedicated input 13 5 1 SSIO Example Code This section includes these software routines InitSSIO SSerialRead Word SSerialWriteWord SSIO ISR Service RHBF Service THBE Initializes the SSIO for synchronous transfers Polled serial read function that receives a single character Polled serial write function that transmits a single character Interrupt Service Routine for interrupts generated by the SSIO Service routine for interrupts generated by the RHBF signal Service routine for interrupts generated by the THBE signal The final code example shows an SSIO transfer in which the transmitter is interrupt driven and the receiver is polled See Appendix C for included header files include lt conio h gt include 80386EX h include EV386EX h WORD value 71 BYTE Control BYTE poll InitSSIO Description 13 26 intel SYNCHRONOUS
131. are ignored the byte count expires when it is decremented from 0000H to FFFFH 16 bit versus 24 bit rollovers 12 27 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 12 3 REGISTER DEFINITIONS Table 12 3 lists the registers associated with the DMA unit and the following sections contain bit descriptions for each register Table 12 3 DMA Registers Sheet 1 of 3 Expanded PC AT Register Address Address Description PINCFG F826H Pin Configuration read write Connects the DMA channel acknowledge DMAACKO DMAACK1 and end of process signals to package pins DACKO DACK1 and EOP respectively DMACFG F830H DMA Configuration read write Determines which signal is connected to the DMA channel request inputs DREQn Masks the channel acknowledge signals DMAACK0 DMAACK1 which is useful when using internal requesters DMACMD1 F008H 0008H DMA Command 1 write only Simultaneously enables or disables both DMA channels Enables the rotating method for changing the bus control priority structure DMAOREQO F010H Channel 0 and 1 Requester Address DMAOREQ EOI OH Contains channel n s 26 bit requester address DMAOREQ2 m During a buffer transfer this address may be DMAOREQS incremented decremented or left unchanged Reading these registers returns the current address DMA1REQO F012H DMA1REQ1 F012H DMA1REQ2 F013H DM
132. at the Device Pins Sheet 1 of 6 Multiplexed With Signal Type Name and Description Alternate Function A25 19 Address Bus A18 6 Outputs physical memory or port I O addresses These CAS2 0 151 signals are valid when ADS is active and remain valid until the next T1 T2P or Ti ADS Address Status Indicates that the processor is driving a valid bus cycle definition and address W R D C M IO A25 1 BHE BLE onto its pins Byte High Enable Indicates that the processor is transferring a high data byte BLE Byte Low Enable Indicates that the processor is transferring a low data byte 58 Bus Size Indicates that an 8 bit device is currently being addressed BUSY Busy TMRGATE2 Indicates that the math coprocessor is busy If BUSY is sampled low at the falling edge of RESET the processor performs an internal self test CAS2 0 Cascade Address A18 16 Carries the slave address information from the master 8259A interrupt module during interrupt acknowledge bus cycles CLK2 ST Input Clock Is connected to an external clock that provides the fundamental timing for the microprocessor The internal processor clock frequency is half the CLK2 frequency CLKOUT Clock Output Use this output to synchronize external devices with the processor COMCLK SIO Baud Clock P3 7 An external source connected to this pin can clock the SIOn
133. base interrupt vector number for the Master interrupts For example if of the master goes active and the MstrBase 0x20 the processor uses interrupt vector table entry 0x21 Which Master IRQs are used for Slave ICUs Mode of operation for Slave ICU Specifies the base interrupt vector number for the Slave interrupts For example if IR1 of the slave goes active and the SlaveBase 0x40 the processor uses interrupt vector table entry 0x41 Defines what EX pins are available externally to the chip for the Master Defines what EX pins are available externally to the chip for the Slave Initialized OK No error REMAPCFG register has Expanded I O space access enabled ESE bit set Syntax define ICU TRIGGER EDGE 0x0 define MPIN INTO define 5 define SPIN_INT4 int error_code error_code Init 0 4 0x2 0x1 ICU ICU TRIGGER EDGE 0x20 MCAS_IR1 ICU_TRIGGER_EDGE 0x30 MPIN_INTO SPIN 4 9 33 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Real Protected Mode No changes required Ck Kk Ck ko Kk k Kk int InitICU BYTE MstrMode BYTE MstrBase BYTE MstrCascade BYTE SlaveMode BYTE SlaveBase BYTE MstrPins BYTE SlavePins BYTE icw cfg pins Program Slave ICU IRQ SlaveBase SlaveBase amp Oxf8 SetEXRegByte ICW1S 0x11 SlaveMode Set slave triggering SetEXRegByte ICW2S IRQ SlaveBase Set slave base interrupt typ
134. basis The requester can be in external device I O space in internal peripheral I O space or memory mapped I O Very simply the requester is the thing that activated DREQn An external device or an internal periph eral requests service by activating a channel s request input DREQn A requester in memory re quests service through the DMA software request register The requester either deposits data to or fetches data from the target A channel is programmed by writing to a set of requester address target address byte count and control registers The address registers specify base addresses for the target and requester and the byte count registers specify the number of bytes that need to be transferred to or from the target Typically a channel is programmed to transfer a block of data Therefore it is necessary to dis tinguish between the process of transferring one byte or word data transfer and the process of transferring the entire block of data buffer transfer The byte count determines the number of data transfers that make up a buffer transfer After each data transfer within a buffer transfer the byte count is decremented by 1 for byte transfers and by 2 for word transfers and the requester and target addresses are either incremented decrement ed or left unchanged When the byte count expires reaches FFFFFFH the buffer transfer is complete If the channel s end of process EOP signal is activated before the byte co
135. bits are undefined 5 R1 Request 1 When set this bit indicates that channel 1 has a hardware request pending When the request is removed this bit is cleared 4 RO Request 0 When set this bit indicates that channel 0 has a hardware request pending When the request is removed this bit is cleared 3 2 Reserved These bits are undefined 1 TC1 Transfer Complete 1 When set this bit indicates that channel 1 has completed a buffer transfer either its byte count expired or it received an EOP input Reading this register clears this bit and clears TC1 in DMAIS 0 TCO Transfer Complete 0 When set this bit indicates that channel 0 has completed a buffer transfer either its byte count expired or it received an EOP input Reading this register clears this bit and clears TCO in DMAIS Figure 12 23 DMA Status Register DMASTS 12 36 intel DMA CONTROLLER 12 3 7 Command 2 Register DMACMD2 Use DMACMD2 to select the DREQn and EOP sampling asynchronous or synchronous Bus timing diagrams that show the differences between asynchronous and synchronous sampling are shown in Figure 12 5 on page 12 10 and Figure 12 13 on page 12 21 Also use DMACMD2 to assign a particular bus request to the lowest priority level for fixed priority mode DMA Command 2 DMACMD2 write only 7 Expanded Addr 1 ISA Addr Reset State 08H PL1 PLO ES DS Bit Bit Number
136. bus cycle length In the case of different bus sizes the CSU defaults to an 8 bit bus size If one overlapping chip select region has the RDY bit set and the other overlapping region does not the CSU defaults to the RDY Bit Set operation in this case an external READY is neces sary to terminate accesses to the address locations in which the two chip selects overlap NOTE If a bus cycle address activates multiple overlapping CSU channels all the enabled chip select signals of those channels go active To avoid contention on the data bus care must be taken when using these chip select signals externally 14 11 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Is any channel Wait for smallest number dependent on of all overlapping regions external wait state values ready Wait State READY Wait for largest number of asserted all overlapping regions wait state values Complete bus cycle A2392 02 Figure 14 3 Bus Cycle Length Adjustments for Overlapping Regions 14 12 intel 14 4 REGISTER DEFINITIONS Table 14 1 and Table 14 2 list the signals and registers associated with the chip select unit There are seven general purpose chip select channels and one upper chip select channel UCS Upon reset the UCS is enabled with the entire 64 Mbyte memory address space as its address block The UCS can be used to select a memory device at the top of the memory address sp
137. channel address is not the starting address of the lowest active address block In this example each active 16 Kbyte address block is followed by an inactive 16 Kbyte address block and each block starts at a 16 Kbyte address boundary Maximum Memory Address 0 2 000 OE2BFFFH Active 0 28000 0 0 000 OEOBFFFH Active 0 08000 14 9 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 14 3 2 System Management Mode Support The processor supports four operating modes system management mode SMM protected real and virtual 86 mode In order for a system to operate correctly in SMM it must meet several re quirements The CSU provides support for some of these requirements To use SMM you must set aside a partition of memory called SMRAM for the SMM driver SMRAM must meet the following conditions Located at 38000 32 Kbytes Accessible only when the processor is in SMM during normal operation Accessible during system initialization when the processor is not in SMM The CSU allows you to specify an address block and control whether or not the chip select is ac tivated while the processor is in SMM While in SMM with CASMM 1 the chip select is ac tive only when the processor is the bus master such as when the processor is not in a hold state Refer to Chapter 7 Programming Considerations on page 7 16 for a code example of pro gramming chip selects to supp
138. clock Power Control ee This register selects the power management mode internal ready options Table 8 2 Clock and Power Management Signals Signal Miss dis Description Input Clock CLK2 Device pin Connect an external clock to this pin to provide the fundamental timing for the microprocessor CLKOUT Device pin Glock CLKOUT is a Phase 1 output clock PH1P IDLE Internal signal Idle Output to the Watchdog Timer Unit IDLE indicates that the device is in idle mode INTR Internal signal Interrupt Input from the Interrupt Control Unit INT causes the device to exit powerdown or idle mode NMI Device pin Nonmaskable Interrupt Input NMI causes the device to exit powerdown or idle mode Prescaled Clock Output PSCLK is one of tw ible clock inputs for the SSIO baud rate PREIS Ingmar sand sae du he ler nE The PSCLK frequency is controlled by the CLKPRS register Powerdown Output multiplexed with P3 6 PWRDOWN Device pin A high state on the PWRDOWN pin indicates that the device is in powerdown mode System Reset Input RESET Device pin This signal resets the processor and causes the device to exit powerdown or idle mode Serial Clock Output SERCLK Internal signal SERCLK is one of two possible clock inputs for the SIO or SSIO baud rate generator The SERCLK frequency is one fourth the CLK2 frequency System Management Interrupt Input SMI Device pin SMI causes the device to exit powerdown or idle mode and causes t
139. consists of a start bit 5 to 8 data characters an optional parity bit and 1 to 2 stop bits The receiver can be programmed for even odd forced or no parity When the receiver detects a parity condition other than what it was programmed for it sets a parity error flag In addition to detecting parity errors the receiver can detect break conditions framing errors and overrun er rors A break condition indicates that the received data input is held in the spacing logic 0 state for longer than a data transmission time the time of the start bit data bits parity stop bits A framing error indicates that the received character did not have a valid stop bit e An overrun error indicates that new data overwrote old data before the old data was read Each SIO channel receiver contains a receive shift register a receive buffer and a receive data pin RXDn Data received is shifted into the receive shift register via the RXDn pin Once a data byte has been received the receiver strips off the asynchronous communication bits start stop and parity and transfers the contents of its shift register to the receive buffer The RXDO pin is multiplexed with another function The pin configuration register P2CFG de termines whether the RXDO signal or the alternate function is connected to the package pin Baud rate Clock RXDn pin mux Receiver Errors To ICU Receive Buffer Full To ICU and DMA A2327 02
140. data in Data is received least significant bit first CTSn Device pin Clear to Send input Indicates that the modem or data set is ready to exchange data with the SlOn channel DSRn Device pin Data Set Ready input Indicates that the modem or data set is ready to establish the communications link with the SIOn channel DCDn Device pin Data Carrier Detect input Indicates that the modem or data set has detected the data carrier RIn Device pin Ring Indicator input Indicates that the modem or data set has detected a telephone ringing signal RTSn Device pin Request to Send output Indicates to the modem or data set that the SIOn channel is ready to exchange data DTRn Device pin Data Terminal Ready output Indicates to the modem or data set that the SIOn channel is ready to establish a communications link SIOINTn Internal Signal SIOINT This signal is connected to the interrupt control unit and is asserted HIGH when any one of the following interrupt types has an active condition and is enabled via the IER register Receiver Error flag Received Data Available Transmitter Holding Register Empty or Modem Status The SIOINT signal is deasserted LOW upon the appropriate interrupt service or reset operation Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Table 11 1 SIO Signals Device Pin or ri Signal Internal Signal Description TXEDMAn Internal Signal Transmitter Empty
141. define DLLO OxFAF8 define IERO OxFAF9 define DLHO OxFAF9 intel EXAMPLE CODE HEADER FILES define IIRO OxFAFA define LCRO OxFAFB define MCRO OxFAFC define LSRO OxFAFD define MSRO OxFAFE define SCRO OxFAFF ASYNCHRONOUS SERIAL CHANNEL 0 SLOT 0 ADDRESSES define RBRODOS 0 03 8 define THRODOS 0 03 8 define TBRODOS 0 03 8 define DLLODOS 0 03 8 define IERODOS Ox03F9 define DLHODOS Ox03F9 define IIRODOS Ox03FA define LCRODOS 0x03FB define MCRODOS Ox03FC define LSRODOS 0x03FD define MSRODOS 0x03FE define SCRODOS Ox03FF ASYNCHRONOUS SERIAL CHANNEL 1 SLOT 15 ADDRESSES define RBR1 OxF8F8 define THR1 OxF8F8 define TBR1 OXF8F8 define DLL1 OxF8F8 define IERI OxF8F9 define DLH1 OxF8F9 define IIR1 OxF8FA define LCR1 OxF8FB define MCR1 OxF8FC define 15 1 OxF8FD define MSR1 OxF8FE define SCR1 OxF8FF ASYNCHRONOUS SERIAL CHANNEL 1 SLOT 0 ADDRESSES define RBRIDOS 0 02 8 define THRIDOS 0 02 8 define TBRIDOS 0 02 8 define DLL1DOS 0 02 8 define IERIDOS 0 02 9 define DLH1DOS 0x02F9 define IIRIDOS 0 02 define LCR1DOS 0 02 define MCR1DOS 0 02 define LSR1DOS 0 02 define MSR1DOS 0 02 define SCR1DOS 0 02 SYNCHRONOUS SERIAL CHANNEL REGISTERS define SSIOTBUF OxF480 define SSIORBUF 0 482 define SSIOBAUD 0 484 define SSIOCON1 OxF486 C 3 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL define SSIOCON2 OxF488 define
142. defined limit of a code segment or an exception 13 fault general protection violation will occur The instruction will execute in s clocks if CPL IOPL If CPL gt IOPL the instruction will take t clocks Clock count shown applies if I O permission allows I O to the port in virtual 8086 mode If I O bit map denies permission exception 13 general protection fault occurs refer to clock counts for INT 3 instruction E 21 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel E 2 INSTRUCTION ENCODING All instruction encodings are subsets of the general instruction format shown in Figure E 1 In structions consist of one or two primary opcode bytes possibly an address specifier consisting of the mod r m byte and scaled index byte a displacement if required and an immediate data field if required Within the primary opcode or opcodes smaller encoding fields may be defined These fields vary according to the class of operation The fields define such information as direction of the opera tion size of the displacements register encoding or sign extension Almost all instructions referring to an operand in memory have an addressing mode byte follow ing the primary opcode byte s This byte the mod r m byte specifies the address mode to be used Certain encodings of the mod r m byte indicate a second addressing byte the scale index base byte which follows the mod r m byte to fully specify the addressing mode
143. each counter s GATEn signal to either V cc or the external timer gate TMRGATEn pin or you can drive each counter s GATEn signal high or low through register bits OUTn Each counter contains an output signal called OUTn You can independently connect these signals to the external timer clock output TMROUTn pins OUTO OUTI and OUT2 are routed to the interrupt control unit OUTI is also routed to DMA channel 0 and OUT2 is also routed to DMA channel 1 10 1 Intel386 EX EMBEDDED PROCESSOR USER S MANUAL intel Therefore the OUTn signals can drive external devices generate interrupt requests initiate DMA transactions or combinations of the three Each counter operates independently Six different counting modes are available and two count formats binary 16 bits or BCD 4 decades Each operating mode allows you to program the counter with an initial count and to change this value the fly You can determine the count and status of each counter without disturbing its current operation Control Logic lt t e E PSCLK i B TMRCLK lt Js P3CFG 0 one Voc m H To ICU TMRGATEO Master IRO PSCLK i TMRCLK1 e NSO merour Vcc M H To ICU TMRGATE1 Slave IR2 e oM PSCLK I CLKIN2 TMRCLK2 052 turout2 Voc S To ICU TMRGATE2 gt up Slave IR3 To DMA MUX A2317 02 Figure 10 1 Timer Counter Unit Signal Connections 10 2 intel
144. from the test logic reset state A one indicates that an IDCODE register is present A zero originates from the BYPASS register and indicates that the device being interrogated has no IDCODE register D 31 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel D 29 IERn Interrupt Enable IERO IER1 IERO IER1 Expanded Addr F4F9H F8F9H read write ISA Addr 03F9H 02F9H Reset State 00H 00H 7 0 m MS RLS TBE RBF Bit Bit 5 Number Mnemonic Function 7 4 Reserved for compatibility with future devices write zeros to these bits 3 MS Modem Status Interrupt Enable 0 Modem input signal changes do not cause interrupts 1 Connects the modem status signal to the interrupt control unit s SIOINTn output A change on one or more of the modem input signals activates the modem status signal 2 RLS Receiver Line Status Interrupt Enable 0 LSR error conditions do not cause interrupts 1 Connects the receiver line status signal to the interrupt control unit s SIOINTn output Sources for this interrupt include overrun error parity error framing error and break interrupt 1 TBE Transmit Buffer Empty Interrupt Enable 0 Transmit Buffer Empty signal does not cause interrupts 1 Connects the transmit buffer empty signal to the interrupt control units SIOINTn output 0 RBF Receive Buffer Full Interrupt Enable 0 Receive buffer full signal does not cause
145. full signal Reading the receive buffer register or the serial line status register clears the LSRn error bits which clears the receiver line status signal 0 IP Interrupt Pending This bit indicates whether an interrupt is pending 0 Interrupt is pending 1 No interrupt is pending D 33 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel D 31 INTCFG Interrupt Configuration Expanded Addr F832H INTCFG ISA Addr read write Reset State 00H 7 0 CE IR3 IR4 SWAP 186 IR5 IR4 IR1 IRO Bit Function Number Mnemonic 7 CE Cascade Enable 0 Disables the cascade signals CAS2 0 from appearing on the A18 16 address lines during interrupt acknowledge cycles 1 Enables the cascade signals CAS2 0 providing access to external slave 82C59A devices The cascade signals are used to address specific slaves If enabled slave IDs appear on the A18 16 address lines during interrupt acknowledge cycles but are high during idle cycles 6 IR3 Internal Master IR3 Connection See Table 5 1 on page 5 8 for all the IR3 configuration options 5 IR4 Internal Master IR4 Connection See Table 5 2 on page 5 8 for all the IR4 configuration options 4 SWAP INT6 DMAINT Connection 0 Connects DMAINT to the slave IR4 Connects INT6 to the slave IR5 1 Connects the INT6 pin to the slave IR4 Connects DMAINT to the slave 5 3 IR6 Internal Slave
146. holding buffer full signal SSRBF 100 TCU counter 2 s output signal OUT2 101 SIO channel 0 s receive buffer full signal RBFDMAO 110 SIO channel 1 s transmit buffer empty signal TXEDMA1 111 SSIO transmit holding buffer empty signal SSTBE DOMSK DMA Acknowledge 0 Mask 0 DMA channel 0 acknowledge DMAACKO signal is not masked 1 Masks DMA channel 0 s acknowledge DMAACKO signal Useful when channel 0 s request DREQO input is connected to an internal peripheral 2 0 DOREQ2 0 DMA Channel 0 Request Connection Connects one of the eight possible hardware sources to channel 0 s request input DREQO 000 DRQO pin external peripheral 001 SIO channel 0 s receive buffer full signal RBFDMAO 010 SIO channel 1 s transmit buffer empty signal TXEDMA1 011 SSIO transmit holding buffer empty signal SSTBE 100 TCU counter 1 s output signal OUT1 101 SIO channel 1 s receive buffer full signal RBFDMA1 110 SIO channel 0 s transmit buffer empty signal TXEDMAO 111 SSIO receive holding buffer full signal SSRBF Figure 5 3 DMA Configuration Register DMACFG intel DEVICE CONFIGURATION 5 2 2 Interrupt Control Unit Configuration The interrupt control unit ICU comprises two 82C59A interrupt controllers connected in cas cade as shown in Figure 5 4 See Chapter 9 for more information Figure 5 5 describes the in terrupt configuration register
147. issued The poll status byte is read When an 82C59A receives an interrupt request before it receives a poll command it sets the re quest s in service bit and configures the poll status byte to reflect the interrupt request The poll status byte is used to determine which device connected to the 82C59A requires servicing At the end of a request s servicing you must issue a command to clear the request s in service bit The polling mode allows expansion of the system s external interrupt capability Without polling the system can have a maximum of 52 external interrupt sources This is accomplished by cas cading six 82C59As to the master s six external interrupt pins and using the four external inter rupt pins connected to the slave The polling mode increases the system s interrupt capability by 9 14 intel INTERRUPT CONTROL UNIT configuring more than six external 82C59As Since the polling mode doesn t require that the ad ditional 82C59As be cascaded from the master the number of interrupt request sources for a polled system is limited only by the number of 82C59As that the system can address Polling and standard interrupt processing can be used within the same program Systems that use polling as the only method of device servicing must still fully initialize the 82C59A modules Al so the interrupt requests to the core must be disabled using the mask bits or the CLI instruction 9 3 REGISTER DEFINITIONS The registers associa
148. k k k k k TimerISR Description Interrupt Service Routine for Timer generated interrupts Parameters None Returns None Assumptions None Syntax Not called by user Real Protected Mode No changes required eK RR RR I RR KARR IIA AA ARR Kk Ck kk KC Kk void interrupt far TimerISR void Write message out to serial port as an example SerialWriteStr SIO 0 In TimerISR n NonSpecificEOI If this ISR services Timerl or Timer2 an EOI is also needed for the Slave 8259 TimerISR 10 40 intel TIMER COUNTER UNIT Kk Kk k k k k KC Kk k k Kk Ck k k k ke kk k ke kk k ke k k k k k k Example of how to write a new initial counter value to a timer This value can be rewritten at any time without affecting the Counter s programmed mode Before writing an initial count value the Control Word must be configured for the proper R W and Count formats This example assumes that Timerl is in the R W format of LSB first then MSB and that the Count format is binary _SetEXRegByte TMR1 InitialCountL _SetEXRegByte TMR1 InitialCountH eK RR A A IRR A ARR AA ARR Kk Kk KC IRR Kk kk BORK RK KKK IK KK k k KR k k k I k k k k k k k k k k k k k k k k k k k kk k k k k kk k k kk k kkk IA kkk ke ke ke X ek Example of how to issue a Read Back command for Timer2 latching both the status and the counter BYTE Status CountL CountH
149. know the exact amount of data to be transferred and you know that there is time to re program the channel requester and target addresses and byte count before another buffer of data needs to be transferred 12 2 6 2 Autoinitialize Buffer Transfer Mode When programmed for the autoinitialize buffer transfer mode the DMA automatically reloads the channel with the original transfer information the requester and target addresses and the byte count when the transfer completes The channel then repeats the original buffer transfer The au toinitialize buffer transfer mode is useful when you need to transfer a fixed amount of data be tween the same locations multiple times 12 2 6 3 Chaining Buffer Transfer Mode This mode is similar to the autoinitialize buffer transfer mode in that the DMA automatically re programs the channel after the current buffer transfer is complete The difference is that the au toinitialize buffer transfer mode uses the original transfer information while the chaining buffer transfer mode uses new transfer information While a channel is performing a chaining buffer transfer you write new requester and target addresses and a new byte count to it This prepares the channel for the next buffer transfer without affecting the current buffer transfer When the channel completes its current buffer transfer the channel is automatically programmed with the new transfer information that you wrote to it The chaining buffer tr
150. low when the count reaches zero The OUTn strobes low only the first time it reaches zero after a count is loaded Mode 5 s basic operation is outlined below and shown in Figure 10 19 Sui pes pua dar e After a control word write OUTn is driven high On the CLKINz pulse following a gate trigger the count is loaded On each succeeding CLKINn pulse the count is decremented When the count reaches zero OUTn is driven low On the following CLKINn pulse OUTn is driven high NOTE Writing a count of N causes to strobe low N 1 CLKINnz pulses after the counter receives a gate trigger OUTn remains low for one CLKINn pulse then goes high Control Word 1AH Writes to Counter n Count 3 CLKINN GATEn 1 Count A2316 01 10 18 Figure 10 19 Mode 5 Basic Operation intel TIMER COUNTER UNIT Figure 10 20 shows retriggering the strobe with a gate trigger On the CLKIN7 pulse following the retrigger the counter reloads the count The control logic then decrements the count on each succeeding CLKINn pulse OUTn remains high until the count reaches zero then strobes low for one CLKINn pulse Control 2 1 Writes to Counter n CLKINN GATEn OUTn 1 1 1 1 1 1 1 1 1 1 1 1 count 2 2 2 2 2 003 0002 0003 0002 0001 A2404 01 Figure 10 20 Mode 5 Retr
151. lower address lines are connected to the Refresh Address Counter Register RFSADD The RFSADD increments through a set sequence at each refresh request Because the lower address bits wired to the Column Address Buffer change with each refresh request the PLD must enable this buffer when is asserted during a refresh cycle Figure 15 7 shows the external logic needed for paged RAS only refresh cycles The PLD can determine a refresh cycle by monitoring BHE and BLE they are both inactive during a refresh cycle or by an active signal on the REFRESH pin The buffer and lines that are active during this type of refresh have a shaded background in Figure 15 7 15 12 intel REFRESH CONTROL UNIT R Row ow Address Upper Address Address ad Buffer OE ROW REFRESH 2001985 M gt RAS Paged Intel386 EX DRAM Embedded Processor CAS A OE_COL Column Address Lower Address Buffer Column Address Note A single mux can be used in place of the row and column address buffers A3264 02 Figure 15 7 RAS Only Refresh Logic Paged Mode Non page Mode In non paged mode the row address buffer can be connected to the lower address lines and the column address buffer to the upper lines Figure 15 8 illustrates the hardware configuration for non paged DRAM accesses The lines and buffer that are enabled in this type of refresh are highlighted in the figure The lower add
152. memory address range 38000 3FFFFH The SMRAM area cannot be relocated internally SMRAM space is intended for access by the CPU only and should be accessible only when SMM is enabled This area is used by the SMM State Save sequence to save the CPU state in a stack like fashion from the top of the SMRAM area downward The CPU state dump area always starts at 3FFFFH and ends at 3FEO0H The following is a map of the CPU state dump in the SMRAM Hex Address Name Description O3FFFC CRO Control flags that affect the processor state O3FFF8 CR3 Page directory base register 0 4 EFLGS General condition and control flags O3FFFO EIP Instruction pointer O3FFEC EDI Destination index O3FFE8 ESI Source index O3FFE4 EBP Base pointer O3FFEO ESP Stack pointer O3FFDC EBX General register O3FFC8 EDX General register O3FFD4 ECX General register O3FFDO EAX General register O3FFCC DR6 Debug register contains status at exception O3FFC8 DR7 Debug register controls breakpoints O3FFC4 TR Task register used to access current task descriptor O3FFCO LDTR Local descriptor table pointer OSFFBC GS General purpose segment register OSFFB8 FS General purpose segment register O3FFB4 DS Data segment register 03F FBO SS Stack segment register CS Code segment register 03FFA8 ES General purpose segment register 03FFA7 03FF04 Reserved 03FF02 Halt restart slot 0
153. mode and two additional address lines for a total of 26 address lines 3 1 1 System Management Mode The Intel386 CX processor core provides a mechanism for system management with a combina tion of hardware and CPU microcode enhancements An externally generated System Manage ment Interrupt SMI allows the execution of system wide routines which are independent and transparent to the operating system The System Management Mode SMM architecture exten sions to the Intel386 SX processor consist of the following elements Interrupt input pin SMI to invoke SMM One output pin to identify execution state SMIACT One new instruction RSM executable only from SMM to exit SMM SMM also added one to four execution clocks to the following instructions IN INS REP INS OUT REP OUT POPA HALT MOV and SRC INTR and NMI also need an additional two clocks for interrupt latency These cycles were added due to the microcode modification for the SMM implementation Refer to Appendix E for the exact execution times Otherwise 100 of the Inte1386 SX processor instructions execute on the Intel386 CX processor core Please refer to Chapter 7 for more details on System Management Mode 3 1 2 Additional Address Lines Two additional address lines were added to the Intel386 CX processor core for a total of 26 This expands the physical address space from 16 Mbytes to 64 Mbytes 3 1 Intel386 EX EMBEDDED MICROPROCESSOR USER
154. monitor mode Read this bit to determine the current status A lockout sequence clears BUSMON and prevents writes to the WDTSTATUS register 0 CLKDIS Clock Disable Write to this bit to stop or restart the clock to the WDT read it to determine the current clock status A lockout sequence clears CLKDIS and prevents writing to this register 0 Clock enabled 1 Processor clock frequency CLK2 2 disabled stopped Figure 17 3 WDT Status Register WDTSTATUS 17 9 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL WDT Reload Value High Expanded Addr WDTRLDH ISA Addr read write Reset State 003FH 15 8 WR31 WR30 WR29 WR28 WR27 WR26 WR25 WR24 7 0 WR23 WR22 WR21 WR20 WR19 WR18 WR17 WR16 WDT Reload Value Low Expanded Addr F4C2H WDTRLDL ISA Addr read write Reset State FFFFH 15 8 WR15 WR14 WR13 WR12 WR11 WR10 WR9 WR8 7 0 WR7 WR6 WR5 WR4 WR3 WR2 WR1 WRO Bit Bit Number Mnemonic Function High 15 0 WR31 16 WDT Reload Value High Word and Low Word Low 15 0 WR15 0 Write the high word of the reload value to WDTRLDH and the low word to the WDTRLDL Figure 17 4 WDT Reload Value Registers WDTRLDH and WDTRLDL 17 10 intel WATCHDOG TIMER UNIT Power Control Register Expanded Addr F800H PWRCON ISA Addr
155. operating mode 10 3 Intel386 EX EMBEDDED PROCESSOR USER S MANUAL intel Table 10 2 TCU Associated Registers Register Expanded Address PC AT Address Function P3CFG PINCFG read write OF824H OF826H Peripheral Pin Selections These registers determine whether a counter s input and output signals are connected to package pins TMRCFG read write OF834H Timer Configuration Enables the counter s CLKINn input signal selects the CLKINn connection PSCLK or TMRCLK2n for each counter and either connects TMRGATEn or Vec to each counter s GATEn input signal or sets GATEn high or low through register bits TMRCON 0F043H 0043H TMRCON has three formats control word counter latch and read back When writing to TMRCON certain bit settings determine which format is accessed Control Word Format Programs a specific counter Selects a counter s operating mode and count format After programming a counter you can write a count value to the counter s TMRn register at any time Counter latch Format Issues a counter latch command to a specific counter The counter latch command allows you to latch the count of a specified counter After issuing a counter latch command you can check the counter s count by reading the counter s TMRn register Read back Format Issues a read back command to one or more counters The read back command allows you to latch the count an
156. operating mode of each pin by writing to the associated bit in the PnCFG registers Figure 16 3 gives an abbreviated version of these registers for the complete register descrip tions see Appendix D Setting a bit selects peripheral mode clearing a bit selects I O mode In ternal peripherals control pins configured for peripheral mode while the PnDIR Figure 16 4 and PnLTC Figure 16 5 registers control pins configured for I O mode Table 16 3 shows the PnDIR and PnLTC register values that determine the pin direction and state NOTE You must program both registers to correctly configure the pins Table 16 3 Control Register Values for I O Port Pin Configurations Desired Pin Configuration Desired Pin State PnDIR PnLTC High impedance input high impedance 1 1 high impedance 1 1 Open drain output 0 1 0 t tput 2 omplementary outpu 0 0 0 Regardless of the pin s configuration you can read the PnPIN registers Figure 16 6 to determine the current pin state Port n Configuration Expanded Addr F820H F822H F824H PnCFG 1 3 ISA Addr read write Reset State 00H 7 0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PMO Pit Pit Function Number Mnemonic 7 0 PM7 0 Pin Mode 0 Places pin in I O mode controlled by PnDIR and PnLTC registers 1 Places pin in peripheral mode controlled by the internal peripheral
157. or mod ss index base indicates source operand E 2 2 6 Encoding of Sign Extend s Field The s field occurs primarily to instructions with immediate data fields The s field has an effect only if the size of the immediate data is 8 bits and is being placed in a 16 bit or 32 bit destination Table E 11 Encoding of Sign Extend s Field s Effect on Immediate Data8 Effect on Immediate Data 16 32 0 1 Sign Extend Datae to fill None 16 bit or 32 bit destination E 2 2 7 Encoding of Conditional Test tttn Field For the conditional instructions conditional jumps and set on condition tttn is encoded with n indicating to use the condition n 0 or its negation n 1 and ttt giving the condition to test Table E 12 Encoding of Conditional Test tttn Field Mnemonic Condition tttn Overflow 0000 NO No Overflow 0001 B NAE Below Not Above or Equal 0010 NB AE Not Below Above or Equal 0011 E Z Equal Zero 0100 NE NZ Not Equal Not Zero 0101 BE NA Below or Equal Not Above 0110 NBE A Not Below or Equal Above 0111 S Sign 1000 NS Not Sign 1001 P PE Parity Parity Even 1010 NP PO Not Parity Parity Odd 1011 L NGE Less Than Not Greater or Equal 1100 NL GE Not Less Than Greater or Equal 1101 LE NG Less Than or Equal Greater Than 1110 NLE G Not Less or Equal Greater Than 1111 E 30 intel INSTRUCTION SET SUMMARY E 2 2 8 Encoding of Control or Debug or Test Regis
158. or3 or3 E 12 intel INSTRUCTION SET SUMMARY Table E 1 Instruction Set Summary Sheet 12 of 19 Clock Count Notes Real Pro Real Pro Ad tected Ad tected i dress Virtual dress Virtual Instruction Format Mode Ad Mode Ad or dress or dress Virtual Mode Virtual Mode 8086 8086 Mode Mode Full displacement A 7 m 7 m r 00001 1 10000101 Full displacement or3 or3 JBE JNA jump on below or equal not above 8 bit displacement Rod 74m 74m r 01110 0 8 bit displacement or 3 or 3 Ful displacement 00001111 10000110 Full displacement or 3 or 3 JNBE JA jump on not below or equal above 8 bit displacement 01110 1 8 bit displacement 7 E or 7 i or r Ful displacement 00001111 10000111 Fulldisplacement NE r JS jump on sign 8 bit displacement 01111000 8 bit displacement 7 50 or 7 n or r Full displacement 00001111 10001000 Full displacement 4 JNS jump on not sign 8 bit displacement 01111001 8 bit displacement 7 or 7 5 or r F lteisplacement 00001111 10001001 Full displacement CET O r JP JPE jump on parity parity even 8 bit displacement 01111010 amp bit displacement 7 em or 7 um or r displacement 00001111 10001010 Full displacement sc 4 JNP JPO jump on not parity parity odd 8 bit displacement 011110414 8 bit displacement 7 m or
159. parameters 106 8x h j k r m From 286 task to 286 TSS 285 h j k r From 286 task to Intel386 SX CPU TSS 310 h j k r From 286 task to virtual 8086 task Intel386 SX CPU TSS 229 h j k r From Intel386 SX CPU task to 286 TSS 285 h j k r From Intel386 SX CPU task to Intel386 SX CPU TSS 392 h j k r From Intel386 SX CPU task to Virtual 8086 task Intel386 SX CPU TSS 309 hjkr indirect intersegment 11111111 mod 0 1 1 r m 30 m 46 m b h j k r Protected mode only indirect intersegment Via call gate to same privilege level 68 10 intel INSTRUCTION SET SUMMARY Table E 1 Instruction Set Summary Sheet 10 of 19 Clock Count Notes Real Pro Real Pro dress Virtual dress Viral Instruction Format Mode Ad Mode Ad or dress or dress Virtual Mode Virtual Mode 8086 8086 Mode Mode Via call gate to different privilege level no parameters 1024 m h j K r Via call gate to different privilege level x parameters 110 8x hjikr m From 286 task to 286 TSS hjkr From 286 task to Intel386 SX CPU TSS hjkr From 286 task to virtual 8086 task Intel386 SX CPU TSS hjkr From Intel386 SX CPU task to 286 TSS hjkr From Intel386 SX CPU task to Intel386 SX CPU TSS 399 hjkr From Intel386 SX CPU task to Virtual 8086 task Intel386 SX CPU TSS hjkr JMP Unconditional jump short 11101011 8 bit displacement 74m 74m r direct within
160. peripherals and therefore these peripher als cannot initiate single cycle fly by DMA transfers An external bus master cannot talk directly to internal peripheral modules because the external address lines are outputs only However an external device could use a DMA channel to transfer data to or from an internal peripheral because the DMA generates the addresses This transaction would be a two cycle DMA bus transaction 5 2 1 2 DMA Service to an SIO or SSIO Peripheral A DMA unit is useful for servicing an SIO or SSIO peripheral operating at a high baud rate At high baud rates the interrupt response time of the core may be too long to allow the serial channels to use an interrupt to service the receive buffer full condition By the time the interrupt service routine ISR is ready to transfer the receive buffer data to memory new data would have been loaded into the buffer The issue is the interrupt latency which is the amount of time the processor takes from recognizing the interrupt to executing the first line of code in the ISR This interrupt latency needs to be calculated to determine if an ISR can handle the high baud rate If the Interrupt Latency is too high data transfers to and from the serial channels can occur within a few bus cycles of the time that a serial unit is ready to move data by using an appropriately 5 3 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel configured DMA channel SIO and SSIO inputs to t
161. processor remains in the halt or shutdown condition until one of the following occurs NMI goes active the processor then services the interrupt RESET goes active the processor is reinitialized e In the halt condition but not in the shutdown condition if maskable interrupts are enabled an active INTR input causes the processor to end the halt cycle and service the interrupt The processor can service processor extension PEREQ requests and hold HOLD requests while in the halt or shutdown condition e processor is in the halt condition and SMI goes active the processor then services the SMI When the processor is in the shutdown condition SMI has no effect BUS INTERFACE UNIT o Lr 8 NE E mem Sat Oc T 2 gt 239 9 2 DAZ r 2 d CLK2 halted until INTR SMI in the HALT state 5 NMI or RESET is asserted CPU tesponds to HOLD input CPU temain Valid 1 Valid 1 Valid 1 CLKOUT BHE A1 W R A25 2 BLE D C READY LOCK Float eat ae at ee Out Undefined D15 0 HALT cycle must be acknowledged by READY asserted This READY could be generated internally or externally A2492 02 Figure 6 10 Halt Cycle 6 27 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 6 3 6 Refresh Cycle The refresh control unit simplifies dynamic memory controller design by iss
162. register memory by 1100000w mod TTT rm immed 8 bit data wure immediate count Instruction 000 001 ROL 010 ROR 011 RCL 100 RER 101 SHL SAL 111 SAR SHLD Shift left double register memory by immed 3 7 3 7 immediate 00001111 10100100 modreg r m 8 bit data register memory by CL 00001111 10100101 mod reg r m 3 7 3 7 E 7 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Table E 1 Instruction Set Summary Sheet 7 of 19 In tel Clock Count Notes Real Pro Real Pro Ad tected Ad tected i dress Virtual dress Virtual Instruction Format Mode Ad Mode Ad or dress or dress Virtual Mode Virtual Mode 8086 8086 Mode Mode SHRD Shift right double register memory by immed 3 7 3 7 immediate 00001111 10101100 modreg r m 8 bit data register memory byCL 00001111 10101101 mod reg r m 3 7 3 7 AND And register to register 001000dw modreg r m 2 2 register to memory 0010000w modreg r m Fas Tu b h memory to register 0010001w modreg r m 6 6 b h immediate to 1000000w mod100r m immediate data 2 27 b n register memory immediate to accumu 9 9 499 40w immediate data 2 lator short form TEST And function to flags no result register memory 1000010w mod reg r m 2 5 2 5 b h and register immediate
163. segment 11101001 full displacement 74m 74m r winn segment 11111111 mod100rm ee Fe direct intersegment 11101010 unsigned full offset selector 16 m 314m jkr Protected mode only direct intersegment Via call gate to same privilege level 534m hjikr From 286 task to 286 TSS hjkr From 286 task to Intel386 SX CPU TSS From 286 task to virtual 8086 task Intel386 SX CPU TSS hjkr From Intel386 SX CPU task to 286 TSS hjkr From Intel386 SX CPU task to Intel386 SX CPU TSS h j k r From Intel386 SX CPU task to Virtual 8086 task Intel386 SX CPU TSS 395 hjkr indirect intersegment 1114 1111 mod 1 0 1 r m 174m 314m b hjkr Protected mode only indirect intersegment Via call gate to same privilege level 494m h j k r From 286 task to 286 TSS h j kr From 286 task to Intel386 SX CPU TSS h j kr From 286 task to virtual 8086 task Intel386 SX CPU TSS hjkr From Intel386 SX CPU task to 286 TSS hj kr From Intel386 SX CPU task to Intel386 SX CPU TSS 328 h j k r From Intel386 SX CPU task to Virtual 8086 task Intel386 SX CPU TSS hjkr RET Return from CALL within segment 11000011 12 b g hr Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Table E 1 Instruction Set Summary Sheet 11 of 19 Clock Count Notes Real Pro Real Pro Ad tected Ad tected Instruction Format dress Virtual dress Virtual Mode Ad Mode A
164. slave OFOAOH 00A0H require servicing If the 82C59A requires servicing this byte read only OFOA1H 00A1H indicates the highest priority pending interrupt NOTE Once the polling bit is set in OCW3 the Poll Status Byte of a particular 82C59A can be read by doing an access to any of the four addresses of that 82C59A NOTE All master 82C59A registers are accessed through two expanded or PC AT addresses all the slave registers are accessed through two other expanded or PC AT addresses The order in which you write or read these addresses along with certain register bit settings determines which register is accessed To initialize the 82C59As 1 Globally disable all maskable interrupts to the core using the CLI instruction 2 Write to the initialization command words NOTE You must initialize both the master and the slave either can be initialized first The 8259A module has a state machine that controls access to the individual registers Improper initialization occurs when the following sequences are not followed To initialize the master write to its initialization command words in order ICW1 ICW2 ICW3 then ICW4 e To initialize the slave write to its initialization command words in order ICW1 ICW2 ICW3 then ICW4 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL 9 3 4 Port 3 Configuration Register P3CFG Use the P3CFG register to connect the interrupt request signals INT3 0 to the package pins Thes
165. software routines InitTimer Initializes the specified timer s mode counter value inputs and outputs SetUp ReadBack Configures the specified timer s for a read back command CounterLatch Latches the counter value of the specified timer ReadCounter Performs a simple read command on the specified timer s current counter value TimerISR Interrupt Service Routine for timer generated interrupts Code is also included that demonstrates how to change the timer s counter value and issue a read back command See Appendix C for included header files include lt conio h gt include 80386ex h include ev386ex h A eR RR InitTimer Description This function initializes a timer s inputs outputs operating mode and initial counter value Parameters Unit Unit number of the timer The processor supports 0 1 or 2 Mode Defines Counter Mode Inputs Specifies Input sources Output Specifies Which Output to drive InitCount Value to be loaded into count register Enable Enable 1 or disable 0 Timer 10 34 intel TIMER COUNTER UNIT Returns Error Codes E INVALID DEVICE Unit number specifies a non existing device E OK Initialized No error Assumptions REMAPCFG register has Expanded I O space access enabled ESE bit set This function also initializes the Timer Counter Unit to be in the Read Write Format of least significant byte first then most significant byte Syntax int error
166. the corresponding master s IR signal NOTE Since the internal slave is cascaded from the master s IR2 signal you must set the S2 bit Initialization Command Word 3 Expanded Addr F021H ICW3 master ISA Addr 0021H write only Reset State XXH 7 0 S7 S6 S5 S4 S3 S2 51 0 Bit Bit Number Mnemonic Function 7 3 573 Slave IRs 0 No slave 8259A is attached to the corresponding IR signal of the master 1 A slave 82C59A is attached to the corresponding IR signal of the master 2 52 0 Internal slave not used 1 Internal slave is cascaded from the master s IR2 signal 1 51 Slave IRs 0 No slave 8259A is attached to the master through the IR1 signal of the master 1 A slave 82C59A is attached to the IR1 signal of the master 0 Clear this bit to guarantee device operation Figure 9 10 Initialization Command Word 3 Register ICW3 Master 9 22 intel INTERRUPT CONTROL UNIT ICW3 at OFOA1H or 00A1H is the internal slave ID register Figure 9 11 Use this register to indicate that the slave 1s cascaded from the master s IR2 signal This gives the internal slave an ID of 2 Each slave device uses the IDs to determine whether it is the slave being addressed Dur ing a slave access the slave s ID is driven on the master s CAS2 0 signals If these signals are enabled bit 7 of INTCFG is 1 they appear on the A18 16 address lines
167. the data byte received read only LCRO OF4FBH 03FBH Line Control LORI 0 8 02FBH Specifies the data frame word length number of stop bits and read write type of parity for transmissions and receptions Allows the transmitter to transmit a break condition LSRO OF4FDH 03FDH Line Status LSR1 OF8FDH 02FDH Contains the transmitter empty transmit buffer empty receive read only buffer full and receive error flags IERO OF4F9H Interrupt Enable IERI OF8F9H 02F9H Independently connects the four signals modem status receive read write line status transmit buffer empty and receive buffer full to the interrupt request output SIOINT 11 15 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Table 11 5 SIO Registers Sheet 2 of 2 Register Address Address Function IIRO OFAFAH Interrupt ID OF8FAH 02FAH Indicates whether the modem status transmit buffer empty read only receive buffer full or receiver line status signal generated an interrupt request MCRO OF4FCH Modem Control MCR1 OF8FCH 02FCH Controls the interface with the modem or data set read write Allows use of external UARTSs MSRO OF4FEH Modem Status MSR1 OF8FEH 02 Provides the current state of the control lines for the modem or read write data set to the CPU SCRO OF4FFH OSFFH Scratc
168. the row and column address buffers A3265 02 Figure 6 19 Intel386 EX Processor and Non Paged DRAM Interface 6 44 intel SYSTEM MANAGEMENT MODE CHAPTER 7 SYSTEM MANAGEMENT MODE The Intel386 EX processor provides a mechanism for system management with a combination of hardware and CPU microcode enhancements For low power systems the primary function of SMM is to provide a transparent means for power management For systems where power man agement is not critical SMM may be used for other functions such as alternate operating systems debuggers hard disk drive backup or virtual I O This chapter is organized as follows System Management Mode Overview see below SMM Hardware Interface page 7 1 System Management Mode Programming and Configuration page 7 3 The Intel386 EX Processor Identifier Registers page 7 15 Programming Considerations page 7 16 7 1 SYSTEM MANAGEMENT MODE OVERVIEW An externally generated system management interrupt SMI allows the execution of system wide routines that are independent and transparent to the operating system The system manage ment mode SMM architectural extensions to the Intel386 CPU consist of the following ele ments An interrupt input pin SMI to invoke SMM output pin SMIACT to identify execution state A new instruction RSM executable only from SMM to exit SMM 7 2 SMM HARDWARE INTERFACE The Inte1386 EX processor provides t
169. timer output would be selected as the DMA request source using the 12 6 intel DMA CONTROLLER DMACEG register but the Requester address registers would be programmed with one of the memory addresses It doesn t really matter which memory is the Requester and which is the Tar get as long as the transfer direction is set to provide the correct Source and Destination 12 2 2 4 Ready Generation For DMA Cycles DMA cycles are identical to any other type of memory or I O cycles in terms of how they are completed A valid READY must be sampled at the end of the last T2 state in order to complete a DMA Read or Write cycle This READY may be generated externally or internally using the appropriate chip select unit see Chapter 14 CHIP SELECT UNIT for a description of gener ating READY internally 12 2 2 5 Usage of the 4 Byte Temporary Register Each DMA channel has a 4 byte temporary FIFO register used for temporary data storage during two cycle transfers The way the DMA channel fills and empties this register depends on the data transfer mode the bus sizes of the source and destination and the data transfer direction The fol lowing describes how the Temporary Register is filled and emptied for the Read and Write Trans fer Directions Filling the Temporary Register Read Cycle Ina Read Cycle data is transferred from the Requester to the Target Each request DREQn in a Read Cycle results in the DMA transferring a byt
170. tion of the mod ss index and base fields The primary addressing byte the mod r m byte also contains three bits shown as TTT in Fig ure E 1 sometimes used as an extension of the primary opcode The three bits however may also be used as a register field reg When calculating an effective address either 16 bit addressing or 32 bit addressing is used 16 bit addressing uses 16 bit address components to calculate the effective address while 32 bit ad dressing uses 32 bit address components to calculate the effective address When 16 bit address ing is used the mod r m byte is interpreted as a 32 bit addressing mode specifier The following tables define all encodings of all 16 bit addressing modes and 32 bit addressing modes E 26 In tel INSTRUCTION SET SUMMARY Table E 7 Encoding of 16 bit Address Mode with mod r m Byte mod r m Effective Address mod r m Effective Address 00 000 DS BX SI 10 000 DS BX SI d16 00 001 DS BX DI 10 001 DS BX DI 416 00 010 SS BP SI 10 010 SS BP SI d16 00 011 SS BP DI 10 011 SS BX DI d16 00 100 05 51 10 100 DS SI 416 00 101 05 01 10 101 DS DI 416 00 110 DS d16 10 110 SS BP 016 00 111 DS BX 10 111 DS BX d16 01 000 DS BX SI d8 11 000 register see tables below 01 001 DS BX DI d8 11 001 register see tables below 01 010 SS BP SI d8 11 010 register see tables below 0
171. tion on the peripheral itself see the chapter describing that peripheral The symbology used for signals that share a device pin is shown in Figure 5 2 Of the two signal names by a pin the upper signal is associated with the peripheral in the figure The lower signal in parentheses is the alternate signal which connects to a different peripheral or the core When a pin has a multiplexer it is shown as a switch and the register bit that controls it is noted above the switch 5 2 1 Controller Bus Arbiter and Refresh Unit Configuration Figure 5 2 shows the DMA controller bus arbiter and refresh unit configuration Requests for a DMA data transfer are shown as inputs to the multiplexer serial I O transmitter TXEDM 0 TXEDMA1 or receiver RBFDMAO RBFDMA1 synchronous serial I O transmitter SSTBE or receiver SSRBF A timer OUTI OUT2 e An external source DRQO DRQ1 The inputs are selected by the DMA configuration register see Figure 5 3 5 2 1 1 Using The DMA Unit with External Devices For each DMA channel three bits in the DMA configuration register Figure 5 3 select the ex ternal request input or one of seven request inputs from the peripherals Another bit enables or disables that channel s DMA acknowledge signal DACKn at the device pin Enable the DACKntt signal only when you are using the external request signal DRQn and need DACKni The acknowledge signals are not routed to the on chip
172. to the reload registers Figure 17 4 1 Write the upper 16 bits of the reload value to WDTRLDH 2 Write the lower 16 bits of the reload value to WDTRLDL In the general purpose timer mode you cannot reload the counter except on a WDT timeout However you can force a reload by entering bus monitor mode allowing an ADS to reload the counter then switching back to general purpose timer mode 17 4 intel WATCHDOG TIMER UNIT 17 2 3 Software Watchdog Mode In software watchdog mode system software must periodically reload the down counter with a reload value or the timer expires and asserts WDTOUT The reload value depends on the design ofthe system software In general determining the proper reload value requires software analysis and some experimentation After reset the WDT defaults to general purpose timer mode Unless you intervene the WDT times out after 4 million 222 processor clock cycles If you want to use the WDT as a system watchdog use this sequence to enable watchdog mode 1 Write the upper 16 bits of the reload value to WDTRLDH Figure 17 4 2 Write the lower 16 bits of the reload value to WDTRLDL Figure 17 4 3 Write two sequential words OFO1EH followed by OFE1H to the WDTCLR location OF4C8H This sequence called a lockout sequence sets the WDTEN bit in the watchdog status register and loads the contents of the reload value register into the down counter Regardless of the values of the two contro
173. transfer complete signal to the interrupt control unit s DMAINT input Note When channel 0 is in chaining mode DMACHR 2 1 and DMACHR 0 0 this bit is a don t care D 19 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel D 15 DMAIS DMA Interrupt Status Expanded Addr 019 DMAIS ISA Addr read only Reset State 00H 7 0 TC1 TCO CIO Bit Bit Number Mnemonic Function 7 6 Reserved These bits are undefined 5 TC1 Transfer Complete 1 When set this bit indicates that channel 1 has completed a buffer transfer either its byte count expired or it received an EOP input This bit is set only if bit 1 of the interrupt enable register is set Reading the DMA status register DMASTS clears this bit Note In chaining mode this bit becomes a don t care 4 TCO Transfer Complete 0 When set this bit indicates that channel 0 has completed a buffer transfer either its byte count expired or it received an EOP input This bit is set only if bit 0 of the interrupt enable register is set Reading the DMA status register DMASTS clears this bit Note In chaining mode this bit becomes a don t care 3 2 Reserved These bits are undefined 1 Cit Chaining Interrupt 1 When set this bit indicates that new requester and target addresses and a new byte count should be written to channel 1 This bit is cleared when new transfer in
174. transfers A byte count configured for 16 bit decrementing expires when it is decremented from 0000H to OFFFFH tel DMA Overflow Enable Expanded Addr F01DH DMAOVFE ISA Addr read write Reset State OAH 7 0 ROV1 TOV1 ROVO TOVO Bit Bit Number Mnemonic Function 7 4 Reserved These bits are undefined for compatibility with future devices do not modify these bits 3 ROV1 Channel 1 Requester Overflow Enable 0 lowest 16 bits of requester address increment decrement 1 all bits of requester address increment decrement 2 TOV1 Channel 1 Target amp Byte Counter Overflow Enable 0 lowest 16 bits of target address and byte count increment decrement 1 all bits of target address and byte count increment decrement 1 ROVO Channel 0 Requester Overflow Enable 0 lowest 16 bits of requester address increment decrement 1 all bits of requester address increment decrement 0 TOVO Channel 0 Target amp Byte Counter Overflow Enable 0 lowest 16 bits of target address and byte count increment decrement 1 all bits of target address and byte count increment decrement Figure 12 21 DMA Overflow Enable Register DMAOVFE 12 34 intel 12 3 5 Command 1 Register DMACMD1 Use DMACMDI to enable both channels and to select the rotating method for changing the bus control priority structure DMA CONTROLLER
175. type least 3 bit must be 0 SetEXRegByte ICW3S 0x2 Set slave ID _SetEXRegByte ICW4S 0 1 Set bit 0 to guarantee operation cfg pins GetEXRegByte INTCFG cfg pins SlavePins SetEXRegByte INTCFG SlavePins Set Slave external interrupt pins return E OK InitICUSlave RRR IKK KK I KK k KK Ck Ck Kk k k k k k k k k k kk k k k k kc k k k k eek Disable8259Interrupt Description Disables 8259a interrupts for the master and the slave Parameters MstrMask Mask value for master ICU SlaveMask Mask value for slave ICU Each bit location that is set disables the corresponding interrupt by setting the bit in the interrupt control register For example to disable master IR3 and IR5 set MstrMask 0x28 bits 3 and 5 are set Returns None Assumptions REMAPCFG register has Expanded I O space access enabled ESE bit set Syntax ICU IRQ Mask Values define IRO 0 1 define IRI 0 2 define IR2 0 4 define 0 8 define IRA 0 10 define 5 0x20 define IR6 0x40 9 36 intel INTERRUPT CONTROL UNIT define IR7 0x80 Disable8259Interrupt IRO IR1 IR3 IRA IR5 IR6 IR7 IR1 IR2 IRA IR5 IR6 Real Protected Mode No changes required kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk void Disable8259Interrupt BYTE MstrMask BYTE SlaveMask BYTE Mask if MstrMask 0 Mask _G
176. undefined for compatibility with future devices do not modify this bit 6 PM6 Pin Mode 0 Selects CS6 at the package pin 1 Selects REFRESH at the package pin 5 5 0 Selects the coprocessor signals PEREQ BUSY and ERROR Z at the package pins 1 Selects the timer control unit signals TMROUT2 TMRCLK2 and TMRGATE2 at the package pins 4 4 Pin Mode 0 Selects DACKO at the package pin 1 Selects CS5 at the package pin 3 0 Selects EOP at the package pin 1 Selects CTS1 at the package pin 2 PM2 Pin Mode 0 Selects DACK1 at the package pin 1 2 Selects TXD1 at the package pin 1 1 Pin Mode 0 Selects SRXCLK at the package pin 1 Selects DTR1 at the package pin 0 PMO Pin Mode 0 Selects SSIOTX at the package pin 1 Selects RTS1 at the package pin Figure 5 15 Pin Configuration Register PINCFG 5 24 intel DEVICE CONFIGURATION P1CFG 7 read write Port 1 Configuration Expanded Addr ISA Addr Reset State F820H 00H PM7 PM6 PM5 PM4 PM2 PM1 PMO Bit Number Bit Mnemonic Function 7 PM7 Pin Mode 0 Selects P1 7 atthe package pin 1 2 Selects HLDA at the package pin PM6 Pin Mode 0 Selects P1 6 at the package pin 1 Selects HOLD at
177. virtual 8086 mode within task 113 From Intel386 SX CPU task to 286 TSS 324 9 h j k r From Intel386 SX CPU task to Intel386 SX CPU TSS 328 g h j k r From Intel386 SX CPU task to virtual 8086 task 377 9 h j r From Intel386 SX CPU task to virtual 8086 mode within task 113 PROCESSOR CONTROL INSTRUCTIONS HLT Halt 11110100 7 Move to and from control debug test registers CRO CR2 CR3 from 10 4 5 10 4 5 register 00001 00100010 11eeereg register from CRO 3 00001111 00100000 eeereg 6 6 1 DRO 3 from register 00001 00100011 eeereg 22 22 DR6 7 from register 00001 00100011 eeereg 16 16 register from DR6 7 00001111 00100001 eeereg 14 14 1 register from DRO 3 00001111 00100001 eeereg 22 22 1 TR6 7 from register 00001 00100110 11 12 12 1 register from TR6 7 00001111 00100100 leeereg 12 12 No operation 10010000 3 3 WAIT Wait until BUSY 10011011 6 6 pin is negated PROCESSOR EXTENSION INSTRUCTIONS Processor Extension 11011TTT mod LL L r m See h Escape Intel387 SX TTT and LLL bits are opcode datashe information for coprocessor et for clock counts E 18 intel Table E 1 Instruction Set Summary Sheet 18 of 19 INSTRUCTION SET SUMMARY Clock Count Notes Real Pro Real Pro dress Virtual dress Viral Instruction Format Mod
178. write function that writes a single character Serial WriteStr Polled serial write function that writes out an entire string of characters SerialWriteMem Polled serial write function that writes out a specified number of characters stored in a buffer Serial ISR Template interrupt service routine for SIO 0 interrupts Service RBF Service routine for interrupts generated by the Receive Buffer Full signal SerialWriteStr Int Interrupt driven serial write function Service TBE Service routine for interrupts generated by the Transmit Buffer Empty signal The last software routine shows how to use these functions to enable RBF interrupts on the SIO See Appendix C for the included header files include lt conio h gt include lt stdio h gt include 80386ex h include ev386ex h Variable Declarations int Tbuffer_index 0 char trans_buffer 1024 char rec_buffer Yet eR ee ee ee ee ee ee ee k k k k k k k k k k k kk k k k k k kk k k k k k InitSIO Description Initialization routine for Asynchronous Serial I O Port Parameters Unit Unit number of the serial port 0 for SIO port 0 T for SLO port L Mode Defines Parity number of data bits number of stop bits Reference Serial Line Control register for various 11 33 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel options ModemCntrl Defines the operation of the modem control lines BaudRate Specifies baud rate The baud divisor value i
179. zero when the CPU reads the Modem Status register Modem Status MSRO MSR1 MSRO MSR1 Expanded Addr F4FEH F8FEH read only ISA Addr OSFEH 02 Reset State 7 0 RI DSR CTS DDCD TERI DDSR DCTS Bit Bit _ Function Number Mnemonic unctio 7 DCD Data Carrier Detect This bit is the complement of the data carrier detect DCDn input In diagnostic test mode this bit is equivalent to MCRn 3 OUT2 6 RI Ring Indicator This bit is the complement of the ring indicator Rl input In diagnostic test mode this bit is equivalent to MCRn 2 OUT1 5 DSR Data Set Ready This bit is the complement of the data set ready DSRn input In diagnostic test mode this bit is equivalent to MCRn 0 DTR 4 CTS Clear to Send This bit is the complement of the clear to send CTS ni input In diagnostic test mode this bit is equivalent to MCRn 1 RTS 3 DDCD Delta Data Carrier Detect When set this bit indicates that the DCDn input has changed state since the last time this register was read Reading this register clears this bit 2 TERI Trailing Edge Ring Indicator When set this bit indicates that the input has changed from a low to a high state since the last time this register was read Reading this register clears this bit 1 DDSR Delta Data Set Ready When set this bit indicates that the DSRn input has changed state since the last time this register was re
180. 0 2 define IR2 0 4 define 0x8 define IRA 0 10 define IR5 0x20 define IR6 0x40 define IR7 0x80 ICU EOI Types define NONSPECIFIC EOI 0x20 define SPECIFIC EOI 0x60 define NonSpecificEOI _SetEXRegByte OCW2S NONSPECIFIC EOI _SetEXRegByte OCW2M NONSPECIFIC EOI define MstrSpecificEOI irq _SetEXRegByte OCW2M 0x60 BYTE amp 0 7 define SlaveSpecificEOI irq _SetEXRegByte OCW2S 0x60 BYTE amp 0 7 define Master 1 define Slave 0 ICU Function Definitions extern extern extern extern extern extern extern int int void int void void int InitICU BYTE MstrMode BYTE MstrBase BYTE MstrCascade BYTE SlaveMode BYTE SlaveBase BYTE MstrPins BYTE SlavePins InitICUSlave BYTE SlaveMode BYTE SlaveBase BYTE SlavePins SetInterruptVector void far interrupt IntrProc void int Vector int IntrType SetIRQOVector void far interrupt IntrProc void int int IntrType Enable8259Interrupt BYTE MstrMask BYTE SlaveMask Disable8259Interrupt BYTE MstrMask BYTE SlaveMask Poll Command int Master or Slave C 7 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel RR e e ke e e e KK Asynchronous C 8 fine fine fine fine fine fine fine fine fine fine fine fine fine fine fine fine fine fine fine fine fine fine fine fine fine fine fine fine fine fine fine fin
181. 0 1 10 3 10 21 13 1 13 5 13 18 PSCLK frequency Controlling 8 7 PSRAM 15 11 R RAS only refresh 15 1 15 12 RCU See Refresh control unit Ready logic 6 10 Real mode 9 8 Refresh control unit 15 1 15 16 bus arbitration 15 5 configuring 5 3 connections 15 3 design considerations 15 11 dynamic memory control 15 1 operation 15 5 overview 15 2 15 5 programming 15 6 15 10 RFSADD 15 10 D 54 RFSADD register 15 10 RFSBAD 15 9 D 54 RFSBAD register 15 9 RFSCIR 15 7 D 55 RFSCIR register 15 7 RFSCON 15 8 D 55 RFSCON register 15 8 refresh addresses 15 4 refresh intervals 15 4 refresh methods 15 1 intel register addresses 4 18 D 4 registers 15 6 signals 15 4 Register naming conventions 1 4 organization 4 1 4 20 Register bits notational conventions 1 4 Register names notational conventions 1 4 Register status during SMM 7 3 Registers BOUND 18 2 BYPASS 18 2 CLKPRS 8 6 8 7 13 16 13 19 D 7 Component and revision ID 7 15 CSnADH 14 14 14 17 D 8 CSnADL 14 14 14 18 D 9 CSnMSKH 14 14 14 19 D 10 CSnMSKL 14 14 14 20 D 11 DLHn 11 15 11 22 D 12 DLLz 11 15 11 22 D 12 DMAOBYOn 12 28 12 33 D 24 DMAOREQn 12 28 12 33 D 24 DMAOTARn 12 28 12 33 D 24 DMAIBYCn 12 28 12 33 D 24 DMAIREQn 12 28 12 33 D 24 DMAITARnz 12 28 12 33 D 24 DMABSR 12 29 12 46 D 13 DMACEG 5 6 12 28 12 32 D 14 DMACHR 12 30 12 47 D 15 DMACMDI 12 28 12 35 D 16 DMACMD2 12 29
182. 0 High impedance On Circuit Emulation ONCE mode test optional instruction HIGHZ Used to place device pins into their inactive drive states Allows BYPASS external components to drive signals onto connections that the processor normally drives The opcode is the sequence of data bits shifted serially into the instruction register IR from the TDI input The opcodes for EXTEST and BYPASS are mandated by IEEE 1149 1 so they should be the same for all JTAG compliant devices The remaining opcodes are designer defined so they may vary among devices All unlisted opcodes are reserved Use of reserved opcodes could cause the device to enter reserved factory test modes 18 7 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 18 2 4 Data Registers The test logic unit uses three data registers bypass identification code and boundary scan The instruction determines which data register is used The single bit bypass register BYPASS provides a minimal length serial path between TDI and TDO During board level testing you can use this path for any devices that are not currently un der test This speeds access to the data registers for the devices that are being tested The 32 bit identification code register IDCODE identifies a device by manufacturer part num ber and version number Figure 18 4 describes the register and shows the values for the Intel386 EX processor
183. 0 MHz processor clock 20 MHz 14 4 Kb s 0 94 8 MHz processor clock 16 MHz 2400 b s 0 16 34H 8 MHz processor clock 16 MHz 9600 b s 0 16 23H 8 MHz processor clock 16 MHz 14 4 Kb s 0 79 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 11 2 2 SIOn Transmitter The data frame for transmissions is programmable It consists of a start bit 5 to 8 data characters an optional parity bit and 1 to 2 stop bits The transmitter can produce even odd forced or no parity The transmitter can also produce break conditions A break condition forces the serial out put TXDn to the spacing logic 0 state for longer than a transmission time the time of the start bit data bits parity bit stop bits On the receiving end a break condition sets an error flag Forced parity sticky bit allows the SIO to be used in multiprocessor communications When using forced parity the serial port uses the parity bit to distinguish between address and data bytes Forced parity is enabled in the SIO by setting the PEN and SP bits in the serial line control register Figure 11 15 When enabled for forced parity the bit that is transmitted in the parity bit location is the complement of the EPS bit also in the serial line control register In the receiver if PEN and SP are 1 the receiver compares the bit that is received in the parity bit location with the com plement of the EPS bit If the values being compared are n
184. 0 define this counter s operation 00 counter 0 01 counter 1 10 counter 2 11 is not an option for TMRCON s control word format Selecting 11 accesses TMRCON s read back format which is shown in Figure 10 29 5 4 RW1 0 Read Write Select These bits select a read write option for the counter specified by bits 7 6 01 read write least significant byte only 10 read write most significant byte only 11 read write least significant byte first then most significant byte 00 is not an option for TMRCON s control word format Selecting 00 accesses TMRCON s counter latch format which is shown in Figure 10 27 3 1 M2 0 Mode Select These bits select an operating mode for the counter specified by bits 7 6 000 mode 0 001 mode 1 X10 mode 2 X11 mode 3 100 mode 4 101 2 mode 5 X is a don t care 0 CNTFMT Count Format This bit selects the count format for the counter specified by bits 7 6 0 binary 16 bits 1 binary coded decimal 4 decades D 64 intel SYSTEM REGISTER QUICK REFERENCE D 67 TMRn Timer n Read Format Expanded Addr F040H F041H TMRn n 0 2 F042H ISA Addr 0040H 0041H 0042H Reset State XXH 7 0 CV7 CV6 CV5 CV4 CV2 CV1 CVO Bit Bit Number Mnemonic Function 7 0 CV7 0 Count Value These bits contain the counter s count value When reading the counter s count value follow the read selection specified in the counter s
185. 00H SRAM for SMM Real Protected Mode No changes required 7 16 intel SYSTEM MANAGEMENT MODE RP Bi AS SL ENS GEN BAe NG SIG ING Bot Ne SENS void SerialWriteStr2 Loops while writing a char out to the serial port asm ax 0x3900 mov BS ax mov sp 0x100 Forever mov O0xf4fd TstStatus in al testal 0x20 je TstStatus Code below is same as SetEXRegByte TransmitPortAddr X mov ax X mov Oxf4f8 out dx al jmp Forever ROR K K k KR ke KK ke ke ke KK ee Function SerialWriteStr KKKKKKKKKKKKKKKKKKKKKKKKKK Parameters Unit Unit number of the serial port 0 for SIO port 0 1 for SIO port 1 Character string to be written out the serial port Returns None Assumptions None Real Protected Mode void SerialWriteStr int Unit const char far str WORD TransmitPortAddr WORD StatusPortAddr Set Port base based on serial port used TransmitPortAddr Unit TBR1 TBRO StatusPortAddr Unit LSR1 LSRO fort ste le X r SEEFF Wait until buffer is empty while GetEXRegByte StatusPortAddr amp SIO TX BUF EMPTY Write Character SetEXRegByte TransmitPortAddr str 7 17 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel ROR K k k k kk ck kk ke ke kk ke kk ek ke ke Function InitSIO KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK Parameters Unit Unit number of the serial por
186. 1 21 56 STXCLK 81 P2 7 7 BLE 32 A22 57 FLT 82 UCS 8 BHE 33 A23 58 P1 0 83 CS6 REFRESH 9 ADS 34 A24 59 P1 1 84 LBA 10 NA 35 A25 60 P1 2 85 DO 11 1 36 5 61 1 3 86 D1 12 37 P3 0 TMROUTO 62 P14 87 D2 INT9 13 A3 38 P3 1 TMROUT1 63 PL5 88 D3 INT8 14 A4 39 SRXCLK 64 P1 6 HOLD 89 D4 15 AS 40 SSIORX 65 RESET 90 D5 16 A6 41 SSIOTX 66 P1 7 HLDA 91 D6 17 A7 42 P3 2 INTO 67 DACK1 TXD1 92 D7 18 8 43 P3 3 INT1 68 EOP 93 D8 19 AQ 44 P3 4 INT2 69 WDTOUT 94 D9 20 A10 45 P3 5 INT3 70 DRQO 95 D10 21 11 46 P3 6 PWRDOWN 71 DRQ1 RXD1 96 D11 22 12 47 P3 7 SERCLK 72 SMIACT 97 D12 23 A13 48 PEREQ TMRCLKk2 73 P2 0 98 D13 24 A14 49 NMI 74 P2 1 99 D14 100 D15 NOTES 1 Bit 0 is closest to TDI bit 100 is closest to TDO 2 The boundary scan chain consists of 101 bits however each bit has both a control cell and a data cell so an EXTEST instruction requires 202 shifts 101 bits X 2 cells 18 9 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 18 3 TESTING This section explains how to use the test logic unit to test the device and the board interconnec tions For any test you must load an instruction and perform an instruction scan cycle then sup ply the correct sequence of ones and zeros to move the TAP controller through the required states to perform the test 18 3 1 Identifying the Device The IDCODE instruction allows you to determine the contents of a device s IDCODE
187. 1 011 SS BP DI d8 11 011 register see tables below 01 100 DS SI 48 11 100 register see tables below 01 101 DS DI 48 11 101 register see tables below 01 110 SS BP 48 11 110 register see tables below 01 111 DS BX d8 11 111 register see tables below Register Specified by r m During 16 bit Data Operations Function of w Field mod r m when w 0 when w 1 11 000 AL AX 11 001 CL CX 11 010 DL DX 11 011 BL BX 11 100 AH SP 11 101 CH BP 11 110 DH SI 11 111 BH DI Register Specified by r m During 32 bit Data Operations Function of w Field mod r m when w 0 when w 1 11 000 AL EAX 11 001 CL ECX 11 010 DL EDX 11 011 BL EBX 11 100 AH ESP 11 101 CH EBP 11 110 DH ESI 11 111 BH EDI E 27 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Table E 8 Encoding of 32 bit Address Mode with Byte No s i b Byte Present mod r m Effective Address mod r m Effective Address 00 000 DS EAX 10 000 DS EAX d32 00 001 DS ECX 10 001 DS ECX d32 00 010 SS EDX 10 010 SS EDX d32 00 011 SS EBX 10 011 SS EBX d32 00 100 S i b is present 10 100 S i b is present 00 101 DS d32 10 101 SS EBP d32 00 110 DS ESI 10 110 SS ESI 432 00 111 DS EDI 10 111 DS EDI 432 01 000 DS EAX 48 11 000 register see tables below 01 001 DS ECX 48 11 001 register see t
188. 1 5 SIO Registers Sheet 1 of 2 Expanded PC AT Register Address Address Function PINCFG OF826H E Pin Configuration read write Connects the SIO1 transmit data TXD1 data terminal ready DTR1 and request to send RTS1 signals to package pins P1CFG OF820H Port 1 Configuration read write Connects the SIOO ring indicator RIO data set ready DSRO data terminal ready DTRO request to send RTSO and data carrier detected DCDO signals to package pins P2CFG 0 822 Port 2 Configuration read write Connects the 5100 clear to send CTSO transmit data TXDO and receive data RXDO signals to package pins P3CFG OF824H Port 3 Configuration read write Connects COMCLK to the package pin SIOCFG 0 836 SIO and SSIO Configuration read write Connects the SIOn modem input signals internally or to package pins and connects either the internal SERCLK signal or the COMCLK pin to the SIOn baud rate generator input DLLO OF4F8H 03F8H Divisor Latch Low DLL1 3 OF8F8H 02F8H Stores the lower 8 bits of the SIOn baud rate generator divisor read write DLHO OFAF9H 03F9H Divisor Latch High DLH1 OF8F9H 02F9H Stores the upper 8 bits of the SIOn baud rate generator divisor read write TBRO OF4F8H 03F8H Transmit Buffer TBR1 OF8F8H 02F8H Holds the data byte to transmit write only RBRO OF4F8H 03F8H Receiver Buffer RBR1 OF8F8H 02F8H Holds
189. 1 Device pin DMA Channel 1 Requests input The SIO channel 1 receiver SIO channel 1 transmitter SIO1 RBFDMA1 TXEDMA1 Internal SIO channel 0 transmitter SIO channel 0 receiver SSIO SIO0 TXEDMAO RBFDMAO signals receiver SSIO transmitter TCU counter 2 output or an SSIO Receiver Transmitter external device can request DMA channel 1 service TCU Counter 2 These sources are referred to as channel 1 hardware requests You can also issue channel 1 software requests by writing to the DMA software request register DACKn Device pin DMA Channel n Acknowledge output Indicates that channel n is ready to service the requesting device An external device uses the DRQn pin to request DMA service the DMA uses the DACKn pin to indicate that the request is being serviced EOP Device pin End of process As an input Activating this signal terminates a DMA transfer As an output This signal is activated when a DMA transfer completes 12 4 intel DMA CONTROLLER 12 2 DMA OPERATION The following sections describe the operation of the DMA See Register Definitions on page 12 28 for details on implementing DMA Controller options 12 2 4 DMA Transfers The DMA transfers data between a requester and a target The data can be transferred from the requester to target or vice versa The target addresses and requester addresses can be located in either memory or I O space and data transfers can be on a byte or word
190. 100 AH SP 101 CH BP 110 DH SI 111 BH DI Register Specified by reg Field During 32 bit Data Operations Function of w Field reg when w 0 when w 1 000 AL EAX 001 CL ECX 010 DL EDX 011 BL EBX 100 AH ESP 101 CH EBP 110 DH ESI 111 BH EDI E 2 2 3 Encoding of the Segment Register sreg Field The sreg field in certain instructions is a 2 bit field allowing one of the four 80286 segment reg isters to be specified The sreg field in other instructions is a 3 bit field allowing the FS and GS segment registers to be specified Table E 6 Encoding of the Segment Register sreg Field m au Segment Register Selected go im Segment Register Selected 00 ES 000 ES 01 CS 001 CS 10 SS 010 SS 11 DS 011 DS 100 FS 101 GS 110 do not use 111 do not use E 25 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel E 2 2 4 Encoding of Address Mode Except for special instructions such as PUSH or POP where the addressing mode is pre deter mined the addressing mode for the current instruction is specified by addressing bytes following the primary opcode The primary addressing byte is the mod r m byte and a second byte of ad dressing information the s i b scale index base byte can be specified The s i b byte is specified when using 32 bit addressing mode and the mod r m byte has r m 100 and mod 00 01 or 10 When the s i b byte is present the 32 bit addressing mode is a func
191. 11 32 11 1 OVERVIEW Each SIO channel contains a baud rate generator transmitter receiver and modem control unit These are shown in Figure 11 1 for SIO Unit 1 see Figure 5 8 on page 5 15 for the SIO Unit 0 configuration The baud rate generator can be clocked by either the internal serial clock SER CLK signal or the COMCLK pin The transmitter and receiver contain shift registers and buffers Data to be transmitted is written to the transmit buffer The buffer s contents are transferred to the transmit shift register and shifted out via the transmit data pin TXDn Data received is shifted in via the receive data pin RXDn When a data byte is received the contents of the receive shift register are transferred to the receive buffer The modem control logic provides interfacing for the handshaking signals between an SIO channel and a modem or data set In addition to the transmit and receive channels each SIO can generate an interrupt or a request to the DMA unit or both An interrupt can be generated when an error has occurred in the receive channel when the transmit channel is ready to transmit another character when the receive chan nel is full or when a change in any of the modem control signals has occurred A DMA request may be issued any time a channel s receive buffer is full or its transmit buffer is empty This al lows the SIO to run at higher speeds for more efficient processing of serial data Intel386 EX EMBEDDED MI
192. 11 gj To different privilege level From 286 task to 286 TSS via Task Gate 358 gj kr From 286 task to Intel 386 SX CPU TSS via Task Gate 388 g j k r From 286 task to virtual 8086 mode via Task Gate 335 g hkr From Intel386 SX CPU task to 286 TSS via Task Gate 368 g kr From Intel386 SX CPU task to Intel 386 SX CPU TSS via task gate 398 9 From Intel386 SX CPU task to virtual 8086 mode via Task Gate 347 gikt From virtual 8086 mode to 286 TSS via Task Gate 368 g j k r From virtual 8086 mode to Intel 386 SX CPU TSS via task gate 398 g j k r From virtual 8086 mode to privilege level 0 via trap gate or interrupt gate 223 INTERRUPT RETURN IRET Interrupt return 11001111 24 9 D k Protected Mode Only IRET To same privilege level within task 42 9 h j r Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Table E 1 Instruction Set Summary Sheet 17 of 19 In tel Clock Count Notes Real Pro Real Pro Ad tected Ad tected Instruction Format dress Virtual dress Virtual Mode Ad Mode Ad or dress or dress Virtual Mode Virtual Mode 8086 8086 Mode Mode To different privilege level within task 86 9 h j r From 286 task to 286 TSS 285 9 h j r From 286 task to Intel386 SX CPU TSS 318 9 h j k r From 286 task to virtual 8086 task 267 g h j F From 286 task to
193. 12 37 D 17 DMAGRPMSK 12 29 12 45 D 18 DMAIEN 12 30 12 48 D 19 DMAIS 12 30 12 49 D 20 DMAMODI 12 29 12 38 12 39 D 21 DMAMOD2 12 29 12 40 12 41 D 22 DMAMSK 12 29 12 44 D 23 DMAOVFE 12 30 12 34 DMASRR 12 29 12 42 12 43 D 26 DMASTS 12 29 12 36 D 27 9 20 D 28 ICW2 9 21 D 29 ICW3 9 22 9 23 D 29 D 30 ICWA 9 24 D 30 INDEX IDCODE 18 2 D 31 Identifier 7 15 IERn 11 15 11 27 D 32 11 16 11 28 D 33 INTCFG 5 10 9 19 D 34 IR 18 7 D 35 LCRn 11 15 11 25 D 36 LSRn 11 15 11 26 D 37 MCRn 11 16 11 29 11 30 D 38 MSRn 11 16 11 31 D 39 OCWI 9 25 D 40 OCW2 9 26 D 41 OCW3 9 27 D 42 PICFG 5 25 11 15 11 18 D 43 P2CFG 5 26 11 15 11 19 14 14 14 16 D 44 P3CFG 5 27 9 18 10 4 10 22 11 15 11 20 D 45 PINCFG 5 24 10 4 10 23 11 15 11 17 12 28 12 31 13 16 13 17 14 14 14 15 D 46 PnCFG 11 15 16 6 16 7 PnDIR 16 6 16 8 D 47 PnLTC 16 6 16 8 D 48 PnPIN 16 6 16 9 D 48 POLL 9 28 D 49 PORT92 5 22 D 50 Port92 5 22 PWRCON 8 6 8 8 17 11 D 51 11 15 11 24 D 52 4 6 4 7 D 53 RFSADD 15 10 D 54 RFSBAD 15 9 D 54 RFSCIR 15 7 D 55 RFSCON 15 8 D 55 SCRn 11 16 11 32 D 56 SIOCFG 5 17 11 15 11 21 13 16 13 18 D 57 SMM revision ID 7 15 SSIOBAUD 13 16 13 20 D 58 SSIOCONI 13 16 13 21 13 22 D 59 SSIOCON2 13 16 13 23 SSIOCTR 13 16 13 21 D 60 SSIORBUF 13 16
194. 14 PICFG4 nd RIO Ring Indicator To From I O Port 1 P1 4 Alternate pin signals are in parentheses A2521 02 Figure 5 8 Serial I O Unit 0 Configuration 5 15 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel SIO1 SIOCFG 1 1 P3CFG7 COMCLK BCLKIN To F VO P P3 7 t SERCLK o From I O Port 3 0 Receive Data r RXD1 To DMA DRQ1 SIOINT1 99 To ICU RBFDMA1 37 To DMA TXEDMA1 32 DMA 4 PINCFG 2 Transmit Data TXD1 SIOGFG 7 From gt 9 DACK1 1 PINCFG 3 CTS1 Clear to Send P To From DMA m UM EOP Request to Send oe U RTS1 From SSIO SSIOTX P DsRi4 To From SSIO STXCLK Pun 0 01 Data Carrier To DMA DRQO Detect 41 PINCFG 1 Zx U DTR14 Data Set Ready Data Terminal Ready To From SSIO SRXCLK Ri Ring Indicator To SSIO SSIORX Voc t Alternate pin signals are in parentheses A2519 02 Figure 5 9 Serial I O Unit 1 Configuration intel DEVICE CONFIGURATION SIO and SSIO Configuration Expanded Addr F836H SIOCFG ISA Addr read write Reset State 00H 7 0 S1M SOM SSBSRC S1BSRC SOBSRC Bit Bit Number Mnemonic Function 7 S1M SIO1 Modem Signal Connections 0 Connects the SIO1 modem input signals to the package pins 1 Connects the SIO1 modem input signals internally 6 SOM SIO0 Modem Signal Connections 0 Connects the SIOO mode
195. 2 3 42 b d d h 6 45 DIV Divide unsigned Accumulator 1111011w mod 110 rm register memory divisor byte 14 17 14 17 b e eh word 22 25 22 25 b e eh doubleword 38 43 38 43 b e eh E 6 intel Table E 1 Instruction Set Summary Sheet 6 of 19 INSTRUCTION SET SUMMARY Clock Count Notes Real Pro Real Pro Ad tected Ad tected i ress Virtual dress Virtual Instruction Format d Mode Ad Mode Ad or dress or dress Virtual Mode Virtual Mode 8086 8086 Mode Mode IDIV Integer divide signed Accumulator by register memory 1111011w mod 111 r m divisor byte 19 22 19 22 b e eh word 27 30 27 30 b e h doubleword 43 48 43 48 b e h AAD ASCII adjustfor 44010101 00001010 19 12 divide AAM ASCII adjust for 17 17 multiply 11010100 00001010 CBW Convert byte to 3 3 word 10011000 CWD Convert word to 10011001 2 2 double word LOGIC shift rotate instructions not through carry ROL ROR SAL SAR SHL and SHR register memory by 1 1101000w mod TTT r m 3 7 3 7 b h register memory by CL 1101001w mod TTT r m 3 7 3 7 b h register memory by hi 3 7 3 7 b h immediate count 1100000w mod TTT r m immed 8 bit data through carry RCL and RCR register memory by 1 1101000w mod TTT r m 9 10 9 10 b h register memory by CL 1101001w mod TTT r m 9 10 9 10 b h
196. 2s ICW3s ICWAs XX OCW1s POLLs Chip select Unit F400H Word CSOADL 0000H F402H Word CSOADH 0000H F404H Word CSOMSKL 0000H F406H Word CSOMSKH 0000H F408H Word CS1ADL 0000H F40AH Word CS1ADH 0000H F40CH Word CS1MSKL 0000H F40EH Word CS1MSKH 0000H F410H Word CS2ADL 0000H F412H Word CS2ADH 0000H F414H Word CS2MSKL 0000H F416H Word CS2MSKH 0000H F418H Word CS3ADL 0000H F41AH Word CS3ADH 0000H F41CH Word CS3MSKL 0000H F41EH Word CS3MSKH 0000H F420H Word CS4ADL 0000H F422H Word CS4ADH 0000H F424H Word CS4MSKL 0000H NOTES 1 Byte pointer in flip flop in DMA determines which register is accessed 2 Shaded rows indicate reserved areas D 3 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Table D 1 Peripheral Register Addresses Sheet 4 of 6 intel poris Register Reset Value F426H Word CS4MSKH 0000H F428H Word CS5ADL 0000H F42AH Word CS5ADH 0000H F42CH Word CS5MSKL 0000H F42EH Word CS5MSKH 0000H F430H Word CS6ADL 0000H F432H Word CS6ADH 0000H F434H Word CS6MSKL 0000H F436H Word CS6MSKH 0000H F438H Word UCSADL FF6FH F43AH Word UCSADH FFFFH F43CH Word UCSMSKL FFFFH F43EH Word UCSMSKH FFFFH Synchronous Serial I O Unit F480H Word SSIOTBUF 0000H F482H Word SSIORBUF 0000H F484H Byte SSIOBAUD 00H F486H Byte SSIOCON1 COH F488H Byte SSIOCON2 00H F48AH Byte SSIOCTR 00H Refresh Control Unit F
197. 3 the GATEn input is both edge and level sensitive In modes 1 2 3 and 5 a gate trigger causes the counter to load new count values 10 5 Intel386 EX EMBEDDED PROCESSOR USER S MANUAL intel Table 10 3 Operations Caused by GATEn piii Low or Falling Rising High 0 Disables counting e Enables counting 1 1 Initiates counting 2 Resets OUTn after next CLKINn 2 1 Disables counting Initiates counting Enables counting 2 Sets OUTn immediately high 3 1 Disables counting Initiates counting Enables counting 2 Sets OUTn immediately high Disables counting Enables counting Initiates counting 10 2 1 Mode 0 Interrupt on Terminal Count This mode allows you to generate a rising edge on a counter s OUT signal Initializing a counter for mode 0 drives the counter s OUTn signal low and initiates counting When the counter reach es terminal count is driven high At this point the counter rolls over and continues count ing with OUTn high stays high and the counter keeps counting down and rolling over until new count is written or you reprogram the counter You can write a new count to the counter at any time to drive OUT low and start a new counting sequence Writing a new control word re programs the counter Mode 0 basic operation is outlined below and shown in Figure 10 2 1 After a control word write OUTn is driven low 2 the CLKINnz pulse fol
198. 3 14 Interrupt Enable Register DMAIEN Use DMAIEN to individually connect channel O s and 1 s transfer complete signal to the DMAINT interrupt request output DMA Interrupt Enable Expanded Addr F01CH Number Mnemonic DMAIEN ISA Addr read write Reset State 00H 7 TC1 TCO Bit Function 7 2 Reserved These bits are undefined for compatibility with future devices do not modify these bits 1 TC1 Transfer Complete 1 0 Disables Transfer Complete interrupts 1 Connects channel 1 s transfer complete signal to the interrupt control unit s DMAINT input Note When channel 1 is in chaining mode DMACHR 2 1 and DMACHR 0 1 this bit is a don t care 0 TCO Transfer Complete 0 0 Disables Transfer Complete interrupts 1 Connects channel 0 s transfer complete signal to the interrupt control unit s DMAINT input Note When channel 0 is in chaining mode DMACHR 2 1 and DMACHR 0 0 this bit is a don t care Figure 12 33 DMA Interrupt Enable Register DMAIEN 12 48 intel DMA CONTROLLER 12 3 15 Interrupt Status Register DMAIS DMAIS indicates which source activated the DMA interrupt request signal channel O transfer complete channel 1 transfer complete channel 0 chaining or channel 1 chaining DMA Interrupt Status Expanded Addr 019 DMAIS ISA Ad
199. 3 4 SIOCFG 5 17 11 21 13 18 D 57 System management mode 2 1 7 1 7 15 CSU support 7 12 14 10 HALT restart 7 9 hardware interface 3 1 7 1 SMI 7 1 SMIACT 7 2 SMRAM state dump area 7 14 I O restart 7 1 identifier registers 3 6 7 15 interaction with idle and powerdown 8 5 overview 7 1 priority 7 7 resume instruction 7 15 SMI interrupt 7 3 7 11 7 15 during HALT cycle 7 8 during I O instruction 7 9 during SMM handler 7 10 HALT during SMM handler 7 11 SMI during SMM operation 7 12 SMRAM 7 2 state dump area 7 14 7 15 System register organization 4 1 INDEX address configuration register 4 6 address space I O for PC AT systems 4 2 addressing modes 4 9 DOS compatible mode 4 9 enhanced DOS mode 4 11 nonDOS mode 4 11 nonintrusive DOS mode 4 11 enabling disabling expanded I O space 4 8 expanded I O address space 4 3 I O address decoding techniques 4 6 organization of peripheral registers 4 5 overview 4 1 peripheral register addresses 4 15 peripheral registers 4 2 processor core architecture 4 2 programming ESE bit 4 8 REMAPCFG example 4 8 T TAP controller 18 4 TAP Test Access Port 18 1 TCU See Timer counter unit Technical support 1 7 Terminology 1 4 1 5 Glossary 1 Glossary 5 Test access port 18 1 Test logic unit See JTAG test logic unit Timer counter unit 10 1 10 33 configuring 5 11 hardware triggerable one shot See Mode 1 hardware triggered st
200. 3FF00 I O trap restart slot O3FEFC SMM revision identifier 10000H OSFEFB OSFEO00 Reserved intel SYSTEM MANAGEMENT MODE The programmer should not modify the contents of this area in SMRAM space directly SMRAM space is reserved for CPU access only and is intended to be used only when the processor is in SMM 7 3 5 Resume Instruction RSM After an SMI request is serviced the RSM instruction must be executed to allow the CPU to return to an application transparently after servicing the SMI When the RSM instruction is ex ecuted it restores the CPU state from SMRAM and passes control back to the operating system The RSM instruction uses the special opcode of OFAAH The RSM instruction is reserved for the SMI handler and should only be executed by the SMI handler Any attempt to execute the RSM outside of SMM mode results in an invalid opcode exception At the end of the RSM instruction the processor drives SMIACT high indicating the end of an SMM routine 7 4 THE Intel386 EX PROCESSOR IDENTIFIER REGISTERS The processor has two identifier registers the Component and Revision ID register and the SMM Revision ID register The component ID is 23H the component revision ID is 09H This register can be read as 2309H The SMM revision identifier is 10000H 7 15 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 7 5 PROGRAMMING CONSIDERATIONS 7 5 1 System Management Mode Code Example The
201. 4 7 6 7 7 8 2 8 3 8 5 8 6 8 7 8 8 9 1 9 2 9 3 9 5 9 6 9 8 9 9 9 10 9 11 9 12 9 13 9 14 9 15 9 16 9 17 9 18 9 19 10 1 10 2 10 3 10 4 10 5 10 6 FIGURES Page Intel386 EX Processor to SRAM FLASH 6 41 Intel386 EX Processor to PSRAM Interface 6 42 Intel386 EX Processor to Paged DRAM 6 43 Intel386 EX Processor and Non Paged DRAM 6 44 7 5 7 6 SMI During HALT iecore t tr e er e a de HR ee 7 8 SMI During 1 neten 7 9 Ae EE 7 10 Interrupted SMI A711 HALT During SMM 7 12 Clock and Power Management Unit 8 2 Clock Synchronization 83 SMM Interaction with Idle and Powerdown Modes eb 8 5 Clock Prescale Register 8 7 Power Control Register 8 8 Timing Diagram Entering and Leaving Idle Mode 8 9 Timing Diagr
202. 4 4 addition AAS ASCII adjust for 4 4 00 1 1 subtraction DAA Decimal adjust 4 4 for addition 00100 1 DAS Decimal adjust for 00101 1 4 4 subtraction E 5 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Table E 1 Instruction Set Summary Sheet 5 of 19 intel Clock Count Notes Real Pro Real Pro Ad tected Ad tected i dress Virtual dress Virtual Instruction Format Mode Ad Mode Ad or dress or dress Virtual Mode Virtual Mode 8086 8086 Mode Mode MUL multiply unsigned accumulator with 1111011w mod100r m register memory multiplier byte 12 17 12 17 b d d h 15 20 15 20 word 12 25 12 25 b d d h 15 28 15 28 doubleword 12 41 12 41 b d d h 17 46 17 46 IMUL Integer multiply signed accumulator with regis 4111011w mod 10 1 r m ter memory multiplier byte 2 17 2 17 b d d h 5 20 5 20 word 2 25 2 25 b d d h 5 28 5 28 doubleword 2 41 2 41 bd d h 7 46 7 46 register with regis 00001111 10101111 mod reg r m ter memory multiplier byte 2 17 2 17 b d dh 5 20 5 20 word 2 25 2 25 b d d h 5 28 5 28 doubleword 2 41 2 41 b d dh 7 46 7 46 register memory with 011010s1 mod reg r m immediate data immediate to register word 3 26 3 26 b d d h 4 27 doubleword 3 4
203. 4 or IR5 Connection These depend on whether INTCFG 4 is set or clear 0 Connects Vss to the slave IR5 signal 1 Connects either the INT6 pin or DMAINT to the slave 5 signal 1 IR1 Internal Slave IR1 Connection 0 Connects the SSIO interrupt signal SSIOINT to the slave IR1 signal 1 Connects the INT5 pin to the slave IR1 signal 0 IRO Internal Slave IRO Connection 0 Connects Vss to the slave IRO signal 1 Connects the INT4 pin to the slave IRO signal Figure 9 7 Interrupt Configuration Register INTCFG 9 19 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL 9 3 3 Initialization begins with writing ICW1 Use ICW1 to select the interrupt request triggering type level or edge The following actions occur within an 82C59A module when its ICW1 is written Initialization Command Word 1 ICW1 The interrupt mask register is cleared enabling all interrupt request signals The IR7 signal is assigned the lowest interrupt level default Special mask mode is disabled Initialization Command Word 1 master slave ICW1 master and slave Expanded Addr F020H write only ISA Addr 0020H Reset State XXH XXH 7 0 0 0 RSEL1 LS 0 0 1 Bit Bit Number Mnemonic Function 7 5 Clear these bits to guarantee device operation 4 RSEL1 Register Select 1 Also see OCW2 and OCW3 ICW1 OCW2 and OCW3 are access
204. 4A0H Word RFSBAD 0000H F4A2H Word RFSCIR 0000H F4A4H Word RFSCON 0000H F4A6H Word RFSADD OOFFH Watchdog Timer Unit F4COH Word WDTRLDH 003FH F4C2H Word WDTRLDL FFFFH Word WDTCNTH 003FH F4C6H Word WDTCNTL FFFFH F4C8H Word WDTCLR Not a register F4CAH Byte WDTSTATUS 00H NOTES 1 Byte pointer in flip flop in DMA determines which register is accessed 2 Shaded rows indicate reserved areas intel SYSTEM REGISTER QUICK REFERENCE Table D 1 Peripheral Register Addresses Sheet 5 of 6 pinnis Pee NEM Register Name Reset Value Asynchronous Serial I O Channel 0 1 FAF8H 03F8H Byte RBRO TBRO DLLO XX XX 02H FAF9H 03F9H Byte IERO DLHO 00H 00H FAFAH Byte IIRO 01H F4FBH 03FBH Byte LCRO 00H FAFCH MCRO 00H FAFDH O3FDH Byte LSRO 60H FAFEH O3FEH Byte MSRO FAFFH O3FFH Byte SCRO XX Clock Generation and Power Management F800H Byte PWRCON 00H F804H Word CLKPRS 0000H Device Configuration Registers F820H Byte P1CFG 00H F822H Byte P2CFG 00H F824H Byte P3CFG 00H F826H Byte PINCFG 00H F830H Byte DMACFG 00H F832H Byte INTCFG 00H F834H Byte TMRCFG 00H F836H Byte SIOCFG 00H Parallel I O Ports F860H Byte P1PIN XX F862H Byte P1LTC FFH F864H Byte P1DIR FFH F868H Byte P2PIN XX F86AH Byte P2LTC FFH F86CH Byte P2DIR FFH F870H Byte P3PIN XX F872H Byte PSLTC FFH F874H Byte P3DIR FFH NOTE
205. 6 4 4 Locked Cycle Activators The LOCK signal is activated explicitly by the LOCK prefix on certain instructions The in structions are listed in the Intel386TM SX Microprocessor Programmer 5 Reference Manual order number 240331 LOCK is also asserted automatically for XCHG instructions descriptor up dates and interrupt acknowledge cycles 6 4 2 Locked Cycle Timing LOCK is activated on the CLK2 edge that begins the first locked bus cycle and deactivated when READY is sampled active at the end of the last bus cycle to be locked LOCK is activated and deactivated on these CLK2 edges regardless of address pipelining If address pipelining is used LOCK remains active until the current bus cycle is completed READY sampled active for the current bus cycle Consequently the LOCK signal can extend into the next memory access cy cle that does not need to be locked See Figure 6 14 The result is that the use of the bus by an other bus master is delayed by one bus cycle 6 34 intel BUS INTERFACE UNIT Unlocked Locked Locked Unlocked Bus Cycle Bus Cycle Bus Cycle Address Asserted LOCK Deasserted LOCK READY a gt Cy ae ok Co ae ae ey A2489 02 Figure 6 14 LOCK Signal During Address Pipelining 6 4 58 LOCK Signal Duration The maximum duration of the LOCK signal affects the maximum HOLD request latency be cause HOLD is recognized only after LOCK goes inactiv
206. 6 EX Processor Peripheral Registers sse ADDRESS SPACE FOR PC AT SYSTEMS EXPANDED I O ADDRESS ORGANIZATION OF PERIPHERAL ADDRESS DECODING TECHNIQUES sess Address Configuration Register CONTENTS 2 1 2 3 3 1 iin iene 3 1 9 1 oe ca creer a LES vade 3 2 23 4 ves 3 4 3 4 3 5 EN 3 5 JU Reg a re 3 6 Intel386 EX MICROPROCESSOR USER S MANUAL intel 4 5 2 Enabling and Disabling the Expanded I O Space 4 8 4 5 2 1 Programming REMAPCFG Example eee emen 4 8 4 6 ADDRESSING MODES esee 4 9 4 6 1 DOS compatible Mode eese enne 459 4 6 2 Nonintrusive DOS Mode seem eene rennen enne 4 11 4 6 3 Enhanced DOS Mode eese nnne 4 11 4 6 4 Non DOS Mode ecrit eerte 4 11 4 7 PERIPHERAL REGISTER ADDRESSES eene mener 4 15 CHAPTER 5 DEVICE CONFIGURATION 5 1 INTRODUCTION i recs 5 2 PERIPHERAL CONFIGURATION Vis hh diane ibe o PP ier Ae cera 5 3 5 2 1 DMA Controller Bus Arbiter and Refresh Unit
207. 7 0 X 0 2 BLE 0 X 1 7 CAS2 0 1 1 1 7 CLKOUT 0 54 0 WH Q X 1 56 5 1 X 1 D15 0 y o 7 7 7 7 DACK1 0 X 1 D C 1 0 0 7 DTR1 0 WH X X X VOD WH Z Z Z HLDA WL Q X 1 LBA 1 X 1 LOCK WH X X 7 0 1 1 Z P1 5 0 yo WH X X X P1 7 6 yo WL X X X P2 4 0 yo WH X X X P2 6 5 yo WL X X X P2 7 yo WH X X X P3 7 0 yo WL X X X PWRDWN WL X 1 Q RD 1 1 1 1 READY yo Z Z Z Z REFRESH 1 X 1 RTS1 WL X X X RTSO WH X X X SMIACT 1 X X 1 SRXCLK y o WH Q X or Q 1 Q SSIOTX WL Q X or Q 1 Q NOTES 1 Xifclock source is internal Q if clock source is external 2 Qwhen shifting data out through the JTAG port otherwise Z Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Table A 4 Pin States After Reset and During Idle Powerdown and Hold Sheet 2 of 2 STXCLK y o WH Q X or Q Q TDO Z or 0 2 Z or Q2 Z or 0 2 Z or 0 2 TMROUT2 O WH Q X or Q 1 Q TMROUT1 0 WL Q X or Q Q TXD1 1 X or Q0 Q TXDO WL Q X or Q 1 Q UCS 0 X 1 WDTOUT O 0 Q X Q W R O 0 1 1 2 WR O 1 1 1 1 NOTES 1 Xifclock source is internal Q if clock source is external 2 Qwhen shifting data out through the JTAG port otherwise Z The following input pins have permanent weak pull up resistors TCK TDI TMS TRST SMI PEREQ TMRCLK2 and FLT intel B COMPATIBILITY WITH THE
208. 7 01 Figure 9 19 Cascading External 82C59A Interrupt Controllers 9 31 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 9 5 PROGRAMMING CONSIDERATIONS Consider the following when programming the ICU When an 82C59A receives an interrupt request it sets the request s pending bit regardless of whether the IR signal is masked or not The pending bit remains set until the interrupt is serviced When the LS bit in ICWI is set to edge triggered during initialization all the interrupt pending bits will be cleared In special fully nested mode care must be taken when processing interrupt requests from the master s internal cascade signal IR2 At the end of the slave s interrupt service routine first issue a nonspecific EOI to the slave Before issuing a nonspecific EOI command to the master make sure that the slave has no other in service bits set Systems that use polling as the only method of device servicing must still fully initialize the 82C59A modules Also the interrupt requests to the core must be disabled using the mask bits or the CLI instruction The 8259A must be initialized before it can be used After reset the 82C594 register states are undefined The 82C59A modules must be initialized before the IF flag in the core FLAG register is set peripherals that use interrupts connected to the ICU must be initialized before initializing the ICU 9 5 1 Interrupt Control Unit Code Examples The exampl
209. 7 um or r Fui gisplacement 00001111 10001011 Full displacement d GNE IA T JL JNGE jump on less not greater or equal 8 bit displacement 0111 00 8 bit displacement 7 or 7 i or r Vul cisplacement 00001111 10001100 Full displacement AEMONA Eris JNL JGE jump on not less greater or equal 8 bit displacement 0111 01 8 bit displacement 7 es or 7 tm or r E 13 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Table E 1 Instruction Set Summary Sheet 13 of 19 Clock Count Notes Real Pro Real Pro Ad tected Ad tected Instruction Format dress Virtual dress Virtual Mode Ad Mode Ad or dress or dress Virtual Mode Virtual Mode 8086 8086 Mode Mode Pull displacement 00001111 10001101 Full displacement j JLE JNG jump on less or equal not greater 8 bit displacement 0111 8 bit displacement 7 E or 7 p or r displacement 0000 10001110 Full displacement JNLE JG jump on not less equal greater 8 bit displacement 0111 8 bit displacemen 7 zm or 7 pu or r displacement 0000 10001111 Fulldisplacement PN e ETAT JCXZ jump on CX zero 110001 8 bit displacemen 7 OF 29 d d JECXZ jump on ECX n 9 mor 9 mor r Zero 11000 8 bit displacemen 5 5 Address size prefix differentiates JCXZ from JECXZ LOOP loop CX times 1100010 8 bit displacemen 11 11
210. 72520 Intel386 EX Microprocessor Pin Multiplexing Map 272587 Packaging 240800 You may also want to refer to Standard 1149 1 1990 IEEE Standard Test Access Port and Boundary Scan Architecture and its supplement Standard 1149 1a 1993 1 5 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 1 5 ELECTRONIC SUPPORT SYSTEMS Intel s FaxBack service and application BBS provide up to date technical information Intel also maintains several forums on CompuServe and offers a variety of information on the World Wide Web These systems are available 24 hours a day 7 days a week providing technical information whenever you need it 1 5 1 FaxBack Service FaxBack is an on demand publishing system that sends documents to your fax machine You can get product announcements change notifications product literature device characteristics de sign recommendations and quality and reliability information from FaxBack 24 hours a day 7 days a week 1 800 525 3019 US or Canada 44 1793 432509 Europe 65 256 5350 Singapore 852 2 844 4448 Hong Kong 886 2 5 14 0815 Taiwan 822 767 2594 Korea 61 2 975 3922 Australia 1 503 264 6835 Worldwide Think of the FaxBack service as a library of technical documents that you can access with your phone Just dial the telephone number and respond to the system prompts After you select a doc ument the system sends a copy to your fax machine Each document has an order number
211. 8 01 100 SS ESP scaled index d8 01 101 SS EBP scaled index d8 01 110 DS ESI scaled index d8 01 111 DS EDI scaled index d8 10 000 DS EAX scaled index d32 10 001 DS ECX scaled index d32 10 010 DS EDX scaled index d32 10 O11 DS EBX scaled index d32 10 100 SS ESP scaled index d32 10 101 SS EBP scaled index d32 10 110 DS ESI scaled index d32 10 111 DS EDI scaled index d32 NOTE Mod field in mod byte ss index base fields in s i b byte ss Scale Factor 00 x1 01 x2 10 x4 11 x8 Index Index Register 000 EAX 001 ECX 010 EDX 011 EBX 100 no index regt 101 EBP 110 ESI 111 EDI When index field is 100 indicating index register the ss field must equal 00 If this is not true the effective address is undefined E 29 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel E 2 2 5 Encoding of Operation Direction d Field In many two operand instructions the d field is present to indicate which operand is considered the source and which is the destination Table E 10 Encoding of Operation Direction d Field d Direction of Operation 0 Register Memory Register reg field indicates source operand mod r m or mod ss index base indicates destination operand 1 Register lt Register Memory reg field indicates destination operand mod
212. 8 signal active at the end of the last T2 when READY is sampled active the processor waits for the current bus to complete and then executes another write cycle with the upper eight bits of the data bus D15 8 copied to the lower eight bits of the data bus D7 0 The processor deactivates BLE on the second cycle BLE is used as address to an 8 bit device this translates to AO 0 for the first cycle and AO 1 for the second 6 3 7 2 Read Cycles Ifthe current bus cycle is a byte read with BHE active and BLE inactive and the processor samples the BS8 signal active at the end of the last T2 when READY is sampled active the processor latches the data on the lower eight bits of the data bus D7 0 and internally routes this data to the upper data bus of the core Ifthe current bus cycle is a byte read with BHE inactive and BLE active the processor ignores the state of the BS8 signal Ifthe current bus cycle is a word read with both BHE and BLE active and the processor samples the BS8 signal active at the end of the last T2 when READY is sampled active the processor waits for the current bus cycle to complete and latches the data on the lower eight bits of the data bus D7 0 It then executes another read cycle with BLE inactive BLE is used as address 0 to an 8 bit device this translates to AO 0 for the first cycle and 0 1 for the second latching the data on the lower eight bits of the data bus 07 0 again a
213. 8 4 1 Reset Consideration S ms rre D ero er et vd Peu ee et 8 11 8 4 2 Power up Considerations iei rd etti eut de e ae eat ie Date rte 8 12 8 4 2 1 B ilt in Self Gest 2 8 4 2 2 RESET m 8 12 8 4 3 Powerdown Mode and Idle Mode Considerations 8 13 8 5 PROGRAMMING CONSIDERATIONS EE mE 8 5 1 Clock and Power Management Unit Code Examples 8 13 CHAPTER 9 INTERRUPT CONTROL UNIT 9 1 OVERVIEW coi ttu ERE DR e E 9 1 9 2 1 Interrupt iier ERR UIN ODER te qi deiude atu eet 9 4 9 2 2 Interrupt Priority 6 9 2 2 1 Assigning an Interrupt Level ITE EN 9 6 9 2 2 2 Determining nennen nennen nns 9 7 9 2 3 Interrupt VectOrS ed ote E OU REOR IRE 9 8 9 2 4 Interrupt ProCe SS Ed 9 9 9 2 5 uite le REPRE e cheats 9 14 9 3 REGISTER DEFINITIONS ERR qe 9 15 9 3 1 Port Configuration Register PSCFG essen 9 18 9 3 2 Interrupt Configuration Register INTCFG 9 19 vi intel CONTENTS 9 3 3 Initialization Command Word 1 9 20 9 3 4 Initialization Command Word 2 9 21 9 3 5 Initialization Command Word 3 ICWS3 9 22 9 3 6 Initialization Command W
214. 80 0 Initialize 5100 pins DRAM and SRAM Chip Selects Interrupt Signals and TimerOut Signals to be in peripheral mode Init IOPorts DCDO RTSO DTRO DSRO RIO Real Protected Mode CS2 CS4 RXDO TXDO CTSO TMROUTO TMROUT1 INTO INT1 INT2 INT3 PWRDWN COMCLK Px_OUT Px_OUT Px_OUT Oxff This example shows all output pins being initially 1 Oxff Note Input pins must be given an initial Oxff value of 1 whereas peripheral pins initially can be set or cleared No changes required ck ck ck ck ck ck ck ck ck ce eee ccce Sk Sk Sk kk Sk Sk Sk Sk Sk Sk Sk Sk kk Sk Sk Sk Sk Sk Sk Sk Sk Sk Sk Sk Sk kk kk kk Sk S S S S Sk S S S S amp S amp S amp S amp M amp M amp M X extern void Init IOPorts BYTE Portl BYTE Port2 BYTE Port3 BYTE PortDirl 16 12 BYTE PortDir2 BYTE PortDir3 BYTE PortLtcl BYTE PortLtc2 BYTE PortLtc3 intel INPUT OUTPUT PORTS Select pin values SetEXRegByte PlLTC PortLtcl SetEXRegByte P2LTC PortLtc2 SetEXRegByte P3LTC PortLtc3 Select pin directions _SetEXRegByte P1DIR PortDirl SetEXRegByte P2DIR PortDir2 SetEXRegByte P3DIR PortDir3 Turn off weak resistors and select either I O or peripheral mode _SetEXRegByte P1CFG Port1 SetEXRegByte P2CFG Port2 SetEXRegByte P3CFG Port3 Init IOPorts 16 13 intel 17 WATCHDOG TIMER UNIT 17 WATCHDOG TIMER UNIT The watchdog timer
215. 9 Clock Count Notes Real Pro Real Pro Ad tected Ad tected Virtual dress Virtual Instruction Format dress Mode Ad Mode Ad or dress or dress Virtual Mode Virtual Mode 8086 8086 Mode Mode table register 00001111 00000001 mod00 1 r m b h SLDT store local descriptor table to register memory 00001111 00000000 mod 00 0 r m N A 2 2 a h SMSW store machine 2 2 2 2 b c hil Staus word 00001111 00000001 mod 100 r m STR store task register to register memory 00001111 00000000 mod00 1 r m N A 2 2 a h VERR verify read access register memory 00001111 00000000 mod 10 0 r m N A 10 11 a 9 h j p VERW verify write 00001111 00000000 mod 10 1 r m N A 15 16 a g h j p access NOTES Notes a through c apply to Real Address Mode only a This is a Protected Mode instruction Attempted execution in Real Mode will result in exception 6 invalid opcode b Exception 13 fault general protection will occur in Real Mode if an operand reference is made that partially or fully extends beyond the maximum CS DS ES FS or GS limit FFFFH Exception 12 fault stack segment limit violation or not present will occur in Real Mode if an operand reference is made that partially or fully extends beyond the maximum SS limit This instruction may be executed Real Mode its purpose is primarily to initialize the CPU for Protected Mode Notes d
216. 9 1 The core initiates interrupt acknowledge cycles for the internal 82C59As External logic must decode the bus signals M IO D C W R and REFRESH see Table 6 2 on page 6 5 to generate external interrupt acknowledge signals Since the cascade bus determines which 82C59A is being acknowledged each external slave must monitor the master s cascade signals to determine whether it is the acknowledged slave For external slaves the mas ter s cascade signals CAS2 0 can be driven using bit 7 of the INTCFG register onto the A18 16 address pins NOTE Since external 82C59As require the CAS2 0 signals to stay valid through the idle states that occur between the two interrupt acknowledge cycles and since the processor drives these lines high during these idle states the CAS2 0 lines must be latched externally to ensure validity during the idle states 9 2 INTERRUPT CONTROL UNIT IRO OUTO TCU 8259A Master IR1 IR2 P3CFG 2 Vss PAN INTCFG IR3 INTCFG 5 ZX LBs P3CFG 3 Vss P3CFG 4 P3CFG 5 INTCFG O INTCFG 1 SSIOINT OUT1 TCU OUT2 TCU INTCFG 4 ae INTCFG 3 INTCFG 2 Vss IR7 F WDTOUT 3 Vss Alternate pin signals are in parentheses Heavier lines indicate multiple signals SIOINTO d 4 2 INTO To From I O Port lt gt P3 2 MCR1 3 SIOINT1 SIOINT1 ie NTCFG 6 P3CFG 1 _ INTS v totu TMROUT1 OUT1 TCU 0 P34 P3 1 MCRO 3 SIOINTO 1
217. A1REQ3 F013H read write DMAOTARO F000H 0000H Channel 0 and 1 Target Address DMAOTAR1 FOOOH 0000H Contains channel n s 26 bit target address During a DMAOTAR2 F087H 0087H buffer transfer this address may be incremented FO86H decremented or left unchanged Reading these registers returns the current address DMA1TARO F002H 0002H DMA1TAR1 F002H 0002H DMA1TAR2 F083H 0083H DMA1TAR3 F085H read write DMAOBYCO F001H 0001H Channel 0 and 1 Byte Count DMAOBYC1 FOO1H 0001H Contains channel 5 24 bit byte count During a DMAOBYC2 F098H v buffer transfer this byte count is decremented Reading these registers returns the current byte DMA1BYCO F003H 0003H count DMA1BYC1 F003H 0003H DMA1BYC2 F099H read write 12 28 intel DMA CONTROLLER Table 12 3 DMA Registers Sheet 2 of 3 Register Expanded Address PC AT Address Description DMASTS read only F008H 0008H DMA Status Indicates whether a hardware request is pending on channel 0 and 1 Indicates whether channel 0 s or channel 1 s byte count has expired DMACMD2 write only F01AH DMA Command 2 Assigns a bus control requester DMA channel 0 DMA channel 1 or external bus master to the lowest priority level Selects the type of sampling for the end of process and the request DRQn inputs The DMA can sample these signals asynchronously or synchronously DMAM
218. AAA A AAA InitRCU Description Initializes the Refresh Control Unit 15 14 intel REFRESH CONTROL UNIT Parameters Counter Value Value of the refresh interval Returns Error Codes E BADVECTOR User input an invalid parameter E OK Executed correctly Assumptions None Syntax define REFRESH INTERVAL 0x186 Counter value for DRAM with 1024 rows and a refresh period of 16 msec 25 MHz Processor Clock int error code error code InitRCU REFRESH INTERVAL Real Protected Mode No changes required k k k k k k k k k Kk k k k k k k k k k extern int InitRCU WORD Counter_Value Check that Counter_Value is 10 bits in length if Counter_Value Counter_Value amp 0x03ff return E_BADVECTOR Clear lower 10 bits of RFSCIR _SetEXRegWord RFSCIR Oxfc00 Set lower 10 bits of RFSCIR to Counter_Value _SetEXRegWord RFSCIR _GetEXRegWord RFSCIR Counter Value Enable Refresh Unit _SetEXRegWord RFSCON _GetEXRegWord RFSCON 0x8000 return E_OK InitRCU IK I RR KA IRR Kk A AR IRR Kk Ck IIR kk k kk ko k k k ke ko ke k k ek Get RCUCounterValue Description This function returns the current value of the refresh interval timer 15 15 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Parameters None Returns Refresh Interval Counter Value Assumptions NONE Syntax WORD CounterValue CounterValue
219. AP Controller Finite State Machine Instruction Register IR Identification Code Register IDCODE Internal and External Timing for Loading the Instruction Register Internal and External Timing for Loading a Data Register Derivation of AEN Signal in a Typical PC AT System Derivation of AEN Signal for Intel386 M EX processor based Systems General Instruction Format CONTENTS xxi Intel386 EX MICROPROCESSOR USER S MANUAL intel TABLES Table Page 2 1 PC compatible Peripherals Ooo 2 2 Embedded Application specific Peripherals ERE 2 4 4 1 Peripheral Register I O Address Map in Slot 15 4 5 4 2 Peripheral Register 0 4 15 5 1 Master s IR3 5 8 5 2 Master s IR4 Connections inns recette ree re enti genta 5 8 5 3 Signal Pairs on Pins without a 5 23 5 4 Example Pin Configuration 5 30 5 5 Example DMACFG Configuration Register eee 5 31 5 6 Example TMRCFG Configuration 5 32 5 7 Example INTCFG Configuration 5 33 5 8 Example SIOCFG Configuration Register seen 5 33 5 9 Pin Configuration Register Design Woksheet sse 5 34 5 10 DMACFG Register Design 5 35 5
220. Address Configuration Register 4 7 4 4 Setting the ESE Bit Code Example 2 4 0 4 5 DOS Compatible 4 10 4 6 Example of Nonintrusive ok d Modena aina eere 412 4 7 Enhanced DOS Mode eese eene menm 419 4 8 NonDOS Mode 5 E EE 5 1 Peripheral and Pin Connections es One 5 2 Configuration of DMA Bus Arbiter Refresh Unit S 5 3 DMA Configuration Register DMACEFG essen 5 6 5 4 Interrupt Control Unit emen 5 9 5 5 Interrupt Configuration Register 5 10 5 6 Timer Counter Unit 5 12 5 7 Timer Configuration Register cu e UE 5 8 Serial I O Unit 0 Configuration 5 9 Serial I O Unit 1 Configuration is DTG 5 10 SIO SSIO Configuration Register SIOCFG nih etes eei as rete 5 17 5 11 SSIO Unit emm ener nens 5 18 5 12 Configuration of Chip select Unit and Clock and Power Management Unit 5 20 5 13 Core Configuration esses enne eene nennen enne nennen nennen 5 21 5 14 Port 92 Configuration Register 92 2 eme 5 22 5 15 Pin Configuration Register PINCFQG esses emen 5 24 5 16 Port 1 Configuration Register
221. Addressing modes can include a displacement immediately following the mod r m byte or scaled index byte If a displacement is present the possible sizes are 8 16 or 32 bits If the instruction specifies an immediate operand the immediate operand follows any displace ment bytes The immediate operand if specified is always the last field of the instruction Figure E 1 illustrates several of the fields that can appear in an instruction such as the mod field and the r m field but the figure does not show all fields Several smaller fields also appear in cer tain instructions sometimes within the opcode bytes themselves Table E 2 is a complete list of all fields appearing in the instruction set Following Table E 2 are detailed tables for each field TTTTTTTT TTTTTTTT modT T T ss index base 16 8 none data32 16 8 none 7 07 0765320 765320 opcode address immediate one or two bytes displacement data T represents an opcode bit 4 2 1 bytes 4 2 1 bytes or none or none register and address mode specifier Figure E 1 General Instruction Format E 22 intel INSTRUCTION SET SUMMARY Table E 2 Fields Within Instructions Field Name Description cad pt w Specifies if data is byte of full size full size is either 16 or 32 bits 1 d Specifies Direction of Data Operation 1 S Specifies if an Immediate Data Field must be Sign Extended 1 reg General Register S
222. Bit If this bit is set and unmasked the CSU activates the chip select channel only while the processor is SMM and not in a hold state Otherwise the CSU activates the channel only when processor is operating in a mode other than SMM Setting the SMM mask bit in the channel s mask low register masks this bit When this bit is masked an address match activates the chip select regardless of whether the processor is in SMM or not BS16 Bus Size 16 bit 0 All bus cycles to addresses in the channel s address block are byte wide 1 Bus cycles are 16 bits unless the bus size control pin BS8 is asserted MEM Bus Cycle Type 0 Configures the channel for an I O addresses 1 Configures the channel for memory addresses RDY Bus Ready Enable 0 External READY is ignored READY generated by CSU to terminate the bus cycle 1 Requires that external READY be active to complete a bus cycle This bit must be set to extend wait states beyond the number determined by WS4 0 see Bus Cycle Length Control on page 14 11 Reserved for compatibility with future devices write zeros to these bits 4 0 WS4 0 Wait State Value WS4 0 defines the minimum number of wait states inserted into the bus cycle A zero value means no wait states D 9 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 0 5 CSnMSKH UCSMSKH Chip select read write Hig
223. CE UNIT 6 6 1 1 System Configuration The Intel387 SX Math Coprocessor can be interfaced to the Intel386 EX embedded processor as shown in Figure 6 15 CPUCLK2 RESETIN Synchronous Reset BUSY CKM PEREQ STEN ERROR READY NUMCLK2 READYO Intel386 EX Intel387 SX Embedded Processor Math Coprocessor A2852 02 Figure 6 15 Intel386 EX Processor to Intel387 SX Math Coprocessor Interface A dedicated communication protocol makes possible high speed transfer of opcodes and oper ands between the Inte1386 EX processor and Inte1387 SX math coprocessor Most control pins of the Intel387 SX Math Coprocessor are connected directly to Intel386 EX processor pins 6 39 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel The interface has these characteristics The Intel387 SX Math Coprocessor shares the local bus of the Intel386 EX processor The Intel386 EX processor and Intel387 SX Math Coprocessor share the same reset signals They also share the same clock input The corresponding BUSY t ERROR and PEREQ pins are connected together The Status Enable STEN selects the math coprocessor It causes the chip to recognize other chip select inputs STEN is tied high CKM is tied high to select the synchronous mode of operation for the coprocessor The math coprocessor NPS1 and NPS2 inputs are connected to the Intel386 EX processor M IO and A23 inputs respe
224. CFG 2 1 IR6 Vss P3CFG 4 0 IR6 Vss INTCFG 3 0 INT2 P3CFG 4 1 INT7 INTCFG 3 1 device pin device pin IR7 Vss P3CFG 5 0 IR7 WDTOUT Hardwired INT3 P3CFG 5 1 watchdog timer device pin Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Interrupt processing begins with the assertion of an IR signal During the ICU initialization pro cess described in Register Definitions on page 9 15 you can program the ICU to be either edge triggered or level triggered See Interrupt Detection on page 9 29 for a description of the difference between level and edge triggered signals 9 2 2 Interrupt Priority Each 82 59 contains eight interrupt request signals An 82C59A can receive several concurrent interrupt requests or can receive a request while the core is servicing another interrupt When ei ther condition occurs the 82C59A uses a programmable priority structure to determine the order in which to process the interrupts There are two parts to the priority structure Assigning an interrupt level to each IR signal Determining their relative priorities 9 2 2 1 Assigning an Interrupt Level By default the interrupt structure for each 82C59A is configured so that IRO has the highest level and IR7 has the lowest level Two methods shown in Figure 9 2 are available for changing this interrupt structure Specific Rotation This method assigns a specific IR signal as the lowest level The other IR signals are automatical
225. CROPROCESSOR USER S MANUAL intel SIO1 SIOCFG 1 1 P3CFG 7 COMCLK BCLKIN To F VO P P3 7 t SERCLK o From I O Port 3 0 Receive Data r RXD1 To DMA DRQ1 SIOINT1 9 ICU RBFDMA1 gt To DMA TXEDMA1 3 DMA 4 PINCFG 2 Transmit Data TXD1 SIOCFG 7 From 3 6 DACK1 4 PINCFG 3 CTS1s Clear to Send P To From DMA om EOP Request to Send XM U RTS1 From SSIO SSIOTX DsRi4 To From SSIO STXCLK In 0 01 Data Carrier y To DMA DRQO Detect 41 PINCFG 1 zZ 0 DTR14 Data Set Ready Data Terminal Ready To From SSIO SRXCLK RH amp Ring Indicator To SSIO SSIORX t Alternate pin signals are in parentheses A2519 02 Figure 11 1 Serial I O Unit 1 Configuration intel 11 1 1 SIO Signals Table 11 1 lists the SIOn signals ASYNCHRONOUS SERIAL I O UNIT Table 11 1 SIO Signals Device Pin or Signal Internal Signal Description Baud rate Internal signal SERCLK Generator Device pin This internal signal is the processor s input clock CLK2 divided by Clock Source input four COMCLK An external source connected to this pin can clock the SIOn baud rate generator TXDn Device pin Transmit Data output The transmitter uses this pin to shift serial data out Data is transmitted least significant bit first RXDn Device pin Receive Data input The receiver uses this pin to shift serial
226. CSADH intel Chip select High Address Expanded Addr F402H F40AH CSnADH 0 6 UCSADH F412H F41AH read write F422H F42AH F432H F43AH ISA Addr Reset State 0000H CSnADH FFFFH UCSADH 15 8 EI CA15 CA14 7 0 CA13 CA12 CA11 CA10 CA9 CA8 CA7 CA6 Bit Bit Number Mnemonic Runcuon 15 10 Reserved for compatibility with future devices write zeros to these bits 9 0 CA15 6 Chip select Channel Address Upper Bits Defines the upper 10 bits of the channel s 15 bit address The address bits CA15 6 and the mask bits CM15 6 form a masked address that is compared to memory address bits A25 16 or I O address bits A15 6 D 8 intel SYSTEM REGISTER QUICK REFERENCE D 4 CSnADL UCSADL Chip select Low Address CSnADL n 0 6 UCSADL read write 15 Expanded Addr F400H F408H F410H F418H F420H F428H F430H F438H ISA Addr Reset State 0000H CSnADL FF6FH UCSADL CA5 4 2 1 CASMM BS16 MEM RDY WS4 WS3 WS2 WS1 WSO Bit Number Bit Mnemonic Function 15 11 CA5 1 Chip select Address Value Lower Bits Defines the lower 5 bits of the channel s 15 bit address The address bits CA5 1 and the mask bits CM5 1 form a masked address that is compared to memory address bits A15 11 or I O address bits A5 1 10 CASMM SMM Address
227. Configuration 5 8 5 2 1 1 Using The DMA Unit with External Devices see DTO 5 2 1 2 Service to an SIO or SSIO Peripheral sse 5 3 5 2 1 3 Using The Timer To Initiate DMA Transfers 5 4 5 2 1 4 Limitations Due To Pin Signal Multiplexing 2 5 4 5 2 2 Interrupt Control Unit Configuration 5 7 5 2 3 Timer counter Unit Configuration 2 5 11 5 2 4 Asynchronous Serial Configuration 2 5 14 5 2 5 Synchronous Serial I O Configuration ee D718 5 2 0 Chip select Unit and Clock and Power Management Unit Configuration xanunesgD t9 5 2 7 Core Configuration 2 21 5 3 PIN CONFIGURATIQN 2 Cod a c eg eco Ed REEL eh e Ra De ens 5 23 5 4 DEVICE CONFIGURATION PROCEDURE 8 28 5 5 CONFIGURATION 5 28 5 5 1 Example Design 5 28 5 5 2 Example Design Solution nnne 5 29 CHAPTER 6 BUS INTERFACE UNIT 6 1 OVERVIEW nite Pop tiet epe eto d i ape tho eate auta e 6 1 6 1 1 Bus Signal Descriptions 2 eem eee D 6 2 1 Bus States nae bentes DAS 6 2 2 Pipelining 52452 ien t5 6 2 3 Data Bus Transfers and Operand Alignment 6 9 6 2 4 Ready MEI 6 10 6 3 1 Read Cycle e
228. D2 3 1 Causes the requester s address for the channel specified by bit 0 to remain constant during a buffer transfer 3 RI Requester Address Increment Decrement 0 Causes the requester address to be incremented after each data transfer in a buffer transfer 1 Causes the requester address for the channel specified by bit 0 to be decremented after each data transfer in a buffer transfer Note that it does not decrement words When decrementing it will do two byte transfers for a word Note When the target address is programmed to remain constant DMAMOD2 4 1 this bit is a don t care 2 TH Target Address Hold 0 Causes the address to be modified incremented or decremented depending on DMAMOD1 5 1 Causes the target s address for the channel specified by bit 0 to remain constant during a buffer transfer 1 0 Must be 0 for correct operation 0 CS Channel Select 0 The selections for bits 7 2 affect channel 0 1 The selections for bits 7 2 affect channel 1 Figure 12 26 Mode 2 Register DMAMOD2 12 41 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 12 3 10 Software Request Register DMASRR Write DMASRR to issue software DMA service requests Software requests are subject to bus control priority arbitration with all other software and hardware requests A software request ac tivates the internal channel request signal This signal remains
229. DMA transfer in asynchronous mode DREQn must be sampled inactive one CLKOUT before READY In synchronous mode it must be sampled inactive at the same time as READY When DREQn is sampled active in either of the above cases another DMA cycle is executed depending on operating mode CLKOUT DRQn ADS EOP As an output READY DMA Cycle xCycle A2483 02 Figure 12 6 Buffer Transfer Ended by an Expired Byte Count CLKOUT ADS READY EOP Async EOP Sync Cycle 2482 02 Figure 12 7 Buffer Transfer Ended by the Input 12 11 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 12 2 6 Buffer transfer Modes After a buffer transfer is completed or terminated a channel can either become idle require re programming or reprogram itself and begin another buffer transfer after it is initiated by a hard ware or software request The DMA s three buffer transfer modes single autoinitialize and chaining determine whether a channel becomes idle or is reprogrammed after it completes or ter minates a buffer transfer 12 2 6 1 Single Buffer Transfer Mode By default single buffer transfer mode the DMA transfers a channel s buffer only once When the entire buffer of data has been transferred the channel becomes idle and must be repro grammed before it can perform another buffer transfer The single buffer transfer mode is useful when you
230. DMAITARO 1 addrDMATar2 nChannel DMA 10 DMAOTAR2 DMA1TAR2 addrDMATar3 nChannel DMA 10 DMAOTAR3 DMA1TAR3 If in tiny small or medium model dif defined M I86TM defined M I86SM defined M I86MM _asm then grab our segment from DS mov ax ds mov wSegment ds wOffset WORD ptMemory and our offset from the pointer 12 55 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel else Else in compact large or huge memory model wSegment SEG ptMemory grab the segment from the pointer wOffset OFF ptMemory and the offset from the pointer endif Assuming real mode compute our physical address lAddress DWORD wSegment lt lt 4 wOffset _SetEXRegByte DMACLRBP 0 0 Clear the byte pointer flip flop Write target address bits 0 7 SetEXRegByte addrDMATarO 1 BYTE lAddress amp OxFF Write target address bits 8 15 SetEXRegByte addrDMATarO0 1 BYTE lAddress gt gt 8 amp OxFF Write target address bits 16 23 SetEXRegByte addrDMATar2 BYTE lAddress 16 amp OxFF Write target address bits 24 25 SetEXRegByte addrDMATar3 BYTE lAddress 24 amp 0x03 return ERR NONE Kk Ck CK Ck KC Kk Ck Ck Kk K Kk kk kk Kk k KK Ck KC A IIR kk ke kk k k kk k k k k SetDMAXferCount Description Sets the
231. DMAO connected to DREQO 010 SIO channel 1 s transmit buffer empty signal TXEDMA1 connected to DREQO 011 SSIO transmit holding buffer empty signal THBE connected to DREQO 100 TCU counter 1 s output signal OUT1 connected to DREQO 101 SIO channel 1 s receive buffer full signal RBFDMA1 connected to DREQO 110 SIO channel 0 s transmit buffer empty signal connected to DREQO 111 SSIO receive holding buffer full signal RHBF connected to DREQO Table 5 5 Example DMACFG Configuration Register 5 31 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Bit 4 TMRCFG Value 7 0 All clock inputs enabled 0 1 CLK2 CLK1 CLKO forced to 0 6 0 Connects GATEn to either the Vcc pin or the TMRGATEn pin 0 1 Turns GATEn on or off depending on whether bits 1 3 and 5 are set or clear 5 0 With bit 6 clear Vcc to GATE2 with bit 6 set GATE2 off 0 1 With bit 6 clear TMRGATE2 pin conn to GATE2 with bit 6 set GATE2 on 4 0 PSCLK connected to CLK2 0 1 TMRCLK2 connected to CLK2 3 0 With bit 6 clear Vcc to GATE1 with bit 6 set GATE1 turned off 0 1 With bit 6 clear TMRGATE 1 pin conn to GATE1 with bit 6 set GATE1 on 2 0 PSCLK connected to CLK1 0 1 TMRCLK1 connected to CLK1 1 0 With bit 6 clear Vcc to GATEO with bit 6 set GATEO turned off 0 1 With bit 6 clear TMRGATEO pin conn to GATEO w
232. ELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells in preparation for another boundary scan test operation You load the SAMPLE PRELOAD instruction by manipulating TDI to supply the binary opcode 0001 The Shift DR state places the boundary scan register in the serial path between TDI and TDO the Capture DR state loads the pin states into the boundary scan register and the Update DR state loads the shift register contents into the boundary scan register s parallel outputs 18 3 4 Testing the Interconnections EXTEST The EXTEST instruction allows testing of off chip circuitry and board level interconnections Boundary scan cells at the system outputs are used to apply test stimuli while cells at system in puts capture the results The Capture DR state captures input pins into the chain the Update DR state drives the new values of the parallel output onto the output pins 18 10 intel JTAG TEST LOGIC UNIT Typically you would use the SAMPLE PRELOAD instruction to load data onto the boundary scan register s latched parallel outputs before loading the EXTEST instruction You load the EX TEST instruction by manipulating TDI to supply the binary opcode 0000 The Update DR state drives the preloaded data onto the pins for the first test Stimuli for the remaining tests are shifted in while the results for the completed tests are shifted out 18 3 5 Disabling the Output Drivers The
233. ER S MANUAL intel FFFFH 8259A 2 8259A 1 On chip DMA F000H Expanded I O Space DOS I O Space A2502 02 Figure 4 8 NonDOS Mode intel SYSTEM REGISTER ORGANIZATION 47 PERIPHERAL REGISTER ADDRESSES Table 4 2 lists the addresses and names of all user accessible peripheral registers I O Registers can be accessed as bytes or words Word accesses to byte registers result in two sequential 8 bit T O transfers The default reset value of each register is shown in the Reset Value column An X in this column signifies that the register bits are undefined Some address values do not access registers but are decoded to provide a logic control signal These addresses are listed as Not a register in the Reset column Table 4 2 Peripheral Register Addresses Sheet 1 of 6 ai Register Reset Value DMA Controller and Bus Arbiter FOOOH 0000H Byte DMAOTARO Note 1 XX F001H 0001H Byte DMAOBYCO Note 1 XX F002H 0002H Byte DMA1TARO 1 Note 1 XX F003H 0003H Byte DMA1BYCO Note 1 XX F004H 0004H Reserved F005H 0005H Reserved FOO6H 0006H Reserved F007H 0007H Reserved F008H 0008H Byte DMACMD1 DMASTS 00H F009H 0009H Byte DMASRR 00H FOOAH 000AH Byte DMAMSK 04H FOOBH 000BH Byte DMAMOD 1 00H FOOCH 000CH Byte DMACLRBP Not a register FOODH 000DH Byte DMACLR Not a register FOOEH 000EH Byte DMACLRMSK Not a register
234. ERVIEW The Intel386 EX processor s external bus is controlled by the bus interface unit BIU To com municate with memory and I O the external bus consists of a data bus a separate address bus seven bus status pins two data status pins and three control pins Bidirectional data bus D15 0 can transfer 8 or 16 bits of data per cycle e Address bus includes the address pins A25 1 a high byte enable pin BHE and a low byte enable pin BLE Address pins select a word in memory and byte enable pins select the byte within the word to access Bus status pins include ADStt indicates the start of a bus cycle and valid address bus outputs WIRtt identifies the bus cycle as a write or a read M IO identifies the bus cycle as a memory or I O access D C identifies the bus cycle as a data or control cycle LOCK identifies a locked bus cycle LBA indicates that the processor generates an internal READY7 for the current bus cycle REFRESH identifies a refresh bus cycle 6 1 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Data status pins indicate that data is available on the data bus for a write or that the processor is ready to accept data for a read RD These pins are available so that certain system configurations can easily connect the processor directly to memory or I O without external logic Buscontrol pins allow external logic to control the bus cycl
235. EVICE CONFIGURATION intel 5 3 PIN CONFIGURATION Most of the microprocessor s package pins support two peripheral functions Some of these pins are routed to two peripheral inputs without the use of a multiplexer These input signal pairs are listed in Table 5 3 The pin is connected to both peripheral inputs The remaining pins supporting two signals have multiplexers For each such pin a bit in a pin configuration register enables one of the signals Table 5 9 lists the bits in each of the four pin configuration registers These abbreviated register tables are discussed in Configuration Exam ple on page 5 28 When configuring ports to use INT8 or INTO first set the appropriate INTCFG bit then the P3CFG bit Setting the bits in this order avoids any potential contention on INT8 or INTO Table 5 3 Signal Pairs on Pins without a Multiplexer Names Signal Descriptions DRQO DMA External Request 0 indicates that an off chip peripheral requires DMA service iiid Data Carrier Detect SIO1 indicates that the modem or data set has detected the asynchronous serial channel s data carrier DRQ1 DMA External Request indicates that an off chip peripheral requires DMA service RADI Receive Data SIO1 accepts serial data from the modem or data set to the asynchronous serial channel SIO1 DSR1 Data Set Ready SIO1 indicates that the modem or data set is ready to establish a STXCLK communicati
236. EX EMBEDDED MICROPROCESSOR USER S MANUAL intel change the reload value write the new values to WDTRLDH and WDTRLDL registers as described in steps 1 and 2 above To disable or enable bus monitor mode write to the bus monitor bit BUSMON 0 disabled enabled 17 3 DISABLING THE WDT If your system has no need for the WDT when the unit is in bus monitor or general purpose timer mode you can disable the unit by setting the CLKDIS bit in the WDTSTATUS register Figure 17 3 which stops the clock to the WDT In this configuration the WDT consumes minimal pow er but you can re enable the unit at any time Ifthe WDT is in watchdog mode you cannot write to the WDTSTATUS register to stop the clock and therefore cannot disable the unit 17 6 intel WATCHDOG TIMER UNIT 17 4 REGISTER DEFINITIONS This section describes the registers associated with the WDT and explains how these registers can be used to enable and use each WDT mode Table 17 2 describes the registers associated with the WDT Table 17 2 WDT Registers Register Address Description WDTCLR OF4C8H Watchdog Timer Clear Write the lockout sequence to this location Circuitry at this address decodes the lockout sequence to enable watchdog mode reload the counter or both This location is used only for watchdog mode WDTCNTH WDTCNTL read only OF4C4H OF4C6H WDT Counter These registers hold the current v
237. EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Description Is an interrupt driven serial port write function The NUL character N0 is used to indicate end of string Parameters Unit Unit number of the serial port 0 for SIO port 0 1 for SIO port 1 str Address of a zero terminated string to be transmitted Returns None Assumptions REMAPCFG register has Expanded I O space access enabled ESE bit set The processor Port pin are initialized separately Syntax define SIO 0 0 SerialWriteStr Int SIO 0 HelloString Real Protected Mode No changes required K RR AR RRR IRR Ck Kk k k k k k k k k k k k k k k k k void SerialWriteStr Int int Unit const char far str BYTE PortIntEnable PortIntEnable Unit IER1 IERO strcpy trans buffer str Copy string into buffer Enable TBE interrupts SetEXRegByte IERO 0x02 SerialWriteStr Int RRR KK KKK IKK IK I Ck RC A A ARR Kk kk Kk k CK Ck KC Kk kk Kk kk ke kk kk k k ko ke k k k eek Service TBE Description Service routine for TBE generated interrupts This function is used for Interrupt Driven Serial Transmits Parameters 11 44 intel ASYNCHRONOUS SERIAL UNIT None Assumptions None Syntax Not called by user Real Protected Mode No changes required Fe RRR AA IRR A ARR Ck CkCk Kk ARR IRR A ARR IRR IA void Service_TBE void if trans buffer Tbuffer index 509
238. Figure 16 3 Port n Configuration Register PnCFG 16 7 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Port Direction Expanded Addr F864H F86CH F874H PnDIR n 1 3 ISA Addr read write Reset State FFH 7 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PDO Bit Bit Number Mnemonic Function 7 0 PD7 0 Pin Direction 0 Configures the pin as a complementary output 1 Configures the pin as an open drain output or high impedance input Figure 16 4 Port Direction Register PnDIR Port Data Latch Expanded Addr F862H F86AH F872H PnLTC n 1 3 ISA Addr read write Reset State FFH 7 0 PL7 PL6 PL5 PL4 PL3 PL2 PL1 PLO Bit Bit Number Mnemonic Function 7 0 PL7 0 Port Data Latch Writing a value to a PL bit causes that value to be driven onto the corresponding pin For a complementary output write the desired pin value to its PL bit This value is strongly driven onto the pin For an open drain output a one results in a high impedance input state atthe pin For a high impedance input write a one to the corresponding PL bit A one results in a high impedance state at the pin allowing external hardware to drive it Figure 16 5 Port Data Latch Register PnLTC 16 8 intel INPUT OUTPUT PORTS Port Pin State Expanded Addr F860H F868H F870H
239. H BP 0 0 DMA1TAR3 DMA1TAR2 DMA1TAR1 DMA1TARO F085H F083H 16 F002H BP 1 8 F002H BP 0 0 DMA1BYC2 DMA1BYC1 DMA1BYCO F099H F003H BP 1 F003H BP 0 intel D 20 DMAOVFE SYSTEM REGISTER QUICK REFERENCE DMA Overflow Enable Expanded Addr F01DH DMAOVFE ISA Addr read write Reset State OAH 7 0 ROV1 TOV1 ROVO TOVO Bit Bit Number Mnemonic Function 7 4 Reserved These bits are undefined for compatibility with future devices do not modify these bits 3 ROV1 Channel 1 Requester Overflow Enable 0 lowest 16 bits of requester address increment decrement 1 all bits of requester address increment decrement 2 TOV1 Channel 1 Target amp Byte Counter Overflow Enable 0 lowest 16 bits of target address and byte count increment decrement 1 all bits of target address and byte count increment decrement 1 ROVO Channel 0 Requester Overflow Enable 0 lowest 16 bits of requester address increment decrement 1 all bits of requester address increment decrement 0 TOVO Channel 0 Target amp Byte Counter Overflow Enable 0 lowest 16 bits of target address and byte count increment decrement 1 all bits of target address and byte count increment decrement D 25 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel
240. H CS Selector 3000H DS ES FS GS SS Selectors 0000H CS Descriptor Base 00030000H DS ES FS GS SS Descriptor Base 00000000H CS DS ES FS GS SS Descriptor Limit OFFFFFH DS ES FS GS SS Attributes 16 bit CRO Bits 0 1 2 3 31 cleared DR6 Unpredictable DR7 Bits 0 10 16 31 cleared When a valid SMI is recognized on an instruction execution boundary the CPU immediately begins execution of the SMM State Save sequence asserting SMIACT low unless the CPU is in a shutdown condition The CPU then starts SMI handler execution An SMI cannot inter rupt a CPU shutdown The SMI handler always starts at 38000H When there are multiple causes of SMEs only one SMTH is generated thereby ensuring that SMI s are not nested 7 3 2 System Management Interrupt The Inte1386 EX processor extends the standard Intel386 microprocessor architecture by adding a new feature called the system management interrupt SMI This section describes in detail how the system designer uses SMI The execution unit recognizes an SME falling edge on an instruction boundary see instruction 3 in Figure 7 1 After all CPU bus cycles have completed including pipelined cycles the state 74 intel SYSTEM MANAGEMENT MODE of the CPU is saved to the SMM State Dump Area After executing a RSM instruction the CPU proceeds to the next application code instruction see instruction 4 in Figure 7 1 SMM latency is measured from the fallin
241. HIGHZ instruction places all system logic outputs into an inactive drive high impedance state This state allows an in circuit emulator to drive signals onto connections that processor out puts normally drive without risk of damaging the processor It also allows you to connect a data source such as a test chip to board level signals such as an array of memory devices that the processor outputs normally drive During normal operation the processor outputs would be ac tive while the test chip outputs would be inactive During testing you would use the HIGHZ in struction to place the processor outputs into an inactive drive state then enable the test chip to drive the connections You load the HIGHZ instruction by manipulating the TDI input to supply the binary opcode 1000 The Capture DR state loads a logic 0 into the bypass register and the Shift DR state shifts the value out 18 11 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 18 4 TIMING INFORMATION The test logic unit s input output timing is as specified in IEEE 1149 1 Figure 18 5 shows the pin timing associated with loading the instruction register and Figure 18 6 shows the timing for loading a given data register TMS Controller State josey 21501 1581 SOL uny ueos HQ 128l9S ul eandeo esneg Ul exa Hl HIX3 ul 1S9 uny n o e o D imi Para
242. ING POWER MANAGEMENT MODES Two power management modes are available idle and powerdown These modes are clock dis tribution functions controlled by the power control register PWRCON shown in Figure 8 5 Power Control Register PWRCON read write 7 Expanded Addr F800H ISA Addr Reset State 00H WDTRDY HSREADY PC1 PCO Bit Number Bit Mnemonic Function 7 4 Reserved These bits are undefined for compatibility with future devices do not modify these bits WDTRDY Watch Dog Timer Ready 0 An external READY must be generated to terminate the cycle when the WDT times out in Bus Monitor Mode 1 Internal logic generates READY to terminate the cycle when the WDT times out in Bus Monitor Mode HSREADY Halt Shutdown Ready 0 An external ready must be generated to terminate a HALT Shutdown cycle 1 Internal logic generates READY to terminate a HALT Shutdown cycle 1 0 PC1 0 Power Control Program these bits then execute a HALT instruction The device enters the programmed mode when READY internal or external terminates the halt bus cycle When these bits have equal values the HALT instruction causes a normal halt and the device remains in active mode PC1 PCO 0 active mode 0 idle mode 1 powerdown mode 1 active mode Figure 8 5 Power Control Register PWRCON intel CLOCK AND PO
243. INTCFG 5 P3GFG 0 INT9 eee 6 TMROUTO OUTO TCU 0 P3 0 P3 0 P3CFG 3 To From I O Port 3 P3 3 V q 55 P3CFG 4 Ks To From I O Port 3 P3 4 4 P3CFG 5 INT3 To From I O Port 3 0 P3 5 INT4 To TCU TMRCLKO INT5 To TCU TMRGATEO DMAINT r J INT6 To TCU TMRCLK1 1 INT7 To TCU TMRGATE1 INTCFG 7 CAS2 0 A18 16 A18 16 A2522 03 Figure 9 1 Interrupt Control Unit Configuration 9 3 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 9 2 ICU OPERATION The following sections describe the ICU operation The ICU s interrupt sources interrupt priority structure interrupt vectors interrupt processing and polling mode are discussed 9 2 1 Interrupt Sources The ICU support a total of 18 interrupt sources see Table 9 1 but only a maximum of 15 simul taneous sources Eight of these sources are internal peripherals and ten are external device pins INT9 0 However IR3 and IR4 of the master can be connected to either SIOINT1 and SIOINTO internal Asynchronous Serial I O interrupts or to external device pins INT8 and INT9 respec tively Similarly IR1 of the slave can be connected to either SSIOINT internal Synchronous Se rial I O interrupt or to external device pin 5 On the slave the external interrupt signal INT6 and the DMA Unit s DMAINT signal can be swapped before connecting to the slave s IRA and IR5 inputs The device pins INT3 0 are multiplexed with port pins Whe
244. IO and SSIO Configuration Register SIOCFG Use SIOCFG to select the baud rate generator clock source for the SIO channels and to have a channel s modem input signals connected internally rather than to package pins Selecting the in ternal modem signal connection option connects RTS to CTS DTR to DSR and DCD and Vcc to RI The modem signal connections for this internal option are shown in Figure 11 20 SIO and SSIO Configuration Expanded Addr F836H SIOCFG ISA Addr read write Reset State 00H 7 0 S1M SOM SSBSRC S1BSRC SOBSRC Bit Bit Number Mnemonic Function 7 S1M SIO1 Modem Signal Connections 0 Connects the SIO1 modem input signals to the package pins 1 Connects the SIO1 modem input signals internally 6 SOM SIO0 Modem Signal Connections 0 Connects the SIOO modem input signals to the package pins 1 Connects the SIOO modem input signals internally 5 3 Reserved These bits are undefined for compatibility with future devices do not modify these bits 2 SSBSRC SSIO Baud rate Generator Clock Source 0 Connects the internal PSCLK signal to the SSIO baud rate generator 1 Connects the internal SERCLK signal to the SSIO baud rate generator 1 S1BSRC SIO1 Baud rate Generator Clock Source 0 Connects the COMCLK pin to the SIO1 baud rate generator 1 Connects the internal SERCLK signal to the SIO1 baud rate generator 0 SOBSRC SI
245. IRK KKK IKK IK ARR A I KR IRR IRR IR AR IRR A IR IRR IA k k k k k k k SetUp_ReadBack Description This routine configures the Control Word for a Read Back Command After calling this function the latched status and counter values can be read from the TMRn registers Example code of how to do this for Timer2 is included after this function Parameters Cleared if Timer0 s values not to be latched Timerl Cleared if Timerl s values are not to be latched Timer2 Cleared if Timer2 s values are not to be latched GetStatus Cleared if Status Byte is not to be latched GetCount Cleared if Count Byte s is not to be latched Returns None Assumptions No assumptions have been made for this set up function However if a user were to latch only the counter value the configured R W Format would have to be known The setting of the R W format can be read from the Status Byte if this value is latched An example of this is included after the SetUp_ReadBack function Syntax define ENABLE 10 36 intel TIMER COUNTER UNIT define DISABLE 0 SetUp ReadBack DISABLE DISABLE ENABLE ENABLE ENABLE Real Protected Mode No changes required AIA IRR Kk Ck AR IRR void SetUp ReadBack BYTE Timer0 BYTE Timerl BYTE Timer2 BYTE GetStatus BYTE GetCount BYTE rb control 0 rb control 0xc0 Set TMRCON to read back command if GetStatus 0 rb control amp Oxef if GetCount
246. ITIONS Table 15 2 provides an overview of the registers associated with the RCU The following sections provide specific programming information for each register Table 15 2 RCU Registers Expanded ae Description Register Address escriptio RFSCIR 4 2 Refresh Clock Interval read write Determines the processor clock CLK2 2 count between refresh requests RFSCON OF4A4H Refresh Control read write Enables the refresh control unit Reading this register also provides the current value of the interval counter RFSBAD OF4A0H Refresh Base Address read write Contains the A25 14 address bits of the refresh address This establishes amemory region for refreshing RFSADD OF4A6H Refresh Address read write Contains the A13 1 address bits of the refresh address The 13 bit address counter generates these values 15 6 intel REFRESH CONTROL UNIT 15 4 1 Refresh Clock Interval Register RFSCIR Use RFSCIR to program the interval timer unit s 10 bit down counter The refresh counter value is a function of DRAM specifications and processor frequency as follows DRAM refresh period us x processor clock MHz counter value X where X 128 or of DRAM rows whichever is greater The DRAM refresh period is the time required to refresh all rows in the DRAM device NOTE Because the lower seven address bits come from a linear feedback shift register which generates all address
247. Initialization only the internal slave Interrupt Control Units ICU This routine only initializes the internal interrupt controller external ICUs must be initialized separately Parameters SlaveMode Mode of operation for Slave ICU SlaveBase Specifies the base interrupt vector number for the Slave interrupts For example if IR1 of the slave goes active and the SlaveBase 0x40 the processor uses interrupt vector table entry 0x41 SlavePins Defines what EX pins are available externally to the chip for the Slave Returns Error Code E OK Initialized OK No error Assumptions REMAPCFG register has Expanded I O space access enabled ESE bit set Syntax ICU Modes define ICU_SFNM 0x10 define ICU_AUTOEOI 0 2 define TRIGGER LEVEL 0x8 define TRIGGER EDGE 0x0 ICU Slave Pins define SPIN_INT4 0 1 define SPIN 5 0x2 define SPIN_INT6 0x4 define SPIN_INT7 0x8 int error_code error_code InitICUSlave ICU_TRIGGER_EDGE 0x30 SPIN_INT4 Real Protected Mode No changes required eK RR AR IRR ARR AIA IRR k k k k k k k k k k int InitICUSlave BYTE SlaveMode BYTE SlaveBase BYTE SlavePins BYTE cfg_pins Program Slave ICU 9 35 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel IRQ SlaveBase SlaveBase amp Oxf8 SetEXRegByte ICW1S 0x11 SlaveMode Set slave triggering SetEXRegByte ICW2S _IRQ_SlaveBase_ Set slave base interrupt
248. Intel386 EXTB Embedded Microprocessor Intel386 Embedded Microprocessor intel Intel386 EX Embedded Microprocessor User s Manual 1996 Order Number 272485 002 Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including in fringement of any patent or copyright for sale and use of Intel products except as provided in Intel s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcontroller products may have minor variations to this specification known as errata Other brands and names are the property of their respective owners Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained from Intel Corporation Literature Sales P O Box 7641 Mt Prospect IL 60056 7641 or call 1 800 548 4725 COPYRIGHT INTEL CORPORATION 1996 intel CHAPTER 1 GUIDE TO THIS MANUAL 1 1 1 2 1 8 1 4 1 5 1 5 1 1 5 2 1 5 3 1 5 4 1 6 1 7 MANUAL CONTENTS sees enne NOTATIONAL CONVENTIONS sese SPECIAL TERMINOLOGY wiii RELATED DOCUMENDS Redde ELECTRONIC SUPPORT
249. Interrupt Requests P3 0 TMROUTO INT8 These maskable inputs cause the processor to suspend P3 1 TMROUT1 INT7 execution of the current program and execute an interrupt TMRGATE1 INT6 acknowledge cycle TMRCLK1 INT5 TMRGATEO INT4 TMRCLKO INT3 P3 5 INT2 P3 4 INT1 P3 3 INTO P3 2 LBA Local Bus Access Indicates that the processor provides the READY signal internally to terminate a bus transaction This signal is active when the processor accesses an internal peripheral or when the chip select unit provides the READY signal for an external peripheral LOCK Bus Lock P1 5 Prevents other bus masters from gaining control of the bus Indicates whether the current bus cycle is a memory cycle or an I O cycle Next Address Requests address pipelining NMI ST Nonmaskable Interrupt Request Causes the processor to suspend execution of the current program and execute an interrupt acknowledge cycle PEREQ Processor Extension Request TMRCLK2 Indicates that the math coprocessor has data to transfer to the processor P1 7 Port 1 HLDA P1 6 General purpose bidirectional I O port HOLD P15 P LOCK P1 4 RIO P1 3 DSRO P1 2 DTRO P1 1 RTSO P1 0 DCDO A 4 intel SIGNAL DESCRIPTIONS Table A 2 Description of Signals Available at the Device Pins Sheet 4 of 6 Multiplexed With Signal Type Name and Description Alt
250. K pin as its clock source The synchronous serial I O SSIO unit can use either the SERCLK signal or the PSCLK signal The timer counters can use either the PSCLK signal or an external clock connected to the TMRCLKn7 input pin The individual peripheral chapters explain how to select the clock inputs INT Power Management From ICU IDLE PWRDN gt ToWDT NEM Async Reset Processor Clock PWRbOWN pin mux To Core PH1 PH2 To Peripherals b Peripheral Buffer To Peripherals SERCLK Divider Programmable e gt 5100 5101 gt SSIO L gt 5510 2470 02 Figure 8 1 Clock and Power Management Unit Connections 8 2 intel CLOCK AND POWER MANAGEMENT UNIT The signal from the RESET pin is also routed to the clock generation unit which synchronizes the processor clock with the falling edge of the RESET signal and provides a synchronous inter nal RESET signal to the rest of the device The RESET falling edge can occur in either PH1 or PH2 If RESET falls during PHI the clock generation circuitry inserts a PH2 so that the next phase is Figure 8 2 If it falls during PH2 the next phase is automatically PHI NOTE The RESET signal must be high for 16 CLK2 cycles to properly r
251. LLER 12 2 8 Cascade Mode Cascade mode allows an external 8237A or another DMA type device to gain bus control A cas caded device requests bus control by holding a channel s request input DRQn active Once granted bus control the cascaded device remains bus master until it relinquishes bus control by deactivating DRQn If a refresh request occurs while a cascaded device has bus control the cascaded device must deassert its request or the refresh cycle will be missed The following steps take place in response to a refresh request 1 The channel deasserts its acknowledge signal DACKn to the cascaded device At this point the cascaded device should relinquish bus control by removing DRQn 2 As soon as DRQn is removed the refresh cycle is started At this point if the cascaded device wants to regain bus control after the refresh cycle it must reassert DRQn 3 Ifthe cascaded device has reasserted DRQn when the refresh cycle is complete the channel reasserts DACKni giving bus control back to the cascaded device without bus priority arbitration The following flowchart Figure 12 17 shows this process flow 12 25 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel After initialization the DMA channel is programmed DRQn active Yes Cascaded device gains bus control DRQn ive Yes active No Cascaded device relinquishes bus control Cascade cycle complete 2337 02
252. LSRO LSR1 LSRO LSR1 Expanded Addr FAFDH F8FDH read only ISA Addr 02FDH Reset State 60H 60H 7 0 TE TBE BI FE PE OE RBF Bit Bit Function Number Mnemonic uncuo Reserved This bit is undefined Transmitter Empty The transmitter sets this bit to indicate that the transmit shift register and transmit buffer register are both empty Writing to the transmit buffer register clears this bit 5 TBE Transmit Buffer Empty The transmitter sets this bit after it transfers data from the transmit buffer to the transmit shift register Writing to the transmit buffer register clears this bit 4 BI Break Interrupt The receiver sets this bit whenever the received data input is held in the spacing logic 0 state for longer than a full word transmission time Reading the receive buffer register or the serial line status register clears this bit 3 FE Framing Error The receiver sets this bit to indicate that the received character did not have a valid stop bit Reading the receive buffer register or the serial line status register clears this bit If data frame is set for two stop bits the second stop bit is ignored 2 PE Parity Error The receiver sets this bit to indicate that the received data character did not have the correct parity Reading the receive buffer register or the serial line status register clears this bit 1 OE Overrun Error The receiver sets this bit to indicate an overrun error An overrun occurs when the receiv
253. MBEDDED MICROPROCESSOR USER S MANUAL intel WDT Counter Value High Expanded Addr F4C4H WDTCNTH ISA Addr read only Reset State 003FH 15 2 WC31 WC30 WC29 WC28 WC27 WC26 WC25 WC24 7 0 WC23 WC22 WC21 WC20 WC19 WC18 WC17 WC16 WDT Counter Value Low Expanded Addr F4C6H WDTCNTL ISA Addr read only Reset State FFFFH 15 B WC15 WC14 WC13 WC12 WC11 WC10 WC9 WC8 7 0 WC7 WC6 WC5 WC4 WC3 WC2 WC1 WCO Bit Number Bit Function Mnemonic High 15 0 WC31 16 WDT Counter Value High Word and Low Word Low 15 0 WC15 0 Read the high word of the counter value from WDTCNTH and the low word from WDTONTL Figure 17 2 WDT Counter Value Registers WDTCNTH and WDTCNTL 17 8 intel WATCHDOG TIMER UNIT WDT Status Expanded Addr FACAH WDTSTATUS ISA Addr read write Reset State 00H 7 0 WDTEN BUSMON CLKDIS Bit Bit Function Number Mnemonic 7 WDTEN Watchdog Mode Enabled This read only bit indicates whether watchdog mode is enabled Only a lockout sequence can set this bit and only a device reset can clear it 0 Watchdog mode disabled 1 Watchdog mode enabled 6 2 Reserved These bits are undefined for compatibility with future devices do not modify these bits 1 BUSMON Bus Monitor Enable 0 Disables bus monitor mode 1 Enables bus
254. MCRn register 11 29 11 30 modem control signals 11 29 11 30 MSRn 11 31 D 39 MSRnz register 11 31 register 11 18 P2CFG register 11 19 P3CFG register 11 20 PINCFG register 11 17 11 24 0 52 register 11 24 SCRn register 11 32 SIOCFG 5 17 11 21 13 18 D 57 SIOCFG register 11 21 TBRn 11 23 D 61 TBRz register 11 23 register addresses 4 19 4 20 D 5 D 6 registers 11 15 11 16 signals 11 3 Set defined 1 5 Signal descriptions 1 10 Signal names notational conventions 1 4 SIO See Serial I O unit SMM See System management mode SMM see System Management Mode 7 3 SMRAM 7 2 chip select unit support for 7 12 state dump area 7 14 Specific EOI command 9 14 SSIO See Synchronous serial I O unit Synchronous serial I O unit 13 1 13 25 configuring 5 18 design considerations 13 25 DMA service 5 3 master slave mode arrangements 13 2 13 3 intel operation 13 5 13 15 baud rate generator 13 5 13 6 receiver 13 12 13 15 transmitter 13 6 overview 13 1 13 4 programming 13 16 13 25 CLKPRS register 13 19 PINCFG 13 17 SIOCFG register 13 18 SSIOBAUD 13 20 D 58 SSIOBAUD register 13 20 SSIOCONI 13 22 D 59 SSIOCONI register 13 21 13 22 D 59 SSIOCON2 register 13 23 SSIOCTR 13 21 D 60 SSIOCTR register 13 21 SSIORBUF 13 25 D 60 SSIORBUF register 13 25 SSIOTBUF 13 24 D 61 SSIOTBUF register 13 24 register addresses 4 18 D 4 registers 13 16 signals 1
255. NUAL intel The baud rate generator contains a seven bit down counter A programmable baud rate value BV is the reload value for the counter The counter counts down from BV to zero toggles the baud rate generator output then reloads the BV and counts down again The baud rate genera tor s output is a function of BV and BCLKIN as follows BCLKIN baud rate output frequency 2BV 2 A BV of 0 gives the maximum output frequency BCLKIN 2 and a BV of 7FH 127 gives the minimum output frequency BCLKIN 256 If you know the desired baud rate output frequency you can determine BV as follows BV 1 2 x baud rate output frequency The maximum and minimum baud rate output frequencies with a 33MHz CLK2 66MHz de vice are shown in Table 13 2 Table 13 2 Maximum and Minimum Baud rate Output Frequencies Baud rate Value BV Input Frequency BCLKIN Output Frequency 0 16 5 MHz 8 25 MHz using either SERCLK or PSCLK with prescale value of 0 7FH 64 327 KHz 251 277 Hz using PSCLK with a prescale value of 1FFH 13 2 2 Transmitter The transmitter contains a 16 bit buffer and a 16 bit shift register When the transmitter is en abled the contents of the buffer are immediately transferred to the shift register The shift register shifts data out via SSIOTX Either the internal baud rate generator master mode or an input sig nal on the STXCLK pin slave mode drives the transm
256. O 111 SSIO receive holding buffer full signal SSRBF intel SYSTEM REGISTER QUICK REFERENCE D 10 DMACHR DMA Chaining Expanded Addr F019H DMACHR ISA Addr write only Reset State 00H 7 0 CE 0 CS Bit Bit Function Number Mnemonic 0 The selection for bit 2 affects channel 0 1 The selection for bit 2 affects channel 1 7 3 Reserved for compatibility with future devices write zeros to these bits 2 CE Chaining Enable 0 Disables the chaining buffer transfer mode for the channel specified 1 AM the chaining buffer transfer mode for the channel specified by bit 0 1 0 Must be 0 for correct operation 0 CS Channel Select D 15 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 0 11 DMACMD1 DMA Command 1 Expanded Addr 008 DMACMD1 ISA Addr 0008H write only Reset State 00H 7 0 PRE CE Bit Bit Number Mnemonic Function 7 5 Reserved for compatibility with future devices write zeros to these bits 4 PRE Priority Rotation Enable 0 Priority is fixed based on value in DMACMD2 1 Enables the rotation method for changing the bus control priority structure That is after the external bus master or one of the DMA channels is given bus control it is assigned to the lowest priority level
257. O space access enabled ESE bit set The processor Port pin are initialized separately Syntax define SIO_O 0 BYTE character character SerialReadChar SIO 0 Real Protected Mode No changes required Fe KR RAR IKK A IRR AIA ARR IR AA k k k k IIR k k k k k k k k BYTE SerialReadChar int Unit WORD ReceivePortAddr WORD StatusPortAddr WORD Status Set Port base based on serial port used ReceivePortAddr Unit RBR1 RBRO StatusPortAddr Unit LSR1 LSRO Status register is cleared after read so we must save it s value when read while Status GetEXRegByte StatusPortAddr amp SIO RX BUF FULL if Status amp SIO ERROR BITS Error Bit set then return NULL return 0 return GetEXRegByte ReceivePortAddr SerialReadChar BRK IKK kk Ck kk Ck kk Ck Ck kk Ck ko kk KC Kk Ck Kk Ck Kk k KK Ck Ck Kk kk Kk k k Kk Ck kk ke kk ko ke OK 11 37 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel SerialWriteChar Description Is a Polled serial port write function that waits forever or until a character has been written to the serial port Parameters Unit Unit number of the serial port 0 for SIO port 0 1 f r SIO port 1 ch Character value to be written out Returns None Assumptions REMAPCFG register has Expanded I O space access enabled ESE bit set The processor Port pin are initialized separately Syntax define SIO_O 0 char Char Ou
258. O0 Baud rate Generator Clock Source 0 Connects the COMCLK pin to the SIOO baud rate generator 1 Connects the internal SERCLK signal to the 5100 baud rate generator Figure 11 11 SIO and SSIO Configuration Register SIOCFG 11 21 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 11 3 3 Divisor Latch Registers DLLn and DLHn Use these registers to program the baud rate generator s output frequency The baud rate gener ator s output determines the transmitter and receiver bit times Divisor Latch Low DLLO DLL1 DLLO DLL1 Expanded Addr F4F8H F8F8H read write ISA Addr O3F8H 02 8 Reset State 02H 02H 7 0 LD7 LD6 LD5 LD4 103 LD2 LD1 LDO Divisor Latch High DLHO DLH1 DLHO DLH1 Expanded Addr F4F9H F8F9H read write ISA Addr 03F9H 02F9H Reset State 00H 00H 7 0 UD15 UD14 UD13 UD12 UD11 UD10 UD9 UD8 Bit Bit Number Mnemonic Function DLLn LD7 0 Lower 8 Divisor and Upper 8 Divisor Bits 7 0 Write the lower 8 divisor bits to DLLn and the upper 8 divisor bits to DLHn The baud rate generator output is a function of the baud rate generator input BCLKIN and the 16 bit divisor DLHn UD15 8 7 0 baud rate generator output frequency frequency divisor bit rate shifting rate baud rate generator output frequency 16 NOTE The divisor latch registers share address ports wi
259. OCESSOR USER S MANUAL intel Bit 4 P1CFG Value Bit P2CFG Value Bit P3CFG Value 7 0 P1 7 7 0 P2 7 7 0 P3 7 1 HLDA 1 50 12 COMCLK 6 0 1 6 6 0 2 6 6 0 P3 6 1 HOLD 1 TXDO 1 PWRDOWN 5 0 P1 5 5 0 2 5 5 0 P3 5 1 LOCK 1 RXDO 1 INT3 4 0 P1 4 4 0 P2 4 4 0 P3 4 1 RIO 1 CS4 1 INT2 3 0 P1 3 3 0 P2 3 3 0 P3 3 1 DSRO 1 CS3 1 INT1 2 0 P1 2 2 0 P22 2 0 P32 12 DTRO 12 CS2 12 INTO 1 02 P1 1 1 0 P2 1 1 0 P3 1 12 RTSO 12 CS14 12 mux 0 0 P1 0 0 0 P2 0 0 0 P3 0 12 DCDO 12 50 12 mux Bit PINCFG Value Pins wo Muxes X Pins w o Muxes X 7 Reserved DRQO TMRCLKO 6 0 CS6 DCD1 INT4 1 REFRESH DRQ1 TMRGATEO 5 0 Coprocessor Sigs RXD1 INT5 1 TMR2 Signals DSR1 TMROCLK1 4 0 DACKO STXCLK INT6 1 CS5 RI1 TMRGATE1 3 0 EOP SSIORX INT7 1 CTS14 2 0 DACK1 1 TXD1 NOTES 1 0 SRXCLK 1 PEREQ BUSY ERROR 1 DTR1 2 TMROUT2 TMRCLK2 TMRGATE2 0 0 SSIOTX 1 RTS1 5 34 Table 5 9 Pin Configuration Register Design Woksheet intel DEVICE CONFIGURATION Bit DMACFG Value 7 0 Enables DACK1 at chip pin 12 Disables DACK1 at chip pin 6 4 000 DRQ1 pin external peripheral connected t
260. OCESSOR USER S MANUAL intel 10 3 2 Initializing the Counters The timer control register TMRCON has three formats control word counter latch and read back When writing to TMRCON certain bit settings determine which format is accessed Use the TMRCON s control word format Figure 10 25 to specify a counter s count format and operating mode Writing the control word forces OUTT to go to an initial state that depends on the selected operating mode 10 24 intel TIMER COUNTER UNIT Timer Control Control Word Format Expanded Addr F043H TMRCON ISA Addr 0043H Reset State XXH 7 0 SC1 SCO RW1 Rwo 1 MO CNTFMT Bit Bit A Number Mnemonic Function 7 6 SC1 0 Select Counter Use these bits to specify a particular counter The selections you make for bits 5 0 define this counter s operation 00 counter 0 01 counter 1 10 counter 2 11 is not an option for TMRCON s control word format Selecting 11 accesses TMRCON s read back format which is shown in Figure 10 29 5 4 RW1 0 Read Write Select These bits select a read write option for the counter specified by bits 7 6 01 read write least significant byte only 10 read write most significant byte only 11 read write least significant byte first then most significant byte 00 is not an option for TMRCON s control word format Selecting 00 accesses TMRCON s counter latch format which is shown in Figure 10 27 3 1 M2 0
261. OD1 write only FOOBH 000BH DMA Mode 1 Determines the data transfer mode Enables the autoinitialize buffer transfer mode Determines the transfer direction whether the target is the destination or source for a transfer Determines whether the DMA increments or decrements the target address during a buffer transfer only if the DMA is set up to modify the target address see DMAMOD2 DMAMOD2 write only 1 2 Selects the data transfer bus cycle option Specifies whether the requester and target are in memory or Determines whether the DMA modifies the target and requester addresses Determines whether the DMA increments or decrements the requester address during a buffer transfer only if the DMA is set up to modify the requester address DMASRR read write F009H 0009H DMA Software Request Write Format Generates a channel 0 and or a channel 1 software request Read Format Indicates whether a software request is pending on DMA channel 0 or 1 DMAMSK write only FOOAH 000AH DMA Individual Channel Mask Individually masks disables channel 0 s and 1 s hardware request input DREQO and DREQ1 This does not mask software requests DMAGRPMSK read write FOOFH 000FH DMA Group Channel Mask Simultaneously masks disables both channels hardware request inputs DREQO and DREQ1 This does not mask software requests DMABSR w
262. OPROCESSOR USER S MANUAL intel define SIO 0 0 define LENGTH 32 char String Read LENGTH int error error SerialReadStr SIO 0 String Read LENGTH Real Protected Mode No changes required eK RR AR IR RR ARAKI Ck ko Kk k kk kk int SerialReadStr int Unit char far str int count WORD ReceivePortAddr WORD StatusPortAddr BYTE Status int i Set Port base based on serial port used ReceivePortAddr Unit RBR1 RBRO StatusPortAddr Unit LSR1 LSRO for i 0 i lt count 1 i Status register is cleared after read so we must save it s value when read while Status GetEXRegByte StatusPortAddr amp SIO RX BUF FULL if Status amp SIO ERROR BITS Error Bit set then return NULL str itl 0 return Status amp SIO_ERROR_BITS str i _GetEXRegByte ReceivePortAddr str i 0 return E_OK SerialReadStr BORK KK KKK kk kk Kk Ck Kk kk Ck Kk KC kk Ck Ck kk Ck Kk KC Kk Ck kk Kk Ck CK Ck Ck Kk KC Kk Ck ke Kk Ck kk ke kk ko ke kk ek SerialReadChar Description Is a Polled serial port read function that waits forever or 11 36 intel ASYNCHRONOUS SERIAL UNIT until a character has been received from the serial port Parameters Unit Unit number of the serial port 0 for SIO port 0 1 for SIO port 1 Returns BYTE Read from serial port if zero an error occurred Assumptions REMAPCFG register has Expanded I
263. ORD CounterH lt lt 8 CounterL return Counter CounterLatch 10 38 intel TIMER COUNTER UNIT BORK KK KKK Kk Ck CK RK A IKK Kk kk Kk k OK Ck Ck Kk k k Kk k k Kk Ck Kk k k Kk Ck k ke k k k k k k ReadCounter Description This function performs a simple read operation on the specified timer However because the counter value is not latched the timer must be disabled read and then re enabled Parameters Timer Unit number of Timer whose count is being read Returns Counter value that was read Assumptions This function assumes that the R W format is configured to be LSB first then MSB Syntax WORD Counter Value Counter Value ReadCounter Real Protected Mode No changes required Ck kk k WORD ReadCounter BYTE Timer BYTE CountL CountH WORD Count 0 DisableTimer switch Timer case TMR 0 CountL GetEXRegByte CountH GetEXRegByte TMRO break case TMR 1 CountL GetEXRegByte TMR1 CountH GetEXRegByte TMR1 break 10 39 Intel386 EX EMBEDDED PROCESSOR USER S MANUAL intel case TMR 2 CountL GetEXRegByte TMR2 CountH GetEXRegByte TMR2 break Count WORD CountH lt lt 8 CountL EnableTimer return Count ReadCounter e e A e e A A E A A e e A k e A He e A A e A k k A k e A A k k A k k k k k k k k k k k k k k
264. ORT92H register B 1 6 HOLD HLDA Pins These pins do not connect directly to the CPU Instead they go to the Bus Arbiter which controls the internal HOLD and HLDA signals connected to the CPU core However the presence of the bus arbiter is transparent as far as functionality of the external HOLD and HLDA pins of Intel386 EX processor are concerned Ina PC AT system if an external bus master gains the bus by raising HOLD to the CPU or raising DREQ in DMA cascade mode the corresponding HLDA or DACK signal stays active until the bus master drops HOLD or DREQ In the Intel386 EX processor when the refresh control unit requests the bus the bus arbiter deactivates the signals on the HLDA or DACK pins while the external bus master still has the bus HOLD or DREQ is high At this point the external bus mas ter or DMA must deassert its HOLD or DREQ signal for a minimum of one CPU clock cycle and it can then assert the signal again B 4 intel COMPATIBILITY WITH THE PC AT ARCHITECTURE B 1 7 Port B The Port B register found on the PC AT is not supported on the Intel386 EX processor It can be implemented externally with PLD EXPLR1 Explorer Evaluation board supports this Port B B 2 SOFTWARE CONSIDERATIONS FOR A PC AT SYSTEM ARCHITECTURE 2 1 Embedded Basic Input Output System BIOS The BIOS provides low level drivers to interface to the hardware The BIOS is hardware depen dent and typically requires changes for the em
265. PC AT ARCHITECTURE APPENDIX B COMPATIBILITY WITH THE PC AT ARCHITECTURE The Intel386 EX embedded processor is NOT 100 PC AT compatible Due to compatibility issues not all PC software executes on the Intel386 EX processor In addition not all ISA PC 104 cards operate in an Intel386 EX processor system Itis the responsibility of the designer to determine if a specific PC AT software or hardware pack age operates on an Intel386 EX processor system Typically an embedded PC can be very differ ent from a traditional desktop PC s system The embedded PC may have more or less functionality than a desktop PC It is important for the designer to evaluate the requirements of the PC software or hardware that is expected to operate on the Intel386 EX processor system This appendix is organized as follows Hardware Departures from PC AT System Architecture see below Software Considerations for a PC AT System Architecture page B 5 1 HARDWARE DEPARTURES FROM PC AT SYSTEM ARCHITECTURE This appendix describes the areas in which the Intel386 EX processor departs from a standard PC AT system architecture and explains how to work around those departures if necessary Chap ter 5 DEVICE CONFIGURATION shows an example configuration for a PC AT compatible system 1 1 DMA Unit The PC AT architecture uses two 8237A DMA controllers connected in cascade for a total of seven channels One DMA controller allows byte transfers and
266. PROCESSOR USER S MANUAL intel 12 3 12 Bus Size Register DMABSR Use DMABSR to determine the requester and target data bus widths 8 or 16 bits DMA Bus Size Expanded Addr F018H DMABSR ISA Addr write only Reset State X1X10000B 7 0 RBS TBS 0 CS Bit Bit Number Mnemonic Function Reserved for compatibility with future devices write zero to this bit RBS Requester Bus Size Specifies the requester s data bus width for the channel specified by bit 0 0 16 bit bus 1 8 bit bus Reserved for compatibility with future devices write zero to this bit TBS Target Bus Size Specifies the target s data bus width for the channel specified by bit 0 0 16 bit bus 1 8 bit bus 3 1 0 Must be 0 for correct operation 0 CS Channel Select 0 The selections for bits 7 4 affect channel 0 1 The selections for bits 7 4 affect channel 1 Figure 12 31 DMA Bus Size Register DMABSR 12 46 intel DMA CONTROLLER 12 3 13 Chaining Register DMACHR Use DMACHR to enable or disable the chaining buffer transfer mode for a selected channel The following steps describe how to set up a channel to perform chaining buffer transfers Set up the chaining interrupt DMAINT service routine Configure the channel for the single buffer transfer mode Program the mode registers Program the target address requester address and byte cou
267. Phase 2 of T2 T2P or T2i The READY signal is also used to deassert the WR signal Refer to Write Cycle on page 6 16 WR Device pin Write Enable Indicates that the current bus cycle is a write cycle and valid data is present on the data bus intel BUS INTERFACE UNIT 6 2 BUS OPERATION The processor generates eight different types of bus operations Memory data read data fetch Memory data write Memory code read instruction fetch I O data read data fetch I O data write Halt or shutdown Refresh Interrupt acknowledge These operations are defined by the states of four bus status pins D C W R and RE FRESH Table 6 2 lists the various combinations and their definitions Table 6 2 Bus Status Definitions D C W R REFRESH Bus Operation 0 0 0 1 interrupt acknowledge cycle 0 1 1 never occurs 0 1 0 1 data read 0 1 1 1 I O data write 1 0 0 1 memory code read 1 0 1 1 halt or shutdown cycle 1 1 0 0 refresh cycle 1 1 0 1 memory data read 1 1 1 1 memory data write byte address is 2 for a halt and 0 for a shutdown For both conditions BHE is high and BLE is low 6 5 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Cycle 4 Idle Cycle 3 Cycle 2 Cycle 1 59 9 285 253 250 xr Cc uj S gt 3 38 P um o 2550 en es 37 9 o E
268. REGISTER QUICK REFERENCE D 68 UCSADH See CSnADH UCSADH on page D 8 D 69 UCSADL See CSnADL UCSADL on page D 9 D 70 UCSMSKH See CSnMSKH UCSMSKH on page D 10 D 71 UCSMSKL See CSnMSKL UCSMSKL on page D 11 D 67 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel D 72 WDTCNTH AND WDTCNTL WDT Counter Value High Expanded Addr F4C4H WDTCNTH ISA Addr read only Reset State 003FH 15 2 WC31 WC30 WC29 WC28 WC27 WC26 WC25 WC24 7 0 WC23 WC22 WC21 WC20 WC19 WC18 WC17 WC16 WDT Counter Value Low Expanded Addr F4C6H WDTCNTL ISA Addr read only Reset State FFFFH 15 B WC15 WC14 WC13 WC12 WC11 WC10 WC9 WC8 7 0 WC7 WC6 WC5 WC4 WC3 WC2 WC1 WCO Bit Number Bit Function Mnemonic High 15 0 WC31 16 WDT Counter Value High Word and Low Word Low 15 0 WC15 0 Read the high word of the counter value from WDTCNTH and the low word from WDTONTL D 68 intel SYSTEM REGISTER QUICK REFERENCE D 73 WDTRLDH AND WDTRLDL WDT Reload Value High Expanded Addr WDTRLDH ISA Addr read write Reset State 003FH 15 8 WR31 WR30 WR29 WR28 WR27 WR26 WR25 WR24 7 0 WR23 WR22 WR21 WR20 WR19 WR18 WR17 WR16 WDT Reload Value Low Expanded Addr F4C2H WDTRLDL ISA Addr r
269. Read Format 10 29 Intel386 EX EMBEDDED PROCESSOR USER S MANUAL intel 10 3 4 3 Read back Command Use the read back format of TMRCON Figure 10 29 to latch the count and or status of one or more counters Latch a counter s status to check its programmed operating mode count format and read write selection and to determine whether the latest count written to it has been loaded Timer Control Read back Format Expanded Addr F043H TMRCON ISA Addr 0043H Reset State XXH 7 0 1 1 COUNT STAT CNT2 CNT1 CNTO 0 Bit Bit Function Number Mnemonic vneto 7 6 Write ones to these bits to select the read back command 00 01 and 10 are not valid options for TMRCON s read back format 5 COUNT Count Latch 0 Clearing this bit latches the count of each selected counter Use bits 3 1 to select one or more of the counters 1 No effect 4 STAT Status Latch 0 Clearing this bit latches the status of each selected counter Use bits 3 1 to select one or more of the counters 1 No effect 3 CNT2 Counter 2 Select 0 The actions specified by bits 5 and 4 do not affect counter 2 1 The actions specified by bits 5 and 4 affect counter 2 2 CNT1 Counter 1 Select 0 The actions specified by bits 5 and 4 do not affect counter 1 1 The actions specified by bits 5 and 4 affect counter 1 1 CNTO Counter 0 Select 0 The actions specified by bits 5 and 4 do not affect cou
270. S READY Pipeline Bus Size Control Internal Control Bus Displacement Bus Linear Address Bus MUX Transceivers Barrel 7 77 Instruction Prefetcher Shifter Status Decode Decoder Limit Adder and Checker Flags Sequencing Multiply Divide 3 Decoded Code Instruction Stream Queue Register File ALU Control ALU Control Instruction Instruction Predecode Prefetch Dedicated ALU Bus A2851 02 Figure 3 2 The Intel386 CX Processor Internal Block Diagram 3 3 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel The six functional units of the Intel386 CX processor are Core Bus Unit Instruction Prefetch Unit Instruction Decode Unit Execution Unit Segmentation Unit Paging Unit 3 2 1 Core Bus Unit The Core Bus Unit provides the interface between the processor and its environment It accepts internal requests for instruction fetches from the Instruction Prefetch Unit and data transfers from the Execution Unit and prioritizes the requests At the same time it generates or processes the signals to perform the current bus cycle These signals include the address data and control outputs for accessing external memory and I O The Core Bus Unit also controls the interface to external bus masters and coprocessors 3 2 2 Instruction Prefetch Unit The Instruction Prefetch Unit performs the program look ahead function of the CPU
271. S 1 Byte pointer in flip flop in DMA determines which register is accessed 2 Shaded rows indicate reserved areas D 5 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Table D 1 Peripheral Register Addresses Sheet 6 of 6 intel Pai NEM Register Name Reset Value Asynchronous Serial I O Channel 1 COM2 F8F8H 02F8H Byte RBR1 TBR1 DLL1 XX XX 02H F8F9H 02F9H Byte IER1 DLH1 00H 00H F8FAH 02FAH Byte IR 1 01H F8FBH 02FBH Byte LCR1 00H F8FCH 02FCH Byte MCR1 00H F8FDH 02FDH Byte LSR1 60H F8FEH 02 MSR1 F8FFH 02 Byte SCR1 XX NOTES 1 Byte pointer in flip flop in DMA determines which register is accessed 2 Shaded rows indicate reserved areas D 6 intel SYSTEM REGISTER QUICK REFERENCE D 2 CLKPRS Clock Prescale Register Expanded Addr F804H CLKPRS ISA Addr read write Reset State 0000H 15 S 58 7 0 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PSO Bit Bit Functi Number Mnemonic uncon 15 9 Reserved These bits are undefined for compatibility with future devices do not modify these bits 8 0 58 0 Prescale Value These bits determine the divisor that is used to generate PSCLK Legal values are from 0000H divide by 2 to O1FFH divide by 513 divisor PS8 0 2 D 7 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL D 3 CSnADH U
272. S MANUAL Reserved Bits Reserved bits are not used in this device but they may be used in future implementations Follow these guidelines to ensure compatibility with future devices Avoid any software dependence on the state of undefined register bits e Use read modify write sequence to load registers Mask undefined bits when testing the values of defined bits Do not depend on the state of undefined bits when storing undefined bits to memory or to another register Do not depend on the ability to retain information written to undefined bits Set and Clear The terms set and clear refer to the value of a bit or the act of giving it a value If a bit is set its value is 1 setting a bit gives it a 1 value If a bit is clear its value is 0 clearing a bit gives it a 0 value 1 4 RELATED DOCUMENTS The following documents contain additional information that is useful in designing systems that incorporate the Intel386 EX processor To order documents please call Intel Literature Fulfill ment 1 800 548 4725 in the U S and Canada 44 0 1793 431155 in Europe Document Name Order Number Intel386 EX Embedded Microprocessor datasheet 272420 Intel386 SX Microprocessor datasheet 240187 Intel386 SX Microprocessor Programmer s Reference Manual 240331 Intel386 SX Microprocessor Hardware Reference Manual 240332 Development Tools 272326 Buyer s Guide for the Intel386 Embedded Processor Family 2
273. S MANUAL intel 3 2 Intel386 CX PROCESSOR INTERNAL ARCHITECTURE The internal architecture of the Intel386 CX processor consists of functional units that operate in parallel Fetching decoding execution memory management and bus accesses for several in structions are performed simultaneously This parallel operation is called pipelined instruction processing With pipelining each instruction is performed in stages and the processing of several instructions at different stages may overlap as shown in Figure 3 1 The pipelined processing of the Intel386 CX processor results in higher performance and enhanced throughput rate over non pipelined processors Elapsed Time Processor Intel386 SX CPU Intel376 CPU Decode Unit Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Execution Addr amp Addr amp Nu ONES OE LEM A2850 01 Figure 3 1 Instruction Pipelining 3 2 intel CORE OVERVIEW Figure 3 2 shows the internal architecture of the Intel386 CX processor 3 Core Plus Segmentation Unit Paging Unit Unit HOLD INTR NMI ERROR BUSY Request RESET HLDA Prioritizer SMl SMIACT PEREQ Effective Address Bus Descriptor Register Effective Address Bus Physical Address Bus Limit and Control and Attribute Attribute PLA BEO BE1 A25 1 Address Protection Driver Test Unit D C W R LOCK AD
274. S MANUAL intel typedef enum DMA 10 0 DMA Channell 1 DMAChannelEnum typedef enum ERR NONE 0 ERR BADINPUT 1 ERREnum DMA Function Definitions int SetDMAReqIOAddr int nChannel WORD wIO int SetDMATargMemAddr int nChannel void ptMemory int SetDMAXferCount int nChannel DWORD lCount int EnableDMAHWRequests int nChannel int DisableDMAHWRequests int nChannel void InitDMA void void InitDMAlForSerialXmitter void RR KR ke ke ke e e ke e e e x Port I O configuration defines ke e e e e x x Port 1 configuration defines define DCDO Ox define RTSO 0x2 define DTRO 0 4 define DSRO 0x8 define RIO 0 10 define LOCK 0x20 define HOLD 0X40 define HOLDACK 0x80 Port 2 configuration defines define CS0 0x define CS 0x2 define CS2 0x4 define CS3 0x8 define CS4 0X10 define RXDO 0x20 define TXDO 0X40 define CTSO 0x80 Port 3 configuration defines define TMROUTO 0 1 define TMROUT1 0x2 define INTO 0 4 define 0 8 define INT2 0x10 define INT3 0x20 define PWRDWN 0x40 define COMCLK 0x80 Port Direction defines define PO IN 0 1 ext intel fine P1 IN 0x2 fine P2 IN 0 4 fine P3 IN 0 8 fine P4 0 10 fine P5 0x20 fine P6 IN 0x40 fine P7_IN 0x80 fine Px_OUT 0 fine RTS1 0 1 fine SSIOTX 0 fine DTR1 0 2 fine SRXCLK 0 fine TXD1 0 4 fine DACK1 0 fine 51 0 8 fine EOP
275. S connected to slave IRO 1 INT4 connected to slave IRO Table 5 12 INTCFG Register Design Worksheet SIOCFG 7 0 SIO1 modem sigs conn to pin muxes 1 SIO1 modem signals internal 6 0 SIOO modem sigs conn to pin muxes 1 5100 modem signals internal 5 3 Reserved 2 0 PSCLK connected to SSIO BLKIN 1 SERCLK connected to SSIO BCLKIN 1 0 COMCLK connected to SIO1 BCLKIN 1 SERCLK connected to SIO1 BCLKIN 0 0 COMCLK connected to 5100 BCLKIN 1 SERCLK connected to SIOO BCLKIN Table 5 13 SIOCFG Register Design Worksheet 5 37 intel BUS INTERFACE UNIT CHAPTER 6 BUS INTERFACE UNIT The processor communicates with memory I O and other devices through bus operations Ad dress data status and control information define a bus cycle The Bus Interface Unit supports read and write cycles to external memory and I O devices It also contains the signals that allow external bus masters to request and acquire control of the bus The Bus Interface Unit BIU can execute memory read write cycles I O read write cycles interrupt acknowledge cycles refresh cycles and processor halt shutdown cycles This chapter is organized as follows Overview see below Bus Operation page 6 5 Bus Cycles page 6 13 Bus Lock page 6 34 External Bus Master Support Using HOLD HLDA page 6 35 Design Considerations page 6 38 6 1 OV
276. SA Addr read write Reset State 0000H 15 8 RA25 RA24 RA23 RA22 7 0 RA21 RA20 RA19 RA18 RA17 RA16 RA15 RA14 Bit Bit Number Mnemonic Function 15 12 Reserved These bits are undefined for compatibility with future devices do not modify these bits 11 0 RA25 14 Refresh Base These bits make up the A25 14 address bits of the refresh address This establishes a memory region for refreshing Figure 15 4 Refresh Base Address Register RFSBAD 15 9 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 15 4 4 Refresh Address Register RFSADD RFSADD contains the bits A13 1 of the refresh address The lowest address bit is not used be cause most DRAM devices contain word wide memory arrays for all refresh operations the low est address bit remains set Refresh Address Expanded Addr F4A6H RFSADD ISA Addr read write Reset State 00 15 8 RA13 RA12 RA11 RA10 RA9 RA8 7 0 RA7 RA6 RA5 RA4 RA3 RA2 RA1 1 Bit Bit Number Mnemonic Function 15 14 Reserved These bits are undefined for compatibility with future devices do not modify these bits 13 1 RA13 1 Refresh Address Bits These bits comprise A13 1 of the refresh address 0 Refresh Bit 0 AO of the refresh address This bit is always 1 and is read only 15 10 Figure 15 5 Refresh Address Register RFSADD inte
277. SERIAL UNIT Initialization routine for Synchronous Serial I O Port Parameters Mode Enables receiver and transmitter Enables TBE and RHBF interrupts MasterTxRx Defines whether Tx and or Rx are in Master Mode BaudValue Enables Baud rate generator and sets Baud rate Value PreScale 9 bit Clock prescale value Returns None Assumptions PINCFG amp SIOCFG should be configured before this is called Prescale is only used if SIOCFG 2 is clear Syntax define SSIO TX MASTR 0x2 Transmit Master Mode define SSIO RX MASTR 0x1 Receive Master Mode define SSIO TX SLAVE 0 Transmit Slave Mode define SSIO RX SLAVE 0 Receive Slave Mode define SSIO TX IE 0x20 Transmit Interrupt Enable define SSIO TX ENAB 0x10 Transmitter Enable define SSIO_RX_IE 0 2 Receive Interrupt Enable define SSIO RX ENAB 0x1 Receiver Enable define SSIO BAUD ENAB 0x80 Enable Baud Rate Generator define SSIO CLK SERCLK 0 1 Baud Rate Clocking Source SERCLK CLK2 4 define SSIO CLK PSCLK 0x0 Baud Rate Clocking Source PSCLK CLK2 2 CLKPRS 2 InitSSIO SSIO TX IE SSIO TX ENAB SSIO_RX_ENAB SSIO RX MASTR SSIO TX SLAVE SSIO BAUD ENAB SSIO CLK PSCLK Real Protected Mode No changes required eK RR A A IK RR Kk Rok kk KC CK Ck Ck IR AA IRR kk Kk void InitSSIO BYTE Mode BYTE MasterTxRx BYTE BaudValue BYTE PreScale Set clocking iff either TX or RX is a master if MasterTxRx 0
278. SMSKL WDTCNTH AND WDTRLDH AND WDTRLDL seen 2 intel APPENDIX E INSTRUCTION SET SUMMARY INSTRUCTION ENCODING AND CLOCK COUNT SUMMARY INSTRUCTION ENCODING 32 bit Extensions of the Instruction Set Encoding of Instruction Fields Encoding of Operand Length w Field Encoding of the General Register reg Field Encoding of the Segment Register sreg Field Encoding of Address Mode sese eee Encoding of Operation Direction d Field Encoding of Sign Extend s Field Encoding of Conditional Test tttn Field 2 Encoding of Control or Debug or Test Register eee Field E 2 1 E 2 2 E 2 2 1 E 2 2 2 2 2 3 2 2 4 E 2 2 5 E 2 2 6 E 2 2 7 E 2 2 8 GLOSSARY INDEX CONTENTS XV Intel386 EX MICROPROCESSOR USER S MANUAL intel FIGURES Figure Page 2 1 Intel386 V EX Embedded Processor Block Diagram 2 2 3 1 Instruction Pipelining cette e teats 3 2 3 2 The Intel386 V CX Processor Internal Block Diagram 3 3 4 1 PC AT I O Address Space 10 bit 4 3 4 2 Expanded I O Address Space 16 bit Decode 4 4 4 3
279. SRAM Device Anexternal device can gain bus control through either the HOLD signal or the DMA cascade mode In this case a refresh request causes HLDA or DACKn signal to be deasserted When this happens the external device must drop its request line HOLD or DRQn to allow the to perform a refresh cycle The refresh request remains pending until the RCU gets control of the bus 15 11 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Ifthe counter value stored in the Refresh Clock Interval Register RFSCIR is 8 and the RCU is enabled the RCU always has bus control and other devices will never gain access to the bus This is because refresh requests have the highest priority in the bus arbitration scheme and you are requesting the bus too often There are two common methods of refreshing DRAM RAS only and CAS before RAS RAS only refresh takes advantage of the Intel386 EX Embedded Processor s built in refresh address counter RFSADD Ina CAS before RAS refresh the DRAM provides the row address for the refresh cycle The RCU counter still generates the row addresses but they are disregarded by the DRAM The only external logic required is a PLD to recognize a refresh cycle and provide the CAS and RAS signals to the DRAM Page Mode A paged DRAM access uses the upper address lines for the row addresses and the lower lines for the column addresses On the Intel386 EX embedded processor the
280. Selects CS4 at the package pin 3 PM3 Pin Mode 0 Selects P2 3 at the package pin 1 Selects CS3 at the package pin 2 PM2 Pin Mode 0 Selects P2 2 at the package pin 1 Selects CS2 at the package pin 1 PM1 Pin Mode 0 Selects P2 1 at the package pin 1 Selects CS1 at the package pin 0 PMO Pin Mode 0 Selects P2 0 at the package pin 1 Selects CSO at the package pin Figure 14 5 Port 2 Configuration Register P2CFG 14 16 intel CHIP SELECT UNIT 14 4 3 Chip select Address Registers The Address Register of each chip select channel defines the address block that the channel re sponds to during an access The value in this register is compared to A25 11 of the processor bus during a memory access and to A15 1 during an I O access A bus cycle whose address matches the non masked see Chip select Mask Registers on page 14 19 bits of the Address Register causes the respective chip select channel to have an address match Even if there is an address match whether or not the CSU activates the channel depends on the values of the channel s SMM address and mask bits CASMM and CMSMM and the chip select channel enable bit CSEN The CASMM and CMSMM bits determine whether or not the channel is activated when the pro cessor is operating in SMM Write a channel s 15 bit address to the chip select address registers These bits are masked by the channel s 15 bit mask NOTE When a chip select chann
281. Selects P2 5 at the package pin 1 Selects RXDO at the package pin 4 PM4 Pin Mode 0 Selects P2 4 atthe package pin 1 Selects CS4 at the package pin 3 PM3 Pin Mode 0 Selects P2 3 at the package pin 1 Selects CS3 at the package pin 2 PM2 Pin Mode 0 Selects P2 2 at the package pin 1 Selects CS2 at the package pin 1 PM1 Pin Mode 0 Selects P2 1 at the package pin 1 Selects CS1 at the package pin 0 PMO Pin Mode 0 Selects P2 0 atthe package pin 1 Selects CSO at the package pin D 44 intel SYSTEM REGISTER QUICK REFERENCE D 42 P3CFG Port 3 Configuration Expanded Addr F824H P3CFG ISA Addr read write Reset State 00H 7 0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PMO Bit Bit Functi Number Mnemonic enor 7 PM7 Pin Mode 0 Selects P3 7 at the package pin 1 Selects COMCLK at the package pin 6 PM6 Pin Mode 0 Selects P3 6 at the package pin 1 Selects PWRDOWN at the package pin 5 PM5 Pin Mode 0 Selects P3 5 at the package pin 1 Connects master to the package pin 4 PM4 Pin Mode 0 Selects P3 4 at the package pin 1 Connects master IR6 to the package pin INT2 3 PM3 Pin Mode 0 Selects P3 3 at the package pin 1 Connects master IR5 to the package pin INT1 2 PM2 Pin Mode 0 Selects P3 2 at the package pin 1 Connects master IR1 to the package pin INTO 1 PM1 Pin Mode S
282. T 17 2 WDT Registers MO nese 17 7 18 1 Test Access Port Dedicated 18 3 18 2 TAP Controller State 418 4 18 3 Example TAP Controller State Selections sse 18 5 18 4 Test logic Unit Instructions 18 5 Boundary scan Register Bit Assignments RR Rr e EE eee tcn 18 9 A 1 Signal Description Abbreviations eese A 1 A 2 Description of Signals Available at the Device 2 A 3 Pin State Abbreviation S essene 8 4 Pin States After Reset and During Idle Powerdown and Hold A 9 D 1 Peripheral Register 0 E 1 Instruction Set E 2 Fields Within Instructions E 3 Encoding of Operand Length w Field E 4 Encoding of reg Field When w Field is not Present in Instruction E 24 E 5 Encoding of reg Field When w Field is Present in Instruction E 25 E 6 Encoding of the Segment Register sreg E725 E 7 Encoding of 16 bit Address Mode with mod r m Byte E 27 E 8 Enco
283. T Gul To TCU TMRCLK1 INTCFG 2 INTCFG 3 Vss 1 77 To TCU TMRGATE1 IR7 lt WDTOUT INTCFG 7 3 Vss 7 CAS2 0 Mode A18 16 Alternate pin signals are in parentheses Heavier lines indicate multiple signals A2522 03 Figure 5 4 Interrupt Control Unit Configuration 5 9 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Interrupt Configuration Expanded Addr F832H INTCFG ISA Addr read write Reset State 00H 7 0 CE IR3 IRA SWAP IR6 IR5 IR4 IR1 IRO Bit Bit Function Number Mnemonic uncuo 7 CE Cascade Enable 0 Disables the cascade signals CAS2 0 from appearing on the A18 16 address lines during interrupt acknowledge cycles 1 Enables the cascade signals CAS2 0 providing access to external slave 82C59A devices The cascade signals are used to address specific slaves If enabled slave IDs appear on the A18 16 address lines during interrupt acknowledge cycles but are high during idle cycles 6 IR3 Internal Master IR3 Connection See Table 5 1 on page 5 8 for all the IR3 configuration options 5 IR4 Internal Master IR4 Connection See Table 5 2 on page 5 8 for all the IR4 configuration options 4 SWAP INT6 DMAINT Connection 0 Connects DMAINT to the slave IR4 Connects INT6 to the slave IR5 1 Connects the INT6 pin to the slave IR4 Connects DMAINT to the slave 5 3 IR6 Internal Slave IR6 Connec
284. TCFG OF832H Interrupt Configuration read write Determines the master s and the slave s IR signal connections SIOINT1 or INT8 SIOINTO or INT9 Vas or INT7 Vss or INT6 SSIOINT or INT5 Vas or INT4 Swaps DMAINT and INT6 Also enables the master s cascade bus CAS2 0 When enabled the cascade signals appear on the A18 16 address lines during an interrupt acknowledge cycle ICW1 master 0 020 0020H Initialization Command Word 1 ICW1 slave 00A0H Determines whether interrupt request signals are level write only sensitive or edge triggered ICW2 master 0 021 0021H Initialization Command Word 2 ICW slave OFOA1H 00A1H Contains the base interrupt vector number for the 82C59A write only The base interrupt vector is the IRO vector number the base plus one is the IR1 vector number and so on ICW3 master 0 021 0021H Initialization Command Word 3 write only Identifies the master s IR signals that are connected to slave 82C59A devices The internal slave is connected to the master s IR2 signal You can connect external slaves to the master s IR1 IR3 IR4 IR5 IR6 and IR7 signals ICW3 slave OFOA1H 00 1 Initialization Command Word 3 write only Indicates that the internal slave is cascaded from the master s IR2 signal ICW4 master 0 021 0021H Initialization Command Word 4 ICWA slave OFOA1H 00A1H Selects either special fully nested or fully nested mode and write only enable
285. The active register retains its previous state Pause DR Update DR Exit2 DR The active register retains its previous state Shift DR Update DR Applies stimulus to the device Data is latched onto Update DR the active register s parallel output on the falling Run Test ldle Select DR Scan edge of TCK If the register has no parallel output it retains its previous state NOTE By convention the abbreviation DR stands for data register and stands for instruction register The active register is the register that the current instruction has placed in the serial path between TDI and TDO 18 4 intel JTAG TEST LOGIC UNIT Table 18 2 TAP Controller State Descriptions Sheet 2 of 2 Next State State Description on TCK Rising Edge TMS 0 TMS 1 Ip Test logic is idle and the instruction register retains SIR Select IR Scan its previous state Capture IR Test Logic Reset Loads the SAMPLE PRELOAD instruction instruction 0001 into the instruction register phu Shifts the SAMPLE PRELOAD instruction one Shift IR stage toward TDO while shifting the new instruction Shift IR Exit1 IR in from TDI on each rising edge of TCK Exit1 IR The instruction register retains its previous state Pause IR Update IR _ The instruction register temporarily stops shifting TE Pause IR and retains its previous state Pause IR Exit2 IR The instruct
286. The processor supports this function by an extension to the internal chip select unit In addition external logic can use this pin to qual ify RESET and SMI SMIACT never transitions during a pipelined bus cycle 7 2 3 System Management RAM SMRAM The SMM architecture requires that a partition of memory be set aside for the SMM driver This is called the SMRAM Several requirements must be met by the system The address range of this partition must be as a minimum from 038000H to 03FFFFH 32 Kbytes The address range from 03 to 03FFFFH 512 bytes is reserved for the CPU and must be RAM The SMM handler must start execution at location 038000H It is not relocatable During normal operation the SMRAM is only accessible when the system is in SMM During system initialization it must be possible to access the SMRAM in order to initialize it and possibly to install the SMM driver Obviously this must be done outside of SMM When the SMRAM overlays other memory in the system then address decoding and chip selects must allow the SMM driver to access the shadowed memory locations while in SMM The SMRAM should not be accessible to alternate bus masters such as DMA These requirements are made to ensure that the SMM remains transparent to non SMM code and to maintain uniformity across the various Intel processors that support this mode NOTE It is possible for the designer of an embedded system to place t
287. This bit is undefined for compatibility with future devices do not modify this bit 6 PM6 Pin Mode 0 Selects CS6 at the package pin 1 Selects REFRESH at the package pin 5 PM5 Pin Mode 0 Selects the coprocessor signals PEREQ BUSY and ERROR Z at the package pins 1 Selects the timer control unit signals TMROUT2 2 and TMRGATE2 at the package pins 4 PM4 Pin Mode 0 Selects DACKO at the package pin 1 Selects CS5 at the package pin 3 PM3 Pin Mode 0 Selects EOP at the package pin 1 Selects CTS1 at the package pin 2 PM2 Pin Mode 0 Selects DACK1 at the package pin 1 Selects TXD1 at the package pin 1 PM1 Pin Mode 0 Selects SRXCLK at the package pin 1 Selects DTR1 at the package pin 0 PMO Pin Mode 0 Selects SSIOTX at the package pin 1 Selects RTS1 at the package pin Figure 12 18 Pin Configuration Register PINCFG 12 31 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 12 3 2 DMA Configuration Register DMACFG Use DMACFG to select one of the hardware sources for each channel and to mask the DMA ac knowledge DMAACKn signals when using internal requesters 7 DMA Configuration DMACFG read write Expanded Addr F830H ISA Addr Reset State 00H 0 D1MSK D1REQ2 D1REQ1 D1REQO DOMSK DOREQ2 DOREQ1 DOREQO Bit Number Bit Mnem
288. Timer n Status Format Expanded Addr F040H F041H TMRn n 0 2 F042H ISA Addr 0040H 0041H 0042H Reset State XXH 7 0 OUTPUT NULCNT RW1 RWO M2 M1 MO CNTFMT Bit Bit Function Number Mnemonic unctio 7 OUTPUT Output Status This bit indicates the current state of the counter s output signal 0 OUT is low 1 OUTnis high 6 NULCNT Count Status This bit indicates whether the latest count written to the counter has been loaded Some modes require a gate trigger before the counter loads new count values 0 the latest count written to the counter has been loaded 1 acount has been written to the counter but has not yet been loaded 5 4 RW1 0 Read Write Select Status These bits indicate the counter s programmed read write selection 00 Never occurs 01 read write least significant byte only 10 read write most significant byte only 11 read write least significant byte first then most significant byte 3 1 M2 0 Mode Status These bits indicate the counter s programmed operating mode 000 mode 0 001 mode 1 X10 mode 2 X11 mode 3 100 mode 4 101 mode 5 X is a don t care 0 CNTFMT Counter Format Status This bit indicates the counter s programmed count format 0 binary 16 bits 1 binary coded decimal 4 decades Figure 10 30 Timer n Register TMRn Status Format 10 32 intel TIMER COUNTER UNIT When counter receives multiple re
289. WER MANAGEMENT UNIT 8 3 1 Mode Idle mode freezes the core clocks low and PH2C high and leaves the peripheral clocks PHIP and PH2P toggling To enter idle mode 1 Program the PWRCON register Figure 8 5 2 Execute a HALT instruction 3 The CPU enters idle mode when READY terminates the halt bus cycle NOTE CLKOUT continues to run while the CPU is in idle mode 1 1 1 1 1 PH2C t 1 1 1 CLKOUT PH1P SN 1 1 1 me _ __ 1 1 1 1 1 1 1 1 1 1 1 1 PH1C i 1 PH2C EE REN XS Gu MER MEZ 1 1 1 1 1 1 1 1 CLKOUT PH1P ASF NV f NV o 1 1 1 1 1 2468 02 Figure 8 6 Timing Diagram Entering and Leaving Idle Mode 8 9 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 8 3 2 Powerdown Mode Powerdown mode freezes both the core clocks and the peripheral clocks PH1C and PHIP low PH2C and PH2P high The BIU cannot acknowledge DMA refresh and external hold requests in powerdown mode since all the clocks are frozen To enter powerdown mode follow these steps 1 Program the PWRCON register Figure 8 5 2 Execute a HALT instruction 3 CPU enters powerdown mode when READY internal or external terminates the halt bus cycle When P3 6 PWRDOWN is configured as a peripheral pin the pin goes high when the clocks stop to indicate that the device is in powerdown mode Chapter 16 explains how to configure the pin as either a per
290. WLSO Bit Bit Number Mnemonic Function 7 DLAB Divisor Latch Access Bit This bit determines which of the multiplexed registers is accessed 0 Allows access to the receiver and transmit buffer registers RBRn and TBRn and the interrupt enable register IERn 1 Allows access to the divisor latch registers DLL n and DLHn 6 SB Set Break 0 No effect on TXDn 1 Forces the TXDn pin to the spacing logic 0 state for as long as bit is set SP Sticky Parity Even Parity Select and Parity Enable EPS These bits determine whether the control logic produces during transmission or checks for during reception even odd no or forced PEN parity SP EPS PEN Function X X 0 parity disabled no parity option 0 0 1 produce or check for odd parity 0 1 1 produce or check for even parity 1 0 1 produce or check for forced parity parity bit 1 1 1 1 produce or check for forced parity parity bit 0 2 STB Stop Bits This bit specifies the number of stop bits transmitted and received in each serial character 0 1 stop bit 1 2 2 stop bits 1 5 stop bits for 5 bit characters 1 0 WLS1 0 Word Length Select These bits specify the number of data bits in each transmitted or received serial character 00 5 bit character 01 6 bit character 10 7 bit character 11 8 bit character D 36 intel SYSTEM REGISTER QUICK REFERENCE D 34 LSRn Serial Line Status
291. X processor s I O address scheme is similar to that of the Extended Industry Stan dard Architecture EISA bus and the Enhanced Industry Standard Architecture E ISA bus Both standards maintain backward software compatibility with the ISA architecture The ISA Platform I O 0 100H is accessed with a 16 bit address decode and is located in the first 256 I O locations The General Slot I O that is typically used by add in boards is repeated throughout the 64 Kbyte I O address range due to their 10 bit only decode This allows 63 of the 64 repetitions of the first 256 address locations of every 1 Kbyte block to be allocated to specific slots Each slot is 4 Kbyte in size allowing for a total of 16 slots The partitioning is such that four groups of 256 address locations are assigned to each slot for a total of 1024 specific address locations per slot 4 3 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel See Figure 4 2 Thus each slot has 1 Kbyte addresses in four 256 byte segments that can po tentially contain extended peripheral registers FFFFH 64K General Slot I O Slot 15 63K General Slot I O Slot 15 9 F800H 62K General Slot I O Sills F400H 61K General Slot I O Slot 15 9 FOOOH 60K e e e e e e 1FFFH 8K General Slot I O 9 1 00 7K General Slot I O Slot 1 2 1800H 6K General Slot I O Slot 1 1400H 5K General Slot I O Slot 1 1000H 4K General Slot I O
292. YSTEM REGISTER ORGANIZATION 4 6 2 Nonintrusive DOS Mode This mode is achieved by first setting the ESE bit using the three sequential writes setting the individual peripherals remap bits and then clearing the ESE bit Peripherals whose remap bits are set are mapped out of DOS I O space Like DOS compatible mode only address lines A9 0 are decoded internally This mode is useful for connecting an external peripheral instead of using the integrated peripheral For example a system might use an external 8237A DMA rather than using the internal DMA unit For this configuration set the ESE bit set the remap bit associated with the DMA unit and then clear the ESE bit In this case the external 8237A is accessible in the DOS I O space while the internal DMA can be accessed only after the expanded I O space is enabled See Figure 4 6 4 6 3 Enhanced DOS Mode This mode is achieved by setting the ESE bit and clearing all PC AT compatible peripherals remap bits Address lines A15 0 are decoded internally The expanded I O space is enabled and the PC AT compatible internal peripherals are accessible in either DOS I O space or expanded I O space See Figure 4 7 If an application frequently requires the additional peripherals but at the same time wants to maintain DOS compatibility for ease of development this is the most useful mode 4 6 4 Non DOS Mode This mode is achieved by setting the ESE bit and setting all peripherals remap b
293. YSTEM REGISTER QUICK REFERENCE D 44 PnDIR Port Direction Expanded Addr F864H F86CH F874H PnDIR n 1 3 ISA Addr read write Reset State FFH 7 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PDO Bit Bit Number Mnemonic Function 7 0 PD7 0 Pin Direction 0 Configures the pin as a complementary output 1 Configures the pin as an open drain output or high impedance input D 47 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel D 45 PnLTC Port Data Latch Expanded Addr F862H F86AH F872H PnLTC 1 3 ISA Addr read write Reset State FFH 7 0 PL7 PL6 PL5 PL4 PL3 PL2 PL1 PLO Bit Bit Function Number Mnemonic unctio 7 0 PL7 0 Port Data Latch Writing a value to a PL bit causes that value to be driven onto the corresponding pin For a complementary output write the desired pin value to its PL bit This value is strongly driven onto the pin For an open drain output a one results in a high impedance input state atthe pin For a high impedance input write a one to the corresponding PL bit A one results in a high impedance state at the pin allowing external hardware to drive it D 46 PnPIN Port Pin State Expanded Addr F860H F868H F870H PnPIN n 1 3 ISA Addr read only Reset State XXH 7 0 PS7 PS6 PS5 PS4 Pss 52 PS1 PSO Bit Bit _ Number Mn
294. a Reception Process Flow D ne ob eei dd 11 11 Pin Configuration Register eee 11 17 Port 1 Configuration Register 11 18 Port 2 Configuration Register 2 11 19 Port Configuration Register 11 20 SIO and SSIO Configuration Register 11 21 Divisor Latch Registers DLLn and 11 22 Transmit Buffer Register ene 11 23 Receive Buffer Register 11 24 Serial Line Control Register 1 1 25 Serial Line Status Register 15 11 26 Interrupt Enable Register IERn esses 11 27 Interrupt ID Register IIR n mE 11 08 Modem Control Signals Diagnostic Mode Connections spei TW 29 Modem Control Signals Internal 11 29 intel Figure 11 21 11 22 11 23 12 1 12 2 12 3 12 4 12 5 12 6 12 7 12 8 12 9 12 10 12 11 12 12 12 13 12 14 12 15 12 16 12 17 12 18 12 19 12 20 12 21 12 22 12 28 12 24 12 25 12 26 12 27 12 28 12 29 12 30 12 31 12 32 12 33 12 34 13 1 13 2 13 3 13 4 13 5 13 6 CONTENTS FIGURES Page Modem Control Register MCRn seem eeeeeiidl 30 Modem Status Register 2
295. ables below 01 010 SS EDX d8 11 010 register see tables below 01 011 SS EBX d8 11 011 register see tables below 01 100 S i b is present 11 100 register see tables below 01 101 SS EBP d8 11 101 register see tables below 01 110 DS ESI d8 11 110 register see tables below 01 111 DS EDI 08 11 111 register see tables below E 28 Register Specified by r m During 16 bit Data Operations Function of w Field mod r m when w 0 when w 1 11 000 AL AX 11 001 CL CX 11 010 DL DX 11 011 BL BX 11 100 AH SP 11 101 CH BP 11 110 DH SI 11 111 BH DI Register Specified by r m During 32 bit Data Operations Function of w Field mod r m when w 0 when w 1 11 000 AL EAX 11 001 CL ECX 11 010 DL EDX 11 011 BL EBX 11 100 AH ESP 11 101 CH EBP 11 110 DH ESI 11 111 BH EDI intel INSTRUCTION SET SUMMARY Table E 9 Encoding of 32 bit Address Mode Byte and s i b Byte Present mod r m Effective Address 00 000 DS EAX scaled index 00 001 DS ECX scaled index 00 010 DS EDX scaled index 00 011 DS EBX scaled index 00 100 SS ESP scaled index 00 101 DS d32 scaled index 00 110 DS ESI scaled index 00 111 DS EDI scaled index 01 000 DS EAX scaled index d8 01 001 DS ECX scaled index d8 01 010 DS EDX scaled index d8 01 011 DS EBX scaled index d
296. ace so that the processor can fetch the first instruction from address 3FFFFFOH after reset CHIP SELECT UNIT Table 14 1 CSU Signals Device Pin or Internal Signal Signal Description 56 0 Device pins Chip select Signals UCS output Indicates that the memory or I O address that the processor is accessing is in channel n s active address region 14 13 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Table 14 2 CSU Registers Expanded Register Address Description PINCFG OF826H Pin Configuration read write Connects the CS6 5 signals to package pins P2CFG OF822H Port 2 Configuration read write Connects the CS4 0 signals to package pins CSOADH OF 402H Chip select High Address DH OF40AH Defines the upper 10 bits of the chip select channel address The iat EAT processor uses a chip select s channel address to determine the starting i f the ch i CS4ADH 0F422H ocation of the channel s active address block CS5ADH 0 42 CS6ADH 0F432H UCSADH OF43AH read write CSOADL OF400H Chip select Low Address OF 408H Defines the lower 5 bits of the chip select channel address Configures S2ADL OF 410H the channel for memory or I O addresses determines whether or not the CSSADL 0 418 channel is activated when the processor is operating in system CS4ADL OF 420H management mode configures the channel s bus size defines the ER minimum num
297. ackage pi 5 2 2 0 Selects 2 2 at the package pin 1 Selects CS2 at the package pi 5 1 1 Pin Mode 0 Selects P2 1 at the package pin 1 Selects CS1 at the package pi 5 0 0 Selects P2 0 atthe package 1 Selects CSO at the package pi 5 Figure 5 17 Port 2 Configuration Register P2CFG 5 26 intel DEVICE CONFIGURATION Port 3 Configuration Expanded Addr F824H P3CFG ISA Addr read write Reset State 00H 7 0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PMO Bit Bit Functi Number Mnemonic uncon 7 PM7 Pin Mode 0 Selects P3 7 at the package pin 1 Selects COMCLK at the package pin 6 6 Pin Mode 0 Selects P3 6 at the package pin 1 Selects PWRDOWN at the package 5 PM5 Pin Mode 0 Selects P3 5 at the package pin 1 Connects master IR7 to the package pin INT3 4 PM4 Pin Mode 0 Selects P3 4 at the package pin 1 Connects master IR6 to the package pin INT2 3 PM3 Pin Mode 0 Selects P3 3 at the package pin 1 Connects master IR5 to the package pin INT1 2 PM2 Pin Mode 0 Selects P3 2 at the package pin 1 Connects master IR1 to the package pin INTO 1 PM1 Pin Mode See Table 5 1 on page 5 8 for all the PM1 configuration options 0 PMO Pin Mode See Table 5 1 on page 5 8 for all the PMO configuration op
298. active until the channel completes its buffer transfer either by an expired byte count or an EOP input In the demand data transfer mode a buffer transfer is suspended by deactivating the channel request signal Because you can not deactivate the internal channel request signal before the end of a buffer transfer you cannot use software requests with demand data transfer mode DMA Software Request write format Expanded Addr 009 DMASRR ISA Addr 0009H Reset State 00H 7 0 SR 0 CS Bit Bit Number Mnemonic Function 7 3 Reserved These bits are undefined for compatibility with future devices do not modify these bits 2 SR Software Request Setting this bit generates a software request for the channel specified by bit 0 When the channel s buffer transfer completes this bit is cleared 1 0 Must be 0 for correct operation 0 CS Channel Select 0 The selection for bit 2 affects channel 0 1 The selection for bit 2 affects channel 1 Figure 12 27 DMA Software Request Register DMASRR write format 12 42 intel DMA CONTROLLER Read DMASRR to see whether a software request for a particular channel is pending Each re quest bit is cleared upon Terminal Count or external When in auto initialize mode both bits are cleared when a Terminal Count or external EOP occurs
299. ad Reading this register clears this bit 0 DCTS Delta Clear to Send When set this bit indicates that the CTSn input has changed state since the last time this register was read Reading this register clears this bit Figure 11 22 Modem Status Register MSRn 11 81 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 11 3 12 Scratch Pad Register SCRn SCRn is available for use as a scratch pad Writing and reading this register has no effect on SIOn operation Scratch Pad SCRO SCR1 SCRO SCR1 Expanded Addr F4FFH F8FFH read write ISA Addr O3FFH 2 Reset State XXH XXH 7 0 SP7 SP6 SP5 SP4 sP3 SP2 SP1 SPO Bit Bit Number Mnemonic Function 7 0 SP7 0 Writing and reading this register has no effect on SIOn operation Figure 11 23 Scratch Pad Register SCR 11 4 PROGRAMMING CONSIDERATIONS Consider the following when programming the SIO The divisor latch low register DLLz is multiplexed with the receive and transmit buffer registers RBRn and TBRn and the divisor latch high register DLHz is multiplexed with the interrupt enable register IERz Bit 7 of the serial line control register LCRn controls which register is accessed The SIO contains four status signals receiver line status receive buffer full transmit buffer empty and modem status You can connect OR these signals to t
300. ad back commands it ignores all but the first command the count status that the core reads is the count status latched from the first read back command see Table 10 6 Table 10 6 Results of Multiple Read back Commands Without Reads Command Sequence Read back Command Command Result 1 Latch counter 0 s count and status Counter 0 s count and status latched 2 Latch counter 1 s status Counter 1 s status latched Latch counter 2 and 1 s status Counter 2 s status latched counter 1 s status command ignored because command 2 already latched its status Latch counter 2 s count Counter 2 s count latched Latch counter 1 s count and status Counter 1 s count latched counter 1 s status command ignored because command 2 already latched its status 6 Latch counter 0 s count Counter 0 s count command ignored because command 1 already latched its count 10 4 PROGRAMMING CONSIDERATIONS Consider the following when programming the TCU The 16 bit counters are read and written a byte at a time The control word format of TMRCON selects whether you read or write the least significant byte only most significant byte only or least significant byte then most significant byte this is called the counter s read write selection You must read and write the counters according to their programmed read write selections When you program a counter for the two byte read or write selection you must read or wri
301. ag If a one is written to ROE the one is ignored and ROE retains its previous value 2 RHBF Receive Holding Buffer Full read only bit The receiver sets this bit when the receive shift register contents have been transferred to the receive buffer Reading the buffer clears this bit 1 RIE Receive Interrupt Enable 0 Clearing this bit prevents the Interrupt Control Unit from sensing when the receive buffer is full 1 Setting this bit connects the receiver buffer full internal signal to the Interrupt Control Unit 0 Receiver Enable 0 Clearing this bit disables the receiver 1 Setting this bit enables the receiver 13 22 Figure 13 20 SSIO Control 1 Register SSIOCON1 intel SYNCHRONOUS SERIAL UNIT 13 3 7 SSIO Control 2 Register SSIOCON2 Use the control bits and RXMM in SSIOCON to put the transmitter or receiver mas ter or slave mode The AUTOTXM bit is used to determine if the TEN bit controls the transmit ting of the data SSIO Control 2 Expanded Addr F488H SSIOCON2 ISA Addr read write Reset State 00H 7 0 AUTOTXM TXMM RXMM Bit Bit Number Mnemonic Function 7 3 Reserved These bits are undefined for compatibility with future devices do not modify these bits 2 AUTOTXM Automatic Transmit off mode for master mode 0 Clearing this bit puts the TEN bit into normal operation 1 Setting thi
302. al CTS n bit In internal connection mode setting this bit activates the internal CTSn signal and the RTSn pin clearing this bit deactivates the internal CTSn signal and the RTSn pin In standard mode setting this bit activates the RTSn pin clearing this bit deactivates the RTSn pin Note that pin is inverted from bit 0 DTR Data Terminal Ready The function of this bit depends on whether the SIOn is in diagnostic mode MCRn 4 1 internal connection mode or standard mode In diagnostic mode setting this bit activates the internal DSRn signal clearing this bit deactivates the internal DSRn signal In internal connection mode setting this bit activates the internal DSRn and DCDn signals and the DTRn pin clearing this bit deactivates the internal DSRn and DCDn signals and the DTRn pin Note that pin is inverted from bit In standard mode setting this bit activates the DTRn pin clearing this bit deactivates the DTRn pin Note that pin is inverted from bit Figure 11 21 Modem Control Register MCRn 11 30 intel ASYNCHRONOUS SERIAL UNIT 11 3 11 Modem Status Register MSRn Read to determine the status of the modem control input signals The upper four bits reflect the current state of the modem input signals and the lower four bits indicate whether the inputs except for RI have changed state since the last time this register was read These lower four bits are reset to
303. al Connections 0 Connects the SIO1 modem input signals to the package pins 1 Connects the SIO1 modem input signals internally 6 SOM SIO0 Modem Signal Connections 0 Connects the SIOO modem input signals to the package pins 1 Connects the SIOO modem input signals internally 5 3 Reserved These bits are undefined for compatibility with future devices do not modify these bits 2 SSBSRC SSIO Baud rate Generator Clock Source 0 Connects the internal PSCLK signal to the SSIO baud rate generator 1 Connects the internal SERCLK signal to the SSIO baud rate generator 1 S1BSRC SIO1 Baud rate Generator Clock Source 0 Connects the COMCLK pin to the SIO1 baud rate generator 1 Connects the internal SERCLK signal to the SIO1 baud rate generator 0 SOBSRC SIO0 Baud rate Generator Clock Source 0 Connects the COMCLK pin to the SIOO baud rate generator 1 Connects the internal SERCLK signal to the SIOO baud rate generator D 57 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel D 58 SSIOBAUD SSIO Baud rate Control Expanded Addr F484H Number Mnemonic SSIOBAUD ISA Addr read write Reset State 00H 7 0 BEN BV6 BV5 BV4 BV3 BV2 BV1 BVO Bit Bit Function 7 BEN Baud rate Generator Enable Setting this bit enables the baud rate generator Clearing this bit disables the baud rate generator clears t
304. al bus master requests the bus using the HOLD input pin then the arbiter asserts the HLDA output 6 35 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 6 5 1 HOLD HLDA Timing To gain control of the local bus the requesting bus master drives the HOLD input active This signal can be asynchronous to the processor s CLK2 input The processor responds by completing its current bus cycle deasserting WR RD LBA SMIACT UCS CS6 0 and REFRESH and three stating all other bus outputs except HLDA effectively removing itself from the bus driving HLDA active to signal the requesting bus master that it may take control of the bus The requesting bus master must maintain HOLD active until it no longer needs the bus When HOLD goes low the processor drives HLDA low and starts a bus cycle if one is pending For valid system operation the requesting bus master must not take control of the bus until it re ceives the HLDA signal and must remove itself from the bus before deasserting the HOLD signal Setup and hold times relative to CLK2 for both rising and falling transitions of the HOLD signal must be met If the internal refresh control unit is used the HLDA signal may drop while an external master has control of the bus in which case the external bus master may or may not drop HOLD to allow the processor to perform the refresh cycle If the latter occurs the memory device s may lose data because the refresh cyc
305. alue of the WDT down counter Software can read them to determine the current count value Any reload event reloads these registers with the contents of WOTRLDH and WDTRLDL WDTRLDH WDTRLDL read write OF4COH OF 4C2H WDT Reload Value Write the reload value to these registers using two word writes After a lockout sequence is issued these registers cannot be written again until after a device reset A reload event each WDT mode has its own refer to Sections 17 2 2 through 17 2 4 reloads WDTCNTH and WDTONTL with the contents of these registers WDTSTATUS read write OFACAH WDT Status This register contains one read only bit WDTEN that indicates whether watchdog mode is enabled and two read write bits that control bus monitor mode and the WDT clock A lockout sequence sets the WDTEN bit and clears the two read write bits disabling bus monitor mode and enabling the WDT clock After a lockout sequence is issued a write to this register has no effect unless the device is reset Software can read this register to determine the current status of the WDT and unless a lockout sequence has been issued can set the BUSMON bit to enable bus monitor mode or set the CLKDIS bit to disable the WDT PWRCON read write OF800H Power Control register This register holds the WDTRDY bit that is used to enable disable internal READY generation for the WDT Bus Monitor mode 17 7 Intel386 EX E
306. am Entering and Leaving Powerdown Mode 8 11 Reset Synchronization 8 12 Interrupt Control Unit Configuration cene 9 3 Methods for Changing the Default Interrupt 9 7 Interrupt Process Master Request from Non slave Source 9 11 Interrupt Process Slave Request zen eet e i dotate Geb Interrupt Process Master Request from Slave Source Linileverehuiese eur S Port Configuration Register ANON CN ase ae a Interrupt Configuration Register INTCFG louie deg tie bct rte geh ee EE 9 19 Initialization Command Word 1 Register ICW1 sese 9 20 Initialization Command Word 2 Register 9 21 Initialization Command Word Register ICW3 9 22 Initialization Command Word Register ICW3 9 23 Initialization Command Word 4 Register 9 24 Operation Command Word 1 emen 9 25 Operation Command Word 2 emen 9 26 Operation Command Word 3 9 27 Poll Status Byte POLL ert elei eee ipei nini Interrupt Acknowledge 9 29 Spurious Interr pts 1 cicer rrt ttt leere eiecerunt dh lee aerei ra 9 30 Cascading External 82C59A I
307. and is listed in a subject catalog The first time you use Fax Back you should order the appropriate subject catalogs to get a complete list of document order numbers Catalogs are updated twice monthly In addition daily update catalogs list the title sta tus and order number of each document that has been added revised or deleted during the past eight weeks To receive the update for a subject catalog enter the subject catalog number fol lowed by a zero For example for the complete microcontroller and flash catalog request docu ment number 2 for the daily update to the microcontroller and flash catalog request document number 20 The following catalogs and information are available at the time of publication 1 Solutions OEM subscription form Microcontroller and flash catalog Development tools catalog Systems catalog Multimedia catalog De Te 249 Multibus and iRMX software catalog and BBS file listings intel GUIDE TO THIS MANUAL 7 Microprocessor PCI and peripheral catalog 8 Quality and reliability and change notification catalog 9 iAL Intel Architecture Labs technology catalog 1 5 2 Bulletin Board System BBS The bulletin board system BBS lets you download files to your computer The application BBS has the latest ApBUILDER software hypertext manuals and datasheets software drivers firm ware upgrades code examples application notes and utilities and quality and reliability data The system
308. and receive serial data Chapter 12 DMA Controller describes how the enhanced direct memory access controller allows internal and external devices to transfer data directly to and from the system and explains how bus control is arbitrated Chapter 13 Synchronous Serial I O SSIO Unit explains how to transmit and receive data synchronously Chapter 14 Chip select Unit explains how to use the chip select channels to access vari ous external memory and I O devices Chapter 15 Refresh Control Unit describes how the refresh control unit generates peri odic refresh requests and refresh addresses to simplify the interface to dynamic memory devices Chapter 16 Input Output Ports describes the general purpose I O ports and explains how to configure each pin to serve either as an I O pin or as a pin controlled by an internal peripheral Chapter 17 Watchdog Timer Unit explains how to use the watchdog timer unit as a soft ware watchdog bus monitor or general purpose timer Chapter 18 JTAG Test logic Unit describes the independent test logic unit and explains how to test the device logic and board level connections Appendix A Signal Descriptions describes the device pins and signals and lists pin states after a system reset and during powerdown idle and hold Appendix B Compatibility with PC AT Architecture describes the ways in which the device is compatible with the sta
309. ansfer mode is useful when you need to transfer data between multiple requesters and targets NOTE If a channel does not contain new transfer information at the end of its buffer transfer the channel becomes idle ending the chaining process it must be reprogrammed before it can perform another buffer transfer The Chaining Buffer Transfer Mode is entered from the Single Buffer Transfer Mode The mode registers should be programmed first with all of the transfer modes defined as if the channel were to operate in the Single Buffer Transfer Mode The channel s base and current registers are then loaded When the channel has been set up in this way and the chaining interrupt service routine is in place the Chaining Buffer Transfer Mode can be entered by programming the Chaining reg ister Chaining Register DMACHR on page 12 47 describes this process 12 12 intel DMA CONTROLLER The DMAINT signal is active immediately after the Chaining Process has been entered as the channel then perceives the Base Registers to be empty and in need of reloading It is important to have the interrupt service routine in place at the time the Chaining Process is entered The inter rupt request is removed when the most significant byte of the Base Target Address is loaded NOTE Since the most significant byte of the Base Target Address only exists in OFXXXH I O address space the Chaining Buffer Transfer Mode cannot be used in a DOS Compatible only m
310. aracter SetEXRegWord SSIOTBUF Use Polled SSIO receiver function to receive character while input z input SSerialReadWord SSIO SLAVE SerialWriteChar SIO 0 BYTE input Print to screen eK RR RR RRR KARR IIR A AAR IIR AA AR 13 33 intel 14 CHIP SELECT UNIT 14 CHIP SELECT UNIT The Chip select Unit CSU of the processor can be used to eliminate external address and bus cycle decoders in your system The chip selects generated by this unit can simplify external glue logic by providing signals that can be connected directly to the chip enable inputs of external memory and I O devices If a particular device or address region does not require a chip enable signal a chip select region can be programmed only to enable termination of accesses to that region A chip select region can also be programmed to generate a chip enable signal and terminate accesses to that region The chip select unit provides eight signals or channels allowing direct access to up to eight de vices or address regions You can individually configure the channels for compatibility with a va riety of devices Each channel can operate in either 16 bit or 8 bit bus mode generate up to 31 wait states and either terminate a bus cycle automatically or wait for an external ready signal This chapter is organized as follows Overview see below CSU Operation page 14 2 Register Definitions pa
311. are represented by the port abbreviation a period and the pin number e g P1 0 P1 1 1 3 SPECIAL TERMINOLOGY The following terms have special meanings in this manual Assert and Deassert DOS I O Address The terms assert and deassert refer to the act of making a signal active and inactive respectively The active polarity high low is defined by the signal name Active low signals are designated by a pound symbol suffix active high signals have no suffix To assert RD is to drive it low to assert HOLD is to drive it high to deassert RD is to drive it high to deassert HOLD is to drive it low Integrated peripherals that are compatible with PC AT system architecture can be mapped into DOS or PC AT addresses O3FFH In this manual the terms DOS address and PC AT address are synonymous Expanded I O Address peripheral registers reside at I O addresses PC AT Address Processor and CPU PC AT compatible integrated peripherals can also be mapped into DOS or PC AT address space 0H 03FFH Integrated peripherals that are compatible with PC AT system architecture can be mapped into PC AT or DOS addresses O3FFH In this manual the terms DOS address and PC AT address are synonymous Processor refers to the Intel386 EX processor including the integrated peripherals CPU refers to the processor core which is based on the static Intel386 SX processor intel GUIDE TO THI
312. at the package pins 1 Selects the timer control unit signals TMROUT2 2 and TMRGATE2 at the package pins 4 PM4 Pin Mode 0 Selects DACKO at the package pin 1 Selects CS5 at the package pin 3 PM3 Pin Mode 0 Selects EOP at the package pin 1 Selects CTS1 at the package pin 2 PM2 Pin Mode 0 Selects DACK1 at the package pin 1 Selects TXD1 at the package pin 1 PM1 Pin Mode 0 Selects SRXCLK at the package pin 1 Selects DTR1 at the package pin 0 PMO Pin Mode 0 Selects SSIOTX at the package pin 1 Selects RTS1 at the package pin Figure 14 4 Pin Configuration Register PINCFG 14 15 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL 14 4 2 Port 2 Configuration Register P2CFG Use P2CFG bits 4 0 to connect the CS4 0 signals to package pins Port 2 Configuration Expanded Addr F822H P2CFG ISA Addr read write Reset State 00H 7 0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PMO Bit Bit Functi Number Mnemonic 7 7 0 Selects 2 7 atthe package 1 Selects CTSO at the package 6 PM6 Pin Mode 0 Selects P2 6 at the package pin 1 Selects TXDO at the package pin 5 PM5 Pin Mode 0 Selects P2 5 at the package pin 1 Selects RXDO at the package pin 4 PM4 Pin Mode 0 Selects P2 4 at the package pin 1
313. ator When set this bit indicates that the RIn input has changed from a low to a high state since the last time this register was read Reading this register clears this bit DDSR Delta Data Set Ready When set this bit indicates that the DSRn input has changed state since the last time this register was read Reading this register clears this bit DCTS Delta Clear to Send When set this bit indicates that the CTSn input has changed state since the last time this register was read Reading this register clears this bit D 39 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL D 37 OCW1 MASTER AND SLAVE 0 Enables interrupts on the corresponding IR signal 1 Disables interrupts on the corresponding IR signal NOTE Setting the mask bit does not clear the respective interrupt pending bit Operation Command Word 1 master slave OCW1 master and slave Expanded Addr F021H FOA1H read write ISA Addr 0021H OOA1H Reset State XXH XXH 7 0 M7 M6 M5 M4 M3 M2 M1 MO Bit Bit 5 Number Mnemonic Function 7 0 M7 0 Mask IR set NOTE The 8259A must be initialized before it can be used After reset the 8259A register states are undefined The 8259A modules must be initialized before the IF flag in the core FLAG register is D 40 intel SYSTEM REGISTER QUICK REFERENCE D 38 OCW2 MASTER AND SLAVE
314. bedded design There are several third party BIOS vendors that support the Intel386 EX processor Embedded PC features supported include PCMCIA Flash Advanced Power Management APM Source Remote Floppy OEM Configurable and Video Keyboard rerouted through the serial port For a complete list of vendors and their features call the Intel BBS as described in Electronic Support Systems on page 1 6 A good evaluation vehicle is the EV386EX Evalua tion Board which comes with five different third party BIOS demonstrations New and updated demonstrations are also available on the Intel BBS B 2 2 Embedded Disk Operating System DOS The DOS operating system offers functions for I O communication floppy hard disk video key board program handling memory management and network support these are available to the Intel386 EX embedded processor user Embedded PC DOS features include Advanced Power Management APM support ROMable Source Disk Compression and XIP A variety of third party DOS vendors support the Inte1386 EX processor For a complete list of vendors and their features call the Intel BBS The EV386EX Evaluation Board also provides a variety of DOS demonstrations New and updated DOS dem onstrations are also available on the Intel BBS B 2 3 Microsoft Windows The Intel386 EX processor can run both Microsoft Windows 3 1 and Microsoft ROM Windows Both require RAM and disk space to execute Other hardware such as a key
315. below and shown in Figure 10 8 1 After a control word write OUTn is driven high 2 count is loaded on CLKINn pulse following one of these events e A write to a control word followed by a write to count A gate trigger The counter reaches one On each succeeding CLKINn pulse the count is decremented When the count reaches one OUT is driven low On the following CLKINn pulse OUTn is driven high and the count is reloaded Qv y 59 The process is repeated from step 3 10 10 intel TIMER COUNTER UNIT Control Word 14H Count 3 Writes to Counter n CLKINn 1 0001 2313 01 Figure 10 8 Mode 2 Basic Operation Figure 10 9 shows suspending the counting sequence A low level on GATEn causes the counter to suspend counting The count remains unchanged and OUTn is immediately driven or stays high If the GATEn goes low when OUTn is low then OUT is immediately driven high A ris ing edge on the GATEn causes the counter to be reloaded with the count A high level on GATEn resumes counting Control Word 14H Count 3 Writes to Counter n CLKINn GATEn OUTn Count 0003 A2398 01 Figure 10 9 Mode 2 Disabling the Count 10 11 Intel386 EX EMBEDDED PROCESSOR USER S MANUAL intel Figure 10 10 shows writing a new count The counter loads the new count after the counter reach es one When the counter receives a gate trigger after a n
316. ber In some cases the letter B is added for clarity Units of Measure following abbreviations are used to represent units of measure A amps amperes Gbyte gigabytes Kbyte kilobytes KQ kilo ohms mA milliamps milliamperes Mbyte megabytes MHz megahertz ms milliseconds mW milliwatts ns nanoseconds pF picofarads W watts V volts uA microamps microamperes uF microfarads us microseconds uW microwatts 1 3 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Register Bits Register Names Signal Names When the text refers to more that one bit the range may appear as two numbers separated by a colon example 7 0 or 15 0 The first bit shown 7 or 15 in the example is the most significant bit and the second bit shown 0 is the least significant bit Register names are shown in upper case If a register name contains lowercase italic character it represents more than one register For example Pn CFG represents three registers P2CFG and P3CFG Signal names are shown in upper case When several signals share a common name an individual signal is represented by the signal name followed by a number while the group is represented by the signal name followed by a variable For example the lower chip select signals are named CSO CS1 CS2 and so on they are collectively called CSn A pound symbol appended to a signal name identifies an active low signal Port pins
317. ber of wait states inserted into the bus cycle and defines heth IR i i i UCSADL 0F438H whether an external READY is required to terminate the bus cycle read write CSOMSKH 0 406 Chip select High Mask CS1MSKH OF40EH Defines the upper 10 bits of the chip select channel mask The processor E uses a chip select s channel mask to determine the size of the channel s i lock if th i CSAMSKH 0F426H active address block and if the address block is repeated CS5MSKH 0 42 CS6MSKH OF436H UCSMSKH 0 4 read write CSOMSKL OF404H Chip select Low Mask CS1MSKL OF40CH Defines the lower 5 bits of the chip select channel mask and enables the CS2MSKL 0 414 output pin CS3MSKL 0F41CH CS4MSKL OF424H CS5MSKL 0 42 CS6MSKL 0F434H UCSMSKL 0 4 read write 14 14 intel CHIP SELECT UNIT 14 4 1 Pin Configuration Register PINCFG Use PINCFG bits 6 and 4 to connect the CS6 and CS5 signals to package pins Pin Configuration Expanded Addr F826H PINCFG ISA Addr read write Reset State 00H 7 0 PM6 PM5 PM4 PM3 PM2 PM1 PMO Bit Bit Number Mnemonic Function 7 Reserved This bit is undefined for compatibility with future devices do not modify this bit 6 PM6 Pin Mode 0 Selects CS6 at the package pin 1 Selects REFRESH at the package pin 5 PM5 Pin Mode 0 Selects the coprocessor signals PEREQ BUSY and ERROR Z
318. bes the signals associated with the BIU Table 6 1 Bus Interface Unit Signals Sheet 1 of 2 Signal Device Pin or Internal Signal only Description 25 Device pins Address Bus Outputs physical memory or I O addresses These signals are valid when ADS is active and remain valid until the next T1 T2P or Ti ADS Device pin Address Strobe Indicates that the processor is driving a valid bus cycle definition and address The processor is driving W R D C M IO WR RD UCS CS6 0 LOCK REFRESH A25 1 BHE and BLE on its pins BHE BLE Device pins Byte Enable Outputs Indicates which byte of the 16 bit data bus of the processor is being transferred BHE BLE Output 0 0 word transfer 0 1 upper byte D15 8 transfer 1 0 lower byte D7 0 transfer 1 1 refresh cycle BS8 Device pin Bus Size Indicates that the currently addressed device is an 8 bit device D15 0 Device pins Data Bus Inputs data during memory read I O read and interrupt acknowledge cycles outputs data during memory write and I O write cycles During reads data is latched at the falling edge of phase 2 coincides with rising edge of PH1 of T2 T2P or T2i when READY is sampled active During writes this bus is driven during phase 2 of T1 and T1P and remains active until phase 2 of the next T1 T1P or Ti LBA Device pin Local Bus Access Indicates that the processor p
319. bit program can check this bit to see whether it has access to the expanded I O space registers Clearing the ESE bit disables the ex panded I O space This can be done by a byte write with a value of 0 to I O address 23H This again locks the REMAPCFG register and makes it read only 4 8 intel SYSTEM REGISTER ORGANIZATION 4 6 ADDRESSING MODES Combinations of the value of ESE bit and the individual remap bits in the REMAPCFG register yield four different peripheral addressing modes for I O address decoding 4 6 1 DOS compatible Mode DOS compatible mode is achieved by clearing ESE and all the peripheral remap bits In this mode all PC AT compatible peripherals are mapped into the DOS I O space Only address lines A9 0 are decoded for internal peripherals Accesses to PC AT compatible peripherals are valid while all other internal peripherals are inaccessible see Figure 4 5 This mode is useful for accessing the internal timer interrupt controller serial I O ports DMA controller in a DOS compatible environment 4 9 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 3FFH On chip UART 0 On chip UART 1 EN B On chip 8259A 2 On chip Timer REMAPCFG 23H Register 22H F000H On chip 8259A 1 Expanded I O Space Note On chip DMA Shaded area indicates that 0H expanded I O space peripherals DOS I O Space are not accessible A2495 02 Figure 4 5 DOS Compatible Mode intel S
320. bit combinations in a nonsequential order the equation above must never be less than 128 to ensure proper refresh of all the rows in a DRAM device that has less than 128 rows Refresh Clock Interval Expanded Addr F4A2H RFSCIR ISA Addr read write Reset State 0000H 15 8 RC9 RC8 7 0 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RCO Bit Bit Number Mnemonic Function 15 10 Reserved These bits are undefined for compatibility with future devices do not modify these bits 9 0 RC9 0 Refresh Counter Value Write the counter value to these ten bits The interval counter counts down from this value When the interval counter reaches one the control unit initiates a refresh request provided it does not have a request pending The counter value is a function of DRAM specifications and processor frequency see the equation above Figure 15 2 Refresh Clock Interval Register RFSCIR 15 7 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 15 4 2 Refresh Control Register RFSCON Use RFSCON to enable and disable the refresh control unit and to check the current interval counter value Refresh Control Expanded Addr F4A4H RFSCON ISA Addr read write Reset State 0000H 15 8 REN CV9 CV8 7 0 CV7 CV6 CV5 CV4 CV2 CV1 CVO Bit Bit Function Number Mnemonic
321. board controller real time clock and video controller may be required For more information on implementing ROM Windows refer to Mobile Intel486 SX CPU PC Designs Using FlashFile Components Or der Number 292149 5 intel C EXAMPLE CODE HEADER FILES APPENDIX C EXAMPLE CODE HEADER FILES This appendix contains the header files called by the code examples that are included in several chapters of this manual Section C 1 contains the register definitions for each code routine Sec tion C 2 contains the variable definitions C 1 REGISTER DEFINITIONS FOR CODE EXAMPLES 80386EX REGISTER DEFINITIONS define SetEXRegWord reg val outpw reg val define _SetEXRegByte reg val outp reg val define _ReadEXRegWord val reg val inpw define _GetEXRegByte reg inp reg define _GetEXRegWord reg inpw reg REMAP ADDRESSING Registers define REMAPCFGH 0x0023 define REMAPCFGL 0x0022 define REMAPCFG 0x0022 INTERRUPT CONTROL REGISTERS SLOT 15 ADDRESSES define ICW1M OxF020 define ICW1S OxFOAO define ICW2M OxF021 define ICW2S OxF0A define ICW3M 0 021 define ICW3S 0 1 define ICW4M 0 021 define ICW4S OxF0A define OCW1M 0 021 define OCW1S 0 1 define OCW2M 0 020 define OCW2S OxFOAO define OCW3M 0 020 define OCW3S OxFOAO INTERRUPT CONTROL REGISTERS SLOT 0 ADDRESSES define ICW1MDOS 0x0020 define ICW1SDOS 0
322. cal 2 1 Architectural overview 2 1 2 4 Assert defined 1 4 Asynchronous serial I O unit See Serial I O unit Automatic end of interrupt AEOI mode 9 9 B Baud rate generator 11 4 11 5 13 5 13 6 BIU See Bus interface unit Block diagram clock and power management unit 8 2 DMA unit 12 2 I O port 16 2 JTAG test logic unit 18 2 SIO unit 11 2 baud rate generator clock 11 4 modem control signals 11 29 receiver 11 9 transmitter 11 7 INDEX SSIO unit 13 2 13 3 baud rate generator clock 13 5 timer counter unit 10 2 watchdog timer unit 17 2 BOUND 18 2 Boundary scan register 18 1 Built in self test 8 12 Bulletin board system BBS 1 7 Bus arbiter register addresses 4 15 D 1 Bus arbiter configuration 5 3 Bus control arbitration 12 9 Bus cycle length adjustments for overlapping chip select regions 14 11 14 12 Bus interface pins 6 3 Bus interface unit 3 4 6 1 6 37 address bus 6 1 bus control pins 6 2 bus cycles 6 13 6 33 BS8 6 31 6 33 halt shutdown 6 26 6 27 interrupt acknowledge 6 23 6 25 pipelined 6 19 6 23 read 6 13 6 14 refresh 6 28 6 30 write 6 16 6 18 bus lock 6 34 6 35 LOCK signal duration 6 35 locked cycle activators 6 34 locked cycle timing 6 34 bus operation 6 5 6 14 bus state diagram 6 8 6 20 bus states 6 7 6 8 bus status definitions 6 5 data bus 6 1 transfers and operand alignment 6 9 HOLD HLDA 6 20 6 35 departures from PC AT architecture B 4 HOLD signal late
323. ccessed Figure 9 13 and Figure 9 15 1 ICW1 register is accessed 3 LS Level Edge Sensitive 0 Selects edge triggered IR input signals 1 Selects level sensitive IR input signals All internal peripherals interface with the 82C59As in edge triggered mode only This is compatible with the PC AT bus specification Each source signal initiates an interrupt request by making a low to high transition External peripherals interface with the 8259As in edge triggered or level sensitive mode The modes are selected for the device not for individual interrupts NOTE If an internal peripheral interrupt is used the 8259A that the interrupt is connected to must be programmed for edge triggered interrupts 2 1 Clear these bits to guarantee device operation 0 Set this bit to guarantee device operation NOTE 82C59A must be initialized before it can be used After reset the 82C59A register states are undefined The 82C59A modules must be initialized before the IF flag in the core FLAG register is set All peripherals that use interrupts connected to the ICU must be initialized before initializing the ICU D 28 intel SYSTEM REGISTER QUICK REFERENCE D 24 ICW2 MASTER AND SLAVE Initialization Command Word 2 master slave ICW2 master and slave Expanded Addr F021H FOA1H writ
324. cle is always an internal cycle and the second may be internal or external Therefore READY is generated internally for the first cycle and for the second cycle if the interrupt request is from one of the internal 82C59A modules If the interrupt is from a cascaded external 82C59A external logic must assert READY to terminate the second cycle The internal Chip select Unit can not generate READY for the second interrupt acknowledge cycle BUS INTERFACE UNIT Idle Interrupt Idle Interrupt Previous c c SOE 858 ef c T a 44 E fat gt a 5 sis c See 85 595 o lt o up CLK2 5 c lt 8 6 Li rs lt 5 SE a as A2490 03 Figure 6 9 Interrupt Acknowledge Cycles 6 25 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 6 3 5 Halt Shutdown Cycle The halt condition occurs in response to a HALT instruction The shutdown condition occurs when the processor is processing a double fault and encounters a protection fault the processor cannot recover and therefore shuts down Externally a shutdown cycle differs from a halt cycle only in the resulting address bus outputs The sequence of signals for a halt cycle is as follows 1 6 26 As with other bus cycles a halt or shutdown cycle is initiated by driving the address and status
325. clocks and the peripheral clocks Refresh control unit The module that simplifies the interface between the processor and DRAM components by providing the necessary bus control and timing for refresh operations Register bits that are not used in this device but may be used in future implementations Avoid any software dependence on these bits The term set refers to the value of a bit or the act of giving it a value If a bit is set its value is 1 setting a bit gives it a 1 value Serial input output unit The internal peripheral that allows the system to communicate with external peripheral devices and modems System management mode The hardware and software enhancement that reduces system power consumption by allowing the device to execute specific routines for power management A 32 Kbyte memory partition 38000H 3FFFFH used for SMM The upper 512 bytes GFE00H 3FFFFH are reserved for the CPU and must reside in the remainder of the partition 1s used for user supplied driver code and may reside in read only storage Synchronous serial input output unit The internal peripheral that provides 16 bit bidirectional serial intel State Time or State TAP TCU Test logic Unit UART WDT GLOSSARY communications The transmitter and receiver can operate independently with different clocks to provide full duplex communication The basic time unit of the device the combined period of
326. control word D 65 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Timer n Status Format Expanded Addr F040H F041H TMRn n 0 2 F042H ISA Addr 0040H 0041H 0042H Reset State XXH 7 0 OUTPUT NULCNT RW1 RWO M2 M1 MO CNTFMT Bit Bit r Number Mnemonic Function 7 OUTPUT Output Status This bit indicates the current state of the counter s output signal 0 OUTn is low 1 OUT is high 6 NULCNT Count Status This bit indicates whether the latest count written to the counter has been loaded Some modes require a gate trigger before the counter loads new count values 0 the latest count written to the counter has been loaded 1 acount has been written to the counter but has not yet been loaded 5 4 RW1 0 Read Write Select Status These bits indicate the counter s programmed read write selection 00 Never occurs 01 read write least significant byte only 10 read write most significant byte only 11 read write least significant byte first then most significant byte 3 1 M2 0 Mode Status These bits indicate the counter s programmed operating mode 000 mode 0 001 mode 1 X10 mode 2 X11 mode 100 mode 4 101 2 mode 5 X is a don t care 0 CNTFMT Counter Format Status This bit indicates the counter s programmed count format 0 binary 16 bits 1 binary coded decimal 4 decades D 66 intel SYSTEM
327. ctively For math coprocessor cycles is always LOW and A23 always HIGH The math coprocessor input CMDO is connected to the A2 output The Intel386 EX embedded processor generates address 8000F8H when writing a command and address 8000 or 8000FEH treated as 8000 by the Intel387 SX Math Coprocessor when writing or reading data It does not generate any other addresses during Intel387 SX Math Coprocessor bus cycles CAUTION A chip select signal could go active during coprocessor cycles if a match for the lower 16 bits of address is found in one of the chip select regions of the Chip select Unit This can happen because only the lower 16 bits are decoded by the Chip select Unit during I O cycles The READY O pin of the coprocessor must be sent through a buffer to prevent the Intel386 EX processor and coprocessor from simultaneously driving the READ Y pin The buffer is enabled using the LBA pin During internal bus cycles the LBA pin is asserted and the Intel386 EX processor provides the READY signal In a coprocessor access the LBA is deasserted the external buffer is enabled and the coprocessor provides the READY 7 signal to the Intel386 EX processor 6 6 1 2 Software Considerations To enable math coprocessor support in the Intel386 EX processor you must set the MP Math Present bit and clear the EM Coprocessor Emulation bit in the Machine Status Word lower half of the CRO register in the core This can be d
328. cy CLK2 2 disabled stopped D 70 intel E INSTRUCTION SET SUMMARY APPENDIX E INSTRUCTION SET SUMMARY This appendix provides reference information for the Intel386 processor family instruction set The appendix is organized as follows Instruction Encoding and Clock Count Summary see below Instruction Encoding page E 22 E 1 INSTRUCTION ENCODING AND CLOCK COUNT SUMMARY To calculate elapsed time for an instruction multiply the instruction clock count as listed in Table E 1 by the processor clock period e g 62 5 ns for 16 MHz Instruction clock count assumptions The instruction has been prefetched decoded and is ready for execution Buscycles do not require wait states There are no local bus HOLD requests delaying processor access to the bus No exceptions are detected during instruction execution When an effective address is calculated it does not use two general register components One register scaling and displacement can be used within the clock counts shown However when the effective address calculation uses two general register components add 1 clock to the clock count shown Instruction clock count notation When two clock counts are given the smaller refers to a register operand and the larger refers to a memory operand n number of times repeated m number of components in the next instruction executed where the entire displacement Gf any
329. cycles 6 2 3 Data Bus Transfers and Operand Alignment The processor can address up to 64 Mbytes 22 bytes addresses 0000000H 3FFFFFFH of physical memory and up to 64 Kbytes 21 bytes addresses 0000H FFFFH of I O The device maintains separate physical memory and I O spaces A programmer views the address space memory or I O as a sequence of bytes Words consist of 2 consecutive bytes Doublewords consist of 4 consecutive bytes However in the system hardware address space is implemented in 2 byte portions When the processor reads a word it accesses a byte from each portion of the 16 bit data bus The processor automatically translates the programmer s view of consecutive bytes into this hardware imple mentation Memory and I O spaces are organized physically as sequences of 16 bit words 225 16 bit mem ory locations and 25 16 bit I O ports maximum Each word starts at a physical address that is a multiple of 2 and has 2 individually addressable bytes at consecutive addresses Pins A25 1 correspond to the most significant bits of the physical address these pins address words of memory The least significant bit of the physical address is used internally to activate the appropriate byte enable outputs BHE or BLE or both Data can be transferred in quantities of either 8 or 16 bits for each bus cycle of a data transfer When a data transfer can be completed in a single cycle the transfer is said to be aligned For exa
330. cycles needed and should be avoided Table 6 3 Sequence of Nonaligned Bus Transfers First Cycle Second Cycle Third Cycle Transfer Physical Type Address Address Byte Address Byte Address Byte Bus Enable Bus Enable Bus Enable word 1 4N 4 2 word 4N 3 4N 4 BLE 4N 2 BHE doubleword 4N 1 4N 4 BLE 4N BHE 4N 2 both doubleword 4N 2 4N 4 both 4N 2 both doubleword 4N 3 4N 4 both 4N 6 BLE 4N 3 BHE 6 2 4 Ready Logic A bus cycle is terminated externally by asserting the READY pin or internally by either an in ternal peripheral or the Chip select Unit s wait state logic When an access is to an internal pe ripheral the address also goes out to the external bus When an external device incorrectly decodes a match to the address and drives the READY pin contention occurs on the signal The LBA pin should be used to alleviate the possibility of contention on the READY pin The READY pin is an output of the processor whenever LBA is asserted and an input to the pro cessor whenever LBA is deasserted The LBA pin becomes active when the processor is generating the READ Y internally Figure 6 3 shows the implementation of the READY signal using the LB A signal If you wish to sim plify decoding of address space and overlap internal I O registers you need to provide external logic to monitor LBA and end the bus cycle externally when the processor generates the READY
331. d or dress or dress Virtual Mode Virtual Mode 8086 8086 Mode Mode within segment addin im ur 12 b h ined eSP 9 11000010 16 bit displacement un 2 intersegment 11001011 36 m b g n intersegment adding non 36 m b 9 h j k immed to SP 11001010 16 bit displacement Protected mode only RET to different privilege level Intersegment 72 hjkr Intersegment adding immed to SP 72 hjikr CONDITIONAL JUMPS times are jump Taken or not Taken JO jump on overflow 8 bit displacement 01110000 8 bit displacement ZEM or3 or3 SU displacement 00001111 10000000 Ful displacement fma p or3 or3 JNO Jump on not overflow 8 bit displacement 74m 74m r 01110001 8 bit displacement or3 or3 Fullgisplacement 00001111 10000001 Ful displacement LEM TEM or3 or3 JB JNAE jump on below not above or equal bit displacement 01110010 8 bit displacement fima Tan j or3 or3 Full displacement 7 7 00001111 10000010 Fulldisplacement or3 or3 JNB JAE jump on not below above or equal 8 bit displacement 01110011 8 bit displacement p eem r or3 or3 Full displacement 74m 74m r 00001 1 10000011 Full displacement or3 or3 JE JZ jump on equal zero 8 bit displacement D 74m 74m r 01110100 8 bit displacement or3 or3 Full displacement 00001111 10000100 Ful displacement Cro pL Seem or3 or3 JNE JNZ jump on not equal not zero 8 bit displacement 01110101 8 bit displacement feme r
332. d Bus Arbiter Coprocessor signals connected to package pins HOLD and HLDA not connected to package pins LOCK and PWRDOWN not connected to package pins 5 5 2 Example Design Solution The configuration register bit values for the example design are recorded in the following abbre viated register tables Blank worksheets are provided for you to use when designing your system Table 5 4 summarizes the bit selections you would need to make in the pin configuration registers to implement the example design Tables 5 5 through 5 8 summarize the bit selections you would make in the peripheral configuration registers 5 29 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Bit 4 P1CFG Value Bit P2CFG Value Bit P3CFG Value 7 0 P1 7 0 7 0 P2 7 0 7 0 P3 7 0 1 HLDA 1 2 CTSO 1 COMCLK 6 0 P1 6 0 6 0 P26 1 6 0 P3 6 0 1 HOLD 1 TXDO 1 PWRDOWN 5 O P1 5 0 5 0 2 5 1 5 0 P3 5 0 1 LOCK 1 RXDO 1 INT3 4 0 P1 4 0 4 0 P2 4 1 4 0 P3 4 0 1 RIO 1 2 CS4 1 INT2 3 0 P1 3 0 3 0 P2 3 1 3 0 P3 3 1 1 DSRO 1 CS3 1 INT1 2 0 P1 2 0 2 0 P2 2 1 2 0 P3 2 1 1 DTRO 1 CS2 1 INTO 1 0 P1 1 0 1 0 P2 1 1 1 0 P3 1 0 1 RTSO 1 CS1 1 mux 0 0 P1 0 0 0
333. d data carrier detect DCDn modem inputs Setting OUT1 activates the internal bit clearing OUT1 deactivates the internal Rin bit Setting OUT2 activates the internal DCDn bit clear OUT2 deactivates the internal DCDn bit In normal user mode bit 4 0 OUT1 has no effect and OUT2 in conjunction with INTCFG 5 6 selects internal SIO interrupt or external interrupt See Table 5 1 on page 5 8 for the configuration options 0 1 1 RTS Ready to Send The function of this bit depends on whether the SIOn is in diagnostic mode MCRn 4 1 internal connection mode or standard mode In diagnostic mode setting this bit activates the internal CTS n bit clearing this bit deactivates the internal CTS bit In internal connection mode setting this bit activates the internal CTS signal and the RTSnit pin clearing this bit deactivates the internal CTSn signal and the RTSn pin In standard mode setting this bit activates the RTS t pin clearing this bit deactivates the RTSn pin Note that pin is inverted from bit 0 DTR Data Terminal Ready The function of this bit depends on whether the SIOn is in diagnostic mode MCRn 4 1 internal connection mode or standard mode In diagnostic mode setting this bit activates the internal DSRn signal clearing this bit deactivates the internal DSRn signal In internal connection mode setting this bit activates the internal DSRn and DCDn signals and the DTRn pin clearing this bit deacti
334. d status buses Hardware can distinguish the difference between an idle cycle and an active bus cycle by the address strobe ADS signal being driven active The ADS signal remains active for only the first T state of the bus cycle while the address signals and status signals remain active until the bus cycle is terminated by an active READY signal or the bus cycle is pipelined Pipelined bus cycles are discussed in Pipelining on page 6 8 Basic bus cy cles are illustrated in Figure 6 1 The bus status signals indicate the type of bus cycle the proces sor is executing Notice that the signal combinations marked as invalid states may occur when the bus is idle and ADS is inactive 6 7 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Memory read and memory write cycles can be locked to prevent another bus master from using the local bus This allows for indivisible read modify write operations Reset Asserted READY Asserted No Request No Request READY Asserted Request Pending Request Pending Bus States T1 First clock of a non pipelined bus cycle CPU drives READY Negated new address and asserts ADS T2 Subsequent clocks of a bus cycle when has not been sampled asserted in the current bus cycle Ti Idle State The fastest bus cycle consists of two states T1 and T2 A2484 02 Figure 6 2 Simplified Bus State Diagram Does Not Include Address Pipelining or Hold states
335. d status of one or more counters After issuing the read back command you can check the counter s status by reading the counter s TMRn register After checking a counter s status you can read the counter s TMRn register again to check its count TMRO TMR1 TMR2 OF040H OF041H OF042H 0040H 0041H 0042H Status Format Read this register after issuing a read back command to check counter status Reading TMRn again accesses its read format Read Format Read this register to check counter r s count value Write Format Write this register at any time after initializing counter n to change the counter s count value 10 4 intel TIMER COUNTER UNIT 10 2 TCU OPERATION Each counter can operate in any one of six operating modes These modes are described in sec tions 10 2 1 through 10 2 6 In all modes the counters decrement on the falling edge of CLKINn In modes 0 1 4 and 5 the counters roll over to the highest count either OFFFFH for binary counting or 9999 for BCD counting and continue counting down However the state of the OUTn is only affected by the first run through the counter and does not change on subsequent runs Modes 2 and 3 are periodic modes in these modes when the counter reaches terminal count it is reloaded with the currently programmed count value To specify a counter s operating mode write to the TMRCON register s control word format Writing to this register initiates coun
336. dependent from the rest of the processor The processor requires that the JTAG unit be reset before normal operation can begin To reset the JTAG unit invert the processor RESET signal and connect this inverted RESET signal to the TRST pin 8 12 intel CLOCK AND POWER MANAGEMENT UNIT 8 4 3 Powerdown Mode and Idle Mode Considerations The wake up signals INT NMI and SMI are level sensitive inputs to the wake up circuitry The active state of any of these inputs prevents the device from entering powerdown or idle mode The refresh control unit cannot perform DRAM refreshes during powerdown Powerdown mode freezes PSCLK and SERCLK When the device exits powerdown mode the PWRDOWN signal is synchronized with CLK2 at the falling edge of PWRDOWN so that other devices in the system exit powerdown at the same internal clock phase as the processor The INTR output of the ICU cannot be masked off to the power management unit using the CLI instruction If it is necessary to mask off INTR to the power management unit all the interrupt inputs to the 82C59As must be masked This applies to both powerdown and idle modes 8 5 PROGRAMMING CONSIDERATIONS 8 5 4 Clock and Power Management Unit Code Example This section contains these software routines Set_Prescale_Value Sets the clock prescale value Enter_Idle_Mode Programs the Intel386 EX processor for idle mode Enter_Powerdown_Mode Programs the Intel386 EX processor fo
337. dge of PH2 of the T2 state after the wait states if any are programmed in the Chip select Unit have expired WRi is asynchronously deasserted as soon as READY is asserted after a small delay caused by the logic The write cycle is then terminated at the end of the T2 state The WR signal operates in this manner to ensure sufficient address and chip select hold time during write cycles required by many memory and I O devices In the first case the address and chip select hold time is approximately one CLK2 cycle 5 When READY is high wait states are added additional T2 states for nonpipelined cycles until is sampled low READY is sampled in each T2 state starting at the rising edge of PH2 to deassert the WR signal appropriately and at the end of each T2 state at the falling edge of PH2 to terminate the cycle 6 Once READY is sampled low the write cycle terminates If a new bus cycle is pending it begins on the next T state 6 17 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL T2 T2 Write Early Ready Cycle 2 Nonpipelined External T1 T2 Write Late Ready External Nonpipelined T1 CLK2 uS e S gt poc 27 G gt Lr 3 85 x o o ma I a REFRESH W R NA READY BS8 N NPs 2 16 gt 5 6 oO gt o 2 ro p 2488 02
338. diagram including the states related to pipelining During the second T state T2 of a nonpipelined read cycle cycle 2 is sampled low A bus cycle was pending internally cycle 3 and the address byte en ables and bus status signals for this pending bus cycle cycle 3 are driven during the next T2P state the first wait state of the current bus cycle The RD and WR signals do not change until READY is sampled low 6 19 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel HOLD Asserted READY Asserted HOLD Asserted Reset Asserted HOLD Negated No Request Negated Request Pending HOLD Negated READY Asserted HOLD Negated Request Pending o 205 READY Asserted 258 HOLD Negated NA Negated a 2S 58 Request Pending o9 2 3 8 sis y IB 5 ga lt 5 8 Zu x45 c Sog 8 2142 READY Asserted HOLD Negated No Request READY Negated NA Asserted HOLD Negated Request Pending READY Asserted Bus States T1 first clock of a non pipelined bus cycle HOLD Negated READY Negated No Request HOLD Asserted READY Negated Request Pending T2 subsequent clock of a bus cycle when has not been sampled active in the current bus cycle T2i subsequent clocks of a bus cycle when NA has been sampled active in the current bus cycle and there i
339. ding of 32 bit Address Mode with Byte No s i b Byte Present E 28 E 9 Encoding of 32 bit Address Mode mod r m Byte and s i b Byte Present E 29 E 10 Encoding of Operation Direction d Field ss E 30 E 11 Encoding of Sign Extend s Field eee E 30 E 12 Encoding of Conditional Test E 30 E 13 When Interpreted as Control Register 31 14 When Interpreted as Debug Register Field E 31 E 15 When Interpreted as Test Register E 31 xxiii intel GUIDE TO THIS MANUAL 1 GUIDE TO THIS MANUAL This manual describes the Inte1386TM EX Embedded Processor It is intended for use by hardware designers familiar with the principles of microprocessors and with the Intel386 processor archi tecture This chapter is organized as follows Manual Contents see below Notational Conventions page 1 3 Special Terminology page 1 4 Related Documents page 1 5 Hlectronic Support Systems page 1 6 Technical Support page 1 7 Product Literature page 1 8 11 MANUAL CONTENTS This manual contains 18 chapters and 5 appendixes a glossary and an index This section sum marizes the contents of the remaining chapters and appendixes The remainder of this chapter d
340. ding the buffer clears RHBF When the receiver is enabled it transfers the contents of the shift register to the receive buffer each time the shift register finishes shifting its current contents If the shift register finishes shifting in its cur rent contents before the old value is read from the receive buffer the receiver transfers the new value into the buffer overwriting the old value and sets the ROE flag This condition is known as a receive overflow error The receiver also has an internal receive holding buffer full signal SSRBF This signal can be connected to the DMA unit for DMA initiated transfers The SSRBF signal is also ORed with the SSTBE signal to generate the SSIOINT signal which is sent to the interrupt controller Before the SSRBF signal is ORed it is masked with the Receive Interrupt Bit RIE in the SSIOCONI reg ister These options allow you to use either an interrupt service routine or a DMA transfer to read data from the receive holding buffer 13 12 intel SYNCHRONOUS SERIAL UNIT The SSIO Unit can be operated either by using a polling method or through interrupts m Figure 13 12 shows a basic flowchart for using the polling method to receive data through the SSIO Figure 13 13 shows a basic flowchart for the Interrupt Service Routine necessary when using interrupts to receive data through the SSIO If interrupts are used follow the below sequence for initialization Initialize the SSIO Initialize t
341. dr read only Reset State 00H 7 0 TC1 TCO CH CIO Bit Bit Number Mnemonic Function 7 6 Reserved These bits are undefined 5 TC1 Transfer Complete 1 When set this bit indicates that channel 1 has completed a buffer transfer either its byte count expired or it received an EOP input This bit is set only if bit 1 of the interrupt enable register is set Reading the DMA status register DMASTS clears this bit Note In chaining mode this bit becomes a don t care 4 TCO Transfer Complete 0 When set this bit indicates that channel 0 has completed a buffer transfer either its byte count expired or it received an EOP input This bit is set only if bit 0 of the interrupt enable register is set Reading the DMA status register DMASTS clears this bit Note In chaining mode this bit becomes a don t care 3 2 Reserved These bits are undefined 1 Cit Chaining Interrupt 1 When set this bit indicates that new requester and target addresses and a new byte count should be written to channel 1 This bit is cleared when new transfer information is written to the channel Writing to the most significant byte of the target address clears this bit Note Outside chaining mode this bit becomes a don t care 0 CIO Chaining Interrupt 0 When set this bit indicates that new requester and target addresses and a new byte count should be written to channel 0 This bit is cleared when new tran
342. dy to establish a communications link DSRn It has detected a data carrier signal DCDn It has detected a telephone ringing signal RIn Itis ready to exchange data CTSn The SIOn uses its output signals to inform the modem or data set when it is ready to establish a communication link DTRn and when it is ready to exchange data RTSn The modem output signals can be internally connected to the modem input signals using the SIO configuration register In this case the modem input signals are disconnected from the pins RTSn is connected to CTSn DTRn is connected to both DSRn and DCDn and V oc is con nected RIn The SIO contains status flags that indicate the current state of the modem control input signals and status flags that indicate whether any of the modem control input signals have changed state 11 2 5 Diagnostic Mode The SIO channels provide a diagnostic mode to aid in isolating faults in the communications link In this mode data that is transmitted is immediately received This feature allows the processor to verify the internal transmit and receive data paths of an SIOn channel The diagnostic mode connections are as follows The transmitter serial output TXDn is set to a logic 1 state The receiver serial input RXDn is disconnected from the pin The transmit shift register output is looped back into the receive shift register The four modem control inputs DSRn DCDn a
343. e least 3 bit must be 0 SetEXRegByte ICW3S 0x2 Set slave ID _SetEXRegByte ICW4S 0 1 Set bit 0 to guarantee operation Program Master ICU IRQ MstrBase MstrBase amp 0 8 _CascadeBits_ MstrCascade 0 4 icw MstrMode amp ICU TRIGGER LEVEL 0x19 0x11 _SetEXRegByte ICW1M 1 Set master triggering SetEXRegByte ICW2M _ MstrBase Set master base interrupt type least 3 bit must be 0 SetEXRegByte ICW3M CascadeBits Set master cascade pins Make sure IR2 set for Cascade icw MstrMode amp ICU TRIGGER LEVEL 1 Set bit 0 and remove Trigger level bit in ICW1 SetEXRegByte ICWA4M icw Set slave IDs in master Program chip configuration registers cfg pins GetEXRegByte INTCFG if MstrCascade amp Oxfb 0 bit 2 IR2 is internal external signals not required 07 for just IR2 cfg pins 0x80 Using external slaves therefore enable Cascade signals cfg pins SlavePins SetEXRegByte INTCFG SlavePins Set Slave external interrupt pins cfg pins GetEXRegByte P3CFG Preserve other set bits SetEXRegByte P3CFG cfg pins MstrPins Set Master external interrupt pins return E OK InitICU 9 34 intel INTERRUPT CONTROL UNIT BRK KK KKK IKK Kk kk Ck CIC kk Kk KC KR IR ko Kk k CK ke k Kk Ck Kk k KK Ck Ck Kk k k Kk k k k k k kk k k k k kc ke k k k k k k InitICUSlave Description
344. e define define define define define define define define define define E OK 0 E INVALID DEVICE 1 E INVALID VECTOR 2 E BADVECTOR 3 INTERRUPT ISR 1 TRAP_ISR 2 IDT_ALIAS 2 Only valid for protected mode TRAP_TYPE 0x8f00 Only valid for protected mode INTR TYPE 0 8 00 Only valid for protected mode LOBYTE w BYTE w HIBYTE w BYTE WORD gt gt 8 amp OxFF LOWORD 1 WORD DWORD 1 HIWORD 1 WORD DWORD 1 gt gt 16 amp OxFFFF Bit Masks BITOMSK 0 1 1 5 0 2 BIT2MSK 0x4 BIT3MSK 0x8 BIT4MSK 0x10 5 5 0 20 6 5 0 40 BIT7MSK 0x80 Global Function extern void EnableExtIOMem void J x3 Interrupt Control Unit configuration defines f e ICU Modes define define define define ICU SFNM 0x10 ICU AUTOEOI 0x2 ICU TRIGGER LEVEL 0x8 ICU TRIGGER EDGE 0x0 ICU Master Pins C 6 intel define define define define define define define define define EXAMPLE CODE HEADER FILES MPIN INTO 0 4 MPIN 0x8 MPIN INT2 0x10 MPIN INT3 0x20 ICU Master External Cascade IRs MCAS_IR1 0 2 MCAS IR2 0 4 MCAS IR5 0x20 MCAS IR6 0x40 MCAS 0x80 ICU Slave Pins define SPIN_INT4 0x1 define SPIN INT5 0x2 define SPIN_INT6 0x4 define SPIN_INT7 0x8 ICU IRQ Mask Values define IRO 0x1 define IR1
345. e fine fine fine fine fine fine fine SIO 0 SIO 1 5100 5101 SIO_SDATA SIO_6DATA SIO_7DATA SIO_8DATA SIO 15 SIO 2STOPBIT SIO NOPARITY SIO ODDPARITY SIO EVNPARITY SIO FRCOPARITY SIO FRCIPARITY SIO SETBREAK SIO INTERNAL SRC SIO EXTERNAL SRC SIO CLKSRC CLK2 SIO CLKSRC COMCLK SIO INTR NONE SIO INTR RBF SIO INTR TBE SIO INTR RLS SIO INTR MS SIO LOOP BACK SIO_MCR_OUT2 SIO_MCR_OUT1 SIO MCR RTS SIO MCR DTR SIO_8N1 SIO_7N1 Status Bits SIO ERROR BITS SIO RX BUF FULL SIO OVERRUN SIO PARITY ERR SIO FRAMING ERR SIO BREAK INTR SIO TX EMPTY Serial I O Port defines x xx 0 1 4 IRQ Master IRQ4 3 IRQ Master IRQ3 0x0 0 1 0 2 0 3 0 0 0 4 0 0 0 8 0 18 0 28 0 38 0 40 0 1 0 0 0 1 0 0 0 1 0 2 0 4 0 8 0 10 0 8 0 4 0 2 0 1 510 8DATA SIO 15 SIO NOPARITY SIO 7DATA SIO 15 SIO NOPARITY Oxle 0 1 0 2 0 4 0 8 0 10 0 20 intel EXAMPLE CODE HEADER FILES define SIO TX EMPTY 0x40 Offsets from beginning of SIO port addresses define RBR 0 define TB define DL define IE define DL define II define LC define MC define LS define MS define SCR define 5100 BASE OxF4F8 define 5101 OxF8F8 ZU UU umet OP FOO Define Function Macros define GetSIO0Status
346. e Ad Mode Ad or dress or dress Virtual Mode Virtual Mode 8086 8086 Mode Mode PREFIX BYTES Address size prefix 01100 1 0 0 LOCK Bus lock prefix 11110000 0 0 m Operand size prefix 01100 0 0 0 Segment override prefix CS 00101110 0 0 DS 00111110 0 0 ES 00100110 0 0 FS 01100100 0 0 GS 01100101 0 0 SS 00110110 0 0 PROTECTION CONTROL ARPL adjust requested privilege level rom register memory 01100011 mod reg r m N A 20 21 a h LAR load access rights rom register memory 00001111 00000010 modreg r m N A 15 16 a g hjp LGDT load global descriptor able register 00001111 00000001 mod01 0 r m 11 11 b c hil LIDT load interrupt descriptor able register 00001111 00000001 mod01 1 11 11 b c hil LLDT load local descriptor bond ta 00001111 00000000 mod0 1 0 r m LMSW load machine status word rom register memory 00001111 00000001 mod110r m 10 13 10 13 b c hil LSL load segment limit rom register memory 00001111 00000011 modreg r m Byte Granular limit N A 20 21 a g h j Page Granular limit N A 25 26 a g h j p LTR load task register from register memory 00001111 00000000 4001 N A 23 27 a g h j SGDT store global descriptor table register 00001111 00000001 4000 9 9 b c h SIDT store interrupt descriptor E 19 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Table E 1 Instruction Set Summary Sheet 19 of 1
347. e scribes notational conventions and special terminology used throughout the manual and provides references to related documentation Chapter 2 Architectural Overview describes the device features and some potential ap plications Chapter 3 Core Overview describes the differences between this device and the Intel386 SX processor core Chapter 4 System Register Organization describes the organization of the system regis ters the I O address space address decoding and addressing modes Chapter 5 Device Configuration explains how to configure the device for various appli cations Chapter 6 Bus Interface Unit describes the bus interface logic bus states bus cycles and instruction pipelining Chapter 7 System Management Mode describes Intel s System Management Mode SMM Chapter 8 Clock and Power Management Unit describes the clock generation circuitry power management modes and system reset logic Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Chapter 9 Interrupt Control Unit describes the interrupt sources and priority options and explains how to program the interrupt control unit Chapter 10 Timer Counter Unit describes the timer counters and their available count formats and operating modes Chapter 11 Asynchronous Serial I O SIO Unit explains how to use the universal asyn chronous receiver transmitters UARTS to transmit
348. e the SMM handler would power up the I O device and reinitialize it The SMM handler would then write OFFH to the I O restart slot in the SMM State Dump area and the RSM instruction would then restart the I O instruction SMI State SMM State Save Handler Resume Figure 7 4 SMI During I O Instruction A2509 01 The SMI input signal can be asynchronous as a result SMI must be valid at least three clock periods before READY is asserted for it to be recognized right after the current bus cycle SMI must be sampled valid for at least two clocks with the other clock used to internally arbitrate for control See Figure 7 5 for details Note that this diagram is only for I O cycles and memory data read cycles 7 9 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Priority Arbitration SMI Sampled SMI T su T lt hold RDY su SMI setup time hold time A251 1 02 Figure 7 5 SMI Timing 7 3 2 5 Restart Bit 16 of the SMM Revision Identifier is set 1 indicating that this device does support the I O trap restart extension to the SMM base architecture The I O trap restart slot provides the SMM handler the option of automatically re executing an interrupted I O instruction using the RSM instruction When the RSM instruction is executed with the I O trap restart slot set to a value of OFFH the CPU automatically re executes the I O in
349. e CS2MSKH 0x00 asm mov mov ax 0x3800 es ax mov mov ax seg SerialWriteStr2 ds ax mov mov 0 100 si offset SerialWriteStr2 di 0 movsb mov rep SetEXRegWordInline CS2MSKL 0x7801 asm pop DI pop SI pop DS pop ES intel Enables SRAM as memory Copy SMM_EXAM BIN code into SRAM Starting address for SMM_EXAM file to be placed Address where SMM_EXAM is located Length of SMM_EXAM file in bytes Resets SRAM to enabled in SMM only Restore register values Loop endlessly and display another serial message while 1 Serial Write Loop SerialWriteStr SIO PORT SMMString ROR KR RK KR KK ke kk KC kk ke kk ke ke ke k END MAIN kkkkkkk KK ko kk ke kk Ck ko kkk kk ke ke 7 20 intel CLOCK AND POWER MANAGEMENT UNIT intel CHAPTER 8 CLOCK AND POWER MANAGEMENT UNIT The clock generation circuitry provides uniform nonoverlapping clock signals to the core and in tegrated peripherals The power management features control the clock signals to provide power conservation options This chapter is organized as follows Overview see below Controlling the PSCLK Frequency page 8 7 Controlling Power Management Modes page 8 8 Design Considerations page 8 11 Programming Considerations page 8 13 8 1 OVERVIEW The clock and power management unit Figure 8 1 includes clock generation power manage m
350. e The duration of LOCK depends on the instruction being executed and the number of wait states per cycle The longest duration of LOCK is 9 bus cycles plus approximately 15 clocks This occurs when an interrupt hardware or software occurs and the processor performs a Locked read of the gate in the interrupt descrip tor table 8 bytes a read of the target descriptor 8 bytes and a write of the accessed bit in the target descriptor 6 5 EXTERNAL BUS MASTER SUPPORT USING HOLD HLDA The processor provides internal arbitration logic that supports a protocol for transferring control of the processor bus to an external bus master This protocol is implemented through the HOLD input and the HLDA output The internal arbitration logic of the processor consists of a bus arbi ter This arbiter supports the core and four other bus masters i e external bus master using HOLD two internal DMA Units and the Refresh Control Unit For a description of the protocol of the internal bus arbiter refer to Bus Control Arbitration on page 12 9 When the internal bus arbiter receives a request through one of its four possible request signals it asserts the HOLD signal to the core The core then completes its current nonlocked bus cycle and asserts its HLDA signal thus informing the arbiter that control of the bus can now be turned over to the requester The arbiter then asserts its appropriate acknowledge signal to the requester For example if an extern
351. e if requester is an 8 bit device or a word if the requester is a 16 bit device from the Source Requester to the temporary register This continues until either the Temporary Register is full or until the byte count or terminal count is reached Write Cycle Ina Write Cycle data is transferred from the Target to the Requester The first request DREQn initiates a fill of the temporary register four byte reads of the Target if the Target is 8 bit or two word reads if it is 16 bit The buffer is considered full if either four bytes have been stored or if less than four bytes the byte count or terminal count has been reached Emptying the Temporary Register Read Cycle Once the Temporary Register has been filled the DMA empties it by doing four byte write cycles if Target is 8 bit or two word write cycles if Target is 16 bit This is done in a burst type fashion since all four requests have already occurred The byte counter is decremented after each write has occurred Write Cycle Once the Temporary Register has been filled the DMA does a single write cycle transferring the first byte if Requester is 8 bit or the first word if Requester is 16 bit This first write cycle happens immediately after the buffer has been filled Each subsequent request DREQn results in another write cycle transferring another byte or word from the Temporary Register to the Requester This continues until either the Temporary Register is empty or b
352. e 14 7 Chip select Low Address Register CSnADL UCSADL 14 18 intel CHIP SELECT UNIT 14 4 4 Chip select Mask Registers The Mask Register of each chip select region is used to prevent bits from being compared with the starting address thus masking them from the comparison This masking allows you to specify the size of the region being defined The mask should be set such that it masks the lower address bits being compared up to the size that you would like the block to be Write a channel s 15 bit mask to the chip select mask registers Also use the chip select low mask register to enable the channel and to mask the channel s SMM address bit When the chan nel s SMM address bit is masked the CSU activates the channel even if the channel is operating in SMM Chip select High Mask Expanded Addr F406H FA0EH CSnMSKH n 0 6 UCSMSKH F416H F41EH read write F426H F42EH F436H F43EH ISA Addr Reset State 0000H CS nMSKH FFFFH UCSMSKH 15 8 CM15 CM14 7 0 CM13 CM12 CM11 CM10 CM9 CM8 CM7 CM6 Bit Bit i Number Mnemonic Function 15 10 Reserved for compatibility with future devices write zeros to these bits 9 0 CM15 6 Mask Value Upper Bits Defines the upper 10 bits of the channel s 15 bit mask The mask bits CM15 6 and the address bits CA15 6 form a masked address that is compared to memory address bits A25 16 or I O address bits A15 6
353. e CPU can also perform a jump and a call anywhere within a 1 Mbyte boundary address space In SMM the processor generates addresses as it does in real mode however there 7 3 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel is no 64 Kbyte limit The value loaded into the selector register is shifted to the left four bits and moved into its corresponding descriptor base then added to the effective address The effective address can be generated indirectly using a 32 bit register However only 16 bits of the Extended Instruction Pointer EIP register are pushed onto the stack during calls exceptions and INTR ser vices Therefore when returning from calls exceptions or INTRs the upper 16 bits of the 32 bit EIP are zero In an SMI handler the EIP should not be over the 64 Kbyte boundary The 16 bit CS allows addressing within a 1 Mbyte boundary Instructions that explicitly access the stack such as MOV instructions can access the entire 4 Gbytes of logical address space by using a 32 bit address size prefix However instructions that implicitly access the stack such as POP PUSH CALL and RET still have the 64 Kbytes limit After SMI is recognized and the processor state is saved the processor state is initialized to the default values shown in Table 7 2 Table 7 2 SMM Processor State Initialization Values Register Content General Purpose Register Unpredictable EFLAGS 00000002H EIP 00008000
354. e IR signal is requesting interrupt service The pending bit resides in the IRR Interrupt Request Register which is accessed through OCW3 The in service bit indicates that the processor is in the process of servicing the interrupt The in service bit resides in the ISR Interrupt Service Register which is accessed through OCW3 When the master 82 59 receives an interrupt request it sets the corresponding pending bit and sends the request to the core assuming the request is enabled and has sufficient priority The core then initiates an acknowledge cycle the master clears its pending bit sets its in service bit and puts the interrupt vector number on the bus When the slave 82C59A receives an interrupt request it sets the corresponding pending bit and sends the request to the master assuming the request is enabled and has sufficient priority When the master receives the slave request it sets its IR2 pending bit and sends the IR2 request to the core assuming the request is enabled and has sufficient priority The core initiates an interrupt acknowledge cycle the master clears its IR2 pending bit and sets its IR2 in service bit The mas ter s cascade bus activates the slave which responds to the interrupt acknowledge cycle clears its pending bit sets its in service bit and puts the interrupt vector number on the bus An 82 59 uses its in service bits and programmed priority structure to determine whether an interrupt ha
355. e Reset Value F019H Byte DMACHR DMAIS 00H F01AH Byte DMACMD2 08H F01BH Byte DMAMOD2 00H F01CH Byte DMAIEN 00H F01DH Byte DMAOVFE OAH F01EH Byte DMACLRTC Not a register Master Interrupt Controller F020H 0020H Byte ICW1m IRRm ISRm XX OCW2m OCW3m F021H 0021H Byte ICW2m ICW3m ICW4m XX OCW1m POLLm Address Configuration Register 0022H 0022H Word REMAPCFG 0000H Timer counter Unit F040H 0040H Byte TMRO XX F041H 0041H Byte TMR1 XX F042H 0042H Byte TMR2 XX F043H 0043H Byte TMRCON XX DMA Page Registers F080H Reserved F081H 0081H Reserved F082H 0082H Reserved F083H 0083H Byte DMA1TAR2 XX F084H Reserved F085H Byte DMA1TAR3 XX F086H Byte DMAOTAR3 XX F087H 0087H Byte DMAOTAR2 XX F088H Reserved F089H 0089H Reserved F08AH 008AH Reserved F08BH 008BH Reserved FO8CH Reserved F08DH Reserved NOTES 1 Byte pointer in flip flop in DMA determines which register is accessed 2 Shaded rows indicate reserved areas D 2 intel Table D 1 Peripheral Register Addresses Sheet 3 of 6 SYSTEM REGISTER QUICK REFERENCE piss Paie NEM Register Name Reset Value FO8EH Reserved FO8FH Reserved F098H Byte DMAOBYC2 XX F099H Byte DMA1BYC2 XX F09AH Reserved FO9BH Reserved A20GATE and Fast CPU Reset F092H 0092H Byte PORT92 XXXXXX10B Slave Interrupt Controller FOAOH 00A0H Byte ICW1s IRRs ISRs XX OCW2s OCW3s FOA1H 00 1 ICW
356. e bus state With this processor address pipelining is optional so that bus cycle timing can be closely tailored to the access time of the memory device Pipelining can be activated once the address is latched externally Pipelining can be not activated if the address is not latched For systems that use address pipelining the great majority of accesses are pipelined Very few idle states occur in an Inte1386 EX processor system This means that once the processor has en tered pipelining another bus cycle request is almost always internally pending resulting in a con tinuous train of pipelined cycles In measured systems about 8596 of bus cycles are pipelined 6 22 intel BUS INTERFACE UNIT A complete discussion of the considerations for using pipelining can be found in the Intel386 SX Processor datasheet order number 240187 or the Intel386 SX Microprocessor Hardware Reference Manual order number 240332 6 3 4 Interrupt Acknowledge Cycle An interrupt causes the processor to suspend execution of the current program and execute in structions from another program called an interrupt service routine Interrupts are described in Chapter 9 The interrupt control unit coordinates the interrupts of several devices internal and external It contains two 82C59A programmable interrupt controllers PICs connected in cascade The slave 82C59A module controls up to five internal interrupt sources and up to four external interrup
357. e byte pointer flip flop Write requester I O address bits 0 7 SetEXRegByte addrDMAReqO 1 BYTE wIO amp OxFF Write requester I O address bits 8 15 SetEXRegByte addrDMAReq0 1 BYTE wIO gt gt 8 amp OxFF _SetEXRegByte addrDMAReq2_3 0x00 Zero requester address bits 16 23 _SetEXRegByte addrDMAReq2_3 0x00 Zero requester address bits 24 25 return ERR NONE RK A IRR Kk kk Kk k kk Ck Ck Kk Ck kk IA kk k k k k SetDMATargMemAddr 12 54 intel DMA CONTROLLER Description Sets the target memory address for the DMA channel specified by nChannel Parameters nChannel channel for which to set target address ptMemory pointer to target memory location Returns None Assumptions Processor is in real mode Syntax static char lpsz Hello World SetDMATargMemAddr DMA Channell lpsz Real Protected Mode The address calculation from ptMemory assumes the processor is in real mode eK RR AR IK RR IRR AA ARR Kk Ck Kk KC CK Ck int SetDMATargMemAddr int nChannel void ptMemory WORD addrDMATar0_1 WORD addrDMATar2 WORD addrDMATar3 WORD wSegment WORD wOffset DWORD lAddress Check input if nChannel DMA 10 amp amp nChannel DMA 11 return ERR BADINPUT Set registers to correct channel addrDMATarO0 1 nChannel DMA 10 DMAOTARO 1
358. e code contains these software routines InitICU Initializes the Master and Slave 82C59A Interrupt Controllers InitICUSlave Initializes the Slave 82C59A Interrupt Controllers Disable8259Interrupt Disables interrupts the Master and internal Slave Enable8259Interrupt Enables interrupts on the Master and internal Slave SetIRQ Vector Loads the interrupt vector table with the address of the Interrupt Service Routine SetInterruptVector Called by SetIRQ Vector to load vector table Poll Command Issues a poll command to read the poll status byte of the ICU See Appendix C for included header files include lt conio h gt include 80386ex h include EV386EX h Globals For information about the ICU BYTE _IRQ_SlaveBase_ 0x30 BYTE _IRQ_MstrBase_ 0x20 9 32 intel BYTE CascadeBits ROR KKK ke kk ke ke kk ke e ke ke ke e ke InitICU Description INTERRUPT CONTROL UNIT 0x4 KKKKKKKKKKK KKK KKK KKK KKK KKK KKK KKK KKK KKK d d d d d d d d E E E E EE EE Initialization for both the master and slave Interrupt Control Units ICU tine only initializes the internal interrupt controllers external ICUs must be initialized separately These should be initial Parameters MstrMode MstrBase MstrCascade SlaveMode SlaveBase MstrPins SlavePins Returns Error Code E OK Assumptions ized before interrupts are enabled i e enable Mode of operation for Master ICU Specifies the
359. e emulated using the CPU SSIO interrupts can be connected to the DMA unit for high speed transfers Refer to Chapter 13 SYNCHRONOUS SERIAL I O UNIT Chip select Programmable eight channel CSU allows direct access to up to eight devices Each Unit CSU channel can operate in 16 or 8 bit bus mode and can generate up to 31 wait states The CSU can interface with the fastest memory or the slowest peripheral device The minimum address block for memory address configured channels is 2 Kbytes The size of these address blocks can be increased by powers of 2 Kbytes for memory addresses and by multiples of 2 bytes for I O addresses Supports SMM memory addressing and provides ready generation and programmable wait states Refer to Chapter 14 CHIP SELECT UNIT Refresh Provides a means to generate periodic refresh requests and refresh addresses Consists of Control Unit a programmable interval timer unit a control unit and an address generation unit Bus RCU arbitration logic ensures that refresh requests have the highest priority The refresh control unit RCU is provided for applications that use DRAMs with a simple EPLD based DRAM controller or PSRAMs that do not need a separate controller Refer to Chapter 15 REFRESH CONTROL UNIT Parallel I O Three I O ports facilitate data transfer between the processor and surrounding system Ports circuitry The Intel386 EX processor is unique in that several functions are multiplexed with eac
360. e inc dec see DMAMOD 4 DMAOVFE 2 1 all bits of channel 1 yo target addr are inc dec DMAOVFE 1 0 untouched channel 0 settings SetDMAReqIOAddr DMA 11 TBRO Sets Req I O address to Serial Receiver Rok Ck kk Ck KR Kk Ck ko kk k IRR Kk kk Kk Kk kk Kk Ck k k k ke kk kk kk kc k k k k k k k DMAInterrupt Description This function is called by the DMA unit when it either completes a transfer or in chaining xfer mode when a new requester target and byte count should be written to the device Parameters None Returns None Assumptions 12 60 intel Syntax regDMAIE GetEXRegByte DMAIEN SetEXRegByte DMAIEN regDMAIE Set interrupt routine SetIRQVector DMAInterrupt Enable8259Interrupt 0 12 IRA NonSpecificEOI Real Protected Mode No changes required DMA CONTROLLER 0x2 Enable tc interrupt for channel 0 INTERRUPT ISR Enable slave IRA DMA interrupt Clear all interrupts Ck KC Kk Ck kk k k k k k kk k k void interrupt far DMAInterrupt void WORD regDMAIS regDMAIS GetEXRegByte DMAIS if regDMAIS amp 0x10 Get interrupt status register Transfer Complete channel 0 SetEXRegByte DMACLRTC 0x00 Clear transfer complete signal if regDMAIS amp 0x20 Transfer Complete channel 1 SetEXRegByte DMACLRTC 0x00 Clear transfer com
361. e modes for 16 bit default sizes com patible with the 8086 80186 80286 Two prefixes the Operand Size Prefix and the Effective Address Size Prefix allow overriding individually the Default selection of operand size and effective address size These prefixes may precede any opcode bytes and affect only the instruction they precede If necessary one or both prefixes may be placed before the opcode bytes The presence of the Operand Size Prefix and the Effective Address Prefix toggles the operand size or the effective address size respectively to the value opposite from the default setting For example if the default operand size is for 32 bit data operations then presence of the Operand Size Prefix toggles the instruction to use 32 bit ef fective address computations These 32 bit extensions are available in all modes including the Real Address Mode or the Vir tual 8086 Mode In these modes the default is always 16 bits so prefixes are needed to specify 32 bit operands or addresses For instructions with more than one prefix the order of prefixes is unimportant E 23 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Unless specified otherwise instructions with 8 bit and 16 bit operands do not affect the contents of the high order bits of the extended registers E 2 2 Encoding of Instruction Fields Within the instruction are several fields indicating register selection addressing mode and so on The exact enc
362. e on a cycle by cycle basis READY indicates that internal logic has completed the current bus cycle or that external hardware has terminated it NA requests the next address to be put on the bus during a pipelined bus cycle BS8 indicates that the current bus transaction is for an 8 bit data bus The remaining external bus pins interface to external bus masters and external logic for transfer ring control of the bus 6 2 An external bus master activates the HOLD pin to request the external bus The internal bus arbiter arbitrates between the HOLD input and other potential requests DMA Units 0 and 1 Refresh Control Unit based on their priorities When another unit has control of the bus the bus is released to the external bus master based on the arbiter s arbitration scheme refer to Bus Control Arbitration on page 12 9 for information on internal bus masters also controlled by the internal bus arbiter and the arbitration protocol used by the arbiter When the core has control of the bus the arbiter passes the request on to the core by asserting the core HOLD signal The core finishes the current nonlocked bus transfer and releases the bus signals The core asserts the core HLDA signal to indicate that the bus has been released The arbiter then asserts the HLDA pin to indicate to the external bus master that the bus has been released intel BUS INTERFACE UNIT 6 1 1 Bus Signal Descriptions Table 6 1 descri
363. e only ISA Addr 0021H 00 1 Reset State XXH XXH 7 0 TZ T6 T5 T4 T3 0 0 0 Bit Bit Number Mnemonic Function 7 3 T7 3 Base Interrupt Type Write the base interrupt vector s five most significant bits to these bits 2 0 T2 0 Clear these bits to guarantee device operation D 25 ICW3 MASTER Initialization Command Word 3 Expanded Addr F021H ICW3 master ISA Addr 0021H write only Reset State XXH 7 0 S7 S6 S5 S4 S3 S2 51 0 Bit Bit Number Mnemonic Function 7 3 S73 Slave IRs 0 No slave 8259A is attached to the corresponding IR signal of the master 1 A slave 82C59A is attached to the corresponding IR signal of the master 2 S2 0 Internal slave not used 1 Internal slave is cascaded from the master s IR2 signal 1 S1 Slave IRs 0 No slave 8259A is attached to the master through the IR1 signal of the master 1 A slave 82C59A is attached to the IR1 signal of the master 0 Clear this bit to guarantee device operation D 29 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL D 26 ICW3 SLAVE Initialization Command Word 3 Expanded Addr 1 ICW3 slave ISA Addr 00A1H write only Reset State XXH 7 0 0 0 0 0 0 0 1 0 Bit Bit Number Mnemonic Function 7 2 Clear these bits to guarantee device operation 1 Set this bit to guarantee device operation 0 Clear thi
364. e signals are multiplexed with port 3 signals P3 5 2 Connecting a port 3 signal to the pack In age pin also connects V to the corresponding master s IR signal disabling the signal Port 3 Configuration Expanded Addr F824H P3CFG ISA Addr read write Reset State 00H 7 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PMO Bit Bit Functi Number Mnemonic Mnenon 7 PM7 Pin Mode 0 Selects P3 7 atthe package pin 1 Selects COMCLK at the package pin 6 PM6 Pin Mode 0 Selects P3 6 at the package pin 1 Selects PWRDOWN at the package pin 5 PM5 Pin Mode 0 Selects P3 5 at the package pin 1 Connects master to the package pin 4 PM4 Pin Mode 0 Selects P3 4 at the package pin 1 Connects master IR6 to the package pin INT2 3 PM3 Pin Mode 0 Selects P3 3 at the package pin 1 Connects master IR5 to the package pin INT1 2 PM2 Pin Mode 0 Selects P3 2 at the package pin 1 Connects master IR1 to the package pin INTO 1 PM1 Pin Mode See Table 5 1 on page 5 8 for all the PM1 configuration options 0 PMO Pin Mode See Table 5 1 on page 5 8 for all the PMO configuration options Figure 9 6 Port 3 Configuration Register P3CFG tel intel INTERRUPT CONTROL UNIT 9 3 2 Interrupt Configuration Register INTCFG Use the INTCFG register to connect the INT9 4 interrupt request pins to the master s and the slave s IR sig
365. e the correct control signals to the I O device since all processor signals are used to access memory This means that if it is an I O to memory transfer this logic generates an I O read cycle and the processor generates the memory write cycle If itis a memory to I O transfer the logic generates an I O write cycle and the processor generates the memory read cycle This way the data is driven by the I O device and latched by the memory de vice during an I O to memory transfer and driven by the memory device and latched by the I O device during a memory to I O transfer 12 2 2 2 Two Cycle Mode The two cycle option first fills the four byte temporary buffer with data from the source then writes that data to the destination This method allows transfers between any combination of memory and I O with any combination of data path widths 8 or 16 bit The amount of data and the data bus widths determine the number of bus cycles required to transfer data For example it takes six bus cycles to transfer four bytes of data from an 8 bit source to a 16 bit destination four read cycles to fill the temporary buffer from the 8 bit source and two write cycles to transfer the data to the 16 bit destination A buffer transfer can complete be terminated or be suspended before the temporary buffer is filled from the source If the buffer transfer completes or is terminated before the temporary buff er is filled the DMA writes the partial data to the desti
366. ead write Reset State FFFFH 15 8 WR15 WR14 WR13 WR12 WR11 WR10 WR9 WR8 7 0 WR7 WR6 WR5 WR4 WR3 WR2 WR1 WRO Bit Bit i Number Mnemonic Function High 15 0 WR31 16 WDT Reload Value High Word and Low Word Low 15 0 WR15 0 Write the high word of the reload value to WDTRLDH and the low word to the WDTRLDL D 69 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel D 74 WDTSTATUS WDT Status Expanded Addr FACAH WDTSTATUS ISA Addr read write Reset State 00H 7 0 WDTEN BUSMON CLKDIS Bit Bit Function Number Mnemonic unctio 7 WDTEN Watchdog Mode Enabled This read only bit indicates whether watchdog mode is enabled Only a lockout sequence can set this bit and only a device reset can clear it 0 Watchdog mode disabled 1 Watchdog mode enabled 6 2 Reserved These bits are undefined for compatibility with future devices do not modify these bits 1 BUSMON Bus Monitor Enable 0 Disables bus monitor mode 1 Enables bus monitor mode Read this bit to determine the current status A lockout sequence clears BUSMON and prevents writes to the WDTSTATUS register 0 CLKDIS Clock Disable Write to this bit to stop or restart the clock to the WDT read it to determine the current clock status A lockout sequence clears CLKDIS and prevents writing to this register 0 Clock enabled 1 Processor clock frequen
367. ecludes use of the coprocessor signals PEREQ BUSY and ERROR The CLKINz and GATEn inputs of Timer counterO and Timer counterl are routed directly to shared input pins TMRCLKO INT4 TMRCLKI INT6 TMRGATEO INTS TMRGATEI INT7 The OUTn inputs of these two counters can be connected to pins TMROUTO INT9 P3 0 and TMROUT1 INT8 P3 1 respectively using bits in registers P3CFG and INTCFG 5 11 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel TMRCFG 7 Timer Counter Unit TMRCFG 0 Q CLKINO PSCLK 1TMRCLKO To ICU INT4 t TMRCFG 1 Voc TMRCFG 1 _ TMRGATEO To ICU 5 To ICU P3CFG 0 p D TMROUTO To From I O Port 3 INT9 TMRCFG 2 5970 CLKIN1 PSCLK 1TMRCLK1 To ICU INT6 TMRCFG 3 Voc TMRCFG 3 TMRGATE1 To ICU INT7 To ICU DMA 4 PSCFG 1 TMROUT1 To From I O Port 3 lt gt INT8 0 P3 1 TMRCFG 4 CLKIN2 PSCLK PINCFG 5 1 1 TMRCLK2 To Core PEREQ TMRCFG 6 TMRCFG 5 o 1 i TMRGATE2 To Core Ee BUSY 0 1 To ICU 1 1 8212 17 TMROUT2 To Core 9 ERROR 0 Alternate pin signals are in parentheses A2517 03 Figure 5 6 Timer Counter Unit Configuration intel DEVICE CONFIGURATION Timer Configuration TMRCFG read write 7 Expanded Addr F834H ISA Addr Reset State 00H 0 TMRDIS SWGTEN GT2CON CK2CON GT1CON CK1CON GTOCON CKOCON
368. ed No other bus master should be permitted to control the bus between two locked bus cycles The address bus byte enable pins and bus status pins with the exception of ADS and WR remain active through the end of the write cycle At the start of Phase 2 in T1 the WR signal is asserted and the CPU begins to drive output data on its data pins The data remains valid until the start of phase 2 in the T State after the present bus cycle has terminated If a chip select region is enabled for the current read cycle but internal READY generation is disabled for that region and the Chip select Unit is programmed to insert wait states then the READY signal is ignored not sampled by the processor until the programmed number of wait states are inserted into the cycle intel BUS INTERFACE UNIT 4 The WR signal can be deasserted in two ways Early Ready is deasserted at the rising edge of CLK2 in the middle of the T2 state after any wait states programmed in the Chip select Unit have expired At the rising edge of PH2 READY is sampled If it is found active WR is synchronously deasserted in the middle of T2 driven inactive by the rising edge of the PH2 clock The write cycle is then terminated at the end of the T2 state NOTE When READY is generated by the processor e g when the Chip select Unit generates it then the write cycle is always an Early Ready cycle e Late Ready When READY goes low after the rising e
369. ed as follows REGION CA25 11 CM25 11 CASMM CMSMM BS16 EPROM 11 1111 0000 0000 0 00 0000 1111 1111 1 0 0 1 RAM 00 0000 0000 0000 0 00 0000 TFET LIII X 0 0 1 SMRAM 00 0001 0011 1000 0 00 0000 0000 0111 1 0 0 0 Only the SMRAM row has been changed the SMRAM chip select has been redirected to the re gion 013F800H to 013FFFFH andthe CASMM bit has been cleared This allows the initialization software to set up the SMRAM without entering the SMM Note that the external design of the system must guarantee that an SMI cannot occur while the SMRAM is being initialized If the SMM driver needs to access the memory shadowed under the SMRAM the chip selects can be reconfigured as follows REGION CA25 11 CM25 11 CASMM CMSMM BS16 EPROM 11 1111 0000 0000 0 00 0000 1111 1111 1 0 0 1 RAM 00 0001 0000 0000 0 00 0000 1111 1111 1 0 1 1 SMRAM 00 0000 0011 1000 0 00 0000 0000 0111 1 1 0 0 This leaves the SMRAM in place but moves the normal RAM into the partition 0100000H to O1FFFFFH The CASMM bit is masked so that the RAM is selected independent of SMM 7 13 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 7 3 4 2 SMRAM State Dump Area The SMM State Save sequence asserts SMIACT This mechanism indicates to internal modules that the CPU has entered and is currently executing SMM The resume RSM instruction is only valid when in SMM SMRAM space is an area located in the
370. ed through the same addresses 0 OCW2 or OCWS is accessed Figure 9 13 and Figure 9 15 1 ICW1 register is accessed 3 LS Level Edge Sensitive 0 Selects edge triggered IR input signals 1 Selects level sensitive IR input signals All internal peripherals interface with the 82C59As in edge triggered mode only This is compatible with the PC AT bus specification Each Source signal initiates an interrupt request by making a low to high transition External peripherals interface with the 8259As in edge triggered or level sensitive mode The modes are selected for the device not for individual interrupts NOTE If an internal peripheral interrupt is used the 8259A that the interrupt is connected to must be programmed for edge triggered interrupts 2 1 Clear these bits to guarantee device operation 0 Set this bit to guarantee device operation NOTE 82C59A must be initialized before it can be used After reset the 82C59A register states are undefined The 82C59A modules must be initialized before the IF flag in the core FLAG register is set All peripherals that use interrupts connected to the ICU must be initialized before initializing the ICU 9 20 Figure 9 8 Initialization Command Word 1 Register ICW1 intel intel INTERRUPT CONTROL UNIT 9 3 4 Initialization Command Word 2 ICW2 Use the ICW2 register to define the base interrupt vector for the 82C594A Valid vector numbers for maskable interr
371. ee Table 5 1 on page 5 8 for all the PM1 configuration options 0 PMO Pin Mode See Table 5 1 on page 5 8 for all the PMO configuration options D 45 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel D 43 PINCFG Pin Configuration PINCFG read write 7 Expanded Addr F826H ISA Addr Reset State 00H PM6 PM5 PM4 PM3 PM2 PM1 PMO Bit Bit Number Mnemonic Function 7 Reserved This bit is undefined for compatibility with future devices do not modify this bit 6 PM6 Pin Mode 0 Selects CS6 at the package pin 1 Selects REFRESH at the package pin 5 5 0 Selects the coprocessor signals PEREQ BUSY and ERROR Z at the package pins 1 Selects the timer control unit signals TMROUT2 TMRCLK2 and TMRGATE2 at the package pins 4 4 Pin Mode 0 Selects DACKO at the package pin 1 Selects CS5 at the package pin 3 0 Selects EOP at the package pin 1 Selects 51 at the package pin 2 PM2 Pin Mode 0 Selects DACK1 at the package pin 1 Selects TXD1 at the package pin 1 1 Pin Mode 0 Selects SRXCLK at the package pin 1 Selects DTR1 at the package pin 0 PMO Pin Mode 0 Selects SSIOTX at the package pin 1 Selects RTS1 at the package pin D 46 intel S
372. ee epe in PER EROR ead 6 13 6 3 2 Witte Cycle ee pe aai dent oe E PUR acne Hr Eie petet D LO 6 3 3 Pipelined Gycle 3 i Ante eredi eere pe 6 19 intel CONTENTS 6 3 4 Interrupt Acknowledge Cycle 6 23 6 3 5 Halt Shutdown enm eee 0 26 6 3 6 Refresh Cycle ec een eee erede eh nac cnt Ple estre eunte 6 28 0 3 7 BSB Cylon uice m UE ICT piter thu HER Den 6 31 06 3 7 1 Write Cycles eite ete ree preis eines O79 1 6 3 7 2 Head Cycles iot RR t REIR 6 31 6 4 BUS EOGOK x te e awh a t e edens anand ead 6 34 6 4 1 Locked Cycle Activators esses 6 34 6 4 2 Locked Cycle Timing 2044400 4500 enne 6 34 6 4 3 LOCK Signal Duration essem T nnne enne 6 35 6 5 EXTERNAL BUS MASTER SUPPORT USING HOLD 6 35 6 5 1 HODD HEDA TIMING s dott e e ee ee ie RR 6 36 6 5 2 HOLD Signal Latency innen 6 37 6 6 DESIGN CONSIDERATIONS 6 6 1 Interface To Intel887 SX Math Coprecessor P niin ea 6 38 6 6 1 1 System Configuratiori n nrbe nei tet rae ris Ro RE 6 39 6 6 1 2 Software Considerations 2 eene 6 40 6 6 2 SRAM FLASH Interface 4 400222 0 0 41 6 6 3 PSRAM Interface
373. egion can be reprogrammed to reflect an 8 bit region One way of doing this is by connecting the pin directly to the BS8 pin if there are no other devices that need to use the BS8 pin If UCS is tied directly to BS8 then the UCS region need not be programmed to reflect an 8 bit region Since LBA may be used as an output enable by both the internal and external READY buffers care must be taken in selecting the external READY buffer to minimize contention on the READY signal caused by differences in buffer characteristics 6 6 1 Interface To Intel387 SX Math Coprocessor The Intel387 SX Math Coprocessor is an extension to the Intel386 EX embedded processor ar chitecture The combination of the Intel387 SX Math Coprocessor with the Intel386 EX embed ded processor dramatically increases the processing speed of computer application software that uses high performance floating point operations An internal Power Management Unit enables the Inte1387 SX Math Coprocessor to perform float ing point operations while maintaining very low power consumption The internal Power Man agement Unit effectively reduces power consumption by 9596 when the coprocessor is idle This section describes special considerations for interfacing the Intel387 SX Math Coprocessor with the Intel386 EX embedded processor For complete information refer to the Intel387 SX Math Coprocessor datasheet Order number 240225 6 38 intel BUS INTERFA
374. egister clears this bit 1 OE Overrun Error The receiver sets this bit to indicate an overrun error An overrun occurs when the receiver transfers a received character to the receive buffer register before the CPU reads the buffer s old character Reading the serial line status register clears this bit 0 RBF Receive Buffer Full The receiver sets this bit after it transfers a received character from the receive shift register to the receive buffer register Reading the receive buffer register clears this bit Figure 11 16 Serial Line Status Register LSRn 11 26 intel ASYNCHRONOUS SERIAL I O UNIT 11 3 8 Interrupt Enable Register IERn Use IERn to connect the SIOn status signals to the interrupt control unit All four status signals can be connected to the interrupt control unit Interrupt Enable IERO IER1 IERO IER1 Expanded Addr F4F9H F8F9H read write ISA Addr O3F9H 02 9 Reset State 00H 00H 7 0 ws RLS TBE RBF Bit Bit Number Mnemonic Function 7 4 Reserved for compatibility with future devices write zeros to these bits 3 MS Modem Status Interrupt Enable 0 Modem input signal changes do not cause interrupts 1 Connects the modem status signal to the interrupt control unit s SIOINTn output A change on one or more of the modem input signals activates the modem status signal 2 RLS Receiver Line Status Interrupt Enable 0 LSR e
375. either the transmit holding register is empty or the receive holding register is full BCLKIN Internal signal Prescaled Clock PSCLK This internal signal is a prescaled value of the internal clock frequency CLK2 2 PSCLK is programmable for a range of divide by values Serial Clock SERCLK This internal signal is half the internal clock frequency CLK2 4 13 4 intel SYNCHRONOUS SERIAL UNIT 13 2 SSIO OPERATION The following sections describe the operation of the baud rate generator transmitter and receiv er 13 2 4 Baud rate Generator Either the prescaled clock or the serial clock PSCLK or SERCLK can drive the baud rate gen erator Figure 13 5 The SIO and SSIO configuration register SIOCFG selects one of these sources Baud rate Generator SERCLK BCLKIN SSIOBAUD 9 bit Programmable Divider BV6 0 CLKPRS A2443 02 Figure 13 5 Clock Sources for the Baud rate Generator BCLKIN SERCLK E OR CLK2 2 BCLKIN prescale value 2 SERCLK provides a baud rate input frequency BCLKIN of CLK2 4 The PSCLK frequency depends on the 9 bit programmable divider The input to the programmable divider is divided by a 9 bit prescale value 2 A prescale value of 0 gives the maximum PSCLK frequency CLK2 4 and a prescale value of 1FFH 511 gives the minimum PSCLK frequency CLK2 1026 13 5 Intel386 EX EMBEDDED MICROPROCESSOR USER S MA
376. el Mask 000000000001101 25 0 Channel Active Address 00000000000 0 XXXXXXXXXXX Because the least significant 0 in the channel s mask is in bit position 2 this channel s active ad dress block size is 2 4 Kbytes Because there are two 1 s to the left of the right most 0 in the channel s mask the block is repeated 2 4 times Also because there are no 1 s in the channel mask where there are 175 in the channel address the channel address is the starting address of the lowest active address block In this example each active 4 Kbyte address block in memory is fol lowed by an inactive 4 Kbyte address block and each active address block starts on a 4 Kbyte address boundary Maximum Memory Address 0007000H Active 0006FFFH 0006000H 0005FFFH 0005000H Active 0004FFFH 0004000H 0003FFFH 0003000H Active 0002FFFH 0002000H 0001FFFH 0001000H Active 0000FFFH 0000000H 14 6 intel Example 3 CHIP SELECT UNIT This example establishes four 2 Kbyte address blocks starting at 2413000H 2433000H 2613000H and 2633000H 15 bit Channel Address 15 bit Channel Mask Channel Active Address 15 100100000100110 000010001000000 25 1001X000X100110 XXXXXXXXXXX Because the least significant 0 in the channel s mask is in bit position 1 this channel s active ad dress block size is 2 2 Kbytes Because there are two 1 s to the left o
377. el is activated it either asserts a chip select signal controls wait states and READY generation or both Chip select High Address Expanded Addr F402H F40AH CSnADH n 0 6 UCSADH F412H F41AH read write F422H F42AH F432H F43AH ISA Addr Reset State 0000H CSnADH FFFFH UCSADH 15 8 CA15 CA14 7 0 CA13 CA12 CA11 CA10 CA9 CA8 CA7 CA6 Bit Bit Number Mnemonic Function 15 10 Reserved for compatibility with future devices write zeros to these bits 9 0 CA15 6 Chip select Channel Address Upper Bits Defines the upper 10 bits of the channel s 15 bit address The address bits CA15 6 and the mask bits CM15 6 form a masked address that is compared to memory address bits A25 16 or I O address bits A15 6 Figure 14 6 Chip select High Address Register CSnADH UCSADH 14 17 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Chip select Low Address Expanded Addr CSnADL n 0 6 UCSADL read write F400H F408H F410H F418H F420H F428H F430H F438H ISA Addr Reset State 0000H CSnADL FF6FH UCSADL 15 5 5 CA4 CA3 CA2 CA1 CASMM BS16 MEM 7 0 RDY WS4 WS3 WS2 WS1 WSO Function 15 11 5 1 Chip select Address Value Lower Bits Defines the lower 5 bits of the channel s 15 bit address The address bits CA5 1 and the mask bits CM5 1 for
378. emains high For an odd count of OUTn remains high for N 1 2 counts and low for N 1 2 counts provided GATEn remains high Figure 10 13 shows suspending the counting sequence A low level on GATEn causes the counter to drive OUTn active When OUT is low a falling edge on GATEn causes OUT to be driven high immediately and suspend counting A rising edge on the GATEn causes the counter to be reloaded with the count A high level on GATEz resumes counting Control Word 16H Count 4 Writes to Tp 1 CLKINN 2401 02 Figure 10 13 Mode 3 Disabling the Count 10 14 intel TIMER COUNTER UNIT Figure 10 14 and Figure 10 15 shows writing a new count If the counter receives a gate trigger after writing a new count but before the end of the current half cycle the count is loaded on the next CLKINn pulse and counting continues from the new count Figure 10 14 Otherwise the new count is loaded at the end of the current half cycle Figure 10 15 Control E _ Word 16H Count 8 Count 10 Writes to Counter i i i i i i i i i i CLKINn GATEn 1 1 1 1 1 Count 2407 02 Figure 10 14 Mode 3 Writing a New Count With a Trigger Control Count 4 Word 16H POU Writes to Counter n peut de a gin pte CLKINn GATEn 1 1 1 1 1 1
379. emonic Function 7 0 PS7 0 Pin State Reading a PS bit returns the logic state present on the associated port pin D 48 intel SYSTEM REGISTER QUICK REFERENCE D 47 POLL MASTER AND SLAVE Poll Status Byte master slave POLL master and slave Expanded Addr F020H FOAOH read only ISA Addr 0020H Reset State XXH XXH 7 0 INT L2 L1 LO Bit Bit 5 Number Mnemonic Function 7 INT Interrupt Pending 0 No request pending 1 Indicates that a device attached to the 82C59A requires servicing 6 3 Reserved These bits are undefined 2 0 L2 0 Interrupt Request Level When bit 7 is set these bits indicate the highest priority IR signal that requires servicing When bit 7 is clear i e no request is pending these bits are indeterminate D 49 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel D 48 PORT92 Port 92 Configuration PORT92 read write 7 Expanded Addr 092 ISA Addr 0092H Reset State XXXXXX10B 0 A20G CPURST Bit Bit Number Mnemonic Function 7 2 Reserved These bits are undefined for compatibility with future devices do not modify these bits 1 A20G A20 Grounded 0 Clearing this bit forces address line A20 to 0 This bit affects addresses generated only by the core Addresses generated by the DMA and the Ref
380. endant separate source Fe RRR AA CK CkCk Kk Ck Kk IC kk Kk IRR Kk Ck Ck Kk k kk Ck int SetIRQVector void far interrupt IntrProc void int IRQ int IntrType int Vector if IRO 15 return E INVALID VECTOR if IRQ 7 Get Vector from Slave Vector IRQ SlaveBase IRQ 8 else From Master if 1 lt lt IRQ amp _CascadeBits_ return E_BADVECTOR Vector _IRQ MstrBase_ IRQ SetInterruptVector IntrProc Vector IntrType 9 39 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel return E OK SetIRQVector Ck Rok Ck Kk A He KCkCk Kk kk Kk KC IRR IR IR kk ke kk ko ko kk ko ko ke kk ke SetInterruptVector Description Loads the interrupt vector table with the address of the interrupt routine The vector table entry number is determined by the vector number Parameters InterProc Address of interrupt function will be loaded into the interrupt table ISR Type Specifies if the interrupt function Real Mode only supports INTERRUPT ISR the parameter is ignored The parameter is kept to maintain compatibility with the protected mode version of this function Returns None Assumptions Compiler supports far and interrupt keywords Compiler may issue a warning about IntrType not used IntrType is kept for protected mode compatibility Syntax SetInterruptVector wdtISR INTERRUPT_ISR Real Protected Mode Real Mode only
381. ent and system reset circuitry It also provides a clock output signal CLKOUT for synchro nizing external logic to the processor s system clock CLKOUT is the PHIP clock 8 1 1 Clock Generation Logic An external oscillator must provide an input signal to CLK2 which provides the fundamental timing for the processor As Figure 8 1 shows the clock generation circuitry includes two divide by two counters and a programmable clock divider The first divide by two counter divides the CLK2 frequency to generate two clocks PH1 and PH2 For power management independent clock signals are routed to the core PH1C and PH2C and to the internal peripherals PHIP and PH2P The second divide by two counter divides the processor clock to generate a clock input SER CLK for the baud rate generators of the asynchronous and synchronous serial I O units The SERCLK frequency is half the internal clock frequency or CLK2 4 The programmable divider generates a prescaled clock PSCLK input for the timer counter and synchronous serial I O units The maximum PSCLK frequency is the internal clock frequency di vided by 2 CLK2 4 and the minimum is the internal clock frequency divided by 513 CLK2 1026 8 1 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Three of the internal peripherals have selectable clock sources The asynchronous serial I O SIO unit can use either the SERCLK signal or an external clock connected to the COMCL
382. equired KOKCKCkCKCkCkCkCKCkCkC RRR RRR IAA IRR IRI void interrupt far SSIO_ISR void Control GetEXRegByte SSIOCON1 If THBE is set and Transmitter Interrupts are enabled if Control amp SSIO THBE amp amp Control amp SSIO TX IE Service THBE Service routine specific to THBE interrupts Else if RHBF is set and Receiver Interrupts are enabled else if Control amp SSIO RHBF amp amp Control amp SSIO RX IE Service RHBF Service routine specific to RHBF interrupts NonSpecificEOI For Slave NonSpecificEOI For Master SSIO ISR RRR KK KKK IK KR I RRA ARR kk Kk k CK k k IR IR CK Ck KC Kk k k k k k k k k ke kk ko k k k k k k k k k k k Service_RHBF Description Service Routine for SSIO interrupts generated by the RHBF signal Parameters None Returns None Assumptions 13 31 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel None Syntax Not called by user Real Protected Mode No changes required eK RR AA IRR KARR IR AA ARR IR AA IRR void Service_RHBF void WORD buffer buffer GetEXRegWord SSIORBUF Display received character on the screen SerialWriteChar SIO 0 BYTE buffer Service_RHBF RRR IKK KK IK KK I RR AR IRR IR AR IRR IR IR RRA IR IR IA I k k kk k k Service_THBE Description Service routine for SSIO interrupts generated by THBE signal Parameters None
383. er transfer Mode 12 22 intel DMA CONTROLLER After initialization the DMA channel is programmed with the requester and target addresses and a byte count M active DMA gains bus control DMA transfers one byte or word of data and decrements the byte count Byte count FFFFFFH or EOP active DMA channel DREQn relinquishes active bus control DMA channel relinquishes bus control DMA channel is reprogrammed with the original addresses and byte count A2339 02 Figure 12 15 Demand Data transfer Mode with Autoinitialize Buffer transfer Mode 12 23 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel After initialization the DAM channel is programmed with the requester and target addresses and a byte count DREQn active Write new requester and target Is there addresses a new process and a new to set up byte count DMA gains bus control DMA transfers one byte or word of data and decrements the byte count Yes Byte E DRE count FFFFFFH q No active No or EOP bus control active DMA channel relinquishes bus control Was the DMA is channel set up programmed Yes with the new byte count No No new transfer information so channel becomes idle addresses and A2336 02 Figure 12 16 Demand Data transfer Mode with Chaining Buffer transfer Mode 12 24 intel DMA CONTRO
384. er transfers a received character to the receive buffer register before the CPU reads the buffer s old character Reading the serial line status register clears this bit 0 RBF Receive Buffer Full The receiver sets this bit after it transfers a received character from the receive shift register to the receive buffer register Reading the receive buffer register clears this bit D 37 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel D 35 MCRn Modem Control MCRO MCR1 MCRO MCR1 Expanded Addr FAFCH F8FCH read write ISA Addr O3FCH 02 Reset State 00H 00H 7 0 LOOP OUT2 OUT1 RTS DTR Bit Bit Number Mnemonic Function 7 5 Reserved for compatibility with future devices write zeros to these bits 4 LOOP Loop Back Test Mode Normal mode Setting this bit puts the SIOn into diagnostic or loop back test mode This causes the SIO channel to set its transmit serial output TXDn disconnect its receive serial input RXDn from the package loop back the transmitter shift register s output to the receive shift register s input disconnect the modem control inputs CTSn DSRn Rin and DCDn from the package pins force modem control outputs RTS mit and DTRn to their inactive states connects MCRn bits to MSRn bits 3 2 OUT2 1 Test Bits In diagnostic mode bit 4 1 these bits control the ring indicator RIn an
385. er while the baud rate generator clock is high the data and clock pin states are as shown in Figure 13 10 If you enable the transmitter while the baud rate generator clock is low the data and clock pin states are as shown in Figure 13 11 These figures show master mode single word transfers At the end of transmission STXCLK and SSIOTX are three stated and require external pull up resistors For single word transfers you must enable the transmitter which starts the shifting process then disable the transmitter before 16 bits are shifted out For high baud rates use the Autotransmit mode 1 l Baud rate PISANI M 4 NORIS Generator Clock i i i Transmitter Enable Ne SE SN if 1 Float i Float AS ee I 1 Float Float 1 1 1 1 1 1 1 2445 01 Figure 13 10 Transmitter Master Mode Single Word Transfer Enabled when Clock is High 1 Generator Clock i i A Transmitter Enable ee a MM Float Float SSIOTX TB15 TB14 eee TB1 TBO A2444 01 Figure 13 11 Transmitter Master Mode Single Word Transfer Enabled when Clock is Low 13 11 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 13 2 2 2 Autotransmit Mode Set AUTOTXM bit SSIOCON2 2 and the TXMM bit SSIOCON2 1 to enable Autotrans mit mode When the AUTOTXM bit is set the word is automatically
386. eriodic refresh requests The address generation unit uses a refresh base address register and a 13 bit address counter to generate DRAM refresh addresses The DRAM device can use these addresses as row addresses during RAS only refresh cycles Each time the interval timer unit times out a new re fresh address is generated 15 2 intel REFRESH CONTROL UNIT Interval Timer Unit Refresh Clock Interval Register 10 bit Interval Counter Processor Clock CLK2 2 Timeout REFRESH Control Unit pin mux Refresh Refresh Control Register Request Refresh Acknowledge Address Generation Unit Refresh Base Address Register 13 bit Address Counter Refresh Address Register A2341 01 Figure 15 1 Refresh Control Unit Connections 15 8 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 15 2 1 RCU Signals Table 15 1 describes the signals associated with the RCU Table 15 1 RCU Signals gt Device Pin or Internal Signal 2 Description Signal CLKOUT Device Pin Processor Clock from Clock and Power Provides the clocking signal for the interval counter The Management Unit interval timer unit loads and decrements the counter on the falling edges of the processor clock Timeout Internal signal Timeout from the interval counter to Indicates that the interval counter has reached one The the control unit control unit initiates a refresh request when it detects this s
387. ernate Function P2 7 Port2 50 2 6 idiracti TXDO l bidirectional port P25 General purpose bidirecti p RXDO P2 4 CS4 P2 3 CS3 P2 2 CS2 P2 1 CS1 P2 0 50 P3 7 Port3 COMCLK P3 6 General bidirectional I O port PWRDOWN P35 eneral purpose bidirecti port INT3 P3 4 INT2 P39 P3 2 INTO P3 1 TMROUT1 INT8 P3 0 TMROUTO INT9 PWRDOWN Powerdown Output P3 6 Indicates that the device is in powerdown mode RD Read Enable Indicates that the current bus cycle is a read cycle and the data bus is able to accept data READY Ready Terminates the current bus cycle The processor drives READY when LBA is active otherwise the processor samples READY on the falling edge of phase 2 of T2 T2P or T2i REFRESH Refresh 56 Indicates that a refresh bus cycle is in progress and that the refresh address is on the bus for the DRAM controller RESET ST System Reset Input Suspends any operation in progress and places the processor into a known reset state Ri Ring Indicator SSIORX RIO Indicates that the modem or data set has received a 1 4 telephone ringing signal RTS1 Request to Send SSIOTX 50 Indicates that the SIO channel is ready to exchange data P1 1 with the modem or data set RXD1 Receive Data DRQ1 RXDO Accepts data from the modem or data set to the SIO P2 5 channel A 5 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Table A 2 D
388. error InitTimer TMR 2 TMR_SQWAVE TMR CLK BIN TMR CLK INTRN TMR OUT ENABLE OxFFFF TMR ENABLE Real Protected Mode No changes required FK AE RR AA IK RR IRR AA IRR IR AIR IRR IA k k k k k k k k k k k k k k k k k k k kk kkk k int InitTimer int Unit WORD Mode BYTE Inputs BYTE Output WORD InitCount int Enable BYTE TmpByte WORD TmrCntPort Me UNIE 2 return E INVALID DEVICE TmrCntPort 0 040 Unit Set depending on which timer Set Pin configuration if Unit 2 TmpByte _GetEXRegByte P3CFG Output lt lt Unit 77 BLS Q que _SetEXRegByte P3CFG TmpByte else TmpByte _GetEXRegByte PINCFG Output lt lt 5 Bit 5 _SetEXRegByte PINCFG TmpByte Set Timer Config TmpByte _GetEXRegByte TMRCFG All Timers share this register Keep previous settings 10 35 Intel386 EX EMBEDDED PROCESSOR USER S MANUAL intel if Enable TmpByte 0x80 Set Timer Disable Bit TmpByte Inputs lt lt Unit 2 Set CKnCON and GTnCON bits _SetEXRegByte TMRCFG TmpByte Set Timer Control Register TmpByte Unit lt lt 6 Set counter select TmpByte 0x30 Mode Set R W low then high byte and Mode bits _SetEXRegByte TMRCON TmpByte Set Initial Counter Value TmpByte HIBYTE InitCount SetEXRegByte TmrCntPort LOBYTE InitCount _SetEXRegByte TmrCntPort TmpByte return E_OK InitTimer RR K
389. es caled value of the processor clock or an external clock The counters contain two count formats binary and BCD and six different operating modes two of which are periodic Both hardware and software triggered modes exist providing for internal or external control The counter s out put signals can appear at device pins generate interrupt requests and initiate DMA transactions This chapter is organized as follows Overview see below CU Operation page 10 5 Register Definitions page 10 20 Programming Considerations page 10 33 10 1 OVERVIEW The TCU contains control logic and three independent 16 bit down counters Figure 10 1 Each counter has two input signals and one output signal CLKINn You can independently connect each counter s clock input CLKINn signal to either the internal prescaled clock PSCLK signal or the external timer clock TMRCLKn pin This allows you to use either a prescaled value of the processor s internal clock or an external clock to drive each counter NOTE The maximum CLKINn frequency whether connected internally or externally is 8 MHz GATEn Each counter has a gate GATEn input signal This signal provides counter operation control In some of the counter operating modes a high level on a counter s GATEn signal enables or resumes counting and a low level disables or suspends counting In other modes a rising edge on GATEn loads a new count value You can independently connect
390. escription of Signals Available at the Device Pins Sheet 5 of 6 Multiplexed With Signal Type Name and Description Alternate Function SMI ST System Management Interrupt Causes the device to enter System Management Mode SMI is the highest priority external interrupt SMIACT System Management Interrupt Active Indicates that the processor is in System Management Mode SRXCLK SSIO Receive Clock DTR1 In master mode the baud rate generator s output appears on SRXCLK and can be used to clock a slave transmitter In slave mode SRXCLK functions as an input clock for the receiver SSIORX SSIO Receive Serial Data RI1 Accepts serial data most significant bit first into the SSIO SSIOTX SSIO Transmit Serial Data RTS1 Sends serial data most significant bit first from the SSIO STXCLK lO SSIO Transmit Clock DSR1 In master mode the baud rate generator s output appears on STXCLK and can be used to clock a slave receiver In slave mode STXCLK functions as an input clock for the transmitter TCK Test Clock Input Provides the clock input for the test logic unit TDI Test Data Input Serial input for test instructions and data Sampled on the rising edge of TCK valid only when either the instruction register or a data register is being serially loaded TDO Test Data Output Serial output for test instructions and data TDO shift
391. eset the processor PH2 1 2 1 X 1 RESET 1 2467 01 Figure 8 2 Clock Synchronization In addition to internal synchronization a CLKOUT clock output is provided to enable external circuitry to maintain synchronization with the Intel386 EX processor Since it is one of the peripheral clock signals it remains active during idle mode but is driven low during power down mode 8 1 2 Power Management Logic The power management circuitry provides two power management modes Idle Mode Idle mode freezes the core clocks but leaves the peripheral clocks running Idle mode can reduce power consumption by about half depending on peripheral usage Powerdown mode Powerdown mode freezes both the core and peripheral clocks reducing current to leakage current microamps Peripherals that are clocked externally SIO Timers SSIO continue to run If inputs are toggling power consumption is higher To prepare for a power management mode program the power control register as described in Controlling Power Management Modes on page 8 8 then execute a HALT instruction The de 8 3 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel vice enters the programmed mode when the HALT cycle is terminated by a valid READY This READY may be generated either internally or externally A device reset an NMI or SMI or any unmasked interrupt request from the
392. etEXRegByte OCW1M SetEXRegByte OCW1M Mask MstrMask if SlaveMask 0 Mask _GetEXRegByte OCW1S _SetEXRegByte OCW1S Mask SlaveMask Disable8259Interrupt BORK KK KKK IK KK Kk Rok Ck Kk A ke Kk Ck Kk Ck ko Kk k CK Ck kk kk Kk k Kk KC Kk Ck AIR kk IA kk kc kk kk eek Enable8259Interrupt Description Enables 8259a interrupts for the master and the slave Parameters MstrMask Enable mask value for master ICU SlaveMask Enable mask value for slave ICU Each bit location that is set enables the corresponding interrupt by clearing the bit in the interrupt control register For example to enable master IR3 and IR5 set MstrMask 0x28 bits 3 and 5 are set Returns None Assumptions REMAPCFG register has Expanded I O space access enabled ESE bit set Syntax 9 37 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel ICU IRQ Mask Values define IRO 0 1 define IR1 0 2 define IR2 0 4 define 0 8 define IRA 0 10 define IR5 0x20 define IR6 0x40 define IR7 0x80 Enable8259Interrupts IR2 IRO IR7 Enable MasterIR2 for cascading Enable INT4 and WDTOUT on Slave Real Protected Mode No changes required Ck kk k Kk void Enable8259Interrupt BYTE MstrMask BYTE SlaveMask BYTE Mask if MstrMask 0 Mask GetEXRegByte OCW1M SetEXRegByte OCW1M Mask amp MstrMask if SlaveMask 0 Mask GetEXRegByte
393. etails on the instruction set 2 1 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Data Address Bus Interface 1 gt Chip select Unit JTAG Unit Address Clock and Power Management Unit Intel386 CX Core Core Enhancements A20 Gate CPU Reset quem DRAM Refresh Control Unit Watchdog Timer Unit Bus Monitor Asynchronous Serial I O 2 channels 16450 compatible Synchronous Serial I O 1 channel full duplex Timer counter Unit 3 channels 82C54 compatible Ports Interrupt Control Unit DMA Controller 2 channels 8237A compatible and Bus Arbiter Unit A2849 02 Figure 2 1 Intel386 EX Embedded Processor Block Diagram 2 2 intel 2 2 ARCHITECTURAL OVERVIEW INTEGRATED PERIPHERALS The Intel386 EX processor integrates both PC compatible peripherals Table 2 1 and peripherals that are specific to embedded applications Table 2 2 Table 2 1 PC compatible Peripherals Name Description Interrupt Consists of two 82C59A programmable interrupt controllers PICs configured as master Control Unit and slave You may cascade up to six external 82C59A PICs to expand the external ICU interrupt lines to 52 Refer to Chapter 9 INTERRUPT CONTROL UNIT Timer counter Provides three independent 16 bit down counters The programmable TCU is Unit TCU functionally equivalent to three 82C54 counter timers with enhancements to al
394. ether you prefer a response by phone or by fax Outside the U S and Canada please contact your local distributor 1 800 628 8686 U S and Canada 916 356 7599 U S and Canada 916 356 6100 fax U S and Canada Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 1 7 PRODUCT LITERATURE You can order product literature from the following Intel literature centers 1 800 548 4725 708 296 9333 44 0 1793 431155 44 0 1793 421333 44 0 1793 421777 8 1 0 120 47 88 32 U S and Canada U S from overseas Europe U K Germany France Japan fax only intel 2 ARCHITECTURAL OVERVIEW intel CHAPTER 2 ARCHITECTURAL OVERVIEW The Intel386 EX embedded processor Figure 2 1 is based on the static Intel386 SX processor This highly integrated device retains those personal computer functions that are useful in embed ded applications and integrates peripherals that are typically needed in embedded systems The Intel386 EX processor provides a PC compatible development platform in a device that is opti mized for embedded applications Its integrated peripherals and power management options make the Intel386 EX processor ideal for portable systems The integrated peripherals of the Inte1386 EX processor are compatible with the standard desktop PC This allows existing PC software including most of the industry s leading desktop and em bedded operating systems to be easily implemented on an Intel386 EX processor based pla
395. ew count was written to it the counter loads the new count on the next CLKINn pulse This allows GATEn to synchronize the counters Control Word 14H Count 4 Count 5 Writes to Counter n CLKINn GATEn OUTn i 1 1 0005 0004 0003 Ccount A2399 01 Figure 10 10 Mode 2 Writing a New Count 10 2 4 Mode 3 Square Wave In this periodic mode a counter s OUT signal remains high for half a specified count then goes low for the remainder of the count A count of N results in a square wave with a period of N CLKINnz pulses A high level on a counter s GATEn signal enables counting a low level on a counter s GATEn signal disables counting The output produced by a counter s OUTn signal de pends on whether a count is odd or even Mode 3 s basic operation for even and odd counts is outlined below and shown in Figure 10 11 and Figure 10 12 Even count basic operation 1 Aftera control word write OUTn is driven high 2 count is loaded on the CLKINn pulse following one of these events e A write to a control word followed by a write to count A gate trigger The counter reaches terminal count On each succeeding CLKINnz pulse the count is decremented by two After the count reaches terminal count OUTn is driven low and the count is reloaded On each succeeding CLKINn pulse the count is decremented by two After the count reaches terminal count OUTn is driven high and the count is rel
396. exist follow steps 3a and 3b a Attempt to resolve the pin configuration conflicts first In some cases you may find that using a different peripheral channel resolves the conflict b Attempt to resolve peripheral configuration conflicts If conflicts remain consider peripheral substitutions 5 5 CONFIGURATION EXAMPLE This section presents an example of a PC AT compatible configuration The last set of tables are blank you can use them as worksheets as you follow the steps in the configuration process 5 5 1 Example Design Requirements The example is a PC AT compatible design with the following requirements Interrupt Control Unit External interrupt inputs available at package pins INT1 0 INT7 4 Timer Control Unit Counters 0 1 Clock input is on chip programmable clock PSCLK no signals connected externally 5 28 intel DEVICE CONFIGURATION Counter 2 Clock input is on chip programmable clock PSCLK no signals connected to package pins DMA Unit Not Used Asynchronous Serial I O channel 0 5100 Clock input is the internal clock SERCLK RXDO TXDO connected to package pins Modem Signals connected internally Asynchronous Serial I O channel 1 SIO1 Clock input is the internal clock SERCLK Modem signals externally connected Synchronous Serial I O SSIO Not Used Chip Select Chip select signals CS6 CS5 1 UCS connected to package pins Core an
397. expanded address space is inaccessible The mode in which the interrupt controller recognizes a rising edge low to high transition on an interrupt request signal as an interrupt request The internal peripherals use edge triggered interrupt requests this is compatible with the PC AT bus specification External peripherals can use either edge triggered or level sensitive interrupt requests The addressing mode in which the internal timer interrupt controller serial I O ports and DMA controller are mapped into both the DOS address space and the expanded address space This mode decodes all 16 address bits All internal peripherals can be accessed in the expanded address space the internal timer interrupt controller serial I O ports and DMA controller can also be accessed in the DOS address space Addresses OF000H OFS8FFH All internal peripheral registers reside in this space The internal timer interrupt controller serial I O ports and DMA controller can also be mapped into DOS or PC AT address space Interrupt control unit The internal peripheral that receives interrupt requests from internal peripherals and external pins resolves priority and presents the requests to the CPU The ICU is functionally identical to two industry standard 82C59A programmable interrupt controllers connected in cascade The power conservation mode that freezes the core clocks but leaves the peripheral clocks running The delay between the
398. extern void Service RHBF void extern void Service THBE void ROR K K k k k k k k k k k k k k k k k k k Watch Dog Timer KAKAK RKKK kk ko ke ke ke e e KKK K define SetWatchDogReload ReloadHi ReloadLow SetEXRegWord WDTRLDL ReloadLow _SetEXRegWord WDTRLDH ReloadHi define WatchDogClockDisable _SetEXRegByte WDTSTATUS GetEXRegByte WDTSTATUS BITOMSK define WatchDogClockEnable _SetEXRegByte WDTSTATUS GetEXRegByte WDTSTATUS amp BITOMSK Watch Dog Timer Function Definitions extern void ReLoadDownCounter void extern DWORD GetWDT_Count void extern void WDT_BusMonitor BYTE EnableDisable extern void EnableWDTInterrupt void void interrupt far wdtISR void fk e eee eee Refresh Control Unit x xoc ke e e e e e e e e x x define EnableRCU _SetEXRegWord RDFSCON _GetEXRegWord RDFSCON 0x8000 define DisableRCU _SetEXRegWord RDFSCON _GetEXRegWord RDFSCON amp Ox7fff Refresh Control Unit Function Definitions extern int InitRCU WORD counter value extern WORD Get RCUCounterValue void RR KK kx x x KKK clock and Power Management Unit xoxc se ss A x f define IDLE 0x02 define PWDWN 0x01 define ACTIVE 0x00 Clock and Power Management Function Definitions extern int Set Prescale Value WORD prescale extern void Enter Idle Mode void extern void Enter Powerdown Mode void extern void Mode Setting To Active void C 13 intel D
399. f the right most 0 in the channel s mask the address block is repeated 2 4 times Also because there are no 1 s in the channel mask where there are 1 s in the channel address the channel address is the starting ad dress of the lowest active address block In this example each active 2 Kbyte address block in memory is followed by an inactive 2 Kbyte address block and each active address block starts at a 2 Kbyte boundary 14 7 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Maximum Memory Address 2633800H Active 26337FFH 2633000H 2613FFFH 2613800H Active 26137FFH 2613000H 2433FFFH 2433800H Active 24337FFH 2433000H 2432FFFH 2413800H Active 24137FFH 2413000H 14 8 intel Example 4 CHIP SELECT UNIT This example establishes two 16 Kbyte address blocks starting at OE08000H and 0 28000 16 Kbyte boundaries 15 bit Channel Address 15 bit Channel Mask Channel Active Address 15 1 001110001010000 000000001000111 25 00111000X010XXX XXXXXXXXXXX Because the least significant 0 in the channel mask is in bit position 4 this channel s active ad dress block size is 2 16 Kbytes Because there is 1 to the left of the right most 0 in the channel mask the address block is repeated 2 2 times Unlike the other examples there is a 1 in the channel mask where there is a 1 in the channel address For this reason the
400. fer a special case These address locations are not used to access any peripheral registers in a PC AT system The Intel386 SL microproces sor and other integrated PC solutions use them to enable extra address space required for config uration registers specific to these products On the Intel386 EX processor these address locations are used to hide the peripheral registers in the expanded I O space The expanded I O space can be enabled registers visible or disabled registers hidden The 16 bit register at I O location 22H can also be used to control mapping of various internal peripherals in I O address space This register REM APCEG is defined in Figure 4 3 The remap bits of this register control whether the internal PC compatible peripherals are mapped into the DOS I O space Setting the peripheral bit makes the peripheral accessible only in expand ed I O space Clearing the peripheral bit makes the peripheral accessible in both DOS I O space and expanded I O space To access the REMAPCFG register you must first enable the expanded I O address space as described in the next section At reset this register is cleared mapping in ternal PC AT compatible peripherals into DOS I O space 4 6 intel SYSTEM REGISTER ORGANIZATION Address Configuration Register Expanded Addr 0022 REMAPCFG PC AT Address 0022 Reset State 0000H 15 8 ESE Em 7 0
401. fer completes or is terminated The block data transfer mode is compatible with the single and autoinitialize buffer transfer modes but not with the chaining buffer transfer mode The chaining buffer transfer mode requires that the transfer information for the next buffer transfer be written to the channel before the current buffer transfer completes This is impossible with block data transfer mode because the channel only relinquishes control of the bus for DRAM refresh cycles during the buffer transfer The following flowcharts show the transfer process flow for a channel programmed for the block data transfer mode with the single Figure 12 11 and autoinitialize Figure 12 12 buffer transfer modes 12 18 intel DMA CONTROLLER After initialization the DMA channel is programmed with the requester and target addresses and a byte count DREQn active Yes DMA gains bus control DMA transfers one byte or word of data and decrements the byte count Byte count FFFFFFH or EOP active DMA channel relinquishes bus control Buffer transfer is complete so channel becomes idle Figure 12 11 Block Data transfer Mode with Single Buffer transfer Mode A2334 02 12 19 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel After initiallization the DMA channel is programmed with the requester and target addresses and a byte count DREQn _ active Yes DMA gains bus cont
402. ffer empty TBE flag At reset TBE and TE are set indicating that the transmit buffer and shift register are empty Writ ing data to the transmit buffer clears TBE and TE When the transmitter transfers data from the buffer to the shift register TBE is set Unless new data is written to the transmit buffer TE is set when the transmitter finishes shifting out the shift register s contents The transmitter s transmit buffer empty signal can be connected to the interrupt control and DMA units Figure 11 4 shows the process for transmitting data Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Select the BCLKIN source and the transmitter input baud rate Select the data frame Word length number of stop bits and type of parity Enable interrupts and or DMA Is transmit buffer empty Write data to transmit buffer register ISR or DMA cycle Transmitter transfers data to shift register and sets transmit buffer empty flag causing More an interrupt or DMA request Data to Transmit Transmitter shifts data frame onto the TXDn pin Data is transmitted least significant bit first Transmitter shifts out last stop bit then sets the transmitter empty flag A2527 02 Figure 11 4 SIOn Data Transmission Process Flow intel ASYNCHRONOUS SERIAL UNIT 11 2 3 SIOn Receiver The data frame for receptions is programmable and is identical to the data frame for transmis sions It
403. flects the current value of the baud rate down counter SSIOCON1 F486H SSIO Control 1 read write Enables the transmitter and receiver indicates when the transmit buffer is empty and the receive buffer is full Enables or disables the transmitter or receiver interrupts SSIOCON1 also indicates two error conditions the transmit underrun and receiver overflow SSIOCON2 F488H SSIO Control 2 read write Selects whether the transmitter and receiver are in master or slave mode In master mode the baud rate generator clocks the transmitter or receiver In slave mode an external master clocks the transmitter or receiver Also controls the enabling of the Automatic Transmit mode SSIOTBUF F480H SSIO Transmit Buffer read write Holds the 16 bit data word to transmit Data is transmitted most significant bit first SSIORBUF F482H SSIO Receive Buffer read only Holds the 16 bit data word received Data is received most significant bit first 13 16 intel SYNCHRONOUS SERIAL UNIT 13 3 1 Pin Configuration Register PINCFG The serial receive clock SRXCLK and transmit serial data SSIOTX pins are multiplexed with other functions Use PINCFG bits 0 and 1 to select the pin functions Pin Configuration Expanded Addr F826H PINCFG ISA Addr read write Reset State 00H 7 0 PM6 PM5 PM4 PM3 PM2 PM1 PMO Bit Bit i Number Mnemonic Function 7 Reserved T
404. following code example contains these software routines SerialWriteStr2 Located in SMRAM upon program execution this routine loops endlessly while writing a character X out the serial port on the EV386EX board Serial WriteStr Located in the main program in FLASH this routine loops endlessly while writing a string out the serial port before entering SMM InitSIO Initializes the serial port including the mode baud rate and clock rate MAIN Executes the program once it is located in FLASH It also configures chip selects copies SMM handler to SMRAM and loops endlessly until an SMI is issued See Appendix C for the included header files include 80386EX h include EV386EX h include lt string h gt include lt conio h gt include lt dos h gt if _DEBUG_ 0 _DEBUG_ must be defined on the command line define SIO_PORT SIO_1 The debugger uses SIO 0 for host communications else Under the debugger we must avoid using SIO O0 define 510 PORT SIO 0 endif define BAUD CLKIN 18432001 Clock rate of COMCLK i e External clocking extern char far SMMString extern void InitEXSystem void int DataSeg For assembly data segment register init BYTE Buf 20 RRR CK ke ke kk ke ke ke ke ke ke ke ke e ke ek Function SerialWriteStr2 KKKKKKKKKKKKKKKKKKKKKKKKKK Parameters None Returns None Assumptions Not called from main This function is used as a jump point and is relocated by the main to 380
405. for Receiving Data Using Interrupts 13 14 Receiver Master Mode Single Word Transfer 13 15 Pin Configuration Register PINCFG esee 13 17 SIO and SSIO Configuration Register 13 18 Clock Prescale Register CLKPRS 19 19 SSIO Baud rate Control Register SSIOBAUD 13 20 SSIO Baud rate Count Down Register 13 21 SSIO Control 1 Register SSIOCONY 1 esee 13 22 SSIO Control 2 Register 55 2 13 23 SSIO Transmit Holding Buffer 5 2 13 24 SSIO Receive Holding Buffer SSIORBUF 13 25 Channel Address Comparison esee 14 3 Determining a Channel s Address Block 51 14 4 Bus Cycle Length Adjustments for Overlapping 22 2 14 12 Pin Configuration Register PINCFG sese emm 14 15 Port 2 Configuration Register 2 eme 14 16 Chip select High Address Register CSnADH 14 17 Chip select Low Address Register CSnADL UCSADL 14 18 Chip select High Mask Registers CS
406. forced to 0 6 0 Connects GATEn to either the Voc pin or the TMRGATEnpin 1 Turns GATEn on or off depending on whether bits 1 3 and 5 are set or clear 5 0 With bit 6 clear Veg to GATE2 with bit 6 set GATE2 off 1 With bit 6 clear TMRGATE2 pin conn to GATE2 with bit 6 set GATE2 on 4 0 PSCLK connected to CLK2 1 TMRCLK2 connected to CLK2 3 0 With bit 6 clear Vcc to GATE1 with bit 6 set GATE1 turned off 1 With bit 6 clear TMRGATE 1 pin conn to GATE1 with bit 6 set GATE1 on 2 0 PSCLK connected to CLK1 1 TMRCLK1 connected to CLK1 1 0 With bit 6 clear Vcc to GATEO with bit 6 set GATEO turned off 1 With bit 6 clear TMRGATEO pin conn to GATEO with bit 6 set GATEO on 0 0 PSCLK connected to CLKO 1 TMRCLKO connected to CLKO 5 36 Table 5 11 TMRCFG Register Design Worksheet intel DEVICE CONFIGURATION Bit 4 INTCFG Value 7 0 CAS2 0 disabled to pins 1 CAS2 0 enabled from pins 6 0 SIOINT1 connected to master IR3 1 P3 1 connected to IR3 5 0 SIOINTO connected to master IR4 1 P3 0 connected to IRA 4 0 DMAINT connected to slave IR4 INT6 connected to slave IR5 1 INT6 connected to slave IR4 DMAINT connected to slave IR5 3 0 VSS connected to slave IR6 1 INT7 connected to slave IR6 2 0 Vgg connected to slave IR5 1 INT6 connected to slave IR5 1 0 SSIO Interrupt to slave IR1 1 INT5 connected to slave IR1 0 0 VS
407. formation is written to the channel Writing to the most significant byte of the target address clears this bit Note Outside chaining mode this bit becomes a don t care 0 CIO Chaining Interrupt 0 When set this bit indicates that new requester and target addresses and a new byte count should be written to channel 0 This bit is cleared when new transfer information is written to the channel Writing to the most significant byte of the target address clears this bit Note Outside chaining mode this bit becomes a don t care D 20 intel D 16 DMAMOD1 SYSTEM REGISTER QUICK REFERENCE DMA Mode 1 Expanded Addr DMAMOD1 ISA Addr 000BH write only Reset State 00H 7 0 DTM1 DTMO TI Al TD1 TDO 0 CS Bit Bit Number Mnemonic Function 7 6 DTM1 0 Data transfer Mode 00 Demand 01 Single 10 Block 11 Cascade 5 Tl Target Increment Decrement 0 Causes the target address to be incremented after each data transfer in a buffer transfer 1 Causes the target address for the channel specified by bit 0 to be decremented after each data transfer in a buffer transfer Note that it does not decrement words When decrementing it will do two byte transfers for a word Note When the target address is programmed to remain constant DMAMOD2 2 1 this bit is a don t care 4 Al Autoinitialize 0 Disables the autoinitialize b
408. forms the DOS op erating system and applications assume that only 1 Kbyte of the total 64 Kbyte I O address space is used The first 256 bytes addresses 00000H 00FFH are reserved for platform motherboard I O resources such as the interrupt and DMA controllers and the remaining 768 bytes addresses 0100H 03FFH are available for general I O peripheral card resources Since only 1 Kbyte of the address space is supported add on I O peripheral cards typically decode only the lower 10 address lines Because the upper address lines are not decoded the 256 platform address locations and the 768 bus address locations are repeated 64 times on 1 Kbyte boundaries covering the entire 64 Kbyte address space See Figure 4 1 Generally add on I O peripheral cards do not use the I O addresses reserved for the platform re sources Software running on the platform can use any of the 64 repetitions of the 256 address locations reserved for accessing platform resources 4 2 intel SYSTEM REGISTER ORGANIZATION FFFFH 64K General Slot I O FCOOH 63K FDOOH Platform I O Reserved OCOOH 3k General Slot I O 0900H Platform I O Reserved 0800H 2K General Slot I O 0500H Platform I O Reserved 0400H 1K General Slot I O 0100H 256 Platform I O Reserved 0000 0 A2498 01 Figure 4 1 PC AT I O Address Space 10 bit Decode 4 3 EXPANDED I O ADDRESS SPACE The Intel386 E
409. g Timer Unit OFACOH OF4CFH Asynchronous Serial I O Channel 0 COM1 OF4F8H OF4FFH Clock Generation and Power Management Unit OF800H OF80FH External Internal Bus Interface Unit OF810H OF81FH Chip Configuration Registers OF820H OF83FH Parallel I O Ports OF860H OF87FH Asynchronous Serial I O Channel 1 COM2 OF8F8H OF8FFH Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 4 5 ADDRESS DECODING TECHNIQUES One of the key features of the Intel386 EX processor is that it is configurable for compatibility with the standard PC AT architecture In a PC AT system the platform I O resources are located in the slot 0 I O address space For the Intel386 EX processor this means that PC AT compatible internal peripherals should be reflected in slot 0 of the I O space for DOS operating system and application software to access and manipulate them properly This discussion leads to the concepts of DOS I O space and expanded I O space DOS I O Space DOS I O space refers to the lower Kbyte of I O addresses where only PC AT compatible peripherals can be mapped Expanded I O Space Expanded I O space refers to the top 4 Kbytes of I O addresses where all peripheral registers are physically located The remainder of this section explains how special I O address decoding schemes manipulate register addresses within these two I O spaces 4 5 1 Address Configuration Register I O address locations 22H and 23H in DOS I O space of
410. g buffer empty signal SSTBE 100 TCU counter 1 s output signal OUT1 101 SIO channel 1 s receive buffer full signal RBFDMA1 110 SIO channel 0 s transmit buffer empty signal 111 SSIO receive holding buffer full signal SSRBF 12 32 Figure 12 19 DMA Configuration Register DMACFG CONTROLLER intel 12 3 3 Channel Registers To program channel s requester and target addresses and its byte count write to the DMA channel registers Some of the channel registers require the use of a byte pointer BP flip flop to control the access to the upper and lower bytes After you write or read a register that requires a byte pointer specification the DMA toggles the byte pointer For example writing to DMAOTARO with BP 0 causes the DMA to set BP The clear byte pointer software command DMACLRBP is available so that you can force BP to a known state 0 before writing to the channel registers Issue DMACLRBP by writing to location FOOCH or 000 the data written to the location doesn t matter writing to the location is all that is necessary to cause the DMA to clear the byte pointer DMA Channel 0 Requester Address Target Address Byte Count Requester Address Target Address Byte Count 24 16 8 0 DMAOREQS3 DMAOREQ2 DMAOREQ1 DMAOREQO F011H BP 1 24 F011H BP 0 16 F010H BP 1 8 F010H BP 0
411. g edge of SMI to the first ADS where SMIACTS is active see Fig ure 7 2 SMI 1 2 3 4 5 1 1 1 Interrupts Interrupts Blocked Blocked gt 9 1 SMI Latency lt 2nd SMI is blocked A2510 02 Figure 7 1 Standard SMI The SMM handler may optionally enable the NMI interrupt but NMI is disabled when the SMM handler is entered Note that the CPU does not recognize NMI while executing the SMM State Save sequence or SMM State Resume sequence NMI is always enabled following the comple tion of the first interrupt service routine ISR or exception handler Even when the processor is in SMM address pipelined bus cycles can be performed correctly by asserting NA Pipelined bus cycles can also be performed immediately before and after SMI ACT assertion The numbers in Figure 7 2 also reflect a pipelined bus cycle 7 5 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel CLK2 CLKOUT SMI ADS READY SMIACT State Save SMM Handler Normal State State Restore Normal State A 21 CLK min B 20 CLK min C 16 CLK min D 4 CLK min A2512 02 Figure 7 2 SMIACT Latency NOTE Even if bus cycles are pipelined the minimum clock numbers are guaranteed 7 6 intel SYSTEM MANAGEMENT MODE 7 3 2 1 SMI P
412. g the one shot On the CLKINnz pulse following the retrigger the counter reloads the count The control logic then decrements the count on each succeeding CLKINnz pulse OUTn remains low until the count reaches zero Control Word 12H Count 3 1 Writes to Counter n CLKINn GATEn OUTn Count A2396 01 Figure 10 6 Mode 1 Retriggering the One shot 10 9 Intel386 EX EMBEDDED PROCESSOR USER S MANUAL intel Figure 10 7 shows writing a new count The counter waits for a gate trigger to load the new count The counter loads the new count on the CLKINn pulse following the trigger then decrements the count on each succeeding CLKINn pulse OUT remains low until the count reaches zero Control Word 12H Count 2 Count 4 Writes to 1 1 1 1 1 Counter n 1 1 1 1 CLKINn GATEn OUTn Count 2397 02 Figure 10 7 Mode 1 Writing a New Count 10 2 3 Mode 2 Rate Generator In this periodic mode a counter s OUTn signal remains high until the count reaches one then goes low for one clock pulse CLKINn After this single clock pulse OUTn goes high and the count is reloaded The cycle then repeats You can use a gate trigger to reload the count at any time This provides a way to synchronize the counting cycle A high level on a counter s GATEn signal enables counting a low level on a counter s GATEn signal disables counting Mode 2 s basic operation is outlined
413. g the periph erals Unlike the RESET pin which is asynchronous and can be used to synchronize internal clocks to CLK2 this core only reset is synchronized with the on chip clocks and does not affect the on chip clock synchronization After the CPU RESET this bit is still set to 1 It must be intel cleared and then set to cause another core only reset Clearing bit 1 in the PORT92 register forces address line A20 to 0 This bit affects only addresses generated by the core addresses generated by the DMA and the refresh control unit are not af fected Port 92 Configuration PORT92 read write 7 Expanded Addr F092H ISA Addr 0092H Reset State XXXXXX10B 0 A20G CPURST Bit Bit Number Mnemonic Function 7 2 Reserved These bits are undefined for compatibility with future devices do not modify these bits 1 A20G A20 Grounded 0 Clearing this bit forces address line A20 to 0 This bit affects addresses generated only by the core Addresses generated by the DMA and the Refresh Unit are not affected by this bit 1 Setting this bit leaves core generated addresses unmodified 0 CPURST CPU Reset 0 Clearing this bit performs no operation 1 Setting this bit resets the core without resetting the peripherals This bit must be cleared before issuing another reset Figure 5 14 Port 92 Configuration Register PORT92 5 22 D
414. ge 14 13 Design Considerations page 14 21 Programming Considerations page 14 22 14 1 OVERVIEW Each chip select channel consists of address and mask registers and an output signal The address and mask registers allow you to define memory or I O address blocks for each channel You also specify whether or not the chip select is activated when the processor is operating in system man agement mode When the processor accesses a channel s address block the CSU activates the channel s output signal Connecting a channel s output to a memory or I O device simplifies memory and I O interfacing by removing the need for and delay of decoding addresses externally NOTE Chip select channels are not activated during interrupt acknowledge cycles and halt and shutdown cycles 14 1 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 14 2 CSU UPON RESET Upon reset of the processor only the UCS channel is enabled and all other chip selects are dis abled UCS is enabled for the entire memory space of the processor The UCS region is initialized upon reset with the following settings e Mask set to 7FFFH CM25 11 in UCSMSKH and UCSMSKL registers CMSMM set 16 bit bus size Memory access External READY ignored 15 wait states With all the UCS mask bits set to 1 the UCS pin is active for the entire 64 MBytes of the pro cessor s memory address space The UCS region can be programmed for a smaller size during initial
415. ge pin 5 PM5 Pin Mode 0 Selects the coprocessor signals PEREQ BUSY and ERROR Z at the package pins 1 Selects the timer control unit signals TMROUT2 2 and TMRGATE2 at the package pins 4 PM4 Pin Mode 0 Selects DACKO at the package pin 1 Selects CS5 at the package pin 3 PM3 Pin Mode 0 Selects EOP at the package pin 1 Selects CTS1 at the package pin 2 PM2 Pin Mode 0 Selects DACK1 at the package pin 1 Selects TXD1 at the package pin 1 PM1 Pin Mode 0 Selects SRXCLK at the package pin 1 Selects DTR1 at the package pin 0 PMO Pin Mode 0 Selects SSIOTX at the package pin 1 Selects RTS1 at the package pin Figure 11 7 Pin Configuration Register PINCFG 11 17 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Use bits 4 0 to connect 5100 signals to package pins Port 1 Configuration Expanded Addr F820H P1CFG ISA Addr read write Reset State 00H 7 0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PMO Bit Bit Functi Number Mnemonic unc Hon 7 PM7 Pin Mode 0 Selects P1 7 at the package pin 1 Selects HLDA at the package pin 6 PM6 Pin Mode 0 Selects P1 6 at the package pin 1 Selects HOLD at the package pin 5 PM5 Pin Mode 0 Selects P1 5 at the package pin 1 Selects LOCK at the package pin 4 PM4 Pin Mode 0 Selects P1 4 at t
416. ge pins The Internal Connection Logic provides three kinds of connections Connections between peripherals Connections to package pins via multiplexers Direct connections to package pins without multiplexers The internal connection logic is controlled by the Peripheral A configuration register Each pin multiplexer Pin Mux connects of two internal signals to a pin One is a periph eral signal The second signal can be an I O port signal or a signal from to another peripheral The pin multiplexers are controlled by the pin configuration registers Some input only pins without multiplexers Shared Pins w o Muxes are routed to two different peripherals Your design should use only one of the inputs and disable or ignore the input going to the second peripheral Together the peripheral configuration registers and the pin configuration registers allow you to select the peripherals to be used to interconnect them as your design requires and to bring se lected signals to the package pins Peripherals B C D Microprocessor Muxes Peripheral A Internal Connection Shared Pins Logic Control w o Muxes Peripheral A Configuration Register Control Pin Configuration Registers A2535 01 Figure 5 1 Peripheral and Pin Connections 5 2 intel DEVICE CONFIGURATION 5 2 PERIPHERAL CONFIGURATION This section describes the configuration of each on chip peripheral For more detailed informa
417. gister last This ensures that all other bits are properly programmed before the region is enabled When reprogramming the channel always disable the channel before changing anything else Achip select channel is enabled by setting bit 0 of its Chip Select Low Mask register and its output signal is connected to the package pin by setting or clearing the appropriate PINCFG or P2CFG register bit The PINCFG and P2CFG registers are shown in Figures 14 4 and 14 5 The minimum address block for memory address configured channels is 2 Kbytes and for I O address configured channels is 2 bytes The size of these address blocks can be increased by powers of 2 Kbytes for memory addresses and by powers of 2 bytes for I O addresses Achannel s address block of size n always starts on an n address boundary 14 6 1 Chip Select Unit Code Example This following code example initializes the UCS and CS4 channels of the CSU See Appendix C for the included header files include lt conio h gt include 80386ex h include EV386EX h Description Initialize Chip Select Unit for UCS Start address is 00H Region size is 512 Kbytes 0 wait states Upper chip select is Enabled 16 bit data bus size in memory space External bus ready is Disabled SMM region is accessible during SMI access and memory access CS4 Start address is 080000H Region size is 512 Kbytes 0 wait states Chip select 4 is Enabled 16 bit data bus size in
418. gisters to support the 26 bit address bus and uses 24 bit byte count registers to support larger data blocks than are possible with the 8237A However each channel can be configured to look like an 8237A with page registers 1 16 bit address and byte count registers Chapter 12 CONTROLLER describes the DMA unit s features in detail While the internal DMA offers a comprehensive set of features to meet the needs of most embed ded applications strict DOS compatibility may be critical to some A PC AT compatible system s Basic Input Output System BIOS only uses the DMA for floppy disk access Since both MS DOS and Microsoft Windows make calls to the BIOS for disk access it is possible to modify the BIOS The floppy disk controller allows data transfers to occur using DMA Polling or Inter rupt based A few BIOS vendors have implemented the transfers using polling for disk transfers Some programs bypass the BIOS and go directly to the hardware typically these are disk inten sive programs like hard disk backup software or disk management software If more DMA channels are required for compatibility external controllers could be added The Intel386 EX processor s flexible address remapping scheme enables you to map the internal out of the DOS I O space and then connect an external 8237A to achieve PC AT compati bility The internal DMA can still be used for other non DOS related functions B 1 2 Industry S
419. h Mask Expanded Addr F406H F40EH CSnMSKH 0 6 UCSMSKH F416H F41EH F426H F42EH F436H F43EH ISA Addr Reset State 0000H CS nMSKH FFFFH UCSMSKH 15 8 CM15 CM14 7 0 CM13 CM12 CM11 CM10 CM9 CM8 CM7 CM6 Bit Bit i Number Mnemonic Function 15 10 Reserved for compatibility with future devices write zeros to these bits 9 0 CM15 6 Mask Value Upper Bits Defines the upper 10 bits of the channel s 15 bit mask The mask bits CM15 6 and the address bits CA15 6 form a masked address that is compared to memory address bits A25 16 or I O address bits A15 6 intel SYSTEM REGISTER QUICK REFERENCE 0 6 CSnMSKL UCSMSKL Chip select Low Mask Expanded Addr F404H FA0CH CSnMSKL n 0 6 UCSMSKL F414H F41CH read write F424H FA2CH F434H F43CH ISA Addr Reset State 0000H CSnMSKL FFFFH UCSMSKL 15 8 5 CM4 CM3 CM2 1 CMSMM 7 0 CSEN Bit Bit i Number Mnemonic Function 15 11 CM5 1 Chip select Mask Value Lower Bits Defines the lower 5 bits of the channel s 15 bit mask The mask bits CM5 1 and the address bits CA5 1 form a masked address that is compared to memory address bits A15 11 or I O address bits A5 1 10 CMSMM SMM Mask Bit 0 The SMM address bit is not masked 1 Masks the SMM address bit in the channel s Chip Select Low Address registe
420. h Pad SCR1 OF8FFH 02FFH An 8 bit read write register available for use as a scratch pad has read write no effect on SIOn operation For PC compatibility the SIO unit accesses its 11 registers through 8 I O addresses The RBRn TBRz and registers share the same addresses and the and DLHn registers share the same addresses Bit 7 DLAB of the LCRn determines which register is accessed during a read or write operation Table 11 6 Table 11 6 Access to Multiplexed Registers Register Accessed Expanded Address PC AT Address DLAB 0 DLAB 1 OF4F8H read 03F8H read RBRO DLLO OFAF8H write 03F8H write TBRO DLLO OF4F9H read write OSF9H read write IERO DLHO OF8F8H read 02F8H read RBR1 DLL1 OF8F8H write 02F8H write 1 DLL1 OF8F9H read write 02 read write IER1 DLH1 11 16 intel ASYNCHRONOUS SERIAL UNIT 11 3 1 Pin and Port Configuration Registers PINCFG and PnCFG n 1 3 Use PINCFG bits 2 0 to connect the SIO1 signals to package pins Pin Configuration Expanded Addr F826H PINCFG ISA Addr read write Reset State 00H 7 0 PM6 PM5 PM4 PM3 PM2 PM1 PMO Bit Bit Number Mnemonic Function 7 Reserved This bit is undefined for compatibility with future devices do not modify this bit 6 PM6 Pin Mode 0 Selects CS6 at the package pin 1 Selects REFRESH at the packa
421. h gt pragma warning disable 4704 Disable optimization warning RRR IKK KKK IK KK I RR KIA IRR IR AR IRR IR AR IRR IA k k k k k k k A k k k k k k k ek EnableDMAHWRequests int EnableDMAHWRequests int nChannel Description Enables channel hardware requests for the given DMA channel Parameters nChannel channel to enable hardware requests Returns Error Code Assumptions None Syntax int error code error code EnableDMAHWRequests DMA Channel0 Real Protected Mode No changes required Ck AC k RIA ARR kk k k k k k k k k int EnableDMAHWRequests int nChannel BYTE regDMAMSK 0 Clear regDMAMSK HRM Check input if nChannel DMA 10 amp amp nChannel DMA_Channell return ERR_BADINPUT regDMAMSK nChannel Set regDMAMSK CS to channel _SetEXRegByte DMAMSK regDMAMSK Clear hardware request mask for 12 52 intel DMA CONTROLLER given channel BRK RK KK RI KK IR IRR RA IRR kk Kk k CK Ck Ck kk KC Kk k CK Ck Ck IA k k k k k k k k kk ko k k k k k k OK DisableDMAHWRequests Description Disables channel hardware requests for the given DMA channel The channel however can still receive software requests Parameters nChannel channel to mask hardware requests Returns Error Code Assumptions None Syntax int error code error code DisableDMAHWRequests DMA Channel0 Real Protected Mode No cha
422. h other or with I O ports This ensures maximum use of available pins and maintains a small package Each multiplexed pin is individually programmable for peripheral or I O function Refer to Chapter 16 INPUT OUTPUT PORTS Watchdog When enabled the WDT functions as a general purpose 32 bit timer a software timer or a Timer WDT bus monitor Refer to Chapter 17 WATCHDOG TIMER UNIT Unit JTAG Test The test logic unit simplifies board level testing Consists of a test access port and a logic Unit boundary scan register Fully compliant with Standard 1149 1 1990 EEE Standard Test Access Port and Boundary Scan Architecture and its supplement Standard 1149 1a 1993 Refer to Chapter 18 JTAG TEST LOGIC UNIT 2 4 intel 3 CORE OVERVIEW CHAPTER 3 CORE OVERVIEW The Intel386 EX processor core is based upon the Intel386 CX processor which is an enhanced version of the Intel386 SX processor This chapter describes the Intel386 CX processor enhance ments over the Intel386 SX processor internal architecture of the Intel386 CX processor and the core interface on the Intel386 EX processor This chapter is organized as follows ntel386 CX Processor Enhancements see below Intel386 CX Processor Internal Architecture page 3 2 Core Inte1386 EX Processor Interface page 3 6 3 1 Intel386 CX PROCESSOR ENHANCEMENTS The Intel386 CX processor based on the Intel386 SX processor adds system management
423. h registers share address ports with other SIO registers Bit 7 DLAB of intel SYSTEM REGISTER QUICK REFERENCE 0 8 DMABSR DMA Bus Size Expanded Addr F018H DMABSR ISA Addr write only Reset State X1X10000B 7 0 RBS TBS 0 CS Bit Function Number Mnemonic Reserved for compatibility with future devices write zero to this bit 6 RBS Requester Bus Size Specifies the requester s data bus width for the channel specified by bit 0 0 16 bit bus 1 8 bit bus Reserved for compatibility with future devices write zero to this bit TBS Target Bus Size Specifies the target s data bus width for the channel specified by bit 0 0 16 bit bus 1 8 bit bus Must be 0 for correct operation Channel Select 0 The selections for bits 7 4 affect channel 0 1 The selections for bits 7 4 affect channel 1 D 13 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel D 9 DMACFG 7 DMA Configuration DMACFG read write Expanded Addr F830H ISA Addr Reset State 00H 0 D1MSK D1REQ2 D1REQ1 D1REQO DOMSK DOREQ2 DOREQ1 DOREQO Bit Number Bit Mnemonic Function 7 D1MSK DMA Acknowledge 1 Mask 0 channel 1 s acknowledge DMAACK1 signal is not masked 1 Masks DMA channel 1 s acknowledge DMAACK1 signal Useful
424. handler must determine which of the status signals caused the interrupt by read ing bits 1 and 2 of the IIRz register Table 11 4 When more than one status signal is enabled as an interrupt source and two or more are active at the same time then the source of the interrupt is based on a fixed priority scheme Table 11 4 Table 11 4 Status Signal Priorities and Sources Interrupt ID Register Priority Status Signal Activated By Bit2 Bit1 BitO 1 Highest Receiver Line Status overrun error parity error framing error or 1 0 break condition 2 Receive Buffer Full the receiver transferring data from its shift register to its buffer 3 Transmit Buffer Empty the transmitter transmitting data from its transmit buffer to its transmit shift register 4 Lowest Modem Status a change on any of the modem control 0 0 0 input signals CTSn DCDn DSRn and Rin 11 2 6 2 SIO DMA sources The transmit and receive channel on each SIO is supported by both DMA channels The receiver buffer full and transmit buffer empty signals of the line status register are brought out as RBFDMAn and TXEDMAn The TXEDMAz signal is connected directly to the multiplexers controlling the source of DREQn for each of the two DMA channels The RBFDMAz signal is also connected to the DREQn muxes but it is qualified by the LSR error conditions so that the DMA request is blocked if an error has occurred in the recept
425. haracter SetEXRegWord SSIOTBUF Ch Enable Transmitter SetEXRegByte SSIOCON1 SSControl SSIO TX ENAB Wait until Transmit Holding Buffer is empty while GetEXRegByte SSIOCON1 amp SSIO THBE for i 0 i 4000 1 Delay so transmit begins before disable asm nop Disable Transmitter _SetEXRegByte SSIOCON1 SSControl else Slave Transmitter MUST already be Enabled Wait until Transmit Holding Buffer is empty while GetEXRegByte SSIOCON1 amp SSIO THBE SetEXRegWord SSIOTBUF Ch Write to Buffer SSerialWriteWord ROR KK KKK I KK KK RRR IK IR ARR Kk KC IA ARR Kk KC A IA CK Ck k k k k k k k k k k kk ke ke k k eek SSIO ISR Description Interrupt Service Routine for SSIO generated interrupts This ISR identifies the cause of the interrupt and calls the appropriate routine Parameters None Returns None Assumptions It is assumed that the Slave 8259 is operating in Fully Nested Mode If the Slave were in SMM a Specific EOI would have to be sent to the 13 30 intel SYNCHRONOUS SERIAL I O UNIT Slave to clear the in service bit It is also assumed that the Master is not operating in AEOI SFNM or SMM If the Master were in SMM or SFNM a Specific EOI would have to be used On the other hand if the Master were operating in AEOI mode no EOI signal would have to be sent Syntax Not called by user Real Protected Mode No changes r
426. hdog is unnecessary Chapter 8 CLOCK AND POWER MAN AGEMENT UNIT discusses idle mode Bus monitor mode protects normally not ready systems from ready hang conditions A normally not ready system is one in which a bus cycle continues until the accessed device asserts 17 1 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel READY In bus monitor mode the ADS signal from the bus interface unit reloads the down counter and the READY signal stops it The READY signal can be generated either ex ternally or internally using the WDTRDY bit in the PWRCON register Figure 17 5 If this bit is deasserted then an external READY f is required to terminate the cycle when the WDT times out WDTOUT is asserted in Bus Monitor mode In this case if a READY is never generated by external logic the processor hangs since the bus cycle never terminates If the WDTRDY bit is set the processor generates an internal READY to terminate the cycle upon time out WDTOUT is asserted in Bus Monitor mode The WDT circuitry correctly matches each READY with a corresponding ADS even in pipe lined mode when two ADS pulses occur before the first READY pulse Reload Registers womud 7 WDTRLDL 32 Bit Down Counter WDTCNTH WDTCNTL 8 State ae WDTOUT ounter 1e Connect WDTCLR to NMI or RESET WDTSTATUS WDTOUT to IR7 of Slave 8259A A2330 02 Figure 17 1 Watchdog Timer Un
427. he processor to enter System Management Mode intel CLOCK AND POWER MANAGEMENT UNIT 8 2 CONTROLLING THE PSCLK FREQUENCY The PSCLK signal can provide a 50 duty cycle prescaled clock to the timer counter and SSIO units This feature is useful for providing various frequencies including a 1 19318 MHz output for a PC compatible system timer or speaker tone generator Determine the required prescale val ue using the following formula then write this value to the CLKPRS register Figure 8 4 internal clock frequency CLK2 2 Prescale value 2 desired PSCLK frequency Clock Prescale Register Expanded Addr F804H CLKPRS ISA Addr read write Reset State 0000H 15 8 PS8 7 0 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PSO Bit Bit i Number Mnemonic Funcuon 15 9 Reserved These bits are undefined for compatibility with future devices do not modify these bits 8 0 PS8 0 Prescale Value These bits determine the divisor that is used to generate PSCLK Legal values are from 0000H divide by 2 to O1FFH divide by 513 divisor PS8 0 2 Figure 8 4 Clock Prescale Register CLKPRS To change the frequency of PSCLK write a new value to the CLKPRS register The new frequen cy takes effect at the first high to low transition of PSCLK after CLKPRS has been changed Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 8 3 CONTROLL
428. he DMA are selected by the DMA configu ration register Figure 5 3 5 2 1 3 Using The Timer To Initiate DMA Transfers A timer output OUT2 can initiate periodic data transfers by the DMA A DMA channel is programmed for the transfer then a timer output pulse triggers the transfer The most useful DMA and timer combinations for this type of transfer are the periodic timer modes mode 2 and mode 3 with the DMA block transfer mode programmed See Chapter 10 TIMER COUNTER UNIT and Chapter 12 DMA CONTROLLER for more information on how to program the peripherals 5 2 1 4 Limitations Due To Pin Signal Multiplexing Pin signal multiplexing can preclude the simultaneous use of a DMA channel and another periph eral or specific peripheral signal see Figure 5 2 For example using DMA channel 1 with an external requester device precludes using SIO channel 1 due to the multiplexed signal pairs DRQI RXDI and DACKIZ TXDI Please refer to the Intel386TM EX Microprocessor Pin Mul tiplexing Map Order Number 272587 for a complete diagram of multiplexed signals 5 4 intel DEVICE CONFIGURATION DMACFG 2 0 DRQO g RBFDMAO SIO0 To SIO1 DCD1 SIO1 SSTBE SSIO OUT1 TCU RBFDMA1 5101 TXEDMAO 5100 SSRBF SSIO DMACFG 3 0 PINCFG 4 DMAACKO From CSU CS5 DMACFG 6 4 DRQ1 RBFDMA1 5101 RXD1 TXEDMAO 5100 SSRBF SSIO OUT2 TCU RBFDMAO
429. he SMM driver code in read only storage as long as the address space between 03FEOOH and 03FFFFH is writable The Intel386 EX processor does not support SMRAM relocation Bit 17 of the SMM Revision Identifier see SMRAM State Dump Area on page 7 14 indicates whether the processor sup 7 2 intel SYSTEM MANAGEMENT MODE ports the relocation of SMRAM When this bit is set 1 the processor supports SMRAM reloca tion When this bit is cleared 0 then the processor does not support SMRAM relocation Since this device doesn t support SMRAM relocation bit 17 of the SMM Revision Identifier is cleared The SMRAM address space is fixed from 38000H to 3FFFFH 7 3 SYSTEM MANAGEMENT MODE PROGRAMMING AND CONFIGURATION 7 3 1 Register Status During SMM When the CPU recognizes SMI on an instruction boundary it waits for all write cycles to com plete and asserts the SMIACT pin The processor then saves its register state to SMRAM space and begins to execute the SMM handler The RSM instruction restores the registers deasserts the SMIACT pin and returns to the user program Upon entering SMM the processor s PE MP EM TS and PG bits in CRO are cleared as shown in Table 7 1 Table 7 1 CRO Bits Cleared Upon Entering SMM CRO Bit Mnemonic Description Function 0 PE Protection Enable 0 protection disabled 1 protection enabled 1 MP Math Coprocessor Present 0 coprocessor not present 1 coproces
430. he baud rate count value and forces the baud rate clock to zero 6 0 BV6 0 Baud rate Value The baud rate value BV is the reload value for the baud rate generator s seven bit down counter The baud rate generator s output is a function of BV and the baud rate generator s input BCLKIN as follows BCLKIN baud rate output frequency Hz q y H2 2BV 2 Hz If you know the desired output baud rate frequency you can determine BV as follows BV 1 2 x baud rate output frequency D 58 intel D 59 SSIOCON1 SYSTEM REGISTER QUICK REFERENCE SSIO Control 1 SSIOCON1 read write 7 Expanded Addr ISA Addr Reset State F486H COH TUE THBE TIE TEN RHBF RIE REN ROE Bit Number Bit Mnemonic Function 7 TUE Transmit Underrun Error The transmitter sets this bit to indicate a transmit underrun error in the TEN transfer mode Clear this bit to clear the error flag If a one is written to TUE it is ignored and TUE retains its previous value THBE read only bit Transmit Holding Buffer Empty The transmitter sets this bit when the transmit buffer contents have been transferred to the transmit shift register indicating that the buffer is now ready to accept new data Writing data to the transmit buffer clears THBE When this bit is clear the buffer is not ready to accept any new data TIE Transm
431. he core stops processing the lower level request processes the higher level request then returns to finish the lower level request The special fully nested mode allows higher or equal level IR signals to have higher interrupt priority In this mode if the core is processing an interrupt a higher or equal level interrupt request is passed through to the core Also since all interrupts from the slave are directed into a single IR line IR2 on the master the master does not know the priorities of the slave interrupts it receives this mode enables a higher level interrupt on the slave to interrupt the 9 7 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel processing of a lower level slave interrupt The special fully nested mode is generally used by the master in a cascaded system Special mask In some applications you may want to allow lower level requests interrupt the processing of higher level interrupts The special mask mode supports these applications Unlike the special fully nested and fully nested modes which are selected during ICU initialization the special mask mode can be enabled and disabled during program operation When special mask mode is enabled only interrupts from the source currently in service are inhibited All other interrupt requests of both higher or lower levels are passed on When the internal slave receives an interrupt request it passes that request to the master The mas ter receives al
432. he interrupt control unit s SIOINTn interrupt request signal using the interrupt enable register IER If you receive an interrupt request on the SIOINTn signal read the interrupt ID register to determine which status signal with the highest priority caused the request Several sources can activate the receiver line status and the modem status signals If indicates that the receiver line status signal caused an interrupt request read the serial line status register LSRn to determine the receive error condition that activated the receiver line status signal If IRn indicates that the modem status signal caused an interrupt request read the modem status register MSRn to determine which modem input signal activated the modem status signal DMA can be used for servicing the SIO channels for higher baud rates When doing this remember that the isolated RBF and TBE RBFDMA and TBEDMA signals are connected to the DMA DREQ inputs RBFDMA is blocked if any of the error bits in the LSR are set Neither signal is gated by the IERz register 11 32 intel ASYNCHRONOUS SERIAL UNIT 11 4 1 Asynchronous Serial I O Unit Code Examples The code example contains these software routines InitSIO Initializes the SIO for asynchronous transfers SerialReadStr Polled serial read function that reads a specified number of characters SerialRead Char Polled serial read function that reads a single character SerialWriteChar Polled serial
433. he interrupts ICU initialization Interrupt Service Routine etc Unmask the interrupts on the ICU Initialize SSIO Read Data SSIORBUF Error Routine A3396 01 Figure 13 12 Receive Data by Polling 13 13 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel SSIO Receiver Causes Interrupt Disable Interrupts While Receiving Data Read Data From Buffer SSIORBUF Error Routine Enable Interrupts Exit Interrupt Service Routine A3397 01 Figure 13 13 Interrupt Service Routine for Receiving Data Using Interrupts 13 14 intel SYNCHRONOUS SERIAL I O UNIT If the receiver is disabled while a data value is being shifted into the shift register it continues running until the last bit is shifted in Then the shift register is loaded into the buffer register the shift register stops and the clock pin SRXCLK is three stated if in the master mode If the receiver is disabled then enabled before the current word has been shifted in it continues as if it were never disabled Figure 13 14 shows the serial receive data SSIORX pin values for a master mode single word transfer For single word transfers it is necessary to enable the receiver thus starting the shifting process then disable the receiver before 16 bits are shifted in A ON A N55 NN Generator Clock i 1 1 1 Receiver Enable _ d i 1 Float i Float
434. he package pin 1 Selects RIO at the package pin 3 PM3 Pin Mode 0 Selects P1 3 at the package pin 1 Selects DSRO at the package pin 2 PM2 Pin Mode 0 Selects P1 2 at the package pin 1 Selects DTRO at the package pin 1 PM1 Pin Mode 0 Selects P1 1 atthe package pin 1 Selects RTSO at the package pin 0 PMO Pin Mode 0 Selects P1 0 at the package pin 1 Selects DCDO at the package pin Figure 11 8 Port 1 Configuration Register P1CFG 11 18 intel ASYNCHRONOUS SERIAL UNIT Use P2CFG bits 7 5 to connect SIOO signals to package pins Port 2 Configuration Expanded Addr F822H P2CFG ISA Addr read write Reset State 00H 7 0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PMO Bit Bit Function Number Mnemonic 7 PM7 Pin Mode 0 Selects P2 7 at the package pin 1 Selects CTSO at the package pin 6 PM6 Pin Mode 0 Selects P2 6 at the package pin 1 Selects TXDO at the package pin 5 PM5 Pin Mode 0 Selects P2 5 at the package pin 1 Selects RXDO at the package pin 4 PM4 Pin Mode 0 Selects P2 4 at the package pin 1 Selects CS4 at the package pin 3 PM3 Pin Mode 0 Selects P2 3 at the package pin 1 Selects CS3 at the package pin 2 PM2 Pin Mode 0 Selects P2 2 at the package pin 1 Selects CS2 at the package pin 1 PM1 Pin Mode 0 Selects P2 1 at the package pin 1 Selects CS1 at the package pin
435. his bit is undefined for compatibility with future devices do not modify this bit 6 6 Pin Mode 0 Selects CS6 at the package pin 1 Selects REFRESH at the package pin 5 PM5 Pin Mode 0 Selects the coprocessor signals PEREQ BUSY and ERROR Z at the package pins 1 Selects the timer control unit signals TMROUT2 TMRCLk2 and TMRGATE2 at the package pins 4 PM4 Pin Mode 0 Selects DACKO at the package pin 1 Selects CS5 at the package pin 3 PM3 Pin Mode 0 Selects EOP at the package pin 1 Selects CTS1 at the package pin 2 PM2 Pin Mode 0 Selects DACK1 at the package pin 1 Selects TXD1 at the package pin 1 PM1 Pin Mode 0 Selects SRXCLK at the package pin 1 Selects DTR1 at the package pin 0 PMO Pin Mode 0 Selects SSIOTX at the package pin 1 Selects RTS1 at the package Figure 13 15 Pin Configuration Register PINCFG 13 17 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 13 3 2 SIO and SSIO Configuration Register SIOCFG Use SIOCFG bit 2 to connect either PSCLK or SERCLK to the baud rate generator s input BCLKIN SIO and SSIO Configuration Expanded Addr F836H SIOCFG ISA Addr read write Reset State 00H 7 0 S1M SOM SSBSRC S1BSRC SOBSRC Bit Bit Number Mnemonic Function 7 S1M SIO1 Modem Signal Connections 0 Con
436. hows two nonpipelined write cycles one with and one without a wait state The sequence of signals for a nonpipelined write cycle is as follows 1 6 16 The processor initiates the cycle by driving the address bus and the status signals active and asserting ADS The type of bus cycle occurring is determined by the states of the address bus 25 1 byte enable pins BLE and BHE and bus status outputs W R M IO D C REFRESH and LOCK Because of output delays these signals should be sampled at the rising edge of the CLK2 signal that coincides with the falling edge of PH2 when ADS is definitely active For a write cycle the bus status outputs have the following states e W R is high e M IOft is high for a memory write and low for an I O write e D C is high for a memory write or I O write cycle During halt and shutdown cycles D C is low Unless D C is decoded by external chip select logic the shutdown or halt cycle looks like a memory write cycle to byte address zero or two respectively Therefore the signal needs to be decoded for memory device chip selects in this address range normally SRAM or DRAM devices in order to recognize halt and shutdown cycles thus preventing incorrect write cycles to memory e REFRESH is deasserted e LOCK is asserted for a locked cycle and deasserted for an unlocked cycle In a read modify write sequence both the memory data read and memory data write cycles are lock
437. iate in service bit However when processing master IR2 interrupts you must make sure all the slave in service bits are cleared before issuing the nonspecific EOI command to the master 9 2 5 Poll Mode The 82C59A modules can operate in a polling mode Conventional polling requires the core to check each peripheral device in the system periodically to see whether it requires servicing With the 82C59 A s polling mode the core by initiating the polling process can determine whether any of the devices attached to the 82C594 require servicing This improves conventional polling ef ficiency by allowing the core to poll only the 82C59A not each of the devices connected to it The polling mode is enabled by setting the polling bit in the Operation Command Word 3 register OCW3 NOTE After the polling procedure has been executed once polling is disabled i e it is a one shot operation To repeat the polling procedure the polling bit must be set again The polling process takes the place of the standard interrupt process In the standard interrupt pro cess the master sends interrupt requests to the core In the polling mode an interrupt request can be detected by reading the 82C59A s poll status byte The poll status byte indicates whether the 82C59A requires servicing If the 82C59A requires servicing the poll status byte indicates the highest priority pending interrupt request Polling is always a two step process A poll command is
438. ic unit allows a tester to perform these tasks Identify a component on a board manufacturer part number and version Bypass one or more components on a board while testing others Preload a pin state for a test or read the current pin state Perform static slow speed testing of this device Test off chip circuitry and board level interconnections Some of the figures and tables in this chapter were reproduced from Standard 1149 1 1990 IEEE Standard Test Access Port and Boundary Scan Architecture Copyright 1993 by the Institute of Electrical and Electronics Engineers Inc with the permission of the IEEE 18 1 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Place all device output pins into their inactive drive high impedance state allowing external hardware to drive connections that the processor normally drives The test logic unit Figure 18 1 is fully compliant with IEEE Standard 1149 1 It consists of the test access port TAP the test access port controller the instruction register IR and three data registers IDCODE BYPASS and BOUND It also includes logic for generating necessary clock and control signals Controller IDCODE Register al 1100 2340 01 Figure 18 1 Test Logic Unit Connections 18 2 intel JTAG TEST LOGIC UNIT 18 2 TEST LOGIC UNIT OPERATION 18 2 1 Test Access Port TAP The test access port consists of five dedicated pins four inputs and o
439. ice bit An interrupt return instruction is issued ending the interrupt process A2427 01 Figure 9 3 Interrupt Process Master Request from Non slave Source Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Slave receives an interrupt request Slave sets the request s pending bit Is special mask mode enabled operating in Is No fully nested mode request enabled Is request higher than any set in service bits in service bit for this request set No Yes Slave sends request to master Note See the Interrupt Process Master Request from Slave Source figure for the continuation of this flow chart A2428 01 Figure 9 4 Interrupt Process Slave Request intel INTERRUPT CONTROL UNIT Master receives IR2 interrupt request Master sets its IR2 pending bit operating in ls fully nested 5 Is master mode special operating in No request i mask mode special full bled k d enabled enabled Is the IR2 in service bit Set request higher level than any set in service bits request equal or higher than any set in service bits Yes Master sends request to CPU CPU initiates interrupt acknowledge cycle Master clears IR2 pending bit and sets IR2 in service bit Slave clears its pending bit sets i
440. iggering the Strobe Figure 10 21 shows the writing of a new count value The counter waits for a gate trigger to load the new count it does not affect the current sequence until the counter receives a trigger On the pulse following the trigger the control logic loads the new count The control logic then decrements the count on each succeeding CLKINn pulse OUTn remains high until the count reaches zero then strobes low for one CLKINn pulse Control Count 3 Count 5 Word 1AH Writes to Counter n CLKINN Voc GATEn i 1 1 1 count 2 2 2 2 3 0002 0001 oo00 FFFF FFFE 0005 0004 A2405 01 Figure 10 21 Mode 5 Writing a New Count Value 10 19 Intel386 EX EMBEDDED PROCESSOR USER S MANUAL intel 10 3 REGISTER DEFINITIONS The following sections describe how to configure a counter s input and output signals initialize a counter for a specific operating mode and count format write count values to a counter and read a counter s status and count 10 3 1 Configuring the Input and Output Signals Each counter is driven by a clock pulse on its CLKINn input You can connect each counter s input to either its timer clock TMRCLKn pin or the prescaled clock PSCLK signal The counters can handle up to 1 2 the processor clock CLK2 4 input frequency but only up to a maximum of 8 MHz CLKINn frequency can never be more than 8 MH
441. ignal unless a refresh request is pending in which case it ignores this signal REFRESH Device pin External Refresh output Indicates that a refresh bus cycle is in progress and that the refresh address is on the bus Refresh Internal signal Refresh Request Request Indicates that the control unit is requesting bus ownership Refresh Internal signal Refresh Acknowledge Acknowledge Indicates that the refresh control unit is being granted bus ownership A25 Device pins Address Bus output Contains the refresh address during refresh cycles This address can be used by the DRAM device to refresh a single row 15 2 2 Refresh Intervals The interval timer unit controls the rate at which the control unit generates refresh requests Re fresh intervals are programmable through the use of a refresh control interval register RFSCIR and a 10 bit down counter The counter is loaded from RFSCIR then decremented on each CLK OUT falling edge When the counter reaches one the interval timer unit reloads the counter from the RFSCIR and asserts its timeout signal The timeout signal causes the control unit to initiate a refresh request provided there is not one already pending The RCU must complete the present refresh cycle before the control logic can generate a new refresh request The control unitignores the timeout signal if it already has a refresh request pending 15 2 3 Refresh Addresses The physical address generated during
442. ignored The byte address driven during the first cycle is 4 during the second cycle the byte address is 0 BHE is high BLE is low and A25 3 and A1 are low for both cycles A2 is high for the first cycle and low for the second If the CAS enable bit in the interrupt control unit s configuration register is set INTCFG 7 1 address bits A18 16 reflect the status of the CAS lines The CAS lines go valid at the rising edge of PH2 of the T1 state of the first interrupt acknowledge cycle They then go invalid at the rising edge of PH2 of the next Ti state At the rising edge of PH2 of the T1 state of the second interrupt acknowledge cycle the CAS lines go valid again They then go invalid at the rising edge of PH2 of the next Ti state 6 23 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 6 24 NOTE Since the CAS lines are invalid in the Ti states between the two interrupt acknowledge cycles cascading of external 82C59A devices requires latching the CAS lines This ensures that the CAS lines remain valid during these Ti states to fulfill the requirements of the external 82C59A devices The processor floats D15 0 for both cycles however at the end of the second cycle if the interrupt is from an external cascaded 82C59A the service routine vector number driven on the lower data bus by the 82 59 is read by the processor on data pins 07 0 Otherwise the active internal 82C59A sends the vector to the processor The first cy
443. immediate data 2 2 aie b register memory immediate to register 2 2 short form 011w reg immediate data Crate en 010000w J full displacement 4 a n accumulator to memory 2 2 b h short form 010001w full displacement register memory to 2 5 22 23 b h i j segment register 000 10 mod sreg3 r m segment register to 2 2 2 2 b h register memory 000 00 mod sreg3 r m MOVSX Move with sign extension registerirom 00001111 1011111w mod reg r m 967 567 b register memory MOVZX Move with zero extension register from 00001111 1011011w modreg 2 3 6 register memory PUSH Push register memory 1111 11 mod 110r m 5 7 7 9 b h register short form 01010 reg 2 4 b h segment register ES 2 4 b h CS SS or DS 000 sreg2 110 short form segment register ES 2 4 b h CS SS or DS FS or 00001111 10 sreg3 000 GS E 2 intel INSTRUCTION SET SUMMARY Table E 1 Instruction Set Summary Sheet 2 of 19 Clock Count Notes Real Pro Real Pro Ad tected Ad tected Instruction Format dress Virtual dress Virtual Mode Ad Mode Ad or dress or dress Virtual Mode Virtual Mode 8086 8086 Mode Mode immediate 011010s0 immediate data 2 4 b h PUSHA Push All 01100000 18 34 b h POP Pop register memory 1000111 mod 0 0 0 r m 5 7 7 9 b h regis
444. in See Figure 10 1 for the TCU signal connections For details on the P3CFG and PINCFG registers see Figure 10 23 and Figure 10 24 The counter output signals are automatically connected to the interrupt control unit Counter 1 s output signal OUT1 is automatically connected to DMA channel 0 and counter 2 s output signal OUT2 is automatically connected to DMA channel 1 Use P3CFG bits 0 and 1 to connect TMROUTO and TMROUTI to package pins Port 3 Configuration Expanded Addr F824H P3CFG ISA Addr read write Reset State 00H 7 0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PMO Bit Bit Number Mnemonic Function 7 PM7 Pin Mode 0 Selects P3 7 atthe package pin 1 Selects COMCLK at the package pin 6 PM6 Pin Mode 0 Selects P3 6 at the package pin 1 Selects PWRDOWN at the package pin 5 5 Pin Mode 0 Selects P3 5 at the package pin 1 Connects master to the package pin 4 4 Pin Mode 0 Selects P3 4 at the package pin 1 Connects master IR6 to the package pin INT2 3 PM3 Pin Mode 0 Selects P3 3 at the package pin 1 Connects master IR5 to the package pin INT1 2 PM2 Pin Mode 0 Selects P3 2 at the package pin 1 Connects master IR1 to the package pin INTO 1 PM1 Pin Mode See Table 5 1 on page 5 8 for all the PM1 configuration options 0 PMO Pin Mode See Table 5 1 on page 5 8 for all the PMO configuratio
445. ing Highest DMA gba External Bus Becomes DMA Level Channel 0 ighest Master Highest Channel 1 Level Level DMA DMA External Bus Channel 1 Channel 0 Master Lowest External Bus Specified DMA Assigned DMA Level Master Lowest Channel 1 Lowest Channel 0 Level Level After Gaining Bus Control A2532 01 Figure 12 5 Changing the Priority of the DMA Channel and External Bus Requests 12 2 5 Ending DMA Transfers When a channel s byte count expires the buffer transfer is complete and the end of process EOP output is activated Figure 12 6 A buffer transfer can be terminated before the byte count expires by activating the EOP input The channel can sample the EOP input synchro nously or asynchronously With synchronous sampling the channel samples EOP at the end of the last state of every data transfer With asynchronous sampling the DMA samples the inputs at the beginning of every state of requester access then waits until the end of the state to act on the input Figure 12 7 illustrates terminating a buffer transfer by activating the EOP input the figure shows both asynchronous and synchronous EOP sampling EOP sampling is programmed in the DMACMD2 register Figure 12 24 12 10 intel DMA CONTROLLER Terminating a buffer transfer by deasserting DREQn can also be done either synchronously or asynchronously The effect is identical to that of synchronous or asynchronous sampling of EOP When DREQn is used to terminate a
446. ing initialization sequence 16 10 pin configuration 16 7 PnCFG register 16 7 PnDIR register 16 8 PnLTC register 16 8 PnPIN register 16 9 register addresses 4 19 D 5 registers 16 6 signals 16 5 Instruction Decode Unit 3 4 Instruction Queue 3 5 Instruction Register IR 18 7 Instructions notational conventions 1 3 Interrupt control unit 9 1 9 30 configuring 5 7 departure from PC AT architecture B 4 design considerations 9 29 interrupt acknowledge cycle 9 29 9 30 interrupt detection 9 29 interrupt polling 9 14 9 15 interrupt priority 9 6 9 8 assigning an interrupt level 9 6 changing the default interrupt structure 9 7 determining priority 9 7 9 8 interrupt process 9 9 9 14 interrupt sources 9 4 interrupt service routine 6 23 interrupt vectors 9 8 intel operation 9 4 9 16 overview 9 1 programming 9 15 9 32 considerations 9 32 9 20 D 28 ICWI register 9 20 ICW2 9 21 D 29 ICW2 register 9 21 ICW3 9 22 9 23 D 29 D 30 ICW3 register 9 22 9 23 ICWA 9 24 D 30 ICWA register 9 24 IERn 11 27 D 32 11 28 D 33 INTCFG 5 10 9 19 D 34 INTCFG register 9 19 OCWI 9 25 D 40 register 9 25 OCW2 9 26 D 41 2 register 9 26 OCW3 9 27 D 42 OCW3 register 9 27 P3CFG register 9 18 POLL 9 28 D 49 POLL register 9 28 register addresses 4 16 4 17 D 2 D 3 registers 9 15 9 17 signals 9 5 spurious interrupts 9 30 Interrupt priority 9 6 9 8
447. ing is not enabled the physical address is the same as the linear address and no translation is necessary The Page Descriptor Cache stores recently used Page Directory and Page Table entries in its Translation Lookaside Buffer TLB to speed this translation The Paging Unit forwards physical addresses to the Core Bus Unit to perform memory and I O accesses 3 5 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 3 3 CORE Intel386 EX PROCESSOR INTERFACE The Intel386 EX processor peripherals are connected to the Intel386 CX processor core through an internal Bus Interface Unit BIU The BIU controls internal peripheral accesses and external memory and I O accesses Because it has the BIU between the Intel386 CX processor core and the external bus the Intel386 EX processor bus timings are not identical to those of the Intel386 CX processor or Intel386 SX processor The Intel386 CX processor numeric coprocessor interface is maintained and brought out to the Intel386 EX processor pins The same I O addresses used on the Intel386 SX processor are used on the Intel386 EX processor even though there are more address lines The A23 line is high for coprocessor cycles Refer to Interface To Intel387 SX Math Coprocessor on page 6 38 for more details 3 6 intel SYSTEM REGISTER ORGANIZATION CHAPTER 4 SYSTEM REGISTER ORGANIZATION This chapter provides an overview of the system registers incorporated in the Intel386TM EX
448. intel 7 3 4 2 SMRAM State Dump Area sese 714 7 3 5 Resume Instruction 7 15 7 4 THE Intel386 EX PROCESSOR IDENTIFIER REGISTERS seen 7 15 7 5 PROGRAMMING CONSIDERATIONS serene 7 16 7 5 1 System Management Mode Code Example 7 16 CHAPTER 8 CLOCK AND POWER MANAGEMENT UNIT 8 1 OVERVIEW A 8 1 8 1 1 Clock Generation pet Gb PARE teenie 8 1 8 1 2 Power Management LOGIC eere 8 3 8 1 2 1 SMM Interaction with Power Management Modes 8 4 8 1 2 2 Bus Interface Unit Operation During Idle Mode 8 5 8 1 2 3 Watchdog Timer Unit Operation During Idle Mode 8 5 8 1 3 Clock and Power Management Registers and Signals 8 6 8 2 CONTROLLING THE PSCLK FREQUENCY seen eene nennen nnns 8 7 8 3 CONTROLLING POWER MANAGEMENT 8 8 8 3 1 Idle Mode urere IRSE DRE IPIS 8 9 8 3 2 Powerdown Mode itr rine tinere coun ndo nee 8 10 8 3 3 Ready Generation During 10 8 4 DESIGN emen OT
449. internally inverted and connected to the interrupt control unit s slave IR7 line If you want a WDT timeout to generate a slave IR7 interrupt maskable interrupt you need only enable unmask the interrupt Refer to Chapter 9 for details Ensure that the slave 8259A is configured for edge triggered interrupts refer to Chapter 9 Interrupt Control Unit if IR7 is unmasked Otherwise the WDT generates continuous interrupts Nonmaskable interrupt If you want a WDT timeout to cause a nonmaskable interrupt connect the WDTOUT pin to the NMI input pin Reset If you want a WDT timeout to reset the system connect the WDTOUT pin to the RESET input pin 17 6 PROGRAMMING CONSIDERATIONS This section outlines programming considerations for the watchdog timer unit 17 6 1 Writing to the WDT Reload Registers WDTRLDH and WDTRLDL WDTRLDH and WDTRLDL are 16 bit registers at addresses OFACOH and OF4C2H respectively Therefore when using a 32 bit write to load the two registers the lower 16 bits should contain the data for WDTRLDH and the higher 16 bits should contain the data for WDTRLDL For example 4321H can be written to WDTRLDH and to WDTRLDL using a 32 bit write of the number OCCCC4321H to I O address OFACOH 17 6 2 Minimum Counter Reload Value To ensure correct operation of the Watchdog Timer the WDT s counter should never be reloaded with a value less than 8 17 6 3 Watchdog Timer Unit Code Examples This section includes
450. interrupt control unit causes the device to exit the power management mode After a reset the CPU starts execut ing instructions at 3FFFFFOH and the device remains in normal operation After an interrupt the CPU executes the interrupt service routine then returns to the instruction following the HALT that prompted the power management mode Unless software modifies the power control register the next HALT instruction returns the device to the programmed power management mode 8 1 2 1 SMM Interaction with Power Management Modes When the processor receives an SMI interrupt while it is in idle or powerdown mode it exits the power management mode and enters System Management Mode SMM Upon exiting SMM software can check whether the processor was in a halt state before entering SMM If it was soft ware can set a flag that returns the processor to the halt state when it exits SMM Assuming the power control register bits were not altered in SMM the processor re enters idle or powerdown when it exits SMM Figure 8 3 illustrates the relationships among these modes 8 4 intel CLOCK AND POWER MANAGEMENT UNIT Halt Instruction with Powerdown Flag Set Halt Instruction with Idle Flag Set Normal Operation Powerdown Mode RSM with Powerdown Flag and Halt Restart Slot Set RSM Instruction with Idle Flag and Halt Restart Slot Set System Management Reset eset or RSM Instruction with Halt Re
451. interrupt is pending bit 0 0 these bits specify which status signal caused the pending interrupt 152 151 Interrupt Source 0 0 modem status signal 0 1 transmitter buffer empty signal 1 0 receive buffer full signal 1 1 receiver line status signal When one of the modem input signals CTSn DSRn Rin and DCDn changes state the modem status signal is activated A framing error overrun error parity error or break interrupt activates the receiver line status signal Reading the modem status register clears the modem status signal Reading the IIRn register or writing to the transmit buffer register clears the transmit buffer empty signal Reading the receive buffer register clears the receive buffer full signal Reading the receive buffer register or the serial line status register clears the LSRn error bits which clears the receiver line status signal 0 IP Interrupt Pending This bit indicates whether an interrupt is pending 0 Interrupt is pending 1 No interrupt is pending 11 28 Figure 11 18 Interrupt ID Register IIR intel ASYNCHRONOUS SERIAL UNIT 11 3 10 Modem Control Register MCRn Use MCRn to put the SIOn into a diagnostic test mode In this mode the modem input signals are disconnected from the package pins and controlled by the lower four MCRn bits and the mo dem output signals are forced to their inactive states Figure 11 19 Additionally the sig nals are also forced
452. interrupts 1 Connects the receive buffer full signal to the interrupt control unit s SIOINTn output NOTE The interrupt enable register is multiplexed with the divisor latch high register You must clear bit 7 DLAB of the serial line control register LCRn before you can access the interrupt control register D 32 intel SYSTEM REGISTER QUICK REFERENCE D 30 IIRn Interrupt ID IIRO IIR1 IIRO IIR1 Expanded Addr F4FAH F8FAH read only ISA Addr 02 Reset State 01H 01H 7 0 152 151 IP Bit Bit 5 Number Mnemonic Function 7 3 Reserved These bits are undefined 2 152 1 Interrupt Source If an interrupt is pending bit 0 0 these bits specify which status signal caused the pending interrupt 152 151 Interrupt Source 0 0 modem status signal 0 1 transmitter buffer empty signal 1 0 receive buffer full signal 1 1 receiver line status signal When of the modem input signals CTSn DSRn Rin and DCDn changes state the modem status signal is activated A framing error overrun error parity error or break interrupt activates the receiver line status signal Reading the modem status register clears the modem status signal Reading the IIRn register or writing to the transmit buffer register clears the transmit buffer empty signal Reading the receive buffer register clears the receive buffer
453. into the MSR register bits MCRn 1 RTSnit 0 forced high MCRn 3 DTRn MCRn 2 forced high Note MCRn 1 indicates that modem control register bit 1 controls the CTS input and so on A2529 01 Figure 11 19 Modem Control Signals Diagnostic Mode Connections Besides the diagnostic mode there are two other options for connecting the modem input signals You can connect the signals internally using the SIO configuration SIOCFG register The inter nal connection mode disconnects the modem input signals from the package pins and connects the modem output signals to the modem input signals in this case the modem output signals re main connected to package pins See Figure 11 20 In this mode the values you write to MCRn bits 0 and 1 control the state of the modem s internal input signals and output pins 2528 01 Figure 11 20 Modem Control Signals Internal Connections The other option is standard mode In standard mode the modem input and output signals are connected to the package pins In this mode the values you write to MCRn bits 0 and 1 control the state of the modem s output pins 11 29 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Modem Control MCRO MCR1 MCRO MCR1 Expanded Addr FAFCH F8FCH read write ISA Addr O3FCH 02 Reset State 00H 00H 7 0 LOOP OUT2 OUT1 RTS DTR Bit
454. ion of a character This prevents the DMA from transferring a character from the SIO with an error 11 13 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 11 2 7 External UART Support Many PC compatible applications may need to support COM3 and serial ports Since the integrated serial ports are mapped to I O addresses that support only 1 and COM2 an inter face to support an external serial I O unit has been included The master ICU interrupt inputs IR3 and IRA may be brought out to package pins as INT8 muxed with P3 1 TMROUT1 and INTO muxed with P3 0 TMROUTO respectively In order to select between the internal SIO units and the external SIO units use the OUT2 bit in the modem control register MCR In normal user mode with no loopback clear the OUT2 bit to enable external SIO support and set OUT2 to enable internal SIO support Doing this com bined with the correct settings of the P3CFG 1 0 and INTCFG 6 5 bits connect the INT8 and INTO pins to IR3 and IR4 of the master ICU respectively Note that the reset state of P3CFG and INTCFG enables SIOINT and disconnects OUT2 gating See Chapter 5 DEVICE CONFIGU Tables 5 1 and 5 2 for more details on how to select this option 11 14 intel ASYNCHRONOUS SERIAL UNIT 11 3 REGISTER DEFINITIONS Table 11 5 lists the registers associated with the SIO unit and the following sections contain bit descriptions for each register Table 1
455. ion register retains its previous state Shift IR Update IR Latches the current instruction onto the instruction Update IR register s parallel output on the falling edge of TCK Pun steele oral NOTE By convent ion the abbreviation DR stands for data register and R stands for instruction register The active register is the register that the current instruction has placed in the serial path between TDI and TDO For example assume that the TAP controller is in its test logic reset state and you want it to start shifting the contents of the instruction register from TDI toward TDO Shift IR state This state change requires a zero two ones then two zeros on TMS at the next five rising edges of TCK see Table 18 3 By supplying the proper values in the correct sequence you can move the TAP controller from any state to any other state Table 18 3 Example TAP Controller State Selections Initial State TMS Value at TCK Rising Edge Resulting State Test Logic s Run Test Idle Reset Run Test Idle 1 Select DR Scan Select DR Select IR Scan Scan Select IR 0 Scan Capture IR Capture IR 0 Shift IR 18 5 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Test Logic Reset Run Test Idle A2356 01 18 6 Figure 18 2 TAP Controller Finite State Machine intel JTAG TEST LOGIC UNIT 18 2 3 Instruction Register IR An instructi
456. ipheral pin or a general purpose I O port pin 8 3 8 Ready Generation During HALT A halt cycle like all other CPU bus cycles requires a valid READY to complete This ready can be generated by either external logic or from the internal bus interface unit BIU Setting bit 2 of the PWRCON causes the READY to be generated by the internal BIU and clearing bit 2 requires it to be generated by external logic When READY is generated internally the LBA signal is driven low External logic can use the PWRDOWN output to control other system components and prevent DMA and hold requests NOTE When the processor exits Powerdown Mode use the CLKOUT pin for external synchronization with the processor clock 8 10 intel CLOCK AND POWER MANAGEMENT UNIT PH1 PH2 CLK2 CLKOUT PH1P PH1C PH2P PH2C PWRDOWN PH2 PH1 PH2 PH1 CLK2 CLKOUT PH1P PH1C PH2P PH2C PWRDOWN A2469 02 Figure 8 7 Timing Diagram Entering and Leaving Powerdown Mode 8 4 DESIGN CONSIDERATIONS This section outlines design considerations for the clock and power management unit 8 4 1 Reset Considerations External circuitry must provide an input to the RESET pin The RESET input must remain high for at least 16 CLK2 cycles to reset the chip properly The RESET pin signal is routed directly to the device s bidirectional pins Even in idle or power down a device reset floats the bidirectional pins and turns on the weak pull up
457. it Connections 17 2 intel 17 1 1 WDT Signals Table 17 1 describes the signals associated with the WDT WATCHDOG TIMER UNIT Table 17 1 WDT Signals Signal Device Pin or Internal Signal Description ADS Device pin Address Status from the bus interface unit Indicates that the processor is driving a valid bus cycle definition and address onto its pins Bus monitor mode reloads and starts the down counter each time ADS is asserted IDLE Internal signal Idle from the clock and power management unit Indicates that the device is in idle mode core clocks stopped and peripheral clocks running In watchdog mode the down counter stops when the core is idle In bus monitor or general purpose timer mode the WDT continues to run while the core is idle READY Device pin Ready from the bus interface unit Indicates that the current bus cycle has completed Bus monitor mode stops the down counter when READY is asserted WDTOUT Device pin Watchdog Timer Output Indicates that the down counter has timed out If you want a WDT timeout to reset the device connect WDTOUT to the RESET input If you want a WDT timeout to generate a nonmaskable interrupt connect WDTOUT to the NMI input An internal signal carries the inverted value of WDTOUT to the interrupt control unit the slave s IR7 line If you want a WDT timeout to cause a maskable interrupt enable the interrupt
458. ith bit 6 set GATEO on 0 0 PSCLK connected to CLKO 0 1 TMRCLKO connected to CLKO 5 32 Table 5 6 Example TMRCFG Configuration Register DEVICE CONFIGURATION 1 P3 0 connected to IR4 Bit 4 INTCFG Value 7 0 CAS2 0 disabled to pins 0 1 CAS2 0 enabled from pins 6 0 SIOINT1 connected to master IR3 0 1 P3 1 connected to IR3 5 0 SIOINTO connected to master IR4 0 4 0 DMAINT connected to slave IR4 INT6 connected to slave IR5 1 INT6 connected to slave IR4 DMAINT connected to slave IR5 3 0 VSS connected to slave IR6 1 INT7 connected to slave IR6 2 0 Vgg connected to slave IR5 1 INT6 connected to slave IR5 1 0 SSIO Interrupt to slave IR1 1 INT5 connected to slave IR1 0 0 VSS connected to slave IRO 1 INT4 connected to slave IRO Table 5 7 Example INTCFG Configuration Register SIOCFG 7 0 SIO1 modem sigs conn to pin muxes 1 SIO1 modem signals internal 6 0 SIOO modem sigs conn to pin muxes 1 5100 modem signals internal 5 3 Reserved 2 0 PSCLK connected to SSIO BLKIN 1 SERCLK connected to SSIO BCLKIN 1 0 COMCLK connected to SIO1 BCLKIN 1 SERCLK connected to SIO1 BCLKIN 0 0 COMCLK connected to 5100 BCLKIN 1 SERCLK connected 5100 BCLKIN Table 5 8 Example SIOCFG Configuration Register 5 33 Intel386 EX EMBEDDED MICROPR
459. its Address lines A15 0 are decoded internally The expanded I O space is enabled and all peripherals can be ac cessed only in expanded I O space This mode is useful for systems that don t require DOS com patibility and have other custom peripherals in slot 0 of the I O space See Figure 4 8 For all DOS peripherals the lower 10 bits in the DOS I O space and in the expanded I O space are identical except the UARTS whose lower 8 bits are identical This makes correlation of their respective offsets in DOS and expanded I O spaces easier Also the UARTS have fixed I O ad dresses This differs from standard PC AT configurations in which these address ranges are pro grammable 4 11 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 3FFH On chip UART 0 On chip UART 1 mE On chip 8259A 2 On chip Timer REMAPCFG 23H Register FOOOH On chip 8259A 1 Expanded I O Space Note on Internal DMA Shaded area indicates that the on chip DMA and expanded I O space DOS I O Space peripherals are not accessible A2496 02 Figure 4 6 Example of Nonintrusive DOS Compatible Mode SYSTEM REGISTER ORGANIZATION 3FFH REMAPCEG 23H Register 22H On chip UART 2 On chip UART 1 FFFFH Other Peripherals 8259A 2 8259A 1 On chip DMA FOOOH Expanded I O Space DOS I O Space A2501 02 Figure 4 7 Enhanced DOS Mode 4 13 Intel386 EX EMBEDDED MICROPROCESSOR US
460. its are given below The Control Unit contains microcode and special parallel hardware that speeds multiply divide and effective address calculation The Data Unit contains the Arithmetic Logic Unit ALU a file of eight 32 bit general purpose registers and a 64 bit barrel shifter which performs multiple bit shifts in one clock The Data Unit performs data operations requested by the Control Unit The Protection Test Unit checks for segmentation violations under the control of the microcode To speed the execution of memory reference instructions the Execution Unit partially overlaps the execution of any memory reference instruction with the previous instruction 3 2 5 Segmentation Unit The Segmentation Unit translates logical addresses into linear addresses at the request of the Ex ecution Unit The on chip Segment Descriptor Cache stores the currently used segment descrip tors to speed this translation At the same time it performs the translation the Segmentation Unit checks for bus cycle segmentation violations These checks are separate from the static segmen tation violation checks performed by the Protection Test Unit The translated linear address is truncated to a 24 bit physical address 3 2 0 Paging Unit When the Inte1386 CX processor paging mechanism is enabled the Paging Unit translates linear addresses generated by the Segmentation Unit or the Instruction Prefetch Unit into physical ad dresses When pag
461. itter The maximum transmitter input fre quency is 8 25 MHz with a 33MHz processor clock CLK2 66MHz In master mode the baud rate generator must be programmed and enabled prior to enabling the transmitter In slave mode the transmitter must be enabled prior to the application of an external clock 13 6 intel SYNCHRONOUS SERIAL UNIT 13 2 2 1 Transmit Mode using Enable Bit The transmitter contains a transmit holding buffer empty THBE flag and a transmit underrun error TUE flag At reset THBE is set indicating that the buffer is empty Writing data to the buffer clears THBE When the transmitter transfers data from the buffer to the shift register THBE is set If the transmitter is enabled TEN bit is set AUTOTXM is clear it transfers the new contents of the transmit buffer to the shift register each time the shift register finishes shifting its current contents If the shift register finishes shifting out its current contents before a new value is written to the transmit buffer it reloads the old value and shifts it out again This condition is known as a trans mitter underrun error TUE is set to indicate an underrun error For high speed transfers this can be a problem since the Baud rate generator clock may be too fast it may not allow enough time to control the TEN bit for each word transfer This could cause the same word to be transmitted more than once See Autotransmit Mode on page 13 12 for a description of h
462. itter Interrupt Enable 0 Clearing this bit prevents the Interrupt Control Unit from sensing when the transmit buffer is empty 1 Setting this bit connects the transmit buffer empty internal signal to the Interrupt Control Unit TEN Transmitter Enable 0 Disables the transmitter 1 Enables the transmitter ROE Receive Overflow Error The receiver sets this bit to indicate a receiver overflow error Write zero to this bit to clear the flag If a one is written to ROE the one is ignored and ROE retains its previous value RHBF read only bit Receive Holding Buffer Full The receiver sets this bit when the receive shift register contents have been transferred to the receive buffer Reading the buffer clears this bit RIE Receive Interrupt Enable 0 Clearing this bit prevents the Interrupt Control Unit from sensing when the receive buffer is full 1 Setting this bit connects the receiver buffer full internal signal to the Interrupt Control Unit REN Receiver Enable 0 Clearing this bit disables the receiver 1 Setting this bit enables the receiver D 59 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel D 60 SSIOCON2 SSIO Control 2 SSIOCON2 read write 7 Expanded Addr F488H ISA Addr Reset State 00H AUTOTXM TXMM RXMM Bit Bit Number Mnemonic Function
463. ization Normally UCS is used to select non volatile memory devices such as ROM and FLASH at the top of the memory address space so that the processor can fetch the first instruction from address 3FFFFFOH after RESET If the Port92 CPU only RESET is used described in Chapter 5 the UCS channel must remain enabled for the top of the memory address space a CPU only RESET does not affect the chip select registers and therefore the UCS channel does not re initialize to its reset state 14 3 CSU OPERATION Each chip select channel functions independently The following sections describe chip select channel address blocks system management mode support and bus cycle length and bus size control 14 3 1 Defining a Channel s Address Block A 15 bit channel address and mask are used to specify a channel s active address block When the processor accesses an address in memory or I O the upper 15 bits of the address are compared to the chip select channel address and OR d with the channel mask This means that the CSU compares the channel address and ORs the channel mask to A25 11 for memory addresses and A15 1 for I O addresses Ones in the channel s mask exclude the corresponding bits from address comparisons Figure 14 1 shows the logic for determining address equality 14 2 intel CHIP SELECT UNIT 15 bit Channel Address Address bit x Chip select Channel Output 15 bit Channel Mask A2533 01
464. izer to a three state buffer that connects the I O port path to the internal data bus Not all peripheral input functions are synchronous For example the interrupt pins INT9 INTO are asynchronous so that they can wake up the chip from Powerdown mode when the clocks are stopped The state of the pin can be read at any time regardless of whether the pin is used as an I O port or for a peripheral function 16 4 INPUT OUTPUT PORTS Table 16 1 Pin Multiplexing Port Pin Peripheral Function Pin Reset Status 1 Signal Direction 1 0 wk 1 DCDO 5100 1 1 wk 1 50 5100 1 2 wk 1 DTRO 5100 P1 3 wk 1 DSRO 5100 1 4 wk 1 RIO 5100 1 5 wk 1 LOCK BIU P1 6 wk 0 HOLD BIU P1 7 wk 0 HLDA O BIU P2 0 wk 1 50 CSU P2 1 wk 1 CS1 CSU P2 2 wk 1 CS2 CSU P2 3 wk 1 CS3 CSU P2 4 wk 1 CS4 CSU P2 5 wk 0 RXDO 5100 2 6 wk 0 TXDO 8100 2 7 wk 1 50 5100 P3 0 wk 0 TMROUTO Timer 0 1 wk 0 TMROUT 1 O Timer 1 P3 2 wk 0 INTO ICU P3 3 wk 0 INT1 ICU P3 4 wk 0 INT2 ICU P3 5 wk 0 INT3 ICU P3 6 wk 0 PWRDOWN O CLK amp PM P3 7 wk 0 COMCLK 5100 SIO1 NOTES 1 weakly pulled down wk 1 weakly pulled up 2 input output 16 5 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 16 2 REGISTER DEFINITIONS Each port has three control registers and a
465. k ck ko Init_IOPorts Description This function initializes the direction and mode of the I O port pins Although the pins are default configured to the peripheral state after RESET they must still be initialized to turn off the weak resistors Parameters Portl Portl Mode Configuration Port2 Port2 Mode Configuration Port3 Port3 Mode Configuration PortDirl Portl Direction PortDir2 Port2 Direction PortDir3 Port3 Direction PortLtcl Portl Data Latch Value PortLtc2 Port2 Data Latch Value PortLtc3 Port3 Data Latch Value Returns None Assumptions None Syntax Port 1 configuration defines define DCDO 0 1 define RTSO 0x2 define DTRO 0 4 define DSRO 0x8 define RIO 0X10 define LOCK 0x20 define HOLD 0X40 define HOLDACK 0x80 Port 2 configuration defines define CS0 0x1 define CS1 0x2 16 11 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel define define define define define define Port define define define define define define define define Port define define define define define define define define define CS2 CS3 54 RXDO TXDO CTSO 0 4 0x8 0X10 0x20 0X40 0X80 3 configuration defines TMROUTO TMROUT1 INTO INT1 INT2 INT3 PWRDWN COMCLK PO P1 P2_ PSs P5_ P6_ P7 N Pee ey N Px_OUT 0 1 0 2 0 4 0 8 0x10 0x20 0x40 0x80 Direction defines 0x1 0x2 0x4 0x8 0x10 0x20 0x40 0x
466. l REFRESH CONTROL UNIT 15 5 DESIGN CONSIDERATIONS Consider the following when programming the RCU The system address bus does not contain an address AO signal instead it uses the BLE and the BHE pins to generate the lowest address bit During all refresh operations BLE and BHE are driven high This needs to be noted especially when interfacing to an 8 bit wide Pseudo Static RAM PSRAM device The lowest address bit generated by the refresh address counter is Al A circuit like the one shown in Figure 15 6 can be used to ensure the refresh of all rows Here BLE is connected to an address line of the PSRAM that is not used during refresh Address A1 of the processor is connected to AO of the PSRAM and so forth For example when using a 128Kx8 bit PSRAM device refresh cycles only use the address present on inputs A8 0 connect Al of the processor to AO of the PSRAM A2 to A1 and so on until A9 to A8 Then connect BLE of the processor to any one of the A16 9 address lines of the PSRAM Since PSRAM is random access memory this scheme works During access cycles sequential accesses by the processor go to non contiguous addresses in the PSRAM but since the processor does both the read and write cycles this does not pose a problem Intel386 BLE can be connected to rocessor any of these address lines BLE A3352 02 Figure 15 6 Connections to Ensure Refresh of Rows in an 8 Bit Wide P
467. l I O unit configuration consisting of channels SIOO and SIO1 Each channel has one output SIOINTO SIOINT 1 to the interrupt control unit see Figure 5 4 and two outputs to the DMA unit These signals do not go to package pins SIOINTn is active when any one of the SIO status signals receiver line status receiver buffer full transmit buffer empty modem status is set and enabled All SIOO pins are multiplexed with I O port signals Using SIOI precludes using DMA channel 1 for external DMA requests due to the multiplexing of the transmit and receive signals with DMA signals RXD1 DRQ1 TXD1 DACK1 NOTE Using SIO1 modem signals 51 DSR1 DTR1 and RI1 precludes use of the SSIO unit 5 14 intel DEVICE CONFIGURATION SIOO SIOCFG 0 1 P3CFG 7 9 COMCLK BCLKIN To From I O Port 3 lt gt 7 SERCLK 0 P2CFG 5 Receive Data uu tH RXDO To From I O Port 2 SIOINTO gt ICU 0 528 RBFDMAO gt To TXEDMAO 3 To DMA 1 2 6 Transmit Data 1 0 SIOCFG 6 To From I O 2 5 gt 9 2 6 1 P2CFG 7 CTSO To From I O Port 2 2 7 Request to Send RTSO To From I O Port 1 P1 1 1 P1ICFG 3 DSRO Data Set Ready To From I O Port 1 9 P1 3 DCDO Data Carrier To From I O Port 1 gt e P1 0 i Clear to Send v Detect T 4 1 2 Data Terminal e DTRO Ready To From I O Port 1 6 0 P1 2
468. l bits BUSMON and CLKDIS in the WDTSTATUS register Figure 17 3 the lockout sequence sets the WDTEN bit and clears the remaining bits The lockout sequence prohibits writes to the WDTSTATUS and reload registers only a system reset can change them This reduces the possibility for errant software to duplicate the instruc tions and illegally reload the timer The same lockout sequence that enables the watchdog reloads the down counter Write two se quential words OFO01EH followed immediately by OFE1H to the WDTCLR location OF4C8H 17 2 4 Bus Monitor Mode In bus monitor mode ADS reloads and starts the down counter and READY f stops it The ini tial values of the reload register and down counter are 3FFFFFH CAUTION For correct operation in Bus Monitor mode see Overview on page 17 1 you must have a minimum reload value Maximum number of wait states in your system 12 For example if the slowest device in your system requires 8 wait states during an access the reload value must be greater than or equal to 20 Use this sequence to enable bus monitor mode 1 Write the upper word of the reload value to WDTRLDH Figure 17 4 2 Write the lower word of the reload value to WDTRLDL Figure 17 4 3 Setthe bus monitor bit BUSMON in WDTSTATUS Figure 17 3 Because you never execute the lockout sequence in bus monitor mode you can change the reload value and enable or disable the mode at any time 17 5 Intel386
469. l internal slave interrupt requests on its IR2 signal This means that in fully nested mode higher level slave requests cannot interrupt lower level slave interrupts For example sup pose the slave gets an interrupt request on its IR7 signal The slave sends the interrupt request to the master s IR2 signal assuming the slave s IR7 interrupt is enabled and has sufficient priority The master sends the interrupt request to the core assume the master s IR2 interrupt is enabled and has sufficient priority The core initiates an interrupt acknowledge cycle and begins process ing the interrupt Next the slave gets an interrupt request on its IRO signal assume IRO is as signed a higher level than IR7 It then sends another IR2 to the master When the master is in fully nested mode it does not relay the request to the core because the core is in the process of servicing the previous IR2 interrupt and only a higher level request can inter rupt its process IR2 is not higher than IR2 When the master is in special fully nested mode the request is passed through to the core IR2 is equal to IR2 9 2 3 Interrupt Vectors Each interrupt request has a corresponding interrupt vector number The interrupt vector number is a pointer to a location in memory where the address of the interrupt s service routine is stored The relationship between the interrupt vector number and the location in memory of the inter rupt s service routine address depend
470. le Cycle 2 Idle E e 285 amp oo eRe T 9 E gt Sem E 28590 amp grt gt 2 E 259 QE meus aic gt T 9 S RE 8 gn secs QE ani ee ae E g 5 S CLK2 A25 1 Valid 4 NN Val Valid 2 Valid 1 BLE D C N 9 ween ts Wl suo MEE gt x o S gt 6 4 9 c c o x gt lt o c 2 en 0 gt lt lt a a LL cc cc Valid 4 Valid 3 LOCK Out 3 A2486 03 Figure 6 4 Basic Internal and External Bus Cycles 6 12 intel BUS INTERFACE UNIT 6 3 BUS CYCLES The processor executes five types of bus cycles Read Write Interrupt Halt shutdown Refresh 6 3 1 Read Cycle Read cycles are of two types In a pipelined cycle the address and status signals are output in the previous bus cycle to allow longer memory access times Pipelined cycles are described in Pipelined Cycle on page 6 19 In a nonpipelined cycle the address and status signals become valid during the first T state of the cycle T1 Figure 6 5 shows the timing for two nonpipelined read cycles one with and one without a wait state The sequence of signals for the nonpipeli
471. le could not execute When the processor receives an active HOLD input it completes the current bus cycle before re linquishing control of the bus Figure 6 7 shows the state diagram for the bus including the HOLD state During HOLD the processor can continue executing instructions that are already in its prefetch queue Program execution is delayed if a read cycle is needed while the processor is in the HOLD state The processor can queue one write cycle internally pending the return of bus access if more than one write cycle is needed program execution is delayed until HOLD is released and the pro cessor regains control of the bus HOLD has priority over most core bus cycles but is not recognized under certain conditions During locked cycles Between two interrupt acknowledge cycles LOCK asserted During misaligned word transfers LOCK not asserted During doubleword 32 bit transfers LOCK not asserted During misaligned doubleword transfers LOCK not asserted During an active RESET signal HOLD is recognized during the time between the falling edge of RESET and the first instruction fetch inputs are ignored while the processor is in the HOLD state except for the following HOLD pin It is monitored to determine when the processor may regain control of the bus RESET pin It is of a higher priority than HOLD An active RESET input reinitializes the device 6 36 intel BUS INTERFACE UNIT NMI
472. leWDTInterrupt Real Protected Mode No changes required OKCKCKCKCkCkCKCKCkCkCKCKCkCk Kk kk Ck KC Kk Ck extern void EnableWDTInterrupt void InitICUSlave ICU TRIGGER EDGE 0x30 0 Initialize Slave ICU SetIRQVector wdtISR 15 INTERRUPT ISR Puts address of interrupt service 17 15 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel routine in Interrupt Vector Table Enable8259Interrupt IR2 IR7 Enable slave interrupt to master IR2 Enable slave IR2 enable Enable Interrupts EnableWDTInterrupt RRR IKK KKK I KK IK IK RK AIA IRR Kk Ck kk k IRR IR AR Kk Ck Kk k k Kk Ck kk k kk k k kk k k k k ek wdtISR Description Interrupt Service Routine for Watchdog Timer Parameters None Returns None Assumptions None Syntax Not called by user Interrupt Control Unit executes this routine upon acknowledgment of a WDT interrupt Real Protected Mode No changes required eK RR AR IKK k k k I k k kk k k k k ARR IR AR IRR IA void interrupt far wdtISR void SerialWriteStr SIO PORT Executing WDT ISR Prints out to Serial Port as a demonstration NonSpecificEOI wdtISR 17 16 intel 1 g JTAG TEST LOGIC UNIT 18 JTAG TEST LOGIC UNIT The JTAG test logic unit enables you to test both the device logic and the interconnections be tween the device and the board system it is plugged into The ter
473. llel Output of IR IDCode X New Instruction TDO Enable Inactive Inactive Don t care or undefined A2361 01 Figure 18 5 Internal and External Timing for Loading the Instruction Register 18 12 intel JTAG TEST LOGIC UNIT TMS Controller State eade uius axa HUS erepdn amp ie 5 g w 5 18 1 26 Hd 129jeS 2 5 Es zt TDI Data Input to IR R Shift Register Parallel Output of IR Instruction D g a Input to TDR TDR Shift Register Parallel Output of TDR Old Data New Data ueog HI 1099 IDCode 1 91607 1591 Instruction Register Test Data Register Cus TDO Don t care or undefined A2362 01 Figure 18 6 Internal and External Timing for Loading a Data Register 18 13 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 18 5 DESIGN CONSIDERATIONS This section outlines considerations for the test logic unit The JTAG Test Logic Unit must be reset upon power up using the TRST pin To do this invert the RESET signal and send this inverted RESET to the TRST pin If this is not done the processor may power up with the JTAG test logic unit in control of the device pins and the system does not initialize properly For system level in circuit emulation use the HIGHZ instruction to enter ONCE m
474. low remapping of peripheral addresses and interrupt assignments Refer to Chapter 10 TIMER COUNTER UNIT Asynchronous Features two independent universal asynchronous receiver and transmitter UART Serial I O units which are functionally equivalent to National Semiconductor s NS16450 Each SIO Unit channel contains a baud rate generator transmitter receiver and modem control unit Receive and transmit interrupt signals can be connected to the ICU controller and DMA controller Refer to Chapter 11 ASYNCHRONOUS SERIAL UNIT Direct Memory Access DMA Controller Transfers internal or external data between any combination of memory and I O devices for the entire 26 bit address bus The two independent channels operate in 16 or 8 bit bus mode Buffer chaining allows data to be transferred into noncontiguous memory buffers The DMA channels can be tied to any of the serial devices to support high data rates minimizing processor interruptions Provides a special two cycle mode that uses only one channel for memory to memory transfers Bus arbitration logic resolves priority conflicts between the DMA channels the refresh control unit and an external bus master SIO and SSIO interrupts can be connected to DMA for high speed transfers Backward compatible with 8237A Refer to Chapter 12 DMA CONTROLLER 2 3 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Table 2 2 Embedded Application s
475. lowing a count write the count is loaded 3 Oneach succeeding CLKIN pulse the count is decremented 4 When the count reaches terminal count OUTn is driven high NOTE Writing a count of N causes a rising edge on OUT in N 1 CLKINn pulses provided GATEn remains high and count was written before the rising edge of CLKINnr 10 6 intel TIMER COUNTER UNIT Control Word 10H COUnt 4 Writes to 1 1 1 1 1 1 1 1 CLKINn GATEn 1 1 OUTn 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Count 2 2 ooo2 0001 0000 FFFF FFFE A2311 01 Figure 10 2 Mode 0 Basic Operation Figure 10 3 shows suspending the counting sequence A low level on causes the counter to suspend counting both the state of OUTn and the count remain unchanged A high level on GATEn resumes counting Writes to Counter n CLKINn GATEn OUTn Count A2394 02 Figure 10 3 Mode 0 Disabling the Count 10 7 Intel386 EX EMBEDDED PROCESSOR USER S MANUAL intel Figure 10 4 shows writing a new count before the current count reaches zero The counter loads the new count on the CLKINn pulse after you write it then decrements this new count on each succeeding CLKINn pulse OUTn remains low until the new count reaches zero Control Word 10H Count 3 Coun Writes to Counter n CLKINn GATEn OUTn Co
476. ly rearranged in a circular manner For example if you specify IR5 as the lowest level IR6 becomes the highest level IR7 becomes the second highest and so on with IRA the second lowest Automatic Rotation This method assigns an IR signal to the lowest level after the core services its interrupt As with specific rotation the other signals are automatically rearranged in a circular manner For example the IRA signal is assigned the lowest level after the core services its interrupt IR5 becomes the highest level IR6 becomes the second highest and so on with IR3 the second lowest 9 6 intel INTERRUPT CONTROL UNIT Default Highest Level Specific Automatic Automatic Rotation Rotation Rotation Before After Becomes Highest Becomes Highest Level Highest Level Before Level Being Serviced Assigned Lowest Specified Level Lowest After Being Level Serviced A2303 02 Figure 9 2 Methods for Changing the Default Interrupt Structure 9 2 2 2 Determining Priority There are three modes that determine relative priorities 1 whether a level higher lower or equal to another level has higher or lower interrupt priority Fully nested Special fully nested In the fully nested mode higher level IR signals have higher interrupt priority In this mode when an 82C59A receives multiple interrupt requests it passes the highest level request to the core or to the master if the 82 59 is a slave T
477. m Counter Reload 17 12 17 6 3 Watchdog Timer Unit Code Examples 17 12 xi Intel386 EX MICROPROCESSOR USER S MANUAL intel CHAPTER 18 JTAG TEST LOGIC UNIT 182 TEST LOGIC UNIT 0718 3 19 2 1 TestAccess Port e e e tee dec 18 3 18 2 2 Test Access Port TAP Controller 18 4 18 2 3 Instruction Register esiotsa LOOT 8 2 4 Data Registers rette 18 8 18 93 TESTING ino E pe ere a Hr aa ae 18 10 18 3 1 Identifying the Device ee eene tet i iere e de d tat 18 10 18 3 2 Bypassing Devices on a Board 18 10 18 3 8 Sampling Device Operation and Preloading Data 18 10 18 3 4 Testing the Interconnections 18 10 18 3 5 Disabling the Output Drivers ooo ee sse emen 18 11 18 4 TIMING 18 12 185 DESIGN CONSIDERATIONSGS eee emm emen 18 14 APPENDIX A SIGNAL DESCRIPTIONS APPENDIX B COMPATIBILITY WITH THE PC AT ARCHITECTURE B 1 HARDWARE DEPARTURES FROM PC AT SYSTEM ARCHITECTURE B 1 B 1 1 DMA Uni rire tries cite e E Meo ftn ind dra tta t o B 1 B 1 2 Industry Standard Bus ISA Signals sse B 2 B 1 3 Interrupt Control Unit ates
478. m J7AG refers to the Joint Test Action Group the IEEE technical subcommittee that developed the testability standard published as Standard 1149 1 1990 IEEE Standard Test Access Port and Boundary Scan Architecture and its supplement Standard 1149 1 1993 The Intel386 EX Embedded Processor JTAG test log ic unit is fully compliant with this standard You can use the JTAG unit for other purposes For example you can perform in system program ming of flash memory refer to AP 720 Programming Flash Memory through the Intel386 EX Embedded Processor JTAG Port order number 272753 This chapter is organized as follows Overview see below Test Logic Unit Operation page 18 3 Testing page 18 10 Timing Information page 18 12 Design Considerations page 18 14 18 1 OVERVIEW As the title of the IEEE standard suggests two major components of the test logic unit are the test access port and the boundary scan register The term test access port TAP refers to the dedicat ed input and output pins through which a tester communicates with the test logic unit The term boundary scan refers to the ability to scan observe the signals at the boundary the pins of a device A boundary scan cell resides at each pin These cells are connected serially to form the boundary scan register which allows you to control or observe every device pin except the clock pin the power and ground pins and the test access port pins The test log
479. m a masked address that is compared to memory address bits A15 11 or I O address bits A5 1 10 CASMM SMM Address Bit other than SMM If this bit is set and unmasked the CSU activates the chip select channel only while the processor is SMM and not in a hold state Otherwise the CSU activates the channel only when processor is operating in a mode Setting the SMM mask bit in the channel s mask low register masks this bit When this bit is masked an address match activates the chip select regardless of whether the processor is in SMM or not 9 BS16 Bus Size 16 bit 0 All bus cycles to addresses in the channel s address block are byte 0 Configures the channel for an I O addresses 1 Configures the channel for memory addresses wide 1 Bus cycles are 16 bits unless the bus size control pin BS8 is asserted 8 MEM Bus Cycle Type 7 RDY Bus Ready Enable the bus cycle 0 External READY is ignored READY generated by CSU to terminate 1 Requires that external READY be active to complete a bus cycle This bit must be set to extend wait states beyond the number determined by WS4 0 see Bus Cycle Length Control on page 14 11 6 5 Reserved for compatibility with future devices write zeros to these bits 4 0 54 0 Wait State Value cycle A zero value means no wait states WS4 0 defines the minimum number of wait states inserted into the bus Figur
480. m input signals to the package pins 1 Connects the SIOO modem input signals internally 5 3 Reserved These bits are undefined for compatibility with future devices do not modify these bits 2 SSBSRC SSIO Baud rate Generator Clock Source 0 Connects the internal PSCLK signal to the SSIO baud rate generator 1 Connects the internal SERCLK signal to the SSIO baud rate generator 1 S1BSRC SIO1 Baud rate Generator Clock Source 0 Connects the COMCLK pin to the SIO1 baud rate generator 1 Connects the internal SERCLK signal to the SIO1 baud rate generator 0 SOBSRC SIO0 Baud rate Generator Clock Source 0 Connects the COMCLK pin to the SIOO baud rate generator 1 Connects the internal SERCLK signal to the 5100 baud rate generator Figure 5 10 SIO and SSIO Configuration Register SIOCFG Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 5 2 5 Synchronous Serial I O Configuration The synchronous serial I O unit SSIO is shown in Figure 5 11 Its single configuration register bit is in the SIOCFG register Figure 5 10 The transmit buffer empty and receive buffer full sig nals SSTBE and SSRBF go to the DMA unit Figure 5 2 and an interrupt signal SSIOINT goes to the ICU Figure 5 4 Depending on the settings in the SSIOCONI register see Chapter 13 SSIOINT is asserted for one of two conditions the receive buffer is full or the transmit buffer is empty N
481. master that does not have a slave cascaded from it Figure 9 4 illustrates the process that occurs when a slave receives an interrupt request Figure 9 5 continues by showing what happens when the master receives a slave interrupt request for example an IR2 request 9 10 intel INTERRUPT CONTROL UNIT Master receives an interrupt request From a non slave source Master sets the request s pending bit operating in 1 fully nested ls S master made request special operating in No mask mode iaj enabled special fully enabled nested mode Is request higher level than any set in service request equal or higher than any set in service bits in service bit for this request set Master sends request to CPU CPU initiates interrupt acknowledge cycle Master clears request s pending bit sets its in service bit and puts its interrupt vector number on the bus Master clears its in service bit The Yes CPU uses its operating mode and the interrupt vector number to find the interrupt service routine s address CPU begins processing interrupt Is master in mode No The CPU uses its operating mode and the interrupt vector number to find the interrupt service routine s address CPU begins processing interrupt The interrupt service routine sends an EOI command causing the master to clear its in serv
482. memory space External bus ready is Disabled SMM region is accessible during SMI access only Parameters None 14 22 intel CHIP SELECT UNIT Assumptions REMAPCFG register has Expanded I O space access enabled ESE bit set ef void Init_CSU void SetEXRegWord UCSADL 0x700 Configure the upper chip select _SetEXRegWord UCSADH 0x0 _SetEXRegWord UCSMSKL OxFCO01 SetEXRegWord UCSMSKH 0 7 _SetEXRegWord CS4ADL 0x300 Configure chip select 4 _SetEXRegWord CS4ADH 0x8 _SetEXRegWord CS4MSKL OxF801 _SetEXRegWord CS4MSKH 0 7 14 23 intel 15 REFRESH CONTROL UNIT 15 REFRESH CONTROL UNIT The Refresh Control Unit RCU simplifies the interface between the processor and a dynamic random access memory device by providing a way to generate periodic refresh requests and refresh addresses These refresh requests and addresses can then be used by an external DRAM controller to generate the appropriate DRAM signals and addresses needed to perform refresh operations The RCU can be used in conjunction with the Chip select Unit to generate chip select signals for DRAM regions these signals can be used by the external DRAM controller to initiate refresh cycles The can also be used when interfacing to pseudo static random access memory PSRAM This type of memory has an interface similar to a static random access memory SRAM but re quires a periodic ref
483. mple a word transfer involving D15 0 and activating BHE and BLE is aligned Word transfers that cross a word boundary or doubleword transfers that cross two word bound aries are called nonaligned transfers Nonaligned word transfers require two bus cycles while nonaligned doubleword transfers require three The processor automatically generates these cy cles For example A word 16 bit transfer at byte address 03H requires two byte transfers The first activates word address 04H and uses D7 0 to write or read the upper byte of the 16 bit word The second activates word address 02H and uses D15 8 to write or read the lower byte of the 16 bit word 6 9 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel A doubleword 32 bit transfer at byte address 03H requires three transfers one word transfer and two byte transfers first word transfer activates word address 04H and uses D15 0 to write or read the middle 2 bytes of the 32 bit doubleword The next transfer activates word address 06H and uses D7 0 to write or read the upper byte of the 32 bit word The last transfer activates word address 02H and uses D15 8 to write or read the lower byte of the 32 bit word Table 6 3 shows the sequence of bus cycles for all possible alignments and operand length trans fers Even though nonaligned transfers are transparent to a program they are slower than aligned transfers due to the extra
484. n 7 DLAB Divisor Latch Access Bit This bit determines which of the multiplexed registers is accessed 0 Allows access to the receiver and transmit buffer registers RBRn and TBRn and the interrupt enable register IERn 1 Allows access to the divisor latch registers DLLn and DLHn 6 SB Set Break 0 No effect on TXDn 1 Forces the TXDn pin to the spacing logic 0 state for as long as bit is set SP Sticky Parity Even Parity Select and Parity Enable EPS These bits determine whether the control logic produces during transmission or checks for during reception even odd no or forced PEN parity SP EPS PEN Function X X 0 parity disabled no parity option 0 0 1 produce or check for odd parity 0 1 1 produce or check for even parity 1 0 1 produce or check for forced parity parity bit 1 1 1 1 produce or check for forced parity parity bit 0 2 STB Stop Bits This bit specifies the number of stop bits transmitted and received in each serial character 0 1 stop bit 1 2 stop bits 1 5 stop bits for 5 bit characters 1 0 WLS1 0 Word Length Select These bits specify the number of data bits in each transmitted or received serial character 00 5 bit character 01 6 bit character 10 7 bit character 11 8 bit character Figure 11 15 Serial Line Control Register LCR n 11 25 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 11 3 7 Serial Line Status Register LSRn Use LSRnz
485. n CPU idle mode the WDT is disabled only if it is in watchdog mode Since no software can execute while the CPU is in idle mode the software watchdog is unnecessary The WDT operates normally in general purpose timer and bus monitor modes if the CPU is in idle mode In CPU powerdown mode the WDT unit is disabled like all other peripherals 17 2 2 General purpose Timer Mode The WDT defaults to general purpose timer mode after reset If your system has no requirement for a software watchdog or a bus monitor you can use the WDT in this mode At reset the down counter begins decrementing once every clock cycle beginning at 3FFFFFH the initial values of the reload and count registers Unless you intervene the WDT times out after 4 million 222 cessor clock cycles Software can read the count registers WDTCNTH and WDTCNTL at any time to determine the current value of the down counter You might for example read the count when one event occurs read it again when a second event occurs then calculate the elapsed time between the two events When the down counter reaches zero the 8 state binary counter drives the WDTOUT pin high for eight processor clock cycles 16 CLK2 cycles During the clock cycle immediately after the down counter reaches zero the down counter is reloaded with the contents of the reload registers If you want fewer than 4 million 222 processor clock cycles between WDT timeouts write a 32 bit reload value
486. n Registers PINCFG and PnCFG ins 1 3 11 3 2 SIO and SSIO Configuration Register SIOCFG 11 3 3 Divisor Latch Registers DLLn and DLHn esee 11 3 4 Transmit Buffer Register 11 3 5 Receive Buffer Register RBRN sse eee emen 11 3 6 Serial Line Control Register e 11 3 7 Serial Line Status Register 15 11 3 8 Interrupt Enable Register IERN em 11 3 9 Interrupt ID Register eee ene 11 3 10 Modem Control Register 11 3 11 Modem Status Register 11 3 12 Scratch Pad Register SCRn sse eee 11 4 PROGRAMMING CONSIDERATIONS 11 4 1 Asynchronous Serial I O Unit Code Examples CHAPTER 12 DMA CONTROLLER 12 1 4 Terminology 12 3 12 1 2 rid ee 12 2 DMA OPERATION reete enti rne dau dene ble 12 5 12 2 1 DMA Transfers 12 2 2 Bus Cycle Options AG Data Transient 12 5 12 2 2 1 Mode 12 2 24 Two Cycle Mode EE 12 6 12 2 2 3 Programmable DMA Transfer Direction 2 12 6 12 2 2 4 Ready Generation For DMA Cycles seem 12 7 12 2 2 5 Usage of the 4 Byte Temporary Register
487. n for I O mode clear its PnCFG bit e To configure a pin for peripheral mode set its PnCFG bit 16 3 DESIGN CONSIDERATIONS This section outlines design considerations for the I O ports Source and sink current are different between the three ports Consult the latest Intel386 EX Embedded Microprocessor datasheet order number 272420 for exact specifications Use read modify write operations to set and clear bits 16 3 1 Pin Status During and After Reset A device reset applies an asynchronous reset signal to the port pins To avoid contention with ex ternal drivers the pins are configured as inputs in I O port mode To prevent pins from floating a weak pull up or pull down resistor holds each pin high or low Table 16 1 Writing to the PnCFG register regardless of the value written turns off these resistors For example writing any value to PICFG after a reset turns off the weak pull down resistors on P1 7 P1 6 and the weak pull up resistors on P1 5 P1 0 The resistors remain off until the next reset 16 10 intel INPUT OUTPUT PORTS 16 4 PROGRAMMING CONSIDERATIONS 16 4 1 I O Ports Code Example The following code example contains a software routine that initializes the I O port pins See Ap pendix C for the included header files include lt conio h gt include 80386ex h include ev386ex h RR kkk kkk kkk ee k k k k k k k k k k k k k k k k k k k k k k k k k k ee k k k Ck ck ko kck ck k c
488. n maintain the same throughput as the nonpipelined bus Only when the bus pipeline gets broken by entering an idle or hold state is the additional one clock overhead required to start the pipe again for the next train of pipelined bus cycles The first bus cycle after an idle bus state is always nonpipelined Systems that use pipelining typ ically assert NA during this cycle to enter pipelining To initiate pipelining this nonpipelined cycle must be extended by at least one T state so that the address and status can be pipelined be fore the end of the cycle Subsequent cycles can be pipelined as long as no idle bus cycles occur Specifically NA is sampled at the start of phase 2 of any T state in which the address and status signals have been active for one T state and a new cycle has begun The first T2 state of a nonpipelined cycle the second T state The TIP state of a pipelined cycle the first T state Any wait state of a nonpipelined or pipelined cycle unless NA has already been sampled active Once NA is sampled active it remains active internally throughout the current bus cycle When NA and READY are active in the same T2 state the state of NA is irrelevant because READY causes the start of a new bus cycle Therefore the new address and status signals are always driven regardless of the state of NA NA has no effect on a refresh cycle because the refresh cycle is entered from an idle bus state and exits to an idl
489. n options Figure 10 23 Port 3 Configuration Register P3CFG 10 22 intel TIMER COUNTER UNIT Use PINCFG bit 5 to connect TMROUT2 TMRCLK2 and TM RGATE2 to package pins PINCFG 7 read write Pin Configuration Expanded Addr F826H ISA Addr Reset State 00H PM6 PM5 PM4 PM3 PM2 PM1 PMO Bit Number Bit Mnemonic Function 7 Reserved This bit is undefined for compatibility with future devices do not modify this bit PM6 Pin Mode 0 Selects CS6 at the package pin 1 Selects REFRESH at the package pin PM5 Pin Mode 0 Selects the coprocessor signals PEREQ BUSY and ERROR Z at the package pins 1 Selects the timer control unit signals TMROUT2 TMRCLK2 and TMRGATE2 at the package pins PM4 Pin Mode 0 Selects DACKO at the package pin 1 Selects CS5 at the package pin 0 Selects EOP at the package pin 1 Selects 51 at the package pin PM2 Pin Mode 0 Selects DACK1 at the package pin 1 Selects TXD1 at the package pin PM1 Pin Mode 0 Selects SRXCLK at the package pin 1 Selects DTR1 at the package pin PMO Pin Mode 0 Selects SSIOTX at the package pin 1 Selects RTS1 at the package pin Figure 10 24 Pin Configuration Register PINCFG 10 23 Intel386 EX EMBEDDED PR
490. n the port pin function rather than the interrupt function is enabled at the pin is internally connected to the ICU s respective interrupt request input The device pins INT7 INT6 and INT4 must be enabled using register bits in order to be used The port 3 configuration register P3CFG controls INT3 0 interrupt source connections and the interrupt configuration register INTCFG controls the INT9 4 inter rupt source connections The modem control registers MCR1 and MCRO are also used to con trol the INT9 8 interrupt source connections 9 4 intel INTERRUPT CONTROL UNIT Table 9 1 82C59A Master and Slave Interrupt Sources Master IR Connected Slave Connected Line Source by IR Line Spuren by IRO TMROUTO Hardwired IRO Vss INTCFG 0 0 timer control unit INT4 INTCFG 0 1 device pin IR1 Vss P3CFG 2 0 IR1 SSIOINT INTCFG 1 0 SSIO unit INTO P3CFG 2 1 INT5 INTCFG 1 1 device pin Device pin IR2 Slave 82C59A Hardwired IR2 TMROUT1 Hardwired Cascade timer control unit IR3 SIOINT1 INTCFG 6 0 IR3 TMROUT2 Hardwired SIO unit P3CFG 1 0 timer control unit INT8 INTCFG 6 1 device pin P3CFG 1 1 MCRO 3 1 IRA SIOINTO INTCFG 5 0 IR4 DMAINT INTCFG 4 0 INT9 INTCFG 5 1 INT6 INTCFG 4 1 device pin P3CFG 0 1 device pin MCR1 3 1 IR5 Vss P3CFG 3 0 IR5 INT6 INTCFG 4 0 device pin INTCFG 2 1 INT1 P3CFG 3 1 DMAINT INTCFG 4 1 device pin DMA unit INT
491. nMSKH 14 19 Chip select Low Mask Registers CSnMSKL 14 20 Refresh Control Unit eene ene 15 3 Refresh Clock Interval Register 15 7 Refresh Control Register RFSCON sse eee 19 8 Refresh Base Address Register RFSBAD sse 15 9 Refresh Address Register RFSADD essem 15 10 Connections to Ensure Refresh of All Rows in an 8 Bit Wide PSRAM Device 15 11 RAS Only Refresh Logic Paged 15 13 RAS Only Refresh Logic Non aedes ee 15 14 Port Block Diagram ele he 16 2 Logic Diagram of a Bi directional Port EU 1653 Port n Configuration Register iin EE e cid HR Ed 16 7 Port Direction Register PnDIR sss eene 16 8 Port Data Latch Register 16 8 Port Pin State Register 16 9 Watchdog Timer Unit Connections 17 2 WDT Counter Value Registers WDTCNTH and WDTCNTL WDT Status Register 17 9 intel Figure 17 4 17 5 18 1 18 2 18 3 18 4 18 5 18 6 B 2 E 1 WDT Reload Value Registers WDTRLDH and WDTRLDL Power Control Register Test Logic Unit Connections E T
492. nable 0 Connects GATEn to either the Voc pin or the TMRGATEn pin 1 Enables GT2CON GT1CON and GTOCON to control the connections to GATE2 GATE1 and GATEO respectively 5 GT2CON Gate 2 Connection SWGTEN GT2CON 0 0 Connects GATE2 to 0 1 Connects GATE2 to the TMRGATE2 pin 1 0 Turns GATE2 off 1 1 Turns GATE2 on 4 CK2CON Clock 2 Connection 0 Connects CLKIN2 to the internal PSCLK signal 1 Connects CLKIN2 to the TMRCLK pin 3 GT1CON Gate 1 Connection SWGTEN GT1CON 0 0 Connects GATE1 to 0 1 Connects GATE1 to the TMRGATE1 pin 1 0 Turns GATE1 off 1 1 Turns GATE1 on 2 CK1CON Clock 1 Connection 0 Connects CLKIN1 to the internal PSCLK signal 1 Connects CLKIN1 to the TMRCLK1 pin 1 GTOCON Gate 0 Connection SWGTEN GTOCON 0 0 Connects GATEO to Vec 0 1 Connects GATEO to the TMRGATE1 pin 1 0 Turns GATEO off 1 1 Turns GATEO on 0 CKOCON Clock 0 Connection 0 Connects CLKINO to the internal PSCLK signal 1 Connects CLKINO to the TMRCLKO pin D 63 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel D 66 TMRCON Timer Control Control Word Format Expanded Addr F043H TMRCON ISA Addr 0043H Reset State XXH 7 0 SC1 SCO RW1 RWO M2 M1 MO CNTFMT Bit Bit 2 Number Mnemonic Function 7 6 SC1 0 Select Counter Use these bits to specify a particular counter The selections you make for bits 5
493. nal If the Boot device is only an 8 bit device then BS8 must be asserted whenever UCS is active until the UCS channel can be reprogrammed to reflect an 8 bit region One way of doing this is by connecting the UCS pin directly to the BS8 pin if there are no other devices that need to use the BS8 pin If UCS is tied directly to BS8 then the UCS channel need not be programmed to reflect an 8 bit region Ifthe Port92 CPU only RESET is used described in Chapter 5 the UCS channel must remain enabled for the top of the memory address space a CPU only RESET does not affect the chip select registers and therefore the UCS channel does not re initialize to its reset state Ifarbitrary chip select regions are required to access external memory and I O devices and a single channel can not be programmed to accommodate the address space of these regions multiple chip select signals can be ORed to create a single chip enable to a device For example a 512 Kbyte region chip select signal starting on a 256 Kbyte boundary can be created by ORing two 256 Kbyte chip select signals Refer to Chapter 6 Design Considerations on page 6 38 for examples of using chip select signals to access external devices 14 21 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 14 6 PROGRAMMING CONSIDERATIONS When programming the CSU consider the following When programming a chip select channel always program the Low Mask Re
494. nals and to enable the master s external cascade signals When enabled the cascade signals appear on address lines A18 16 during interrupt acknowledge cycles Every external slave monitors these lines to determine whether it is the slave being addressed Interrupt Configuration Expanded Addr F832H INTCFG ISA Addr read write Reset State 00H 7 0 CE IR3 IRA SWAP IR6 IR5 IR4 IR1 IRO Bit Bit Number Mnemonic Function 7 CE Cascade Enable 0 Disables the cascade signals CAS2 0 from appearing on the A18 16 address lines during interrupt acknowledge cycles 1 Enables the cascade signals CAS2 0 providing access to external slave 82C59A devices The cascade signals are used to address specific slaves If enabled slave IDs appear on the A18 16 address lines during interrupt acknowledge cycles but are high during idle cycles 6 IR3 Internal Master IR3 Connection See Table 5 1 on page 5 8 for all the IR3 configuration options 5 IR4 Internal Master IR4 Connection See Table 5 2 on page 5 8 for all the IR4 configuration options 4 SWAP INT6 DMAINT Connection 0 Connects DMAINT to the slave IR4 Connects INT6 to the slave IR5 1 Connects the INT6 pin to the slave IR4 Connects DMAINT to the slave 5 3 IR6 Internal Slave IR6 Connection 0 Connects Vss to the slave IR6 signal 1 Connects the INT7 pin to the slave IR6 signal 2 IR5 IRA Internal Slave IR
495. nation When a requester suspends a buffer transfer the contents of the partially filled temporary buffer are stored until the transfer is restart ed At this point the DMA performs read cycles until the buffer is full then performs write cycles to transfer the data to the destination 12 2 2 3 Programmable DMA Transfer Direction The relationship between Requester Target Source and Destination is determined by the pro grammable DMA transfer direction The transfer directions are defined as Write Read or Verify The following table describes which operations are being performed by the Requester and Target for each transfer direction In this table the device being read is the Source and the device being written is the Destination The Verify cycle is used to perform a data read only No write cycle is indicated or assumed in a Verify cycle The Verify cycle is useful for validating block fill opera tions An external comparator must be provided to do any comparisons on the data read Table 12 2 Operations Performed During Transfer Read Write Verify Requester Read Write Read Target Write Read Read A special case not indicated in this table is when the Requester is neither the Source nor Destina tion One example of this case would be when the DMA is being used to transfer data from one memory or I O location to another and one of the timer outputs is being used to initiate that trans fer In this case the
496. ncy 6 37 timing 6 36 Index 1 INTEL386 EX MICROPROCESSOR USER S MANUAL operation during idle mode 8 5 overview 6 1 6 3 pipelining 6 8 ready logic 6 10 See also Bus control arbitration signals 6 3 6 4 Bus signals departures from PC AT architecture 2 3 Bus size control for chip selects 14 11 BYPASS 18 2 C CAS before RAS refresh 15 1 15 12 Chip select unit 14 1 14 24 operation 14 2 14 12 bus cycle length adjustments 14 12 bus cycle length control 14 11 bus size control 14 11 defining a channel s address block 14 2 14 9 overlapping regions 14 11 system management mode support 14 10 overview 14 1 programming 14 13 14 20 considerations 14 22 CSnADH 14 17 D 8 CSnADL 14 18 D 9 CSnMSKH 14 19 D 10 CSnMSKL 14 20 D 11 P2CFG register 14 16 PINCFG register 14 15 UCSADH 14 17 D 8 UCSADL 14 18 D 9 UCSMSKH 14 19 D 10 UCSMSKL 14 20 D 11 register addresses 4 17 D 3 registers 14 14 14 20 signals 14 13 Clear defined 1 5 Clock and power management unit 8 1 8 13 clock generation logic 8 1 8 3 controlling power management modes 8 8 controlling PSCLK frequency 8 7 design considerations powerdown considerations 8 13 reset considerations 8 11 Index 2 idle mode 8 9 overview 8 1 8 7 power management logic 8 3 8 5 powerdown mode 8 10 registers 8 6 CLKPRS 8 7 PWRCON 8 8 reset considerations 8 11 signals 8 6 synchronization 8 3 timing diagram 8 9 8
497. nd RIn are disconnected from the pins and controlled by modem control register bits The modem control output pins RTSn DTRn are forced to their inactive states 11 12 intel ASYNCHRONOUS SERIAL UNIT 11 2 6 SIO Interrupt and DMA Sources 11 2 6 1 SIO Interrupt Sources Each SIO channel has four status signals receiver line status receiver buffer full transmit buffer empty and modem status An overrun error parity error framing error or break condition can activate the receiver line status signal When the receiver transfers data from its shift register to its buffer it activates the receive buffer full signal When the transmitter transfers data from its transmit buffer to its transmit shift register it activates the transmit buffer empty signal A change on any of the modem control input signals activates the modem status signal When the modem signals are connected internally either through the configuration register or the diagnostic mode changes of state still activate the modem status signal For these cases however the signal values are controlled by register bits rather than by external input signals Each of the four status signals can be used as an interrupt request source for the SIOINTn signal The Interrupt Enable register IER is used to enable any or all of the status signals as interrupt sources When an SIOINTn occurs the IP bit bit 0 of the Interrupt ID register is cleared and the interrupt
498. nd using it 6 31 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel The BS8 cycle generates additional bus cycles for read and write cycles only For interrupt and halt shutdown cycles the accesses are byte wide and the BS8 signal is ignored For a refresh cycle the byte enables are both disabled and the BS8 signal is ignored 6 32 NOTE If a BS8 cycle requires an additional bus cycle the processor retains the current address for the second cycle Address pipelining cannot be used with BS8 cycles because address pipelining requires that the next address be generated on the bus before the end of the current bus cycle NA must be kept deasserted during the T2 states of BS8 memory cycles NA is ignored in all I O cycles NOTE BS8 must be inactive at the falling edge of PH2 of the T1 state of a non BS8 cycle for example if the current cycle is a BS8 cycle BS8 asserted and the next cycle is not a BS8 cycle BS8 must be deasserted before the end of the state of the next cycle i e the 58 cycle BUS INTERFACE UNIT o E o BQ 7 o E 2 gt as i2 PARE or I 2 B gt __ amp c 251 o gt a Soe m cee o29 T S r N Soe mzp d zz zl g S CLK2 N 2 gt om E ee ond Leos EE 27
499. ndard PC AT architecture and the ways in which it departs from the standard Appendix C Example Code Header Files contains the header files called by the code ex amples that are included in several chapters of this manual Appendix D System Register Quick Reference contains an alphabetical list of registers Appendix E Instruction Set Summary lists all instructions and their clock counts Glossary defines terms with special meaning used throughout this manual Index lists key topics with page number references intel GUIDE TO THIS MANUAL 1 2 NOTATIONAL CONVENTIONS The following notations are used throughout this manual The pound symbol appended to a signal name indicates that the signal is active low Variables Variables are shown in italics Variables must be replaced with correct values New Terms New terms are shown in italics See the Glossary for a brief definition of commonly used terms Instructions Instruction mnemonics are shown in upper case When you are programming instructions are not case sensitive You may use either upper or lower case Numbers Hexadecimal numbers are represented by a string of hexadecimal digits followed by the character H A zero prefix is added to numbers that begin with A through F For example FF is shown as OF FH Decimal and binary numbers are represented by their customary notations That is 255 is a decimal number and 1111 1111 is a binary num
500. ne output It is through these pins that all communication with the test logic unit takes place This unit has its own clock TCK and reset TRST pins so it is independent of the rest of the device The test logic unit can read or write its registers even if the rest of the device is in reset or powerdown CAUTION The Test Logic Unit must be reset upon power up using the TRST pin To do this invert the RESET signal and send this inverted RESET to the TRST pin If this is not done the processor may power up with the test logic unit in control of the device pins and the system does not initialize properly The test logic unit allows you to shift test instructions and test data into the device and to read the results of the test A tester that is an external bus master such as automatic test equipment or a component that interfaces to a higher level test bus controls the TAP controller s operation by applying signals to the clock TCK and test mode select TMS inputs Instructions and data are shifted serially from the test data input TDI to the test data output TDO Table 18 1 describes the test access port pins Table 18 1 Test Access Port Dedicated Pins Pin Description TCK Test Clock Input Provides the clock input for the test logic unit An external signal must provide a maximum input frequency of one half the CLK2 input frequency TCK is driven by the test logic unit s control circ
501. nects the SIO1 modem input signals to the package pins 1 Connects the SIO1 modem input signals internally 6 SOM SIO0 Modem Signal Connections 0 Connects the SIOO modem input signals to the package pins 1 Connects the SIOO modem input signals internally 5 3 Reserved These bits are undefined for compatibility with future devices do not modify these bits 2 SSBSRC SSIO Baud rate Generator Clock Source 0 Connects the internal PSCLK signal to the SSIO baud rate generator 1 Connects the internal SERCLK signal to the SSIO baud rate generator 1 S1BSRC SIO1 Baud rate Generator Clock Source 0 Connects the COMCLK pin to the SIO1 baud rate generator 1 Connects the internal SERCLK signal to the SIO1 baud rate generator 0 SOBSRC 5100 Baud rate Generator Clock Source 0 Connects the COMCLK pin to the SIOO baud rate generator 1 Connects the internal SERCLK signal to the 5100 baud rate generator 13 18 Figure 13 16 SIO and SSIO Configuration Register SIOCFG intel SYNCHRONOUS SERIAL I O UNIT 13 3 3 Prescale Clock Register CLKPRS Use CLKPRS to program the PSCLK frequency Clock Prescale Register Expanded Addr F804H CLKPRS ISA Addr read write Reset State 0000H 15 8 PS8 7 0 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PSO Bit Bit Functi Number Mnemonic uneuon 15 9 Reserved These bits are undefined for compatibilit
502. ned read cycle is as follows 1 The processor initiates the cycle by driving the address bus and the status signals active and asserting ADS The type of bus cycle occurring is determined by the states of the address bus A25 1 byte enable pins BLE and BHE and bus status outputs W R M IO D C REFRESH and LOCK Because of output delays these signals should be sampled at the rising edge of the CLK2 signal that coincides with the falling edge of PH2 when ADS is definitely active For a read cycle the bus status outputs have the following states e W Rit is low e M IOft is high for a memory read and low for an I O read e Di Ctt is high for a memory or I O data read and low for a memory code read e REFRESHH is deasserted e LOCK is asserted for a locked cycle and deasserted for a nonlocked cycle In a read modify write sequence both the memory data read and memory data write cycles are locked No other bus master should be permitted to control the bus between two locked bus cycles The address bus byte enable pins and bus status pins with the exception of ADS remain active through the end of the read cycle At the start of phase 2 of T1 RD becomes active as the processor prepares the data bus for input This indicates that the processor is ready to accept data 6 13 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 6 14 When chip select region is enabled for the current read cycle but i
503. nent of the JTAG standard Chip select unit The internal peripheral that selects an external memory device during an external bus cycle The term clear refers to the value of a bit or the act of giving it a value If a bit is clear its value is 0 clearing a bit gives it a 0 value The act of making a signal inactive disabled The polarity high low is defined by the signal name Active low signals are designated by a pound symbol f suffix active high signals have no suffix To deassert RD is to drive it high to deassert HLDA is to drive it low Direct memory access controller The internal peripheral that allows external or internal peripherals to transfer information directly to or from the system The two channel DMA controller is an enhanced version of the industry standard 8237A DMA peripheral Addresses OH 03FFH The internal timers interrupt controller serial I O ports and DMA controller can Glossary 1 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel DOS compatible Mode Edge triggered Enhanced DOS Mode Expanded Address Space ICU Idle Mode Interrupt Latency Glossary 2 be mapped into this space In this manual the terms DOS address and PC AT address are synonymous The addressing mode in which the internal timer interrupt controller serial I O ports and DMA controller are mapped into the DOS address space This mode decodes only the lower 10 address bits so the
504. nges required eK RR AR IRR A IRR AA ARR Kk Ck kk KC KK Ck int DisableDMAHWRequests int nChannel WORD regDMAMSK 0 Check input ift nChannel DMA 10 amp amp nChannel DMA Channell return ERR BADINPUT regDMAMSK nChannel Set regDMAMSK CS to channel regDMAMSK amp 0x04 Set regDMAMSK HRM _SetEXRegByte DMAMSK regDMAMSK Set hw request mask for given channel return ERR_NONE ROKK IKK KKK IK KK IRR A ARR IIR IR IRR IR IR IRR IA IR IRR A k k k k k k k SetDMAReqIOAddr 12 53 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Description Sets the requester to an I O port address wIO for the DMA channel specified by nChannel Parameters nChannel channel for which to set Requester I O port address wIO I O address Returns None Assumptions None Syntax SetDMAReqIOAddr DMA 11 TBRO Sets Req to Serial Receiver Real Protected Mode No changes required Kk KC Kk int SetDMAReqIOAddr int nChannel WORD wIO WORD addrDMAReqO0 1 WORD addrDMAReq2 3 Check input if nChannel DMA 10 amp amp nChannel DMA 11 return ERR BADINPUT Set registers to correct channel addrDMAReq0 1 nChannel DMA 10 DMAOREQO 1 DMAIREQO 1 addrDMAReq2 3 nChannel DMA 10 DMAOREQ2 3 DMAIREOQ2 3 SetEXRegByte DMACLRBP 0x0 Clear th
505. nnel s Address Block Size Any ones that are to the left of the right most zero determine the number of blocks and the loca tions where the blocks are repeated This is best illustrated by the following four examples The examples assume the channel is configured for memory addresses however the concepts dis cussed also apply to I O configured channels 14 4 intel CHIP SELECT UNIT Example 1 This example establishes a single 32 Kbyte address block starting at 1340000H a 32 Kbyte boundary In this example the 15 bit channel address is the starting address of the channel s ac tive address block because there are 1 s in the channel mask where there 1 s in the channel address 15 1 15 bit Channel Address 010011010000000 15 bit Channel Mask 000000000001111 25 0 Channel Active Address 01001101000XXXX XXXXXXXXXXX Because the least significant 0 in the channel s mask is in bit position 5 this channel s active ad dress block size is 2 32 Kbytes Because there are no 1 s to the left of the right most 0 in the channel s mask the block is not repeated 1347FFFH Active 1340000H 14 5 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Example 2 This example establishes four 4 Kbyte address blocks starting at 0000000H 0002000H 0004000H and 0006000H 4 Kbyte boundaries 15 1 15 bit Channel Address 000000000000000 15 bit Chann
506. not invoke the Idle or Powerdown Mode Parameters None Returns None Assumptions None Syntax Mode Setting To Active Real Protected Mode No changes required eK RR A A IRR Kk Ck Ck kk CIC kk kk Kk IRR Kk AIA IR void Mode Setting To Active void BYTE pwrcon 0x00 pwrcon GetEXRegByte PWRCON clear lowest two bits of pwrcon pwrcon pwrcon amp Oxfc Set mode to active _SetEXRegByte PWRCON pwrcon ACTIVE Mode Setting To Active intel INTERRUPT CONTROL UNIT CHAPTER 9 INTERRUPT CONTROL UNIT The Interrupt Control Unit ICU consists of two cascaded interrupt controllers a master and a slave that allow internal peripherals and external devices through interrupt pins to interrupt the core through its interrupt input The interrupt control unit is functionally identical to two industry standard 82C59As connected in cascade The system supports a maximum of 15 simultaneous interrupt sources which can be individually or globally disabled The ICU passes the interrupts on to the core based on a pro grammable priority structure Though the ICU can only handle a maximum of 15 simultaneous sources a total of 18 interrupt sources can be connected to the ICU Eight of these interrupt sources come from internal periph erals and the other ten come from external pins To increase the number of possible interrupts you can cascade additional 82C59As to six of the external i
507. nt of the two channels bus arbitration set to no rotation external bus master request HOLD assigned to lowest priority level EOP sampling set to asynch no effect when DMA is used with internal peripherals DROn sampling set to synch no effect when DMA is used with internal peripherals Parameters None Returns None Assumptions None 12 57 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Syntax InitDMA Initialize DMA peripheral Real Protected Mode No changes required Fe RRR AR KR A IRR Ck Kk Ck kk Ck KC Kk kk void InitDMA void _SetEXRegByte DMACLR 0 0 Resets peripheral SetEXRegByte DMACMD1 0x0 DMACMD1 7 5 0 reserved DMACMD1 4 0 disable priority rotation enable DMACMD1 2 0 enable channel s 0 and 1 DMACMD1 1 0 0 reserved _SetEXRegByte DMACMD2 0x8 DMACMD2 7 4 0 reserved DMACMD2 3 2 2 assign HOLD to the lowest priority level DMACMD2 1 0 EOP samples input async DMACMD2 0 0 DRQn samples input async IK e e RRA KC Kk Ck Kk k k Kk Ck k k k k kk k k kk k k k k ek InitDMAlForSSIXmitterToMem Description This function prepares DMA channel 1 for transfers between the async serial port transmitter channel 0 and memory After calling this function a DMA transfer can be initiated by setting the Target address setting the transfer count
508. nt registers Enable the channel for the chaining buffer transfer mode This enables the DMAINT output Qe 6 Enable the DMAINT interrupt in the ICU and service it The service routine should load the transfer information for the next buffer transfer 7 Enable the channel by unmasking DREQn and setting bit 2 in DMACMDI From this point the chaining interrupt indicates each time the channel requires new transfer in formation The cycle continues as long as the chaining buffer transfer mode is enabled and new transfer information is written to the channel New transfer information must be written to the channel before the channel s current buffer transfer completes DMA Chaining Expanded Addr 019 DMACHR ISA Addr write only Reset State 00H 7 0 CE 0 CS Bit Bit Number Mnemonic Function 7 3 Reserved for compatibility with future devices write zeros to these bits 2 CE Chaining Enable 0 Disables the chaining buffer transfer mode for the channel specified by bit 0 1 Enables the chaining buffer transfer mode for the channel specified by bit 0 1 0 Must be 0 for correct operation 0 CS Channel Select 0 The selection for bit 2 affects channel 0 1 The selection for bit 2 affects channel 1 Figure 12 32 DMA Chaining Register DMACHR 12 47 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL In 12
509. nter 0 1 The actions specified by bits 5 and 4 affect counter 0 0 Reserved for compatibility with future devices write zero to this bit Figure 10 29 Timer Control Register TMRCON Read back Format 10 30 intel TIMER COUNTER UNIT The read back command can latch the count and status of multiple counters This single com mand is functionally equivalent to several counter latch commands one for each counter latched Each counter s latched count and status is held until itis read or until you reconfigure the counter A counter s latched count or status is automatically unlatched when read but other counters latched values remain latched until they are read After latching a counter s status and count with a read back command reading TMRn accesses its status format Figure 10 30 Reading TMRn again accesses its read format When both the count and status of a counter are latched the first read of TMRnz indicates the counter s status and the next one or two reads depending on the counter s read selection indicate the counter s count Subsequent reads return unlatched count values When only the count of a counter is latched then the first one or two reads of return the counter s count When the counter is programmed for the two byte read selection you must read two bytes 10 31 Intel386 EX EMBEDDED PROCESSOR USER S MANUAL intel
510. nternal READ Ys generation is disabled for that region and the Chip select Unit is programmed to insert wait states the READY signal is ignored not sampled by the processor until the programmed number of wait states are inserted into the cycle At the falling edge of PH2 in every T2 state after the wait states if any are programmed in the Chip select Unit have expired READY is sampled If READ Y is active the processor reads the input data on the data bus and deactivates RD If READY is high wait states are added additional T2 states for nonpipelined cycles until READY is sampled low READY is sampled at the end of each T2 state at the falling edge of PH2 Once READY is sampled low the processor reads the input data deactivates RD and terminates the read cycle If a new bus cycle is pending it begins on the next T state BUS INTERFACE UNIT o o e o 0 aage S 2 e E 8 Sgt 956 6296 ZE cu 9 5 Lr CLK2 CLKOUT Valid1 BHE BLE A25 1 M lO D C REFRESH W R READY LBA BS8 LOCK A2487 03 Figure 6 5 Nonpipelined Address Read Cycles 6 15 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 6 3 2 Write Cycle Write cycles are of two types Pipelined Pipelined write cycles are described in Pipelined Cycle on page 6 19 Nonpipelined Figure 6 6 s
511. nterrupt 9 31 Timer Counter Unit Signal Connections 2 10 2 Mode 0 Basic 10 7 Mode 0 Disabling the nennen nennen nene 10 7 Mode 0 Writing a New em eme 10 8 Mode 1 Basic Operation LR 10 9 Mode 1 Retriggering the 10 9 xvii Intel386 EX MICROPROCESSOR USER S MANUAL intel Figure 10 7 10 8 10 9 10 10 10 11 10 12 10 13 10 14 10 15 10 16 10 17 10 18 10 19 10 20 10 21 10 22 10 23 10 24 10 25 10 26 10 27 10 28 10 29 10 30 11 1 11 2 11 3 11 4 11 5 11 6 11 7 11 8 11 9 11 10 11 11 11 12 11 13 11 14 11 15 11 16 11 17 11 18 11 19 11 20 xviii FIGURES Page Mode 1 Writing a New 10 10 Mode 2 Basic Operaltiol n orasi trente po vibe rebas 10 11 Mode 2 Disabling the Count em ee emere 10 11 Mode 2 Writing a New 10 12 Mode Basic Operation Even 10 13 Mode Basic Operation Odd Count senem 10 14 Mode Disabling the 10 14 Mode Writing a New Count With a 10 15 Mode Writing New Count Without a
512. nterrupt pins the pins that connect to the master 82C59A only This chapter describes the interrupt control unit and is organized as follows Overview see below CU operation page 9 4 Register Definitions page 9 15 Design Considerations page 9 29 Programming Considerations page 9 32 9 1 OVERVIEW The ICU consists of two 82C59As configured as master and slave Each 82C59A has eight inter rupt request IR signals The master has seven interrupt sources and a slave 82C59A connected to its IR signals The slave has nine interrupt sources connected to its IR signals two sources are multiplexed into IR1 The interrupts can be globally or individually enabled or disabled The master can receive multiple interrupt requests at once It can also receive a request while the core is already processing another interrupt The master uses a programmable priority structure that determines The order in which to process multiple interrupt requests Which requests can interrupt the processing of other requests When the master receives an interrupt request it checks to see that the interrupt is enabled and determines its priority If the interrupt is enabled and has sufficient priority the master sends the request to the core This causes the core to initiate an internal interrupt acknowledge cycle 9 1 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel The slave 82C59A is cascaded from or connected to the maste
513. nterrupt signals IRQ10 IRQ11 and IRQ15 found on an ISA bus are not directly available for external interrupt connections in systems based on an Intel386 EX processor If an application intends to use these IRQn signals then they can be rerouted to other IRQ signals available in an Intel386 EX processor architecture and the respective interrupt handler routines assigned accord ingly B 1 4 SIO Units In the modem control register MCR the OUT1 register bit is used only in loopback tests The OUT bit in the MCR is used as an SIO interrupt enable control signal This allows two additional UARTS to be added externally as COM3 and COM4 The SIO units COMI and COM2 are connected to the equivalent of a PC s local bus not the ISA bus However this does not affect the compatibility with DOS application software in any form B 1 5 CPU only Reset The RESET pin on the Intel386 EX processor can be considered to function as a system reset function because all of the on chip peripheral units as well as the CPU core are initialized to a known start up state There is no separate reset pin that goes only to the CPU Some CPU only reset modes such as a keyboard controller generated CPU only reset will not function as expect ed A CPU only reset can be implemented by routing the reset signal to either the NMI or SMI sig nal and the appropriate handler code could then generate a corresponding CPU Only Reset func tion by setting bit 0 of the P
514. ntinues to be asserted If the system designer wants to take advantage of existing device drivers that le verage interrupts the memory controller must take this into account M SMM Intr 1 SMM DH Application Handler Service Handler Application SMI Latency 4 gt SMI State i State Restore 1 Save SMM Handler RSM SMIACT lt aM is Blocked A2505 02 Figure 7 6 Interrupted SMI Service 7 3 3 2 HALT During SMM Handler The system designer may wish to place the system into a HALT condition while in SMM The CPU allows this condition to occur however unlike a HALT while in normal mode the CPU in ternally blocks INTR and NMI from being recognized until after the RSM instruction is executed When a HALT needs to be breakable in SMM the SMM handler must enable INTR and NMI before a HALT instruction execution NMI is enabled after the completion of the first interrupt service routine within the SMM handler After the SMM handler has enabled INTR and NMI the CPU exits the HALT state and returns to the SMM handler when INTR or NMI occurs See Figure 7 7 for details Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel SMI 1 82 43 4 INTR or NMI State SMM Enable HALT Halted Save Handler INTR amp NMI State 1 Interrupt Handler Figure 7 7 HALT During SMM Handler A2507 01 7 3 3 3 Idle Mode and Powe
515. o DREQ1 001 SIO channel 1 s receive buffer full signal RBFDMA1 connected to DREQ1 010 SIO channel 0 s transmit buffer empty signal TXEDMAO to DREQ1 011 SSIO receive holding buffer full signal SSRBF to DREQ1 100 TCU counter 2 s output signal OUT2 to DREQ1 101 SIO channel 0 s receive buffer full signal RBFDMAO to DREQ1 110 SIO channel 1 s transmit buffer empty signal TXEDMA1 to DREQ1 111 5510 transmit holding buffer empty signal SSTBE to DREQ1 3 0 Enables DACKO at chip pin 1 Disables DACKO at chip 2 0 000 DRQ O pin external peripheral connected to DREQO 001 SIO channel 0 s receive buffer full signal RBFDMAO connected to DREQO 010 SIO channel 1 s transmit buffer empty signal TXEDMA1 connected to DREQO 011 SSIO transmit holding buffer empty signal THBE connected to DREQO 100 TCU counter 1 s output signal OUT1 connected to DREQO 101 SIO channel 1 s receive buffer full signal RBFDMA1 connected to DREQO 110 SIO channel 0 transmit buffer empty signal connected to DREQO 111 2 SSIO receive holding buffer full signal RHBF connected to DREQO Table 5 10 DMACFG Register Design Worksheet 5 35 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Bit 4 TMRCFG Value 7 0 All clock inputs enabled 1 CLK2 CLK1 CLKO
516. oaded DU A The process is repeated from step 3 10 12 intel TIMER COUNTER UNIT Control _ Werd 16a une Writes to Counter n CLKINN OUTn Count A2314 01 Figure 10 11 Mode 3 Basic Operation Even Count Odd count basic operation 1 Aftera control word write OUTn is driven high 2 Onthe CLKINz pulse following a gate trigger or when the count rolls over count minus one is loaded 3 On each succeeding CLKINn pulse the count is decremented by two 4 When the count rolls over OUTn is driven low and the count minus one is loaded This causes to stay high for one more CLKINn pulse than it stays low 5 On each succeeding CLKINn pulse the count is decremented by two 6 After the count reaches terminal count OUTn is driven high and the count minus one is loaded 7 process is repeated from step 3 10 13 Intel386 EX EMBEDDED PROCESSOR USER S MANUAL intel Control Word 16H Count 5 Writes to 1 1 1 1 1 1 1 1 1 1 1 1 1 Counter n i i 1 1 1 1 1 1 CLKINn f D D 1 1 1 1 1 count 2 2 2 0002 A2400 01 Figure 10 12 Mode 3 Basic Operation Odd Count NOTE For an even count of N OUT remains high for N 2 counts and low for N 2 counts provided GATEn r
517. od performance it is the responsibility of the SMI generation circuitry to man age multiple SME assertions 7 3 8 SMRAM Programming 7 3 4 1 Chip select Unit Support for SMRAM The internal chip select unit CSU has been extended to support the SMRAM by using bit 10 in each Low Address CASMM and Low Mask register CMSMM The CSU acts on these bits 7 12 intel SYSTEM MANAGEMENT MODE exactly as if they represented another address line The following options are supported by the chip select unit CASMM CMSMM Chip select active 0 0 During normal mode only 1 0 During SMM only X 1 During normal mode or SMM To see how this extension of the CSU supports the SMRAM requirements consider an embedded system which has 1 Mbyte of 16 bit wide EPROM in the region 03F00000H to 03FFFFFFH and 1 Mbyte of 16 bit wide RAM in the region 00000000H to 000FFFFFH A single 32 Kbyte RAM in the region 00038000H to 0003FFFFH is added to support SMM The chip selects for this sys tem during normal operation would be programmed as follows REGION CA25 11 CM25 11 CASMM CMSMM BS16 EPROM 11 1111 0000 0000 0 00 0000 1111 1111 1 0 0 1 RAM 00 0000 0000 0000 0 00 0000 1111 1111 1 0 0 1 SMRAM 00 0000 0011 1000 0 00 0000 0000 0111 1 1 0 0 Each row the above table represents a region of memory and its associated chip select logic During initialization these same chip selects could be programm
518. ode The interrupt occurs again when the first buffer transfer expires and the Current Registers are loaded from the Base Registers The cycle continues until the Chaining Process is disabled or the host fails to respond to DMAINT before the Current Buffer expires Exiting the Chaining Process can be done by resetting the Chaining Mode Register If an interrupt is pending for the channel when the Chaining Register is reset the interrupt request is removed The Chaining Process can be temporarily disabled by setting the channel s mask bit in the Mask Register The interrupt service routine for DMAINT has the responsibility of reloading the Base Register as necessary It should check the status of the channel to determine the cause of the channel ex piration etc It should also have access to operating system information regarding the channel if any exists The DMAINT service routine should be capable of determining whether the chain should be continued or terminated and act on that information NOTE The chaining buffer transfer mode is not useful with block transfer mode since the CPU must be able to get control of the bus before the end of the block in order to reprogram the new values into the DMA registers Since block transfer mode locks out any other bus requests except refresh the processor cannot regain control of the bus until the entire block has been transferred 12 2 7 Data transfer Modes There are three data transfer modes
519. ode For device level in circuit emulation you assert the pin to enter ONCE mode This method can interfere with the test logic unit s parallel functions although it does not affect the shifting functions or the TDO output 18 14 intel SIGNAL DESCRIPTIONS APPENDIX A SIGNAL DESCRIPTIONS This appendix provides reference information for the pins and signals of the device including the states of certain pins during reset idle powerdown and hold The information is presented in four tables Table 1 defines the abbreviations used in Table A 2 to describe the signals Table 2 describes each signal Table 3 defines the abbreviations used in Table A 4 to describe the pin states Table 4 lists the states of output and bidirectional pins after reset and during idle mode powerdown and hold Table A 1 Signal Description Abbreviations Abbreviation Definition signal is active low not applicable or none standard TTL input standard CMOS output OD open drain output VO bidirectional input and output ST Schmitt trigger input P power pin ground pin A 1 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Table 2 is an alphabetical list of the signals available at the device pins The Multiplexed With column lists other signals that share a pin with the signal listed in the Signal column Table A 2 Description of Signals Available
520. odings of these fields are defined in the next several section E 2 2 1 Encoding of Operand Length w Field For any given instruction performing a data operation the instruction is executing as a 32 bit op eration or a 16 bit operation Within the constraints of the operation size the w field encodes the operand size as either one byte or the full operation size as shown in Table E 3 Table E 3 Encoding of Operand Length w Field Operand Size During 16 bit Operand Size During 32 bit new Data Operations Data Operations 0 8 bits 8 bits 1 16 bits 32 bits 2 2 2 Encoding of the General Register reg Field The general register is specified by the reg field which may appear in the primary opcode bytes or as the reg field of the mod r m byte or as the r m field of the mod r m byte Table E 4 Encoding of reg Field When w Field is not Present in Instruction reg Field Register Selected During Register Selected During 16 bit Data Operations 32 bit Data Operations 000 AX EAX 001 CX ECX 010 DX EDX 011 BX EBX 100 SP ESP 101 BP EBP 110 SI ESI 111 DI EDI E 24 intel Table E 5 Encoding of reg Field When w Field is Present in Instruction INSTRUCTION SET SUMMARY Register Specified by reg Field During 16 bit Data Operations Function of w Field reg when w 0 when w 1 000 AL AX 001 CL CX 010 DL DX 011 BL BX
521. of a buffer trans fer With synchronous sampling the channel samples DRQn at the end of the last state of every data transfer With asynchronous sampling the channel samples DRQn at the beginning of every state then waits until the end of the state to act on the input See Figure 12 13 The DRQn sam pling is programmed in the DMACMD2 register Figure 12 24 CLKOUT ADS READY DRQn Async DRQn Sync x DMA Cycle Cycle 2481 02 Figure 12 13 Buffer Transfer Suspended by the Deactivation of DRQn The demand data transfer mode is compatible with all of the buffer transfer modes The follow ing flowcharts show the transfer process flow for a channel programmed for the demand data transfer mode with each buffer transfer mode single Figure 12 14 autoinitialize Figure 12 15 and chaining Figure 12 16 12 21 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel After initialization the DMA channel is programmed with the requester and target addresses and a byte count DREQn active Yes DMA gains bus control DMA transfers one byte or word of data and decrements the byte count Byte count FFFFFFH or active DMA channel relinquishes bus control DREQn active DMA channel relinquishes bus control Buffer transfer is complete so channel becomes idle A2338 02 Figure 12 14 Demand Data transfer Mode with Single Buff
522. on link with asynchronous serial channel SIO1 SSIO Transmit Clock synchronizes data being sent by the synchronous serial port RI14 Ring Indicator SIO1 indicates that the modem or data set has received a telephone SSIORX ringing signal SSIO Receive Serial Data accepts serial data most significant bit first being sent to the synchronous serial port TMRCLKO Timer CounterO Clock Input can serve as an external clock input for timer counterO INT4 The timer counters can also be clocked internally Interrupt 4 is an undedicated external interrupt TMRGATEO Timer Counter0 Gate Input can control timer counter0 s counting enable disable or INT5 trigger depending on the programmed mode Interrupt 5 is an undedicated external interrupt TMRCLK1 Timer Counter1 Clock Input can serve as an external clock input for timer counter1 INT6 The timer counters can also be clocked internally Interrupt 6 is an undedicated external interrupt TMRGATE1 Timer Counter1 Gate Input can control timer counter1 s counting enable disable or INT7 trigger depending on the programmed mode Interrupt 7 is an undedicated external interrupt 5 23 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Pin Configuration PINCFG read write 7 Expanded Addr F826H ISA Addr Reset State 00H PM6 PM5 PM4 PM2 PM1 PMO Bit Bit Number Mnemonic Function 7 Reserved This bit is
523. on opcode is clocked serially through the TDI pin into the four bit instruction register Figure 18 3 The instruction determines which data register is affected Table 18 4 lists the in structions with their binary opcodes descriptions and associated registers Instruction Register Reset State IR Using TRST 02H 3 0 INST3 INST2 INST1 INSTO Bit Bit L Number Mnemonic Function 3 0 INST3 0 Instruction opcode At reset using TRST or after 5 cycles with TMS held low this field is loaded with 0010 the opcode for the IDCODE instruction Instructions are shifted into this field serially through the TDI pin Table 18 4 lists the valid instruction opcodes Figure 18 3 Instruction Register IR Table 18 4 Test logic Unit Instructions PEP Affected Mnemonic Opcodet Description Register 1111 Bypass on chip system logic mandatory instruction BYPASS T BYPASS Used for those components that are not being tested 0000 Off chip circuitry test mandatory instruction EXTEST DOSE d BOUND Used for testing device interconnections on a board 0001 Sample pins preload data mandatory instruction SAMPRE Used for controlling preload or observing sample the signals at BOUND device pins This test has no effect on system operation 0010 ID code test optional instruction IDCODE IDCODE Used to identify devices on a board 100
524. one using the following code smsw Store Machine Status Word into AX or ax 2 Set MP bit and ax Offfbh Clear EM bit lmsw ax Load AX into Machine Status Word 6 40 intel BUS INTERFACE UNIT Also bit 5 in the PINCFG register Figure 5 15 on page 5 24 must be cleared to connect the coprocessor related signals of the core to the package pins Below is an example of a simple routine that can be executed using the math coprocessor fninit Initialize Math Coprocessor fldpi Load Push on to the 387 stack Pi fldl Load Push on to the 387 stack 1 fadd Add the two values i e Pi 1 fist word ptr di Convert to integer and Store at 77 location pointed to by DS DI 6 6 2 SRAM FLASH Interface SRAM and FLASH devices can be connected directly to the Intel386 EX processor as shown in Figure 6 16 Separate CSn RD and WR strobes enable a glueless interface The WR sig nal when used with an EARLY READYTP described in Write Cycle on page 6 16 guaran tees the WE Inactive to Address Invalid time of most SRAM and FLASH devices Intel386 EX SRAM or FLASH Embedded Adress Processor A2853 02 Figure 6 16 Intel386 EX Processor to SRAM FLASH Interface 6 41 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 6 6 3 PSRAM Interface Pseudo SRAM PSRAM devices can be easily interfaced Figure 6 17 to the Intel386 EX pro cessor
525. onic Function 7 D1MSK DMA Acknowledge 1 Mask 0 channel 1 s acknowledge DMAACK1 signal is not masked 1 Masks DMA channel 1 s acknowledge DMAACK1 signal Useful when channel 1 s request DREQ1 input is connected to an internal peripheral 6 4 D1REQ2 0 DMA Channel 1 Request Connection Connects one of the eight possible hardware sources to channel 1 s request input DREQ1 000 DRQ1 pin external peripheral 001 SIO channel 1 s receive buffer full signal RBFDMA1 010 SIO channel 0 s transmit buffer empty signal 011 SSIO receive holding buffer full signal SSRBF 100 TCU counter 2 s output signal OUT2 101 SIO channel 0 s receive buffer full signal RBFDMAO 110 SIO channel 1 s transmit buffer empty signal TXEDMA1 111 SSIO transmit holding buffer empty signal SSTBE DOMSK DMA Acknowledge 0 Mask 0 DMA channel 0 acknowledge DMAACKO signal is not masked 1 Masks DMA channel 0 s acknowledge DMAACKO signal Useful when channel 0 s request DREQO input is connected to an internal peripheral 2 0 DOREQ2 0 DMA Channel 0 Request Connection Connects one of the eight possible hardware sources to channel 0 s request input DREQO 000 DRQO pin external peripheral 001 SIO channel 0 s receive buffer full signal RBFDMAO 010 SIO channel 1 s transmit buffer empty signal TXEDMA1 011 SSIO transmit holdin
526. ontroller has features that are unavailable on an 8237A but it can be configured to operate in an 8237A compatible mode This chapter is organized as follows Overview see below DMA Operation page 12 5 Register Definitions page 12 28 Design Considerations page 12 50 Programming Considerations page 12 50 12 1 OVERVIEW Figure 12 1 shows a block diagram of the DMA unit The DMA channels are independently con figurable Each channel contains a request input DREQz and an acknowledge output DMAACKn An external peripheral connected to the DRQn pin or one of the internal pe ripherals asynchronous serial I O synchronous serial I O or timer control unit can request DMA service The DMA configuration register is used to select one of the possible sources In addition to these hardware request sources each channel contains a software request register that can be used to initiate software requests The channels share an end of process signal This signal functions as either an input or an open drain output either terminates a transfer as an input or signals that a transfer is completed as an output 12 1 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL DMACFG 2 0 RBFDMAO 100 8101 76501 SSTBE 5510 OUT1 TCU RBFDMAt1 5101 TXEDMAO SIO0 SSRBF SSIO DMACFG 3 PINCFG 4 DMBAGISUS From DMACFG 6 4
527. or has three 8 bit bidirectional I O ports all of which are functionally identical Figure 16 1 Each port has three control registers and a status register three ports share pins with internal peripherals see Table 16 1 If your design does not re quire a pin s peripheral function you can configure that pin for use as an I O port For example if you don t need serial channel 0 you can use P1 4 P1 0 and P2 7 P2 5 as I O ports and still allow the bus interface unit to use P1 7 P1 5 and the chip select unit to use P2 4 P2 0 Each pin can operate either in I O mode or in peripheral mode In I O mode a pin has three pos sible configurations high impedance input open drain output requires an external pull up resistor complementary output In I O mode register bits control the direction input or output of each pin and the value of each output pin In peripheral mode the internal peripheral controls the operation input or output of the pin Table 16 1 lists the port pins with their reset status multiplexed peripheral functions di rection input or output and associated internal peripheral 16 1 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel PnCFG x Internal Peripherals PnDIR x PnLTC x PnPIN x 5 5 Pnx 2393 01 Figure 16 1 1 0 Port Block Diagram 16 1 1 Port Functionality The function of a bi directional port
528. or pull down tran sistors The clock generation logic generates a synchronous internal RESET signal for the internal pe ripherals If you need a synchronous RESET signal for other system components you can use a simple circuit such as the one shown in Figure 8 8 to generate it Otherwise the CPU does not need a synchronous reset Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Synchronous Asynch RESET synchronous RES Reset Signal to chip and dy d other system logic A2465 02 Figure 8 8 Reset Synchronization Circuit 8 4 2 Considerations 8 4 2 1 Built in Self Test The Inte1386 EX processor supports the Intel386 SX processor built in self test BIST mode for testing core functions To initiate the self test follow these steps 1 Hold the RESET pin high for a minimum of 80 CLK2 cycles 2 Transition the RESET pin from high to low while keeping the BUSY pin asserted The BUS Yit input should be asserted at least eight CLK2 cycles before the falling edge of RESET and must be kept asserted for at least eight CLK2 cycles after the falling edge of RESET Once BIST has been initiated it takes approximately 22 processor clock cycles to complete At the completion of the BIST the processor performs an internal reset and begins normal operation 8 4 2 2 JTAG Reset The processor supports an IEEE 1149 1 compliant JTAG boundary scan The JTAG unit has its own clock and RESET signals in
529. ord 4 4 em 9 24 9 3 7 Operation Command Word 1 9 25 9 3 8 Operation Command Word 2 9 26 9 3 9 Operation Command Word 3 OCWS3 9 27 9 3 10 Interrupt Request Register IRR seem 9 28 9 3 11 In Service Register ISR essen enne nnne 9 28 9 2212 Poll Stat s Byte eee eere REED A Ee 9 28 9 4 DESIGN CONSIDERATIONS esee eene 9 29 9 4 1 Interrupt Acknowledge sse 9 29 9 4 2 interrupt Detection c e e e e te ein eid 9 29 9 4 3 opurious Interr pts x o Fr t noe ER d ree ate 9 30 9 4 4 Cascading Interrupt Controllers 2 emm 9 30 9 5 PROGRAMMING CONSIDERATIONS seem eem 9 92 9 5 1 Interrupt Control Unit Code Examples 2 9 32 CHAPTER 10 TIMER COUNTER UNIT 10 1 1 TCU Signals and Registers ai apost ipte adsis t e yer ote 10 3 10 2 TCU OPERATION AA Ad ede E AERA es 1055 10 2 1 Mode0 Interrupt o on n Terminal Count 0 6 10 2 2 Mode 1 Hardware Retriggerable One shot Jw Bele a neon A 10 8 10 2 3 Mode 2 Rate Generator esses eee 10 10 10 2 4 Mode 3 Square Wave ste 10 2 5 Mode 4 Software triggered Strobe Dian Ghat EM 10 16 10 2 6 Mode 5 Hardware triggered Strobe sees 10 18 10 3 REGISTER DEFINITIONS 2
530. ort 2 0 P2CFG 1 as 51 Es 2 1 To From I O Port 2 0 1 P2CFG 2 CS24 P2 2 To From I O Port 2 0 1 P2CFG 3 CS34 P2 3 To From I O Port 2 0 P2CFG 4 1 FERES 54 eg To From I O Port 2 0 1 PINCFG 4 CS54 DACKO DACKO DMA 0 1 PINCFG 6 CS6 REFRESH REFRESH RCU 0 Clock and Power Management Unit 1 P3CFG 6 PWRDOWN Lt 0 To From I O Port 3 0 A3380 01 Figure 5 12 Configuration of Chip select Unit and Clock and Power Management Unit 5 20 intel DEVICE CONFIGURATION 5 2 7 Core Configuration Three coprocessor signals ERROR PEREQ and BUSY in Figure 5 13 can be routed to the core as determined by bit 5 of the PINCFG register see Figure 5 15 Due to signal multiplexing at the pins the coprocessor and Timer counter2 cannot be used simultaneously PINCFG 5 Core PINCFG 5 ERROR ERROR From TCU gt TMROUT2 11 PEREQ To TCU e TMRCLK2 55 1 BUsY amp TMRGATE2 To ae Voc RESET Timing PORT92 0 Generation From Chip RESET Pin PORT92 1 To Chip select Unit and A20 Pin P1CFG 5 1 zZ C LOCK To From I O Port 1 1 5 t Alternate pin signals in parentheses A2520 02 Figure 5 13 Core Configuration 5 21 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Setting bit 0 in the PORT92 register see Figure 5 14 resets the core without resettin
531. ort SMM 14 10 intel CHIP SELECT UNIT 14 3 3 Bus Cycle Length Control Each chip select channel controls how bus cycles to its address block terminate Each channel can generate up to 31 wait states and then unconditionally terminate or wait for an external bus ready signal to terminate If the channel is programmed for wait states and to sample external READY the external READY is ignored until the programmed number of wait states has been inserted into the cycle If greater than 31 wait states are required ready must be generated externally and the external READY option must be selected NOTE When a chip select region overlaps on chip peripheral addresses the on chip peripheral always generates READ Y and overrides the channel s configuration 14 3 4 Bus Size Control The processor assumes that the currently addressed device requires a 16 bit data bus unless the bus size control pin BS8 is asserted When asserted BS8 tells the processor that the addressed device requires an 8 bit data bus You can program a chip select channel specifically for 8 bit de vices This causes the CSU to assert BS8 automatically each time it activates the channel 14 3 5 Overlapping Regions You can configure CSU channels to have overlapping address blocks When channels with over lapping address blocks have different bus cycle length and bus size configurations the CSU must adjust these parameters Figure 14 3 shows how the CSU adjusts the
532. ortAddr Set Port base based on serial port used TransmitPortAddr Unit TBR1 TBRO StatusPortAddr Unit LSR1 LSRO for str 0 str Wait until buffer is empty while GetEXRegByte StatusPortAddr amp SIO TX BUF EMPTY Write Character SetEXRegByte TransmitPortAddr str SerialWriteStr 11 39 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel RRR KK KKK IKK Kk Ck k Kk Ck Kk Ck AR KK Ck kk kk Kk Ck kk k kk ko ke kk k k k k eek SerialWriteMem Description Is a Polled serial port write function that waits forever or until count characters have been written to the serial port Parameters Unit Unit number of the serial port 0 for SIO port 0 1 for SIO port 1 mem Address of a buffer to be transmitted count Number of characters in buffer to be transmitted Returns None Assumptions REMAPCFG register has Expanded I O space access enabled ESE bit set The processor Port pin are initialized separately Syntax define SIO 0 0 define COUNT 32 char Buffer COUNT SerialWriteMem SIO 0 Buffer COUNT Real Protected Mode No changes required Fe KR RAR IRR A IRR kk Ck KC void SerialWriteMem int Unit const char far mem int count WORD TransmitPortAddr WORD StatusPortAddr irt d Set Port base based on serial port used TransmitPortAddr Unit TBR1 TBRO StatusPortAddr Unit LSR1
533. ot below or equal above register memory 0000 0010111 mod 00 0 r m 4 5 4 5 h SETS set byte on sign register memory 0000 00 000 4000 4 5 4 5 h SETNS set byte on not sign register memory 0000 00 001 mod 00 0 r m 4 5 4 5 h SETP SETPE set byte on parity parity even register memory 0000 00 010 mod 000 r m 4 5 4 5 h SETNP SETPO set byte on not parity parity odd register memory 0000 00 011 mod 0 0 0 r m 4 5 4 5 h SETL SETNGE set byte on less not greater or equal register memory 0000 00 00 mod000r m 4 5 4 5 h SETNL SETGE set byte on not less greater or equal register memory 0000 011 01 mod 00 0 r m 4 5 4 5 h SETLE SETNG set byte on less or equal not greater register memory 0000 100 10 mod000r m 4 5 4 5 h SETNLE SETG set byte on not less or equal greater register memory 0000 100 mod 00 0 4 5 4 5 h ENTER enterproce 11001000 16 bit displacement 8 level L 0 10 10 b h I 14 14 b h L 1 17 8 17 8 n 1 1 LEAVE leave proce 11001001 4 4 b h INTERRUPT INSTRUCTIONS INT Interrupt Type specified 11001101 type 37 b Type 3 11001100 33 b aon If OF 1 35 b e If OF 0 3 3 b e E 15 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Table E 1 Instruction Set Summary Sheet 15 of 19 intel Clock Count Notes Real Pro Real Pro Ad tected Ad tected Instruction Format dress Virtual
534. ot equal the receiver sets the Parity Error bit in LSR and causes an error interrupt if line status interrupts are enabled For example if forced parity is enabled and EPS is 0 the receiver expects the bit received at the parity bit location to be 1 If it is not the parity error bit is set By forcing the bit value at the parity bit location rather than calculating a parity value a system with a master transmitter and multiple receivers can identify some transmitted characters as receiver addresses and the rest of the char acters as data If PEN 0 the SP bit is ignored Each SIO channel transmitter contains a transmit shift register a transmit buffer and a transmit data pin TXDn Data to be transmitted is written to the transmit buffer The transmitter then transfers the data to the transmit shift register The transmitter shifts the data along with asynchro nous communication bits start stop and parity out via the TXDn pin The TXDO and TXDI pins are multiplexed with other functions The pin configuration registers PINCFG and P2CFG determine whether a TXDn signal or an alternate function is connected to the package pin intel ASYNCHRONOUS SERIAL UNIT Baud rate Clock SIOn Transmit Shift Register SIOn Transmit Buffer TXDn pin mux Transmit Buffer Empty To ICU and DMA A2326 01 Figure 11 3 SIOn Transmitter The transmitter contains a transmitter empty TE flag and a transmit bu
535. ote that using the SSIO signals precludes the use of four of the SIO1 modem signals SSIO SIOCFG 2 PSCLK BCLKIN SERCLK SSTBE To DMA SSRBF To DMA SSIOINT To ICU Receive Data SSIORX To SIO1 RI1 0 Transmit Data SSIOTX From 5101 39 RTS1 Transmit Clock STXCLK To SIO1 DSR1 0 PINCFG 1 Receive Clock JSRXCLK From SSIO1 39 DTR1 Alternate pin signals are in parentheses A2518 02 Figure 5 11 SSIO Unit Configuration 5 18 intel DEVICE CONFIGURATION 5 2 6 Chip select Unit and Clock and Power Management Unit Configuration Figure 5 12 shows the multiplexing of signals of the Chip select Unit and the Clock and Power Management Unit The Chip select signals CS6 and CS5 are multiplexed with the REFRESH signal from the Refresh Control Unit and the DACKO signal from the DMA Unit respectively Bits 6 and 4 in the PINCFG register see Figure 5 15 control these multiplexers CS3 CS2 CS1 and CSO are multiplexed with I O Port 2 signals P2 3 P2 2 P2 1 and P2 0 respectively Bits 4 0 in the P2CFG register see Figure 5 17 control these multiplexers The PWRDOWN output signal of the Clock and Power Management Unit is multiplexed with I O Port 3 signal P3 6 Bit 6 in the P3CFG register see Figure 5 18 controls this multiplexer 5 19 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel P2CFG 0 1 CSO P2 0 To From I O P
536. ow to avoid this problem The transmitter also has a transmit holding buffer empty signal SSTBE This signal can be con nected to the interrupt control and DMA units This allows you to use either an interrupt service routine or a DMA transfer to load new data in the transmit holding buffer Figures 13 6 and 13 7 are simple descriptions of the SSIO transmitter state machine when Au totransmit mode is enabled or disabled oom 21 gt HOLD Initialize SSIO Data Written Into SSIOTBUF Clears THBE Data In Buffer Moved To Shift Register THBE Set THBE 1 A3400 01 Figure 13 6 SSIO Transmitter with Autotransmit Mode Enabled 13 7 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Ago HOLD Initialize SSIO Data Written Into SSIOTBUF Clears THBE Data In Buffer TUES Moved To Shift Register THBE Set A3399 01 Figure 13 7 SSIO Transmitter with Autotransmit Mode Disabled The SSIO Unit can be operated either by using a polling method or through interrupts Figure 13 8 shows a basic flowchart for using the polling method to transmit data through the SSIO Figure 13 9 shows a basic flowchart for the Interrupt Service Routine necessary when using interrupts to transmit data through the SSIO If interrupts are used follow the below sequence for initialization 1 Initialize the SSIO N Initialize the interr
537. pecific Peripherals Name Description System The Intel386 EX processor provides a mechanism for system management with a Management combination of hardware and CPU microcode enhancements An externally generated Mode SMM system management interrupt SMI allows the execution of system wide routines that are independent and transparent to the operating system The system management mode SMM architectural extensions to the Intel386 CPU are described in Chapter 7 SYSTEM MANAGEMENT MODE Clock and An external clock source provides the input frequency The clock and power management Power unit generates separate internal clock signals for core and peripherals half the input Management frequency divides the internal clock by two for baud clock inputs to the SIO and SSIO and Unit divides the internal clock by a programmable divisor to provide a prescaled clock signal various frequencies for the TCU and SSIO Power management provides idle and powerdown modes idle stops the CPU clock but leaves the peripheral clocks running powerdown stops both CPU and peripheral clocks An external clockout signal is also provided Refer to Chapter 8 CLOCK AND POWER MANAGEMENT UNIT Synchronous Provides simultaneous bidirectional high speed serial I O Consists of a transmit channel Serial I O receive channel and a baud rate generator Built in protocols are not included because SSIO unit these can b
538. pecifier 3 mod r m Address Mode Specifier Effective Address can be a General Register 2 for mod 3 for r m ss Scale Factor for Scaled Index Address Mode 2 index General Register to be used as Index Register 3 base General Register to be used as Base Register 3 sreg2 Segment Register Specifier for CS SS DS ES 2 sreg3 Segment Register Specifier for CS SS DS ES FS GS 3 tttn For Conditional Instructions specifies a condition asserted or a condition negated 4 NOTE Figure E 1 shows encoding of individual instructions E 2 1 32 bit Extensions of the Instruction Set With the Intel386 EX processor the 8086 80 186 80286 instruction set is extended in two orthog onal directions 32 bit forms of all 16 bit instructions are added to support the 32 bit data types and 32 bit addressing modes are made available for all instructions referencing memory This or thogonal instruction set extension is accomplished having a Default D bit in the code segment descriptor and by having 2 prefixes to the instruction set The instruction defaults to operations of 16 bits or 32 bits depending on the setting of the D bit in the code segment descriptor which gives the default length either 32 bites or 16 bits for both operands and effective addresses when executing that code segment In the Real Address Mode or Virtual 8086 Mode no code segment descriptors are used but a D value of 0 is assumed inter nally by the Intel386 EX processor when operating in thos
539. pin The request is recognized and latched It is serviced after HOLD is released e SMI pin The request is recognized and latched It is serviced after HOLD is released 6 5 2 HOLD Signal Latency Because other bus masters may be used in time critical applications the amount of time the bus master must wait for bus access HOLD latency can be a critical design consideration Because a bus cycle must be terminated before HLDA can go active the maximum possible latency occurs when a bus cycle instruction is being executed or a DMA block mode transfer is in progress Wait states increase latency and HOLD is not recognized between locked bus cycles and interrupt ac knowledge cycles The internal DMA may also contribute to the latency The HOLD latency is dependent on a number of parameters The instruction being executed at the time the HOLD request occurs The number of wait states during various access cycles including the following Memory wait states Code fetch wait states Interrupt acknowledge wait states Refresh wait states The priority of the requester The mode of the DMA Block mode Single cycle mode Demand transfer mode 6 37 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 6 6 DESIGN CONSIDERATIONS Upon reset UCS is configured as a 16 bit chip select signal If the Boot device is only an 8 bit device then BS8 must be asserted whenever UCS is active until the UCS r
540. pin is controlled by the state of the Port Control Latch LTC This is shown in Figure 16 2 16 2 INPUT OUTPUT PORTS From Internal Peripheral Read Port Data latch Write Port Data Latch Read Port Pin State To Internal Peripheral Internal Data Bus F Bus Write Port Direction Read Port Direction From Internal Peripheral Direction Control Write Port Control Read Port Control t Depends on peripheral s inactive state A3266 01 Figure 16 2 Logic Diagram of a Bi directional Port 16 3 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel The output of the Pin Configuration latch selects whether the I O port or peripheral is connected to the pin When the port is programmed to act as a peripheral pin both the data for the pin and the directional control signal for the pin come from the associated integrated periph eral When a bi directional port pin is programmed as an I O port all port parameters are under software control The output of the Port Direction latch PnDIR enables or disables the three state output driver when the pin is programmed as an I O port The three state output driver is enabled by clearing the Port Direction latch The data driven to an output port pin is held in the Port Data latch Setting the Port Direction latch disables the three state output driver making the pin an input The signal present on the pin is routed through a synchron
541. plete signal if regDMAIS amp 0 1 Chaining Interrupt channel 0 if regDMAIS amp 0 2 Chaining Interrupt channel 1 NonSpecificEOI Send End Of Interrupt Signal to Master Slave 12 61 intel 13 SYNCHRONOUS SERIAL I O UNIT 13 SYNCHRONOUS SERIAL I O UNIT The synchronous serial I O SSIO unit provides 16 bit bidirectional serial communications The transmit and receive channels can operate independently that is with different clocks to provide full duplex communications Either channel can originate the clocking signal or receive an exter nally generated clocking signal This chapter is organized as follows Overview see below SSIO Operation page 13 5 Register Definitions page 13 16 Design Considerations page 13 25 Programming Considerations page 13 26 13 1 OVERVIEW The SSIO unit contains a baud rate generator transmitter and receiver The baud rate generator has two possible internal clock sources PSCLK or SERCLK The transmitter and receiver are double buffered They contain 16 bit holding buffers and 16 bit shift registers Data to be trans mitted is written to the transmit holding buffer The buffer s contents are transferred to the trans mit shift register and shifted out via the serial data transmit pin SSIOTX Data received is shifted in via the serial data receive pin SSIORX Once 16 bits have been received the contents of the recei
542. pro cessor focusing on register organization from an address architecture viewpoint The chapters that cover the individual peripherals describe the registers in detail This chapter is organized as follows Overview see below Address Space for PC AT Systems page 4 2 Expanded I O Address Space page 4 3 Organization of Peripheral Registers page 4 5 Address Decoding Techniques page 4 6 Addressing Modes page 4 9 Peripheral Register Addresses page 4 15 4 1 OVERVIEW The Inte1386 EX processor has register resources in the following categories ntel386 processor core architecture registers General purpose registers Segment registers Instruction pointer and flags Control registers System address registers protected mode Debug registers Test registers ntel386 EX processor peripheral registers Configuration space control registers Interrupt control unit registers Timer counter unit registers DMA unit registers 8237A compatible and enhanced function registers Asynchronous serial I O SIO registers Clock generation selector registers 4 1 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Power management control registers Chip select unit control registers Refresh control unit registers Watchdog timer control registers Synchronous serial I O control registers Parallel I O port control registers
543. quest The REFRESH status pin indicates that the Refresh Control Unit has gained bus control and that a valid refresh cycle is being executed After receiving a bus 12 9 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel control request the bus arbiter services these requests by issuing an internal hold signal request ing control of the bus from the core The core returns an internal hold acknowledge signal to the arbiter when bus ownership is granted The arbiter then issues an acknowledge signal to the re questing device Refresh requests always have the highest priority while the priority structure of the other three requests is configurable By default channel 0 requests have the next highest priority fol lowed by DMA channel 1 requests and external bus master requests There are two methods for changing the priority of the and external bus requests low priority selection or rotation The priority requests are programmed in the DMACMD2 register see Figure 12 24 The low priority selection method allows you to assign a particular request to the lowest priority level With the rotation method a request is automatically assigned to the lowest priority level after it gains bus control The rotation method allows requesting devices to share the system bus more evenly With both methods the other request priority levels are adjusted in a circular manner see Figure 12 5 Low priority Default Select Rotat
544. r 12 2 10 8237A Compatibility Although the DMA is an enhancement over the 8237A you can configure it to operate in an 8237A compatible mode A list of the features common to the DMA and 8237A and a list of DMA enhancements follow Features common to the DMA and 8237A Data transfer modes single block and demand Buffer transfer modes single and autoinitialize Fly by data transfer bus cycle option Programmed via 8 bit registers Transfers between memory and I O target must be in memory and requester must be external DMA enhancements Chaining buffer transfer mode Two cycle data transfer bus cycle option provides byte assembly and allows memory to memory transfers using only one channel Transfers between any combination of memory and I O Address registers for both the target and the requester addresses can be incremented decremented or left unchanged during a buffer transfer A channel is configured for 8237A compatibility by enabling only the common features and lim iting the byte count and the target address modification capability The 8237A uses 16 bit target address and a 16 bit byte count while the DMA uses a 26 bit target address and a 24 bit byte count Therefore for compatibility the DMA contains an overflow register that allows you to configure the target and byte count so that only the lower 16 bits are modified during buffer trans fers With this configuration the upper byte count bits
545. r s IR2 signal Like the master the slave uses a programmable priority structure When the slave receives an interrupt request it sends the request to the master assuming the request is enabled and has sufficient priority The master sees the slave request as a request on its IR2 line The master then sends the request to the core assuming the request is enabled and has sufficient priority and the core initiates an internal interrupt acknowledge cycle The internal interrupt acknowledge cycle consists of two pulses that are sent to the 82C59A IN TA inputs This cycle causes the 82C59A that received the original interrupt request to put the request s vector number on the bus The master s cascade signals CAS2 0 determine which 82 59 is being acknowledged 1 which 82C59A needs to put the vector number on the bus The core uses its processing mode real or protected and the vector number to find the address of the interrupt service routine The master 82C594 has six device pins INT9 8 INT3 0 connected to it You can cascade addi tional external 82C59A slaves to these pins to increase the number of possible interrupt sources The external interrupt signals INT9 8 are multiplexed with the internal asynchronous serial I O interrupt signals SIOINTO and SIOINTI On the slave 82 59 the external interrupt signal INT6 and the DMA Unit s DMAINT signal can be swapped before connecting to the slave s IRA and IRS inputs see Figure
546. r TMRn Write Format Table 10 5 lists the minimum and maximum initial counts for each mode Table 10 5 Minimum and Maximum Initial Counts Mode Minimum Count Maximum Count 0 1 1 0 2 3 2 0 4 5 1 0 NOTE is equivalent to 216 for binary counting and 104 for BCD counting 10 26 intel TIMER COUNTER UNIT 10 3 4 Reading the Counter To read the counter you can perform a simple read operation or send a latch command to the counter TMRCON contains two formats that allow you to send latch commands to individual counters the counter latch and read back format The counter latch command latches the count ofa specific counter The read back command latches the count and or status of one or more spec ified counters 10 3 4 1 Simple Read To perform a simple read operation in modes 0 2 3 and 4 suspend the counter s operation using the counter s GATEn signal then read the counter s TMR register To read an accurate value you must disable the counter so that the count is not in the process of changing when it is read However in modes 1 and 5 where the counter s operation can not be suspended the counter can still be read But since the counter is running there is a minor inaccuracy in the read value 10 3 4 2 Counter latch Command Use the counter latch format of TMRCON Figure 10 27 to latch the count of a specific counter To issue a counter latch command to a counter write to the TMRCON registe
547. r When the SMM address bit is masked an address match activates the chip select regardless of whether the processor is in SMM 9 1 Reserved for compatibility with future devices write zeros to these bits CSEN Chip select Enable 0 Disables the chip select channel 1 Enables the chip select channel Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL 0 7 DLLn AND DLHn LCRn must be set in order to access the divisor latch registers If DLL DLH 00H baud rate generator ouput frequency 0 stops clock Divisor Latch Low DLLO DLL1 DLLO DLL1 Expanded Addr F4F8H F8F8H read write ISA Addr 03F8H 02 8 Reset State 02H 02H 7 0 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LDO Divisor Latch High DLHO DLH1 DLHO DLH1 Expanded Addr F4F9H F8F9H read write ISA Addr 03F9H 02 Reset State 00H 00H 7 0 UD15 UD14 UD13 UD12 UD11 UD10 UD9 UD8 Bit Bit i Number Mnemonic Funeuon DLLn LD7 0 Lower 8 Divisor and Upper 8 Divisor Bits 7 0 Write the lower 8 divisor bits to and the upper 8 divisor bits to DLHn The baud rate generator output is a function of the baud rate generator input BCLKIN and the 16 bit divisor DLHn UD15 8 7 0 Uo baud rate generator output frequency frequency divisor bit rate shifting rate baud rate generator output frequency 16 NOTE The divisor latc
548. r powerdown mode Mode Setting to Active Returns the Intel386 EX processor to active mode See Appendix C for the included header files include lt conio h gt include 80386ex h include EV386EX h 8K RR A A A A A AAA A AAA k k k AAA AAA AA A Set_Prescale_Value Description This function sets the clock prescale value Parameters Prescale Prescale value Returns Error Codes E_BAD_VECTOR Specified Prescale is invalid E OK Initialized OK No error Assumptions 8 13 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel None Syntax int error WORD psclk 0x02 error Set Prescale Value psclk Real Protected Mode No changes required eK RR AA KK RR AAR Kk Ck AA IRR Kk AIA IRR Kk Ck kk int Set Prescale Value WORD Prescale WORD clkprs 0x0000 clkprs GetEXRegWord CLKPRS clear lowest nine bits of clkprs clkprs clkprs amp Oxfe00 check that prescale value is only 9 bits in length if Prescale Prescale amp 0 01 return E_BADVECTOR _SetEXRegWord CLKPRS clkprs Prescale return E_OK Set_Prescale_Value RR KIRK KK IK RK RRR IRA A IRR IRA IRR IRR IA IR IR k k k k k k k k k kk k k k Enter_Idle_Mode Description This function programs the 386EX for Idle mode This freezes the core clocks while leaving the peripheral clocks toggling Parameters None Returns None Assumptions None
549. r this bit when the target for the channel specified by bit 0 is in memory space 1 Setthis bit when the target for the channel specified by bit 0 is in space 4 RH Requester Address Hold 0 Causes the address to be modified incremented or decremented depending on DMAMOD2 3 1 Causes the requester s address for the channel specified by bit 0 to remain constant during a buffer transfer 3 RI Requester Address Increment Decrement 0 Causes the requester address to be incremented after each data transfer in a buffer transfer 1 Causes the requester address for the channel specified by bit 0 to be decremented after each data transfer in a buffer transfer Note that it does not decrement words When decrementing it will do two byte transfers for a word Note When the target address is programmed to remain constant DMAMOD2 4 1 this bit is a don t care 2 TH Target Address Hold 0 Causes the address to be modified incremented or decremented depending on DMAMOD1 5 1 Causes the target s address for the channel specified by bit 0 to remain constant during a buffer transfer 1 0 Must be 0 for correct operation 0 CS Channel Select 0 The selections for bits 7 2 affect channel 0 1 The selections for bits 7 2 affect channel 1 D 22 intel SYSTEM REGISTER QUICK REFERENCE D 18 DMAMSK DMA Individual Channel Mask Expanded Addr
550. r with bits 5 4 reset and SC1 and SCO bits 7 6 programmed appropriately A counter continues to run even after the count is latched The counter latch command allows reading the count without disturbing the count in progress 10 27 Intel386 EX EMBEDDED PROCESSOR USER S MANUAL intel Timer Control Counter latch Format Expanded Addr F043H TMRCON ISA Addr 0043H Reset State XXH 7 0 SC1 SCO 0 0 0 0 0 0 Bit Bit Number Mnemonic Function 7 6 SC1 0 Select Counter These bits specify the counter that receives the counter latch command 00 counter 0 01 counter 1 10 counter 2 11 is not an option for TMRCON s counter latch format Selecting 11 accesses TMRCON s read back format which is shown in Figure 10 29 5 4 Write zeros to these bits to issue a counter latch command to the counter specified by bits 7 6 01 10 and 11 are not valid options for TMRCON s counter latch format 3 0 Reserved for compatibility with future devices write zeros to these bits NOTE Bits 5 0 serve another function when you select the read back command SC1 0 11 See Figure 10 29 for the read back bit functions Figure 10 27 Timer Control Register TMRCON Counter latch Format When a counter receives a counter latch command it latches the count This count remains latched until you either read the count or reconfigure the counter When you send multiple
551. rammed by the user Voc P System Power Provides the nominal DC supply input Connected externally to a board plane Vas G System Ground Provides the 0 volt connection from which all inputs and outputs are measured Connected externally to a ground board plane WDTOUT Watchdog Timer Output Indicates that the watchdog timer has expired W R Write Read Indicates whether the current bus cycle is a write cycle or a read cycle WR Write Enable Indicates that the current bus cycle is a write cycle A 7 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Table A 3 defines the abbreviations used in Table A 4 to describe the pin states Table A 3 Pin State Abbreviations Abbreviation Description Output driven to Voc Output driven to Vas Output floats Output remains active Output retains current state Pin floats and has a temporary weak pull up Pin floats and has a temporary weak pull down In tel intel SIGNAL DESCRIPTIONS Table A 4 lists the states of output and bidirectional pins after reset and during idle mode pow erdown and hold Table A 4 Pin States After Reset and During Idle Powerdown and Hold Sheet 1 of 2 Pin State Symbol Type Reset Idle Powerdown Hold A25 1 O 1 1 1 2 ADS 1 1 1
552. rate Control Register SSIOBAUD 13 20 intel SYNCHRONOUS SERIAL UNIT 13 3 5 SSIO Baud rate Count Down Register SSIOCTR Read SSIOCTR to determine the status of the baud rate generator The down counter is reloaded when CV6 0 reaches zero or when a new value is written to SSIOBAUD Baud rate Count Down Expanded Addr F48AH SSIOCTR ISA Addr read only Reset State 00H 7 0 BSTAT CV6 CV5 CV4 CV2 CV1 cvo Bit Bit Function Number Mnemonic unctio 7 BSTAT Baud rate Generator Status 0 The baud rate generator is disabled 1 The baud rate generator is enabled 6 0 CV6 0 Current Value These bits indicate the current value of the baud rate down counter Figure 13 19 SSIO Baud rate Count Down Register SSIOCTR 13 3 6 SSIO Control 1 Register SSIOCON1 SSIOCONI contains both transmit and receive control and status bits Use the control bits to en able the receiver and transmitter and to connect the transmit buffer empty and receive buffer full signals to the interrupt control unit The status bits indicate that the transmit buffer is empty a transmit underrun error occurred the receive buffer is full or a receive overflow error occurred Both the transmit buffer empty and the receive buffer full signals can be connected ORed to the interrupt request source SSIOINT When an interrupt request from this source is detected you can dete
553. ration Command Word 2 OCW2 intel INTERRUPT CONTROL UNIT 9 3 9 Operation Command Word OCW3 Use OCW3 to enable the special mask mode issue a poll command and provide access to the interrupt in service and request registers ISR IRR Operation Command Word 3 master slave OCW3 master and slave Expanded Addr F020H FOAOH write only ISA Addr 0020H Reset State XXH XXH 7 0 0 ESMM SMM RSEL1 RSELO POLL ENRR RDSEL Bit Bit Number Mnemonic Function m Clear this bit to guarantee device operation ESMM Enable Special Mask Mode ESMM and Special Mask Mode SMM SMM Use these bits to enable or disable special mask mode ESMM SMM 0 0 No action 0 1 No action 1 0 Disable special mask mode 1 1 Enable special mask mode 4 3 RSEL1 0 Register Select ICW1 OCW2 and OCWS are accessed through the same addresses The states of RSEL1 0 determine which register is accessed Write 01 to these bits to access OCW3 RSEL1 RSELO 0 0 OCW2 0 1 OCWS 1 X ICW1 2 POLL Poll Command Set this bit to issue a poll command thus initiating the polling process 1 ENRR Enable Register Read Select ENRR and Read Register Select 0 RDSEL RDSEL These bits select which register is read during the next F020H and FOAOH or PC AT address 0020H 00A0H read access ENRR RDSEL Register Read on Next Read Pulse 0 0 No action 0 1 No action 1 0 Interrupt Request Register 1 1
554. rator in put frequency intel ASYNCHRONOUS SERIAL UNIT The baud rate generator s output frequency is determined by BCLKIN and a divisor as follows baud rate generator output frequency BU ERIN fr guoney divisor baud rate generator output frequency 16 bit rate The minimum divisor value is 1 giving a maximum baud rate of BCLKIN The maximum divisor value is OFFFFH 65535 giving a minimum of BCLKIN 65535 For example the maximum and minimum bit rate frequencies using SERCLK with a 25 MHz device CLK2 50 MHz or COMCLK with a 12 5 MHz input are shown in Table 11 2 Table 11 3 shows the divisor values required for common baud rates Table 11 2 Maximum and Minimum Output Bit Rates Input Clock BCLKIN Divisor Output Bit Rate 12 5 MHz 0001H 781 25 KHz max 12 5 MHz OFFFFH 11 921 Hz min Table 11 3 Divisor Values for Common Bit Rates Divisor Input Clock BCLKIN Output Bit Rate Error 1AEH 16 5 MHz processor clock 33 MHz 2400 b s 0 07 6BH 16 5 MHz processor clock 33 MHz 9600 b s 0 39 48H 16 5 MHz processor clock 33 MHz 14 4 Kb s 0 54 145H 12 5 MHz processor clock 25 MHz 2400 b s 0 15 51H 12 5 MHz processor clock 25 MHz 9600 b s 0 47 36H 12 5 MHz processor clock 25 MHz 14 4 Kb s 0 46 104H 10 MHz processor clock 20 MHz 2400 b s 0 15 41H 10 MHz processor clock 20 MHz 9600 b s 0 16 2BH 1
555. rdown Mode During SMM Both Idle Mode and Powerdown Mode may be used while in SMM Entering and exiting either of these power management modes from SMM is identical to entering or exiting from normal mode The interaction between SMM and power management modes is described in Chapter 8 7 3 3 4 SMI During SMM Operation If the SME request is asserted during SMM operation the second SMI cannot nest the currently executing SMM The second SMI request is latched and held pending by the CPU Only one SMI request can be pending After RSM execution is completed the pending 5 is serviced At this time SMIACT is deasserted once at completion of RSM then asserted again for the sec ond SMI When the SMM handler polls the various SMI sources for one of the SMI triggers and two SMI sources are found in the SMI generation circuit the SMM handler services both SMI sources and executes a RSM instruction In this SMM handler if the SMI generation circuit as serts the second SMI during the first SMI service routine the second SMI is pending Next the SMM handler finds and services two SMI sources After the CPU completes the RSM exe cution the pending SMI second 5 is generated but there is nothing to service because the second SMI was serviced during the first SMM handler This unnecessary SMI transaction re quires a few hundred clocks There may be some performance degradation if this example occurs frequently For go
556. re 9 12 Initialization Command Word 4 Register ICW4 intel 9 3 7 Operation Command Word 1 OCW1 INTERRUPT CONTROL UNIT OCW is the interrupt mask register Setting a bit in the interrupt mask register disables masks interrupts from the corresponding IR signal For example setting the master s OCW1 M3 bit dis ables interrupts from the master IR3 signal Clearing a bit in the interrupt mask register enables interrupts from the corresponding IR signal 0 Enables interrupts on the corresponding IR signal 1 Disables interrupts on the corresponding IR signal NOTE Setting the mask bit does not clear the respective interrupt pending bit Operation Command Word 1 master slave OCW1 master and slave Expanded Addr F021H FOA1H read write ISA Addr 0021H 1 Reset State XXH XXH 7 0 M7 M6 M5 4 2 1 MO Bit Bit Number Mnemonic Function 7 0 M7 0 Mask IR set NOTE The 8259A must be initialized before it can be used After reset the 8259A register states are undefined The 8259A modules must be initialized before the IF flag in the core FLAG register is Figure 9 13 Operation Command Word 1 OCW1 9 25 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 9 3 8 Operation Command Word 2 OCW2 Use OCW2 to change the priority structure and issue EOI commands Opera
557. re eterne ahd pere doce 14 4 4 Pin Configuration Register PINCFG 2 14 4 2 Port 2 Configuration Register 2 2 14 4 8 Chip select Address Registers eene 14 4 4 Chip select Mask Registers essere ener 14 5 DESIGN 14 6 PROGRAMMING 14 6 1 Chip Select Unit Code Example CHAPTER 15 REFRESH CONTROL UNIT 15 1 DYNAMIC MEMORY 15 1 1 Refresh Methods 15 2 REFRESH CONTROL UNIT OVERVIEW 15 244 RCU Signals eet eene Den de 15 2 2 Refresh Intervals intel CONTENTS 15 2 3 Refresh Addresses cce wei teet 1594 15 244 Bus Arbitration ccc iore ree 19 5 153 BGU OPERATION min erret dr rx o ee aes ned ey 15 5 15 4 REGISTER DEFINITIONS vial 970 15 4 4 Refresh Clock Interval Beaister RFSCIR io EQUI Rie teste ue d OS 15 4 2 Refresh Control Register RFSCON sse 19 8 15 4 8 Refresh Base Address Register RFSBAD 19 9 15 4 4 Refresh Address Register RFSADD see emen 15 10 15 5 DESIGN 11215 11 15 6 PROGRAMMING
558. re mapped into the expanded address space This mode decodes all 16 address bits All internal peripherals can be accessed only in the expanded address space The addressing mode in which the internal timer interrupt controller serial I O ports and DMA controller can be individually mapped out of the DOS address space and replaced by the corresponding external peripherals This mode decodes only the lower 10 address bits so the expanded address space is inaccessible The term normally not ready refers to a system in which a bus cycle continues until the accessed device asserts READY Glossary 3 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel PC AT Address Space Pipelining Powerdown Mode RCU Reserved Bits Set SIO Unit SMM SMRAM SSIO Unit Glossary 4 Addresses OH 03FFH The internal timers interrupt controller serial I O ports and DMA controller can be mapped into this space In this manual the terms DOS address and PC AT address are synonymous A bus interface technique that controls the address and status outputs so the outputs for the next bus cycle become valid before the end of the current bus cycle allowing external bus cycles to overlap By increasing the amount of time available for external memory or I O devices to respond pipelining allows systems to achieve high bandwidth with relatively slow inexpensive components The power conservation mode that freezes both the core
559. register When TRST is asserted the test logic reset state forces the IDCODE instruction into the in struction register s parallel output latches You can also load this instruction like any other by ma nipulating the TDI input to supply the binary opcode 0010 The Capture DR state loads the identification code into the IDCODE register and the Shift DR state shifts the value out 18 3 2 Bypassing Devices on a Board The BYPASS instruction allows you to bypass one or more devices on a board while testing oth ers This significantly reduces the time required for a test For example assume that a board has 100 devices each of which has 101 bits in its boundary scan register If the boundary scan cells are all connected in series the boundary scan path is 10 100 stages long Bypassing devices al lows you to shorten the path considerably If you set 99 of the devices to shift through their bypass registers and only a single chip to shift through its boundary scan register 101 bits in this case the serial path is only 200 stages long You load the BYPASS instruction by manipulating TDI to supply the binary opcode 1111 The Capture DR state loads a logic 0 into the bypass register and the Shift DR state shifts the value out 18 3 3 Sampling Device Operation and Preloading Data The SAMPLE PRELOAD instruction has two functions SAMPLE takes a snapshot of data flow ing from or to the system pins to or from on chip system logic while PR
560. registered logic such as PALs PLDs and EPLDs Many signals are sampled by the processor on every other CLK2 rising edge some are sampled on the CLK2 edge when CLKOUT is going high while others are sampled on the CLK2 edge when is going low The maximum data transfer rate for a bus operation is 16 bits for every two processor clock cycles two CLKOUT cycles During the first bus state T1 address and bus status pins go active During the second bus state T2 external logic and devices respond When the READY input is sampled low at the falling edge of PH2 in T2 the bus cycle terminates When READY is high when sampled the bus cycle continues for an additional T2 state called a wait state and READY is sampled again This process continues until READY is sampled active at which point the bus cycle terminates Wait states are added until READY is sampled low READY is sampled externally when the LBA signal is inactive When the LBA signal is active the processor is generating the READY signal internally READY can be generated internally by either an internal peripheral or the chip select unit s wait state generator When no bus cycles are needed no bus requests are pending the processor remains in the idle bus state Ti The relationship between T1 T2 and Ti is shown in Figure 6 2 From an idle bus the processor begins a bus cycle by first driving a valid address and bus cycle status onto the address an
561. res from PC AT architecture bus signals B 2 CPU only reset B 4 DMA unit B 1 HOLD HLDA pins B 4 B 5 interrupt control unit B 4 SIO units B 4 DRAM refreshing 15 12 DRAM See Refresh control unit E EISA compatibility 4 3 4 5 ESE bit programming 4 8 Exceptions and interrupts relative priority 7 7 Execution Unit 3 4 3 5 Expanded address defined 1 4 Expanded I O address space 4 3 enabling disabling 4 8 F FaxBack service 1 6 Flow diagram CSU bus cycle length adjustment 14 12 demand data transfer mode 12 22 12 24 DMA block data transfer mode 12 19 12 20 DMA cascade mode 12 26 DMA demand data transfer mode 12 22 DMA single data transfer mode 12 15 12 17 interrupt process 9 11 9 12 9 13 SIO reception 11 11 SIO transmission 11 8 H HALT cycle Ready generation 8 10 HALT restart from SMM 7 9 HOLD HLDA departures from PC AT architecture B 4 B 5 timing 6 20 6 35 I O ports See Input output ports I O restart from SMM 7 9 ICU See Interrupt control unit Index 4 intel IDCODE 18 2 Identifier registers 3 6 7 15 Idle mode 8 9 bus interface unit operation during 8 5 SMM interaction with 8 5 timing diagram 8 9 watchdog timer unit operation during 8 5 IEEE Standard Test Access Port and Boundary Scan Architecture 18 1 Input output ports 16 1 16 10 block diagram 16 2 design considerations 16 10 overview 16 1 16 5 pin multiplexing 16 5 pin reset status 16 5 programm
562. resh Unit are not affected by this bit 1 Setting this bit leaves core generated addresses unmodified 0 CPURST CPU Reset 0 Clearing this bit performs no operation 1 Setting this bit resets the core without resetting the peripherals This bit must be cleared before issuing another reset D 50 intel SYSTEM REGISTER QUICK REFERENCE D 49 PWRCON Power Control Register Expanded Addr F800H PWRCON ISA Addr read write Reset State 00H 7 0 WDTRDY HSREADY PC1 PCO Bit Bit Number Mnemonic Function 7 4 Reserved These bits are undefined for compatibility with future devices do not modify these bits 3 WDTRDY Watch Dog Timer Ready 0 An external READY must be generated to terminate the cycle when the WDT times out in Bus Monitor Mode 1 Internal logic generates READY to terminate the cycle when the WDT times out in Bus Monitor Mode 2 HSREADY Halt Shutdown Ready 0 An external ready must be generated to terminate HALT Shutdown cycle 1 Internal logic generates READY to terminate a HALT Shutdown cycle 1 0 PC1 0 Power Control Program these bits then execute a HALT instruction The device enters the programmed mode when READY internal or external terminates the halt bus cycle When these bits have equal values the HALT instruction causes a normal halt and the device remains in active mode PC1
563. resh similar to DRAM This chapter is organized as follows Dynamic Memory Control see below Refresh Control Unit Overview page 15 2 RCU Operation page 15 5 Register Definitions page 15 6 Design Considerations page 15 11 Programming Considerations page 15 14 15 1 DYNAMIC MEMORY CONTROL Typical DRAM devices require control logic to enable read write and refresh operations The RCU simplifies control logic design requirements by providing the necessary cell access require ments for refresh operations DRAM devices are built as matrices of memory cells Therefore each memory cell has a row and column address associated with it A typical controller design strobes addresses into DRAM de vice through the use of two control lines a row address strobe RAS and a column address strobe CAS The controller presents lower or row address bits during RAS and upper or column address bits during CAS Activating RAS accesses all cells within the specified row Accessing a cell refreshes it therefore cycling through the row addresses refreshes a DRAM de vice 15 1 1 Refresh Methods There are two common methods for refreshing a DRAM device RAS only and CAS before RAS The DRAM controller design requirements are simpler for RAS only than for CAS be fore RAS 15 1 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel The RAS only method requires that the DRAM controller activate its RAS
564. ress bits are connected to the Row Address Buffer and the upper address bits are connected to the Column Address Buffer As in Page Mode the PLD recognizes a refresh request by sampling both BHE and BLE they are both inactive during a refresh cycle or by detecting an active signal on the REFRESH pin The buffer and lines that are active during this type of refresh have a shaded background in Figure 15 8 15 13 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Row Lower Address Row Address Address Buffer OE ROW Address RAS Non paged DRAM REFRESH eee gt Intel886 EX Embedded Processor CAS Y OE Column Address Upper Address Buffer Column Address Note A single mux can be used in place of the row and column address buffers A3265 02 Figure 15 8 RAS Only Refresh Logic Non Paged Mode 15 6 PROGRAMMING CONSIDERATIONS REFRESH and CS6 share a package pin To select the REFRESH signal at this pin set bit 6 in the PINCFG register _SetEXRegByte PINCFG GetEXRegByte PINCFG 0x40 15 6 1 Refresh Control Unit Example Code The following code example contains software routines that initialize the refresh control unit and retrieve the current value of the refresh interval timer See Appendix C for the included header files include lt conio h gt include 80386ex h include ev386ex h 8K Rk A A A A A A AA A
565. ri 3 internally driven low 1 0 0 P3 1 selected at pin P3 1 IR3 connected to pin INT8 1 0 1 IR3 connected to SIOINT 1 P3 1 selected at pin P3 1 IR3 connected to SIOINT 1 pin INT8 must not be left floating NOTE X isa don t Table 5 2 Master s IR4 Connections Function INTCFG 5 MCRO 3 P3CFG 0 IR4 connected to SIOINTO 0 X 0 P3 0 selected at pin P3 0 IR4 connected to SIOINTO 0 X 1 OUTO connected to pin TMROUTO IRA i Ily dri internally driven low 1 0 0 P3 0 selected at pin P3 0 IR4 connected to pin INT9 1 0 1 IR4 connected to SIOINTO P3 0 selected at pin P3 0 IR4 connected to SIOINTO pin INT9 must not be left floating NOTE intel DEVICE CONFIGURATION IRO OUTO TCU 8259A P3CFG 2 4 2 Master IR1 INTO 2 Vss IR2 DLN To From I O Port 3 lt gt MCR1 3 SIOINT1 SIOINT1 ie NTCFGS INTS INTCFG ER wt TMROUT1 OUT1 TCU 0 P3 1 P3 1 MCRO 3 SIOINTO d SIOINTO INTCFG 5 1 INTCFG pP P3GFG 0 INT9 TMROUTO uni 7 OUTO TCU 0 pa Seo P3 0 1 P3CFG 3 To From I O Port 3 0 Pee V 55 4 P3CFG 4 8 To From I O Port 3 0 P3 4 P3CFG 5 Vss 1 P3CFG 5 INT3 To From I O Port 3 0 5 INTCFG 0 Vss 7174 To TCU TMRCLKO INTCFG 1 SSIOINT INT5 To TCU TMRGATEO OUT1 TCU OUT2 TCU INTCFG 4 P DMAIN
566. ring any cycle has no additional pffects i cue 0503 2210222 osa oa 2477 03 Figure 6 8 Pipelined Address Cycles 6 21 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel In cycle 3 NA is sampled in the first T state T1P the address and status have been valid for one previous T state and this is a new bus cycle NA is sampled active and because a bus cy cle cycle 4 is pending internally the address byte enables and bus status signals for this pending bus cycle cycle 4 are driven during the next T2P state In cycle 4 NA is sampled in the first T state T1P the address and status have been valid for one previous T state and this is a new bus cycle is sampled active and because a bus cycle is not internally pending the address and byte enables go to an unknown state and the bus status signals go inactive in the next T2i state When this cycle is terminated by an active READY signal there is no bus cycle pending internally and the bus enters the idle state Ti From an idle bus an additional overhead of one clock cycle is required to start a pipelined bus cycle this is true with all pipelined bus architectures This additional clock is used to pipeline the address and status signals for the first bus cycle in a train of pipelined bus cycles As long as back to back bus cycles are executed the pipelined bus ca
567. riority When more than one exception or interrupt is pending at an instruction boundary the processor services them in a predictable order The priority among classes of exception and interrupt sourc es is shown in Table 7 3 The processor first services a pending exception or interrupt from the class that has the highest priority transferring execution to the first instruction of the handler Lower priority exceptions are discarded lower priority interrupts are held pending Discarded ex ceptions are reissued when the interrupt handler returns execution to the point of interruption SMI has the following relative priority where 1 is highest and 11 is lowest Table 7 3 Relative Priority of Exceptions and Interrupts 1 Double Fault Highest priority 2 Segmentation Violation 3 Page Fault 4 Divide by zero 5 SMI 6 Single step 7 Debug 8 ICE Break 9 NMI 10 INTR 11 Lock Lowest Priority Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 7 3 2 2 System Management Interrupt During HALT Cycle Since SME is an asynchronous signal it may be generated at any time A condition of interest arises when an SMI occurs while the CPU is in a HALT state To give the system designer max imum flexibility the processor allows an SMI to optionally exit the HALT state Figure 7 3 shows that the CPU normally re executes the HALT instruction after RSM however by modify ing the
568. rite only F018H DMA Bus Size Determines the requester and target data bus widths 8 or 16 bits 12 29 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Table 12 3 DMA Registers Sheet 3 of 3 mois Register Address Address Description DMACHR F019H DMA Chaining write only Enables chaining buffer transfer mode for a specified channel DMAIEN F01CH DMA Interrupt Enable read write Connects the channel transfer complete status signals to the interrupt request output DMAINT DMAIS F019H DMA Interrupt Status read only Indicates which signal generated an interrupt request channel 0 transfer complete channel 1 transfer complete channel 0 chaining or channel 1 chaining status DMAOVFE F01DH DMA Overflow Enable read write Included for 8237A compatibility Controls whether all 26 bits or only the lower 16 bits of the requester and target addresses are incremented or decremented during buffer transfers Controls whether the byte count is 24 bits or 16 bits 12 30 intel DMA CONTROLLER 12 3 1 Pin Configuration Register PINCFG Use PINCFG to connect DACKO EOP and DACK1 to package pins Pin Configuration Expanded Addr F826H PINCFG ISA Addr read write Reset State 00H 7 0 PM6 PM5 PM4 PM3 PM2 PM1 PMO Bit Bit Number Mnemonic Function 7 Reserved
569. rmine which signal caused the request by reading the SSIOCONI receive buffer full and transmit buffer empty status bits 13 21 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL SSIO Control 1 Expanded Addr F486H SSIOCON1 ISA Addr read write Reset State COH 7 0 TUE THBE TIE TEN ROE RHBF RIE REN Bit Bit Number Mnemonic Function 7 TUE Transmit Underrun Error The transmitter sets this bit to indicate a transmit underrun error in the TEN transfer mode Clear this bit to clear the error flag If a one is written to TUE itis ignored and TUE retains its previous value 6 THBE Transmit Holding Buffer Empty read only bit The transmitter sets this bit when the transmit buffer contents have been transferred to the transmit shift register indicating that the buffer is now ready to accept new data Writing data to the transmit buffer clears THBE When this bit is clear the buffer is not ready to accept any new data 5 TIE Transmitter Interrupt Enable 0 Clearing this bit prevents the Interrupt Control Unit from sensing when the transmit buffer is empty 1 Setting this bit connects the transmit buffer empty internal signal to the Interrupt Control Unit 4 TEN Transmitter Enable 0 Disables the transmitter 1 Enables the transmitter 3 ROE Receive Overflow Error The receiver sets this bit to indicate a receiver overflow error Write zero to this bit to clear the fl
570. robe See Mode 5 initial count values 10 26 interrupt on terminal count See Mode 0 mode 0 10 6 10 8 basic operation 10 7 disabling the count 10 7 writing a new count 10 8 mode 1 10 8 10 10 basic operation 10 9 retriggering the one shot 10 9 writing a new count 10 10 mode 2 10 10 10 12 basic operation 10 11 disabling the count 10 11 writing a new count 10 12 Index 9 INTEL386 EX MICROPROCESSOR USER S MANUAL mode 3 10 12 10 15 basic operation 10 13 10 14 basic operation odd count 10 14 disabling the count 10 14 writing a new count 10 15 mode 4 10 16 10 17 basic operation 10 16 disabling the count 10 17 writing a new count 10 17 mode 5 10 18 10 19 basic operation 10 18 retriggering the strobe 10 19 writing a new count 10 19 operation 10 5 10 19 operations caused by GATEn 10 6 overview 10 1 10 4 programming considerations 10 33 initializing the counters 10 24 10 25 D 63 input and output signals 10 20 10 23 reading the counter 10 27 10 33 counter latch command 10 27 read back command 10 30 simple read 10 27 TMRCFG 5 13 10 21 D 62 TMRCON 10 25 10 28 D 63 TMRn 10 29 10 32 D 64 D 65 writing the counters 10 26 rate generator See Mode 2 read back commands multiple 10 33 register addresses 4 16 D 2 registers 10 4 TMRCON 10 30 TMRn 10 26 signals 10 3 software triggered strobe See Mode 4 square wave See Mode 3 Timing 8 9 Timing diagram basic external bus cycles
571. rol DMA transfers one byte or word of data and decrements the byte count Byte count FFFFFFH or active No Yes DMA channel relinquishes bus control DMA channel is reprogrammed with the original addresses and byte count A2333 02 Figure 12 12 Block Data transfer Mode with Autoinitialize Buffer transfer Mode 12 20 intel DMA CONTROLLER 12 2 7 3 Demand Data transfer Mode In demand data transfer mode a channel request initiates a buffer transfer The channel gains bus control and begins the buffer transfer As long as the request signal DRQn remains active the channel continues to perform data transfers When the DRQn signal goes inactive the channel completes its current bus cycle and relinquishes bus control suspending the buffer transfer In this way the demand mode allows peripherals to access memory in small irregular bursts without wasting bus control time As in other data transfer modes a buffer transfer is completed when the buffer s byte count expires or is terminated if the input is activated At this point the chan nel s buffer transfer mode determines whether the channel becomes idle or is reprogrammed Since DRQn going inactive suspends a buffer transfer the channel continually samples DRQn during a demand buffer transfer During a buffer transfer the channel can sample DRQn synchro nously or asynchronously it always samples DRQn asynchronously at the start
572. rovides the READY signal internally to terminate a bus transaction This signal is active when the processor accesses an internal peripheral or when the chip select unit generates the READY signal for accesses to an external peripheral LBA is also active when internal READY generation is enabled for Halt Shutdown cycles and the Watchdog Timer Unit s Bus Monitor Mode timeouts The LBA signal goes active in the first T2 state and stays active until the first T2 T2i or T2P state of the next cycle that does not have internal READY generation LOCK Device pin Bus Lock Prevents other bus masters from gaining control of the system bus Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Table 6 1 Bus Interface Unit Signals Sheet 2 of 2 Device Pin or Signal Internal Signal Description only Device pins Bus Cycle Definition Signals Data Control Write Read D C and Refresh W R These four status outputs define the current bus cycle type as shown REFRESH in Table 6 2 NA Device pin Next Address Requests address pipelining RD Device pin Read Enable Indicates that the current bus cycle is a read cycle and the data bus is able to accept data READY Device pin Ready This bidirectional pin is used to terminate the current bus cycle The processor drives READY when LBA is active The processor samples the READY pin at the falling edge of
573. rror conditions do not cause interrupts 1 Connects the receiver line status signal to the interrupt control unit s SIOINTn output Sources for this interrupt include overrun error parity error framing error and break interrupt 1 TBE Transmit Buffer Empty Interrupt Enable 0 Transmit Buffer Empty signal does not cause interrupts 1 Connects the transmit buffer empty signal to the interrupt control units SIOINTn output 0 RBF Receive Buffer Full Interrupt Enable 0 Receive buffer full signal does not cause interrupts 1 Connects the receive buffer full signal to the interrupt control unit s SIOINTn output control register NOTE The interrupt enable register is multiplexed with the divisor latch high register You must clear bit 7 DLAB of the serial line control register LCRn before you can access the interrupt Figure 11 17 Interrupt Enable Register IER n 11 27 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 11 3 9 Interrupt ID Register IIR Use the IIRn to determine whether an interrupt is pending and if so which status signal generated the interrupt request Interrupt ID IIRO IIR1 IIRO IIR1 Expanded Addr F4FAH F8FAH read only ISA Addr 2 Reset State 01H 01H 7 0 152 151 IP Bit Bit A Number Mnemonic Function 7 3 ao Reserved These bits are undefined 2 IS2 1 Interrupt Source If an
574. rs the received word from the receive shift register to SSIORBUF Figure 13 23 SSIO Receive Holding Buffer SSIORBUF 13 4 DESIGN CONSIDERATIONS The transmit buffer empty signal can be connected to the interrupt control and DMA units How ever at high baud rates interrupt latency is too long to prevent a transmit underrun error For these cases use the DMA to load the data to be transmitted into the transmit buffer To illustrate this point assume the maximum input transmit baud rate of 8 25 MHz To prevent a transmit underrun error a new 16 bit data word must be written to the transmit buffer before the transmit shift register shifts out 16 bits 16 bits x 16 121 1939 ns 3 25 MHZ At 33 MHz one clock is 30 ns The transmit buffer must be reloaded within 64 clocks 1939 30 but interrupt latency is longer than 64 clocks Therefore the DMA unit is required to load the transmit buffer 13 25 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 13 5 PROGRAMMING CONSIDERATIONS When operating the transmitter in Master mode and not in Autotransmit mode you must ensure that the last character to be transmitted is in the process of being shifted out before disabling the transmitter If the transmitter is disabled before the character has begun shifting the character remains in the shift register and is shifted out when the transmitter is re enabled At high baud rates this can be a problem
575. rst intel SYSTEM MANAGEMENT MODE SetEXRegByte SIOPortBase DLH HIBYTE BaudDivisor SetEXRegByte SIOPortBase DLL LOBYTE BaudDivisor Set Serial Line control register SetEXRegByte SIOPortBase LCR Mode Sets Mode and resets the Divisor latch Set modem control bits _SetEXRegByte SIOPortBase MCR ModemCntrl return E_OK RRR KK k k k k kk k k k k k k k kk k k k k k ke ke k k MAIN FRR IK KK I KK I OR Parameters None Returns None Assumptions None Real Protected Mode No changes required ee ee eee eee ee ee ee ee 26 ae hae nee ane fn 4 s zn at TE ERE ifndef SetEXRegWordInline define SetEXRegWordInline address word asm mov dx address N asm mov ax word asm out dx void main void InitSIO SIO PORT Which Serial Port SIO 8 1 Mode 8 data no parity 1 stop SIO RTS SIO MCR Modem line controls 9600 Baud Rate BAUD_CLKIN Baud Clocking Rate asm Store registers to preserve values push DI push SI push DS push ES SetEXRegWordInline CS4ADL 0x702 Configure chip select 4 SetEXRegWordInline CS4ADH 0x0 SetEXRegWordInline CS4MSKL OxFCO1 SetEXRegWordInline CS4MSKH 0x0 7 19 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL SetEXRegWordInline CS2ADL 0x08700 SetEXRegWordInline CS2ADH 0 3 SetEXRegWordInline CS2MSKL 0x07C01 SetEXRegWordInlin
576. s For both edge and level triggered interrupts a high level must be maintained on the IR line until after the falling edge of the first INTA pulse see Figure 9 18 A spurious interrupt request is generated if this stipulation is not met A spurious interrupt on any IR line generates the same vec tor number as an IR7 request The spurious interrupt however does not set the in service bit for IR7 Therefore an IR7 interrupt service routine must check the in service register to determine whether the interrupt source was a valid the in service bit is set or a spurious interrupt the in service bit is cleared INTA IR Spurious A IR Valid A IR sampled on this edge A2431 01 Figure 9 18 Spurious Interrupts 9 4 4 Cascading Interrupt Controllers Figure 9 19 is a block diagram showing the connections for two cascaded 82C59As The PLD generates READY for the second Interrupt Acknowledge Cycle and INTA to the external 82C59A devices The PLD also generates appropriate timings for the INTA signals to satisfy 82C59A specifications The RD and WR strobes are used to read and write to the 82C59A registers These strobes are inactive during Interrupt Acknowledge Cycles 9 30 intel INTERRUPT CONTROL UNIT Intel386 EX Processor READY BEADS W R D C ADS LBA CLKOUT CLK2 INTA and READY State Machine CASO CAS1 External CAS Decode 82C59As A285
577. s When a channel is configured to decrement the requester or target address and transfer words the correct number of words is transferred however the transfers are on a byte basis Enabling both the autoinitialize and chaining buffer transfer modes will have unpredictable results The DMA controller does not allow programming one channel while another channel is active If both channels are being used the programmer must mask an active channel before reprogramming the other channel Failure to do this may result in incorrect DMA transfers 12 5 1 DMA Controller Code Examples This section contains these software routines EnableDMAHWRequests Enables channel hardware requests for the given DMA channel DisableDMAHWRequests Disables channel hardware requests for the specified DMA channel SetDMAReqIOAddr Sets the requester to an I O port address for the specified channel SetDMATargMemAddr Sets the target memory address for the specified DMA channel SetDMA XferCount Sets the target memory device for the specified DMA channel InitDMA Initializes the DMA 12 51 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel InitDMA 1ForSSIXmitterToMem Initializes DMA channell for transfers between the SIO transmitter port and memory DMAInterrupt Interrupt Service Routine for DMA generated interrupts See Appendix C for included header files include 80386ex h include ev386ex h include dma h include lt DOS
578. s bit and the TXMM bit causes TEN to be ignored Every time a word is loaded into the transmit shift register from the transmit holding buffer it is transmitted out and then stops 1 TXMM Transmit Master Mode 0 Clearing this bit puts the transmitter in slave mode In slave mode an external device controls the transmit serial communications An input on the STXCLK pin clocks the transmitter 1 Setting this bit puts the transmitter in master mode In master mode the internal baud rate generator controls the transmit serial communications The baud rate generator s output clocks the internal transmitter and appears on the STXCLK pin 0 RXMM Receive Master Mode 0 Clearing this bit puts the receiver in slave mode In slave mode an external device controls the receive serial communications An input on the SRXCLK pin clocks the receiver 1 Setting this bit puts the receiver in master mode In master mode the internal baud rate generator controls the receive serial communications The baud rate generator s output clocks the internal receiver and appears on the SRXCLK pin Figure 13 21 SSIO Control 2 Register SSIOCON2 13 23 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 13 3 8 SSIO Transmit Holding Buffer SSIOTBUF Write the data words to be transmitted to SSTOTBUF Use the interrupt controller DMA unit or polling read SSIOCON1 to determine when to write to the transmit buffer
579. s bit to guarantee device operation D 27 ICW4 MASTER AND SLAVE Initialization Command Word 4 master slave ICWA master and slave Expanded Addr F021H FOA1H write only ISA Addr 0021H 00A1H Reset State XXH XXH 7 0 0 0 0 SFNM 0 0 1 Bit Bit Number Mnemonic Function 7 5 Write zero to these bits to guarantee device operation 4 SFNM Special fully Nested Mode 0 Selects fully nested mode 1 Selects special fully nested mode Only the master 82C59A can operate in special fully nested mode 3 2 Write zero to these bits to guarantee device operation 1 Automatic Mode 0 Disables automatic EOI mode 1 Enables automatic EOI mode Only the master 82C59A can operate in automatic EOI mode 0 Write one to this bit to guarantee device operation D 30 intel SYSTEM REGISTER QUICK REFERENCE D 28 IDCODE Identification Code Register 2027 0013H 3V IDCODE Reset State 2827 0013H 5V 31 24 0 0 1 0 0 3V 0 0 0 1 5V 23 16 0 0 1 0 0 1 1 1 15 8 0 0 0 0 0 0 0 0 7 0 0 0 0 1 0 0 1 1 Bit Bit Number Mnemonic Funci n 31 28 V3 0 Device version number 27 12 PN15 0 Device part number 11 1 MFR10 0 Manufacturer identification compressed JEDEC106 A code 0 IDP Identification Present Always true for this device This is the first data bit shifted out of the device during a data scan immediately following an exit
580. s calculated based on clocking source and clock frequency The clocking frequency is set by calling the InitializeLibrary function ClockRate Specifies the serial port clocking rate for internal clocking CLK2 for external COMCLK Returns Error Codes E_INVAILD_DEVICE Unit number specifies a non existing device E_OK Initialized OK No error Assumptions SIOCFG Has already been configured for Clocking source and Modem control source REMAPCFG register has Expanded I O space access enabled ESE bit set The processor Port pin are initialized separately Syntax define SIO 0 0x0 define SIO_8N1 SIO 8DATA SIO 1STOPBIT SIO NOPARITY define SIO MCR RTS 0 2 define SIO MCR DTR 0 1 define SIO 8DATA 0x3 define SIO 1STOPBIT 0 0 Clock rate of COMCLK i e External clocking define BAUD_CLKIN 1843200L int error error InitSIO SIO 0 Which Serial Port SIO 8 1 Mode 8 data no parity 1 stop SIO MCR RTS SIO MCR Modem line controls 9600 Baud Rate BAUD_CLKIN Baud Clocking Rate Real Protected Mode No changes required eK RK AR I RRR ARR AIA k k k A k k k k k k k k k k k IR int InitSIO int Unit BYTE Mode BYTE ModemCntrl DWORD BaudRate DWORD BaudClkIn WORD SIOPortBase WORD BaudDivisor Check for valid unit if Unit gt 1 11 34 intel return E INVALID DEVICE ASYNCHRONOUS SERIAL I O UNIT Set Port base based on serial port used
581. s not yet an internal bus request pending T2P subsequent clocks of a bus cycle when has been sampled active in the current bus cycle and there is an internal bus request pending T1P first clock of a pipelined bus cycle Ti idle state Th hold acknowledge state READY Negated A2376 02 Figure 6 7 Complete Bus States Including Pipelined Address 6 20 intel BUS INTERFACE UNIT 1 Cycle 2 Cycle 3 Cycle 4 Pipelined i Non pipelined i Pipelined Pipelined Write Read Write Read Late Ready i i Late Ready i i TIP 2 T2P T2 T2P TIP T2i T2 CLK2 CLKOUT 4 i DICE Valid2 alid3 alid ADS is asserted as i i i i d i i i soon as the GPU has i i another bus cycle to i i i i i perform which is not i i i always immediately i i after NAG i is dsserted WIRE WR WR i i i RD i i i i ADS i i i M e E Note ADS i is long as the CPU enters the T2P asserted in state during Cycle 13 address i every T2P state pelining is maintained in Cycle 4 ON J 1 NA could have been asserted in T1P if desired Assertion now is the latest time pbssible to allow the CPU to enter T2P state to maintain pipelining in cycle 3 Asserling more than once du
582. s on the system s programmed operating mode real pro tected or virtual86 Chapter 9 of the Intel386 SX Microprocessor Programmer s Reference Manual explains this relationship During an interrupt acknowledge cycle the ICU puts the interrupt s vector number on the bus From the interrupt vector number and the system s operating mode the core determines where to find the address of the interrupt s service routine You must initialize each 82C59A with an interrupt vector base number The 82C59As determine the vector number for each interrupt request from this base number The base vector number cor responds to the IRO signal s vector number and must be on an 8 byte boundary Other vector numbers are determined by adding the line number of the IR signal to the base For example if the base vector number is 32 the IR5 vector number is 37 Valid vector numbers for maskable interrupts range from 32 to 255 Because the base vector number must reside on an 8 byte boundary the valid base vector numbers are 32 n x 8 where 0 n 27 9 8 intel INTERRUPT CONTROL UNIT 9 2 4 Interrupt Process Each IR signal has a mask a pending and an in service bit associated with it The mask bit disables the IR signal The respective mask bits provide a way to individually disable the IR signals You can globally disable all interrupts to the core using the CLI instruction The mask bits reside in the OCWI The pending bit indicates that th
583. s out the contents of the instruction register or the selected data register LSB first on the falling edge of TCK If serial shifting is not taking place TDO floats TMRCLK2 Timer Counter Clock Input PEREQ TMRCLK1 An external clock source connected to the TMRCLKn pin INT6 TMRCLKO can drive the corresponding timer counter INT4 TMRGATE2 Timer Counter Gate Input BUSY TMRGATE1 Can control the counter s operation enable disable or INT7 TMRGATEO trigger depending on the programmed mode INTS TMROUT2 Timer Counter Output ERROR TMROUT1 Can provide the timer counter s output The form of the 1 8 TMROUTO output depends on the programmed mode P3 0 INT9 A 6 intel SIGNAL DESCRIPTIONS Table A 2 Description of Signals Available at the Device Pins Sheet 6 of 6 Multiplexed With Signal Type Name and Description Alternate Function TMS Test Mode Select Controls the sequence of the test logic unit s TAP controller states Sampled on the rising edge of TCK TRST ST Test Reset Resets the test logic units TAP controller Asynchronously clears the data registers and initializes the instruction register to 0010 the IDCODE instruction opcode TXD1 Transmit Data DACK1 TXDO Transmits serial data from the corresponding SIO channel P2 6 UCS Upper Chip select Activated when the address of a memory or I O bus cycle is within the address region prog
584. s programmed to generate an SIOINT on receiver errors the error can be serviced as part of the interrupt handler 11 10 ASYNCHRONOUS SERIAL I O UNIT Select the BCLKIN source and the receiver input baud rate Select the data frame Word length number of stop bits and type of parity Enable interrupts and or DMA Receiver shifts data into shift register from the RXDn pin Was a framing error detected No Was No a parity error detected Receiver sets the framing error flag Receiver sets the parity error flag Any error flags set Service error interrupt Yes if enabled Is receive buffer full flag set No Yes Receiver transfers data to receive buffer and sets overrun error flag No Receiver transfers data to receive buffer and sets receive buffer full flag End Was No a break condition detected Receiver sets the break interrupt flag Service error interrupt if enabled A2525 02 Figure 11 6 SIOn Data Reception Process Flow 11 11 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 11 2 4 Modem Control The modem control logic provides interfacing for four input signals and two output signals used for handshaking and status indication between the SIOn and a modem or data set An external modem or data set uses the input signals to inform the SIOn when tis rea
585. s sufficient priority The in service bits indicate which interrupt requests are being ser viced The priority structure determines whether a new interrupt request s level has sufficient pri ority to interrupt the current process You can use one of three methods to clear an in service bit enable the automatic end of interrupt AEOI mode issue a specific end of interrupt EOI command or issue a nonspecific EOI com mand The AEOI mode is available only on the master 82C59A AEOI mode This mode is enabled during system initialization In this mode the 82C594 clears the in service bit at the beginning of an interrupt s processing This means that interrupts of any level can interrupt the processing of other interrupts Specific EOI command This command instructs the 82C59A to clear a specific IR in service bit Nonspecific EOI command This command instructs the 82C59A to clear the in service bit that corresponds to the highest level IR signal active at that time 9 9 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel NOTE Unlike the AEOI mode this is a mode and not a command like specific EOI or nonspecific EOD which is enabled during initialization the other methods are commands issued during interrupt processing usually at the end of an interrupt s service routine Figure 9 3 illustrates the process that takes place when the master receives a non slave interrupt request which is a request on any IR signal to the
586. s the DMA to set BP The clear byte pointer software command DMACLRBP allows you to force BP to a known state 0 before writing to the registers The target and requester addresses are incremented decremented or left unchanged and the byte count is decremented after each data transfer within a buffer transfer Reading a register returns the current or modified value rather than the original programmed values The chaining buffer transfer mode requires that you write new transfer information to the channel before the current buffer transfer completes The channel determines whether new transfer information was written to it by checking the most significant byte of the target address Writing to this byte sets an internal flag that tells the channel that new transfer information was written to it Therefore it is only necessary to change the target address between chaining buffer transfers If you want to change the requester address and byte count also you should write these values before writing the most significant byte of the target address Ifachannel is configured to increment the requester address and the requester s bus size is selected as 16 bits the channel increments the requester address by two after each data transfer However if the channel is configured to decrement the requester address the channel only decrements the address by one This is true for the target also In other words the channels cannot decrement by word
587. s the automatic end of interrupt mode OCWh master 0 021 0021H Operation Command Word 1 OCW1 slave 0 1 00A1H Masks disables individual interrupt request signals read write OCWA2 master 0 020 0020H Operation Command Word 2 OCW2 slave 00A0H Changes interrupt levels and sends end of interrupt write only commands OCWS master 0 020 0020H Operation Command Word 3 OCWS slave 00A0H Enables special mask mode issues the poll command and write only allows access to the interrupt request and in service registers NOTE All master 82C59A registers are accessed through two expanded or PC AT addresses all the slave registers are accessed through two other expanded or PC AT addresses The order in which you write or read these addresses along with certain register bit settings determines which register is accessed intel INTERRUPT CONTROL UNIT Table 9 2 ICU Registers Sheet 2 of 2 Register Expanded POAT Function 9 Address Address IRR master 0 020 0020H Interrupt Request IRR slave OFOAOH 00 0 Indicates pending interrupt requests read only ISR master 0 020 0020H In service ISR slave OFOAOH 00A0H Indicates the interrupt requests that are currently being read only serviced POLL master 0 020 0020H Poll Status Byte 0 021 0021 Indicates whether any of the devices connected to the 82 59 POLL
588. set has detected the 510 1 0 channel s data carrier DRQ1 DMA External Request RXD1 DRQO Indicates that an external device requires DMA service DCD1 DSR1 Data Set Ready STXCLK DSRO Indicates that the modem or data set is ready to establish P1 3 the communications link with the SIO channel DTR1 Data Terminal Ready SRXCLK DTRO Indicates that the SIO channel is ready to establish a 1 2 communications link with the modem or data set l OD End of process 51 As an input this signal terminates transfer As an ouput it indicates that a DMA transfer has completed ERROR Error TMROUT2 Indicates the the math coprocessor has an error condition FLT Float Forces all bidirectional and output signals except TDO to a high impedance state HLDA Hold Acknowledge P1 7 Indicates that the processor has relinquished local bus control to another bus master in response to a HOLD request A 3 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Table A 2 Description of Signals Available at the Device Pins Sheet 3 of 6 Multiplexed With Signal Type Name and Description Alternate Function HOLD Hold Request P1 6 An external bus master asserts HOLD to request control of the local bus The processor finishes the current nonlocked bus transfer releases the bus signals and asserts HLDA INT9
589. sfer information is written to the channel Writing to the most significant byte of the target address clears this bit Note Outside chaining mode this bit becomes a don t care Figure 12 34 DMA Interrupt Status Register DMAIS 12 49 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 12 3 16 Software Commands The DMA contains four software commands clear byte pointer clear DMA clear mask register and clear transfer complete signal Each software command has an I O address associated with it see Table 12 4 To issue a software command write to its I O address the data written doesn t matter writing to the location is all that is necessary Table 12 4 DMA Software Commands Name i Command Functions Address DMACLRBP Clear byte pointer Resets the byte pointer flip flop Perform this OFOOCH or command at the beginning of any access to the 000CH channel registers to ensure a predictable place in the register programming sequence DMACLR Clear DMA Sets all DMA functions to their default states OFOODH or 000DH DMACLRMSK Clear mask register Simultaneously clears the mask bits of all channels OFOOEH or enabling all channels 000 DMACLRTC Clear transfer complete signal Resets the transfer complete signal DMAINT Allows the source of the request hardware software to acknowledge the completion of a transfer process
590. sh address 0 Refresh Bit 0 AO of the refresh address This bit is always 1 and is read only D 53 RFSBAD Refresh Base Address RFSBAD Expanded Addr ISA Addr F4A0H read write Reset State 0000H 15 8 RA25 RA24 RA23 RA22 7 0 RA21 RA20 RA19 RA18 RA17 RA16 RA15 RA14 Bit Bit Number Mnemonic runction 15 12 Reserved These bits are undefined for compatibility with future devices do not modify these bits 11 0 RA25 14 Refresh Base These bits make up the A25 14 address bits of the refresh address This establishes a memory region for refreshing D 54 intel SYSTEM REGISTER QUICK REFERENCE D 54 RFSCIR Refresh Clock Interval Expanded Addr F4A2H RFSCIR ISA Addr read write Reset State 0000H 15 8 RC9 RC8 7 0 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RCO Bit Bit i Number Mnemonic Function 15 10 Reserved These bits are undefined for compatibility with future devices do not modify these bits 9 0 RC9 0 Refresh Counter Value Write the counter value to these ten bits The interval counter counts down from this value When the interval counter reaches one the control unit initiates a refresh request provided it does not have a request pending The counter value is a function of DRAM specifications and processor frequency see the equation above
591. signals active and asserting ADS Figure 6 10 shows a halt bus cycle The address and status signals are driven to the following active states e M IOf and W R are driven high and D C is driven low to indicate a halt cycle or a shutdown cycle The address bus outputs a byte address of 2 for a halt condition and a byte address of for a shutdown condition These signals are used by external devices to respond to the halt or shutdown cycle NOTE The halt or shutdown bus cycle appears as a memory write operation to byte address 0 or 2 depending on whether a shutdown or halt cycle is being performed if the signal is not decoded External address decoders need to decode the D C signal to avoid erroneous writes to devices in this address region otherwise a halt or shutdown cycle corrupts the data at those addresses RD WR and the chip select signals UCS and CS6 0 are inactive during halt cycles READY can be generated externally or internally to terminate a Halt Shutdown cycle The HSREADY bit in the Power Control Register PWRCON see Figure 8 5 in Chapter 8 can be set to generate an internal READY for halt shutdown cycles If internal READY generation is enabled then the LB A signal goes active and behaves as described in Ready Logic on page 6 10 Also the cycle is always a zero wait state cycle When external READY is required to terminate the halt shutdown cycle then READY may be delayed to add wait states The
592. single block and demand that determine how the bytes or words that make up a buffer of data are transferred The DMAMODI register is used to select a channel s data transfer mode Single Mode A channel request causes one byte or word depending on the selected bus widths to be transferred Single mode requires a channel request for every data transfer within a buffer transfer Block Mode A channel request causes the entire buffer of data to be transferred Demand Mode The amount of buffer data bytes or words that the channel transfers depends on how long the channel request input is held active In this mode the channel continues to transfer data while the channel request input is held active when the signal goes inactive the buffer 12 13 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel transfer is suspended and the channel waits for the request input to be reactivated before it continues 12 2 7 1 Single Data transfer Mode In single data transfer mode a DMA request causes the channel to gain bus control The channel transfers data a byte or a word decrements the buffer byte count by 1 for byte transfers and 2 for word transfers then relinquishes bus control The channel will then Autoinitialize if it has been programmed to do so The channel continues to operate in this manner until the buffer trans feris complete or terminated In this mode the channel gives up bus control after every data trans fer and mu
593. smitter to controller SSIOCON 5 TIE ssiorx pin mux SSIOINT to Slave interrupt controller IR1 SSIOCON 1 RIE Receiver SSRBF SSIORX to DMA controller SRXCLK pin mux A2435 02 Figure 13 2 Transmitter in Master Mode Receiver in Slave Mode 13 2 intel SYNCHRONOUS SERIAL UNIT Clock Source Baud rate PSCLK or SERCLK Generator Transmitter SSTBE to DMA controller SSIOCON 5 TIE SSIOTX SSIOINT to Slave interrupt controller IR1 SRXCLK pin mux SSRBF SsioRX to DMA controller Receiver A2436 02 Figure 13 3 Transmitter in Slave Mode Receiver in Master Mode SSTBE to DMA controller SSIOCON 5 TIE SSIOINT A m C to Slave interrupt controller IR1 Transmitter SSIOTX pin mux SSIOCON 1 RIE Receiver SSRBF SSIORX to DMA controller SRXCLK pin mux 2437 02 Figure 13 4 Transmitter and Receiver Slave Mode 13 3 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL 13 1 1 SSIO Signals Table 13 1 lists the SSIO signals Table 13 1 SSIO Signals Device Pin or input i Description Signal Internal Signal STXCLK Device pin Serial Transmit Clock input or output This pin functions as either an output or an input depending on whether the transmitter is operating in master or sla
594. sor present 2 EM Emulate Coprocessor 0 coprocessor opcodes execute 1 coprocessor opcodes generate a fault 3 TS Task Switched 0 coprocessor ESC opcode does not cause fault 1 coprocessor ESC opcode causes fault 31 PG Paging Enable 0 paging disabled 1 paging enabled Debug register DR7 is also cleared except for bits 11 15 Internally a descriptor register invisible to the programmer is associated with each program mer visible segment register Each descriptor register holds a 32 bit segment base address a 32 bit segment limit and other necessary segment attributes When a selector value is loaded into a segment register the associated descriptor register is automatically updated with the correct in formation In Real mode only the base address is updated directly by shifting the selector value four bits to the left since the segment maximum limit and attributes are fixed in Real mode In Protected mode the base address the limit and the attributes are all updated per the contents of the segment descriptor indexed by the selector After saving the CPU state the SMM State Save sequence sets the appropriate bits in the segment descriptor placing the core in an environment similar to Real mode without the 64 Kbyte limit checking In SMM the CPU executes in a Real like mode In this mode the CPU can access read and write any location within the 4 Gbyte logical address space The physical address space is 64 Mbytes Th
595. st regain bus control through priority arbitration before every data transfer The channel s buffer transfer mode determines whether the channel becomes idle or is reprogrammed after a buffer transfer completes or is terminated The single data transfer mode is compatible with all of the buffer transfer modes The following flowcharts show the transfer process flow for a channel programmed for single data transfer mode with each buffer transfer mode single Figure 12 8 autoinitialize Figure 12 9 and chaining Figure 12 10 12 14 CONTROLLER After initialization the channel is programmed with the requester and target addresses and a byte count DREQn active Yes DMA gains bus control DMA transfers one byte or word of data and decrements the byte count DMA channel relinquishes bus control Byte count FFFFFFH or EOP active Yes Buffer transfer is complete so channel becomes idle A2331 02 Figure 12 8 Single Data transfer Mode with Single Buffer transfer Mode 12 15 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel After initialization the DMA channel is programmed with the requester and target addresses and a byte count DREQn active Yes DMA gains bus control DMA transfers one byte or word of data and decrements the byte count DMA channel relinquishes bus control Byte count FFFFFFH or active
596. start Slot Clear A2229 03 Figure 8 3 SMM Interaction with Idle and Powerdown Modes 8 1 2 2 Bus Interface Unit Operation During Idle Mode The bus interface unit BIU can process DMA DRAM refresh and external hold requests during idle mode When the first request occurs the core wakes up long enough to relinquish bus control to the bus arbiter then returns to idle mode For the remaining time in idle mode the bus arbiter controls the bus DMA DRAM refresh and external hold requests are processed in the same way as during normal operation 8 1 2 3 Watchdog Timer Unit Operation During Idle Mode When the watchdog timer unit is in system watchdog mode idle mode stops the down counter Since no software can run while the CPU is idle a software watchdog is not needed When it is in bus monitor or general purpose timer mode the watchdog timer unit continues to run while the device is in idle mode Chapter 17 describes the watchdog timer unit Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 8 1 3 Clock and Power Management Registers and Signals Table 8 1 lists the registers and Table 8 2 list the signals associated with the clock and power man agement unit Table 8 1 Clock and Power Management Registers Register pins Description Clock Prescale CLKPRS OF804H This register contains the programmed divisor value used to generate PSCLK from the internal
597. status register associated with it Table 16 2 The con trol registers PRCFG Pn DIR and PnLTC be both read and written The status register PIN can only be read four registers reside in I O address space Table 16 2 I O Port Registers Register Address Description P1CFG OF820H Port n Mode Configuration P2CFG OF822H Each bit controls the mode of the associated pin PSCFG OF824H 0 Selects I O mode read write 1 Selects peripheral mode P1DIR OF864H Port n Direction PIDE Pc Each bit controls the direction of a pin that is in I O mode 0 Configures a pin as a complementary output If a pin is in peripheral read write mode this value is ignored 1 Configures a pin as either an input or an open drain output P1LTC OF862H Port n Data Latch P2LTC OF86AH Each bit contains data to be driven onto an output pin that is in I O mode Write PSLTC 0F872H the desired pin state value to this register If a pin is in peripheral mode this read write value is ignored Reading this register returns the value in the register not the actual pin state P1PIN OF860H Port n Pin State P2PIN OF 868H Each bit of this read only register reflects the state of the associated pin 0 870 Reading this register returns the current pin state value regardless of the 5 read only mode and direction 16 6 intel INPUT OUTPUT PORTS 16 2 1 Pin Configuration You select the
598. struction that the SMI has trapped If the slot contains 00H when the RSM instruction is exe cuted the CPU does not re execute the I O instruction This slot is initialized to 00H during an SMI It is the SMM handler s responsibility to load the I O trap restart slot with OFFH when re start is desired NOTE The SMM handler must not set the I O trap restart slot to OFFH when the SMI is not asserted an I O instruction boundary because this causes unpredictable results 7 3 3 SMM Handler Interruption 7 3 3 1 Interrupt During SMM Handler When the CPU enters SMM both INTR and NMI are disabled Figure 7 6 The SMM handler may enable INTR by executing the STI instruction NMI is enabled after the completion of the first interrupt service routine software or hardware initiated ISR or exception handler within the SMM handler Software interrupt and exception instructions are not blocked during the SMM handler The SMM feature can be used without any other interrupts INTR and NMI are blocked by the system during SMI unless enabled by software If INTR or NMI are not enabled during SMM 7 10 intel SYSTEM MANAGEMENT MODE then any pending INTR and NMI is serviced after completion of RSM instruction execution Only one INTR and one NMI can be pending The SMM handler may choose to enable interrupts to take advantage of device drivers Since in terrupts were enabled while under control of the SMM handler the signal SMIACT co
599. supports 1200 through 19200 baud modems Typical modem settings are 14400 baud no parity 8 data bits and 1 stop bit 14400 8 1 To access the BBS use a terminal program to dial the telephone number given below for your area once you are connected respond to the system prompts During your first session enter your name and location The system operator will set up your access account within 24 hours At that time you can access the files on the BBS 503 264 7999 U S Canada Japan Asia Pacific up to 19 2 Kbaud 44 0 1793 432955 Europe NOTE If you have problems accessing the BBS use these settings for your modem 2400 N 8 1 Refer to your terminal software documentation for instructions on changing these settings 1 5 8 CompuServe Forums The CompuServe forums provide a means for you to gather information share discoveries and debate issues Type go intel for access For information about CompuServe access and service fees call CompuServe at 1 800 848 8199 U S or 614 529 1340 outside the U S 1 5 4 World Wide Web We offer a variety of information through the World Wide Web http www intel com Select Embedded Design Products from the Intel home page 1 6 TECHNICAL SUPPORT In the U S and Canada technical support representatives are available to answer your questions between 5 a m and 5 p m PST You can also fax your questions to us Please include your voice telephone number and indicate wh
600. t SerialWriteChar SIO 0 Char Out Real Protected Mode No changes required Fe KR IR AR IRR A IRR AIA ARR Kk Ck ko Kk k Kk void SerialWriteChar int Unit BYTE ch WORD TransmitPortAddr WORD StatusPortAddr Set Port base based on serial port used TransmitPortAddr Unit TBR1 TBRO StatusPortAddr Unit LSR1 LSRO Wait until buffer is empty while _GetEXRegByte StatusPortAddr amp SIO TX BUF EMPTY SetEXRegByte TransmitPortAddr ch SerialWriteChar Ck Kk Ck Kk Ck Kk A ke Kk Ck kk ko ke kk ko ko ke kk ek SerialWriteStr 11 38 intel ASYNCHRONOUS SERIAL UNIT Description Is a Polled serial port write function that waits forever or until all characters have been written to the serial port The NUL character N0 is used to indicate end of string Parameters Unit Unit number of the serial port 0 for SIO port 0 l tor SIO port Ti str Address of a zero terminated string to be transmitted Returns None Assumptions REMAPCFG register has Expanded I O space access enabled ESE bit set The processor Port pin are initialized separately Syntax define SIO 0 0 SerialWriteStr 510 0 HelloString Real Protected Mode No changes required K KR IR A A RRR kk k k A k k k k k k k k k k k k k k k void SerialWriteStr int Unit const char far str WORD TransmitPortAddr WORD StatusP
601. t 0 for SIO port 0 1 for SIO port 1 Mode Defines parity number of data bits number of stop bits Reference Serial Line Control register for various options ModemCntrl Defines the operation of the modem control lines BaudRate Specifies baud rate The baud divisor value is calculated based on clocking source and clock frequency The clocking frequency is set by calling the InitializeLibrary function ClockRate Specifies the serial port clocking rate for internal clocking CLK2 for external COMCLK Returns Error Codes E_INVAILD_DEVICE Unit number specifies a non existing device E_OK Initialized OK No error Assumptions SIOCFG Has already been configured for Clocking source and Modem control source REMAPCFG register has Expanded I O space access enabled ESE bit set The processor Port pin are initialized separately Real Protected Mode No changes required int InitSIO int Unit BYTE Mode BYTE ModemCntrl DWORD BaudRate DWORD BaudClkIn WORD SIOPortBase WORD BaudDivisor Check for valid unit if Unit 1 return E INVALID DEVICE Set Port base based on serial port used SIOPortBase Unit 5101 BASE 5100 BASE Initialized Serial Port registers Calculate the baud divisor value based on baud clocking BaudDivisor WORD BaudClkIn 16 BaudRate Turn on access to baud divisor register SetEXRegByte SIOPortBase LCR 0x80 Set the baud rate divisor register High byte fi
602. t sources depending upon the configuration programmed The master 82C59A module controls the slave 82C59A three internal interrupt sources and up to six external interrupt sources depending upon the configuration programmed When a device signals an interrupt request the interrupt control unit activates the processor s INTR input Interrupt acknowledge cycles are special bus cycles that enable the interrupt control unit to output a service routine vector onto the data bus The processor performs two back to back interrupt ac knowledge cycles in response to an active INTR input as long as the interrupt flag is enabled Interrupt acknowledge cycles are similar to regular bus cycles in that the processor initiates each bus cycle and an active READ Y terminates each bus cycle The cycles are shown in Figure 6 9 The sequence of signals for an interrupt acknowledge cycle is as follows 1 address and status signals are driven active and ADS is driven low to start each bus cycle e Status signals M IO D C and W R are low to indicate an interrupt acknowledge bus cycle These signals must be decoded to generate the INTA input signal for an external 82C59A if an external cascaded 82 59 is used The REFRESH signal is high e LOCK is active from the beginning of the first cycle to the end of the second HOLD requests from other bus masters are not recognized until after the second interrupt acknowledge cycle is completed e NA is
603. t be kept deasserted during the T2 states of BS8 memory cycles During the T2 state of a nonpipelined cycle if NA is sampled active one of four states occur Ifa bus cycle is internally pending in the processor and READY 15 returned inactive to the processor and the HOLD input is inactive then the address byte enables and bus status signals for the next bus cycle are driven and the processor bus unit enters a T2P state T2P states are repeated until the bus cycle is terminated Ifa bus cycle is internally pending in the processor and READY is returned active to the processor and the HOLD input is inactive then the address byte enables and bus status signals for the next bus cycle are driven and the processor bus unit enters a T1 nonpipelined state In effect the input is ignored in this case If READY is returned inactive and either a bus cycle is not internally pending or the HOLD input is active then the address and byte enables enter an unknown state the bus status signals go inactive and the processor bus unit enters a T2i state If the bus cycle is not terminated then the next state is either a T2P state or a T2i state depending on whether a bus cycle is pending f HOLD is asserted to the processor and READY is returned active then the Th state is entered from a T2 state regardless of whether an internal bus cycle is pending Figure 6 8 illustrates the effect of NA Figure 6 7 shows the full bus state
604. tandard Bus ISA Signals The address data and control signals along with the interrupt and DMA control signals do not directly conform to the PC AT ISA bus They more closely match the Intel386 SX processor local bus signals However you can easily construct a subset PC AT ISA bus from these signals or a combination of these signals For example the AEN signal is typically generated as shown in Figure B 1 in a PC AT compatible system B 2 intel COMPATIBILITY WITH THE PC AT ARCHITECTURE HLDA Processor MASTER From PC AT Bus A2504 01 Figure B 1 Derivation of AEN Signal in a Typical PC AT System For systems based on Inte1386 EX processor the AEN signal could be derived as shown in Figure B 2 Notice that since the DMA acknowledge signals are used instead of a generic HLDA there is no need to incorporate the REFRESH signal in the logic DACKO O Processor DACK1 MASTER From PC AT Bus A2503 01 Figure B 2 Derivation of AEN Signal for Intel386 EX processor based Systems In a PC AT system using the 8237A DMA controller in fly by mode the 8237A generates appro priate control signals for memory MEMR or MEMW and for I O IOW and IOR The Intel386 EX processor s internal DMA during fly by transfers generates control signals and W R that apply to the memory device There needs to be some external logic that can detect the DMA operation thro
605. target memory device for the DMA channel specified by nChannel PARAMETERS nChannel channel for which to set target address ptMemory pointer to target memory location Returns None Assumptions Processor is in real mode Syntax static char lpsz Hello World SetDMATargMemAddr DMA 10 1 2 Real Protected Mode The address calculation from ptMemory assumes the processor is in real mode 12 56 intel DMA CONTROLLER Fe KKK AR IRR A Kk Rok Ck Kk int SetDMAXferCount int nChannel DWORD lCount WORD addrDMABycO0 1 WORD addrDMAByc2 Check input if nChannel DMA 10 amp amp nChannel DMA 11 return ERR BADINPUT Set registers to correct channel addrDMABycO0 1 nChannel DMA 10 DMAOBYCO 1 DMAI1BYCO 1 addrDMAByc2 nChannel DMA_ChannelO DMAOBYC2 DMA1BYC2 SetEXRegByte DMACLRBP 0x0 Clear the byte pointer flip flop Write count bits 0 7 SetEXRegByte addrDMABycO 1 BYTE l1Count amp OxFF Write count bits 8 15 SetEXRegByte addrDMABycO 1 BYTE 1Count gt gt 8 amp OxFFE Write count bits 16 23 SetEXRegByte addrDMAByc2 BYTE 1Count gt gt 16 amp OxFF return ERR NONE RRR IK KKK IK KK IRR IR Kk k Kk Ck kk IR Kk KC A IR kk ke kk ko ko kk ke kk kk ke InitDMA Description Enables the DMA and initializes settings independe
606. te both bytes If you re using more than one subroutine to read or write a counter make sure that each subroutine reads or writes both bytes before transferring control You can program the counters for either an internal or external clock source to CLKINn The internal source is a prescaled value of the processor clock and therefore is turned off in the processor s powerdown mode processor clock is off If an external clock source is used it is not affected by the processor s powerdown mode because the clock signal is provided by an off chip source Controlling Power Management Modes on page 8 8 describes the processor s powerdown and idle modes 10 33 Intel386 EX EMBEDDED PROCESSOR USER S MANUAL intel With the readback command fboth the status and counter values are latched the user can read the value of the Read Write selection bits from the status register to know what bytes of the counter value are being latched in the TMRz register Ifonly the counter value is latched you must know the Read Write selection before the counter value can be read correctly e When a read back command is issued to latch both the counter and the status of a timer the TMR register holds both of these values The first read of TMR7 accesses the status byte and the next one or two reads depending on the R W format of TMR7 access the timer s counter value 10 4 1 Timer Counter Unit Code Examples The example code contains these
607. ted with the ICU consist of pin and signal configuration registers initializa tion command words ICWs operation command words 5 and status registers The configuration registers enable the external interrupt sources The ICWs initialize the 82C59As during system initialization The OCWs modify an 82C59 A s operation during program execution The status registers reflect pending and in service interrupts NOTE ICW2 ICW3 and ICW4 of an 82C594 are all at the same address Therefore a programming sequence must be followed to program these registers The first access goes to ICW2 the second to ICW3 and the third to ICW4 When programming any of these registers the above sequence must be followed and completed every time When initializing the ICU write first to ICWI then to ICW2 ICW3 and ICWA in order Table 9 2 describes these registers and the following sections contain bit descriptions for each register 9 15 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Table 9 2 ICU Registers Sheet 1 of 2 Expanded PC AT Function Register Address Address P3CFG 0 824 Port 3 Configuration read write The INT3 0 signals are multiplexed with P3 5 2 This register determines which signals are connected to the package pins When a P3 n signal rather than an INTn signal is connected to a package pin is connected to the master s IRn signal IN
608. ter eee Field For the loading and storing of the Control Debug and Test registers Table E 13 When Interpreted as Control Register Field eee Code Reg Name 000 CRO 010 CR2 011 NOTE Do use any other encoding Table E 14 When Interpreted as Debug Register Field eee Code Reg Name 000 DRO 001 DR1 010 DR2 011 DR3 110 DR6 111 DR7 NOTE Do notuse any other encoding Table E 15 When Interpreted as Test Register Field eee Code Reg Name 110 TR6 111 TR7 NOTE Do notuse any other encoding E 31 intel GLOSSARY intel GLOSSARY This glossary defines acronyms abbreviations and terms that have special meaning in this man ual Chapter 1 GUIDE TO THIS MANUAL discusses notational conventions Assert BIOS BIU Boundary scan CSU Clear Deassert DMA DOS Address Space The act of making a signal active enabled The polarity high low is defined by the signal name Active low signals are designated by a pound symbol suffix active high signals have no suffix To assert RD is to drive it low to assert HLDA is to drive it high Basic input output system The interface between the hardware and the operating system Bus interface unit The internal peripheral that controls the external bus The term boundary scan refers to the ability to scan observe the signals at the boundary the pins of a device A major compo
609. ter short form 01011 reg 6 6 b h segment register ES 7 25 b h i j CS SS or DS 000 sreg2 11 short form segment register ES ri 25 b h i j CS SS or DS FS or 0000111 10 sreg3 001 GS POPA Pop all 0110000 29 35 b h XCHG Exchange register memory 3 5 3 5 b f fh with register 1000011w modreg r m register with accumula 3 3 tor short form 10010 reg Clk Count Virtual IN Input from 8086 Mode fixed po 1110010w port number 127 14 8 29 s t m variable port 110110w 128 15 9 29 s t m OUT Output to fixed port 1110011w port number 127 14 8 29 s t m variable port 110111w 128 15 9 29 s t m ed Load EA to regis 000110 mod reg r m 2 2 SEGMENT CONTROL ord Load pointer to 100010 mod reg r m T 26 28 b h i Load pointer to 1000100 mod reg r m 7 26 28 b h i pr PPM pointerto 00001111 10110100 mod reg r m LA 29 31 b h i LGS Loadpointerto 00001111 10110101 mod reg r m 26 28 b h i 188 Load pointerto 00001111 10110010 mod reg rim LE p nd FLAG CONTROL CLC Clear carry flag 11111000 2 2 E 3 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Table E 1 Instruction Set Summary Sheet 3 of 19 In tel Clock Count Notes Real Pro Real Pro Ad tected Ad tected Instruction Format dress Virtual dress Virtual
610. ter value GetWDT Count Real Protected Mode No changes required eK RR A A ARR Kk Ck kk DWORD GetWDT Count void WORD LowWord HiWord LowWord GetEXRegWord WDTCNTL HiWord GetEXRegWord WDTCNTH return DWORD HiWord lt lt 16 LowWord GetWDT Count BRK KK KKK I KK Kk A k KR IR AR IRR IA Kk k CK Ck KC Kk k k Kk k k k k ke kk ko k k k k ke ke k k k k k WDT BusMonitor Description Enables the bus monitor mode of the Watch Dog Timer Parameters EnableDisable Nonzero if bus monitor mode is to be enabled Zero if it is to be disabled Returns None Assumptions None Syntax define Enable 0x01 define Disable 0x00 17 14 intel WATCHDOG TIMER UNIT WDT BusMonitor Enable Real Protected Mode No changes required eK RR KR IR RRR RR IIR AR ARR Kk Ck kk Ck AR void WDT_BusMonitor BYTE EnableDisable BYTE Status Status _GetEXRegByte WDTSTATUS if EnableDisable If true Enable SetEXRegByte WDTSTATUS Status 5 Set Bit else else Disable SetEXRegByte WDTSTATUS Status amp BITIMSK Clear Bit WDT BusMonitor RR Kk A ke KR Kk Ck Ck Kk k Kk kk Ck Ck Kk k CK Ck Ck IA IIR kk k kk kk kk k k k k eek EnableWDTInterrupt Description Enables a maskable interrupt on the assertion of WDTOUT Parameters None Returns None Assumptions None Syntax Enab
611. termines which register is accessed 2 Shaded rows indicate reserved areas intel Table 4 2 Peripheral Register Addresses Sheet 3 of 6 SYSTEM REGISTER ORGANIZATION pss Register Reset Value F08DH Reserved FO8EH Reserved FO8FH Reserved F098H Byte DMAOBYC2 XX F099H Byte DMA1BYC2 XX F09AH Reserved FO9BH Reserved A20GATE and Fast CPU Reset F092H 0092H Byte PORT92 XXXXXX10B Slave Interrupt Controller FOAOH 00A0H Byte ICW1s IRRs ISRs XX OCW2s OCW3s FOA1H 00 1 ICW2s ICW3s ICWAs XX OCW1s POLLs Chip select Unit F400H Word CSOADL 0000H F402H Word CSOADH 0000H F404H Word CSOMSKL 0000H F406H Word CSOMSKH 0000H F408H Word CS1ADL 0000H F40AH Word CS1ADH 0000H F40CH Word CS1MSKL 0000H F40EH Word CS1MSKH 0000H F410H Word CS2ADL 0000H F412H Word CS2ADH 0000H F414H Word CS2MSKL 0000H F416H Word CS2MSKH 0000H F418H Word CS3ADL 0000H F41AH Word CS3ADH 0000H F41CH Word CS3MSKL 0000H F41EH Word CS3MSKH 0000H F420H Word CS4ADL 0000H F422H Word CS4ADH 0000H NOTES 1 Byte pointer in flip flop in DMA determines which register is accessed 2 Shaded rows indicate reserved areas Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL Table 4 2 Peripheral Register Addresses Sheet 4 of 6 intel
612. tform Using PC compatible peripherals also allows for the development and debugging of application software on a standard PC platform Typical applications using the Intel386 EX processor include automated manufacturing equip ment cellular telephones telecommunications equipment fax machines hand held data loggers high precision industrial flow controllers interactive television medical equipment modems and smart copiers This chapter is organized as follows ntel386 EX Embedded Processor Core see below Integrated Peripherals page 2 3 2 1 Intel386 EX EMBEDDED PROCESSOR CORE The Intel386 EX processor contains a modular fully static Intel386 CX central processing unit CPU The Intel386 CX processor is an enhanced Intel386 SX processor with the addition of System Management Mode SMM and two additional address lines The Intel386 EX processor has a 16 bit data bus and a 26 bit address bus supporting up to 64 Mbytes of memory address space and 64 Kbytes of I O address space The performance of the Intel386 EX processor closely reflects the Intel386 SX CPU performance at the same speeds Chapter 3 OVERVIEW describes differences between the Intel386 EX processor core and the Intel386 SX processor Please refer to the Intel386 SX Microprocessor Programmer s Reference Manual order number 240331 for applications and system programming informa tion descriptions of protected real and virtual 8086 modes and d
613. th other SIO registers Bit 7 DLAB of LCRn must be set in order to access the divisor latch registers If DLL DLH 00H baud rate generator ouput frequency 0 stops clock Figure 11 12 Divisor Latch Registers DLLn and DLHn 11 22 intel ASYNCHRONOUS SERIAL UNIT 11 3 4 Transmit Buffer Register TBRn Write the data words to be transmitted to Use the interrupt control or units or poll the serial line status register LSRn to determine whether the transmit buffer is empty Transmit Buffer TBRO TBR1 TBRO TBR1 Expanded Addr F4F8H F8F8H write only ISA Addr O3F8H 02 8 Reset State XXH XXH 7 0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TBO Bit Bit Number Mnemonic Function 7 0 7 0 Transmit Buffer Bits These bits make up the next data word to be transmitted The transmitter loads this word into the transmit shift register The transmit shift register then shifts the bits out along with the asynchronous communication bits start stop and parity The data bits are shifted out least significant bit TBO first NOTE The transmit buffer register shares an address port with other SIO registers You must clear bit 7 DLAB of LCRn before you can write to the transmit buffer register Figure 11 13 Transmit Buffer Register TBRn 11 23 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 11 3 5 Receive Buffer Register RBRn
614. the assertion of an interrupt request at one of the IR signals During system initialization you can program the IR signals as a group to be either edge or level triggered using ICW1 described in Figure 9 8 Edge triggered The 82C59A recognizes a rising edge transition on an IR signal as an interrupt request A device requesting service must maintain a high state on an IR signal until after the falling edge of the first INTA pulse You can reset the edge detection circuit during initialization of the 82C59A or by deasserting the IR signal To reset the edge detection circuit properly the interrupt source must hold the IR line low for a minimum time of 10 9 29 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Level triggered The 82C59A recognizes a high level on an IR line as an interrupt request A device must maintain the high level until after the falling edge of the first INTA pulse Unlike an edge triggered IR signal a level triggered IR signal continues to generate interrupts as long as it is asserted To avoid continuous interrupts from the same source a device must deassert a level sensitive IR signal before the interrupt handler issues an end of interrupt EOI command All internal peripherals interface with their respective 82C59As in edge triggered mode This is compatible with the PC AT bus specification Each source signal initiates an interrupt by making a low to high transition 9 4 3 Spurious Interrupt
615. the other allows word transfers However the 8237A has two major restrictions Ithas only 16 bit addressing capability This requires a page register to allow address extension for a system based on a processor like the Intel386 EX processor with 26 bit 64 Mbyte physical memory addressing capability A page register implementation is cumbersome and degrades the system performance The 8237A has no natural two cycle data transfer mode to allow memory to memory transfers Instead two DMA channels have to be used in a very specific manner Transferring data between memory and memory mapped I O devices common in embedded applications would not be easy 1 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel To eliminate these problems with an 8237A DMA controller the Intel386 EX processor inte grates a DMA controller unit that differs from the 8237A DMA in these ways t provides two channels each capable of either byte or word transfers Eachchannel can transfer data between any combination of memory and I O The Bus Interface Unit supports both external fly by and two cycle operation For programming compatibility the internal DMA unit preserves all of the 8 bit registers of the 8237A The 8237 A s command register bits that affect two channel memory to memory transfers compressed timing and DREQ DACK signal polarity selection are not supported by the internal DMA The internal DMA uses 26 bit address re
616. the package pin PM5 Pin Mode 0 Selects P1 5 at the package pin 1 Selects LOCK at the package pin PM4 Pin Mode 0 Selects P1 4 at the package pin 1 Selects RIO at the package pin 0 Selects P1 3 at the package pin 1 Selects DSRO at the package pin PM2 Pin Mode 0 Selects P1 2 at the package pin 1 Selects DTRO at the package pin 1 0 Selects 1 1 at the package 1 Selects RTSO at the package PMO Pin Mode 0 Selects P1 0 at the package pin 1 Selects DCDO at the package pin Figure 5 16 Port 1 Configuration Register P1CFG 5 25 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Port 2 Configuration Expanded Addr F822H P2CFG ISA Addr read write Reset State 00H 7 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PMO Bit Bit Function Number Mnemonic 7 PM7 Pin Mode 0 Selects P2 7 at the package pin 1 Selects 50 at the package pin 6 PM6 Pin Mode 0 Selects P2 6 at the package pin 1 Selects TXDO at the package pin 5 PM5 Pin Mode 0 Selects P2 5 at the package pin 1 Selects RXDO at the package pin 4 PM4 Pin Mode 0 Selects P2 4 at the package pin 1 Selects CS4 at the package pin 3 PM3 Pin Mode 0 Selects P2 3 at the package pin 1 Selects CS3 at the p
617. the two internal timing signals PH1 and PH2 With a 50 MHz external clock one state time equals 80 ns Because the device can operate at many frequencies this manual defines time requirements in terms of state times rather than in specific units of time Test access port The dedicated input and output pins through which a tester communicates with the fest logic unit A major component of the JTAG standard Timer counter unit The internal peripheral that provides three independent 16 bit down counters The module that facilitates testing of the device logic and interconnections between the device and the board This module is fully compliant with IEEE Standard 1149 1 commonly called the JTAG standard Universal asynchronous receiver and transmitter A part of the SIO unit Watchdog timer An internal 32 bit down counter that can operate as a general purpose timer a software watchdog timer or a bus monitor Glossary 5 intel Index intel defined 1 3 82C59A 9 1 A Address bus 6 1 Address lines new 3 1 Address space configuration register 4 6 expanded I O 4 3 enabling disabling 4 8 I O decoding techniques 4 6 I O for PC AT systems 4 2 peripheral registers 4 15 Addressing modes 4 9 4 14 DOS compatible mode 4 9 4 10 enhanced DOS mode 4 11 4 13 nonDOS mode 4 11 4 14 nonintrusive DOS mode 4 11 4 12 AEN signal deriving B 2 B 3 AEOI mode 9 9 aligned data transfers 6 9 Applications typi
618. these software routines ReLoadDownCounter Initiates a lockout sequence GetWDT Count Reads the value of the counter WDT BusMonitor Places the WDT in Bus Monitor Mode EnableWDTInterrupt Enables WDT interrupts 17 12 intel See Appendix C for included header files include include include include lt dos h gt lt conio h gt 80386ex h ev386ex h WATCHDOG TIMER UNIT KC k k KC A IIR kk ke kk kk kk kk k k ek ReLoadDownCounter Description This function initiates a lockout sequence which results in the setting of the WDTEN bit in the status register WDTEN Parameters None Returns None Assumptions None Syntax ReloadDownCounter Real Protected Mode No changes required the software watchdog mode is enabled By setting Ck CK Ck Ck kk Ck k Kk k Kk k Kk k k void ReLoadDownCounter void _disable SetEXRegWord WDTCLR 0xf01e SetEXRegWord WDTCLR Oxfel enable ReLoadDownCounter Disable interrupts Enable interrupts GetWDT Count Description Returns current value of watch dog counter 17 13 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Parameters None Returns 16 bit down counter value Assumptions None Syntax WORD counter value coun
619. through g apply to Real Address Mode and Protected Virtual Address Mode d The Intel386 SX CPU uses an early out multiply algorithm The actual number of clocks depends the position of the most significant bit in the operand multiplier Clock counts given are minimum to maximum To calculate actual clocks use this formula Actual Clock if m lt gt 0 then max log m 3 b clocks if m 0 then 3 b clocks In this formula m is the multiplier and b 9 for register to register b 12 for memory to register E 20 tel INSTRUCTION SET SUMMARY b 10 for register with immediate to register b 11 for memory with immediate to register An exception may occur depending on the value of the operand LOCK is automatically asserted regardless of the presence or absence of the LOCK prefix LOCK is asserted during descriptor table accesses Notes h through r apply to Protected Virtual Address Mode only h Exception 13 fault general protection violation will occur if the memory operand in CS DS ES FS or GS cannot be used due to either a segment limit violation or access rights violation If a stack limit is violated an exception 12 stack segment limit violation or not present occurs For segment load operations the CPL RPL and DPL must agree with the privilege rules to avoid an exception 13 fault general protection violation The segment s descriptor must indicate present or exception 11 CS
620. time that the master 82C59A presents an interrupt request to the CPU and the time that the interrupt acknowledge cycle begins intel Interrupt Response Time Interrupt Resolution ISR JTAG Level sensitive LSB NonDOS Mode Nonintrusive DOS Mode Normally not ready GLOSSARY The amount of time required to complete an interrupt acknowledge cycle and transfer program control to the interrupt service routine The delay between the time that the interrupt controller receives an interrupt request and the time that the master 82C59A presents the request to the CPU Interrupt service routine A user supplied software routine designed to service specific interrupt requests Joint Test Action Group The IEEE technical subcommittee that developed the testability standard published as Standard 1149 1 1990 IEEE Standard Test Access Port and Boundary Scan Architecture and its supplement Standard 1149 1a 1993 The test logic unit is fully compliant with this standard The mode in which the interrupt controller recognizes a high level logic one on an interrupt request signal as an interrupt request Unlike an edge trig gered interrupt request a level sensitive interrupt request will continue to generate interrupts as long as it is asserted Least significant bit of a byte or least significant byte of a word The addressing mode in which the internal timer interrupt controller serial I O ports and DMA controller a
621. ting To specify a count write to the counter s TMRz regis ter s write format In modes 0 and 4 the count is loaded on the falling edge of CLKINn Modes 1 and 5 require a rising edge on a counter s GATEn signal or gate trigger to load the count In modes 2 and 3 the count is loaded when the counter reaches terminal count or when the counter receives a gate trigger whichever is first The GATEn signal affects the counting operation for each mode differently Table 10 3 For modes 0 2 3 and 4 GATEn is level sensitive and the logic level is sampled on the rising edge of CLKINn The action then occurs on the falling edge of the next CLKINn In these modes GATEn must be high for counting to begin During a counting sequence a low level at GATEn suspends counting while a high level at GATEz resumes counting For modes 1 2 3 and 5 GATEn is rising edge sensitive In these modes a rising edge at GATEn sets an edge sensitive flip flop in the counter This flip flop is then sampled on the next rising edge of CLKINn the flip flop is reset immediately after it is sampled In this way a trigger is detected no matter when it occurs a high level does not have to be maintained until the next ris ing edge of CLKINn Therefore a rising edge on GATEn that occurs between two rising CLKINn edges is recognized as a gate trigger The operation caused by a gate trigger occurs on the falling CLKINn edge following the trigger Note that in modes 2 and
622. tion 0 Connects to the slave IR6 signal 1 Connects the INT7 pin to the slave IR6 signal 2 IR5 IR4 Internal Slave IR4 or IR5 Connection These depend on whether INTCFG 4 is set or clear 0 Connects to the slave IR5 signal 1 Connects either the INT6 pin or DMAINT to the slave IR5 signal 1 IR1 Internal Slave IR1 Connection 0 Connects the SSIO interrupt signal SSIOINT to the slave IR1 signal 1 Connects the INT5 pin to the slave IR1 signal 0 IRO Internal Slave IRO Connection 0 Connects Vas to the slave IRO signal 1 Connects the INT4 pin to the slave IRO signal Figure 5 5 Interrupt Configuration Register INTCFG intel DEVICE CONFIGURATION 5 2 3 Timer counter Unit Configuration The three channel Timer counter Unit TCU and its configuration register TMRCFG are shown in Figure 5 6 and Figure 5 7 The clock inputs can be external signals TMRCLK2 0 or the on chip programmable clock PSCLK All clock inputs can be held low by programming bits in the TMRCFG register The gate inputs can be controlled through software using TMRCFG 6 and the appropriate GInCON bits in the TMRCFG register Several of the timer signals go to the interrupt control unit see Figure 5 4 Timer counterO and Timer counter signals are selected individually In contrast the Tim er counter2 signals TMRCLK2 TMRGATE2 TMROUT2 are selected as a group Note that us ing the Timer counter2 signals pr
623. tion Command Word 2 master slave OCW2 master and slave Expanded Addr F020H write only ISA Addr 0020H Reset State XXH XXH 7 0 R SL EOI RSEL1 RSELO L2 L1 LO Bit Bit Number Mnemonic Function R The Rotate R Specific Level SL and End of Interrupt EOI Bits SL These bits change the priority structure and or send an EOI command EOI R SLEOI Command 000 Cancel automatic rotation 001 Send a nonspecific command 010 011 Send specific EOI command 100 Enable automatic rotation 1 0 1 Enable automatic rotation and send a nonspecific EOI 110 Initiate specific rotation 1 1 1 Initiate specific rotation and send a specific EOI These cases allow you to change the priority structure while the 82C59A is operating in the automatic EOI mode L2 0 bits see below specify the specific level for these cases 4 3 RSEL1 0 Register Select Bits ICW1 OCW2 and OCWS are accessed through the same addresses The states of RSEL1 0 determine which register is accessed Write 00 to these bits to access OCW2 RSEL1 RSELO 0 0 OCW2 0 1 OCWS 1 X ICW1 2 0 L2 0 IR Level When you program bits 7 5 to initiate specific rotation these bits specify the IR signal that is assigned the lowest level When you program bits 7 5 to send a specific EOI command these bits specify the IR signal that receives the EOI command If SL 0 then these bits have no effect 9 26 Figure 9 14 Ope
624. tions Figure 5 18 Port 3 Configuration Register P3CFG 5 27 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 5 4 DEVICE CONFIGURATION PROCEDURE Before configuring the microprocessor make the following selections The set of peripherals to be used The signals to be available at the package pins The desired peripheral peripheral and peripheral core connections Although final decisions regarding these selections may be influenced by the possible configura tions we recommend that you initially make the selections without regard to limitations on the configurations We suggest the following procedure for configuring the device for your design An aide for re cording the steps in the procedure and an example configuration are given in Configuration Ex ample on page 5 28 1 Pin Configuration For each desired pin signal consult the peripheral configuration diagram to find the bit value in the pin configuration register that connects the signal to a device pin When the signal shares a pin that has no multiplexer make a note of its companion signal 2 Peripheral Configuration For each peripheral in your design consult the peripheral configuration diagram and the peripheral configuration register to find the bit values for your desired internal connections 3 Configuration Review Review the results of steps 1 and 2 to see if the configuration registers have conflicting bit values If conflicts
625. to check the status of the transmitter and receiver Serial Line Status LSRO LSR1 LSRO LSR1 Expanded Addr F4FDH F8FDH read only ISA Addr OS3FDH 02FDH Reset State 60H 60H 7 0 TE TBE BI FE PE OE RBF Bit Bit i Number Mnemonic Function Reserved This bit is undefined TE Transmitter Empty The transmitter sets this bit to indicate that the transmit shift register and transmit buffer register are both empty Writing to the transmit buffer register clears this bit 5 TBE Transmit Buffer Empty The transmitter sets this bit after it transfers data from the transmit buffer to the transmit shift register Writing to the transmit buffer register clears this bit 4 BI Break Interrupt The receiver sets this bit whenever the received data input is held in the spacing logic 0 state for longer than a full word transmission time Reading the receive buffer register or the serial line status register clears this bit 3 FE Framing Error The receiver sets this bit to indicate that the received character did not have a valid stop bit Reading the receive buffer register or the serial line status register clears this bit If data frame is set for two stop bits the second stop bit is ignored 2 PE Parity Error The receiver sets this bit to indicate that the received data character did not have the correct parity Reading the receive buffer register or the serial line status r
626. transferred to the shift reg ister and the THBE bit is set In this mode the TEN bit is ignored Once the data is transferred to the shift register the word is shifted out If no new data has been written into the buffer the trans mitter stops The Transmit Underrun Error TUE bit is not used in Autotransmit mode The Autotransmit mode eliminates the problem of controlling the TEN bit during high speed data transfers using polling or interrupts to move new data to the transmit buffer SSIOTBUF 13 2 2 3 Slave Mode Operation in transmitter slave mode is similar to master mode except the transmitter is clocked from the STXCLK pin When the transmitter is enabled any time during the STXCLK clock cy cle TB15 appears on the SSIOTX pin and remains on the pin until the second falling edge of STXCLK 13 2 3 Receiver The receiver contains a 16 bit holding buffer and a 16 bit shift register When enabled the shift register shifts data in via the SSIORX pin After the receiver shifts in 16 bits of data the contents of the shift register are transferred to the buffer Either the internal baud rate generator master mode or an input signal on the SRXCLK pin slave mode can clock the receiver The receiver contains a receive holding buffer full flag RHBF and a receive overflow error flag ROE At reset RHBF is clear indicating that the buffer is empty When the receiver transfers data from the shift register to the buffer RHBF is set Rea
627. ts in service bit and puts its interrupt vector number on the bus The CPU uses its operating mode and the interrupt vector number to find the interrupt service routine s address The CPU processes the interrupt Interrupt routine sends an EOI command to the slave clearing its IR2 in service bit Does slave have Interrupt routine sends an other command to the master rti bits clearing its IR2 in service bit set An interrupt return instruction is issued ending the interrupt process Figure 9 5 Interrupt Process Master Request from Slave Source A2429 02 9 13 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel The interrupt s priority structure determines which EOI command should be used Use the spe cific EOI command for the special mask mode In this mode a lower level interrupt can interrupt the processing of a higher level interrupt The specific EOI command is necessary because it al lows you to specifically clear the lower level in service bit The fully nested mode allows only interrupts of higher levels to interrupt the processing of a low er level interrupt In this mode the nonspecific EOI command automatically clears the in service bit for the current process because it has the highest level Special fully nested mode allows equal or higher level requests to interrupt the processing of oth er interrupts For this mode the nonspecific EOI command automatically clears the appropr
628. uctions shifting information toward TDO scanning pins and pausing to allow time for the tester to perform other operations The TAP controller changes state only in response to the assertion of the test reset input TRST or the state of the mode select pin TMS on the rising edge of TCK TRST causes the TAP con troller to enter its test logic reset state and the state of TMS on the rising edge of TCK controls the subsequent states Table 18 2 describes the states and Figure 18 2 illustrates how the TAP state machine moves from one state to another Table 18 2 TAP Controller State Descriptions Sheet 1 of 2 Next State State Description on TCK Rising Edge TMS 0 TMS 1 Resets the test logic unit and forces the IDCODE instruction into the instruction register In Test Logic Reset components that have no IDCODE instruction the Run Test Idle Test Logic Reset BYPASS instruction is loaded instead Test logic is disabled the device is in normal operating mode Run Test Idle Executes a test or disables the test logic Run Test ldle Select DR Scan Selects the data register to be placed in the serial Selec DR Scan path between TDI and TDO Capture DR Select IR Scan Parallel loads data into the active data register if Capture DR necessary Otherwise the active register retains its Shift DR Exit1 DR previous state Shift DR in stagetoward Shift DR Exit1 DR Exit1 DR
629. uffer transfer mode for the channel specified by bit 0 1 Enables the autoinitialize buffer transfer mode for the channel specified by bit 0 3 2 TD1 0 Transfer Direction Determines the transfer direction for the channel specified by bit 0 00 Target is read nothing is written used for testing 01 Data is transferred from the requester to the target 10 Data is transferred from the target to the requester 11 Reserved Note In cascade mode these bits become don t cares 1 0 Must be 0 for correct operation 0 CS Channel Select 0 The selections for bits 7 2 affect channel 0 1 The selections for bits 7 2 affect channel 1 D 21 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel D 17 DMAMOD2 DMA Mode 2 Expanded Addr F01BH DMAMOD2 ISA Addr write only Reset State 00H 7 0 BCO RD TD RH RI TH 0 CS Bit Bit Number Mnemonic Function 7 BCO Bus Cycle Option 0 Selects the fly by data transfer bus cycle option for the channel specified by bit 0 1 Selects the two cycle data transfer bus cycle option for the channel specified by bit 0 6 RD Requester Device Type 0 Clear this bit when the requester for the channel specified by bit 0 is in memory space 1 Setthis bit when the requester for the channel specified by bit 0 is in I O space This bit is ignored if BCO is cleared 5 TD Target Device Type 0 Clea
630. ugh the AEN signal and generate a complementary I O cycle For ex ample if the DMA is generating a memory read cycle and AEN is active then the logic should drive the IOW signal on the PC AT bus Actually the internal DMA could be programmed in a two cycle mode eliminating the need for external logic This will not have a significant impact onthe performance of the two cycles required to complete the transfer the I O cycle is the long one meeting PC AT timings while the memory cycle is relatively very quick The drive capability and the operating frequency of the Intel386 EX processor signals are differ ent from the standard PC AT bus which requires 24 mA drive capacity at 200 pF capacitive load Most PC AT systems presently operate in a quiet bus mode so that non ISA cycles are not re flected on the ISA bus In a typical implementation the address data buses may change states but the control signals are not strobed if a non IS A cycle is detected External three state buffers and some decoding logic are needed to implement this scheme The EV386EX evaluation board for B 3 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel the Intel386 EX embedded processor demonstrates the design of a Synchronous Expansion Bus that is very similar to the ISA bus The Intel386 EX processor is not capable of providing a 10096 compatible ISA bus due to its lack of DMA channels and interrupt inputs B 1 3 Interrupt Control Unit I
631. uing dummy read cy cles at specified intervals For more information refer to Chapter 15 REFRESH CONTROL UNIT Figure 6 11 shows a basic refresh cycle The sequence of signals for a refresh cycle is as follows 1 Like a read cycle the refresh cycle is initiated by asserting ADS and completed by asserting READY The address and status pins are driven to the following values M IO and D C are driven high and W R and REFRESH are driven low to indicate a memory refresh Address lines are driven to the current refresh address the value in the Refresh Address Counter in the Refresh Control Unit while the BHE and BLE are driven high 2 complete the refresh cycle either READY must be asserted externally or the chip select unit must be programmed to generate READ Y for the address region specified in the Refresh Address Base Register in the refresh control unit The refresh control unit then relinquishes control to the current internal bus master until the next refresh cycle is needed During hold acknowledge cycles with the HLDA pin active a refresh request causes the internal bus arbiter to deassert the HLDA pin The processor then waits for the HOLD pin to be deasserted for at least one processor clock cycle Once HOLD is deasserted the processor begins the refresh cycle Figure 6 12 shows a refresh cycle during a HOLD HLDA condition NOTE BS8 is ignored during refresh cycles It has no effect on a refresh c
632. uitry TDI Test Data Input Serial input for test instructions and data Sampled on the rising edge of TCK valid only when either the instruction register or a data register is being serially loaded SHIFT IR SHIFT DR TDO Test Data Output Serial output for test instructions and data TDO shifts out the contents of the instruction register or the selected data register LSB first on the falling edge of TCK If serial shifting is not taking place TDO floats TMS Test Mode Select Input Controls the sequence of the TAP controller s states Sampled on the rising edge of TCK TRST Test Reset Input Resets the TAP controller Asynchronously clears the data registers and initializes the instruction register to 0010 the IDCODE instruction opcode NOTE The JTAG Test Logic Unit must be reset upon power up using the TRST pin If this is not done the processor may power up with the JTAG test logic unit in control of the device pins and the system does not initialize properly 18 3 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 18 2 2 Test Access Port TAP Controller The TAP controller is a finite state machine that is capable of 16 states Figure 18 2 Three of its states provide the basic actions required for testing Applying stimulus update data register Executing a test run test idle Capturing the response capture data register Its remaining states support loading instr
633. unt A2395 02 Figure 10 4 Mode 0 Writing a New Count 10 2 2 Mode 1 Hardware Retriggerable One shot This mode is similar to mode 0 it allows you to generate a rising edge on a counter s OUTn sig nal Unlike mode 0 however the counter waits for a gate trigger before loading the count and driving its OUTn signal low When the counter reaches zero OUTn is driven high At this point the counter rolls over and continues counting with OUT high OUT stays high and keeps count ing down and rolling over until the counter receives another gate trigger or you reprogram it You can retrigger the one shot at any time with a gate trigger causing the counter to reload the count and drive OUTn low Writing a new control word to the counter reprograms it Mode 1 s basic operation is outlined below and shown in Figure 10 5 1 After a control word write OUTn is driven high 2 the CLKINnz pulse following a gate trigger the count is loaded and OUT is driven low On each succeeding CLKINnz pulse the count is decremented 4 When the count reaches zero OUTn is driven high NOTE Writing a count of N causes a rising edge on OUTn in N CLKIN pulses after the count is loaded using a gate trigger 10 8 intel TIMER COUNTER UNIT Control Word 12H Count 3 Writes to Counter n CLKINn GATEn OUTn A2312 02 Figure 10 5 Mode 1 Basic Operation Figure 10 6 shows retriggerin
634. unt ex pires the buffer transfer is terminated NOTE Since the buffer transfer is complete when the byte count reaches FFFFFFH the number of bytes transferred is the byte count 1 12 2 2 Bus Cycle Options for Data Transfers There are two bus cycle options for transferring data fly by and two cycle Fly by allows data to be transferred in one bus cycle It requires that the requester be in external I O and the target be in memory The two cycle option allows data to be transferred between any combination of mem ory and I O through the use of a four byte temporary buffer 12 2 2 1 Fly By Mode The fly by option performs either a memory write or a memory read bus cycle A write cycle transfers data from the requester to the target memory and a read cycle transfers data from the target memory to the requester When a data transfer is initiated the DMA places the memory address of the target on the bus and selects the requester by asserting the DACKn signal The requester then either deposits the transfer data on the data bus or fetches the transfer data off the 12 5 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel data bus depending on the transfer direction Since the requester is selected via the DACKni sig nal the requester address is not meaningful in a fly by mode transfer Support logic either external or built in to the I O device must be designed to monitor the DACKntt signal and accordingly generat
635. upt driven Serial Writes break case 2 RBF signal Service RBF Routine specific to RBF generated interrupts break case 3 receive line status signal lsr0 GetEXRegByte LSRO if 1sr0 amp 0x10 break interrupt if 15 0 0x08 1 framing error if 15 0 amp 0x04 parity error J if 15 0 amp 0x02 overrun error break End of switch NonSpecificEOI Send End Of Interrupt Signal to Master SerialO ISR 11 42 intel ASYNCHRONOUS SERIAL UNIT BRK KK KKK IK KK e e RRR IRR IR AR IRR IR IR IRR A IR I IA k k k k k k k Service_RBF Description Service routine for interrupts generated by RBF signal This routine is used for Interrupt Driven Serial Reads It echoes the typed character to the screen stopping when it receives an ESC character Parameters None Returns None Assumptions None Syntax Not called by user Real Protected Mode No changes required eK RR AR IK RR IRR Ck A ARR IIR Kk KC IRR void Service_RBF void Read in contents of RBRO rec buffer GetEXRegByte RBRO SerialWriteChar SIO 0 rec buffer Echo to screen if rec buffer Oxlb ESC character received disable RBF interrupts SetEXRegByte IERO 0x00 Service RBF IRR Kk Ck Kk k CK Ck KC Kk Ck IR kk ke kk kk kk k k k k eek SerialWriteStr Int 11 43 Intel386
636. upts ICU initialization Interrupt Service Routine etc 3 Unmask the interrupts on the ICU 13 8 intel SYNCHRONOUS SERIAL I O UNIT Write Data to Buffer SSIOTBUF No Yes Enable Transmitter TEN 1 Yes x o Delay To Allow Transmitter To Shift First Bit Out Disable Transmitter 0 o Yes Error Routine A3394 01 Figure 13 8 Transmit Data by Polling 13 9 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel SSIO Transmitter Causes Interrupt Disable Interrupts While Transmitting Data Error Routine Write Data to Buffer SSIOTBUF Enable Transmitter TEN 1 Delay To Allow Transmitter To Shift First Bit Out Disable Transmitter TEN 0 Enable Interrupts Exit Interrupt Service Routine Figure 13 9 Interrupt Service Routine for Transmitting Data Using Interrupts A3398 01 13 10 intel SYNCHRONOUS SERIAL I O UNIT Ifthe transmitter is disabled while a data value in the shift register is being shifted out it continues running until the last bit is shifted out Then the shift register stops and the data and clock pins SSIOTX and STXCLK are three stated the contents of the buffer register are not loaded into the shift register If the transmitter is disabled then re enabled before the current value has been shifted out it con tinues as if it were never disabled If you enable the transmitt
637. upts range from 32 to 255 Because the base vector number must reside on an 8 byte boundary the valid base vector numbers are 32 n x 8 where 0 n 27 Write the base interrupt vector s five most significant bits to ICW2 s five most significant bits The 82C594A de termines specific IR signal vector numbers by adding the number of the IR signal to the base in terrupt vector Initialization Command Word 2 master slave ICW2 master and slave Expanded Addr F021H FOA1H write only ISA Addr 0021H 00A1H Reset State XXH XXH 7 0 T7 T6 T5 T4 T3 0 0 0 Bit Bit Number Mnemonic Function 7 3 7 3 Base Interrupt Type Write the base interrupt vector s five most significant bits to these bits 2 0 T2 0 Clear these bits to guarantee device operation Figure 9 9 Initialization Command Word 2 Register ICW2 9 21 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 9 3 5 Initialization Command Word 3 ICW3 The ICW3 register contains information about the master slave connections For this reason the functions of the master s ICW3 and the slave s ICW3 differ ICW3 at 0F021H or 0021H is the master s cascade configuration register Figure 9 11 The master has an internal slave cascaded from its IR2 signal You can cascade additional slaves from the master s IR7 IR6 IR5 IRA IR3 and IRI signals Setting a bit indicates that a slave 82C59A is cascaded from
638. v 11 2 Maximum and Minimum Output Bit Rates d uns ep 11 5 11 3 Divisor Values for Common Bit 11 5 11 4 Status Signal Priorities and eee 11 13 11 5 SIO Registers iot e rer er c ERE Ge Pee ie dme rg 11 15 11 6 Access to Multiplexed 11 16 12 1 DMA Signals 225 eR Rae eee nisal ed 12 2 Operations Performed During Transfer M 12 6 12 3 DMA Registers xd irae nad oi p E P EG UE D e P DOR 12 28 12 4 DMA Software Commands seem nee enne 12 50 13 1 SIernrc 13 4 xxii intel CONTENTS TABLES Table Page 13 2 Maximum and Minimum Baud rate Output 13 6 13 3 SSIO Registers een repete ne shen 13 16 14 1 CSU Signals one ee EU or vesicae aed eee t 14 13 14 2 CSW Registers nt etre aisha nena e ener eodd qt dc m deret 14 14 15 1 RGU Sighals eee 15 2 RGU Reglsters c ipte puede deret niue ciere src ires tee ete Porte de teen OO 16 1 Pin Multiplexing pee E Ha ee 16 5 16 2 Port Registers ET 255 16 3 Control bu add Values for UO Port Pin Configurations Lea Cien erp 16 7 17 1 WDT Signals Ec DPI pM cM CE
639. vates the internal DSRn and DCDn signals and the DTRn pin Note that pin is inverted from bit In standard mode setting this bit activates the DTRn pin clearing this bit deactivates the pin Note that pin is inverted from bit D 38 intel D 36 MSRn SYSTEM REGISTER QUICK REFERENCE Modem Status MSRO MSR1 read only MSR1 Expanded Addr F4FEH F8FEH ISA Addr O3FEH 02 Reset State RI DSR CTS DDCD TERI DDSR DCTS Bit Number Bit Mnemonic Function DCD Data Carrier Detect This bit is the complement of the data carrier detect DCDn input In diagnostic test mode this bit is equivalent to MCRn 3 OUT2 RI Ring Indicator This bit is the complement of the ring indicator RIn input In diagnostic test mode this bit is equivalent to MCRn 2 OUT1 DSR Data Set Reagy This bit is the complement of the data set ready DSRn input In diagnostic test mode this bit is equivalent to MCRn 0 DTR CTS Clear to Send This bit is the complement of the clear to send CTS nit input In diagnostic test mode this bit is equivalent to MCRn 1 RTS DDCD Delta Data Carrier Detect When set this bit indicates that the DCDn input has changed state since the last time this register was read Reading this register clears this bit TERI Trailing Edge Ring Indic
640. ve mode In master mode STXCLK functions as an output The baud rate generator s output appears on this pin through the transmitter and can be used to clock a slave receiver In slave mode STXCLK functions as an input clock for the transmitter SRXCLK Device pin Serial Receive Clock input oroutput This pin functions as either an output or an input depending on whether the receiver is operating in master or slave mode In master mode SRXCLK functions as an output The baud rate generator s output appears on this pin through the receiver and can be used to clock a slave transmitter In slave mode SRXCLK functions as an input clock for the receiver SSIOTX Device pin Transmit Serial Data output The transmitter uses this pin to shift serial data out of the device Data is transmitted most significant bit first SSIORX Device pin Receive Serial Data input The receiver uses this pin to shift serial data into the device Data is received most significant bit first SSRBF Internal signal Receive Buffer Full output This internal signal is used to indicate that received serial data has been transferred from the receive shift register to the receive holding buffer SSTBE Internal signal Transmit Buffer Empty output This internal signal is used to indicate that serial data has been shifted from the transmit holding register to the transmit shift register SSIOINT Internal signal SSIO Interrupt output This internal signal goes active when
641. ve shift register are transferred to the receive buffer Both the transmitter and receiver can operate in either master or slave mode In master mode the internal baud rate generator controls the serial communications by clocking the internal transmit ter or receiver If the transmitter or receiver is enabled in master mode the baud rate generator s signal appears on the transmit or receive clock pin and is available for clocking an external slave transmitter or receiver In slave mode an external master device controls the serial communica tions An input on the external transmit or receive clock pin clocks the transmitter or receiver The transmitter and receiver need not operate in the same mode This allows the transmitter and re ceiver to operate at different frequencies an internal and an external clock source or two different external clock sources can be used Figures 13 1 through 13 4 illustrate the various transmit ter receiver master slave combinations 18 1 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Baud rate Clock Source Generator PSCLK or SERCLK STXCLK SSTBE to DMA controller SSIOCON 5 TIE SSIOTX ai pin mux SSIOINT gp to Slave interrupt controller IR1 E SRXCLK SSIOCON 1 RIE Receiver pin mux SSRBF SSIORX to DMA controller A2434 02 Figure 13 1 Transmitter and Receiver in Master Mode Clock Source 2 PSCLK or SERCLK STXCLK S DM m Tran
642. wo pins for use in SMM systems SMI and SMIACT 7 2 4 System Management Interrupt Input SMIZ The SMI input signal is used to invoke system management mode SMI is a falling edge triggered interrupt input signal and is the highest priority of all external interrupt sources SMI forces the core into SMM at the completion of the current instruction SMI has these characteristics e SMI is not maskable e SMI is recognized on an instruction boundary and at each iteration for repeat string instructions SMI does not break locked bus cycles 7 1 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel SMI cannot interrupt currently executing SMM code The processor latches the falling edge of a pending SMI signal while the Intel386 EX processor is executing an existing SMI this allows one level of buffering The nested SMI is not recognized until after the execution of a resume instruction RSM e SMTH brings the processor out of idle or powerdown mode 7 2 2 SMM Active Output SMIACTZ This output indicates that the processor is operating in system management mode It is asserted when the CPU initiates the SMM sequence and remains active low until the processor executes the RSM instruction described in Resume Instruction RSM on page 7 15 to leave SMM Be fore SMIACT is asserted the CPU waits until the end of the instruction boundary SMIACT is used to establish a new memory map for SMM operation
643. write only Reset State 00H 7 0 DTM1 DTMO TI Al TD1 TDO 0 CS Bit Bit Number Mnemonic Function 7 6 DTM1 0 Data transfer Mode 00 Demand 01 Single 10 Block 11 Cascade 5 Tl Target Increment Decrement 0 Causes the target address to be incremented after each data transfer in a buffer transfer 1 Causes the target address for the channel specified by bit 0 to be decremented after each data transfer in a buffer transfer Note that it does not decrement words When decrementing it will do two byte transfers for a word Note When the target address is programmed to remain constant DMAMOD2 2 1 this bit is a don t care 4 Al Autoinitialize 0 Disables the autoinitialize buffer transfer mode for the channel specified by bit 0 1 Enables the autoinitialize buffer transfer mode for the channel specified by bit 0 3 2 TD1 0 Transfer Direction Determines the transfer direction for the channel specified by bit 0 00 Target is read nothing is written used for testing 01 Data is transferred from the requester to the target 10 Data is transferred from the target to the requester 11 Reserved Note In cascade mode these bits become don t cares 1 0 Must be 0 for correct operation 0 CS Channel Select 0 The selections for bits 7 2 affect channel 0 1 The selections for bits 7 2 affect channel 1 Figure 12 25 DMA Mode 1 Register DMAMOD1 12 39 Intel386
644. x00A0 define ICW2MDOS 0x0021 define ICW2SDOS 0x00A1 define ICW3MDOS 0x0021 define ICW3SDOS 0x00A1 define ICWAMDOS 0x0021 define ICW4SDOS 0x00A1 define OCW1MDOS 0x0021 define OCW1SDOS 0x00A1 define OCW2MDOS 0x0020 C 1 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel define define define OCW2SDOS OCW3MDOS OCW3SDOS 0x00A0 0x0020 0x00A0 CONFIGURATION Registers define define define define define define define define define define define define define define define define define define 2 DMACFG INTCFG TMRCFG SIOCFG PlCFG P2CFG P3CFG PINCFG WDTRLDH WDTRLDL WDTCNTH WDTCNTL WDTCLR WDTSTATUS TMRO TMR1 TMR2 TMRCON OxF830 OxF832 OxF834 OxF836 OxF820 OxF822 OxF824 OxF826 0 4 0 OxF4C2 OxF4C4 OxF4C6 OxF4C8 OxF4CA TIMER CONTROL REGISTERS 0 040 OxF041 0 042 OxF043 TIMER CONTROL REGISTERS WATCHDOG TIMER Registers SLOT 15 ADDRESSES SLOT 0 ADDRESSES define TMRODOS 0x0040 define TMR1DOS 0x0041 define TMR2DOS 0x0042 define TMRCONDOS 0x0043 INPUT OUTPUT PORT UNIT Registers define P1PIN OxF860 define P1LTC OxF862 define P1DIR OxF864 define P2PIN OxF868 define P2LTC OxF86A define P2DIR OxF86C define P3PIN OxF870 define P3LTC 0 872 define P3DIR OxF874 ASYNCHRONOUS SERIAL CHANNEL 0 SLOT 15 ADDRESSES define RBRO OxFAF8 define THRO OxFAF8 define TBRO OxFAF8
645. xternal device should deassert its request line HOLD or DRQn to allow the to perform a refresh cycle The refresh cycle is not executed until the external device deasserts its request If the external device reasserts its request signal before the RCU completes the refresh cycle bus control is given back to the external device after the refresh cycle completes without further arbitration 15 3 RCU OPERATION The following steps describe the basic refresh cycle which is initiated every time the interval counter reaches one 1 The interval timer unit asserts the timeout signal and reloads the interval counter with the refresh clock interval register value The interval counter decrements on each succeeding processor clock falling edge 2 The RCU requests bus ownership 3 Bus ownership is given to the control unit 4 The control unit asserts the REFRESH signal and bus memory read cycle with neither Byte enable signal active is executed with the address supplied by the RCU 5 The DRAM controller asserts RAS latching the row address inside the DRAM device This refreshes the row 6 The control unit deasserts REFRESH and the process repeats from step 1 when the interval counter reaches one again Once enabled the DRAM refresh process continues until you reprogram the RCU a reset occurs or the processor enters powerdown mode 15 5 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 15 4 REGISTER DEFIN
646. y with future devices do not modify these bits 8 0 PS8 0 Prescale Value These bits determine the divisor that is used to generate PSCLK Legal values are from 0000H divide by 2 to O1FFH divide by 513 divisor PS8 0 2 Figure 13 17 Clock Prescale Register CLKPRS 13 19 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel 13 3 4 SSIO Baud rate Control Register SSIOBAUD Use SSIOBAUD to enable the baud rate generator and determine the baud rate generator s sev en bit down counter s reload value BV SSIO Baud rate Control Expanded Addr F484H SSIOBAUD ISA Addr read write Reset State 00H 7 0 BEN BV6 BV5 BV4 BV3 BV2 BV1 BVO Bit Bit i Number Mnemonic Function 7 BEN Baud rate Generator Enable Setting this bit enables the baud rate generator Clearing this bit disables the baud rate generator clears the baud rate count value and forces the baud rate clock to zero 6 0 BV6 0 Baud rate Value The baud rate value BV is the reload value for the baud rate generator s seven bit down counter The baud rate generator s output is a function of BV and the baud rate generator s input BCLKIN as follows BCLKIN baud rate output frequency Hz P a y Hz 2BV 2 Hz If you know the desired output baud rate frequency you can determine BV as follows BV Im 1 2 x baud rate output frequency Figure 13 18 SSIO Baud
647. ycle CAUTION External bus arbitration logic should monitor the HLDA signal when the refresh control unit is being used If a refresh request is not serviced by performing a refresh cycle because an external master does not give up the bus the DRAM devices may lose data 6 28 BUS INTERFACE UNIT Cycle 3 Nonpipelined External Write Late Ready 5 ET N S e 2 0 o gt mc o 88 o Bag P oo0tg 0 20 Pc Poko o 2 as Lr CLK2 2 x A e e 5 S See cium cantus t bata eec heb af JOll Ll T T gt gt gt enses ape Pine th hj 8 gt rm l S S Sf Jaf qT TT T r1 Lp gt gt TF weg 8 8 3 lt 2 af cc i gt LOCK Q lt aly o 2491 02 Figure 6 11 Basic Refresh Cycle 6 29 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL 92 52 Mt es o Lr lt 5 Cs c E UE 8 25 77 Or o Lr da HOLD Acknowledge Th CLK2 Valid 1 o E o Joc me hee PEE Pee een N p lt lt 21 oc o uo Ta n c Floating 1 Floating Floating
648. yte count or terminal count has been reached 12 7 Intel386 EX EMBEDDED MICROPROCESSOR USER S MANUAL intel Figures 12 2 and 12 3 are simple diagrams of how the Temporary Register is filled and emptied for a Read DMA cycle and a Write DMA cycle Filling the Temporary Register Emptying the Temporary Register DREQn DREQn DREQn DREQn 1 2 4 Four separate requests each with a read gre Mese Cun esie Write write porary Register 1 1 1 1 Once the Temporary Resister is full the DMA does four burst writes to the target to empty it A3381 01 Figure 12 2 DMA Temporary Buffer Operation for a Read Transfer Filling the Temporary Register Emptying the Temporary Register DREQn 1 A single request with four separate reads of the target Each read stores a byte in the DREQn DREQn DREQn Temporary Register 2 3 4 Once the Temporary Resister is full the DMA does a write cycle to transfer the first byte from the Temporary Register to the target On each subsequent request the DMA performs a write cycle transferring a byte from the Temporary Register to the target This continues until empty A3382 01 Figure 12 3 DMA Temporary Buffer Operation for A Write Transfer 12 8 intel DMA CONTROLLER 12 2 3 Starting DMA Transfers Internal I O external I O or memory can request DMA service The internal I O requesters the asynchronous serial I O synchronous serial I O
649. z PSCLK is an internal signal that is a prescale value of the processor s internal clock The frequency of PSCLK is pro grammable See Controlling the PSCLK Frequency on page 8 7 The GATEn signals of the counters can be controlled through hardware or software as described in the next two sections 10 3 1 1 Hardware Control of GATEn You can connect each counter s GATEn signal to Its timer gate TMRGATEnD pin Hardware through a pin or Vcc control of the GATEz requires that the SWGTEN bit in the register be reset 10 3 1 2 Software Control of GATEn You can also use the TMRCFG register to drive GATEn high or low through register bits The SWGTEN and GTnCON bits are used to control the GATEn signal If SWGTEN is set then the value ofthe GTnCON bit causes the GATEn input of the counter to be driven to the corresponding voltage level Table 10 4 GATEn Connection Options SWGTEN GTnCON Meurs 0 Vas 1 TMRGATEn 1 0 0 Gaten is OFF 1 1 1 Gaten is ON The timer configuration register TMRCFG enables the counter s CLKINn signals and deter mines each counter s CLKINn and GATEnz signal connections or logical value Figure 10 22 10 20 intel TIMER COUNTER UNIT Timer Configuration Expanded Addr F834H TMRCFG ISA Addr read write Reset State 00H 7 0 TMRDIS SWGTEN GT2CON CK2CON GT1CON CK1CON GTOCON CKOCON

Intel386™ EX Embedded Microprocessor User`s Manual

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Intel386™ EX Embedded Microprocessor User`s Manual