datasheet here
Contents
1. pa die GG KADAR NA abala 7 2 1 VO Pons eee op dea val dana eel need ee ee os 10 PAA AA 10 2 3 Electrical Characteristics siennes 11 2 4 Absolute Maximum Ratings here tte de e bd Au GG 11 2 5 Recommended Operating Conditions 11 262 DC CharacteristiCs vetat E edle n ERREUR APER eed 11 247 Gurrent Gohns mptiolts zt dr rti itd eb tp Re Pda Pado As 12 2 8 Antenna characteristics naala tee np beca ect betta etre bv 13 3 Physical Dimensions if rette er un PRA ie 16 4 Power On Reset and Brownout Detector ss 18 5 Design Guidelines s putabit iUe 19 5 1 General Design Guidelines 19 5 2 Eayout Guide Lines AN eite cee ta aa eat ta 19 5 3 IBEETT9S A Layout Guide e idt eH nde Pee HE e D Ede 20 6 Soldering Recommendations iii 22 7 Blockidiagkami aito t aeu he fer tre prec ue Mar e eue 23 8 C rtifications fesse 26 8 1 Bluetooth E A re 26 8 2 POC rail Ge a PERDE 26 SE ETE IM 29 8 4 MIG Japa mie NANA NBA TAGA pe fr ie tei p Hate un Bre eoi bed ees 29 9 9 KCC Korea etched te GA e GN a Ai ee i totes 29 9 Contact2. lt txpower power gt Figure 2 BLE113 TX peak current as a function of the setting in the HW configuration file Bluegiga Technologies Oy Page 12 of 30 2 8 RF Characteristics Parameter Min Typ Max Unit Transmit power 1 5 0 1 dBm Receiver Sensitivity 93 dBm Gain of the Antenna 0 5 dBi Efficiency of the antenna 30 E 5 Table 8 RF Characteristic of BLE113 BA 6 8 lt txpower power gt 10 2 9 Antenna characteristics Figure 3 BLE113 TX power as a function of the setting in the HW configuration file The antenna is monopole type of chip antenna The antenna impedance matching is optimized for 1 mm 2 mm mother board PCB thickness The radiation pattern is impacted by the layout of the mother board Typically the highest gain is towards GND plane and weakest gain away from the GND plane Figures 4 6 show the radiation pattern of BLE113 when mounted to the development board The typical efficiency of the antenna is 25 35 depending on the mother board layout Maximum gain is 0 5 dBi Bluegiga Technologies Oy Page 13 of 30 Legend 2400 00 MHz 2440 00 MHz 2485 00 MHz Figure 4 Radiation pattern of BLE113 top view Udeg Legend 2400 00 MHz 2440 00 MHz 2485 00 MHz 270deg Figure 5 Radiation pattern
3. BLE112 A a Figure 17 Simplified block diagram of BLE113 CPU and Memory The 8051 CPU core is a single cycle 8051 compatible core It has three different memory access buses SFR DATA and CODE XDATA a debug interface and an 18 input extended interrupt unit The memory arbiter is at the heart of the system as it connects the CPU and DMA controller with the physical memories and all peripherals through the SFR bus The memory arbiter has four memory access points access of which can map to one of three physical memories an SRAM flash memory and XREG SFR registers It is responsible for performing arbitration and sequencing between simultaneous memory accesses to the same physical memory The SFR bus is a common bus that connects all hardware peripherals to the memory arbiter The SFR bus also provides access to the radio registers in the radio register bank even though these are indeed mapped into XDATA memory space Bluegiga Technologies Oy Page 23 of 30 The 8 KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces The SRAM is an ultralow power SRAM that retains its contents even when the digital part is powered off power modes 2 and 3 The 128 256 KB flash block provides in circuit programmable non volatile program memory for the device and maps into the CODE and XDATA memory spaces Peripherals Writing to the flash block is performed through a flash controller that allows page wise erasure an
4. BLE113 DATA SHEET Thursday 20 March 2014 Version 1 4 Copyright 2000 2014 Bluegiga Technologies All rights reserved Bluegiga Technologies assumes no responsibility for any errors which may appear in this manual Furthermore Bluegiga Technologies reserves the right to alter the hardware software and or specifications detailed here at any time without notice and does not make any commitment to update the information contained here Bluegiga s products are not authorized for use as critical components in life support devices or systems The WRAP is a registered trademark of Bluegiga Technologies The Bluetooth trademark is owned by the Bluetooth SIG Inc USA and is licensed to Bluegiga Technologies All other trademarks listed herein are owned by their respective owners Bluegiga Technologies Oy VERSION HISTORY Version Comment 1 0 Preliminary datasheet gt production datasheet No changes 1 1 Pull up resistors added to P1_0 and P1_1 in the example schematic 1 2 5 mm restriction removed from the FCC statement Product code for 256k variant added Peripheral mapping table analog 1 3 comparator added Added note that pins configured as peripheral I O signals do not have pull up down capability RF Characteristics added 1 4 Product numbering updated Bluegiga Technologies Oy TABLE OF CONTENTS 1 BEET S Product Umber ios ce nieder derit o ee BANG Aa ka a Ng NANANG ad ap 6 2
5. 2 Configurable 1 0 port with 20mA driving Digital I O capability See table 3 P1 0 2 sina be used as I C clock pin or digital I O Leave EN floating if not used If grounded disable pull up 2 pah be used as data pin or digital I O Leave EBEN Cata en agal 1O floating if not used If grounded disable pull up Table 2 Terminal Descriptions BLE113 is configurable as either SPI master or SPI slave Bluegiga Technologies Oy Page 8 of 30 PERIPHERAL POP HARDWAREXMLExmplet Function _ 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 o 2 1 o Analog Comparator jA7z AejAS M As A2 AT A0 lana a usart channel 0 mode spi_master alternate 1 ana usart channel 0 mode spi master alternatez 2 lt usart channel 0 mode uart alternate 1 ana mener USART spi ce ana RES ERAS PESE EET RR RM SE _ E DD lt usart channel 0 mode uart alternatez 2 maa Er RTT EF a a EN lt usart channel 1 mode spi master alternate 1 lt usart channel 1 mode spi master alternate 2 usart cha
6. of BLE113 front view Bluegiga Technologies Oy Page 14 of 30 Figure 6 Radiation pattern of BLE113 side view Bluegiga Technologies Oy Page 15 of 30 3 Physical Dimensions 1 50mm 5 35mm 0 50mm 4 0 80mm J 1 15 725mm 0 300mm 1 450 Figure 7 Physical dimensions pinout top view 15 73 mm 0 1mm c o c lt 9 15 0 1mm 0 6 5 53 9 6 0 6 Figure 8 Physical dimensions top view Bluegiga Technologies Oy Page 16 of 30 ee 1 7 1075 0 6 mm lt gt 15 73 0 1 mm Figure 9 Physical dimensions side view 2 00mm 5 35mm 0 50mm 0 80mm 3 _ s 0 550mm 1 675mm J Figure 10 Recommended land pattern for BLE113 A Bluegiga Technologies Oy Page 17 of 30 4 Power On Reset and Brownout Detector BLE113 includes a power on reset POR providing correct initialization during device power on It also includes a brownout detector BOD operating on the regulated 1 8 V digital power supply only The BOD protects the memory contents during supply voltage variations which cause the regulated 1 8 V power to drop below the minimum level required by digital logic flash memory and SRAM When power is initially applied the POR and BOD hold the device in the reset state until the supply voltage rises above the power on reset and brownout voltages Bluegiga Technologies Oy Page 18 of 30 5
7. particular solder paste for profile configurations Avoid using more than one flow Reliability of the solder joint and self alignment of the component are dependent on the solder volume Minimum of 150um stencil thickness is recommended Aperture size of the stencil should be 1 1 with the pad size A low residue no clean solder paste should be used due to low mounted height of the component 250 200 150 3 3 o o 100 50 gi 2 k3 0 50 100 150 200 250 300 Figure 16 Reference reflow profile Bluegiga Technologies Oy Page 22 of 30 7 Block diagram BLE113 is based on Tl s CC2541 chip Embedded 32 MHz and 32 678 kHz crystals are used for clock generation Matched balun and low pass filter provide optimal radio performance with extremely low spurious emissions Small ceramic chip antenna gives good radiation efficiency even when the module is used in layouts with very limited space CC2540 Debug interface 8051 CPU core and memory arbitrator Analog comparator IRQ controller 1 0 Radio arbiter Radio registers Link layer engine SRAM 48 043002 0 1 Demodulator Modulator 1 Assembly variant BLE112 A or DSARIID BLE112 USART1 Frequency Receive synthetisizer Transmit 1 U FI 1 connector TU BLE112 E TIMER 3 Balun Chip I TIMER 4 LPF antenna
8. 13 with a coin cell battery TPS62730 DCDC converter and an 2 accelerometer 5 2 Layout Guide Lines Use good layout practices to avoid excessive noise coupling to supply voltage traces or sensitive analog signal traces If using overlapping ground planes use stitching vias separated by max 3 mm to avoid emission from the edges of the PCB Connect all the GND pins directly to a solid GND plane and make sure that there is a low impedance path for the return current following the signal and supply traces all the way from start to the end A good practice is to dedicate one of the inner layers to a solid GND plane and one of the inner layers to supply voltage planes and traces and route all the signals on top and bottom layers of the PCB This arrangement will make sure that any return current follows the forward current as close as possible and any loops are minimized Bluegiga Technologies Oy Page 19 of 30 Signals GND Power Signals Figure 12 Typical 4 layer PCB construction CC ON KCC D Overlapping GND layers without Overlapping GND layers with GND stitching vias GND stitching vias shielding the RF energy Figure 13 Use of stitching vias to avoid emissions from the edges of the PCB 5 3 BLE113 A Layout Guide For optimal performance of the antenna place the module at the corner of the PCB as shown in the figure 14 Do not place any metal traces components battery etc within the clearance area o
9. A Flexible peripheral interfaces o UART and SPI o 126 PWM GPIO o 12 bit ADC Host interfaces UART Programmable 8051 processor for stand alone operation Dimensions 9 15 x 15 75 x 2 1 mm Bluetooth CE FCC IC South Korea and Japan qualified Bluegiga Technologies Oy 1 BLE113 Product numbering Product code Description BLE113 A BLE113 with integrated chip antenna 128k flash memory BLE113 A M256K BLE113 with integrated chip antenna 256k flash memory Bluegiga Technologies Oy Page 6 of 30 2 Pinout and Terminal Description GND 36 NC 35 Reset 34 L 33 1 32 2 31 3 30 po 4 L 29 po 5 L 28 Po 6 22 po 7 L 29 GND 25 NM S S AL R amp Figure 1 BLE113 PIN PAD TYPE RESET GND DESCRIPTION Active low reset GND GND DVDD AVDD bo mu upply voltage 2V 3 6V upply voltage 2V 3 6V Supply voltage Supply voltage Table 1 Supply and RF Terminal Descriptions Bluegiga Technologies Oy Page 7 of 30 PIN NUMBER PIN NAME PIN TYPE DESCRIPTION ae 2820 10 Pi 412 P17 re 5176 11 P15 _ 2 Pi4 21 P13 22 Pi2 Digital I O Configurable I O port See table 3 _26 Po7 27 Po6 28 P05 29 P04 30 P03 East P02 83 Po1 KEN 10 11 12 13 19 0 1 2 6 7 8 9 0 1 2 3 3 4 14 15 2 2 2 2 2 2 2 3 3 3 3 2
10. BGTBLE113 ou Contient identification FCC QOQBLE113 lt Contient IC 5123A BGTBLE113 gt Dans le guide d utilisation du produit final l int grateur OEM doit s abstenir de fournir des informations l utilisateur final portant sur les proc dures suivre pour installer ou retirer ce module RF ou pour changer les param tres RF Bluegiga Technologies Oy Page 28 of 30 8 3 CE BLE113 is conformity with the following standards SAFETY e EN 60950 1 2006 A11 2009 A1 2010 A12 2011 EMC Art 3 1 a e EN 301 489 1 v 1 9 2 e EN 301 489 17 V2 2 1 Radiated electric field immunity EN 61000 4 3 2006 SPECTRUM Art 3 2 e EN 300 328 v1 7 1 o Equivalent isotropic radiated power Maximum spectral power density e EN 300 328 V1 8 1 Occupied channel bandwidth o Transmitter unwanted spurious emissions in the out of band domain Transmitter unwanted spurious emissions in the spurious domain o Receiver spurious emissions 8 4 MIC Japan BLE113 is certified as a module with type certification number 007 AB0103 As a certified module BLE113 can be integrated to an end product without a need for additional MIC Japan certification of the end product 8 5 KCC Korea BLE113 has type certification in Korea with certification number KCC CRM BGT BLE113 Bluegiga Technologies Oy Page 29 of 30 9 Contact Information Sales Technical support Orders WWW Head Office Finland Postal address Finl
11. Design Guidelines 5 1 General Design Guidelines LE113 can be used directly with a coin cell battery Due to relatively high internal resistance of a coin cell battery it is recommended to place a 100uF capacitor in parallel with the battery The internal resistance of a coin cell battery is initially in the range of 10 ohms but the resistance increases rapidly as the capacity is used Basically the higher the value of the capacitor the higher is the effective capacity of the battery and thus the longer the life time for the application The minimum value for the capacitor depends on the end application and the maximum transmit power used The leakage current of a 100uF capacitor is in the range of 0 5 uA to 3 uA and generally ceramic capacitors have lower leakage current than tantalum or aluminum electrolytic capacitors Optionally Tl s TPS62730 can be used to reduce the current consumption during TX RX and data processing stages TPS62730 is an ultra low power DC DC converter with by pass mode and will reduce the current consumption during transmission nominally by 20 when using 3V coin cell battery TPs62730 7 PROGRAMMING INTERFACE P1 O and P1 1 require external pull up or pull down resistor if configured as inputs Figure 11 Example schematic for BLE1
12. Information nnn era eee 30 Bluegiga Technologies bive sis BLE113 Bluetooth Smart Module DESCRIPTION BLE113 is a Bluetooth Smart module targeted for small and low power sensors and accessories It integrates all features required for a Bluetooth Smart application Bluetooth radio software stack and GATT based profiles BLE113 Bluetooth Smart module can also host end user applications which means no external micro controller is required in size or price constrained devices BLE113 module has flexible hardware interfaces to connect to different peripherals and sensors BLE113 can be powered directly from a standard 3V coin cell battery or pair of AAA batteries In lowest power sleep mode it consumes only 500nA and will wake up in few hundred microseconds APPLICATIONS Health and fitness sensors Medical sensors iPhone and iPad accessories Security and proximity tags Key fobs Smart home sensors and collectors Wireless keys HID keyboards and mice KEY FEATURES Bluetooth v 4 0 single mode compliant o Supports master and slave modes o Up to eight connections Integrated Bluetooth Smart stack o GATT L2CAP and SMP o Bluetooth Smart profiles Radio performance o TX power 0 dBm to 23 dBm o Receiver sensitivity 93 dBm Ultra low current consumption o Transmit 18 2 mA OdBm o Transmit 14 3 mA OdBm DC DC o Receive 14 3 o Sleep mode 3 0 4 u
13. action Timer 2 is a 40 bit timer used by the Bluetooth low energy stack It has a 16 bit counter with a configurable timer period and a 24 bit overflow counter that can be used to keep track of the number of periods that have transpired A 40 bit capture register is also used to record the exact time at which a start of frame delimiter is received transmitted or the exact time at which transmission ends There are two 16 bit timer compare registers and two 24 bit overflow compare registers that can be used to give exact timing for start of RX or TX to the radio or general interrupts Timer 3 and timer 4 are 8 bit timers with timer counter PWM functionality They have a programmable prescaler an 8 bit period value and one programmable counter channel with an 8 bit compare value Each of the counter channels can be used as PWM output USART 0 and USART 1 are each configurable as either an SPI master slave or a UART They provide double buffering on both RX and TX and hardware flow control and are thus well suited to high throughput full duplex applications Each USART has its own high precision baud rate generator thus leaving the ordinary timers Bluegiga Technologies Oy Page 24 of 30 free for other uses When configured as SPI slaves the USARTs sample the input signal using SCK directly instead of using some oversampling scheme and are thus well suited for high data rates The AES encryption decryption core allows the user to encrypt and decr
14. and Sales Office USA Sales Office Hong Kong sales bluegiga com support bluegiga com http techforum bluegiga com orders bluegiga com www bluegiga com www bluegiga hk Phone 358 9 4355 060 Fax 358 9 4355 0660 Sinikalliontie 5A 02630 ESPOO FINLAND P O BOX 120 02631 ESPOO FINLAND Phone 1 770 291 2181 Fax 1 770 291 2183 Bluegiga Technologies Inc 3235 Satellite Boulevard Building 400 Suite 300 Duluth GA 30096 USA Bluegiga Technologies Ltd Phone 852 3972 2186 Bluegiga Technologies Oy Page 30 of 30
15. ction with any other antenna or transmitter except in accordance with FCC multi transmitter product procedures IC Statements This device complies with Industry Canada licence exempt RSS standard s Operation is subject to the following two conditions 1 this device may not cause interference and 2 this device must accept any interference including interference that may cause undesired operation of the device Under Industry Canada regulations this radio transmitter may only operate using an antenna of a type and maximum or lesser gain approved for the transmitter by Industry Canada To reduce potential radio interference to other users the antenna type and its gain should be so chosen that the equivalent isotropically radiated power e i r p is not more than that necessary for successful communication OEM Responsibilities to comply with FCC and Industry Canada Regulations The BLE113 module has been certified for integration into products only by OEM integrators under the following condition Bluegiga Technologies Oy Page 26 of 30 e The transmitter module must not be co located or operating in conjunction with any other antenna or transmitter except in accordance with FCC multi transmitter product procedures As long as the two condition above is met further transmitter testing will not be required However the OEM integrator is still responsible for testing their end product for any additional compliance requirements require
16. d with this module installed for example digital device emissions PC peripheral requirements etc IMPORTANT NOTE In the event that these conditions can not be met for certain configurations or co location with another transmitter then the FCC and Industry Canada authorizations are no longer considered valid and the FCC ID and IC Certification Number can not be used on the final product In these circumstances the OEM integrator will be responsible for re evaluating the end product including the transmitter and obtaining a separate FCC and Industry Canada authorization End Product Labeling The BLE113 module is labeled with its own FCC ID and IC Certification Number If the FCC ID and IC Certification Number are not visible when the module is installed inside another device then the outside of the device into which the module is installed must also display a label referring to the enclosed module In that case the final end product must be labeled in a visible area with the following Contains Transmitter Module FCC ID QOQBLE113 Contains Transmitter Module IC 5123A BGTBLE113 or Contains FCC ID 113 Contains IC 5123A BGTBLE113 The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module or change related parameters in the user manual of the end product 8 2 1 FCC et IC D claration d IC Ce dispositif est conforme aux nor
17. d 4 bytewise programming A versatile five channel DMA controller is available in the system accesses memory using the XDATA memory space and thus has access to all physical memories Each channel trigger priority transfer mode addressing mode source and destination pointers and transfer count is configured with DMA descriptors that can be located anywhere in memory Many of the hardware peripherals AES core flash controller USARTs timers ADC interface etc can be used with the DMA controller for efficient operation by performing data transfers between a single SFR or XREG address and flash SRAM Each CC2541 contains a unique 48 bit IEEE address that can be used as the public device address for a Bluetooth device Designers are free to use this address or provide their own as described in the Bluetooth specification The interrupt controller services a total of 18 interrupt sources divided into six interrupt groups each of which is associated with one of four interrupt priorities and sleep timer interrupt requests are serviced even if the device is in a sleep mode power modes 1 and 2 by bringing the CC2541 back to the active mode The debug interface implements a proprietary two wire serial interface that is used for in circuit debugging Through this debug interface it is possible to erase or program the entire flash memory control which oscillators are enabled stop and start execution of the user program execute instr
18. enna with matching network Optimal matching combined with effective low pass filter provides extremely low in band spurious emissions and harmonics Bluegiga Technologies Oy Page 25 of 30 8 Certifications BLE113 is compliant to the following specifications 8 1 Bluetooth BLE113 is BT qualified as a controller subsystem As a controller subsystem the module can be used as such with a Host Subsystem to make a Bluetooth end product without additional qualification or QDID The Bluetooth QDID of BLE13 is B021015 The Bluetooth listing can be vied from the link below https www bluetooth org tpg QLI viewQDL cfm gid 21015 8 2 FCC and IC This device complies with Part 15 of the FCC Rules Operation is subject to the following two conditions 1 this device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation Any changes or modifications not expressly approved by Bluegiga Technologies could void the user s authority to operate the equipment FCC RF Radiation Exposure Statement This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment End users must follow the specific operating instructions for satisfying RF exposure compliance This transmitter meets both portable and mobile limits as demonstrated in the RF Exposure Analysis This transmitter must not be co located or operating in conjun
19. f the antenna Connect all the GND pins directly to a solid GND plane Place the GND vias as close to the GND pins as possible Use good layout practices to avoid any excessive noise coupling to signal lines or supply voltage lines Avoid placing plastic or any other dielectric material closer than 5 mm from the antenna Any dielectric closer than 5 mm from the antenna will detune the antenna to lower frequencies 3 50mm Board outline learance area Figure 14 Recommended layout for BLE113 A Bluegiga Technologies Oy Page 20 of 30 2550 Freq MHz Figure 15 Typical return loss of BLE113 A with two different mother board PCB thickness Bluegiga Technologies Oy Page 21 of 30 6 Soldering Recommendations BLE113 is compatible with industrial standard reflow profile for Pb free solders The reflow profile used is dependent on the thermal mass of the entire populated PCB heat transfer efficiency of the oven and particular type of solder paste used Consult the datasheet of particular solder paste for profile configurations Bluegiga Technologies will give following recommendations for soldering the module to ensure reliable solder joint and operation of the module after soldering Since the profile used is process and layout dependent the optimum profile should be studied case by case Thus following recommendation should be taken as a starting point guide Refer to technical documentations of
20. gured as inputs with pull ups P1 O and P1 1 are inputs but do not have pull up or pull down NOTE Pins configured as peripheral I O signals do not have pull up down capability 2 2 UART UART baud rate can be configured up 2 Mbps See the Profile Toolkit developer guide for more information Following table lists commonly used baud rates for BLE113 Baud rate bps Error 2400 0 14 4800 0 14 9600 0 14 14 400 0 08 19 200 0 14 28 800 0 03 38 400 0 14 57 600 0 03 76 800 0 14 115 200 0 03 230 400 0 03 Table 4 Commonly used baud rates for BLE113 Bluegiga Technologies Oy Page 10 of 30 2 3 Electrical Characteristics 2 4 Absolute Maximum Ratings Note These are absolute maximum ratings beyond which the module can be permanently damaged These are not maximum operating conditions The maximum recommended operating conditions are in the table 6 Rating Min Max Unit Storage Temperature 40 85 C AVDD DVDD 0 3 3 9 V Other Terminal Volatages VSS 0 4 VDD 0 4 V supply nets must have the same voltage Table 5 Absolute Maximum Ratings 2 5 Recommended Operating Conditions Rating Min Unit Operationg Temperature Range 40 85 AVDD DVDD 2 0 3 6 V Supply voltage noise should be less than 10mVpp Excessive noise at the supply voltage will reduce the RF performance Table 6 Recommended Operati
21. mes RSS exemptes de licence d Industrie Canada Son fonctionnement est assujetti aux deux conditions suivantes 1 ce dispositif ne doit pas provoquer de perturbation et 2 ce dispositif doit accepter toute perturbation y compris les perturbations qui peuvent entrainer un fonctionnement non d sir du dispositif Selon les r glementations d Industrie Canada cet metteur radio ne doit fonctionner qu avec une antenne d une typologie sp cifique et d un gain maximum ou inf rieur approuv pour l metteur par Industrie Canada Pour r duire les ventuelles perturbations radio lectriques nuisibles d autres utilisateurs le type d antenne et son gain doivent tre choisis de mani re ce que la puissance isotrope rayonn e quivalente P L R E n exc de pas les valeurs n cessaires pour obtenir une communication convenable Responsabilit s des OEM quant la conformit avec les r glementations de FCC et d Industrie Canada Les modules BLE113 ont t certifi s pour entrer dans la fabrication de produits exclusivement r alis s par des int grateurs dans les conditions suivantes Bluegiga Technologies Oy Page 27 of 30 e Le module transmetteur ne doit pas tre install ou utilis en concomitance avec une autre antenne ou un autre transmetteur Tant que ces deux conditions sont r unies il n est pas n cessaire de proc der des tests suppl mentaires sur le transmetteur Cependant l int grateur est responsable des
22. ng Conditions 2 6 DC Characteristics Parameter Test Conditions Min Typ Unit Logic 0 input voltage 0 5 V Logic 1 input voltage DVDD 3V0 2 5 V Logic 0 input current Input equals OV 50 50 nA Logic 1 input current Input equals VDD 50 50 nA I O pin pull up and pull down resistors 20 kQ Logic 0 output voltage 4 mA pins Output load 4 mA 0 5 V Logic 0 output voltage 4 mA pins Output load 4 mA 24 V For detailed I O terminal characteristic and timings refer to the CC2541 datasheet available in http www ti com lit ds symlink cc2541 pdf Bluegiga Technologies Oy Page 11 of 30 2 Current Consumption Power mode hardware xml Min Typ Max Unit lt txpower power 1 gt slow clock enable true 5 18 2 lt txpower power 7 gt slow clock enable true 5 18 3 mA lt txpower power 15 gt 20 7 mA slow clock enable true Transmit iw lt txpower power 1 gt 23 6 mA lt slow clock enable false gt lt txpower power 7 gt slow clock enable false 23 6 mA lt txpower power 15 gt slow clock enable false 26 1 MA slow clock enable true 21 9 mA Receive slow clock enable false 27 0 mA Power mode 1 270 HA Power mode 2 1 HA Power mode 3 0 5 HA 5 195 o x m a Table 7 Current consumption of BLE113 N
23. nnel 1 mode uart alternate 1 usart channel 1 mode uart alternate 2 ESTER RS SS ER timer index 1 alternate 1 lt timer index 1 alternate 2 lt timer index 3 alternate 1 lt timer index 3 alternate 2 lt timer index 4 alternate 1 lt timer index 4 alternate 2 osse S TT Refer to Profile Toolkit Developer Guide for detailed settings SS is the slave select signal when BLE113 is set as SPI slave When set as SPI master any available I O can be used as chip select signal of BLE113 The analog comparator and the ADC will be turned on automatically when taken in use and the configuration is done using API Application Programming Interface Refer to Bluetooth Smart Software API Reference NOTE Pins configured as peripheral I O signals do not have pull up down capability Table 3 Peripheral I O Pin Mapping Bluegiga Technologies Oy Page 9 of 30 2 1 I O Ports Each I O port can be configured as an input or output When configured as input each I O port except pins P1 O and P1 1 can also be configured with internal pull up pull down or tri state Pull down or pull up can only be configured to whole port not individual pins Unused I O pins should have defined level and not be floating See the Profile Toolkit developer guide for more information about the configuration During reset the I O pins are confi
24. tests effectu s sur le produit final afin de se mettre en conformit avec d ventuelles exigences compl mentaires lorsque le module est install exemple missions provenant d appareils num riques exigences vis vis de p riph riques informatiques etc REMARQUE IMPORTANTE En cas d inobservance de ces conditions en ce qui concerne certaines configurations ou l emplacement du dispositif proximit d un autre metteur les autorisations de FCC et d Industrie Canada ne seront plus consid r es valables et l identification de FCC et le num ro de certification d IC ne pourront pas tre utilis s sur le produit final Dans ces cas l int grateur OEM sera charg d valuer nouveau le produit final y compris l metteur et d obtenir une autorisation ind pendante de FCC et d Industrie Canada tiquetage du produit final Le module BLE113 est tiquet avec sa propre identification FCC et son propre num ro de certification IC Si l identification FCC et le num ro de certification IC ne sont pas visibles lorsque le module est install l int rieur d un autre dispositif la partie externe du dispositif dans lequel le module est install devra galement pr senter une tiquette faisant r f rence au module inclus Dans ce cas le produit final devra tre tiquet sur une zone visible avec les informations suivantes Contient module metteur identification FCC QOQBLE113 Contient module metteur IC 5123A
25. uctions on the 8051 core set code breakpoints and single step through instructions in the code Using these techniques it is possible to perform in circuit debugging and external flash programming elegantly The I O controller is responsible for all general purpose I O pins The CPU can configure whether peripheral modules control certain pins or whether they are under software control and if so whether each pin is configured as an input or output and if a pullup or pulldown resistor in the pad is connected Each peripheral that connects to the I O pins can choose between two different I O pin locations to ensure flexibility in various applications The sleep timer is an ultra low power timer that uses an external 32 768 kHz crystal oscillator The sleep timer runs continuously in all operating modes except power mode 3 Typical applications of this timer are as a real time counter or as a wake up timer to exit power modes 1 or 2 Timer 1 is a 16 bit timer with timer counter PWM functionality It has a programmable prescaler a 16 bit period value and five individually programmable counter capture channels each with a 16 bit compare value Each of the counter capture channels can be used as a PWM output or to capture the timing of edges on input signals It can also be configured in IR generation mode where it counts timer 3 periods and the output is ANDed with the output of timer 3 to generate modulated consumer IR signals with minimal CPU inter
26. ypt data using the AES algorithm with 128 bit keys The AES core also supports ECB CBC CFB OFB CTR and CBC MAC as well as hardware support for CCM The ADC supports 7 to 12 bits of resolution with a corresponding range of bandwidths from 30 kHz to 4 kHz respectively DC and audio conversions with up to eight input channels I O controller pins are possible The inputs can be selected as single ended or differential The reference voltage can be internal AVDD or a single ended or differential external signal The ADC also has a temperature sensor input channel The ADC can automate the process of periodic sampling or conversion over a sequence of channels The module provides a digital peripheral connection with two pins and supports both master and slave operation support is compliant with the NXP 2 specification version 2 1 and supports standard mode up to 100 kbps and fast mode up to 400 kbps In addition 7 bit device addressing modes are supported as well as master and slave modes The ultralow power analog comparator enables applications to wake up from PM2 or based on an analog signal Both inputs are brought out to pins the reference voltage must be provided externally The comparator output is connected to the I O controller interrupt detector and can be treated by the MCU as a regular I O pin interrupt RF front end RF front end includes combined matched balun and low pass filter and ceramic chip ant
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