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EXM32_AU1250_User-Manual-V10

1. BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 JO Pi R IR IR IR IR IR RH R IR IR IR IR IR IR IR R DEFAULT E z BIT NAME VALUE DESCRIPTION 15 FREQUENCY SET 1 14 FREQUENCY SET 0 13 AU PSC1 DO 12 AU PSC1 SYNC 7 11 X2D_FR_RXD 0 ES 1 10 X2D_FR_STB 9 X2D_FR_ERR 8 X1C_PWRFLT 7 x 0 1A SPI MISO 1 0 6 AU PSC1 CLK 1 5 AU PSC1 SYNCO 7 4 X1C_AC97_SYNC 3 X2C I2C1 SDA 0 EE 1 0 2 X2C I2C1 SCL 1 1 X2C DDC SCL 0 X2C DDC SDA 7 EXM32_AU1250_User Manual V10 doc page 76 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 5 1 21 Test Register 2 Input Signals OxE8 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ET R R R R R R R IR R R R R R R R R DEFAULT d z E 2 BIT NAME VALUE DESCRIPTION 15 4 14 13 12 11 10 o I i 2 X1C_AC97_SDINO 1 X1C_12S1_SCLK 7 0 X1C_l2S1_LRCLK EXM32_AU1250_User Manual V10 doc page 78 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 5 1 22 Test Register 3
2. BIT NAME VALUE DESCRIPTION 15 14 ES 12 11 EE EE NE 7 GPOUT 7 Default 6 GPOUTIS BEL 5 GPOUT 5 paraul 4 GPOUTIA D BU 3 GPOUTI3 Default 2 GPOUTI2 Detagli 1 GPOUTII Derat 0 GPOUTIO parauli EXM32_AU1250_User Manual V10 doc page 71 of 110 EXM32 AU1250 CPU Module User s Manual 5 1 16 GPIO Direction Register 0x40 MSC Vertriebs GmbH BIT 15 114113 12 11 11019 8 7 6 15 4 3 2 1 0 PW W W W W W W W W KS KS ET Vm p Em rA Em DEFAULT O 0 JO lO JO 10 JO JO 1 1 1 1 1 1 1 1 BIT NAME VALUE DESCRIPTION 15 GPIO DIR 0 GPIO DIR 7 write operation is disabled EN 7 1 GPIO DIR 7 write operation is enabled 14 GPIO DIR 0 GPIO DIR 6 write operation is disabled EN 6 1 GPIO DIR 6 write operation is enabled 13 GPIO Din 0 GPIO DIR 5 write operation is disabled EN 5 1 GPIO DIR 5 write operation is enabled 19 GPIO DIR 0 GPIO DIR 4 write operation is disabled EN 4 1 GPIO DIR 4 write operation is enabled 41 SPIO_DIR_ 0 GPIO DIRI3 write operation is disabled EN 3 1 GPIO DIR 3 write operation is enabled 10 SPIO_DIR_ 0 GP
3. sys trioutclr Address 0x0 11900100 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PN w IW IW jw jw jw jw jw W jw w w jw jw IW IW DEFAULT 0 10 O O 10 10 O O O 10 10 0 JO O JO 0 INIT 0 0 0 10 O JO 10 IO IO JO 0 1 1 1 1 0 BIT 15 14 13 12 11 110 9 8 7 6 5 4 3 2 1 0 z W IWJ W w IWIWIWIWIWIWIWIW IW DEFAULT 0 0 0 0 0 0 JO 0 O 0 JO JO O INIT 0 0 0 0 1 1 1 0 0 0 0 1 0 l 0x100E0708 Sys outputclr Address 0x0 1190010C BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E w IW IW jw jw jw jw jw IW jw w w jw jw jw IW DEFAULT INIT 0 O 10 10 JO JO 10 0 O 0 10 O JO 0 O0 JO BIT 15 14 13 12 11 1109 8 7 6 5 4 3 2 1 0 z w IW IW jw jw jw jw W W jw w w W jw jw IW DEFAULT INIT 0 O 10 10 JO JO 10 0 JO O 0 O JO 0 O JO 0x00000000 Setting GPIO Block 2 Port Direction gpio2_dir Address 0x0_1170_0000 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PA R IR R JR IR IR R IR RR RH IR R RH RH R R DEFAULT O O 10 0 10 0 0 JO JO 0 O JO JO O O JO INIT e e e E e
4. 5 1 5 LCDCTRL LCD Control Register Offset 0x10 entspricht BOARD_SPECIFIC BIT USA d ds 128 fal oO e 17 G 15 14 Is J2 ja KO R R IR R R R IR Rai ele Wella DEFAULT O 10 10 10 O 10 1 O JO O JO O O 10 JO 0 BIT NAME Ve DESCRIPTION 0 15 1 0 14 1 0 13 1 0 12 1 0 11 1 0 10 1 9 OS 0 LCD Display is feed by AU1250 Default 1 LCD Display is feed by Spread Spectrum Clock Modulator Clock Range and Dither Rate Select Three level input that determines the CM CR dither rate 8 7 d CM CR SEL 1 0 CLKIN Range Dither Rate 10 66MHz to 134MHz fIN 2048 01 33MHz to 80MHz fIN 1024 00 Default 20MHz to 38MHz fIN 512 6 E ABE E 0 Spread Spectrum Modulator disabled Default 1 Spread Spectrum Modulator enabled Spread Spectrum Magnitude Select Inputs These digital inputs select the desired spread spectrum magnitude as shown in the table below CM CM SEL 1 0 Magnitude 5 4 SELLO 11 0 5 10 1 96 01 31 596 Ar ix 42 3 LCD 0 Display off only STN displays DON 1 Display on only STN displays 2 LCD 0 disable backlight BLON 1 enable backlight 1 LCD 0 disable digital power supply VDD VDON 1 enable digital power supply VDD 0 LCD 0 disable power inverter voltage VEE VCON 1 enable power inverter voltage VEE EXM32_AU1250_User Manual V10 doc page 61 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertrie
5. L CD is Color STN Panel Color TFT Panel GE mue Signal Zen 8 bit Single Dual 12 bit 18 bit 24 bit LCD D 0 MO MO DO DO BO GP OUT 2JLCD2 D 13 LCD DIT Mi M1 D1 D1 Bt GP OUT 3 LCD2 D12 LCD DEL M2 M2 D2 D2 BO B2 LCD Bio LCD D 3 M3 M3 D3 D3 B1 B3 LCD BT LCD D 4 M4 D4 BO B2 B4 LCD _B 2 LCD DIS M5 D5 B1 B3 B5 LCD BI LCD Drei M6 D6 B2 B4 B6 LCD _B 4 LCD D M7 D7 B3 B5 B7 LCD B 5 LCD DI8 GO GP OUT 4VLCD DITT LCD DIS G1 GP OUT B LCD2 D10 LCD DI10 GO G2 LCD G 0 LCD DITT G1 G3 LCD Gl LCD DZ GO G2 G4 LCD GP LCD D 13 G1 G3 G5 LCD Gi LCD D 14 G2 G4 G6 LCD Ga LCD D 15 G3 G5 G7 LCD G 5 LCD De RO GP OUT GJLCD2 DIS LCD D 17 R1 GP OUT 7 LCD2 D 8 LCD DS RO R2 LCD G 0 LCD De R1 R3 LCD _GI1 LCD D So RO R2 R4 LCD GP LCD DI21 R1 R3 R5 LCD Gi LCD DI22 R2 R4 R6 LCD G 4 LCD DI23 R3 R5 R7 LCD G 5 LCD BIAS LCD M DE LCD FCLK LCD VSYNC LCD LCLK LCD HSYNC LCD PCLK LCD SHFCLK Table 6 EXM32 Au1250 LCD Interface EXM32_AU1250_User Manual V10 doc page 28 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 4 1 9 2 Spread Spectrum LCD Clock Modulator The AU1250 CPU Module is equiped with a DS1081L Clock Modulator The AU1250 LCD Clock can be feed through the DS1081L for EMV purposes or bypassed by an analog switch Refer to section 6 1 5 LCDCTRL LCD Control Register and the Maxim DS
6. EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 5 1 FPGA Register Description RCEO RCE3 RESET INIT REGISTER ACCESS SIZE ADDRESS ADDRESS VALUE VALUE BRDREV R 16 Ox1FFF_0000 Ox3FFF 0000 E BRDSTAT R 16 OxiFFF 0004 Ox3FFF 0004 3 BRDCTRL y 16 OxiFFF 0008 Ox3FFF 0008 0x0000 LEDCTRL R 16 Ox1FFF_000C Ox3FFF 000C 0x0000 LCDCTRL y 16 OxiFFF 0010 Ox3FFF 0010 0x0000 CFCTRL Ry 16 Ox1FFF_0014 Ox3FFF_0014 0x0000 PDCTRL R 16 Ox1FFF_0018 Ox3FFF 0018 0x0000 FWCTRL R 16 Ox1FFF_001C Ox3FFF 001C 0x0000 IRQCLREN Ry 16 Ox1FFF_0020 Ox3FFF 0020 0x0000 IRQSETEN R 16 OxiFFF 0024 Ox3FFF_0024 0x0000 IRQCLRMSK V 16 OxiFFF 0028 Ox3FFF 0028 0x0000 IROSETMSK V 16 Ox1FFF_002C Ox3FFF 002C 0x0000 SIGSTAT R 16 OxiFFF 0030 Ox3FFF 0030 a IRQSTAT R 16 OxiFFF 0034 Ox3FFF 0034 0x0000 SWITCHES R 16 OxiFFF 0038 Ox3FFF 0038 GPOUT P 16 Ox1FFF_003C Ox3FFF 003C 0x0000 GPIO DIR V 16 OxiFFF 0040 Ox3FFF 0040 Ox00FF GPIO DOUT y 16 OxiFFF 0044 Ox3FFF 0044 0x0000 GPIO PINSTAT R 8 oxtFFF_0048 Ox3FFF 0048 TST REG INO R 16 Ox1FFF OOEO Ox3FFF 00 EO TST REG IN R 16 Ox1FFF_00E4 Ox3FFF 00 E4 TST REG IN2 R 16 Ox1FFF_00E8 Ox3FFF 00 ES TST REG INS R 16 OxiFFF OOEC Ox3FFF 00 EC TST REG OUTO 4 16 OxiFFF OOFO Ox3FFF OOFO 0x0000 TST REG OUT V 16 Ox1FFF_00F4 Ox3FFF_00F4 0x0000 TST REG OUT2 4 16 Ox1FFF_00F
7. EXM32_AU1250_User Manual V10 doc page 84 of 110 EXM32 AU1250 CPU Module Users Manual 0x0 0000 0008 0x0_OFFF_FFFF DDR MEMORY 256 MByte 0x0_1000_0000 0x0_LLFF_FFFF 1 0 Devices 32 MByte 0x0_1200_0000 0x0_L3FF_FFFF 0x0_1400_0000 0x0_LTFF_FEFE 1 0 Devices 64 MByte xd U000 0000 0x0 Dier FEEF DDR MEMORY Bank 0 D Can 0x0_0800_0000 DDR MEMORY Bank 1 D_CS1 0x0_1800_0000 NO TLB TRANSLATION REQUIRED 512MByte 0x0_LFFF_FFFF Area 0 RCEO NOR Flash IDE 0x0 2000 0000 0x0_2FFF_FFFF Area 1 RCE1 NAND Flash 0x0_3000_0000 0x0_3FFF_FFFF 0x0 5000 0000 0x0_7FFF_FEFF Area 3 RCE3 Peripheral Devices CSA CSB 0x0 8000 0000 OxE_FFFF_FEFF 0xF_0000_0000 ONE Free FEEF Area 2 RCE2 PCMCIA Flash up to 992 x 128 kByte 0x0 1BEE FFFF 0x0_1Fc0_0000 0x0 1FFD FFFF Bootloader 81 x 128 kByte 0x0_1FFE 0000 0x0 1FFE FFFF 0x0_1FFF_0000 PERIPHERAL DEVICES xd 3000 000 0x0 33FF FFFF CSA 64MByte 0x0_3400_0000 0x0 37FE FFFF CSB 64MByte 0x0 3800 0000 0x0 3FFE FFFF 0x0 EFF 0000 QUO JEFE FFFF PERIPHERAL DEVICES RR 000 ONE BEEF FFFF VO x 4000 0000 ONE eer FFFF Attribute OxE 8000 0000 ONE BEEF FFFF Memory Ox C000 0000
8. BIT NAME VALUE DESCRIPTION 15 IRQ15 0 Power Fault Interrupt is disabled EN 1 Power Fault Interrupt is enabled 14 IRQ14 0 12C1 Interrupt is disabled EN 1 12C1 Interrupt is enabled 13 IRQ13 0 I2CDDC Interrupt is disabled EN 1 I2CDDC Interrupt is enabled 12 IRQ12 0 SPI Interrupt is disabled EN 1 SPI Interrupt is enabled 11 IRQ11 0 CFO ATAO interrupt is disabled EN 1 CFO ATAO interrupt is enabled 10 IRQ10 0 CF1 ATA1 interrupt is disabled EN 1 CF1 ATA1 interrupt is enabled 9 IRQ9 0 CFO card detect interrupt is disabled EN 1 CFO card detect interrupt is enabled 8 IRQ8 0 CF1 card detect interrupt is disabled EN 1 CF1 card detect interrupt is enabled 7 IRQ7 0 SD card detect interrupt is disabled EN 1 SD card detect interrupt is enabled 6 IRQ6 0 UARTO Interrupt is disabled EN 1 UARTO Interrupt is enabled 5 IRQ5 0 UART1 Interrupt is disabled EN 1 UARTI Interrupt is enabled 4 IRQ4 0 UART2 Interrupt is disabled EN 1 UART2 Interrupt is enabled 3 IRQ3 0 CANO controller interrupt is disabled EN 1 CANO controller interrupt is enabled 2 IRQ2 0 CAN1 controller interrupt is disabled EN 1 CANT controller interrupt is enabled 1 IRQ1 0 CANO error interrupt is disabled EN 1 CANO error interrupt is enabled 0 IRQO 0 CANI error interrupt is disabled EN 1 CANT error interrupt is enabled EXM32_AU1250_User Manual V10 doc page 64 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 5 1 9 IRQCLREN IRQ Clea
9. Figure 13 EXM32 Au1250 CPU module memory map MSC Vertriebs GmbH Keen 0x0 LEEF OFFF FPGA 0x0_1FFF_1000 0x0_1FFF_17FF 12C1 0x0_1FFF_1800 0x0 IF IF 12C_DDC 0x0 1FFF 2000 0x0 1FFF FEE SPI 0x0_1FFF_3000 0x0_1EFF_3FFF RESERVED 0x0_1FFF_4000 0x0_1FFF_4FFF UART1 COM1 0x0_1FFF_5000 0x0 IFFF SEE UART2 optional 0x0_1FFF_6000 0x0_1FFF_GFFF UART3 optional 0x0_1FFF_7000 0x0 IF 9FFF 0x0_1FFE_ADOO Ox0_1FFF_AFFF ATA IDE 0x0 1FFF 2000 0x0 IF BEEF 0x0_1PFE_COOO 0x0_1EFF_CEFF CANO Optional HW Rev 2 0 0x0_1FFF_DO00 0x0 IF DEF CAN1 Optional HW Rev 2 0 0x0_1FFF_E000 0x0_1EFF_EFFF ETHERNET Ox0_1FFF_FOOO FIREWIRE Optional HW Rev 2 0 Lance 0x0_3FFF_OFFF FPGA 0x0_3FFF_1000 0x0_3FFF_LTEF 1201 0x0_3FFF_1800 0x0_3FFF_LFFF 12C_DDC 0x0_3FFF_2000 0x0_3FFF_2FFF SPI 0x0_3FFF_3000 0x0 3FFF 3FFF RESERVED 0x0 BEEF 4000 0x0_3FFF_AFFF UART1 COM1 0x0_3FFF_5000 0x0_3FFF_SFEF UART2 optional HW Rev 2 0 0x0_3FFF_6000 0x0_3FFF_GFFF UART3 optional HW Rev 2 0 0x0_3FFF_7000 0x0_3FFF_OFFF 0x0 3FFF A000 0x0_3FFF_AFFF ATA IDE 0x0_3FFF_B000 0x0_3FFF_BFFF 0x0_3FFF_C000 0x0_3FFF_CFFF CANO Optional HW Rev 2 0 0x0_36FF_DOQO 0x0_3FFF_DFFF C
10. f l l J JO 0 ID 0 O 0 0 0 BIT NAME VALUE DESCRIPTION 0 15 1 0 14 1 0 13 1 0 12 1 0 11 1 0 10 1 0 9 1 0 8 1 7 GPIO PIN 0 STAT 7 1 6 GPIO_PIN_ 0 STAT 6 1 5 GPIO_PIN_ 0 STAT 5 1 4 GPIO_PIN_ 0 STAT 4 1 3 GPIO PIN 0 STAT 3 1 2 GPIO_PIN_ 0 STAT 2 1 1 GPIO_PIN_ 0 STAT 1 1 0 GPIO_PIN_ 0 STAT 0 1 EXM32_AU1250_User Manual V10 doc page 74 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 5 1 19 Test Register 0 Input Signals OxEO BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P R IR R IR JR R R R R R R IR IR RH IR OR DEFAULT BIT NAME VALUE DESCRIPTION 15 X2D_SDIO_CD 14 X2D_SDIO_WP 13 X1D_DREQO 12 X1D_DREQ1 11 X2D COM1 RXD 10 X2D COM CTS 9 X2A_CAN1_ERR 8 X2A_USB_OC 7 X2A CANO ERR 6 X1A CEO CD 5 X1A CF1 CD 4 X2A FW LINKON 3 X1C ACHT BCLK 2 X1C AC97 SDIN1 1 X1A_CFO_RDY_IRQ O 2JO O O O O O O O O O O O O O 0O O X1A_CF1_RDY_IRQ EXM32_AU1250_User Manual V10 doc page 75 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 5 1 20 Test Register 1 Input Signals OxE4
11. INIT 492Mhz INIT 600Mhz 0x00000049 INIT 0x00000049 INIT 0x00000049 INIT 0x00000049 INIT 336Mhz 396Mhz 492Mhz 492Mhz de eee ee EXM32_AU1250_User Manual V10 doc page 97 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH Static Bus NAND Control Register mem stndctrl Address 0x0 1400 1100 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Es _ _ _ _ y y DEFAULT INIT BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B R _ _ R An R y R N R N R ym R R R R N DEFAULT 0 0 0 0 0 1 INIT 1 0 0 0 0 0 0 0 0 0x00000100 6 4 3 DDR2 Memory Controller Chip Select 0 Timing Register mem sdmodeO Address 0x0 1400 0800 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P fe d d dw wy ae Pe LM Ven Vu a Fav Fav Fay DEFAULT 1 1 1 1 1 1 1 1 1 1 INIT 336Mhz a 0 0 1 0 1 0 0 1 1 1 INIT 396Mhz S 0 0 1 0 1 0 0 1 1 1 INIT 492Mhz 0 1 0 0 1 1 1 0 0 1 INIT 600Mhz 0 0 1 0 1 0 0 1 1 1 BIT 15 14
12. BIT 15 14 13 112 111110 9 8 17 6 5 Va 13 J2 1 lo P ine ie KE ele AE ur D Le 4 SE OIE Le K DEFAULT o lo lo lo lo lo lo lo lo lo lo lo Jo lo lo 1 INIT o jo lo lo o lo lo lo lo jo lo Jo lO lo lo Jo 0x00000000 EXM32_AU1250_User Manual V10 doc page 102 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH Enable GPIOs Block 2 as a Interrupt Source gpio2 inten Address OxO 1170 0010 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 b R IR R R IR R R IR IR IR IR R R IR RR DEFAULT O O 10 0 10 10 0 JO 10 0 O JO JO 0 O JO INIT e e amp E p F A BIT 15 14 13 12 11 11019 8 7 6 5 4 3 2 1 0 W w Gw Lue l w Oe BIEG BE IR R A R LE R DEFAULT 0 0 O 10 10 JO O lO O JO JO 0 lO JO JO 1 INIT 1 0 0 JO O O 10 JO J z 0x00008000 Enable Block 2 gpio2_enable Address 0x0_1170_0014 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ET R IR IR R R R R IR IR IR IR R R IR R DEFAULT O O 10 0 10 0 0 JO 10 0 JO JO JO O O JO INIT 3 x S E E S e 5 5 E BIT 15 14 133 12 1 00 9 Va 7 6 5 4 3 2 1 o pa R R R R R R R IR JR R R IR IR Rwy By DEFAULT o lo lo o o Jo o lo o lo J
13. 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Ki w IW jw IW w w jw jw IW IW W jw jw Jw IW W DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT o 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 15 14 13 12 11 1109 8 7 6 5 4 3 2 1 0 E w IW jw w w w jw jw w W W W jw Jw Jw lw DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT o o 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0x000000A0 EXM32 AU1250 User Manual V10 doc page 108 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH Interrupt STAT Register 1 ic STATset Address 0x0 1180 0070 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E w IW IW IW jw jw jw IW IW jw w w W jw w W DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 BIT 15 14 13 12 11 109 8 7 16 5 4 3 2 1 0 ET w IW jw W w w jw jw W w W Wi Wi Wi ww DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT 0 1 0 0 0 1 0 0 1 0 1 0 0 1 1 1 0xA8014497 EXM32_AU1250_User Manual V10 doc page 109 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 7 Appendix 7 1 ID EEPROM Register Map EEPROM Content Content Field Off Size Format Content hex Example ASCII Remarks set Byte Example Boot Counter 0x000 4 Binary C8 45 00 00 C
14. COMI TXD 46 FR BGE 47 LCD DON 48 reserved don t use 47 COM1 RXD 48 FR EN 49 LCD SHFCLK 50 reserved don t use 49 COM1_RTS 50 FR STB 51 LCD BLON 52 VGA GND 51 COMI CTS 52 FR ERR 1 signal connected only to bottom pad layout 2 signal input on bottom pad layout signal output on top pad layout EXM32_AU1250_User Manual V10 doc page 12 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH Please note that all pins that are marked with reserved don t use must not be used for general purpose hardware They may be used in specific combinations of CPU modules and motherboards 3 2 Connector X1 3 2 1 1 Power Supply All Signals are TTL level signals unless other specified N C not connected LC internal connected not to be used by customer GND logic ground VCC3V3 3 3 VDC 5 main power supply VCC3V3STB 3 3 VDC standby voltage e g for self refreshing SDRAM CPU in sleep mode VCC5VO 5 0 VDC 10 optional power supply VBAT battery voltage e g for real time clock battery is on EXM32 Motherboard 3 2 1 2 SPI Bus Interface Up to two SPI Serial Peripheral Interface bus channels may be provided on EXM32 CPU Modules All signals are LV TTL level signals SPI SCK Serial Clock output signal SPI MOSI Master Output Slave Input signal SPI MISO Master Input Slave Output signal SPI SS lt 1 0 gt Slave Select signals active low 3 2 1 3 Compact Flash Interface
15. EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH ic cfgOset Address 0x0 1180 0040 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E w IW jw IW w w jw jw w w jw jw jw Jw Jw W DEFAULT INIT 1 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 15 14 13 12 11 109 8 7 16 5 4 3 2 1 0 PAN w IW jw W w w jw jw W W W jw jw Jw lw W DEFAULT INIT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x80000000 ic cfgiset Address 0x0 1180 0048 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ET w IW jw IW w w jw jw W W W jw jw Jw Jw w DEFAULT INIT 0 0 1 0 1 0 0 0 0 0 0 0 0 1 BIT 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 Ca w IW IW IW jw jw jw IW IW W w w W jw w W DEFAULT INIT 0 1 0 0 0 1 0 0 1 0 1 1 0 1 1 1 0x280144A7 ic cfg2set Address 0x0 1180 0050 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 D w IW IW IW IW jw W IW IW jw w IW W jw w W DEFAULT INIT 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 BIT 15 14 13 12 11 10 9 8 7 16 5 4 3 2 1 0 PAN w IW jw w w w jw jw W W W Wi
16. MSC EXM32 Au1250 CPU Module User s Manual Revision 1 0 Hardware Revision V5 0 MICROCOMPUTERS SYSTEMS COMPONENTS VERTRIEBS GMBH embedding excellence EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH Preface Copyright Notice Copyright 2008 MSC Vertriebs GmbH All rights reserved Copying of this document and giving it to others and the use or communication of the contents thereof are forbidden without express authority Offenders are liable to the payment of damages All rights are reserved in the event of the grant of a patent or the registration of a utility model or design Important Information This documentation is intended for qualified audience only The product described herein is not an end user product It was developed and manufactured for further processing by trained personnel Disclaimer Although this document has been generated with the utmost care no warranty or liability for correctness or suitability for any particular purpose is implied The information in this document is provided as is and is subject to change without notice EMC Rules This unit has to be installed in a shielded housing If not installed in a properly shielded enclosure and used in accordance with the instruction manual this product may cause radio interference in which case the user may be required to take adequate measures at his or her own expense Trademarks All used product names
17. The Compact Flash interface can be used in 2 Modes Memory Mode and in I O Mode Address and data lines are connected the CPU bus CF lt 1 0 gt _CD These Card Detect pins are connected to GND on the Compact Flash Storage Card or CF Card They are used by the host to determine that the CompactFlash Storage Card or CF Card is fully inserted into its socket CF_SCKSEL Allows to multiplex between 2 CF Slots 0 Slot0 1 Slot glue logic is required is an output of the EXM32 CPU Module CF_CE lt 2 1 gt These input signals are used both to select the card and to indicate to the card whether a byte or a word operation is being performed CE2 always accesses the odd byte of the word CE1 accesses the even byte or the Odd byte of the word depending on AO and CE2 A multiplexing scheme based on AO CE1 and CE2 allows 8 bit hosts to access all data on DO D7 CF IORD Z This signal is not used in PC Card Memory Mode in PC Card VO Mode this signal is an VO Read strobe generated by the host It gates l O data onto the bus from the CompactFlash Storage Card or CF Card when the card is configured to use the I O interface active low CF IOWR This signal is not used in PC Card Memory Mode in PC Card I O Mode the I O Write strobe pulse is used to clock I O data on the Card Data bus into the CompactFlash Storage Card or CF Card controller registers when the CompactFlash Storage Card or CF Card is configured to use the I O interfac
18. 0 0 1 0 1 1 1 1 0 0 1 0 1 0 0 0 INIT 600Mhz O 0 1 0 0 1 1 0 0 0 1 0 0 0 0 0 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PT dle vee Renee DEFAULT 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 INIT 336Mhz O 0 1 1 1 0 1 1 1 1 1 0 1 1 0 1 INIT 396Mhz O 1 0 0 0 1 0 0 1 1 0 1 0 0 0 0 INIT 492Mhz O 1 0 1 0 1 0 1 1 1 1 1 0 1 0 0 INIT 600Mhz O 1 0 0 0 1 0 0 1 0 1 0 0 0 0 0x1F1A3BED INIT 336Mhz 0x262044D0 INIT 396Mhz 0x2F2855F4 INIT 492Mhz 0x262044D0 INIT 600Mhz Chip Select 2 Adress Region Register mem staddr2 Address 0x0 1400 1028 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 My R IR Rella e DEFAULT 0 0 0 0 1 1 1 1 1 1 1 1 1 1 INIT 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ET PaL AE NE JK AE ME AE NE AE LG ae AE XR DEFAULT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 INIT 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0x18003C00 EXM32_AU1250_User Manual V10 doc page 95 of 110 EXM32 AU1250 CPU Module User s Manual 6 4 2 4 Configuration for RCS3 External Devices Chip Select 3 Configuration Register MSC Vertriebs GmbH mem stcfg3 Address 0x0 1400 1030 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P Pan Av Fan w Fav Div Vw IR R Pw Fav Fav Fav dw Di
19. 6 nc not available 7 LCD DOS3 B3 8 I2C1 SCL 7 GP_IN4 not available 8 nc not available 9 LCD DO4 B4 10 ETH ACTLED 9 GP IN3 notavailable 10 nc not available 11 LCD DO5 B5 12 ETH LILED 11 GP_IN2 not available 12 nc not available 13 LCD D06 GO 14 ETH SPLED 13 GP_IN1 notavailable 14 nc not available 15 LCD DO7 G1 16 ETH GND 15 GP INO notavailable 16 nc not available 17 LCD _D08 G2 18 ETH TXD 17 GP OUT7 notavailable 18 SDIO WP 19 LCD DO9 G3 20 ETH TXD 1 19 GP OUT6 notavailable 20 SDIO CLK 21 LCD D10 G4 22 ETH GND 21 GP OUTS notavailable 22 SDIO CD 23 LCD D11 G5 24 ETH RXD 23 GP_OUT4 notavailable 24 SDIO CMD 25 LCD D12 RO 26 ETH RXD 25 GP OUT3 notavailable 26 SDIO DATO 27 LCD D13 R1 28 ETH GND 27 GP OUT2 notavailable 28 SDIO DAT1 IRQ amp 29 LCD D14 R2 30 reserved don t use 29 GP OUT notavailable 30 SDIO DAT2 RW 31 LCD D15 R3 32 reserved don t use 31 GP OUTO notavailable 32 SDIO DAT 33 LCD D16 R4 34 VGA GND 33 reserved don t use 34 CPUIDO e 35 LCD D17 R5 36 reserved don t use 35 MODULE DETECT 36 CPUID1 e 37 LCD VDON 38 VGA GND 37 COMO TXD 38 FR TXD 39 LCD M DE 40 reserved don t use 39 COMO RXD 40 FR RXD 41 LCD VCON 42 VGA GND 41 COMO RTS 42 FR TXEN 43 LCD HSYNC 44 reserved don t use 43 COMO CTS 44 FR RXEN 45 LCD VSYNC 46 VGA GND 45
20. 85 C non operating 40 85 C Humidity rel operating 10 90 non operating 5 95 EMI The EXM32 Au1250 CPU Module is designed to meet DIN EN55022 emission and DIN EN 61000 6 2 immunity when mounted into in an appropriate shielded and grounded enclosure EXM32_AU1250_User Manual V10 doc page 8 of 110 EXM32 AU1250 CPU Module User s Manual 2 3 Mechanical Dimensions MSC Vertriebs GmbH Top View 2 7 6x 85 w pce 5 Location Peg for Location Peg for Bottom Connector Top Connector vo D1 5 4x _ Q 1 5 4x Y 83 La 90 UN 1 UN Expansion p el R A AA Module z A DE 1 6 typ i C i i CPU Side View Module all dimensions in mm Expansion Connector Height A 6 5 Top Component Height B 4 0 CPU Connector Height C 6 5 Bottom Component Height D 2 0 Figure 3 EXM32 Au1250 CPU Module mechanical dimensions 2 4 Connector Positions E Ur Figure 4 EXM32 AU1250 CPU module connector positions EXM32 AU1250 User Manual V10 doc page 9 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 3 Interfaces 3 4 Connectors 3 1 1 EXM32 Connector Pin Definition Orientation Mark oo O Strip A B Strip B Top View X2 O Strip C m D Strip D co
21. B8 8 TXR 0x03 8 8 B8 B 4 1 15 4 Register description 4 1 15 4 1 Prescale Register PRERx This register is used to prescale the SCL clock line Due to the structure of the I C interface the core uses a 5 SCL clock internally The prescale register must be programmed to this 5 SCL frequency minus 1 Change the value of the prescale register only when the EN bit is cleared Example1 I2C Clock 66 MHz desired SCL 100KHz prescale BE 131 dec 83 hex 5 100 KHz 2 effective SCL 100 kHz Example2 12C Clock 66 MHz desired SCL 400KHz prescale LO MES o 1 32 dec 20 hex 5 400 KHz gt effective SCL 400 kHz Reset value OxFFFF EXM32_AU1250_User Manual V10 doc page 43 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 4 1 15 4 2Control register CTR Access Description RW EN FC core enable bit When set to 1 the core is enabled When set to 0 the core is disabled IEN IFC core interrupt enable bit When set to 1 interrupt is enabled When set to 0 interrupt is disabled Reset Value 0x00 The core responds to new commands only when the EN bit is set Pending commands are finished Clear the EN bit only when no transfer is in progress i e after a STOP command or when the command register has the STO bit set When halted during a transfer the core can hang the I C bus 4 1 15 4 3Transmit
22. DEFAULT 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 INIT 336Mhz O 0 1 0 0 0 1 0 0 0 1 0 1 1 0 0 INIT 396Mhz O 0 0 0 0 0 1 0 0 0 1 0 1 1 0 0 INIT 492Mhz 0 1 0 0 0 0 1 0 0 0 1 0 1 1 0 0 INIT 600Mhz O 0 0 0 0 0 1 0 0 0 1 0 1 1 0 0 BIT 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 P Paw Mw FAm dw R Pw Ve Yu Ve Fav Ve Fav Ye Fav Fav Di DEFAULT 0 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 INIT 336Mhz O 0 0 0 0 0 0 0 1 0 0 0 0 0 0 INIT 396Mhz O 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 INIT 492Mhz 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 INIT 600Mhz O 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0x222C00C0 INIT 336Mhz 0x222C00C0 INIT 396Mhz 0x422C00C0 INIT 492Mhz 0x222C00C0 INIT 600Mhz Chip Select 3 Timing Register mem sttime3 Address 0x0 1400 1014 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 73 R RR By Fav Div Me Fav Fav Fav Fav Fav Fav Fav A DEFAULT 0 0 0 1 0 0 0 1 1 1 1 1 1 1 0 0 INIT 336Mhz O 0 0 1 0 0 1 0 0 0 1 1 0 0 0 1 INIT 396Mhz O 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 INIT 492Mhz 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 0 BIT 15 14 13 12 11 109 8 7 16 5 4 3 2 1 0 PN Par wy By w w Vu Vul Vul Pa Pa Vw Vu Ven Die vul vw DEFAULT 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 INIT 336Mhz 1 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 INIT 396Mhz O 0 0 0 0 1 0 1 1 1 0 0 1 1 0 1 INIT 492Mhz 1 0 0 0 1 0 1 0 1 0 0 0 1 1 1 1 INIT 6
23. FAm dw Fav Fav Fav ROP Rw Fav Fav Fav Fav Fav Fay DEFAULT 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 INIT 336Mhz O 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 INIT 396Mhz O 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 INIT 492Mhz O 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 INIT 600Mhz O 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 o Pan Av Fam Die IB Pw Ve dw Ve Fav Fav Fav Fav Fav Fav DA DEFAULT 0 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 INIT 336Mhz O 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 INIT 396Mhz O 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 INIT 492Mhz 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 INIT 600Mhz O 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0x00040042 INIT 336Mhz 0x00040042 INIT 396Mhz 0x00040042 INIT 492Mhz 0x00040042 INIT 600Mhz EXM32 AU1250 User Manual V10 doc page 94 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH Chip Select 2 Timing Register mem sttime2 Address 0x0 1400 1024 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 o Pan Die PA dw w vu vul Div Vw Yw w Vu w Fav Div DA DEFAULT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 INIT 336Mhz O 0 0 1 1 i 1 1 0 0 0 1 1 0 1 0 INIT 396Mhz O 0 1 0 0 1 1 0 0 0 1 0 0 0 0 0 INIT 492Mhz
24. If bit 3 is 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1 Break Control bit 1 the serial out is forced into logic 0 break state 0 break is disabled 7 RW Divisor Latch Access bit 1 The divisor latches can be accessed 0 The normal registers are accessed Reset Value 0000001 1b EXM32 AU1250 User Manual V10 doc page 35 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 4 1 13 2 5Modem Control Register MCR The modem control register allows transferring control signals to a modem connected to the UART Access Description W Data Terminal Ready DTR signal control 0 DTR is 1 1 DTRis 0 W Request To Send RTS signal control 0 RTS is 1 1 RTS is 0 Out1 In loopback mode connected Ring Indicator RI signal input Out2 In loopback mode connected to Data Carrier Detect DCD input Loopback mode 0 normal operation 1 loopback mode When in loopback mode the Serial Output Signal STX PAD O is set to logic 1 The signal of the transmitter shift register is internally connected to the input of the receiver shift register The following connections are made DTR 2 DSR RTS 3 CTS Out1 gt RI Out2 gt DCD RTS CTS Autoflow 0 RTS CTS is exclusively controled by software Set RTS bit in modem control register mcr 1 Read CTS bit in the modem stat
25. rei SE minDelay maxDetay EXM32_AU1250_User Manual V10 doc page 52 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 4 3 3 2 32 bit read timing By Em Bus Clock AU 1200 Tesori Re Typ al Tucs Ten e Twcz ROBY Ri A Le AU1200 Bus State Resta N 3 EI Controller Signals ROEM RIVER RAortem ED Addn Addi 1 0 TIR RD 1517 DatX151 Baptist oor ch aa EN X18_CSBH L X1B CEA i DSi X1B_RB BIZ m 5 15 X18_R8 54110 EXM32 Connector Bus State Controller Signals X1B VUES d Na X1B OER X1B Bang EA 2 8 X18 AS PAAS Oh 2 3 F s 2 5 minTime maxTime x18_0010 A Dai valid 35 Imin Delay maxDetayi EXM32_AU1250_User Manual V10 doc page 53 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 4 4 Power Supply EXM32 Modules are supplied via the EXM32 Elastomeric Connectors X1 and X2 form the EXM32 Motherboards power supplies The maximum available current is e Main supply voltage 3 3 VDC 5 current rating max 8 8A e Optional supply voltage 5 0 VDC 10 current rating max 2 0 A e Battery supply voltage 2 4 3 6 VDC current rating max 100 mA e Standby supply voltage for SDRAM 3 3 VDC 5 current rating max 100 mA EXM32_AU1250_User Manual V10 doc page 54 of 110 EXM32 AU1250 CPU Module User s Manual 5 FPGA Software Driver required MSC Vertriebs G
26. w Pan An DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT 336Mhz 1 0 1 0 0 O JO 0 0 0 JO JO JO 1 0 INIT 396Mhz 1 0 1 0 0 O JO 0 0 0 JO JO JO 1 0 INIT 492Mhz 1 0 1 0 0 O JO 0 O 0 JO JO JO 1 0 INIT 600Mhz 1 0 1 0 0 O JO 0 10 0 JO JO JO 1 0 BIT 15 14 13 12 11 1109 8 7 6 5 4 3 2 1 0 Pan Pan Vu V w Yw w Ye Yu w Pan V Ve w w Fav DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT 336Mhz O 0 0 0 0 0 0 0 0 0 0 1 1 0 0 INIT 396Mhz O 0 0 0 0 0 0 0 0 0 0 1 1 0 0 INIT 492Mhz O 0 1 0 0 0 0 0 0 0 0 1 1 0 0 INIT 600Mhz O 0 0 0 0 0 0 0 0 0 0 1 1 0 0 OxA002000C INIT 336Mhz OxA002000C INIT 396Mhz OxA002000C INIT 492Mhz 0xA002000C INIT 600Mhz 6 4 4 Interrupt Controller Setting up the GPIOs Controller as Interrupts sys pinfunc Address 0x0 1190002C BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P R IR IR R R IR IR R RH R IR R R DEFAULT 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 INIT 1 1 0 0 0 1 1 0 0 0 0 0 1 1 0 0 BIT 15 14 13 12 11 110 9 8 7 6 5 4 3 2 1 0 Hiv Paw Aw w Mw Fa Fav w Fa Fav w Fav Ve Fav Fav Fay DEFAULT 0 1 1 0 0 0 0 0 0 1 1 1 1 INIT 1 1 0 1 0 0 0 1 1 0 0 1 1 0xC60CCCCC EXM32 AU1250 User Manual V10 doc page 101 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH
27. 0 1 INIT 396Mhz O 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 INIT 492Mhz O 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 INIT 600Mhz O 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o Par wy wy w w n Vul vul Pa w Vw Vn Ven Die vul D DEFAULT 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 INIT 336Mhz O 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 INIT 396Mhz O 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 INIT 492Mhz O 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 INIT 600Mhz O 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0x06610002 INIT 336Mhz 0x06610002 INIT 396Mhz 0x06610002 INIT 492Mhz 0x06610002 INIT 600Mhz Chip Select 0 Adress Region Register mem staddrO Address 0x0 1400 1008 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Ki R IR OE ice a eee DEFAULT 0 0 0 1 0 0 0 1 1 1 1 1 1 0 0 INIT 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p lt TE NL Nb SR We GE 2S 4E 25 N IE AL SE A DEFAULT 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 INIT 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0x10003000 EXM32 AU1250 User Manual V10 doc page 92 of 110 EXM32 AU1250 CPU Module User s Manual 6 4 2 2 Configuration for RCS1 NAND Flash Chip Select 1 Configuration Register MSC Vertriebs GmbH mem stcfg1 Address
28. 1 0 1 1 1 0 1 1 1 0 1 0 0 INIT 396Mhz O 1 1 1 0 1 1 1 0 1 1 1 0 1 0 0 INIT 492Mhz 0 1 1 1 0 1 1 1 0 1 1 1 0 1 0 0 INIT 600Mhz O 1 1 1 0 1 1 1 0 1 1 1 0 1 0 0 0x00006664 INIT 336Mhz 0x00007774 INIT 396Mhz 0x00009996 INIT 492Mhz 0x00007774 INIT 600Mhz EXM32 AU1250 User Manual V10 doc page 93 of 110 EXM32 AU1250 CPU Module User s Manual Chip Select 1 Adress Region Register mem staddr1 MSC Vertriebs GmbH Address 0x0 1400 1018 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 D R IR GR Bw Fav Div Vel Div Fav Fav Fav vw Fav Fav A DEFAULT o o To o 1 1 1 1 Vi 1 1 Ja Ja a 1 1 INIT o jojo 1 Jo jo 1 11 Jo Jo Jo Jo Jo Jo fo o BIT 15 14 13 12 11 1019 8 7 6 5 4 3 2 1 Jo gt Ps p GC Ra y Ba Ze 5 Pi By m D R P Ps DEFAULT 1 Te h Ta D feig IA TE x A p D INIT o To 1 1 1 1 lo Jo Jo Jo o Jo Jo Jo fo fo 0x12503C00 6 4 2 3 Configuration for RCS2 Compact Flash PCMCIA Chip Select 2 Configuration Register mem stcfg2 Address 0x0 1400 1020 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Hiv Pan Av
29. 1251_SDIO Figure 12 EXM32 Au1250 audio codec interface SIE Connector Sene Connector SE PSC1 CLK AC97 SDINO SCLK AC97 BCLK BCLK PSC1 SYNC AC RESET RST PSC1 SYNCO AC97 SYNC LRCLK AC97 SYNC SYNC PSC1_D1 l281 SDIO DIN AC97 SDINO DIN PSC1 DO AC97 SDOUT DOUT AC97 SDOUT DOUT PSC1 EXTCLK 125_MCLK MCLK EXM32 AU1250 User Manual V10 doc page 46 of 110 EXM32 AU1250 CPU Module Users Manual MSC Vertriebs GmbH 4 2 Power Management ADDRESSE FPGA_INT FWTOY PWR_OFF PWR_OFF IRQs EXM32 Module Connector SUSPEND SLEEP p a WAKEUP AU_WAKE_IRQ d PWRFLT Figure 13 EXM32 Au1250 power management The complete EXM32 System can be set to power off sleep or hibernate mode by the Au1250 CPU To turn the systems power off the Au1250 has to access the Board Controll Register and set the SW PWR OFF bit Refer to section 6 1 3 BRDCTRL Board Controll Register for details To set the EXM32 System in sleep mode follow the instructions in Au1250 datasheet section 10 4 4 Device Power Management Sleep for details The System can be wake up by asserting the wake up interrupt signals AU_RTC IRQ FPGA_INT AU_WAKE_IRQ Refer to section 7 3 Interrupt handling of this manual and the AU1250 datasheet for details Only the core voltage of the AU1250 is turned off in sleep
30. 13 12 11 1109 8 7 6 5 4 3 2 1 0 E R IR JR IR R R IR IR R R RH R IR IR R DEFAULT O O 10 10 O 0 O 10 JO 10 10 O O 10 JO 0 BIT NAME VALUE DESCRIPTION 15 IRQ15 0 no power fault interrupt STAT 1 pending power fault interrupt 14 IRQ14 0 no 12C1 interrupt request STAT 1 Pending 12C1 interrupt request 13 IRQ13 0 no I2CDDC interrupt request STAT 1 pending I2CDDC interrupt request 12 IRQ12 0 no SPI interrupt request STAT 1 pending SPI interrupt request 11 IRQ11 0 no CFO ATAO interrupt STAT 1 pending CFO ATAO interrupt 10 IRQ10 0 no CF1 ATA1 interrupt STAT 1 pending CF1 ATA1 interrupt 0 no CFO card detect interrupt 9 IRQ9 writing a 0 has no effect STAT 1 pending CFO card detect interrupt writing a 1 clears the interrupt status bit to 0 0 no CF1 card detect interrupt 8 IRQ8 writing a 0 has no effect STAT 1 pending CF1 card detect interrupt writing a 1 clears the interrupt status bit to 0 0 no SD card detect interrupt 7 IRQ7 writing a 0 has no effect STAT 1 pending SD card detect interrupt writing a 1 clears the interrupt status bit to 0 6 IRQ6 0 no UARTO interrupt request STAT 1 pending UARTO interrupt request 5 IRQ5 0 no UARTI interrupt request STAT 1 pending UART1 interrupt request 4 IRQ4 0 no UART2 interrupt request STAT 1 pending UART2 interrupt request 3 IRQ3 0 no CANO controller interrupt request STAT 1 pending CANO controller interrupt request 2 IRQ2 0 no CANI controller interrupt request STAT 1 pending CANT
31. 20 19 18 17 16 Pan Fan Pan aw Fw Fav w Fav Ye w w w Pan V DEFAULT 1 0 0 0 1 1 1 1 1 1 1 1 1 INIT 336Mhz O 1 1 0 JO 0 1 0 0 0 1 0 0 INIT 396Mhz O 1 1 0 0 0 1 0 1 0 JO O B INIT 492Mhz O 1 1 0 JO 0 1 1 0 0 1 0 0 INIT 600Mhz O 1 1 o 0 0 1 0 1 0 JO x 0 0 BIT 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 My Pan Di Div Fav dw Fav Fav Yu Div Fav w Vw Ye Fav Fav DA DEFAULT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 INIT 336Mhz O 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 INIT 396Mhz O 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 INIT 492Mhz 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 INIT 600Mhz O 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0x31100520 INIT 336Mhz 0x3140060A INIT 396Mhz 0x31900781 INIT 492Mhz 0x3140060A INIT 600Mhz EXM32_AU1250_User Manual V10 doc page 100 of 110 EXM32 AU1250 CPU Module User s Manual Global Configuration Register B mem sdconfigb MSC Vertriebs GmbH Address 0x0 1400 0848 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P Pan aw Fav Fav Yw Ye Ve e Fav Fav w Ve
32. AU1250 CPU Module Users Manual MSC Vertriebs GmbH 4 3 2 16 write timing Dre rec re are I I l 1 l I I I I I I 1 I I I By Em Bus Clock AU 1200 ACER TT Twcz RIES n LL AU1200 Bus State ar Controller Signals RADE 0 i ROSA ef m D TCA A sn X1B CLKOUT pO X1B_CSAH X18 CSBH X1B RBERZ NEL 5 15 5 15 m gt xs aeri PES 5 x La 5 15 EXM32 Connector Bus MENS EE Nb State Controller Signals X1B OEN mj En xi Me El a Ly DA X1B_A 2SI C S Addis zB 7 22 Si minTene maxTime xi opum RE QT AE UD minDelay maxDelay EXM32_AU1250_User Manual V10 doc page 50 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 4 3 3 32 Bit optional DATA 31 16 16 Bit Data Buffer EXM32 Module Connector DATA 15 0 16 Bit Data Latch DATA 16 0 Figure 14 EXM32 Au1250 32 Bit Bus The AU1250 CPU Module is available with an optional 32 bit data bus X1B_D 31 0 In the 32 bit version two consecutive 16 bit accesses are necessary With the first 16 bit access the lower 16 bit are stored in a data latch With the second beat the upper 16 bit of the 32 bit word are issued by the AU1250 During the second beat the complete 32 bit word is available on X1B D 31 0 The control signals for the data latch the data buffer and the EXM32 bus state controller are issued by th
33. Also four bits also provide an indication in the state of one of the modem status lines These bits are set to 1 when a change in corresponding line has been detected and they are reset when the register is being read Bit Access Description R Delta Clear To Send DCTS indicator 1 The CTS line has changed its state Delta Data Set Ready DDSR indicator 1 The DSR line has changed its state Trailing Edge of Ring Indicator TERI detector The RI line has changed its state from low to high state Delta Data Carrier Detect DDCD indicator 1 The DCD line has changed its state EXM32_AU1250_User Manual V10 doc page 37 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 4 1 13 2 8Divisor Latches The divisor latches can be accessed by setting the 7 bit of LCR to 1 You should restore this bit to 0 after setting the divisor latches in order to restore access to the other registers that occupy the same addresses The 2 bytes form one 16 bit register which is internally accessed as a single number You should therefore set all 2 bytes of the register to ensure normal operation The register is set to the default value of 0 on reset which disables all serial VO operations in order to ensure explicit setup of the register in the software The value set should be equal to system clock speed 16 x desired baud rate The internal counter starts to work when the L
34. DOUT 7 write operation is enabled 14 GEO DOU 0 GPIO DOUT 6 write operation is disabled T EN 6 1 GPIO DOUT 6 write operation is enabled 13 GEO DOU 0 GPIO DOUT 5 write operation is disabled T_EN 5 1 GPIO DOUT 5 write operation is enabled 19 GPIO DOU 0 GPIO DOUT 4 write operation is disabled T EN 4 1 GPIO DOUT 4 write operation is enabled 41 GPIO DOU 0 GPIO DOUT 3 write operation is disabled T_EN S 1 GPIO DOUT 3 write operation is enabled 10 GEO DOU 0 GPIO DOUT 2 write operation is disabled T EN 2 1 GPIO DOUT 2 write operation is enabled g GPIO DOU 0 GPIO DOUT 1 write operation is disabled T_EN 1 1 GPIO DOUT 1 write operation is enabled g GPIO_DOU 0 GPIO DOUT 0 write operation is disabled T EN 0 1 GPIO DOUT 0 write operation is enabled 7 GPIO_DOU 0 T 7 1 e GPIO_DOU 0 T 6 1 5 GPIO DOU 0 T 5 1 4 GPIO DOU 0 T I4 1 3 GPIO DOU 0 TIS 1 2 GPIO_DOU 0 T 2 1 4 GPIO DOU 0 Ti 1 o GPIO DOU 0 T 0 1 EXM32_AU1250_User Manual V10 doc page 73 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 5 1 18 GPIO Pin Status Register 0x48 BIT 15 14 13 12 11 109 8 7 6 5 4 13 2 1 0 ET R IR IR IR IR IR IR R IR IR RH IR IR IR IR R DEFAULT
35. EN 1 CAN1 controller interrupt is enabled 1 IRQ1 0 CANO error interrupt is disabled EN 1 CANO error interrupt is enabled 0 IRQO 0 CANI error interrupt is disabled EN 1 CANT error interrupt is enabled EXM32 AU1250 User Manual V10 doc page 65 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 5 1 10 IROSETMSK IRQ Set Mask Register Offset 0x28 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pM w vw Aw dw rw w w w vw w dw w e w w D DEFAULT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BIT NAME VALUE DESCRIPTION 15 IRQ15 0 Power Fault Interrupt is disabled MASK 1 Power Fault Interrupt is masked 14 IRQ14 0 I2C1 Interrupt is disabled MASK 1 I2C1 Interrupt is masked 13 IRQ13 0 I2CDDC Interrupt is disabled MASK 1 I2CDDC Interrupt is masked 12 IRQ12 0 SPI Interrupt is disabled MASK 1 SPI Interrupt is masked 11 IRQ11 0 CFO ATAO interrupt is disabled MASK 1 CFO ATAO interrupt is masked 10 IRQ10 0 CF1 ATA1 interrupt is disabled MASK 1 CF1 ATA1 interrupt is masked 9 IRQ9 0 CFO card detect interrupt is disabled MASK 1 CFO card detect interrupt is masked 8 IRQ8 0 CF1 card detect interrupt is disabled MASK 1 CF1 card detect interrupt is masked 7 IRQ7 0 SD card detect interrupt is disabled MASK 1 SD card detect interrupt i
36. FFER GPOUT 5 GPOUT 7 s GPOUT 7 0 Data Addr XM32 Module Connector E LCD2 ENABLE LCD D2 7 0J GP IN 7 0 Figure 8 EXM32 LCD2 Interface To set the LCD Interface in GPIO Mode reset Bit 5 in BRDCTRL Resister 6 1 3 BRDCTRL Board Control Register Signal LCD2 ENABLE reflects the Status of Bit 5 to the EXM Connector It can be used to control external buffers on the Motherboard If LCD mode is disabled the GPOUT Register Baseaddress Ox3FFF 003C takes control of the Signals LCD2 D 8 15 GP OUT 7 0 Refer to section 6 1 16 GPOUT General Purpose Output Register LCD Mode GPIO Mode BRD CTRL B LCD2 EN 0 BRD CTRL B LCD2 EN 1 EXM32 Connector Signals Baseaddress 0x3FFF0008 Baseaddress 0x3FFF0008 AU 1258 AU1250 CIM D9 D2 GPIO 209 202 CIM D9 D2 GPIO 209 202 Refer to AU1250 Datasheet to GPI 7 0 LCD2_D 7 0 set these pins to Camera Interface Mode Refer to AU1250 Datasheet to set these pins to GPIN Mode AU1250 LCD2 17 GPOUTI7 24 Bit TFT Baseaddress 0x3FFF003C GPOI VLCD2 DIe AU1250 LCD D 16 GPIO 211 GPOUTIG 24 Bit TFT Baseaddress 0x3FFF003C GPOI6VLCD2 DIe EXM32 AU1250 User Manual V10 doc page 30 of 110 EXM32 AU1250 CPU Module Users Manual MSC Vertriebs GmbH Ee iii GPO S LCD2_D 10 eg aau MA HEP ders M GPORICGDE DEMI dd DE d WEZ MM GPOISILODE HE idi GE di Se GPO 2 LCD2 D 13 DEE ai SERIES HE EE ee el e
37. Input Signals OxEC BIT 15 14 13 12 11 10 9 8 7 6 5 la 13 2 1 To y R R IR IR IR R R IR R R IR R JR R R IR DEFALET EEE ES PS PO PES mme E BIT NAME VALUE DESCRIPTION 15 14 13 12 11 10 2 X1B_RDY EXM32_AU1250_User Manual V10 doc page 79 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 5 1 23 Test Register 0 Output Signals 0xF0 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 y Ra w Bay wy Phy Bey Bn Phy B Ban Bi Bey Fay Pay By My DEFAULT 010100101010 010010100000 BIT NAME VALUE DESCRIPTION 15 X2A CANO EN 14 X2A FW LPS 13 X1A CF1 RESET 12 X2D_COM1_RTS 11 X2D_COM1_TXD 10 X2C_LCD_DON 9 X2C_LCD_VCON 8 X2C_LCD_BLON 7 X2C_LCD_VDON 6 X1A_CF1_PWEN 5 X1A_CFO_PWEN 4 X1A_CFO_RESET 3 X1A_SPI_SCK 2 X1A_SPI_SSOH 1 X1A SPI SS1 0 X1A_SPI_MOSI O O O O O O O O O O O O O O O O EXM32_AU1250_User Manual V10 doc page 80 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertrieb
38. OC 0 USB Overcurrent 1 USB no Overcurrent 10 SDIO 0 SD Card is fully accessible WP 1 SD Card is write protected 9 s 0 1 8 FLASH 0 Flash device is busy BUSY 1 Flash device is idle 0 j 1 6 SWAP 0 boot from ROM BOOT 1 boot from FLASH 00 reserved 5 01 CPU Module 1 4 EN ug CPU Module 2 11 CPU Module 3 00 3 3 V default 3 CF1 01 3 3Vor5 0V 2 VS 10 3 3 V 11 5 0 V 00 3 3 V default 1 CFO 01 3 3 Vor 5 0 V 0 VS 10 3 3 V 11 5 0 V EXM32_AU1250_User Manual V10 doc page 58 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 5 1 3 BRDCTRL Board Control Register Offset 0x08 entspricht SYSTEM CONTROL und CONTROL RESETS BIT 15 14 13 12 11 110 9 8 7 6 5 14 3 2 1 0 W Pw WIR IR JR IR IR IR JR Pu Pw Pw n w D DEFAULT O 10 1 10 O 10 O lO JO O 10 O O JO JO 0 BIT NAME VALUE DESCRIPTION 15 SW 0 De assert System Reset RST 1 Assert System Reset 14 SW PWR 0 no change OFF 1 turn off power supply 13 PSC1 0 AC97 selection CFG 1 I2S selection default 0 12 1 0 11 1 0 normal operation Default PCE 1 set system to hibernate mode 9 g 0 1 0 8 1 7 Test 0 Test Mode is deactivated 6 Mode 1 Test Mode is activated Certain EXM Signals can be set read manually Enable in TST REG IN OUT V0 6 Update 5 LCD2 0 LC
39. Storage Card or CF Card has been configured for I O operation this signal is used as Interrupt Request This line is strobed low to generate a pulse mode interrupt or held low for a level mode interrupt When the pin is high this signal resets the CompactFlash Storage Card or CF Card The CompactFlash Storage Card or CF Card is reset only at power up if this pin is left high or open from power up The CompactFlash Storage Card or CF Card is also reset when the Soft Reset bit in the Card Configuration Option Register is set When the pin is set high the power supply for Compact Flash socket is enabled in PC Card Memory Mode This is a signal driven by the host and used for strobing memory write data to the registers of the CompactFlash Storage Card or CF Card when the card is configured in the memory interface mode It is also used for writing the configuration registers in PC Card I O Mode In PC Card VO Mode this signal is used for writing the configuration registers only The WAIT signal is driven low by the CompactFlash Storage Card or CF Card to signal the host to delay completion of a memory or VO cycle that is in progress in PC Card Memory Mode Used as Write Protect signal The CompactFlash Storage Card or CF Card does not have a write protect switch This signal is held low after the completion of the reset initialization sequence in PC Card I O Mode When the CompactFlash Storage Card or CF Card is configured f
40. Wi Www DEFAULT INIT 0 1 0 0 0 1 0 0 1 0 1 1 0 1 1 1 0x280144A7 EXM32_AU1250_User Manual V10 doc page 107 of 110 EXM32 AU1250 CPU Module User s Manual Interrupt Controller 1 Source Select Register MSC Vertriebs GmbH ic srcset Address OxO 1180 0058 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E w IW jw IW w w jw jw W W W W jw Jw ww DEFAULT INIT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BIT 15 14 13 12 111 1109 8 7 6 5 4 3 2 1 0 ET w IW jw w w w jw jw W W W Wi Wi Wi ww DEFAULT INIT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 OxFFFFFFFF Interrupt Assignment Register 1 ic assignset Address 0x0 1180 0060 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AN w IW jw w w w jw jw W W W jw jw Jw Jw lw DEFAULT INIT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BIT 15 14 13 12 11 110 9 8 7 6 5 4 3 2 1 0 ET w IW jw w w w jw jw W W W jw jw Jw lw W DEFAULT INIT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 OxFFFFFFFF Wake up Source Selection ic wakeset Address 0x0 1180 0068 BIT 31
41. controller interrupt request 1 IRQ1 0 no CANO error interrupt request STAT 1 pending CANO error interrupt request 0 IRQO 0 no CANI error interrupt request STAT 1 pending CAN error interrupt request EXM32 AU1250 User Manual V10 doc page 69 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 5 1 14 SWITCHES Board Configuration Register Offset 0x38 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W R R R R R In R R R TR DEFAULT 0 O 10 O O 10 JO 10 1 lO 10 JO O 1 1 1 BIT NAME VALUE DESCRIPTION 0 15 1 0 14 0 13 1 0 12 1 0 11 1 0 10 1 0 a 1 0 S j 1 0 Big Endian 1 Little Endian The Value in this Register sets the maximum CPU Clock Frequency Switches 6 3 Frequency Mhz x 1011 600 6 3 s 6 3 1101 492 1110 396 1111 336 0 gt SE 1 Default 1 SI d 1 Default 0 SPE op i Default EXM32_AU1250_User Manual V10 doc page 70 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 5 1 15 GPOUT General Purpose Output Register 0x3C BIT 15 14 13 12 11 10 9 PW R R R R R R N N N N N N N N DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 co N o u R co N nd o JD JD a
42. data input via the TDI pin Its protocol conforms to the JTAG standard EXM32 AU1250 User Manual V10 doc page 17 of 110 EXM32 AU1250 CPU Module User s Manual JTAG_TRST Module MSC Vertriebs GmbH JTAG Reset signal is received asynchronously with TCK signal Asserting this signal resets the JTAG interface circuit 3 3 1 5 MOST Media Local Bus Interface not available on the EXM32 AU1250 CPU All signals are LV TTL level signals 3 3 1 6 CAN 5 pin mode default 3 pin mode clock input clock input MLBCLK signal information input no function signal information output signal information in out MLBSIG data input no function data output data in out MLBDAT Up to two CAN Bus Interfaces are provided on EXM32 CPU Modules All signals are LV TTL level signals External CAN Transceivers are required to convert the LV TTL signals to the physical CAN interface CAN 1 0 TX CAN lt 1 0 gt _RX CAN lt 1 0 gt _ERR CAN lt 1 0 gt _EN CAN lt 1 0 gt _STB CAN Bus Transmit CAN Bus Receive CAN Bus Error Flag active low CAN Transceiver Enable active high CAN Transceiver Standby active low 3 3 1 7 Serial Audio Interface Up to two digital audio interfaces provided on the EXM32 CPU Modules All signals are LV TTL level signals Audio Channel 0 DAO SPDIF DAO MCLK DAO SCLK DAO LRCLK DAO SDINO Audio Channel 1 DA1 SPDIF DA1 MCLK DA SCLK DA1 LRCLK DA1 SDOUTO Digital Audio signal IEC 609
43. don t use 43 PS0 LRCLK 44 en SCK 43 PCIE GND 44 45 PS1_LRCLK 46 PS1 SCK 45 PCIE_GND 46 PCIE GND AC 97 SDOUT reserved don t use 47 AC GND 48 PS0 SDIO 47 PCIE GND 48 AC 97 BCLK reserved don t use 49 PS MCLK 50 1251_SDIO 49 PCIE_GND 50 51 AC_GND 52 reserved don t use 51 PCIE_GND 52 PCIE_GND EXM32_AU1250_User Manual V10 doc page 11 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH Connector X2 Interfaces Strip A Strip B Pin Signal Pin Signal Pin Signal Pin Signal 1 FW GND 2 reserved don t use 1 DA GND 2 DA GND 3 reserved don t use 4 reserved don t use 3 DAO SPDIF 4 DA1 SPDIF 5 reserved don t use 6 reserved don t use 5 DA GND 6 DA GND 7 FW GND 8 reserved don t use 7 DAO MCLK 8 DA1 MCLK 9 reserved don t use 10 reserved don t use 9 DA GND 10 DA GND 11 reserved don t use 12 reserved don t use 11 DAO SCLK 12 DA1 SCLK 13 FW GND 14 JTAG TDO 13 DAO LRCLK 14 DA1 LRCLK 15 reserved don tuse 16 JTAG TDI 15 DAO SDINO 16 DA1 SDOUTO 17 reserved don t use 1
44. from the CPU Module Clock GND used for shielding controlled impedance Interrupt Request from Extension Modules active low IRQ_EXTO has highest priority Interrupt Request from Motherboard active low IRQ_MBO has highest priority DMA Request Inputs are used by external devices to indicate whether they need service from the CPU modules DMA controller active low not available on the EXM32 AU1250 CPU Module DMA Request Acknowledge outputs notifies acceptance of DMA transfer request to external device which has output DREQ active low not available on the EXM32 AU1250 CPU Module DMA Acknowledge outputs notification Strobe output to external device which has output DREQ active low not available on the EXM32 AU1250 CPU Module Module input indicates that the primary power supply voltage of the motherboard is dropping below the operating voltage range This signal can be used to save a limited amount of data in a non volatile memory before the CPU shuts down or to enter sleep mode using VCC BAT Sleep output this signal is used to indicate the CPUs sleep mode to external devices active low Power Off Suspend output this signal is used to shutdown supply voltages only VSTBY and VBAT may be available active high Wakeup CPU from Sleep mode input for CPU module active high 3 2 1 5 Audio Codec AC 97 I S Interface Serial data can be received from and transmitted to an AC 97 or PS codec that may be mounted on the mo
45. programming voltage is disabled when the output is LOW To enable or disable the write protection access to the internal registers of the FPGA is necessary The device driver must support this feature For detailed description of the memory space mapping please refer to chapter 6 2 Off chip Memory Map 4 1 5 NAND Flash The Au1250 CPU module is availabel with a optional 8 Bit NAND Flash assembly The EXM32 CPU Module supports write protection for NAND Flash Memory When the output is HIGH the Flash Memory is fully accessible The card is write protected when the output is LOW To enable or disable the write protection access to the internal registers of the FPGA is necessary The device driver must support this feature 4 1 6 DDR2 SDRAM The EXM32 Au1250 CPU Module provides up to 256 Mbyte DDR2 SDRAM The CPU Module uses two DDR2 banks each bank with two memory modules Each memory module is organised x16 bit in order to provide the 32 bit wide working memory directly interfaced to the CPU All SDRAM signals are driven directly by the processor For detailed description of the memory space mapping and for detailed setup and initialization of the Au1250 SDRAM Controller please refer to chapter 6 2 Off chip Memory Map 4 1 7 Ethernet The EXM32 Au1250 CPU Module is equipped with an SMSC LAN91C1111 Single Chip MAC PHY to support 10 100BaseT Ethernet Power saving modes can be controlled individually for the MAC and the PHY by s
46. register TXR Bit Access Description 7 W Next byte to transmit via fC W In case of a data transfer this bit represent the data s LSB In case of a slave address transfer this bit represents the RW bit 1 reading from slave 0 writing to slave Reset value 0x00 4 1 15 4 4 Receive register RXR Bit Access Description 7 0 R Last byte received via FC Reset value 0x00 4 1 15 4 5 Command register CR Bit Access Description STA generate repeated start condition STO generate stop condition RD read from slave WR write to slave ACK when a receiver sent ACK ACK 0 or NACK ACK 1 Reserved IACK Interrupt acknowledge When set clears a pending interrupt Reset Value 0x00 The STA STO RD WR and IACK bits are cleared automatically These bits are always read as zeros EXM32_AU1250_User Manual V10 doc page 44 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 4 1 15 4 6 Status register SR Description RxACK Received acknowledge from slave This flag represents acknowledge from the addressed slave 1 No acknowledge received 0 Acknowledge received Busy TC bus busy 1 after START signal detected 0 after STOP signal detected AL Arbitration lost This bit is set when the core lost arbitration Arbitration is lost when e a STOP signal is detected but non requested e The master drives SDA h
47. 0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 b w IW jw W iw IW iw W w jw WM IW w W DEFAULT INIT 0 o 0 JO 0 0 0 0 0 JO 0 0 BIT 15 14 13 12 111109 18 7 6 5 14 3 2 1 10 E w IW IW IW IW IW jw Jw W W W W WW W W DEFAULT INIT 0 JO 0 O 10 0 0 JO JO O JO JO 0 0x00000000 ic_cfg1set Address 0x0_1040_0048 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ES w IW jw jw iw jw W W IW jw W WW W w IW DEFAULT INIT 0 1 10 JO JO O 0 0 0 0 JO O 0 BIT 15 14 13 12 111109 8 7 16 5 4 3 2 1 O0 Ca w IW IW IW w IW IW IW W W W W W IW W W DEFAULT INIT 0 JO 10 O 10 0 O 0 JO lO JO JO 0 0x10000000 EXM32 AU1250 User Manual V10 doc page 104 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH ic cfg2set Address 0x0 1040 0050 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E w IW jw IW w w jw jw W W W yw jw Jw Jw w DEFAULT INIT 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 BIT 15 14 13 12 11
48. 0 PWRELT active low STAT 1 PWRFLT active low 14 SIG14 0 I2C1_IRQ active low STAT 1 I2C1 IRO active low 13 SIG13 0 I2CDDC IRQX active low STAT 1 I2CDDC IRQX active low 12 SIG12 0 SPI IRQ active high STAT 1 SPI IRQ active high 0 CEO IRQX active low T SIG11 ATAO IRQ active high STAT 1 CFO_IRQ active low ATAO_IRQ active high 0 CF1_IRQ active low 10 SIG10 ATA1_IRQ active high STAT 1 CF1 IRQ amp active low ATA1 IRQ active high 9 SIG9 0 CEO CD active low STAT 1 CFO_CD active low 8 SIG8 0 CF1 CD active low STAT 1 CF1_CD active low 7 SIG7 0 SDIO_CD active low STAT 1 SDIO_CD active low 6 SIG6 0 UARTO IRQ active high STAT 1 UARTO IRQ active high 5 SIG5 0 UART1 IRQ active high STAT 1 UART1 IRQ active high 4 SIG4 0 UART2 IRQ active high STAT 1 UART2 IRQ active high 3 SIG3 0 CANO IRQX active low STAT 1 CANO IRQX active low 2 SIG2 0 CAN1 IRQX active low STAT 1 CAN1 IRQX active low 1 SIG1 0 CANO ERR active low STAT 1 CANO ERR active low 0 SIGO 0 CANT ERR active low STAT 1 CANT ERR active low EXM32 AU1250 User Manual V10 doc page 68 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 5 1 13 IRQSTAT IRQ Status Register Offset 0x34 BIT 15 14
49. 00Mhz O 0 0 0 0 1 0 1 1 1 0 0 1 1 0 1 0x1231C58B INIT 336Mhz 0x123205CD INIT 396Mhz 0x22428A8F INIT 492Mhz 0x123205CD INIT 600Mhz EXM32_AU1250_User Manual V10 doc page 96 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH Chip Select 3 Adress Region Register mem staddr3 Address 0x0 1400 1018 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 D R IR GR wy Mw Div Vel Div Vw Fav Fav Fav Fav A DEFAULT 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 INIT 0 0 0 1 0 1 0 O O O O O JO JO lO 0 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gt Ba P Pd PU Ba Ze P E P Pg Ze b P Z BG DEFAULT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 INIT 0 0 1 1 1 1 0 0 10 O O JO JO JO IO 0 0x14003C00 6 4 2 5 Global Chip Select Configuration Addresslatch Timing Register mem staltime Address 0x0 1400 1040 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 hii E E 5 d T 2 E E 3 8 z z DEFAULT INIT 336Mhz INIT 396Mhz INIT 492Mhz INIT 600Mhz BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w fe d bk b b b w Ve Ve Vw w w w w w DEFAULT z 1 INIT 336Mhz 0 INIT 396Mhz E z 0 0 0
50. 1 1 1 1 1 0 0 0 1 0 1 0 1 0 INIT 336Mhz O 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 INIT 396Mhz O 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 INIT 492Mhz 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 INIT 600Mhz O 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 BIT 15 14 13 12 11 109 8 7 16 5 4 3 2 1 0 Av Pan Aw FAm w R Pw dw Fav Fav Fav Fav Fav Fav Fav Fav Di DEFAULT 0 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 INIT 336Mhz O 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 INIT 396Mhz O 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 EXM32_AU1250_User Manual V10 doc page 91 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH INIT 492Mhz O 1 1 10 10 JO 0 10 11 1 0 0 JO JO JO JO INIT 600Mhz O 1 O O 10 10 JO 10 1 1 0 IO JO JO JO 0 0x003D40C0 INIT 3 0x003D40C0 INIT 0x003D60C0 INIT 0x003D40C0 INIT 36Mhz 396Mhz 492Mhz 600Mhz a Chip Select 0 Timing Register mem sttime0 Address 0x0 1400 1004 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E la ee eae les ae n DEFAULT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 INIT 336Mhz O 0 0 0 0 1 1 0 0 1 1 0 0 0
51. 1081L datasheet for details 4 1 10 Camera Interface The LCD 2 interface available at the EXM32 connector is directly connected to the Au1250 CPU Camera Interface 8 bit data For details refer to the AU1250 Datasheet LCD2 SHFCLK LCD2 HSYNC LCD2 VSYNC EXM32 Module Connector LCD2_D 0 LCD2 D 7 Figure 7 EXM32 AU1250 CPU module camera interface EXM32 Connector Camera Interface Signal LCD2 D OJGP IN 7 CIM D2 LCD2_D 1 GP_IN 6 CIM_D3 LCD2_D 2 GP_IN 5 CIM_D4 LCD2_D 3 GP_IN 4 CIM_D5 LCD2_D 4 GP_IN 3 CIM_D6 LCD2_D 5 GP_IN 2 CIM_D7 LCD2_D 6 GP_IN 1 CIM_D8 LCD2_D 7 GP_IN 0 CIM_D9 EXM32_AU1250_User Manual V10 doc page 29 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 4 1 11 GPIO LCD2 Interface V0 5 Update The AU1250 LCD2 Interface can be used either in LCD2 or GPIO mode The Camera Interface of the AU1250 CPU is directly connected to the dual function pins LCD2_D 7 0 GP_IN 7 0 on the EXM Connector Refer to the AU1250 Datasheet to set these pins in GPIN Mode if necessary The MSB of the LCD2 Interface LCD2 D 8 15 GP OUT 7 0 can be used either in GROUT Mode or in LCD Mode If 24 Bit TFT Mode on LCD 1 Interface is necessary the LCD 2 interface is used to provide the additional 6 Bit to the EXM Connector see Table 6 LCD D 17 0 LCD 17 0GPOUT 7 0 EE LCD D2 17 8 GP OUT 7 0 LCD DISVLCD D 17 BU
52. 109 8 7 16 5 A4 3 2 1 0 PAN w IW jw w w w jw jw W w W w jw Jw Jw W DEFAULT INIT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x10000000 Interrupt Controller 0 Source Select Register ic srcset Address 0x0 1040 0058 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ET w IW jw w w w jw jw W W W Wi Wi Www DEFAULT INIT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BIT 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 Ca w IW IW IW W IW W iw IW W W w W jw w W DEFAULT INIT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 OxFFFFFFFF Interrupt Assignment Register 0 ic assignset Address 0x0 1040 0060 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PAN w IW jw W w w jw jw W W Pw jw jw Jw lw W DEFAULT INIT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BIT 15 14 13 12 11 109 8 7 16 5 4 3 2 1 0 m w IW jw w w w jw jw w W W jw jw Jw Jw W DEFAULT INIT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 OxFFFFFFFF EXM32 AU1250 User Manual V10 doc page 105 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH Interrupt STAT Register 0 ic STATset Address 0x0 1040 0070 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E w IW I
53. 13 12 11 109 8 7 6 5 A4 3 2 Bu _ Bo n VT _ p UT Um i Ki B UT 5 p Ki KC DEFAULT 1 1 1 1 1 1 1 1 1 1 1 1 INIT 336Mhz 0 1 0 0 1 0 0 1 0 1 0 0 INIT 396Mhz 0 1 0 0 1 0 0 1 0 1 0 0 INIT 492Mhz 0 1 1 0 1 1 0 1 1 1 0 1 INIT 600Mhz 0 1 0 0 1 0 0 1 0 1 0 0 0x01272224 INIT 336Mhz 0x01272224 INIT 396Mhz 0x02393335 INIT 492Mhz 0x01272224 INIT 600Mhz EXM32 AU1250 User Manual V10 doc page 98 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH Chip Select 1 Timing Register mem _sdmode1 Address 0x0 1400 0808 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Du _ _ _ _ _ Sa E P _ Pi M Se e P s DEFAULT 1 1 1 1 1 1 1 1 1 1 INIT 336Mhz 0 0 1 0 1 0 0 1 1 1 INIT 396Mhz 0 0 1 0 1 0 0 1 1 1 INIT 492Mhz 0 1 0 0 1 1 1 0 0 1 INIT 600Mhz 0 0 1 0 1 0 0 1 1 1 BIT 15 14 13 12 11 1109 8 7 6 5 4 3 2 0 E jo P E _ Ba Ze P S P Ba P 3 Ps P Ba DEFAULT 1 1 1 1 1 1 1 1 1 1 1 1 INIT 336Mhz 0 1 0 0 1 0 0 1 0 1 0 0 INIT 396Mhz 0 1 0 0 1 0 0 1 0 1 0 0 INIT 492Mhz 0 1 1 0 1 1 0 1 1 1 0 1 INIT 600Mhz 0 1 0 0 1 0 0 1 0 1 0 0 0x012
54. 50 CPU Module User s Manual 6 4 Au1250 Initialisation 6 4 1 Clock CPU PLL Control preliminary MSC Vertriebs GmbH sys cpupll Address 0x0 1190 0060 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E B E S T E E i S S S 5 S 7 3 z DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT 336Mhz 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT 396Mhz O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT 492Mhz 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT 600Mhz O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 15 14 13 12 111 1109 8 7 6 5 4 3 2 1 0 E _ _ _ i _ _ E E p P is P P S DEFAULT 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 INIT 336Mhz O 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 INIT 396Mhz O 0 0 0 0 0 0 0 0 0 1 0 0 0 0 i INIT 492Mhz 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 INIT 600Mhz O 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0x0000001C INIT 336Mhz 0x00000021 INIT 396Mhz 0x00000029 INIT 492Mhz 0x00000032 INIT 600Mhz 6 4 2 Bus State Controller 6 4 2 1 Configuration for RCSO SRAM On board Peripherals Chip Select 0 Configuration Register mem stcfg0 Address 0x0 1400 1000 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 z w Aw Fave Me wl Be IR IR Be Fav A Fav Kw AN UN DEFAULT 1 1
55. 58 Master Clock Serial Bit Clock Left Right Channel Select Word Select Serial Data Input Digital Audio signal IEC 60958 Master Clock Serial Bit Clock Left Right Channel Select Word Select Serial Data Output 0 contains channel 1 Left and channel 2 Right information Serial Data Output 1 contains channel 3 Left Surround and channel 4 Right Surround information not available on the EXM32 AU1250 CPU Module EXM32 AU1250 User Manual V10 doc page 18 of 110 EXM32 AU1250 CPU Module User s Manual DA ERR DA MUTE AUDIO GND MSC Vertriebs GmbH Serial Data Output 2 contains channel 5 Center and channel 6 Low Frequency Effect information not available on the EXM32 AU1250 CPU Module Audio Error signal Audio Mute signal Digital Audio Ground for shielding purposes 3 3 1 8 Digital Video Interface Two digital video interfaces may be provided on EXM32 CPU Modules All signals are LV TTL level signals Video Channel 0 DVO CLK DVO De7 0 DVO ENG DVO AV DVO HSYNC DVO SYNC DV VSYNC DVO DVALID Video Channel 1 DV 1 CLK DV 1_D lt 7 0 gt DV 1 ENG DV 1 AV DV 1 HSYNC DV 1 SYNC DV 1 VSYNC DV 1 DVALID DV GND 3 3 1 9 Primary LCD Port Video Clock signal Channel 0 data lines Port Enable active low Available signal active low Horizontal Sync signal high active Sync signal indicates the start of packet high Vertical Sync signal high active Data Valid signal indi
56. 7 GND 38 GND 37 IRQ_EXT1 38 reserved don t use 39 GND 40 GND 39 IRO EXTO 40 CSA 41 GND 42 GND 41 IRQ MB2 42 CSB 43 GND 44 GND 43 IRQ_MB1 44 BS 45 GND 46 GND 45 IRO MBO 46 OE 47 GND 48 GND 47 CLK GND 48 WE 49 GND 50 GND 49 CLKOUT 50 RW 51 GND 52 GND 51 CLK GND 52 RDY Strip C Strip D Pin Signal Pin Signal Pin Signal Pin Signal 1 VCC3V3 2 VCC3V3 1 A00 2 A01 3 VCC3V3 4 VCC3V3 3 A02 4 A03 5 VCC3V3 6 VCC3V3 5 A04 6 A05 7 VCC3V3 8 VCC3V3 7 A06 8 A07 9 VCC3V3 10 VCC3V3 9 A08 10 A09 11 VCC3V3 12 VCC3V3 11 A10 12 A11 13 VCC3V3 14 VCC3V3STB 13 A12 14 A13 15 VCC3V3 16 VCC3V3STB 15 A14 16 A15 17 VCC3V3 18 VCC3V3STB 17 A16 18 A17 19 VCC3V3 20 VCC3V3STB 19 A18 20 A19 21 VCC3V3 22 VCC3V3STB 21 A20 22 A21 23 VCC3V3 24 VCC3V3STB 23 A22 24 A23 25 VBAT 26 VCC5V0 25 A24 26 A25 27 reserved don t use 28 VCC5V0 27 reserved don t use 28 reserved don t use 29 PWROFF SUSPEND 30 VCC5V0 29 reserved don t use 30 reserved don t use 31 SLEEP 32 VCC5VO 31 reserved don t use 32 reserved don t use 33 WAKEUP 34 VCC5VO 33 reserved don t use 34 reserved don t use 35 PWRFLT 36 VCC5VO 35 reserved don t use 36 reserved don t use 37 RESET IN 38 reserved don t use 37 reserved don t use 38 reserved don t use 39 RESET OUT 40 reserved don t use 39 PCIE GND 40 PCIE GND 41 AC_RESET 42 AC 97 SDIN1 41 PCIE GND 42 reserved don t use AC 97 SYNC AC 97 SDINO reserved
57. 72224 INIT 336Mhz 0x01272224 INIT 396Mhz 0x02393335 INIT 492Mhz 0x01272224 INIT 600Mhz Chip Select 0 Adress Configuration and Enable mem sdaddr0 Address 0x0 1400 0820 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Rey p bo E Bo lo m i _ p po E p BW DEFAULT o 0 0 0 0 1 0 1 1 1 1 INIT 0 0 1 1 0 1 0 0 0 0 0 1 0 1 0 1 BIT 15 14 13 12 11 1109 8 7 6 5 4 3 12 1 0 Av Pan Pan ar Pv Fa Fav w Fav Fa Fav w Fav Fav Fav w DA DEFAULT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 INIT 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0x341503E0 EXM32_AU1250_User Manual V10 doc page 99 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH Chip Select 1 Adress Configuration and Enable mem sdaddri Address 0x0 1400 0828 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 p Mai Ze p _ Ba M P _ _ _ P Bai ET a DEFAULT 0 0 0 0 0 1 0 1 1 1 1 INIT 0 0 1 1 0 1 0 0 0 0 0 1 0 1 0 1 BIT 15 14 13 12 11 109 8 7 16 5 4 3 2 1 0 E Ps P GC Pas P 6 Ze Ti E A Pg Ze b P Z BG DEFAULT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 INIT 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0x341583E0 Global Configuration Register A mem_sdconfiga Address 0x0_1400 0840 BIT 31 30 29 28 27 26 25 24 23 22 21
58. 8 JTAG TCK 17 DAO_SDIN1 18 reserved don t use 19 FW GND 20 JTAG TMS 19 DAO SDIN2 20 reserved don t use 21 reserved dontuse 22 JTAG_TRST 21 DA MUTE 22 DA ERR 23 reserved dont use 24 CANO EN 23 DV GND 24 DV GND 25 FW GND 26 CANT RX 25 DVO CLK 26 DV1 CLK 27 reserved don t use 28 CANO ERR 27 DV GND 28 DV GND 29 reserved don t use 30 CAN1 TX 29 DVO AV 30 DV1_AV DVO_HSYNC DV1_HSYNC 31 SATA GND 32 CANO STB 31 DVO SYNC 32 DVI SYNC reserved don t use DVO_VSYNC DV1 VSYNC gt gt En 33 bvo DVALID 9 DVI DVALID 35 reserved dontuse 36 CANO RX 35 DV GND 36 DV GND 37 GND 38 CANT ERR 37 DVO DO 38 DV1 DO 39 USB GND 40 CANO TX 39 DVO D1 40 DV1 D1 41 USBO 2 D 42 CAN1 STB 41 DVO D2 42 DV1 D2 43 USBO 2 D 44 USBO ID g 43 DVO D3 44 DV1 D3 45 USB GND 46 USBO VBUS 45 DVO D4 46 DV1 D4 47 USB1 3 D 48 USBO 2 PWEN 47 DVO D5 48 DV1 D5 49 USB1 3 _D 9 50 USB1 3 _PWEN 49 DVO D6 50 DV1 D 51 USB GND 52 USB OC 51 DVO D7 52 DV1 Di 3 USBO 1 is available on bottom pad layout USB2 3 on top pad layout Strip C Strip D Pin Signal Pin Signal Pin Signal Pin Signal GPIO Mode LCD2 Mode GPIO Mode LCD2 Mode 1 LCD DOO BO 2 I2C0 SDA 1 GP IN7 notavailable 2 nc not available 3 LCD DO1 B1 4 I2C0 SCL 3 GP ING not available 4 nc not available 5 LCD D02 B2 6 12C1_SDA 5 GP IN5 not available
59. 8 OxSFFF_00F8 0x0000 TST REG OUT3 4 16 Ox1FFF_00FC Ox3FFF OOFC 0x0000 EXM32 AU1250 User Manual V10 doc page 56 of 110 EXM32 AU1250 CPU Module Users Manual MSC Vertriebs GmbH 5 1 1 BRDREV Board Revision Register Offset 0x00 entspricht WHO AM I BIT 15 14 13 12 11 10 9 18 7 6 5 4 3 2 1 10 PA R R IR IR IR R IR IR IR IR IR R IR IR IR IR DEFAULT l BIT NAME VALUE DESCRIPTION 15 FIN 3 CPU Module Revision REV 12 H HW SUBREV CPU Module Subrevision 7 FPGA FPGA Software Revision used for major updates 4 REV FPGA FPGA Software Subrevision used for minor updates 0 SUBREV p EXM32 AU1250 User Manual V10 doc page 57 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 5 1 2 BRDSTAT Board Status Register Offset 0x04 entspricht BOARD STATUS BIT 15 14 13 12 131 10 9 8 E R IR IR IR JR JR IR IR JR R IR R DEFAULT 0 o jo o Jo 10 1 Jo lo 0 lo jo fo N al R O N e wu pu pu wu BIT NAME VALUE DESCRIPTION 0 15 1 0 14 1 0 13 1 0 12 1 11 USB
60. ANI Optional HW Rev 2 0 Ox0 BEEF E00 0x0_3FFF_EFFF ETHERNET 0x0_3FFF_FOQO EEEE FIREWIRE Optional HW Rev 2 0 EXM32_AU1250_User Manual V10 doc page 85 of 110 EXM32 AU1250 CPU Module User s Manual 6 2 1 DDR2 Memory Area AU DDR CSO OxO 0000 0000 AU DDR CS1s OxO 0800 0000 6 2 2 Area0 MSC Vertriebs GmbH Area 0 contains the flash memory space and VO spaces of the peripheral devices The whole address decoding is done by a programmable logic device FPGA The FPGA generates from chip select 0 multiple address decoded chip selects One chip select for each device The interface type of Area 0 is set to SRAM with a bus width of 16 bit Flash FLASH_CS FLASH base address 0x0_1800_0000 Linear Flash memory is provided by one device The chip select signals for the two flash memories are address decoded There is an Address Space of 128 MByte Reserved for Linear Flash on the Au1250 CPU Module FPGA Register in FPGA integrated FPGA base address OxO 1FFF 0000 DC in FPGA integrated 12C1 base address 0x0_1FFF_1000 I2CDDC base address OxO 1FFF 1800 SPI in FPGA integrated SPI base address OxO 1FFF 2000 UART16550 in FPGA integrated UARTO base address OxO 1FFF 4000 UART1 base address not available OXO 1FFF 5000 UART2 base address n
61. Controller USB 2 0 high Speed OTG Host Function controller 2 port CAN 2x Asynchr Serial Interface 2x I2C 3x SPI AC97 12S Sound Interface RTC Bus The 16 Bit optional 32 Bit CPU bus for SRAM or VLIO type peripherals available on module connector buffered 5V tolerant EXM32 allows to stack multiple CPU modules that share the motherboard s or extension module s resources Connectors Two EXM32 Connectors carries all interfaces the system CPU bus and the power supply A Debug connector allows the connection of an JTAG based debug tool EXM32 AU1250 User Manual V10 doc page 6 of 110 EXM32 AU1250 CPU Module Users Manual MSC Vertriebs GmbH 1 2 1 Block Diagram EXM32 AU1250 CPU Module am AU1250 DDR SDRAM Interface aa e IDE CF Bus State Interface Controller EXM32 Connector X1 EXM32 Connector X2 External Data Buffer Internal Data Buffer Figure 2 EXM32 Au1250 block diagram EXM32_AU1250_User Manual V10 doc page 7 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 2 Overview 2 4 Connectors EXM32 Connectors Two EXM32 208 pin connectors These connectors support EXM32 compatible modules Debug Connector Allows the connection of an JTAG based Debugger Tool Board type Compact CPU module size 90 x 65 mm stackable with other EXM32 modules 2 2 Specification Environment Temperature operating 40
62. D2 GPIO Interface is configured in LCD Mode ENABLE 1 LCD2 GPIO Interface is configured in GPIO Mode 0 Flash is write protected common for Strata Flash and NAND Flash 4 FLWE 1 Flash is fully accessible 3 2 ETH 0 De assert Ethernet Controller Reset RST 1 Assert Ethernet Controller Reset 1 PD 0 De assert Peripheral Devices Reset RST 1 Assert Peripheral Devices Reset 0 MB 0 De assert Motherboard Reset RST 1 Assert Motherboard Reset EXM32 AU1250 User Manual V10 doc page 59 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 5 1 4 LEDCTRL LED Control Register Offset 0x0C entspricht DISC LEDS BIT 15 14 43 12 1 110 9 8 7 6 5 Ja 3 2 1 lo EM RJR IR IR JR IR IR IR JR IR IR IR Pw Pi P Py DEFAULT O O 0 JO 0 10 JO 0 O JO O JO O O 0 JO BIT NAME VALUE DESCRIPTION 15 14 3 13 12 11 o of E 2 TE A sl E 1 LED2 0 LED2 is turned off yellow green 1 LED2 is turned on yellow green o ter EUER o vl EXM32_AU1250_User Manual V10 doc page 60 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH
63. EE EUTROPIO OE OE N i 8 2 3 Mechanical Dimensions ss 9 2 4 Connector POSITIONS 2 5 RA aid 9 Be ITCH ACCS EE EE EE EE EE eut 10 3 1 else EE Et A ebbe re i abt e EO OO ri br EE oh 10 3 1 1 EXM32 Connector Pin Definition nnns 10 3 1 2 Connector X1 CPU Bus Compact Flash SPI AC 97 I S PCI E see dee ees see 11 Gonnect r X2 InterfaCOS NET 12 3 2 Connector SE a eter debe ir re bete ne ir tr ir br Er irr dadi 13 3 3 rere ge iaia EE EE OE EE aS ad AE yte 17 3 4 Debug Connector ioco eee ete rre rr Er re Er rera eiert 23 4 Hardware Description e rere Lr e re Le e En n Ea Er rd n Ear tens 24 4 1 Funcional BIOGKS rientranti 24 4 1 1 O OE A EN 24 41 2 SS Z aste ust EE EERDER EFE ences KERKE ER KEER ER EER KERE REGEER GEERF EER GEE EE EEN EE 25 4 1 3 PC Card Compact Flash Interface 25 4 14 BE E EE 26 4 1 5 NBA A eene oko 26 4 1 6 DDRZESDRAM c OR AT EA O AAR OR AAA 26 4 77 EE 26 AGB HEER AN OE ER eege 26 4 1 9 Giaphics SontlrolleEx asesor aazn a o azana odaiawt www wywi pe nef dont ag 27 4 1 10 Camera Interface iii 29 4 1 11 GPIO LCD2 Interface V0 5 Update 30 41 12 GAN BUS ara N etri rtp Pha rate hes ERR ET EIE s RE AE OR RE N PE 31 4 1 13 Serial Communication Interfaces COMO COM1 eee aaa aaa aaa aaa wana aaca 32 4144 e EE N N AA AE 38 A Gie OE EE OR MOE RR EE EE EE MEUM IM IET 41 4 1 16 Audio Codec Interface AC 97 125S L4J RJ iii 45 4 2 Power Managemen
64. H GND ETH ACTLED ETH LILED ETH_SPLED s integrated on the EXM32 CPU Module The EXM32 Ethernet r use with Ethernet Magnetics Analog Twisted Pair Ethernet Transmit Differential Pair These pins transmit the serial bit stream for transmission on the Unshielded Twisted Pair UTP cable Available on bottom pad layout only Analog Twisted Pair Ethernet Receive Differential Pair These pins receive the serial bit stream from the Ethernet Magnetics Available on bottom pad layout only Ethernet GND for shielding controlled impedance The Activity LED pin indicates either transmit or receive activity When activity is present the activity LED is on when no activity is present the activity LED is off The Link Integrity LED pin indicates link integrity If the link is valid in either 10 or 100 Mbps the LED is on if link is invalid the LED is off The Speed LED pin indicates the speed The speed LED will be on at 100 Mbps and off at 10 Mbps All LED signals pull external LEDs with max 5 mA to GND 3 3 1 12 CRT not available on EXM32 AU1250 CPU Module A standard analogue C RT interface may be provided on EXM32 CPU Modules The 75 Ohm termination resistors are integrated on the EXM32 CPU Module VGA_GND Red analogue video output signal for CRT displays not available on EXM32 AU1250 CPU Module Green analogue video output signal for CRT displays not available on EXM32 AU 1250 CPU Module Blue analogue vid
65. IO DIR 2 write operation is disabled EN 2 1 GPIO DIR 2 write operation is enabled g GPIO_DIR_ 0 GPIO DIR 1 write operation is disabled EN 1 1 GPIO DIR 1 write operation is enabled g GPIO_DIR_ 0 GPIO DIR 0 write operation is disabled EN 0 1 GPIO DIR 0 write operation is enabled 7 GPIO DIR 0 GPOUTT 7 used as input 7 1 GPOUTT 7 used as output e GPIO_DIR 0 GPOUT 6 used as input 6 1 GPOUT 6 used as output 5 GPIO DIR 0 GPOUT 5 used as input S 1 GPOUT 5 used as output 4 GPIO DIR 0 GPOUT 4 used as input 4 1 GPOUT 4 used as output 3 GPIO DIR 0 GPOUTI3 used as input 3 1 GPOUT 3 used as output 2 GPIO DIR 0 GPOUT 2 used as input 2 1 GPOUT 2 used as output 1 GPIO DIR 0 GPOUT 1 used as input 1 1 GPOUTI1 used as output 0 GPIO DIR 0 GPOUTIO used as input 0 1 GPOUTIO used as output EXM32 AU1250 User Manual V10 doc page 72 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 5 1 17 GPIO Data Output Register 0x44 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PW W W W W W W W W A W R Ww A Ww D W A Ww A W A W p Ww DEFAULT 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BIT NAME VALUE DESCRIPTION 15 GPIO DOU GPIO DOUT 7 write operation is disabled 0 T EN 7 1 GPIO
66. OxO 1400 1010 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 V Paw Aw Aw ee w IR IR Be Pew wi vw Fav au Fay DEFAULT 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 INIT 336Mhz O 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 INIT 396Mhz O 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 INIT 492Mhz O 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 INIT 600Mhz O 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 BIT 15 14 13 12 11 1109 8 7 6 5 4 3 2 1 0 D w Awe Ae ye Vul vw he ew Pw Vl e D n LN DEFAULT 0 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 INIT 336Mhz O 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 INIT 396Mhz O 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 INIT 492Mhz O 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 INIT 600Mhz O 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0x00450045 INIT 336Mhz 0x00450045 INIT 396Mhz 0x00450045 INIT 492Mhz 0x00450045 INIT 600Mhz Chip Select 1 Timing Register mem sttime1 Address 0x0 1400 1014 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E R IR JR R IR R IR IR IR IR RH IR IR IR IR R DEFAULT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 INIT 336Mhz 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT 396Mhz O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT 492Mhz 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT 600Mhz O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 15 14 13 12 111 1109 8 7 6 5 4 3 2 1 0 V R IR IR IR a Bw P w Pau w Ku Fav vw D w Fay DEFAULT 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 INIT 336Mhz O 1 1
67. SB of DL is written so when setting the divisor write the MSB first and the LSB last 4 1 14 SPl Interface An external SPI controller is used on the Au1250 CPU to support the the serial protocol interface SPI The SPI IP is integrated in the FPGA The SPI Interface is available on the EXM32 Connector UART MOSI SPI MOSI CTRLINT UART_MISO SPI_MISO T O a E a a ND UART_SS 1 SPI_SS 1 EXM32 Module Connector UART_SS o SPI_SS 0 Figure 10 EXM32 Au1250 SPI interface EXM32_AU1250_User Manual V10 doc page 38 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 4 1 14 1 SPI Clock The variable SPI Clock depends on the used CPU frequency Refer to chapter 5 1 1 CPU for details The clock divider register has to be initialized according to the used clock frequency Name Source Min Max Resolution Description AU1250 clk CLKOUT 113 bps 7 373 Mbps 4 1 14 2 SPI Core Registers Base Address 0x1FFF2000 0x3FFF2000 Address offset Access Description 0x00 R Data receive register 0 Rx1 mp D R Data receive register 4 D mn D R X Datareceiveregister2 _ Rx3 pe D J R Datareceiveregisters R4 meng 16 R X Datareceiveregister4 R5 pe 16 R fpDatareceveregiterb D pe 16 R Datareceiveregister6 R7 ie 16 R___ Datarec
68. SK 1 CFO ATAO interrupt is masked 10 IRQ10 0 CF1 ATA1 interrupt is disabled MASK 1 CF1 ATA1 interrupt is masked 9 IRQ9 0 CFO card detect interrupt is disabled MASK 1 CFO card detect interrupt is masked 8 IRQ8 0 CF1 card detect interrupt is disabled MASK 1 CF1 card detect interrupt is masked 7 IRQ7 0 SD card detect interrupt is disabled MASK 1 SD card detect interrupt is masked 6 IRQ6 0 UARTO Interrupt is disabled MASK 1 UARTO Interrupt is masked 5 IRQ5 0 UART1 Interrupt is disabled MASK 1 UART1 Interrupt is masked 4 IRQ4 0 UART2 Interrupt is disabled MASK 1 UART2 Interrupt is masked 3 IRQ3 0 CANO controller interrupt is disabled MASK 1 CANO controller interrupt is masked 2 IRQ2 0 CAN1 controller interrupt is disabled MASK 1 CANT controller interrupt is masked 1 IRQ1 0 CANO error interrupt is disabled MASK 1 CANO error interrupt is masked 0 IRQO 0 CANI error interrupt is disabled MASK 1 CANT error interrupt is masked EXM32 AU1250 User Manual V10 doc page 67 of 110 EXM32 AU1250 CPU Module User s Manual 5 1 12 SIGSTAT Signal Status Register Offset 0x30 MSC Vertriebs GmbH BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AN R IR R R R R R DEFAULT O O O O o 10 0 10 JO O 0 O O lO 0 BIT NAME VALUE DESCRIPTION 15 SIG15
69. The CSB address Space is reserved for 32 bit devices FPGA Register in FPGA integrated FPGA base address 0x0_3FFF_0000 12C in FPGA integrated EXM32_AU1250_User Manual V10 doc page 87 of 110 EXM32 AU1250 CPU Module User s Manual 12C1 base address OxO SFFF 1000 I2CDDC base address 0x0_3FFF_1800 SPI in FPGA integrated SPI base address 0x0_3FFF_2000 UART16550 in FPGA integrated MSC Vertriebs GmbH UART1 COM1 base address 0x0_3FFF_4000 CAN CANO CS CANT CS CANO base address OxO SFFF C000 CAN1 base address 0x0_3FFF_D000 Ethernet ETH_CS Ethernet base address 0x0_3FFF_E000 EXM32_AU1250_User Manual V10 doc page 88 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 6 3 Interrupt Handling There are two types of interrupt Sources Exerternal IRQ request ntegrated Peripheral modules The AU1250 GPIO pins are configurable as a level sensitive or edge triggered interrupt Source 6 3 1 IRQ There are two interrupt controllers in the Au1250 processor Each interrupt controller supports 32 interrupt sources Each interrupt source is individually maskable to either enable or disable the core from detecting the interrupt Interrupts are generated by software integrated interrupt controllers performance counters and timers All inter
70. The chosen CPU speed determines the maximum peripheral clock frequency available on the EXM32 Connector X1B CLKOUT CPU Speed AU1250 CLKOUT EXM32 Connector 336 Mhz 56 Mhz 396 Mhz 66Mhz 492 Mhz 61 5Mhz 600 Mhz 66 67Mhz Clocks There are three crystal oscillators populated on the EXM32 AU1250 A 12 MHz crystal oscillator is feed to the AU1250 for generation of internal and external frequencies A 25 000 MHz crystal oscillator provides the clock for a phase locked loop PLL clock generator PLL clock generator CY22393 The PLL clock synthesiser populated on the CPU module generates the clocks for all peripheral modules The Cypress CY22393 clock generator features three independent phase locked loops The device is in system serial and flash programmable thus all frequency settings can be changed On the EXM32 SHAu1250 CPU module the PLL clock generator is connected to Channel 0 of the integrated I C Bus To access the PLL device address 1101001 must be used PLL device address 1101001x 0xD2 The CY22393 clock generator provides up to six output clocks OUTPUT FREQUENCY MODULE CLOCK XBUF 25 000 MHz Ethernet Clock CLKA variable default 33 33 MHz Digital Video Clock CLKB 2 000 MHz VRG synchronisation clock CLKC 27 000 MHz Digital Video clock HSDI clock CLKD 14 769231 MHz Not Used CLKE 48 Mhz USB clock The Cypress clock generator offers pow
71. User Manual V10 doc page 82 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 5 1 26 Test Register 3 Output Signals OxFC BIT 15 14 13 12 11 110 9 8 7 6 5 14 3 2 1 0 y PT Pv Bay wy hy By Bn Phy B Ban Bi Ev Fav ey Bey My DEFAULT 0 0 0 0 0 0 0 O O0 0 0 0O O 0 0 0 BIT NAME VALUE DESCRIPTION 15 9 X1A_CF_CE1 8 X1A_CF_CE2 7 X1A_CF_SCKSEL O O O Of Al OJ O O O O At OJ Al Of A Oy A Oj O O O 6 X1B_CSB 5 X1B_BEO 4 X1B_BE1 3 X1B_BE2 2 X1B_BE3 1 X1B_BS 0 X1B_RW EXM32_AU1250_User Manual V10 doc page 83 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 6 Programming Guide 6 1 Peripheral Memory Map For a description of the peripheral memory space please refer to the AU1250 Hardware Manual 6 2 Off chip Memory Map The Au1250 processor supports four external chip select spaces Ze OFF CHIP Base ADDRESSES SIZE STarEs uge INTERFACE O 0x0 1800 0000 to 0x0 1FFF FFFF 128MB 16 Bit A s 1 0x0_2000_0000 to ox0 2FFF FFFF 256MB 16 Bit NAND Flash 3 0x0 3000 0000 to 0x0 3FFF_FFFF 256MB 16 32 Bit Peripheral devices 2 oxF_0000 0000 to OxF_FFFF_FFFF 8 16 Bit PCMCIA CF
72. W jw W jw jw IW W jw w w W jw w W DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT o o 0 1 0 0 0 0 0 0 0 0 0 0 0 0 BIT 15 14 13 12 11 109 8 7 16 5 A4 3 2 1 0 ET w IW jw W w w jw jw W w W Wi Wi Wi ww DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT o o 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x10000000 6 4 4 1 Interrupt Controller 1 Interrupt Controller 1 Configuration Register The Signal in the Following Table corresponds with the according Bit in the following Interrupt register BIT NAME DESCRIPTION 31 GPIO 31 ETH IRQ 30 GPIO 30 not used 29 GPIO 29 X1B_IRQ_MB1 28 GPIO 28 not used 27 GPIO 27 X1B_IRQ_MBO 26 GPIO 26 not used 25 GPIO 25 not used 24 GPIO 24 not used 23 GPIO 23 not used 22 GPIO 22 not used 21 GPIO 21 not used 20 GPIO 20 not used 19 GPIO 19 not used 18 GPIO 18 not used 17 GPIO 17 not used 16 GPIO 16 X1B_IRQ_MB2 15 GPIO 15 not used 14 GPIO 14 not used 13 GPIO 13 not used 12 GPIO 12 AU DREQ1 11 GPIO 11 not used 10 GPIO 10 not used 9 GPIO 9 not used 8 GPIO 8 not used 7 GPIO 7 AU _WAKE_IRQ 6 GPIO 6 not used 5 GPIO 5 FPGA_INT 4 GPIO 4 AU_DREQO 3 GPIO 3 not used 2 GPIO 2 AU RTC_IRQ4 1 GPIO 1 X1B_IRQ_EXT1 0 GPIO 0 X1B IRQ EXTO EXM32_AU1250_User Manual V10 doc page 106 of 110
73. bs GmbH 5 1 6 CFCTRL Compact Flash Control Register Offset 0x14 entspricht POMCIA CONTROL BIT 15 14 13 12 11 110 9 8 7 6 5 4 3 2 1 O P Sax yA p Pt Rai m E Dm EW Rai z Se y Bi E Mi DEFAULT O 10 10 10 O 0 O lO JO O 10 10 O 10 JO 0 BIT NAME VALUE DESCRIPTION 15 CF1 0 De assert Compact Flash Card 1 Reset RST 1 Assert Compact Flash Card 1 Reset 0 14 1 13 o 12 CF1 0 Disable Compact Flash 1 Interface EN 1 Enable Compact Flash 1 Interface 00 power supply disabled 11 CF1 01 set CF1 card power supply to 3 3 V 10 VCC 10 set CF1 card power supply to 5 0 V not supported by EXM AU1250 11 set CF1 card power supply to 3 3 V 9 0 1 0 8 i 1 7 CFO 0 De assert Compact Flash Card 0 Reset RST 1 Assert Compact Flash Card 0 Reset 0 2 i 1 5 ATAO 0 Compact Flash Interrupt EN 1 IDE Interrupt 4 CFO 0 Disable Compact Flash 0 Interface EN 1 Enable Compact Flash 0 Interface 00 power supply disabled 3 CFO 01 set CFO card power supply to 3 3 V 2 VCC 10 set CFO card power supply to 5 0 V not supported by EXM Au1250 11 set CFO card power supply to 3 3 V 1 A 0 1 0 1 EXM32 AU1250 User Manual V10 doc page 62 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 5 1 7 PDCTRL Peripheral Devices Control Register Of
74. cates if data is valid for reading or writing high Video Clock signal Channel 1 data lines Port Enable active low Available signal active low Horizontal Sync signal high active Sync signal indicates the start of packet high active Vertical Sync signal high active Data Valid signal indicates if data is valid for reading or writing high active Digital Video Ground for shielding purposes All signals are LV TTL level signals LCD D lt 17 00 gt LCD HSYNC LDC VSYNC LCD SHFCLK LCD VDON LCD VCON LCD DON LCD BLON Data for LCD panel LCD Horizontal Sync signal LCD Vertical Sync signal LCD Pixel Clock enables Supply Voltage for Display Logic enables Power Inverter Voltage Display On signal for STN displays enables Backlight EXM32 AU1250 User Manual V10 doc page 19 of 110 EXM32 AU1250 CPU Module LDC M DE 3 3 1 10 FC Interface Up to two I C channels TTL level signals I2C lt 1 0 gt _SDA 12C lt 1 0 gt SCL User s Manual MSC Vertriebs GmbH in case of STN Display in case of TFT Display AC Bias signal M LCD Data Enable DE may be provided on EXM32 CPU Modules All signals are LV Serial Data Input Output signal used to connect the CPU Modules on board IS units Serial Clock Input Output signal reserved for Motherboard and Extension Modules PS units 3 3 1 11 Ethernet 10 100Mbit The signal termination Interface is designed fo ETH TXD ETH TXD ETH RXD4 ETH RXD ET
75. ce supports two sockets A signal CF SCKSEL on the EXM32 connector is used to multiplex between the two sockets 0 and 1 When CF SCKSEL is low socket 0 is active Socket 1 is active when CF SCKSEL is HIGH CF SCKSEL is generated by a programmable logic device Lattice CPLD The reset signals CF lt 1 0 gt RESET active high are generated by the programmable logic device To reset the PC Card Compact Flash Card access to the internal registers of the CPLD is necessary The device driver must support this feature EXM32_AU1250_User Manual V10 doc page 25 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 4 14 Linear Flash Flash Memory is used for program and data storage The EXM32 Module supports up to 128 MByte flash memory provided by one device see memory map Linear Flash memory is mapped into Area 0 and 3 of the external memory space This allows the system to boot from flash The Linear Flash shares memory space with the Ethernet Controller the USB Controller the UART two I2C controller the SPI Controller the CAN Controller the programmable logic device FPGA The EXM32 CPU Module supports write protection for Linear Flash Memory An output of the programmable logic device FPGA is used to enable or disable the write protection shared with NAND Flash write protection When the output is HIGH the Flash Memory is fully accessible The card is write protected when the programming voltage is turned off The
76. data Transmitter serial data output from serial port Receiver serial data input handshake signal which notifies the UART that the modem is ready to receive data handshake signal which notifies the modem that the UART is ready to receive data 3 3 1 16 FlexRay not available on the EXM32 AU1250 CPU Module A FlexRay interface is provided on EXM32 CPU Modules All signals are LV TTL level signals An external transceiver is required to convert the LV TTL signals to the desired physical interface 3 3 1 17 MISC MODULE_DETECT CPUID lt 1 0 gt transmit data receive data transmitter enable active low receive data enable active low bus guardian enable transceiver enable active high transceiver standby active low bus error flag active low A lower EXM32 Module can detect if another Module is mounted on top this feature is used for automatic JTAG chain configuration a the pad on every modules bottom side is connected to VCC3V3 b the top side pad is used for readout there is no connection to the bottom side pad There are no direct connections between the top and bottom side pads of CPUID lt 1 0 gt The modules ID value binary is available on the top side signal pads for the next upper Module The ID value is generated by reading the lower module s ID value vie the bottom side pads and incrementing this value by 1 A EXM32 motherboard has the ID value 00 the CPU Module ID value is 01 As a sec
77. dth Access Description Divisor Latch Byte 1 LSB 0 8 RW The LSB of the divisor latch Divisor Latch Byte 2 A A The MSB of the divisor latch 4 1 13 2 1 Interrupt Enable Register IER This register allows enabling and disabling interrupt generation by the UART Access Description RW Received Data available interrupt 0 disabled 1 enabled Transmitter Holding Register empty interrupt 0 disabled 1 enabled Modem Status Interrupt 0 disabled 1 enabled Reserved Should be logic 0 Table 7 External UART Interrupt Enable Register IER 2 RW Receiver Line Status Interrupt 0 disabled 1 enabled Reset Value 00h EXM32_AU1250_User Manual V10 doc page 33 of 110 EXM32 AU1250 CPU Module User s Manual 4 1 13 2 2 Interrupt Identification Register IIR MSC Vertriebs GmbH The IIR enables the programmer to retrieve what is the current highest priority pending interrupt Bit 0 indicates that an interrupt is pending when it s logic 0 When it s 1 no interrupt is pending The following table displays the list of possible interrupts along with the bits they enable priority and their source and reset control Interrupt Type Interrupt Source Interrupt Reset Control 2 Sola 0 1 1 1 Receiver Line Parity Overrun or Framing Reading the Line Status Status errors or Break I
78. e The clocking will occur on the negative to positive edge of the signal raising edge active low CF BOES This is an Output Enable strobe generated by the host interface It is used to read data from the CompactFlash Storage Card or CF Card in Memory Mode and to read the CIS and configuration registers active low EXM32_AU1250_User Manual V10 doc page 13 of 110 EXM32 AU1250 CPU Module User s Manual CF lt 1 0 gt _RDY_IRG CF lt 1 0 gt RESET CF lt 1 0 gt _ PWEN CF PWE CF_WAIT CF IOIS16 CF PREGZ 3 2 1 4 CPU Bus D lt 31 00 gt A lt 25 00 gt BE lt 3 0 gt CSA CSB OE WE R W RDY BS MSC Vertriebs GmbH in PC Card Memory Mode In Memory Mode this signal is set high when the CompactFlash Storage Card or CF Card is ready to accept a new data transfer operation and held low when the card is busy The Host memory card socket must provide a pull up resistor At power up and at Reset the RDY BSY signal is held low busy until the CompactFlash Storage Card or CF Card has completed its power up or reset function No access of any type should be made to the CompactFlash Storage Card or CF Card during this time The RDY BSY signal is held high disabled from being busy whenever the following condition is true The CompactFlash Storage Card or CF Card has been powered up with RESET continuously disconnected or asserted in PC Card VO Mode The signal is IREQ After the CompactFlash
79. e FPGA A 32 bit databus thus isn t an advantage in access time The time remains the same like in two separate 16 bit memory accesses A 32 bit device is always selected with the chip select X1B CSB and an address match on the address bus X1B A 25 2 A 8 16 and 32 bit access is possible on a 32 bit device by analyzing the byte enable X1B BE 3 0 The AU1250 timing values in the timing diagrams Ta Toecs Tcoes Twcs Tcsw and Tcsoff are defined by initialization The values on the EXM32 connector show the minimum and maximum possible timing for this signals The timing diagrams show the minimum timing requirements for a 32 bit read write access To guarantee the correct function of the AU1250 CPU module it is prohibited to change this values To extend access time the signal X1B RDY available on the EXM32 connector has to be pulled low The cycle is extended until the signal is released The chip select X1B_CSA and X1B_CSB are configured in normal mode no page mode is possible EXM32 AU1250 User Manual V10 doc page 51 of 110 EXM32 AU1250 CPU Module Users Manual MSC Vertriebs GmbH 4 3 3 1 32 bit read timing BCS RIVES E AU1200 Bus State Controller Signals A RADIO X18 Dp1101t X18_CLKOUT KIB CEA XIB_CSBER X1B RBERZ X18 RBEM1f EE IR 2 m EXM32 Connector Bus X18 WER D State Controller Signals KIB 0 ES X1B Bang 15 22 15 22 15 22 16 22 xm Ape esa DS WERE 53 iminT ene max
80. e RTC device This module is a serial interface real time clock with built in crystal oscillator The Seiko Epson RTC 8564NB real time clock module offers many functions such as calendar clock alarm timer and frequency output 1 Hz 32 Hz 1024 Hz 32 768 kHz The device functions can be controlled by a two wire interface I2C On the EXM32 Au1250 CPU Module the RTC is connected to channel 0 of the integrated l2C Bus To access the real time clock module device address 1010001 must be used RTC device address 1010001x 0xA2 For a detailed description of the real time clock module please refer to the Seiko Epson RTC 8564NB Application Manual 4 1 2 MMC SD SDIO MultiMedia Card MMC Secure Digital Memory Card SD Secure Digital Input Output Card SDIO The EXM32 Au1250 CPU Module supports a SD SDIO MMC I O Card interface Secure Digital Memory Card support a mechanical write protect switch An input of the programmable logic device FPGA is used to readout the status of this switch When the signal EXT SDIO WP is LOW the SD Card is fully accessible The card is write protected when EXT SDIO WP is HIGH To readout the actual status of the write protect switch access to the internal registers of the FPGA is necessary The device driver must support this feature BRDSTAT Board Status Register 4 1 3 PC Card Compact Flash Interface The EXM32 Au1250 CPU Module features a PC Card Compact Flash interface This interfa
81. e nr Bb eR PER Prata at 110 7 1 ID EEPROM Register Map 110 Document change history Date Version Document change description 2005 09 14 01 EXM32 AU1200 CPU Module Initial Version 2008 03 12 08 Update to EXM32 AU1250 CPU Module V30 2008 09 08 09 Register Definition Update 2008 09 17 1 0 released EXM32_AU1250_User Manual V10 doc page 4 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 1 General Information 1 1 Introduction The EXM32 Au1250 CPU Module is designed to operate with an EXM32 compatible motherboard to form a complete system The motherboard will provide power supply and legacy interface connectors as required by the specific application With the possibility to add expansion modules an EXM32 system can be easily adopted to very specific applications such as gigabit transmission interfaces wireless communication etc An example EXM32 system is shown in figure 1 Expansion Module optional L CPU Module Side View Motherboard Figure 1 EXM32 System Special notice is given to meet the enhanced environment requirements in automotive and industrial applications the EXM32 system is designed to EXM32 is a new form factor to develop compact industrial control systems It is small enough for most applications yet provides enough space to implement complete systems with very few modules Special notice is given to me
82. ee SFOIESDZ DES Table 7 Signal routing in LCD2 GPIO Mode 4 1 12 CAN Bus The EXM32 AU1250 CPU Module features two independent OKI ML9620 CAN bus controllers The operation mode of the CAN transceivers on an EXM32 Motherboard is controlled by the signals CAN 1 0 EN and CAN lt 1 0 gt _STB Those signals can be controlled in peripheral devices control register PDCTRL section 6 1 7 in the FPGA Addresses Data CTRL CAN Controller CANO_INT CANO EN CAN1 EN CANO EN CAN1 EN CANO STB4 CAN1_STB CANO STB4 CAN1_STB CANO_ERR CAN1_ERR CANO_ERR CAN1_ERR I CANI INT CTRL Addresses Data CAN Controller Figure 8 EXM32 Au1250 CAN interface EXM32 Module Connector CAN1_RXD CAN1_TXD EXM32_AU1250_User Manual V10 doc page 31 of 110 EXM32 AU1250 CPU Module Users Manual MSC Vertriebs GmbH 4 1 13 Serial Communication Interfaces COMO COM 1 The EXM32 AU1250 CPU module features a two channel serial communication Interface COMO The Au1250 integrated serial interface 1 is connected to the EXM32 Connector The second serial interface PSC1 of the AU1250 is not used Refer to the AU1250 datasheet for a detailed description of the AU1250 integrated UART COM1 COM1 is implemented in an FPGA The FPGA integrated IP is a 16550 compatible UART The 8 bit interface of the UART is c
83. elveregister All registers are 16 bit wide and accessible only with 16 bits all wb sel i signals must be active 4 1 14 2 1 Data receive registers RxX Reset Value 0x0000 RxX The Data Receive registers hold the value of received data of the last executed transfer Valid bits depend on the character length field in the CTRL register i e if CTRL 9 3 is set to 0x08 bit RxL 7 0 EXM32 AU1250 User Manual V10 doc page 39 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH holds the received data If character length is less or equal to 16 bits Rx1 Rx7 are not used if character length is less than 32 bits Rx2 Rx7 are not used and so on NOTE The Data Received registers are read only registers A Write to these registers will actually modify the Transmit registers because those registers share the same FFs 4 1 14 2 2 Data transmit register TxX Reset Value 0x0000 TxX The Data Receive registers hold the data to be transmitted in the next transfer Valid bits depend on the character length field in the CTRL register i e if CTRL 9 3 is set to 0x08 the bit Tx0 7 0 will be transmitted in next transfer If character length is less or equal to 16 bits Tx1 Tx7 are not used if character len is less than 32 bits Tx2 Tx7 are not used and so on 4 1 14 2 3Control and status register CTRL Es 15 14 ERE T R RW Eg RW Reset Value 0x0000 ASS If this bit
84. eo output signal for CRT displays not available on EXM32 AU1250 CPU Module Horizontal sync signal This output supplies the horizontal synchronisation pulse not available on EXM32 AU1250 CPU Module Vertical sync signal This output supplies the vertical synchronisation pulse not available on EXM32 AU1250 CPU Module VGA Ground Display Data Channel the signals DDC_SCL and DDC_SDA can be used for a DDC interface between the graphics controller chip and the CRT monitor EXM32 AU1250 User Manual V10 doc page 20 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH All signals are LV TTL level signals 3 3 1 13 GPIO LCD2 is not available on the EXM32 AU1250 CPU Module All signals are LV TTL level signals 16 I O signals are provided by an EXM32 CPU module These signal pins can alternatively be used as secondary LCD data signals The usage is defined by the logic level LCD2 EN that is controlled by the EXM32 CPU Module LCD Mode GPIO Mode GP IN 7 0 GP_OUT lt 7 0 gt when set to high it enables the 2nd LCD Port on GPIO Pins high LCD on GPIO pins low GPIO default Data for LCD panel LCD Horizontal Sync signal LCD Vertical Sync signal LCD Pixel Clock enables Supply Voltage for Display Logic enables Power Inverter Voltage Display On signal for STN displays enables Backlight in case of STN Display in case of TFT Display AC Bias signal M LCD Data Enable DE Ge
85. er Signal positive Transmitter Signal negative Receiver Signal positive Receiver Signal negative SATA GND for shielding controlled impedance Four USB ports are provided on the EXM32 AU1250 CPU Module USB lt 1 0 gt signals are available on bottom pad layout USB lt 3 2 gt signals are available on top pad layout intended to be used on expansion modules Note All pull up resistors are integrated on the EXM32 CPU Module USB lt 3 0 gt _D USB lt 3 0 gt _D USBO_ID USBO_VBUS USB lt 3 0 gt _PWEN USB_OC USB_GND 3 3 1 4 JTAG Interface Signal positive Signal negative USB OTG Configuration ID High peripheral Low host signal available only on bottom pad layout USB Supply Voltage also used for OTG Session Request Protocol signal available only on bottom pad layout USB Bus Power Enable signal active high enables the USB ports 5V supply Overcurrent Detect Signal for the USB 5V power line from motherboard common for two USB ports active low USB GND for shielding controlled impedance JTAG signals are used only for boundary scan and PLD programming JTAG_TDO JTAG_TDI JTAG_TCK JTAG_TMS Data is read from external device in synchronization with a TCK signal Data is sent to external device in synchronization with a TCK signal Functions as the serial clock input pin stipulated in the JTAG standard IEEE standard 1149 1 Mode Select input Changing this signal determines the significance of
86. er saving features that are controlled by a programmable logic device FPGA The input pin SHUTDOWN OE three states all outputs when pulled LOW If shutdown is enabled a LOW on this pin disables all phase locked loops counters the reference oscillator and all other active components The S2 SUSPEND connected to the SUSPEND signal input of the clock generator can be configured to shut down a customisable set of outputs and or phase locked loops when LOW This feature can be used for power saving For a detailed description of the PLL clock generator device please refer to the Cypress CY22393 Datasheet EXM32_AU1250_User Manual V10 doc page 24 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH LC ID EEPROM The ID EEPROM is used to store module specific parameters For a parameter overview and a memory map of the ID EEPROM please refer to appendix A The Catalyst Supervisor CAT1026 device used on the board provides 2048 byte of serial electrical erasable and programmable read only memory and is equipped with a two wire interface ISCH On the EXM32 Au1250 CPU Module the CAT1026 is connected to Channel 0 of the integrated GC Bus To access the ID EEPROM device address 1010000 must be used ID EEPROM device address 1010000x 0xAO For a detailed description of the ID EEPROM device please refer to the Catalyst CAT1026 Datasheet Real Time Clock The EXM32 Au1250 CPU Module is equipped with a discret
87. et the enhanced environment requirements in industrial applications EXM32 CPU modules can operate in the extended industrial temperature range and meet DIN EN 60068 environmental conditions for electrical and electronic equipment for road vehicles The revolutionary EXM32 connector technology uses very reliable elastomeric contact elements in a robust shell This is no plug and socket system only one EXM32 connector element is used for every connector location This allows also an easy preparation of system extensions without cost penalty The inter board connection between Module and Motherboard or between two modules is established by compressing the contact elements in between two module boards that have matching contact pads The connection has zero insertion force is compressed and secured by screws and therefore withstands shock and vibration EXM32 AU1250 User Manual V10 doc page 5 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 1 2 Functional Blocks The EXM32 Au1250 CPU Module includes the following functional blocks CPU AMD Alchemy Au1250 MIPS CPU 500 MHz Memory on board up to 256 MByte DDR RAM 32 bit bus width up to 128 Mbyte linear Flash 16 bit bus width optional NAND Flash up to 256 Mbyte 8 bit bus width Peripherals Au1250 integrated LCD STN TFT controller with a maximum resolution 2048x2048 pixel PCMCIA CF Interface dual slot supported Camera Interface Ethernet 10 100T
88. fset 0x18 BIT 15 14 13 12 11 1109 8 7 6 15 4 3 2 1 0 PW R IR R R R R R IR JR R IR R JR R I RH MH DEFAULT 0 0 10 10 0 10 O lO JO O 10 10 O JO JO 0 BIT NAME VALUE DESCRIPTION 0 15 1 14 13 CAN1 0 de assert CAN1 standby signal STB 1 assert CAN1 standby signal 12 CAN1 0 de assert CAN1 enable signal EN 1 assert CAN1 enable signal 0 11 1 10 9 CANO 0 de assert CANO standby signal STB 1 assert CANO standby signal 8 CANO 0 de assert CANO enable signal EN 1 assert CANO enable signal 0 1 R 5 USB1 0 X2A_USB1_PWEN is high impedance TRI 1 X2A_USB1_PWEN is has a defined value PDCTRL 4 4 USB1 0 USB1 power disable PWEN 1 USB1 power enable 0 gt 1 0 2 1 0 1 0 USBO 0 USBO power disable PWEN 1 USBO power enable EXM32 AU1250 User Manual V10 doc page 63 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 5 1 8 IRQSETEN IRQ Set Enable Register Offset 0x20 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E w Av Av dw rw LI ESE Av hw w D DEFAULT O O 10 JO O 10 O JO O JO O JO O O 0 JO
89. igh but SDA is low See bus arbitration section for more information EE 1 TIP Transfer in progress EN 1 when transferring data 0 when transfer complete IF Interrupt Flag This bit is set when an interrupt is pending which will cause a processor interrupt request if the IEN bit is set The Interrupt Flag is set when e one byte transfer has been completed e arbitration is lost Reset Value 0x00 Please note that all reserved bits are read as zeros To ensure forward compatibility they should be written as zeros 4 1 16 Audio Codec Interface AC 97 PS LJ RJ The EXM32 Au1250 CPU Module features one audio codec interface This channel supports various serial interfaces e g AC 97 IS Left Justified Right Justified and is configurable in master or slave mode By default it is set to slave mode The on board FPGA is responsible for the audio signal routing The register setting of the board controll register brdctrl determines the signal routing for the respective audio mode AC97 I2S master slave Refer to section 6 1 3 brdctrl board control register for details The audio codec channel is available on the EXM32 Connector motherboard EXM32_AU1250_User Manual V10 doc page 45 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH AC97 RESET AC97 SYNC AC97 BCLK 12S1_MCLK AC97 SDIN1 AC97 SDINO AC97 SDOUT EXM32 Module Connector 1251_LRCLK 1251_SCLK Adresses
90. is set ss pad o signals are generated automatically This means that slave select signal which is selected in SS register is asserted by the SPI controller when transfer is started by setting CTRL GO BSY and is de asserted after transfer is finished If this bit is cleared slave select signals are asserted and de aserted by writing and clearing bits in SS register IE If this bit is set the interrupt output is set active after a transfer is finished The Interrupt signal is deasserted after a Read or Write to any register LSB If this bit is set the LSB is sent first on the line bit TxL 0 and the first bit received from the line will be put in the LSB position in the Rx register bit RxL 0 If this bit is cleared the MSB is transmitted received first which bit in TxX RxX register that is depends on the CHAR LEN field in the CTRL register Tx NEG If this bit is set the mosi pad o signal is changed on the falling edge of a sclk pad o clock signal or otherwise the mosi pad o signal is changed on the rising edge of sclk pad o Rx NEG If this bit is set the miso pad i signal is latched on the falling edge of a sclk pad o clock signal or otherwise the miso pad i signal is latched on the rising edge of sclk pad o GO BSY EXM32_AU1250_User Manual V10 doc page 40 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH Writing 1 to this bit starts the transfer This bit remains set during the transfer and is auto
91. is set writing 1 to any bit location of this field will select appropriate ss_pad_o line to be automatically driven to active state for the duration of the transfer and will be driven to inactive state for the rest of the time 4 1 15 PC Interface The EXM32 Au1250 CPU Module offers three different I2C Bus channels The PSCO port of the Au1250 is configured to act as a integrated 12C controller The PSCO is connected to the peripheral devices on the CPU module EPROM RTC PLL and the external 12C0 bus available on the EXM32 Connector Refer to the Au1250 datasheet for details In addition two separate exernal 12C controller are available on the Au1250 CPU module The additional external l2C Controller IPs are integrated in the FPGA EXM32_AU1250_User Manual V10 doc page 41 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH CAT1026 RTC 8564 CY22933 EEPROM Real Time Clock Clock Generator Supervisor Supervisor Supervisor Address 1010000x Address 1010001x Address 1101001x A A A 12C0 SDA 12C0_SCL CTRL INT 12C0 SDA l2C1 SDA EXMS2 Module Connector 12C0_SCL 1201_SCL ADDRESSE I2C IP FPGA 12C1 SDA 12C_DDC_SDA 12C1_SCL 12C_DDC_SCL Figure 11 EXM32 Au1250 CPU module PC interfaces In the following explanations only the the external I2C controller I2C1 and VGA DDC I2C Bus is described For a detailed description of i
92. logos or trademarks are property of their respective owners Certification MSC Vertriebs GmbH is certified according to DIN EN ISO 9001 2000 standards Life Cycle Management MSC products are developed and manufactured according to high quality standards Our life cycle management assures long term availability through permanent product maintenance Technically necessary changes and improvements are introduced if applicable A product change notification and end of life management process assures early information of our customers Product Support MSC engineers and technicians are committed to provide support to our customers whenever needed Before contacting Technical Support of MSC Vertriebs GmbH please consult the respective pages on our web site at www msc ge com support boards for the latest documentation drivers and software downloads If the information provided there does not solve your problem please contact our Technical Support Email support boards msc ge com Phone 49 8165 906 200 EXM32_AU1250_User Manual V10 doc page 2 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH Contents Contents WR A EE Ee 3 Document change history RA n ce RR RE OE ae EC E Le 4 T General iInformatio EE 5 1 1 IMTFOGUCTION te TEE 5 1 2 Functional BIOCKS eege ee 6 1 2 1 Block DlagraM caca aia alada aaa Ra eses 7 A 000 00 DE EE 8 2 1 CONNECIONS KORONA ERGE DEE RES DEE Ee 8 2 2 Specificato Mren tatto
93. matically cleared after the transfer finished Writing O to this bit has no effect NOTE All registers including the CTRL register should be set before writing 1 to the GO BSY bit in the CTRL register The configuration in the CTRL register must be changed with the GO BSY bit cleared i e two Writes to the CTRL register must be executed when changing the configuration and performing the next transfer firstly with the GO BSY bit cleared and seconaly with GO BSY bit set to start the transfer When a transfer is in progress writing to any register of the SPI Master core has no effect CHAR LEN This field specifies how many bits are transmitted in one transfer Up to 127 bits can be transmitted CHAR LEN 0x01 1 bit CHAR LEN 0x02 2 bits CHAR LEN Ox7f 127 bits 4 1 14 2 4 Divider register DIVIDER Enz E Access RW R W DIVIDER Reset Value Oxffff DIVIDER The value in this field is the frequency divider of the system clock wb_clk_i to generate the serial clock on the output sclk_pad_o The desired frequency is obtained according to the following equation f wb _clk fe DIVIDER 1 2 4 1 14 2 5Slave select register SS PRS 158 1 1 1 1 70 O Ames R yyy Reset Value 0x0000 ss If CTRL ASS bit is cleared writing 1 to any bit location of this field sets the proper ss_pad_o line to an active state and writing O sets the line back to inactive state If CTRL ASS bit
94. mbH The EXM AU1250 module is equipped with a LFEC3E FPGA This programmable logic device controls many operations of the CPU Module address decoding address and data buffer control LED control Hardware Power Saving Modes control Control for 32Bit Data Bus Mode Integrated SPI Master 2 Integrated I2C Master Integrated UART 16550 LCD Power up Controller The FPGA I O space is mapped into area 0 RCE3 and area 3 RCE3 The FPGA shares its I O space with the Ethernet Controller CAN Controller and external chip select CSA and CSB memory space Example preliminary INTEVT IRQ BIT SIGNAL DESCRIPTION CODE IRQ15 15 PWRFLT Primary Power Supply Fault IRQ14 14 I2C1_IRQ I2C1 controller interrupt IRQ13 13 I2CDDC IRQ 12CDDC controller interrupt IRQ12 12 SPI IRQ SPI controller interrupt IRQ11 11 CFO IRQ CF ATAO interrupt IRQ10 10 CF1_IRQ CF ATA1 interrupt IRQ9 9 CFO_CD CFO card detect IRQ8 8 CF1 CD CF1 card detect IRQ7 7 SDIO CD SD card detect IRQ6 6 UARTO IRQ UARTO interrupt IRQ5 5 UART1 IRQ UARTI interrupt IRQ4 4 UART2 IRQ UART2 interrupt IRQ3 13 CANO IRQ reserved for CANO interrupt IRQ2 2 CAN1 IRQ reserved for CAN1 interrupt IRQ1 1 CANO_ERR CAN channel 0 error interrupt IRQO 0 CAN1_ERR CAN channel 1 error interrupt EXM32_AU1250_User Manual V10 doc page 55 of 110
95. mode To enter hibernate mode the FWTOY bit in the board controll register of the FPGA has to be set The FPGA releases the FWTOY signal connected to the according pin on the AU1250 and the CPLD The CPLD sets the SLEEP signal This signal is available on the EXM32 connector and can be used to shutdown external voltage regulators in the EXM32 System A standby voltage still remains to supply the system with the required standby voltage To enter a proper hybernate mode refer to the AU1250 datasheet for details The EXM32 system can be wake up by releasing the WAKEUP signal available on the EXM32 connector EXM32_AU1250_User Manual V10 doc page 47 of 110 EXM32 AU1250 CPU Module Users Manual MSC Vertriebs GmbH 4 3 Data Bus The EXM32 AU1250 is available in a standard 16 bit and in a optional 32 bit Databus version 4 3 1 16 Bit standard In the 16 bit version the 16 bit Databus of the Au1250 is buffered with a 74LVCR162245 The FPGA generates the output enable and data direction signals for the 16 bit data buffer from the Au1250 bus state controller signals EXM32 Module Connector DATA 16 0 16 Bit Data Buffer DATA 16 0 Figure 14 EXM32 Au1250 16 Bit Bus The following timing diagrams show the EXM32 connector signals depending on the AU1250 bus state controller signals Refer to section 3 2 Static Bus Controller of the AU1250datasheet and section 7 4 2 Bus state co
96. neral Purpose Input signals for EXM32 CPU Module General Purpose Output signals for EXM32 CPU Module 3 3 1 14 MultiMedia Card Secure Digital Memory Card Secure Digital Input Output Card A MultiMedia Secure Digital Memory Secure Digital Input Output Card interface may be provided All signals SDIO DATO SDIO_DAT1 IRQ SDIO_DAT2 RW SDIO_DAT3 SDIO_CLK SDIO_CMD SDIO_WP are LV TTL level signals Bidirectional data line 0 4 bit and 1 bit mode Bidirectional data line 1 4 bit mode interrupt signal 1 bit mode only SDIO Card low active Bidirectional data line 2 4 bit mode read wait signal 1 bit mode only SDIO Card optional Bidirectional data line 3 4 bit mode Host to card clock signal Bidirectional command response signal Write protect active high EXM32_AU1250_User Manual V10 doc page 21 of 110 EXM32 AU1250 CPU Module SDIO_CD 3 3 1 15 Serial Ports User s Manual MSC Vertriebs GmbH Card detect active low All signals are LV TTL level signals External drivers are required to convert the LV TTL signals to the desired physical interface like RS232 RS422 RS485 COMO TXD COMO RXD COMO CTS COMO RTS COM1 TXD COM1 RXD COM1_CTS COM1_RTS Transmitter serial data output from serial port Receiver serial data input handshake signal which notifies the UART that the modem is ready to receive data handshake signal which notifies the modem that the UART is ready to receive
97. nnector alignment pin B o n n a Ei 5 OO 52 pin definiton for 0 8mm pitch Figure 5 EXM32 Au1250 CPU module Connectors Note The EXM32 CPU Module is secured by six M2 5 screws that have to be fastened with 30 Ncm clamping torque EXM32_AU1250_User Manual V10 doc page 10 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 3 1 2 Connector X1 CPU Bus Compact Flash SPI AC 97 PS PCI E Strip A Strip B Pin Signal Pin Signal Pin Signal Pin Signal 1 reserved don t use 2 CF SCKSEL 1 DOO 2 DO1 3 reserved don t use 4 CF_CE1 3 D02 4 D03 5 reserved don t use 6 CF_CE2 5 D04 6 D05 7 CFO_PWEN 8 CF IORD 7 D06 8 D07 9 CF1 PWEN 10 CF IOWR 9 D08 10 D09 11 reserved don t use 12 CF BOES 11 D10 12 D11 13 CFO RESET 14 CF PWE 13 D12 14 D13 15 CF1 RESET 16 CF_WAIT 15 D14 16 D15 17 SPI_SSO 18 CF_IOIS164 17 D16 18 D17 19 SPI SS1 20 CF PREG 19 D18 20 D19 21 reserved don t use 22 CFO RDY IRQ 21 D20 22 D21 23 SPI SCK 24 CF1 RDY IRO 23 D22 24 D23 25 SPI MOSI 26 CEO CD 25 D24 26 D25 27 SPI MISO 28 CF1 CD 27 D26 28 D27 29 GND 30 GND 29 D28 30 D29 31 GND 32 GND 31 D30 32 D31 33 GND 34 GND 33 BEO 34 BE1 35 GND 36 GND 35 BE2 36 BE3 3
98. nternal Au1250 SMBus I2C Controller refer to the Au1250 datasheet 4 1 15 1 Features Compatible with Philips 1 C standard Multi Master Operation Software programmable clock frequency Clock Stretching and Wait state generation Software programmable acknowledge bit Interrupt or bit polling driven byte by byte data transfers Arbitration lost interrupt with automatic transfer cancelation Start Stop Repeated Start Acknowledge generation Start Stop Repeated Start detection Bus busy detection Supports 7 and 10bit addressing mode Operates from a wide range of input clock frequencies EXM32_AU1250_User Manual V10 doc page 42 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 4 1 15 2 12C Clock The external I2C Controller clock source is the variable CPU output clock This clock signal is feed into the SPI controller as well For each 12C controller a maximum wire speed of 400khz is possible CHANNEL SPEED Device DEVICE ADDRESS 400 kHz Au1250 PSC 0 100kHz interface SMBUS Refer to Au12500 datasheet 1 dE External I2C Controller 0x1FFF1000 0x3FFF1000 DDC en External I2C Controller 0x1FFF1800 0x3FFF1800 Each I C Bus channel is available on the module connector motherboard 4 1 15 3 Registers list Name Address Width Access Description PRERlo 0x00 8 RW Clock Prescale register lo byte R X jReceveregister i O i IR Command register Status register
99. nterrupt Register EE lo 12 Receiver Data FIFO trigger level reached FIFO drops below available trigger level 111 o 2 Timeout There s at least 1 character in Reading from the FIFO Indication the FIFO but no character has Receiver Buffer been input to the FIFO or read Register from it for the last 4 Char times 0 0 1 3 Transmitter Transmitter Holding Register Writing to the Holding Register Empty Transmitter Holding empty Register or reading IIR o o 0 4 Modem Status CTS DSR RI or DCD Reading the Modem status register Bits 4 and 5 Logic 0 Bits 6 and 7 Logic 1 for compatibility reason Reset Value C1h 4 1 13 2 3FIFO Control Register FCR The FCR allows selection of the FIFO trigger level the number of bytes in FIFO required to enable the Received Data Available interrupt In addition the FIFOs can be cleared using this register Description Ignored Used to enable FIFOs in NS16550D Since this UART only supports FIFO mode this bit is ignored Writing a 1 to bit 1 clears the Receiver FIFO and resets its logic But it doesn t clear the shift register i e receiving of the current character continues Maar a 1 to bit 2 clears the Transmitter FIFO and resets its logic The shift register is not cleared Ma i e transmitting of the current character LI Mg de Reset Value 11000000b Define the Receiver FIFO Interrupt trigge
100. ntroller of the EXM32 AU1250 user manual A external 16 Bit device is connected to the bits 15 0 of the external data bus X1B_D 15 0 The device is selected with the chip select X1B_CSA and a address match on the Address bus X1B_A 25 1 For the timing Values of the AU1250 Bus state controller signals Ta Tcsoe Tcsoe Twp Twcs Tcsw refer to the AU1250 datasheet and section Initialization The resulting Timing Values on the EXM32 connector are affected by the delay time of the FPGA and the external bus buffers The timing diagrams show a minimum and a maximum delay time between AU1250 bus state controller and EXM32 connector signals and the resulting minimum and maximum time for the EXM32 connector bus state controller signals A 16 Bit device can be accessed 8 or 16 bit wide by analysing the byte enables X1B BE 1 0 EXM32_AU1250_User Manual V10 doc page 48 of 110 EXM32 AU1250 CPU Module Users Manual MSC Vertriebs GmbH 4 3 1 1 16 bit read timing 5 rs Dos 15018 pa RCSW RIVER SR Controller Signals Gg Toa menm EE fo E RADIO Sort 407 Rosa x Data 50 valid P MS A pe O libi Ri 6 19 X1B CSed X18 RBENDA ape E 5 19 xit RBER p C SY pa Us EXM32 Connector Bus State Controller Signals X18_0EN X1B RANK 16 23 16 23 E Z E 2 iminTme max Time xiB DPI DaBpt 18 mu UUU Dabs geval minDelay maxDelay EXM32_AU1250_User Manual V10 doc page 49 of 110 EXM32
101. o Jo io lo 1 lo INIT E Ja e la je le Te e Je e es je Te TR 11 0x00000001 Interrupt Controller 0 Configuration Register The Bits in the Following Registers correspond with the interrupt described in the Following Table Refer to the Au1250 Datasheet chapter 5 1 Interrupt Controller sources BIT NAME DESCRIPTION 31 MAE Done 30 LCD Controll 29 USB Controller 28 GPIO 208 215 Optional external Watchdog Timer Interrupt GPIO215 27 GPIO 207 Not Used 26 GPIO 206 Not Used 25 GPIO 205 Not Used 24 GPIO 204 Not Used 23 NAND Controlller 22 GPIO 203 Not Used 21 RTC Match 2 20 RTC Match 1 19 RTC Match 0 18 RTC tick 17 TOY Match 2 EXM32_AU1250_User Manual V10 doc page 103 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 16 TOY Match 1 15 TOY Match 0 14 TOY tick 13 Camera Interface Module AES Cryptographie 12 Engine 11 PSC1 10 PSCO 9 MAE Frontend 8 UART1 7 GPIO 202 Not Used 6 GPIO 201 Not Used 5 GPIO 200 Not Used 4 MAE Backend 3 DDMA Controller 2 Secure Digital Decoder 1 Software Counter Match 0 UARTO ic cfgOset Address 0x0 1040 0040 BIT 31 3
102. o point interconnects Switch based technology and packetized protocol to deliver new levels of performance and features More information is available at www intel com technology pciexpress and http www pcisig com home Contact pads for up to two PCIE connection lanes are provided in the EXM32 CPU modules specification The PCIE signals are intended to serve as Transmitter Signal positive not available on EXM32 AU1250 CPU Module Transmitter Signal negative not available on EXM32 AU 1250 CPU Module Receiver Signal positive not available on EXM32 AU1250 CPU Module Receiver Signal negative not available on EXM32 AU1250 CPU Module present signal active low not available on EXM32 AU1250 CPU Module PCIE GND PCIE GND for shielding controlled impedance EXM32_AU1250_User Manual V10 doc page 16 of 110 EXM32 AU1250 CPU Module 3 3 Connector X2 User s Manual MSC Vertriebs GmbH 3 3 1 1 IEEE 1394 FireWire not available on the EXM32 AU1250 CPU Module Up to two IEEE1394 ports may be provided on EXM32 CPU Modules FW_GND Twisted Pair A Differential Signals pos Twisted Pair A Differential Signals neg Twisted Pair B Differential Signals pos Twisted Pair B Differential Signals neg Cable Power Status IEEE1394 GND for shielding controlled impedance 3 3 1 2 Serial ATA not available on the EXM32 AU1250 CPU Module One Serial ATA port may be provided on EXM32 CPU Modules SATA_GND 3 3 1 3 USB Transmitt
103. oftware The Ethernet Controller VO space is mapped into Area 0 and 3 of the external memory space The SMSC LAN91C111I shares its VO space with the Flash Memory the USB Controller and the programmable logic device FPGA For detailed description of the memory space mapping please refer chapter 6 2 Off chip Memory Map For a detailed description of the Ethernet Controller please refer to the SMSC LAN91C1 111 Datasheet 4 1 8 USB The Au1250 microprocessor features two integrated USB 2 0 high speed ports A 2 0 compatible enhanced host controller and and a 2 0 compatible USB device with OTG support The USB host controller of the Au1250 processor is connected to port 1 the device controller to port 0 of the EXM32 Au1250 CPU Module EXM32 AU1250 User Manual V10 doc page 26 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH An external power switch and over current detection is implemented in a programmable device FPGA The Power Enable for USB Port 0 and 1 can be set in the peripheral devices control register PDCTRL The status of the overcurrent is available in the board status register BRDSTAT 6 1 7 PDCTRL Peripheral Devices Control Register For a detailed description of the integrated USB controller please refer to Au1250 Datasheet 4 1 9 Graphics Controller 4 1 9 1 Integrated Graphics Controller The Au1250 features an integrated LCD Controller with a maximum resolution of 2048x2048 pixel This contr
104. oller is capable of driving 4 24 bit color STN and TFT displays If 24 Bit Interface is necessary additional 6 Bit of the LCD 2 Interface have to be used In this case no GPIO function is available on the EXM Connector Refer to Table 6 and section 5 1 12 GPIO Interface for details The Au1250 CPU Module provides four signals used to control display power sequences Signal TYPE INIT SIGNAL DESCRIPTION X1C LCD2 VDON O 0 VDON enables digital power supply X1C_LCD2_VCON O 0 VCON enables power inverter voltage X1C LCD2 BLON O 0 BLON Enables backlight inverter X1C_LCD2 DON O 0 DON enables display only STN D STN Displays connect to pin DISP OFF on STN D STN displays Software controlls the timing for the LCD power up seqence The LCD power control signals can be set in the LCD Control Register Refer to section 6 1 5 LCDCTRL LCD Control Register for details EXM32_AU1250_User Manual V10 doc page 27 of 110 EXM32 AU1250 CPU Module User s Manual LCD power supply control sequence MSC Vertriebs GmbH VDON DISPLAY DATA VCON LCD module LCD module stopped active Figure 6 EXM32 Au1250 CPU module LCD power on timing For valid timing values please refer to the display manufacturer s datasheet The AU1250 LCD interface is connected to the EXM32 Connector as follows LCD module stopped
105. ond function the module ID value may be used to address the modules motherboards ID EEPROM on the I C Bus refer to EXM32 AU1250 User Manual V10 doc page 22 of 110 EXM32 AU1250 CPU Module User s Manual 3 4 Debug Connector The Debug Connector accepts a FPC cable Channel 0 connects the debug adaptor to the on board PLDs FPGA CPLD and Channel 1 to the CPUs JTAG Debug Port The on board PLDs FPGA CPLD can be accessed via the debug adaptor or the EXM32 Connector DEBUG 31 Pin FPC Connector RMO 50 90 Bottom contact Weitronic 570 31 30 10 Pin Signal 1 VCC 2 VCCIO 3 TCKO 4 TRSTO 5 TDIO 6 TDOO 7 TMSO 8 SRESET 9 GND 10 TCK1 11 TRST1 12 TDI 13 TDO1 14 TMS1 15 ASEBRK 16 GND 17 TRACECLK nc 18 TRACESYNC nc 19 GND 20 TRACEDATAO nc 21 TRACEDATAI nc 22 TRACEDATA2 nc 23 TRACEDATAS nc 24 TRAGEDATA4 nc 25 TRACEDATAS nc 26 TRACEDATAE nc 27 TRACEDATA7 nc 28 DEBUG DETECT 29 TXD nc 30 RXD nc 31 BOOT nc EXM32 AU1250 User Manual V10 doc page 23 of 110 MSC Vertriebs GmbH EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 4 Hardware Description 4 1 Functional Blocks 4 1 1 CPU The EXM32 Au1250 CPU module is equipped with the Au1250 processor The user can choose to run the CPU at three different frequencies per option of assembly
106. onnected to the lower 8 bit of the external 16 bit data bus of the Au1250 CPU Module COMO TXD COMO RXD COMO RTS COMO CTS UART TXD COM1 TXD EXM32 Module Connector UART RXD COM1 RXD ADDRESSE UART RTS COM1 RTS UART 16550 IP FPGA UART CTS COM1 CTS Figure 9 EXM32 Au1250 serial interfaces 4 1 13 1 UART Clock COMI The FPGA integratet UART uses the AU1250 CLOCKOUT Refer to chapter 5 1 for details Name Source Min Max Resolution Description clk CPU 14 0625 bps 115200 bps UART Clock EXM32_AU1250_User Manual V10 doc page 32 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 4 1 13 2 Registers of the FPGA integrated UART COM1 Base Address 0x1FFF4000 0x3FFF4000 Name Address Width Access Description Receiver Buffer R Receiver FIFO output Transmitter Holding W Transmit FIFO input Register THR Interrupt Enable Enable Mask interrupts generated by the UART Interrupt Identification R_____ Get interrupt information FIFO Control Line Control Register Modem Control Line Status R Status information Modem Status LR Modem Status In addition there are 2 cascaded 8 bit clock dividers The registers can be accessed when the 2 DLAB bit of the Line Control Register is set to 1 At this time the above registers at addresses 0 1 can t be accessed Name Address Wi
107. or SDIO_CD SDIO Card Detect EXM32 Connector UART1 INT UART1 Interrupt Au1250 CPU Module UART2_INT UART2 Interrupt optional Au1250 CPU Module UARTS INT UARTS Interrupt optional Au1250 CPU Module CANO INT CAN Controller 0 Interrupt Au1250 CPU Module CAN1_INT CAN Controller 1 Interrupt Au1250 CPU Module EXM32 AU1250 User Manual V10 doc page 89 of 110 MSC Vertriebs GmbH EXM32 AU1250 CPU Module User s Manual CANO_ERR CAN Controller 0 Error Au1250 CPU Module CAN1_ERR CAN Controller 1 Error Au1250 CPU Module To detect the wake up interrupt source the Interrupt Status register has to be read out Refer to section 1 1 2 IRQSTAT CPLD IRQ Status Register for details The AU WAKE IRO is the logical or of the signals Name Description Source AU PM WAKE Wake up from hibernate Au1250 WAKEUP EXM32 Connector IRQ_EXT1 Extension module 1 Interrupt EXM32 Connector IRO EXTO Extension module 0 Interrupt EXM32 Connector IRQ_MB2 Motherboard 2 Interrupt EXM32 Connector IRQ MB1 Motherboard 1 Interrupt EXM32 Connector IRQ_MBO Motherboard 0 Interrupt EXM32 Connector Externer Watchdogtimer WATCHDOG emo EEN 9 Au1250 CPU module ETH IRQ Ethernet Interrupt Au1250 CPU module Both Signals FPGA_INT AU WAKE IRQz and AU_RTC_IRQ can generate a Wake up interrupt to the Au1250 CPU EXM32 AU1250 User Manual V10 doc page 90 of 110 EXM32 AU12
108. or VO Operation the signal indicates if the selected VO is a 16 Bit Port IOIS16 A Low signal indicates that a 16 bit or odd byte only operation can be performed at the addressed data port in PC Card Memory Mode This signal is used during Memory Cycles to distinguish between Common Memory and Register Attribute Memory accesses High for Common Memory Low for Attribute Memory in PC Card I O Mode The signal must also be active low during I O Cycles when the I O address is on the Bus CPU Data bus lines CPU Address bus lines Byte Enable signals for write cycles only BEO indicates the least significant byte active low Chip Select signals for external devices active low Output Enable signal read strobe active low Write Enable signal write strobe active low Read Write signal for direction control of Data Bus buffers output from CPU Module write cycle low Ready signal from peripheral indicates that a transfer is complete active high Bus Start signal indicates the start of a bus cycle active low EXM32_AU1250_User Manual V10 doc page 14 of 110 EXM32 AU1250 CPU Module User s Manual RESET INS RESET OUT CLKOUT CLK GND IRQ_EXT lt 1 0 gt IRQ_MB lt 2 0 gt PWRFLT SLEEP PWROFF SUSPEND WAKEUP MSC Vertriebs GmbH CPU Module Reset Input active low This output is the system reset generated from the CPU Module to reset external devices active low System Clock generated
109. ot available OXO 1FFF 6000 ATA IDE ATAO CS ATA1_CS ATAO base address OxO 1FFF A000 ATA base address OxO 1FFF BOOO CAN CANO CS CAN1_CS CANO base address OxO 1FFF C000 EXM32 AU1250 User Manual V10 doc page 86 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH CAN1 base address OxO 1FFF DOOO Ethernet ETH_CS Ethernet base address OxO 1FFF E000 6 2 3 Area 1 Area 1 contains the NAND Flash memory space The Au1250 can be equipped with a optional 32 to 128 MByte NAND Flash memory device NAND Flash LBSC_RCS1 NAND Flash base address 0x0_2000_0000 6 2 4 Area 2 The AU1250 CPU provides the Chip Selects AU CF CE12 AU CF CE2 instead of LBSC RCS2 Refer to the Au1250 Datasheet for details X1C A26 and consequently X1A CF SCKSEL determines if Compact Flash or an IDE drive is selected X1C A26 X1A CF SCKSEL 20 gt Compact Flash Socket A X1C A26 X1A CF SCKSEL 21 gt Compact Flash Socket B Compact Flash AU CF CEIR AU CF CE2 Compact Flash base address OxF 0000 0000 6 2 5 Area3 The Area 3 Address Space is reserved for peripheral devices like SRAM or I O devices CSA X1C_CSA CSA base address 0x0_ 3000 0000 The CSA address space is reserved for 16 bit devices CSB X1C_CSB CSB base address 0x0_ 3400 0000
110. ounter 17864 increased by bootloader Manufacturin 0x004 6 BCD 24 12 04 20 18 15 Production Date e g g Date 24 12 2004 18 15 Maintenance 0x00A 6 BCD 01 07 05 20 10 45 Last Service e g Time 01 07 2005 10 45 HW Platform 0x010 16 ASCII 4D 53 43 20 45 58 4D 2D MSC EXM Board ID String 53 48 37 37 36 30 00 00 SH7760 HW Revision 0x020 16 ASCII 34 30 2D 61 62 63 64 65 40 abcdefghi 40 V4 0 66 67 68 69 00 00 00 00 abc Board Revision and Variant Code Serial 0x030 16 ASCII 30 33 30 30 30 39 36 30 03000960011 10 digit series number Number 30 31 31 2D 31 00 00 00 Also on barcode label on the module User Area 0x080 1968 User specific User specific e ASCII Fields must be terminated by 0x00 e Binary LSB on lowest address ascending e Manufacturing Date Maintenance Time o 0 when not supported o BCD Day Month Year Hour Minute Location of the ID EEPROM Hardware DC Bus Device Adr Offset EXM32 AU1250 0 OxA0 0x00 Size 2048 Byte Partitioning System area 0x000 0x07F 128 Byte User area 0x080 0x7FF 11968 Byte Speed 400 kHz Protocol 8 Bit Register Offset EXM32_AU1250_User Manual V10 doc page 110 of 110
111. r Enable Register Offset 0x24 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ET An Wwe An wl Aw Aw Aw An LN w AA w w Ml LN DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NAME VALUE DESCRIPTION 15 IRQ15 0 Power Fault Interrupt is disabled EN 1 Power Fault Interrupt is enabled 14 IRQ14 0 12C1 Interrupt is disabled EN 1 12C1 Interrupt is enabled 13 IRQ13 0 I2CDDC Interrupt is disabled EN 1 I2CDDC Interrupt is enabled 12 IRQ12 0 SPI Interrupt is disabled EN 1 SPI Interrupt is enabled 11 IRQ11 0 CFO ATAO interrupt is disabled EN 1 CFO ATAO interrupt is enabled 10 IRQ10 0 CF1 ATA1 interrupt is disabled EN 1 CF1 ATA1 interrupt is enabled 9 IRQ9 0 CFO card detect interrupt is disabled EN 1 CFO card detect interrupt is enabled 8 IRQ8 0 CF1 card detect interrupt is disabled EN 1 CF1 card detect interrupt is enabled 7 IRQ7 0 SD card detect interrupt is disabled EN 1 SD card detect interrupt is enabled 6 IRQ6 0 UARTO Interrupt is disabled EN 1 UARTO Interrupt is enabled 5 IRQ5 0 UART1 Interrupt is disabled EN 1 UART1 Interrupt is enabled 4 IRQ4 0 UART2 Interrupt is disabled EN 1 UART2 Interrupt is enabled 3 IRQ3 0 CANO controller interrupt is disabled EN 1 CANO controller interrupt is enabled 2 IRQ2 0 CAN 1 controller interrupt is disabled
112. r level 00 1 byte 01 4 bytes 10 8 bytes 11 14 bytes EXM32_AU1250_User Manual V10 doc page 34 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 4 1 13 2 4 Line Control Register LCR The line control register allows the specification of the format of the asynchronous data communication used A bit in the register also allows access to the Divisor Latches which define the baud rate Reading from the register is allowed to check the current settings of the communication Access Description Select number of bits in each character 00 5 bits 01 6 bits 10 7 bits 11 8 bits Specify the number of generated stop bits 0 1 stop bit 1 1 5 stop bits when 5 bit character length selected and 2 bits otherwise Note that the receiver always checks the first stop bit only Parity Enable 0 No parity 1 Parity bit is generated on each outgoing character and is checked on each incoming one Even Parity select 0 Odd number of 1 is transmitted and checked in each word data and parity combined In other words if the data has an even number of 1 in it then the parity bit is 1 1 Even number of 1 is transmitted in each word Stick Parity bit 0 Stick Parity disabled 1 If bits 3 and 4 are logic 1 the parity bit is transmitted and checked as logic 0
113. rupt sources are equal in priority that is the interrupt sources are not prioritized in hardware As a result software determines the relative priority of the interrupt sources See the Au1250 datasheet and chapter 2 6 2 Interrupt Architecture and chapter 5 Interrupt Controller for details Interrupt sources connected to the Au1250 Au1250 Interrupt Active E Interr Interr pon dus ds Contes X1B_IRQ_EXTO low level GPIO 0 B9 0 1 X1B_IRQ_EXT1 low level GPIO 1 C7 1 1 AU_RTC_IRQ low level GPIO 2 D8 2 1 FPGA_INT low level GPIO 5 C10 5 1 AU WAKE IRO low level GPIO 7 A9 7 1 X1B_IRQ_MB2 low level GPIO 16 C22 16 1 X1B_IRQ MBO low level GPIO 27 D17 27 1 X1B_IRQ_MB1 low level GPIO 29 C15 29 1 ETH_IRQ high level GPIO 31 C21 31 1 AU WATCHDOG high level GPIO 215 D20 28 0 The FPGA Interrupt is the described in chapter 1 1 2 IRQSTAT CPLD IRQ Status Register The FPGA_INT is the logical or of the signals Name Description Source PWRFLT Powerfault EXM32 Connector 2C0 INT 12C Controller 0 Interrupt Au1250 CPU Module 12C1_INT 12C Controller 1 Interrupt Au1250 CPU Module SPI_INT SPI_IRQ Au1250 CPU Module Compact Flash 0 Read CFO_RDY_IRQ Ge Y EXM32 Connector CF1 RDY IRO pan Flash 1 Ready Exm32 Comnector CEO CD Compact Flash 0 Card Detect EXM32 Connector CF1_CD Compact Flash 1 Card Detect EXM32 Connect
114. s GmbH 5 1 24 Test Register 1 Output Signals OxF4 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 y Ra w Bay wy Phy Bey Bn Phy B Ban Bi Bey Fay Pay By My DEFAULT 010100101010 010010100000 BIT NAME VALUE DESCRIPTION 15 X2D FR EN 14 X2D FR TXEN 13 X2D FR RXEN 12 X1C AC97 RESET 11 AU DREOO 10 AU_DREQ1 9 AU PSC1 D1 8 AU PSC1 EXTCLK 7 X1C_AC97_RESET 6 X2A_USB1_PWEN 5 X2A USBO PWEN 4 X2A_USB1_PWEN 3 XA_CAN1_EN 2 X2A CANO STB 1 X1D_DACKO 0 X1D_DACK1 O O O OO O O O O OO O O O O O EXM32_AU1250_User Manual V10 doc page 81 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 5 1 25 Test Register 2 Output Signals OxF8 BIT 15 14 13 112 131 10 9 8 7 6 5 4 a J2 1 Jo d Zen el uo HP eue A Bee M er Ba A ea DEFAULT 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 BIT NAME VALUE DESCRIPTION 15 14 13 12 11 10 3 X2D LCD2 EN 2 2 X1C_AC97_SDOUT 7 1 X2D_FR_TXD 0 X2D FR BGE EXM32_AU1250_
115. s masked 6 IRQ6 0 UARTO Interrupt is disabled MASK 1 UARTO Interrupt is masked 5 IRQ5 0 UART1 Interrupt is disabled MASK 1 UARTI Interrupt is masked 4 IRQ4 0 UART2 Interrupt is disabled MASK 1 UART2 Interrupt is masked 3 IRQ3 0 CANO controller interrupt is disabled MASK 1 CANO controller interrupt is masked 2 IRQ2 0 CAN1 controller interrupt is disabled MASK 1 CANT controller interrupt is masked 1 IRQ1 0 CANO error interrupt is disabled MASK 1 CANO error interrupt is masked 0 IRQO 0 CANI error interrupt is disabled MASK 1 CANT error interrupt is masked EXM32 AU1250 User Manual V10 doc page 66 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 5 1 11 IRQCLRMSK IRQ Clear Mask Register Offset 0x2C BIT 15 14 13 12 11 110 9 8 7 6 5 4 3 2 1 0 W P w Vw w w w w w w w Di Div Div Fa Fav 7 DEFAULT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BIT NAME VALUE DESCRIPTION 15 IRQ15 0 Power Fault Interrupt is disabled MASK 1 Power Fault Interrupt is masked 14 IRQ14 0 I2C1 Interrupt is disabled MASK 1 I2C1 Interrupt is masked 13 IRQ13 0 I2CDDC Interrupt is disabled MASK 1 I2CDDC Interrupt is masked 12 IRQ12 0 SPI Interrupt is disabled MASK 1 SPI Interrupt is masked 11 IRQ11 0 CFO ATAO interrupt is disabled MA
116. t n mE eg pe gege 47 4 3 RE NET 48 4 8 1 16 Bit standard ERIT 48 4 3 2 SI iii 50 4 3 3 32 Bit optional iii 51 4 4 melee 54 N ie N EE EE N RE N DE AGE 55 5 1 FPGA Register Description sise 56 5 1 1 BRDREV Board Revision Register Offset 0x00 ie ee ke nano 57 5 1 2 BRDSTAT Board Status Register Offset 0x04 aaa aaa aaa aaa aeecanna 58 5 1 3 BRDCTRL Board Control Register Offset 0x08 eeeeueeaaaa aaa aaa aaa aaa aaa aaaaaaaaci 59 5 1 4 LEDCTRL LED Control Register Offset Ox0C eee ee dd aaa aaa ee ee ee sach 60 5 1 5 LCDCTRL LCD Control Register Offset Ox10 61 5 1 6 CFCTRL Compact Flash Control Register Offset 0x14 i 62 5 1 7 PDCTRL Peripheral Devices Control Register Offset 0x18 63 5 1 8 IRQSETEN IRQ Set Enable Register Offset 0x20 eaeeo aaa aaa aaa aaa ek ee 64 5 1 9 IRQCLREN IRQ Clear Enable Register Offset 0x24 aaa ee aaa aaa dd ee ee nach 65 5 1 10 IRQSETMSK IRQ Set Mask Register Offset 0x28 uua ee aaa aaa ee ek ee 66 5 1 11 IRQCLRMSK IRQ Clear Mask Register Offset 0X20 67 5 1 12 SIGSTAT Signal Status Register Offset Ox30 aaa Re ee 68 5 1 13 IRQSTAT IRQ Status Register Offset OX34 aaa aaa aaa aaa aaa aaa awe ee 69 5 1 14 SWITCHES Board Configuration Register Offset 0x38 i 70 EXM32 AU1250 User Man
117. the top of the FIFO did not have a valid stop bit Of course generally it might be that all the following data is corrupt The bit is cleared upon reading from the register Generates Receiver Line Status interrupt 0 No framing error in the current character Break Interrupt BI indicator 1 A break condition has been reached in the current character The break occurs when the line is held in logic 0 for a time of one character start bit data parity stop bit In that case one zero character enters the FIFO and the UART waits for a valid start bit to receive next character The bit is cleared upon reading from the register Generates Receiver Line Status interrupt 0 No break condition in the current character Transmit FIFO is empty 1 The transmitter FIFO is empty Generates Transmitter Holding Register Empty interrupt The bit is cleared when data is being been written to the transmitter FIFO 0 Otherwise Transmitter Empty indicator 1 Both the transmitter FIFO and transmitter shift register are empty The bit is cleared when data is being been written to the transmitter FIFO 0 Otherwise 1 At least one parity error framing error or break indications have been received and are inside the FIFO The bit is cleared upon reading from the register 0 Otherwise 4 1 13 2 7Modem Status Register MSR The register displays the current state of the modem control lines
118. therboard All signals are LVTTL level signals Up to two digital sound channels may be provided on EXM32 CPU Modules AC RESET AC 97 BCLK I S_MCLK Channel 0 AC 97 SYNC PS0 LRCLK AC 97 SDINO PS0 SCK AC 97 SDIN1 AC 97 SDOUT PS0 SDIO Channel 1 1251_LRCLK 1251_SCK 1251_SDIO PS Mode Codec Reset Master Clock only master mode Left Right Channel Select Word Select Serial Bit Clock no function Serial Data In Out Left Right Channel Select Word Select Serial Bit Clock Serial Data In Out AC 97 Mode Codec Reset Serial Data Clock Bit Clock Frame Sync Serial Data In Primary Codec Serial Data In Secondary Codec Serial Data Out no function no function no function EXM32 AU1250 User Manual V10 doc page 15 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH AC GND Audio Codec Ground for shielding purposes 3 2 1 6 PCI Express Interface not available on the EXM32 AU1250 CPU Module The PCI Express Interface is a new upcoming standard It is a high performance general purpose I O Interconnect defined for a wide variety of future computing and communication platforms Key PCI attributes such as its usage model load store architecture and software interfaces are maintained whereas its bandwidth limiting parallel bus implementation is replaced by a highly scalable fully serial interface The PCI Express Interface takes advantage of recent advances in point t
119. ual V10 doc page 3 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH 5 1 15 GPOUT General Purpose Output Register 0x3C sss 71 5 1 16 GPIO Direction Register 0x40 ss 72 5 1 17 GPIO Data Output Register 0x44 nnne 73 5 1 18 GPIO Pin Status Register 0x48 anar o narco nnnannncnannnns 74 5 1 19 Test Register O Input Signals 0xEQ eeeeaaa aaa aaa aaa aaa aaa aaa wach 75 5 1 20 Test Register 1 Input Signals 0xE4 ii 76 5 1 21 Test Register 2 Input Signals 0xE8 seeeesseeeeesesessssrrrrssssseirrrrssssstsssrrrnrnnssssssrrrrnnn 78 5 1 22 Test Register 3 Input Signals ONEC aaa aaa aaa aaa aaa aaa nnns 79 5 1 23 Test Register 0 Output Signals 0NEO ee 80 5 1 24 Test Register 1 Output Signals ONEA aaa aaa ee nnns 81 5 1 25 Test Register 2 Output Signals 0NEO aaa aaa aaa aaa ek ee 82 5 1 26 Test Register 3 Output Signals OXFC ss 83 6 Programming Guide E 84 6 1 Peripheral Memory Map 84 6 2 Off chip Memory Map 84 6 2 1 DDR2 MemMon EG TTT 86 EE AR N EER OE EE Ree Re RE 86 RE WEE 87 0 2 4 Ataca 87 0 2 Dn EER EE EE na 87 6 3 interrupt ak Dele EE ZA iene iaia alain 89 6 3 1 lcm EE 89 6 4 Au1250 Initialisation preliminary ss 91 6 4 1 CLOCK SPE 91 6 4 2 Bus State Controller sise 91 6 4 3 DDR2 Memory Controller ii 98 6 4 4 Interrupt Controller nnn ek ee ee nsns 101 TAE Ne ee AA OE AR EE sa bi
120. us register mcr 0 4 1 RTS CTS is controled by hardware but can be set or read by software as well RTS is set as soon as the trigger level is reached and reset as soon as the trigger level is underflown If CTS is set the transmission of a full transmitt fifo is interrupted immediately and will be continued at the point of interruption if CTS is reset Software can take take control on the hardware handshake in addition if autoflow is selected Reset Value 0 4 1 13 2 6Line Status Register LSR Description Data Ready DR indicator 0 No characters in the FIFO At least one character has been received and is in the FIFO Overrun Error OE indicator If the FIFO is full and another character has been received in the receiver shift register If another character is starting to arrive it will overwrite the data in the shift register but the FIFO will remain intact The bit is cleared upon reading from the register Generates Receiver Line Status interrupt 0 No overrun state Parity Error PE indicator 1 The character that is currently at the top of the FIFO has been received with parity error The bit is cleared upon reading from the register Generates Receiver Line Status interrupt EXM32 AU1250 User Manual V10 doc page 36 of 110 EXM32 AU1250 CPU Module User s Manual MSC Vertriebs GmbH Framing Error FE indicator 1 The received character at

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