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1. e e e e e e e l UO X090 1000 4 HP m e e Se Bie m Week TOS xb ub AR dd es diste ue BET ole Se age iby Mb ade mie MOR b SE SY Xe m ORIS usos tudo gt SSS bs dae xu Gee et ace Jae id Apr RS Stet IAS due ume Ns SUE oe BAR ter eost ues ib 25216 S A Gh dieu uM dU bue BEI Ord BE te ee ee ECCE Tata Ss RO ee Bs aa he Se a hes 20 bu Jee ahd pis ae ki SSS Mo ee ce OL Fat en du mme UR a OSA le a JM ae at 0 IR DoD SD eo cs ee ae SAS Modify Macrostatus Optional e e e Soe e e s o e e 5 43 Conditional Memory Access Optional es e 5 45 Decode Optional ue GS KD AE yo 9 86 DAM
2. 15 15 0 B15 15 U 15 15 15 15 NRIs U 15 BIS 815 where 15 B15 and R15 are the most significant bits of the A operand B operand and result respectively The c and v microcondition codes can be stored in the microstatus register MS L and V bits respec tively using the MC field of the microcommand In the CPU the carry input CIN to AU can also be specified by the MC field of the microcommand The states can be programmed as CIN 1 CIN 0 or CIN 1 amp Uy EE C21518008 XO The ADD microcommand is A B CIN where CIN is the carry in under MC field control Thus it is possible to add the fixed constants ONE or ZERO to the result or to add the state of the L bit which can contain the carry propagation for multiple precision addition for example A 3 SUBTRACTION The CPU performs true binary subtraction as well as addition This provides considerably greater flexibility in implementing the arithmetic microcommands than would the usual use of complement addition Examples 4 0100 4 1100 2 0010 2 1110 2 0010 2 1110 4 0100 4 1100 2 1110 2 0010 6 0110 6 1010 The notation c in this case indicates that a borrow output is generated by the subtractor The borrow out is of significance only if the two operands represent something other than the most signifi cant bits of
3. 7 21518008 0 APPENDICES APPENDIX A ENGINE ARITHMETIC A A A 1 NUMBER REPRESENTATION e e oo 2 ADDITION gt e e 3 SUBTRACTI ON gt e e e APPENDIX FIXED MEMORY ASSIGNMENTS APPENDIX C CONNECTOR PIN ASSIGNMENTS b I Vogd gd 1 x Figure Tu pede p NO DON C21518008 x0 TABLES Title 1 1 5 o Cal Data 1 Computer Specifications Microstatus Register Bit Definitions gt Cal Data 100 Engine Microcommand Summary e Microcondition Codes for Logical Microcommands Microcondition Codes for Arithmetic Microcommands SO Field Shift Specification e e e e e o Interrupt Vectors amp 5 gt e e gt gt gt gt gt o Connector A Pin Assignments MACROBUS Connector B Pin Assignments MACROBUS e Connector C Pin Assignments e e e Connector D Pin Assignments gt gt e e e gt Connector E Pin Assignments e e e s e gt o Connector Pin Assignments e e e s Connector Jl Pin Ass
4. NOTE Optional Figure 2 2 Cal Data 1 Computer System Organization us 2 3 central Microbus for very high speed communication between the CPU and other Microbus devices and can permit I O channel devices to communicate directly with each other independently of the CPU Macropanel A Macropanel representing the control panel of a general purpose com puter is often provided in an emulation application The Macropanel is serviced by the CPU as an I O device interfacing with the MACROBUS Special support firmware is provided for the Macropanel The primary Macropanel for the Cal Data 1 system is the Cal Data 1 Macropanel Microconsole A Microconsole is available to provide microlevel control and display for checking out and debugging firmware and also for various mainten ance and troubleshooting procedures The Microconsole consists of a remotely mounted Micropanel and a plug in Micropanel control board that permits the user to exercise direct control over the CPU Facilities are provided to construct full microcommands to display microcommands and to execute microcommands on a single step or trap mode basis The Microconsole also contains 32 words of alterable control memory that can substitute for equivalent blocks of CPU control memory The Microconsole can be used in conjunction with the Macropanel and is useful for initial debugging of new firmware as well as for on line troubleshooting of
5. 15 14 13 12 11 10 09 O8 07 O6 05 04 03 02 Ol OO b Byte mode 15 14 13 12 11 10 O9 08 07 06 05 04 03 2 Ol OO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Description For word shifts the A operand and the contents of XR are shifted left one bit XR bit 15 is shifted into A operand bit OO A operand bit 15 is the shift carry out and is also shifted into XR bit OO The shifted A operand result is transferred to the destination The shifted XR result remains in XR Byte shifts are the same as word shifts except that the A operand shift is on the less significant byte only A operand bit 07 is the shift carry out and is also shifted into XR bit OO The more significant byte is unmodified Micro Same as logical open left shift condition Codes C21518008 x0 21518008 X0 Logical Open Right Shift Word or Byte Operation Description Micro condition Codes a Word mode 15 14 13 12 11 10 09 O8 07 06 O5 04 03 O2 01 OO CIN 15 14 13 12 11 10 09 08 07 O6 05 04 03 02 01 OO b Byte mode 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 OO CIN 15 14 13 12 11 10 O9 08 For word shifts the A operand and the contents of XR are shifted right one bit The state of CIN designated by the MC field is shifted into XR bit 15 XR bit OO is shifted into A operand bit 15 A operand bit 00 is the shift carry out The shifted A operand result is transferred to the destination The shifted XR
6. MCD XR X XR C L Yes Determine and insert sign Exit Repeat MUS 5 38 Micro Condition Codes Example AU shift carry v shift overflow 2 1 n 1 otherwise 1 1 otherwise if AU shift result 0 otherwise if AU shift result most significant bit 0 if AU shift result gt 0 0 otherwise if AU shift result least significant bit 0 Multiply the following four bit numbers all registers assumed to be four bits MPR 0101 MCD 0111 MPR L XR 0101 0 0000 1010 0 0111 5 ou 1010 0100 0 1110 0 0100 100i 0 1100 1 0011 b 1010 0100 0110 0010 0011 ee product Lc Explanation Initial condition Shift MPR left test MPR O Add MCD to XR Add L to MPR Shift MPR and XR left NUS Add MCD to XR MUS Exit LC 0 Shift MPR and XR right for final product C21518008 X0 5 5 3 Divide Step The DVS microcommand is a specialized version of the subtract operation conditional with an automatic iterative repeat that permits high speed implementation of a Divide instruction The fixed execution time is two clock cycles per bit plus the time required to preformat the divisor and dividend check for overflow determine the sign of the quotient and format the final result No additional hardware is required for the high speed division since all operations are implemented in control mem
7. These sources are identified on all block diagrams by a shaded triangle in the lower right corner of each block providing signals to the A operand bus The data section utilizes 16 bit parallel data paths and operational elements Provision is made for byte mode operations The general file register FR Structure provides either eight or 16 general purpose registers directly addressable by each microcommand The output of any FR can be selected as either the A or B operand input to the arithmetic logic unit AU and the results of the operation are routed via MB to many destinations including FR within the Engine Dynamic condition codes indicating conditions of the operational results e g overflow negative etc are generated for each microcommand executed These conditions can be saved as static status bits Either the static or the current dynamic conditions can be tested by any micro command 4 3 1 File Registers FR FRs provide general purpose storage within the data section Either eight or 16 FRs labeled FRO to FRL5 of 16 bits each can be implemented The FRs permit the following simultaneous operations to be performed a Any two FRs can be specified as the A and B operand sources to AU b The FR selected as the A operand source can also be specified as a destination register c Any FR can be specified as a destination register for MB 4 3 2 Operand Buses AB BB Operands are transferred to AU via AB a
8. chassis with provision for air filters we Modular power supply providing 36 A at 5 Vdc C21518008 x0 Electrical and Electronic Wide timing margins Single phase clock 2 5 SPECIFICATIONS Low noise internal power distribution and grounding system Convenient external I O cabling Extension chassis available System designed to meet UL standards to 50 C ambient operating temperature lO to 90 relative humidity without condensation Bipolar TTL integrated circuits multisourced Extensive use of MSI and LSI High noise immunity I O drivers and receivers Conservative component derating Metal can transistors and hermetically sealed passive devices only General specifications for the Cal Data 1 Computer are given in Table 2 1 Table 2 1 Cal Data 1 Computer Specifications Characteristic Specification CONTROL Microcommand length Execution rate Microcommand classes Special operations Conditional Skip branch Fixed control memory Alterable control memory C21518008 Xx0 High speed microprogrammed digital com puter designed for efficient emulation of general purpose computer architectures and for direct custom applications 48 bits 165 ns min 330 ns if skip or branch is made clock rate is adjustable 8 arithmetic 16 logical 8 special Special microcommands include double precision Shift Multiply Step and Divide Step Each microcommand with cond
9. 500 Condi 03 503 02 502 01 501 00 500 tional i The update functions permit each PS bit to be left unal tered unconditionally reset unconditionally set or 1 fied by the contents of the corresponding four bits of the A operand which is routed via MB If MS is selected as 621518008 0 the A operand source the MMS microcommand can transfer the L V N and Z microstatus bits directly to PS Micro During the execution of MMS AU is set to copy AB onto condition MB leading to unpredictable generally meaningless Codes microcondition codes 5 5 6 Conditional Memory Access Optional For emulation of a set of instructions involving one or more operands it is usually desirable to read some operands from memory in a read restore mode and others in a read modify write mode The read restore mode is associated with operands that are not modified by the instruc tion Examples are a Load memory to hardware register b Add memory to hardware register C Compare memory with hardware register For high emulation speed the address mode and operand fetch operations are generally executed before the specific operation is determined so the memory access mode is not known at the time the operand fetch cycle is initiated If a read restore mode is used in all cases an extra memory cycle is required to write the modified operand Use of a read modify write operati
10. The Engine is a reliable solid state device designed to perform con tinuously for many years without degredation Preventive maintenance consists of performing the following tasks every six months a b Inspect the boards for damaged wires or components or other obvious defects Using a low pressure source of air 75 psi one foot from the board or 5 kg cm2 30 cm from the board blow off accumulated dust and foreign matter Check the 5 Vdc input to the Engine should be within 5 percent Another aspect of preventive maintenance is proper handling of the unit The following points should be observed a b Always be sure that system power is OFF before installing or removing any board Install each board with the component side toward the front of the chassis Check each board for proper orientation before attempting to install it Because the connectors are keyed excessive force applied to a reversed board can result in connector damage Make sure that the board is completely and evenly seated Insert and remove each board slowly and carefully so that it does not make contact with adjacent boards Never use components as finger grips use the grip areas at the corners of the board To prevent oxides from forming the gold plating do not touch connector pins 6 43 CORRECTIVE MAINTENANCE Repair of the Engine in the field is not recommended If a malfunction is detected replace the board with a sp
11. dE lh E OE CES IR s SAO he 8 25 5 SPERCPIERICATIONS i se MEL ie et WD Ld d Ur UT O1 S aS D d dd ar Mrd ere SECTION 3 PHYSICAL DESCRIPTION 3 1 SYSTEM HARDWARE 4 919 90 9 e ET XC des te See ENGINE BOARDS e Wi SECTION 4 ENGINE 4 1 FUNCTIONAL DESCRIPTION s e e o e o o e dede o o o o o o Se ae 4 4 2 CONTROL SECTION yc a es r is 4 4 2 1 Control Memory CM s IECUR GE ax Rs om Veo SR Sa at Location Counter A Microcommand Register CR 4 Conttol SESGE abe 4 4 4 4 4 NN NN e ARAR Loop Counter LC x 1 ub OD Ba a a 4 3 DATA SECTION ter oie o dan ind cia File Registers FR QC ee ae ee es EL EE Operand Buses Arithmetic rogic Unit AU 99 wk We oe a AU Shift Elements SX and Shift Register XR 4 12 M Bus MB uut o ee Shee ae cae RS cu ese um MiorseondibiondOdeSuo i ara wer woes Gat Be ee me Vil Microstatus Register MS Word and Byte Operations i 109 s
12. cuits data paths registers control logic and timing circuitry of the machine The CPU communicates with the rest of the system via the Microbus 2 252 Microbus The Microbus is a universal bus that is the main communication and con trol channel of the system The Microbus transmits data and control in formation between the CPU and all elements of the system The Microbus can be conditioned by one or more I O channel adapters to interface with a wide variety of I O devices obeying specific interface rules The primary channel adapter of the Cal Data 1 system is the Cal Data 1 MACROBUS Channel Adapter 2 223 MACROBUS Channel Adapter The MACROBUS Channel Adapter MCA provides data address and control circuitry for parallel I O operations in the system The MCA frees the 21518008 2 1 Figure 2 1 Cal Data 1 Computer System with Memory Management Unit 128K Words of Cal Data l6KX16 850 ns Core Memory and Serial I O Controller 21518008 6 MACROBUS TERMINATOR SERIAL 1 0 MACROPANEL CHANNEL ZZ fos umm BOARD cad RUNE MEMORY LA MANAGEMENT UNIT M C R 0 B U S Unc Uo SG e e e PERIPHERAL CONTROLLER SYSTEM INTERFACES SPECIAL FUNCT IONS 1 0 CHANNEL ADAPTER N AER D 1 0 CHANNEL N MACROBUS TERMINATOR MICROBUS COMMUNICATION CHANNEL AND INTERNAL CONTROL
13. Conditional Memory Access A operand optional Conditional Memory Access B operand Decode optional C21518008 XO0 TS 5 5 The following symbols are used in addition to many defined in Table 1 1 DN CIN absolute value of contents of Boolean complement Boolean AND Boolean OR Boolean exclusive OR equal to less than greater than or equal to not equal to arithmetic addition two s complement arithmetic subtraction two s complement arithmetic multiplication arithmetic division A operand to AU from A operand source specified by the microcommand nth bit of A A b ts m to n B operand to AU from B operand source specified by the microcommand result word on MB more significant byte of R less signficant byte of R destination location specified by the microcommand carry input replaces The logical microcommands listed in Table 5 1 can be executed in either the word or byte mode With one exception SXA the operation is per formed on the full pair of operand words in AU and tHe 16 bit result is transferred to the destination via MB 21518008 0 Microcondition codes are determined on the full word in the word mode and on the less significant byte in the byte mode This is illustrated below 15 O0 15 00 15 00 15 00 15 00 15 08Y07 00 ne Microcondition Microcondition Code Test Code Test Th
14. The logical AND of the A and B operands is added to the A operand and to the value of CIN designated by the MC field and the result is transferred to th destination Micro Addition Table 5 3 condition Codes Example Add the absolute value of the less significant byte of to the operand 110 1111111110010010 mask 0000000001111111 18 0000000000010010 110 1111111110010010 0 0000000000000000 92 1111111110100100 The microcondition codes generated are 0 0 2 0 1 5418 di 21518008 5 amp 5 SPECIAL MICROCOMMANDS C21518008 X0 The seven special microcommands listed in Table 5 1 provide a powerful extension of the basic logical and arithmetic microcommands Four of these are standard and have general application in all emulation micro programs Three microcommands are defined as optional since they must be tailored to a particular emulation system The hardware elements that implement the optional microcommands are modularized to permit them to be either omitted or redefined without affecting the basic hardware of the Engine Microcondition codes generated for the special microcommands are generally identical to those defined for the arithmetic microcommands with major exceptions The overall uses and limitations of the special microcommands are described in the following paragraphs 5 5 1 5 20 Shift
15. as opposed to complementary addition Negative numbers are assumed to be represented as two s complements of positive numbers although one s complement arithmetic can be performed since the programmer has independent con trol of the carry and borrow inputs to AU complete description of binary arithmetic operations in the CPU is given in Appendix A The carry and overflow microcondition codes differ for the addition and subtraction operations as does the use of the carry in term The data value microcondition codes z n p and d are the same for addition and subtraction and only on the value of the arithmetic result Arithmetic be executed in either the word or byte mode In either mode the specified operation is performed on the full pair of operand words The 16 bit result is transferred to the destina tion via MB The microcondition codes are determined on the full word in the word mode and On the less significant byte in the byte mode see illustration in subsection Di 3 The microcondition codes for addition and subtraction operations are Table 5 3 c21518008 x Table 5 3 Micro Condition Code 21518008 M Addition or Subtraction Microcondition Codes for Arithmetic Microcommands a15 R15 U 23150 R15 A07 R07 R07 Addition 15 15 Ris A07 fi R07 A15 N 83150 25 Addit
16. circuitry located on a separate Emulate Board This circuitry provides a Automatic table generated addresses to CC to steer the micro program directly to specific emulation microroutines by passing lengthy processing to decode instruction codes and addressing modes b Automatic interrupt microroutine location entry to CC Automatic table generated modifiers to microcommands read from CM d Automatic modification of processor status conditions for the emulated instruction e Direct designation of word or byte mode operations Emulation related features are described in a separate emulation user manual available for each computer model 4 2 1 Control Memory CM C21518008 X0 The control memory is a high speed random access unit Three device implementations can be used Read only memory ROM These bipolar semiconductor devices are organized on chips of four by 256 or four by 512 bits Twelve such devices implement each 256 word or 512 word CM page The code pattern in each chip is permanently inscribea during the factory manufacturing process and cannot be altered ROM is used for faghovetune production of fully debugged firm ware p W xooTH OOT Note 7 MBOO CONTROL CONTROL 47 s 09 STACK CC11
17. 02 01 OO do Convert DVR to a positive number 15 14 13 12 11 10 O9 08 07 O6 05 04 O3 O2 01 OO B Test for DVR lt 2 X DVD If true set overflow and exit If no overflow shift DVD left and set initial conditions 0 LC 15 Program DVS control fields as follows SB 03 branch if LC 0 before decrementing SIA DVS DN DVDL NX 51 execute next microcommand if branch AO DVDM 5 modify link status CIN 1 MX 0 no operation DVR location of DVS The symbolic microassembler automatically sets up all fields except DN AO and BO DVS is used in conjunction with a double length left shift on the A operand and XR with L added to XR The final double length result must be left shifted one bit after the final iteration The quotient is in XR and the remainder in the A operand source The sign of the quotient is determined and set separately Qm C21518008 x0 8 The basic microcommand sequence is illustrated Shift DVDM left one bit below DVDM DVR 1 test carry No Set LC 15 Shift DVD left one bit CIN 0 Shift DVD left one bit CIN L Execute DVS Repeat DVS Shift DVDL left CIN L Insert sign in quotient C21518008 X0 Divide Overflow 5 42 Example 1 0101 0011 0 Exit LC 0 Divide the following numbers all registers are assumed t
18. 2 HLINT H DS16 H 0517 VIRTAD H 2 00 2 CCOO1 L 2 CCOO2 L 2 2 4 2 CCO05 L 2 CCO06 L 2 CC007 L 2 2 CC009 L GND 2 CCO10 L 2 CCO1l L 5V 15V GND LTCL L PBBSY L HALTP L MSR15 L RESET L BG7 IN BG7 OUT BG6 IN BG6 OUT BG5 IN BG5 OUT BG4 IN BG4 OUT NPG IN NPG OUT 5 Vdc 15 Vdc Ground Line Frequency Clock Processor Bus Busy Panel Halt Microstatus Register 15 Reset Bus Bus Bus Bus Bus Bus Bus Bus Grant Grant Grant Grant Grant Grant Grant Grant In Out In In Out In Out Nonprocessor Grant In Nonprocessor Grant Out These signals are assigned on the backplane but are not used on this assembly 2 Signal used only on Engine 2 1032euuoo2 Control Control Control Control Control Control Control Control Memory 00 Memory 01 Memory 02 Memory 03 Memory 05 Memory 07 Memory 09 Memory 11 Decode Address OO Control Control Control Control Memory 13 Memory 15 Memory 17 Memory 19 Switch Register O Control Ground Control Control These signals are assigned on the backplane but are not used on this assembly 1 Signal used only on Engine 1 2 Signal used only on Engine 2 Memory 21 Memory 23 Memory 25 CMOO0 H CMOOL H CMO02 H CMOO3 H 5 CM007 H CM009 H
19. 5 3 6 Complement B Mnemonic Operation Description C21518008 X0 MVA 02 R A R 3 DN The A operand is transferred unmodified to the destination MVB 03 B 3 DN The B operand is transferred unmodified to the destination OCA 04 3 DN The logical or one s complement of the A operand is transferred to the destination Binary A 0110110100101100 R 1001001011010011 OCB 05 R B gt DN Octal 066454 111323 Hexadecimal 6D2C 92D3 The logical or one s complement of the B operand is transferred to the destination 5 3 7 Mnemonic Operation Description 5 3 8 AND A B Mnemonic Operation Description 5 3 9 AND A B Mnemonic Operation Description 5 3 10 Not OR Mnemonic Operation Description 06 DN The logical AND of the A and B operands is transferred to the destination NDB 07 R ANB DN The logical complement of the B operand is ANDed with the A operand and the result is transferred to the destination NDA 08 R ANB DN The logical complement of the A operand is ANDed with the B operand and the result is transferred to the destination NOR 09 AUB DN The logical NOR of the and B operands is transferred to the destination C21518008 x0 5 3 11
20. 75 characters per second fanfold tape Card Reader High speed photoelectric card reader 300 cards per minute with code conversion in the controller d Line Printer 80 or 132 column printer 125 or 200 lines per minute e Memory extensions FIRMWARE DEVELOPMENT AIDS Cal Data offers specialized hardware and software elements to aid users in developing custom firmware These are briefly described below Alterable Control Memory Alterable Control Memory ACM is a modular plug in unit that contains increments of 256 words of electrically alterable control memory The ACM also contains alterable elements associated with instruction emula tion and decoding With the ACM a programmer can load or read the contents of control memory directly and execute trial firmware code at normal processor execution speeds The ACM is particularly useful for dynamic system tests where external real time events must be considered to fully eval uate a firmware microprogram The ACM is supported by a software oper ating system that permits the programmer to use a teleprinter to control the system E Support Software The following software is available to support firmware development a Symbolic Microassembler This program is a complete symbolic assembler that permits convenient coding and listing of microprograms It is written in Cal Data 135 emulator language and can be run on any Cal Data 135 or compatible computer having the required
21. Bus Grant 6 5 Vdc Bus Grant 5 Ground Bus Request 5 Ground Ground Bus Request 4 Ground l Bus Grant 4 AC Low DC Low Address 01 0 L Address 00 Address 03 Address 02 Address O5 Address 04 Address 07 Address 06 Address 09 L Address Address 11 Address 10 Address 13 Address 12 Address 15 i Address 14 Address 17 Address 16 Ground Control 1 Slave Synchronization Control 0 Master Synchronization Ground These signals are assigned on the backplane but are not used on this assembly 9TqeL SnHONHOVM sQueuubrssy 4 io32euuoj Q E si np O 200 A M M M M M M M M M A A A A A Q a 3 These signals are assigned on the backplane but are not used this assembly 5V 15V GND MB004 L MBOO6 L MBO08 L MBO10 L MB0O12 L MBO14 L ABOO0 H ABOO2 H 4 ABOO6 H ABOO8 H ABO10 H ABOll H ABO12 H ABO14 H Dppppsppp iimEmuXEuxux Sjuswuhbtssy 210329uuo5 _ Power Failure Interrupt Halt Interrupt Data Switch 16 Data Switch 17 Virtual Addres Control Count Control Count Control Count Control Count Control Count Control Count Control Count Control Count Control Count Control Count Ground Control Count Control Count S 00 01 02 03 04 05 06 07 08 09 2 PFINT H
22. C21518008 X0 B 0A Examples 4 0100 4 1100 2 40010 2 1110 6 0110 6 c 1010 4 0100 4 1100 2 1110 2 0010 2 0010 2 1110 The notation indicates that a carry output is generated by AU This carry out is generally of no significance in addition unless the two operands represent something other than the most significant bits of a multiple precision set of numbers such a case the carry out bit can be saved as the link L bit and added to the next most significant set of bits when the next step of the multiple precision addition is performed For example suppose that the following two eight bit numbers are added using a four bit adder 44 0100 1100 23 1110 1001 0000 T 0101 Add link 0001 21 0001 0101 In the previous example none of the additions resulted in an arith metic overflow i e all results are within the maximum number range possible which for the four bit numbers is 27 1 range 277 An overflow occurs if two positive numbers are added with a sum greater than seven 5 0101 4 0100 7 1001 overflow The negative seven is an incorrect result and the overflow is deter mined by a change of sign to negative when the two positive operands are added A carry out is not generated The carry and overflow condition orders for addition are determined in the CPU by
23. CS CM MB11 MBOO MB11 MBOO MICROCOMMAND LOCATION COUNTER AS a cu CC _ INTERRUPTS INTERRUPT INTERRUPT PRIORITY ENTRY MCA EMULATE INSTRUCTION 8 ADDRESS us EMULATION BB15 ENHANCEMENT sELECTED CM47 cMoo MICROCOMMAND BBOO DATA S REGISTER gt SELECTOR CIRCUITRY BITS fen ned SECTION TIMING INTERNAL TIMING AND AND CONTROL CONTROL SIGNALS v 4 provides signals to the A operand bus see Figure 4 4 CM47 b Programmable read only memory These bipolar semi conductor devices are organized on chips of four by 256 bits pin and speed compatible with the equivalent ROM The code pattern in each device is electrically and permanently in scribed by a portable programming device PROM is used for development and field debugging of firmware and also for low production firmware packages c Alterable Control Memory Cal Data ACM is a complete modular control memory that can be installed in the computer in addition to or in place of ROM and PROM devices is imple mented with bipolar random access memory devices that can be electrically altered read write When installed in the com puter ACM can be loaded and read via the MACROBUS using I O microcommands The ACM can then take control of the CPU for execution of ACM firmware at real time processor speeds The ACM is most useful for initial and on
24. DESCRIPTION 3 1 SYSTEM HARDWARE All Cal Data Engine and system elements are modular and can be mounted in a standard chassis Figure 3 1 that occupies 10 5 inches 26 7 cm of a 19 inch 48 cm RETMA rack This modularity gives the user maximum flexibility in system design and configuration The standard computer chassis dimensions are 10 4 inches 26 5 cm high 19 0 inches 48 3 cm wide 24 0 inches 61 0 cm deep Hardware items included with the standard computer chassis are a Chassis box with backplane b and bottom covers c Hinged fan panel and four fans d Chassis slides e Macropanel bezel and overlay A power supply mounts at the rear of the chassis The ac power cord exits from a control panel accessible at the rear of the chassis This panel also has the ac line switch fuses convenience outlet 115 Vac model only and Macropanel lock switch The four fans provide horizontal positive pressure air flow across the vertical computer boards and power supply The fan panel is hinged to permit moving the fans when boards are removed or installed System electronics are mounted on modular printed circuit boards that insert vertically through the top of the chassis into connectors mounted on the backplane in the bottom of the chassis The backplane provides printed circuit and wire wrap connections between all boards Device controller cables are generally connected at the top edge of I O boards by means of flat ca
25. O6 05 04 03 02 01 OO b Byte mode 15 14 13 12 11 10 O9 08 07 06 05 04 02 O1 00 CIN N Description For word shifts the A operand is shifted right one bit The state of the microstatus bit ORed with the value of CIN designated by the MC field is shifted into bit 15 Bit 00 is the shift carry out The result is transferred to the destination Byte shifts are the same as word shifts except that the shift is on the less significant byte only The value of N ORed with CIN is shifted into bit 07 The more significant byte is unmodified The resulting word is transferred to the destination Micro sondi tibi a Word mode b Byte mode Codes A00 v 15 CIN v A07 CIN U N z lif z lif otherwise otherwise 1if Rl5 1 lif RO7 1 otherwise otherwise 1 if 1 if otherwise otherwise 1 if ROO 1 1 if ROO 1 otherwise otherwise C21518008 XO Arithmetic Closed Right Shift Word or Byte Description Same as logical closed right shift 5 5 1 2 Double Precision Shifts Double precision shifts involve AU shift elements and XR When a double precision shift is specified in the SO field an XR shift operation specified by the FN field is ignored Swap Halves Word or Byte Description Operation on the A operand and the microcondition codes generated are the same as for single precisi
26. a multiple precision set of numbers In such a case the borrow out bit can be saved as the link L bit and then subtracted from the result of subtracting the next most significant bits For example suppose that the following two eight bit numbers are subtracted using a four bit subtractor 60 0011 1100 30 0001 1110 es T 1110 Subtraction Link 0001 30 0001 1110 Overflow results from subtraction as from addition when the result is outside the range of the number system 2 1 lt result 2 for a four bit range The borrow and overflow condition codes for subtraction are determined in the CPU by c 215 15 A15 R15 U 815 fl R15 v a15 15 R15 15 15 R15 The borrow is designated c in the computer The microcondition codes can be stored in the microstatus register L and V bits respectively using the MC field of the microcommand In the CPU the borrow input also CIN to AU can also be specified by the MC field of the microcommand The states can be programmed as J CIN 1 CIN 0 or CIN L The SUB microcommand is A B CIN where CIN is the borrow in under MC field control c21518008 10 cs FIXED MEMORY ASSIGNMENTS System interrupt vectors two words per vector are given in Table B 1 Only those vectors used by the Cal Data computer and standard options are given Other vector locations are reserved Users should obser
27. for shifting an AU operand The following can be performed a Left shift one bit b Right shift one bit logical or arithmetic c Swap more significant and less significant bytes d Swap more significant and less significant halves of the less significant byte For shift operations the L bit in MS is normally used as the shift carry in and c is the bit shifted out of SX This carry bit can be saved as L for the next AU operation Provision is made for both single and double length shifts either of which can be logically open closed or arithmetic Double length shifts are performed in conjection with XR which is a l6 bit shift register In this case the L input and c output are dependent on the direction of the shift For left shifts SX holds the more significant 16 bit word For right shifts XR holds the more significant word Shifts are performed by using shift operation codes in microcommands Because the A operand is always used in the shift AU performs a copy AB operation Shift microcommands must specify the type of shift to be performed and the carry input function Multibit shifts can be performed by the use of LC by setting up a shift count and repeating the microcommand This permits execution of shifts of all types to be performed in one clock step per bit shifted Bus MB part of the Microbus receives the resultant output from an AU or Shift operation and provides the transfer path to all inter
28. memory con figuration b ACM Software Operating System This program is designed to provide operational control over execution of firm ware in the ACM It requires that the Cal Data 135 emulator be resident in control memory FEATURES The Cal Data computer architecture combines general microprogramming capability with specialized optional features permit high emulation speeds with efficient control memory space utilization The mechanical design used provides full modularity mounting fl xibility and service convenience Cooling power distribution and the r critical system re quirements are optimized for OEM applications Conservative electrical implementation ensures wide margins readily available components and reliable operation over a wide environmental range Subassemblies are C21518008 x0 eal 2 5 designed for easy assembly and automated testing and the overall system is structured for simple straightforward manufacturing procedures Basic design features of the Cal Data computer system are 48 bit microcommand word length Parallel execution of multiple functions per microcommand l65 ns microcommand execution time l6 bit data word length l6 multipurpose file registers 16 bits each Nine additional registers accessible by microcommand l6 level hardware pushdown stack Microcommand sequence repeat loop counter Optional high speed emulation instruction decode function generati
29. result remains in XR 07 06 05 04 03 02 Ol OO Byte shifts are the same as word shifts except that the A operand shift is on the less significant byte only XR bit OO is shifted into A operand bit 07 The more significant byte is unmodified a Word mode b Byte mode AOO AOO v XROO A15 v XROO D 07 z l if A 0 z 1 if AL 0 O otherwise 0 otherwise n l if XR15 1 1 if XR15 1 O otherwise O otherwise 1 if A gt 0 1 if AL O otherwise otherwise d 1 if AOO 1 1 if AO0 1 otherwise 0 otherwise 5 31 Logical Closed Right Shift Word or Byte Operation a Word mode 15 14 13 12 11 10 09 08 07 06 05 04 03 O2 01 OO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 b Byte mode 15 14 13 12 11 10 09 08 07 06 05 04 03 O2 01 00 MIHI FC Description For word shifts the A operand and the contents of XR are shifted right one bit bit 00 is shifted into A operand bit 15 A operand bit 00 is the shift carry out The shifted A operand is transferred to the destination The shifted XR result remains in XR Byte shifts are the same as word shifts except that the A operand shift is on the less significant byte only XR bit OO is shifted into A operand bit 07 The more significant byte is unmodified Micro Same as logical open right shift condition Codes C21518008 X0 21518008 Arithmetic Open Right Shift Word
30. 00001 CIN O 0000000000000000 R 7818 0001111010001010 The microcondition codes generated are 0 0 0 0 1 0 Another example where overflow is affected 32 766 0111111111111110 1 1 0000000000000001 TCIN 1 0000000000000001 32 768 1000000000000000 The microcondition codes generated are c 0 v i1 z2 0 n 1 p 0 dad 0 C21518008 x0 5 4 6 Decrease Mnemonic Operation Description Micro condition Codes Example C21518008 x0 DEC 15 R A 1 CIN gt DN The quantity one and the value of CIN designated by the MC field are subtracted from the A operand and the result is transferred to the destination If CIN is ONE the A operand is decreased by two otherwise it is decreased by one Subtraction Table 5 3 Decrease the A operand by two if the L microstatus bit is set decrease by one otherwise a If L 1 1 0000000000000001 1 1 0000000000000001 CIN 1 0000000000000001 1 1 1111111111111111 c The microcondition codes generated are 1 borrow 0 2 0 1 c P 0 d 1 b If L 0 A 1 0000000000000001 1 1 0000000000000001 CIN 0 0000000000000000 0 0000000000000000 The microcondition codes generated c 0 v 0 z 1 n 0 07 d 0 5 4 7 Add A Masked Mnemonic MSA 16 Operation R A ANB cIN DN Description
31. 2019 south ritchey street santa ana california 92705 714 558 8211 CAL DATA 100 ENGINE P N C81080180 AND C81080190 TECHNICAL MANUAL C21518008 X0 DOCUMENT C21518008 Revision XO January 1975 Cal Data MACROBUS QUADBOARD and HEXBOARD are trademarks of California Data Processors i The information herein is the property of California Data Processors Transmittal receipt or possession of the in formation does not express license or imply any rights to use sell or manufacture from this information and no re production or publication of it in whole or in part shall be made without written authorization from an officer of the above firm 15i00 V copyright 1975 california data processors REVISIONS Revision Date Approval Description XO 3 75 Preliminary The revision history of each page in this document is indicated below d P C21518008 X0 a O 11 amp He H BRWNYE 1 H FS Ut i WD FH He NON HS H For 004 d Ig NH l N reer MAANA NNA A w N v w v w Dd v RARS QOoO0Q00000Wm O Ui i I0 HP FW JA oJ gd gd od 1 gt U to P gt gt 21 Je TUJ gt M 5 1 INTR
32. CMO11 H 2 DADOO H CMO13 H CM015 H 2 CM017 H 2 CM019 H SRO L CMO21 H GND CM023 H CM025 H 5V 15V GND CMO04 H CMO06 H l EMINH L CMO08 H CMO10 H CMO12 H CMO14 H 2 DADO1 H 2 16 2 CM018 H CM020 H CM022 H CM024 H CM026 H CM027 H 5 Vde 15 Vdc Ground Control Control Emulate Control Control Control Control re ce ex ol Memory 04 Memory 06 Inhibit Memory 08 Memory 10 Memory 12 Memory 14 Decode Address 01 Control Control Control Control Control Control Control Memory 16 Memory 18 Memory 20 Memory 22 Memory 24 Memory 26 Memory 27 G O 9Td L w OX 8008T5TZ2O Control Memory 2 Control Memory Control Memory Control Memory Control Memory Control Memory Control Memory Control Memory Instruction Repeat Control Memory 41 Control Memory 43 Control Memory 45 Control Memory 47 Decode Address 03 Ground System Clock CM028 H CM029 H 2 CM031 H 2 CMO30 H CMO33 H CMO35 H CM037 H CM039 H IRPTE L CM041 H CM043 H CM045 H CM047 H 2 DADO3 H Reserved GND Reserved SYSCK L Ej GND CMO32 H CM034 H 2 DADO2 H CM036 H CM038 H CMO40 H CM042 H 2 CPEN L CM044 H CM046 H 2 ACMSL L 2 AUXRM L IRINH L IWAIT L GND 45 Vdc 15 Vdc Ground Control Control Memory Memory Decode Address Control Control Control Control Memory Memory Memory
33. Data 1 Computer Figure 2 1 is a high speed microprogrammed digital computer designed for application in a wide variety of computing and control applications Microprogramming combined with a powerful and flexible hardware architecture centering around the Cal Data 100 Engine and Microbus permits the basic computer to be fully optimized to a specific application The Cal Data 100 Engine is designed primarily for efficient high speed emulation of general purpose computer archi tectures It can also be applied as a direct function processor by im plementation of problem oriented microprograms 2 2 SYSTEM ORGANIZATION The overall system organization is shown in Figure 2 2 The system consists of a set of hardware and software elements that can be utilized in a wide variety of applications A brief description of the elements of the computer system is given below Details are given in other sec tions of this manual and in supporting manuals 2 2 1 Engine The central element of the system is the Engine CPU divided into con trol and data sections and controlled by microprogram sequences firm ware stored in a control memory By changind the contents of control memory the entire operation of the system can be altered An emulation system is implemented by placing appropriate firmware in control memory causing the CPU to operate like the computer being emulated The control and data sections contain the internal arithmetic logic cir
34. FO6 L SPFNC H INHBF L EMLAT H PFAIL L AUCIN L WRITE L IRERD H INTR H MMCO L MMCl L 2 7 1 SLINT H 2 DRWEN L 2 1 2 EIAO03 H 2 EIA005 H 2 EIA007 H EIAO09 H 11 EIAO13 H EIAO15 H l3 H H H H HN x IN INS ES FNNDN LD Reserved MINTP L BYTDA L Reserved MARLD H CCCEN H SPRlA L SPR19 L SPRlB L MLTPY L ENSPF H CRO08 H Reserved Reserved FILE6 H XA815 L XA007 L RSTRA L YELLW L BYTMD L MSO06 H RRWEN L EIAO00 H EIAO02 H EIAO04 H EIAO06 H EIAO08 H EIAO10 H EIAO12 H EIAO14 H Microinterrupt Byte Data Management Address Load CC Count Enable Special Register 1A Special Register 19 Special Register 1B Multiply Enable Special Function Microcommand Register 08 File 6 Inhibit A Field File 8 to 15 Inhibit A Field File O to 7 Restore A Yellow Byte Mode Microstatus Register 06 RR Write Enable Emulate Emulate Emulate Emulate Emulate Emulate Emulate Emulate Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Address Address Address Address Address Address Address Address 8 O 9Iqd L sS3ueuubrssvy X10329euuoj These signals are assigned on the small processor interconnection board but are not used on this assembly 1 2 Signal used only on Engine 1 Signal used only on Engine 2 NC AT A
35. Memory 32 34 02 36 38 40 42 Control Panel Enable Control Memory 44 Control Memory 46 Alterable Control Memory Select Auxiliary ROM Select Instruction Inhibit Instruction Wait Ground These signals are assigned on the backplane but are not used on this assembly 2 Signal used only on Engine 2 9 9 s4ueuubrssvy 4 1032euuoj5 Ca ppe Skip SKIPP L Emulate Address 0 AR Write Enable 2 ARWEN L EMAOl H Emulate Address i Stack Limit Write Enable 2 SLWEN L EMAO2 H Emulate Address 02 Slave Synchronization Error SSYER H EMAO3 H Emulate Address 03 Double Slave Synchronization DSYER H EMAO4 H Emulate Address 04 Error Load Special Function LDSPF H EMAO5 H Emulate Address 05 Fatal Interrupt FINTP L EMAO6 H Emulate Address 06 Special Function SPFNC H EMAO7 H Emulate Address 07 Panel Halt HALTP L Reserved Reserved PSSEL L Program Status Select Carry 1 CARRY H Reserved Reserved Reserved Address Error ADERR H Reserved Program Status 03 PSO03 L Reserved Reserved 2 XD007 L Inhibit Destination File O to 7 Reserved 2 XD815 L Inhibit Destination File 8 to 15 Reserved 2 XB815 L Inhibit B Field File 8 to 15 Control Count Write Enable CCWEN H 2 XB007 L Inhibit B Field File O to 7 Static Conditi
36. Mnemonic Operation Description 5 3 12 OR A B Mnemonic Operation Description 5 3 13 OR A B Mnemonic Operation Description 5 3 14 Not AND Mnemonic Operation Description C21518008 x0 ORI 0 R 3 DN The logical OR of the A and B operands is transferred to the destination ORB 0 AUB DN The logical complement of the B operand is ORed with the A operand and the result is transferred to the destination 50 AUB DN The logical complement of the operand is ORed with the B operand and the result is transferred to the destination NAND 500 Xn B gt DN The logical NAND of the A and B operands is transferred to the destination 5 3 15 5 3 16 Exclusive OR Mnemonic XOR 0 Operation R A D B DN Description The logical exclusive OR of the A and B operands is transferred to the destination The exclusive OR by definition is A B A 1 B u Coincidence Mnemonic SOF Operation R A B R DY Description The complement of the logical exclusive OR of the A and B operands is transferred to the destination This is the coincidence function aNs ANB 5 4 ARITHMETIC MICROCOMMANDS The arithmetic microcommands are listed ir Table 5 1 Tksre are eight microcommands in this class The CPU performs both binary addition and subtraction
37. ODUCTION rage yop a cac ui de De we Se ee Ml 1 2 DOCUMENTATION s t dcm 92 7 amp 4 A Mew CE Cae UM DAR de 1 2 1 PoObliCGAblONS 2 e w qas uw Ao TA we dp wr 1 2 2 Engineering 1 5 l l 1 2 3 Abbreviations and Conventions 1 3 SECTION 2 DESCRIPTION 2 1 OVERVIEW ec o VAS KS WS PAD SYSTEM ORGANIZATION e e gt o o gt o o o o 2 2 1 Engine s a die aes OEC Ee Ye dao Vap 2 2 2 Microbus EE 2 2 3 5 Channel ake RD cas 2 2 4 4 amp 7 4 2 2 5 Mcrocognsole e ss ww i 2 2 6 2 2 7 Magnetic Core Peripheral DEVICES e 42 coe 0909 DA Jl de 8818 2 3 FIRMWARE DEVELOPMENT 5 2 3 1 Alterable Control 223 2 Support Software La I ocu GR UR dc d e den ES 2 4 FEATURES v2 65 4
38. RO swap halves shift left logical shift right logical shift right arithmetic Single precision double precision open shift closed shift XxX HOKX KX PORK MRK MM 21518008 5 5 1 1 Single Precision Shifts Single precision shifts involve only AU shift elements operating on the A operand Swap Halves Word or Byte Operation a Word mode R15 R08 A07 A00 R07 15 08 R DN 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 b Byte mode R15 RO8 A15 A08 RO7 RO4 A03 A00 RO3 ROO A07 A04 gt DN 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 CALL Ld C21518008 x0 5 21 Description Micro condition Codes For word swaps the more significant and less significant bytes of the A operand are swapped and the result is transferred to the destination For byte swaps the more significant and less significant halves of the less significant byte of the A operand are swapped and the result is transferred to the less significant byte of the destination byte of the A operand is transferred unchanged to the more significant byte of the destination Word mode c y 2 15 15 14 if 0 otherwise if RL5 1 otherwise if gt 0 otherwise if ROO 1 otherwise The more significant Byt
39. ROBUS Connectors C to F and Jl and J2 inter face with the main computer Microbus Connectors A to F are standard backplane connectors Connectors Jl and J2 plug into the two small processor interconnection boards There are no controls or adjustable elements on the Engine Because or the universal connections in the CPU area the chassis the Engine boards can operate in any slot from 1 to 5 21518008 15 69 COMPONENT SIDE 2 Solder Side to B30 Likewise with connector J2 AQ Solder Side AV2 to 2 Likewise with connectors B to NOTES C Figure 3 2 Cal Data 100 Engine Board Configuration Es 800077 5 07 ez1518008 xo 4 ENGINE 4 1 FUNCTIONAL DESCRIPTION Figure 4 1 is a block diagram of the Cal Data 100 Engine showing three main functional sections control data and MCA The control section contains the control memory emulation enhancement circuitry if needed and timing circuits that control the sequence of operations performed Emulation enhancement circuitry is provided only when a computer configuration requires the speed or special capabilities of the added circuitry The data section contains the arithmetic logic gating and busing elements that perform data transfers and manipula tions The basic control and data sections together are referred to as the Engine or CPU The main communication path in the computer is the Micr
40. S em C21518008 X0 4 2 CONTROL SECTION A block diagram of the control section is shown in Figure 4 3 Control is organized around the control memory CM which stores the micro programs to be executed Microcommands are 48 bits in length Normal CM capacity is from 256 to 4 096 words 48 bits each A 12 bit location counter CC addresses CM and advances on each clock step unless altered by a sequence change Microcommands read from CM are held in a microcommand register CR during execution The micro commands read from CM can be modified prior to input to CR for execu tion Microcommands can also be entered manually into CR and executed from the Microconsole not shown A l6 level control stack CS is provided to permit the contents of CC to be saved and restored under microprogram control This permits automatic nesting of microroutines and microprogram interrupts giving increased speed and CM space efficiency The system contains a unique facility that permits designated areas to be patched from aux iliary CM or from the Microconsole This is a highly useful feature since nonalterable storage elements are generally used to implement CM An eight bit loop counter LC is provided to permit single microcom mands or entire sequences to be repeated a specified number of times This feature enhances execution speed of iterative loops A special feature of the Cal Data 100 Engine is emulation enhancement
41. SYSTEM HARDWARE POWER SUPPLY MEMORY OR I O BOARD 1 1 1 1 14 13 MEMORY 1 0 BOARD 12 MEMORY 1 0 BOARD 1 0 BOARD OR OPTION 11 MEMORY OR 1 0 BOARD 10 SY Computer System Ww Om o Engine Microprogramming NOTES Technical Manual A Standard 18 Slot Backplane is Shown Theory of Operation T ae DP Ehgineering Drawing Package MACROBUS Terminator or Extension Cable IM Installation Manual a dps UM User Manual Figure 1 1 Relationship of Publications to Cal Data l System Elements 7 C21518008 x0 1 2 3 Abbreviations and Conventions Table 1 1 lists the abbreviations found in this manual Conventions used in the text of this manual include 21518008 Equipment panel nomenclature is reproduced in all upper case characters The proper names of instructions microcommands and signals are capitalized ZERO and ONE are used to express binary logic O and 1 states respectively Hexadecimal numbers are preceded by a dollar sign for easy identification A colon is used to indicate a range of bits For example the range of address bits A12 to A03 is written A12 A03 Table 1 1 Abbreviations 1 California Data Processors CPU central processing unit engine MCA MACROBUS Channel Adapter I O input output LFC Line Frequen
42. The Shift microcommand provides complete flexibility for single length shifts involving only the A operand and AU and double length shifts involving AU and XR Shifts can be left or right logical or arithmetic open or closed While the basic microcommand shifts only a single bit multibit shifts can be performed by repeating the micro command using LC Mnemonic Microcommand Type Description Table 5 4 SHF 18 Special branch or special skip The SO field specifies the type and direction of shift as shown in Table 5 4 For a single precision 16 bit shift the A operand is shifted one place left or right and the result is transferred to the destination For a double precision 32 bit shift the A operand and the contents of XR are shifted one place left or right with a linked carry between the two words The shifted AU result is transferred to the destination and the shifted XR result remains in XR The shift operation is performed in the word mode unless a byte operation is specified by the FN field Using the special skip type format for the shift can lead to possible conflict between a double length shift specification in the SO field and an XR shift specifica tion in the FN field If such a conflicting specifica tion is made the SO field control is effective and the FN field control is ignored SO Field Shift Specification SO Field Bits 13 12 Shift Operation 15 14 XM RX HO
43. are known to be operating properly and return the malfunctioning board for repair to California Data Processors or an authorized representative C21518008 X0O APPENDIX ENGINE ARITHMETIC 1 NUMBER REPRESENTATION In the Cal Data Engine the AU is implemented to perform both addition and subtraction internally as opposed to complement addition for the subtraction function Hence the dynamic arithmetic condition codes generated carry out and overflow and the function of the carry in CIN to the AU depend on whether addition or subtraction is per formed Arithmetic operations assume the use of the two s complement representation for negative numbers in the computer with the state of the most significant bit representing the sign of the number The l6 bit single precision number range of the computer is therefore Binary Hex Decimal 0111111111111111 7FFF 219 1 32 767 0000000000000001 0001 l 0000000000000000 0000 0 1111111111111111 FFFF 15 1000000000000000 8000 2 32 768 form the two s complement of a binary number perform Ix l x 1 where X is the logical or one s complement of the binary number For example 5 0101 X 1010 one s complement 1 0001 X 1011 two s complement _ 2 ADDITION If all negative numbers are represented in two s complement form then the result of any addition generates the proper result regardless of the sign of the two operands
44. asic knowledge of design principles and circuits used in small computers is assumed hence no tutorial material of this kind is included As a stand alone publication this manual has a good functional and physical description of the Cal Data 100 Engine providing the information needed to understand the capabilities and features of the computer and to plan a system using it The maintenance coverage of this manual is commensurate with the prerequisite skills and B knowledge of the defined user characteristics of the product and maintainability requirements established by Cal Data 1 2 DOCUMENTATION This manual describes the engine of a Cal Data computer system that is equipped with a MACROBUS Channel Adapter part number C81080300 and an Emulate Board part number C81080210 The following paragraphs define publications and conventions that support this manual lc2l Publications Figure 1 1 illustrates the relationship between Cal Data system elements and technical publications Controlled copies of publications provided in accordance with the terms of the purchase contract are kept current for the life of the product 1 2 2 Engineering Drawings For maintenance purposes this manual is supported by a drawing package that contains schematic diagrams assembly drawings and other required engineering drawings The drawing package is updated with the latest revision of each drawing C21518008 x0 P GE 1 1 PUBLICATIONS
45. bit Bit 15 is the shift carry out and is also shifted into bit 00 The result is transferred to the destination Byte shifts are the same as word shifts except that the shift is on the less significant byte only The carry bit is shifted out of bit 07 The more significant byte is unmodified The resulting word is transferred to the destination Word mode b Byte mode condition Codess 15 07 15 14 A07 A06 z 1 if 0 z 1 if RI 0 otherwise otherwise n 1 if R15 1 n 1 if 07 1 otherwise otherwise 1 if RO p l if RL 0 O otherwise O otherwise 1 if ROO 1 d 1 if ROO 1 O otherwise O otherwise C21518008 x0 Logical Open Right Shift Word or Byte Operation Description Micro condition Codes C21518008 x0 b a Word mode 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 OO CIN 15 14 13 12 11 10 O9 08 the right field is shifted into bit 15 Byte mode CIN For word shifts the A op rand is shifted one bit to 07 06 05 04 03 02 01 OO The value of CIN designated by the MC The bit shifted out The result is of bit OO is the shift carry out transferred to the destination a Word mode A00 v 15 CIN z 1 0 1 0 1 1 if R 0 otherwise if R15 1 otherwise if otherwise if ROO 1 otherwise b value of CIN is shifted into bit 07 Byte shifts are the same as wor
46. ble These cables are routed over the top of the boards and exit via a cutout at the top rear of the chassis A strain relief clamp is provided All standard 1 I O and memory boards have provision for this cable routing scheme The backplane contains up to 18 connector rows board slots The Macropanel is mounted on a printed circuit board that plugs into the first connector row of the backplane The Macropanel is covered by an overlay held in place by the bezel The bezel and overlay are de mE removable from the front when the chassis is installed in a rack C21518008 X0 E cta 3 1 SA ERRORS 1 i y 1 Cal Data 1 Computer with Boards Installed Fan Panel T Co o r4 un a E Shown Down is 3 1 VE Figure 3 2 3 2 ENGINE BOARDS The Engine comprises two boards labeled Engine 1 part number C81080180 and Engine 2 part number C81080190 Each Engine board Figure 3 2 15 a hex width board 15 7 by 8 9 inches 33 9 by 22 7 cm Engine 1 normally plugs into slot 4 of the Cal Data computer chassis Engine 2 normally plugs into slot 3 The right hand edge of each board has a 1 0 by 5 5 inch 2 5 by 14 0 cm cutout as clearance for the side mounted cooling fans in the chassis There are six printed circuit connectors A to F on the bottom edge of each board and two Jl and J2 on the top edge Connectors A and B interface with the MAC
47. computer hardware but is usually not required in an applied system configuration Magnetic Core Memory Cal Data core memory comprises modular blocks of 8K 8 192 or 16K l6 bit words each contained on a single circuit board Each module plugs directly into the MACROBUS and is treated as an I O device in the system The maximum normal system capacity is 128K words Two identi cal modules can be interleaved to achieve an increased effective through put rate on the MACROBUS The MACROBUS can accommodate memory devices other than magnetic core such as semiconductor ROM or RAM modules The only requirement is that such units obey MACROBUS use rules Modules of varying size and speed can be freely mixed with core memory DMA type MACROBUS devices may communicate with memory Peripheral Devices peripheral controllers and system interfaces are attached to the MACROBUS as shown in Figure 2 2 The user can readily interface devices with the MACROB S using simple design rules Cal Data offers I O channels such as the MACROBUS with different structures as well as several Standard subsystems to enhance user applications The Subsystems offered to support normal programming and system development operations E v C21518008 X0 2 3 2 3 1 2 34 2 4 a Paper Tape Reader High speed photoelectric reader 300 characters per second fanfold tape b Paper Tape Punch High speed punch
48. cro commands are n T PL a Instead of a branch condition a condition is specified under which execution of the microcommand at the next CM location can be inhibited skipped The CM address sequence itself is not altered b The B operand source and branch address are replaced by a 16 bit literal value This value is used directly as the B operand for those logical and arithmetic that in volve a B operand input to AU Because of the space reserved for literal value heier or not one is required the auxiliary control functions defined for the branch type microcommand cannot be specified All other operations of a skip type microcommand are identical to the corresponding branch type microcommand C21518008 x0 TS 5 3 5 2 2 Special Class The special class of microcommands provides functions that affect spe cialized control and other operations required of the computer Some of these microcommands involve the use of AU The operation performed is specified by the OP field total of seven special operations are im plemented Branch Type The special branch type microcommand permits the programmer to specify a conditional or unconditional branch just as for the logical or arith metic branch type And in the same way either a branch address or a set of auxiliary control functions can be specified depending on whether or not a branch condition is specified by the microcommand Skip Type The special skip t
49. cy Clock RAM random access memory ROM read only memory programmable read only memory medium scale integration large scale integration Memory Management Unit light emitting diode Alterable Control Memory direct memory access control memory microcommand location counter microcommand register control stack stack counter loop counter M bus data destination bus file register A operand bus B operand bus arithmetic logic unit AU shift elements processor macro status register stack limit register data read register instruction register shift register emulate decode register emulate instruction address carry out microcondition code overflow microcondition code zero data value microcondition code negative data value microcendition code positive data value microcondition code odd data value microcondition code Meaning microstatus register MS register link bit MS register overflow bit MS register zero data value bit MS register negative data value bit MS register positive data value bit MS register odd data value bit characters per second cards per minute lines per minute 1 024 address or memory locations maximum minimum ampere alternating current direct current root mean square _ volt nanosecond hertz degrees celsius centimeter part of the main Microbus C215180008 x0 SECTION 2 DESCRIPTION 2 1 OVERVIEW The Cal
50. d shifts except that the shift is on the less significant byte only The The more significant byte is unmodified The resulting word is transferred to the destination Byte mode A07 CIN c y 2 if 0 otherwise if R07 1 otherwise if RL gt O otherwise if ROO 1 otherwise Logical Closed Right Shift Word or Byte Operation a Word mode 15 14 13 12 11 10 09 08 07 O6 05 04 03 02 01 OO b Byte mode 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 OO OM Description For word shifts the A operand is shifted right one bit Bit 00 is the shift carry out and is also shifted into bit 15 The result is transferred to the destination Byte shifts are the same as word shifts except that the shift is on the less significant byte only The carry bit is shifted into bit 07 The more significant byte is unmodified The resulting word is transferred to the destination dpa a Word mode b Byte mode condition Codes c AOO A00 15 A07 A00 2 1 if z 1 if RL 0 O otherwise O otherwise 1 if R15 1 1 if RO7 1 O otherwise otherwise 1 if 1 if gt 0 otherwise otherwise 1 if RO0 1 1 if ROO 1 0 otherwise otherwise 21518008 0 Arithmetic Open Right Shift Word or Byte Operation a Word mode 15 14 13 12 11 10 O9 O8 O7
51. d the contents of the emulate decode register ER The AO and BO fields of DCD are used as follows a Bits 28 and 27 of the AO field select one of four groups of four bits each in ER The ER bit group selected is taken as the least significant four bits of an eight bit address to the decode table b Bits 26 to 24 of the AO field select one of eight possible field modification patterns for the next microcommand read from CM The BO field is taken as the most significant four bits of the eight bit address to the decode table The 16 bit modifier word fetched from the decode table is ANDed with the least significant 16 bits in the next microcommand read from CM before it is transferred to CR for execution gt 21518008 0 Micro condition Codes 21518008 0 During the execution of DCD AU is set to copy AB onto MB leading to unpredictable generally meaningless microcondition codes 6 1 GENERAL SECTION 6 MAINTENANCE This section describes preventive and corrective maintenance procedures that apply to the Engine In general corrective maintenance is limited to isolation of a fault to a specific Engine board followed by replace ment of the board Troubleshooting may then be used to verify that the suspected board is malfunctioning and to help diagnose the specific problem Repair should be conducted at the factory or by an authorized Cal Data representative 6 2 PREVENTIVE MAINTENANCE
52. e Mode 2 A07 A07 A06 if RL 0 otherwise if RO7V 1 otherwise if RL 0 otherwise if ROO 1 otherwise C21518008 X0 Logical Open Left Shift Word or Byte Operation a Word mode 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 OO b Byte mode 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 AL CIN c Description For word shifts the A operand is shifted left one bit The value of CIN designated by the MC field is shifted into bit OO The bit shifted out of bit 15 is the shift carry out The result is transferred to the destination Byte shifts are the same as word shifts except that the shift is on the less significant byte only The carry bit is shifted out of bit 07 The more significant byte is unmodified The resulting word is transferred to the destination cm a Word Mode b Byte mode condition Codes 15 7 A15 A14 A07 A06 2 1 if R 0 2 1 if RL 0 otherwise otherwise n lif Rl5 1 1 if RO7 1 O otherwise O otherwise 1 if 1 if RL gt 0 otherwise otherwise 1 if 00 1 d 1 if ROO 1 otherwise otherwise C21518008 X0 n 5 23 Logical Closed Left Shift Word or Byte Operation a Word mode 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 b Byte mode 15 14 13 12 11 10 09 08 07 O6 05 O4 03 02 O1 OO For word shifts the A operand is shifted left one Description
53. e microcondition codes for all logical class microcommands are given in Table 5 2 All logical microcommands are standard except Emulate EML which is optional The main purpose of EML is for very rapid emulation decoding of instruction operation codes and control fields The procedure is to store the instruction in IR EML then initiates translation of the contents of IR into a CM branch address generated from a table of values The address directs the microprogram to the proper microroutine in CM for the emulation of each instruction The emulate table is specifi cally programmed for each computer to be emulated The decoding opera tion performed by EML can be accomplished by other methods using only standard microcommands but at the cost of time and CM space For this reason the need to implement EML depends on the specific application Table 5 2 Microcondition Codes for Logical Microcommands Word Mode Byte Mode field of the microcommand field of the microcommand l if R 0 O otherwise l if RL 0 O otherwise i 1 if R15 1 otherwise 1 if RO7 1 O otherwise 1 if R50 0 otherwise 1 if RL 0 O otherwise 1 if ROO 1 O otherwise l if R00 1 otherwise Microcondition Code C21518008 XO 5 3 1 5 3 2 Emulate Optional Mnemonic Operation Description EML 00 R A DN emulation unless higher priority CC modification occurs The A operand is transf
54. ed by a microcommand are executed simultaneously within a single clock step with the following exceptions a When the microprogram execution sequence is altered one addi tional clock step is required to execute the branch operation b A MACROBUS access delay inhibits microcommand execution until a synchronizing I O response is received A CPU clock period is 165 nanoseconds and all microcommands are executed within an integer multiple of that period The CPU incorporates a 48 bit microcommand word to perform all operations in the machine The microcommand structure permits simultaneous exe cution of many parallel functions specified in each microcommand to achieve exceptionally fast emulation of general purpose computer opera tions The structure of the microcommands provides considerable flexibility in organizing a particular microprogram to maintain high effective execu tion rates with economical use of control memory space 5 2 MICROCOMMAND CLASSES The three classes of microcommands are a Logical b Arithmetic c Special Every microcommand regardless of class has the ability to specify a conditional or unconditional branch or skip operation Since the format of the microcommands differs depending on whether a branch or skip is specified the microcommands in each class can be considered to be one of two types Branch type b Skip type Figure 5 1 shows the formats for the classes and types of microcommands exec
55. erred to the destination The contents of IR are translated into a branch address emulate instruction address to CC using an emulate table on the Emulate Board a higher priority CC modification occurs concurrent with the microcommand the EIA is ignored All microcommand fields are effective as defined except that the BO field is ignored since no B operand is used Sign Extend A Mnemonic Operation Description Example f ADD SXA 501 Word mode Byte mode R A RM N U A15 A08 R DN RL A07 A00 RM RL gt DN In the word mode the A operand is transferred to the destination In the byte mode the state of the negative microstatus bit N is extended to the more significant byte of the A operand The contents of the less significant byte of the A operand are unmodified The result is trans ferred to the destination Perform a byte mode add on A and B and store the result in the A operand location then extend the sign of the byte result A 00000000 10110100 76 00000000 11101100 20 R 00000001 10100000 96 The microcondition codes generated are 1 1 0 2 0 1 p 0 da 0 00000001 10100000 00 R 11111111 10100000 TY YY RM RL d 5 21518008 5 3 3 Mnemonic Operation Description 5 3 4 Move B Mnemonic Operation Description 5 3 5 Complement A Mnemonic Operation Description Example
56. evel and is useful for firmware development hardware maintenance and troubleshooting The Macropanel is treated as an I O device Special interpretive firmware services the functions of the Macropanel ds Maximum memory capacity of the basic system is 32K words A Cal Data Memory Management Unit is required for expansion beyond this capacity C21518008 x0 QB 421 40 SELECTOR CONTROL DEDE 7 ee NOTE AB A OPERAND BUS SOURCES UL 4 2 2 C21518008 x0 140 ub M e e SY SS E E Figure de 1 c21518008 X0 M WES u LE ENG 222222 SELECT GATES EMULATE TABLES CONTROL SECTION EMULATION ENHANCEMENT MACROBUS CHANNEL ADAPTER NOT PART OF ENGINE CONTROL E MACROBUS PRIORITY 061 5 Continued 4 42 N a pee e p Oo 42 UO c gt 6 C to all functional areas of the Engine Interface with the Microbus E 2 dA witT a Uu S cA 3C e 2 Tec gt n oe Tun Figure wu ctu REU
57. ficant byte across the entire word e g where word and byte arithmetic operations are mixed A microcommand is provided that will insert the state of the microstatus L bit into the most significant eight bits of a word Thus if the state of the c bit from the previous example is saved as L the sign extended result is 1111111101000001 This can be generated by execution of the Sign Extend microcommand The CPU has an extensive complement of Shift microcommands that includes arithmetic as well as logical open and closed forms both single and double precision double length shifts involve XR For byte shift operations shifting is performed on only the less signi ficant byte The more significant byte remains unchanged The carry input and microcondition codes are associated with the less significant byte Examples are C21518008 X0 C21518008 XO0 Byte mode open left shift 00000011 10101101 L R 00000011 0101101L c 1 1 1 2 0 1 1 Note that L is the shift carry input and that the carry out is the most significant bit of the less significant byte Byte mode open right shift 00000011 L 10101111 00000011 11010111 1 Jj 1 1 1 2 0 1 p L 1 SECTION 5 MICROCOMMANDS 5 1 GENERAL Microcommands generate the control signals that enable all internal operations of the Engine There are no suboperations performed 11 functions specifi
58. full word operations The CPU is also designed to operate on bytes half words if so specified by a microcommand The byte mode can be designated as unconditional or conditional In the conditional case a byte mode operation is performed only if the emulation circuitry indi cates that the instruction being emulated is a byte mode instruction The Engine has the capability of transferring either words or bytes on the MACROBUS For arithmetic and logical byte operations involving AU the specified operation is performed on the full 16 bit A and B operands Since microcondition codes are generated on only the less significant byte bits 07 to 00 of the result the bytes to be manipulated must be right justified Carry bits propagated out of the less significant byte can affect the results in the more significant byte A byte operation with a file register FR as a destination does not modify the most significant byte of the specified FR register destination however reflects the full l6 bit result For example consider addition of the following two right justified bytes 00000000 10110110 74 00000000 11101011 21 00000001 10100001 95 Microcondition codes are generated from the less significant byte as follows pcs 1 0 d 1 The result for byte mode operations is interpreted for the less signifi cant byte only In many cases it is desirable to extend the sign of the less signi
59. ignments e e gt Connector J2 Pin Assignments e s e e e gt ILLUSTRATIONS Title Relationship of Publications to Cal Data 1 System Elements Cal Data 1 Computer System with Memory Management Unit Words of Cal Data 16 16 850 ns Core Memory and Serial Controller 1 D Ies Cal Data 1 Computer System Organization gt Cal Data 1 Computer with Boards Installed Fan Panel is Cal Data 100 Engine Board Configuration Cal Data 100 Engine Block Diagram e e e ecs o Cal Data 100 Engine Interface with the Microbus Cal Data 100 Engine Control Section Block Diagram Cal Data 100 Engine Data Section Block Diagram ie Microcommand Formats gt gt e gt 128K I O Shown ge eh t o w I E i dog 1 to E IP t0 S SD Qi BR iR 9 NO gt iii 1 INTRODUCTION 1 1 5 This manual provides the information needed to understand and maintain the Cal Data 100 Engine part numbers C81080180 and C81080190 when used with the drawing package provided The information in this manual is for the use of a skilled technician familiar with standard test equipment solid state logic theory common maintenance practices and standard troubleshooting techniques A b
60. ion U a15 N B15 07 07 A07 N B07 R07 1 A07 507 _ U A07 B07 R07 Subtraction 15 15 u a15 B15 2070 5e7 U a07 N U B15N R15 U B07 R07 U a15 B15 815 Addition or lif 807 1 Subtraction otherwise O otherwise if R gt 0 l if RL gt 0 0 Addition or Subtraction otherwise otherwise 1 if ROO 1 o Addition or if 1 otherwise Subtraction 0 otherwise 5 4 1 Mnemonic Operation Description Micro condition Codes Example 5 4 2 Subtract A B Mnemonic Operation Description Micro condition Codes Example ADD 10 R A B CIN 3 DN The A and B operands and the value of CIN designated by the MC field are added arithmetically and the result is transferred to the destination Addition Table 5 3 Add A and B and increment the result A 27 435 0110101100101011 1 747 1111100100101101 CIN 1 0000000000000001 25 689 1 0110010001011001 The microcondition codes generated are 1 v 0 2 0 0 1 1 SUB 11 R A B CIN R DN The operand and the value of CIN designated by the MC field are subtracted from the A operand and the result is transferred to the destination Subtraction Table 5 3 Subtract B from A and decrement the resu
61. itional skip or branch capability Tests on either current dynamic conditions or on previous static conditions Bipolar ROM or PROM 4 096 E max ET Bipolar RAM 512 dnt wi auxiliary power 1 rds max with auxiliary power us sedes uu D 2 8 Table 2 1 Continued Characteristic Specification Control memory stack 16 level hardware pushdown stack Emulation enhancement Special emulation decode tables provide automatic addresses to control memory microroutines for high speed program execution Loop counter Eight bit counter for single or multi instruction repeats Interrupts Multilevel priority interrupt structure provides automatic addresses to control memory microroutines for internal and external conditions PROCESSING Word length l6 bits Arithmetic logic Both word and byte operations are pro vided fixed point one s or two s complement arithmetic arithmetic condition codes carry link over flow negative zero positive odd arithmetic and logical shifts multibit using loop counter for repeats are provided Registers Eight or sixteen l6 bit multipurpose files FR Shift register XR Microstatus register MS Instruction register IR Decode Register ER Processor macrolevel status register PS INPUT OUTPUT TYPICAL Type Asynchronous bidirectional I O channel derived from the Microbus requires 1 0 channel adapter handles communication
62. itry interrupt vector CC normally advances sequentially to the next location through all 4K locations in CM including the wrap around transition from 4 095 to 0 unless the normal sequence is altered PH Auxiliary power is required above 512 words c21518008 40 005 4 7 4 2 3 modifiers from CR and the emulation enhancement circuitry are 11 bits long permitting branches to occur from these sources within only a 2K word area The most significant bit of CC is unaltered for such branches To branch to a location outside a 2K word area the program mer must execute a microcommand that transfers a full 12 bit branch ad dress via MB Interrupt vectors are to only the first 256 CM locations i e the four most significant CC bits are forced to ZERO Certain conditions cause an automatic reset of CC to location O a cor responding microstatus bit is set for each condition a catastrophic system error b power up sequence The contents of CC can be read by microcommand via For systems that do not contain an implemented CS this provides a means of saving a return location in CM Microcommand Register CR The 48 bit CR stores the current microcommand read from CM for execution The microcommand from CM can be modified prior to entry into CR by a function specified by the special decode circuitry on the Emulate Board CR can also be loaded from the Microconsole to per
63. line checkout of new firm ware prior to conversion to ROM or PROM devices The normal maximum capacity of CM is 4K words when ROM or PROM devices are used Although each microcommand is 48 bits in length the CM ad dressing structure of the microcommand limits direct access to 2K words however a paging scheme between 2K word blocks permits convenient ac cess anywhere within 4K words Auxiliary Control Memory It is often desirable to alter the contents of CM either temporarily or permanently When nonalterable devices are used the usual requirement is replacement of the existing devices The Cal Data 100 Engine incorporates circuitry that permits either one or two 32 word blocks of auxiliary memory in the Microconsole to func tionally replace designated 32 word blocks in CM This enables patching for corrections additions or deletions from existing firm ware temporary overlay for diagnostic and troubleshooting operations etc 4 2 2 Location Counter CC The location counter is a 12 bit binary counter register that points to the location in CM of the next microcommand to be executed The micro program sequence can be altered conditionally or unconditionally as specified by the programmer and the state of the system sequence change is made by loading CC from one of the following sources a CR for programmed branches b M bus for computed branches c The current CS register d A vector from the emulation enhancement circu
64. lt A 444 1111111001000100 B 1 747 1111100100101101 CIN 1 0000000000000001 O 0000010100010110 R 1 302 c This operation produces a one s complement result when the result is negative since CIN is specified as a ONE The microcondition codes generated are 0 0 2 0 0 1 0 E C21518008 x0 524 3 Add Carry Mnemonic ADC 12 Operation DN Description The value of CIN designated by the MC field is added to the A operand and the result is transferred to the destination Micro Addition Table 5 3 condition Codes 5 4 4 Subtract Carry Mnemonic SBC 13 Operation R A CIN R DN Destination The value of CIN designated by the MC field is subtracted from the A operand and the result is transferred to the destination Micro Subtraction Table 5 3 condition Codes 21518008 0 5 4 5 Increase Mnemonic Operation Description Micro condition Codes Examples INC 14 R A 1 CIN R gt DN The value one and the value of CIN designated by the MC field are added to the A operand and the result is transferred to the destination If CIN is ONE the A operand is increased by two otherwise it is increased by one Addition Table 5 3 Increase the A operand by two if MC designates CIN as ONE increase by one otherwise 7817 0001111010001001 1 1 00000000000
65. mit direct operator control of internal functions The least significant 11 bits of CR modify CC when a branch operation is specified by the microcommand in CR e Microcommand Sequencing ana Timing The basic clock cycle is 165 ns adjustable and ordinarily a microcommand is read from CM and exe cuted on each cycle There is a one clock delay between the time CC addresses a word in CM and the time that the microcommand is transferred to CR for execution For this reason when the normal CC counting se quence is modified two clock cycles are required to access the micro command at the branch location and transfer it to CR Furthermore the microcommand accessed at the time CC is modified is transferred to CR even though a branch is being made Whether or not this extra micro command is executed can be specified by the programmer The following Sequence illustrates the operation Time cc CR Operation T 1 X x 1 T lt X 1 X Branch to Y specified THI Y X 1 Microcommand at 1 can be executed 7 2 Y 1 Microcommand at branch location In addition to sequence modification the programmer can specify that the succeeding microcommand be skipped In this case the succeeding microc mmand is transferred to CR but execution is inhibited This action is not considered to be a Sequence change since CC concinnus normal sequential counting The output of CR is decoded to generate the timing and signal
66. n be programmed to gener ate a set of PS update control bits that are specific to the instruction contained in IR When the MMS microcommand is executed the PS update control bits steer the contents of MB directly to the proper PS location In this way the microprogram generates proper values for each emulated instruction using only one clock step Since each emulated computer requires a different treatment of PS values the emulate table associated with MMS is unique In some cases MMS is not needed at all to meet overall emulation speed objectives For this reason MMS is considered an optional microcommand that can be omitted or tailored for a specific emulation task Mnemonic MMS S1C Microcommand Special branch or special skip Type Description The operand is transferred to the destination Any or all of the least significant four bits of the A operand can also be transferred to the corresponding least signi ficant four bits of PS if specified by the microcommand The contents of IR are translated into a set of update functions that specify a modification of the least signi ficant four bits of PS The update functions are con tained in the emulate table The update functions that can be specified individually for PS bits 03 00 are PS Update PS Bit No change PSO3 PSO3 502 3 502 PSO1 PSO1 500 500 Reset 0 503 0 502 501 0 500 1 503 1 502 1 501 1
67. nal computer destinations Each microcommand specifies a destination address to one MB location In addition by setting one bit of the microcommand the AU result can be transferred to the AB source Microcondition Codes For each operation performed by the AU or shift gates a set of condition codes is dynamically generated describing the result These are Carry d t c The carry out is generated as the arithmetic carry for add operation the borrow for a subtract operation or shift carry out for a shift operation b Overflow v Overflow is generated for add subtract or shift operations The conditions under which overflow occurs depends on the operation 9 21518008 0 c Zero 2 The zero condition exists when all bits of the result are ZERO d Negative n The negative condition exists when the most significant bit of the result shifted if applicable is ONE e Positive p The positive condition exists when the result is greater than zero not zero and not negative f Odd d The odd condition exists when the least significant bit of the result is ONE The last four conditions are referred to as data value codes and are generated from the value of the AU result on MB A microcommand can specify dynamic conditional testing of the micro condition codes generated as the result of an operation and the condi tional test can cause a skip of the next microcomma
68. nches 22 7 by 39 9 cm six connector positions 216 pins on long edge POWER AC input 115 208 230 Vac 50 or 60 Hz A S s DI aera outputs Regulated 5 Vdc 36 e 15 Vdc 12 4 C2 1518008 x0 B Ta 2 10 gt Table 2 1 Continued Characteristic Specification Power monitor ENVIRONMENT Temperature Humidity CIRCUITS Integrated circuits Discrete devices Internal logic levels I O logic levels MICROPROGRAMMING SUPPORT HARDWARE Microconsole Alterable control memory ACM MICROPROGRAMMING SUPPORT SOFTWARE FIRMWARE Symbolic micro assembler ACM software operating system Unregulated 22 Vdc 1 5 A 8 Vrms 1 5 A Power failure restart signals to CPU for automatic shutdown and restart operations 09 4509 ambient temperature 10 to 905 relative without condensa tion Bipolar TTL extensive MSI and LSI usage Metal can transistors hermetically sealed components only ZERO Vdc ONE 5 Vdc nominal ZERO 43 4 Vdc nominal ONE 0 Vdc Provides direct control over Engine microcommand entry and display single step and trap mode micro command execution Modular 256 word increments of control memory that can be loaded and read operates CPU at full execution speed Symbolic assembler for microprogram coding and documentation Operating system used in conjunction with ACM C21518008 X0 3 PHYSICAL
69. nd BB part of the Microbus All microcommands executed by the CPU involve the use of information on one or both of these buses x AB sources can be selected from any one of the FRs or from one of 11 other operational registers in the computer There are five unused AB source addresses of which two are reserved for user defined functions The BB source can be a Any one of the FRs b The least significant 16 bits of the current microcommand contained in CR i literal one value The second BB source listed above represents a 16 bit literal value con tained in the microcommand 4 3 3 Arithmetic Logic Unit AU 21518008 0 AU is l6 bit parallel element that performs arithmetic Appendix A and logical functions on two variables input via AB with the link L status bit from the microstatus register MS used conditionally as a carry input for addition and subtraction operations A carry output c resulting from AU operations can be tested as conditional skip or branch condition and can also be stored in MS in the L bit as a static status condition dR 4 11 _ 4 3 4 4 3 6 Each microcommand specifies either implicitly or explicitly the AU operation to be performed and the use of the L input total of 15 logical and eight arithmetic functions are implemented AU Shift Elements SX and Shift Register XR SX is a set of gates that can be used in conjunction with shift register XR
70. nd or a branch to a new microprogram location This capability saves considerable time over machine designs that require conditional testing to be performed on the condition generated by a previous operation 4 3 7 Microstatus Register MS The six dynamic condition codes can be saved as static microstatus bits in MS Each microcommand can specify separate storing of the carry overflow and the four data value codes in MS These static microstatus conditions instead of the dynamic microcondition codes can then be tested by microcommands for conditional skips or branches MS is 16 bits in length In addition to the six microcondition codes other status bits are stored in this register The contents of MS can be read via AB and can be loaded as a destination via MB The complete set of status bits contained in MS is defined in Table 4 1 Table 4 1 Microstatus Register Bit Definitions Stored state of dynamic carry out c of AU or shift gates Overflow Stored state of dynamic arith metic or shift overflow v Stored of zero z data value code Negative Stored state of negative n data value code Positive Stored stats of M data value code Stor d ste of odd 3 data value code 15 to 06 aun depending on TROU ONES emulation 21518008 0 4 3 8 Word and Byte Operations The AU and shift elements of the CPU handle 16 bits and therefore exe cute
71. o Se e WWWWW WW Qo M OY Ur M C21518008 x0 SECTION 5 MICROCOMMANDS DeL 5 2 5 5 GENERAL MICROCOMMAND CLASSES 5 2 1 Logical and Arithmetic 522 2 Special Class LOGICAL MICROCOMMANDS Emulate Optional Sign Extend A Move A o Move Complement Complement B ANDA B ANDA B ANDA B Not OR 8 e gt o OR A Bie Be uc B Not AND Exclusive Coincidence THMETIC MICROCOMMANDS Add Subtract Add Carry Subtract Carry Increase Decrease C w Uw HEE pm piI dEBHAIO0 10Ud4UN Pp Om amp CO to O R NOM PB WN tg Ci E S amp oS S oS DA H D MICROCOMMANDS Shift e s s xe gt e e H 5 5 1 1 Single Precision Multiply Step Divide Step Test Bit x4 Ul 9 You 4 IN A SECTION 162 MAINTENANCE 6 1 6 2 6 3 ii IoGENEBAL 4 QR es PREVENTIVE MAINTENANCE MAINTENANCE Add A Masked e 9 Classes
72. o be four bits DVD 0011 0110 DVR 0111 L DVDL XR Explanation 0011 0110 3 Initial condition 0 0110 1100 3 Shift DVD left 1001 Add DVR two s complement no DVD modify 1111 No overflow continue DVS 1101 1000 3 Shift DVD left 1001 Add DVR two s complement 1 0110 1000 2 Modify DVDM and test LC DVS 1101 0001 2 Shift DVD left and add L 1001 1 0110 0001 1 2x 1100 0011 l Shift DVD left and add L 1001 DVS 0101 0111 Shift DVDL left and add L S27 Remainder Quotient 21518008 0 5 5 4 Test Bit The TSB microcommand provides the ability to test and conditionally branch on the state of a specified bit in the A operand The microcom mand cannot be a skip type the K bit 47 is ignored and the BF field is always treated as a branch address The SB field can also specify a Separate branch condition If either the bit test or the SB field condi tion is met the branch occurs This provides considerable flexibility in performing multiple test operations at high speed Mnemonic TSB 1B Microcommand Special branch Type Description The A operand is transferred unmodified to the destina tion The state of the A operand bit specified by the SO field is tested If the bit test condition is met as specified by the T bit 43 a branch is made to the loca tion given in the BF field The SB field can specify an additional branch condition If either the bit test or the SB condition is met the b
73. obus used for parallel transfers of information and Signals between the CPU and all functional system elements The microbus comprises the A operand bus AB the B operand bus BB the M bus MB and other lines Appendix A The Engine and all external devices including memory Macropanel and peripherals communicate with the Microbus The relationship of the Microbus and Engine logic is illsutrated in Figure 4 2 Certain Microbus functions can be performed by the MCA for common I O devices allowing the Microbus to attend to higher speed units Devices on the MACROBUS can communicate with the CPU and directly with other devices depending on their design The MCA is shown in Figure 4 1 because of its important function of conditioning the Microbus for use by the mass of common peripheral devices A basic MACROBUS device is the magnetic core memory which is generally required in any system Cal Data core memory modules are available in 8K and l6K word increments and can be added directly to the MACROBUS up to a typical maximum of 128K words Semiconductor memory can be interchanged with core in any speed capacity mix The CPU addresses memory locations like any other I O devices 4 Two types of control panels are available Macropanel that is adapted to a particular emulation and permits the operator to control the system at the emulated level of operation and a Microconsole that permits control and display at the microl
74. on STATIC L LITRL L Literal Master Synchronization MSYN H PLUS1 L Plus 1 Special Function 04 1 SPFO4 L 2 PSWEN L Processor Status Write Enable B Bus Inhibit 1 BBINH L 2 IRWEN L IR Write Enable B Bus Ol BBOO1 H BBOO0 H B Bus OO B Bus 03 BB0O03 H BB002 H B Bus 02 B Bus 05 BB005 H BBOO4 H Bus 04 07 BB007 H BBOO6 H B Bus 06 Bus 09 BB009 H BBOO8 H Bus 08 B Bus 1l BBO11 H BBO10 H B Bus 10 13 BBO13 H BBOl2 H B Bus 12 OB BB015 H B Bus 14 BB0O14 H Pus 15 These signals are assigned on the small processor interconnection board but are not used on this assembly 1 Signal used only on Engine 1 2 Signal used only on Engine 2 1 9 9 Load CC Register Bus Request Bus Grant Bus Grant Enable Memory Management Inhibit Data Inhibit Special Function 7 1 1 Function 5 Special Function 6 Special Function Decode Inhibit B Field Emulate Power Failure AU Carxy In Write IR Read Interrupt Memory Management Memory Management Cl Microcommand Register 07 DR Write Enable Emulate Emulate Emulate Emulate Emulate Emulate Emulate Emulate Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Stack Limit Interrupt Address Address Address Address Address Address Address Address DAINH L 1 SPFO7 L 1 SPFO5 L 1 SP
75. on and interrupt response hardware Bit byte and word manipulations 256 to 4096 word control memory using bipolar ROM or PROM devices Power failure restart circuitry and line frequency clock included in the computer e Unique control memory substitution provisions e Optional Multiply Divide and single and double precision Shift microcommands e Hardware microprogram interrupts Input Output and Memory e Universal asynchronous I O channel with direct memory access capability Four external priority interrupt levels o l6 bit parallel word or byte mode transfers Automatic I O channel delay time out protection e Optional asynchronous serial I O channel e 8K word 675 ns cycle 275 ns access and 16 850 ns cycle 300 ns access core memory modules e Interleaved data transfers between identical memory modules e Optional extended addressing feature for addressable memory expan sion to 31K without memory management Expansion to 124K or 127K of directly addressable memory with optional Memory Management Unit Microprogramming Aids Microconsole e Alterable Control Memory and support software e Symbolic Microassembler Packaging Power and Environmental e 10 inch computer chassis with vertical board mounting from the top e S Printed circuit backplane with up to 13 spare slots for Memory and CIZQ 6gntroller boards e BougNtans for high volume positive pressure air flow through the
76. on saves both memory and CPU time CMA The CMA microcommand uses the emulate table to generate a control signal that specifies whether the memory access to the A operand is to be read restore or read modify write This is determined by the contents of IR which holds the current instruction being emulated Since the table is unique for each emulation and in some cases may not be required the CMA microcommand is considered optional Mnemonic ID Microcommand Special skip or special branch Type Description The A operand is transferred to the destination The microcommand automatically generates either a memory read restore or a memory read modify write operation on the MACROBUS The type of operation is determined by the state of the conditional memory access control bit from the emulate table The location of the memory word is specified by the contents of the A operand source The operation is performed in the word or byte mode depending on the state of the I O byte control bit from the emulate table The word or byte read memory is stored in RR when received Micro During the execution of CMA AU is set to copy AB onto condition MB leading to unpredictable generally meaningless Codes microcondition codes C21518008 X0 5 45 555 7 Programming In a special skip type microcommand the FN field can generally designate a memory access operation however an FN field memory access o
77. on swap The contents of XR are unmodified C21518008 x0 C21518008 X0 Logical Open Left Shift Word or Byte Operation a Word mode 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 OO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 b Byte mode 15 14 13 12 11 10 09 08 07 06 05 04 03 O2 01 OO 15 14 13 12 11 10 09 08 07 06 05 04 03 O2 01 OO CIN Description For word shifts the A operand and the contents of XR are shifted left one bit The value of CIN designated by the MC field is shifted into XR bit 00 The XR bit 15 is shifted into the A operand bit 00 A operand bit 15 is the shift carry out The shifted A operand result is transferred to the destination The shifted XR result remains in XR Byte shifts are the same as word shifts except that the A operand shift is on the less significant byte only A operand bit 07 is the shift carry out The more significant byte is unmodified Micro a Word modes b Byte modes condition Codes 15 07 A15 4 07 A06 z 1 if A 0 z 1 if AL 0 otherwise otherwise n 1 if 15 1 1 if 07 1 otherwise lt 0 otherwise 1 if gt 0 1 if gt 0 otherwise 70 otherwise 1 if 15 1 1 if 15 1 otherwise otherwise Co E Logical Closed Left Shift Word or Byte Operation a Word mode 15 14 13 12 11 10 O9 08 07 O6 05 O4 03 O2 O1 OO
78. operations are implemented in control memory Mnemonic Microcommand Type Description Registers Used 50 Field MUS 19 Special branch The MUS microcommand provides a set of simultaneous add shift and test operations involving a register containing the multiplier MPR plus XR LC and the state of the next MPR digit The microcommand is automatically re peated until LC 0 For each ONE in MPR a branch is made to a microcommand that adds the multiplicand MPD to XR This permits complete execution of multiply steps in one clock cycle for a ZERO MPR digit and three clock cycles for a ONE MPR digit The MUS microcommand is used for multiplication of two 16 bit operands with a resulting 32 bit product a MPR in a register designated by the AO field of the MUS microcommand This register contains the more significant half of the product at the end of the complete multiplication b MCD in a register designated a separate microcom mand that adds MCD to the partial product XR which accumulates MCD additions to the partial product and contains the less significant half of the product at the end of the complete multiplication d LC which counts the number of MUS iterations per formed e The L microstatus bit used to propagate carries from the less significant half to the more significant half of the partial product The SO field must be programmed for a double precision logical open lift Shift bi
79. or Byte Operation a Word mode 15 14 13 12 11 10 O9 08 07 06 05 04 03 02 01 00 CIN 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 b Byte mode 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 T 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Description For word shifts the A operand and the contents of XR Micro condition Codes are shifted right one bit XR bit 15 ORed with the State of CIN designated by the MC field is shifted into XR bit 15 XR bit 00 is shifted into A operand bit 15 A operand result is transferred to the destina tion The shifted XR result remains in XR Byte shifts are the same as word shifts except that the A operand shift is on the less significant byte only bit 00 is shifted into A operand bit 07 The more significant byte is unmodified Same as logical open right shift Arithmetic Closed Right Shift Word or Byte Description Same as logical closed right shift Multiply Step The MUS microcommand is a specialized version of the Shift microcommand with an automatic iterative repeat that permits high speed implementa tion of a Multiply instruction The average execution time is 300 ns per bit plus the additional time required to preformat the multiplier and multiplicand determine the sign of the product and format the final result No additional hardware is required for the high speed multiply function since all
80. ory Mnemonic Microcommand Type Operation Description Registers Used Procedure 21518008 0 DVS 1 Special branch R A 4B 1 1 PA The DVS microcommand executes two s complement addition of the divisor DVR to the more significant word of a double precision dividend DVD a carry out is generated by the addition the result replaces the more Significant word of DVD otherwise DVD is unchanged The carry out must be saved in the L microstatus bit the microcommand is used in conjunction with a double length left shift of the operand and XR on each iteration with the carry out saved in L shifted into XR DVS can be automatically repeated using LC The result is a single length quotient with a single length remainder a DVD more significant word DVDM in a file register designated by the AO field of the DVS microcommand This register contains the remainder at the end of _ the complete division operation b DVD less significant word DVDL in XR DVR in a register designated by the BO field of the DVS microcommand This register contains the quotient at the end of the complete division operation d which counts the number of iterations performed The L microstatus bit used to propagate quotient bits into XR 1 Convert DVD to a 3l bit positive number 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 OO 15 14 13 12 11 10 09 08 07 06 05 04 03
81. peration is overridden by the conditional memory access operation specified by the OP field CMB The CMB microcommand performs the same functions for the B operand as CMA performs for the A operand Mnemonic CMB SIE Decode Optional In emulation microroutines it is desirable to have a means to modify specific bit fields in a given microcommand based on the particular instruction being emulated For example an add and a subtract micro routine may differ only in that the operands are added or subtracted By modifying the OP field of the arithmetic microcommand a common routine can be used Another example is accessing a particular FR based on a field in the microcommand The DCD microcommand permits this type of operation to be accomplished directly through use of a decode table that modifies specified bits in the microcommand following the DCD microcommand The table is set up for the specific emulation and in some cases may not be needed For this reason the DCD is considered an optional microcommand Mnemonic DCD 1 Microcommand Special skip or special branch Type Description A zero word is placed on MB The DCD microcommand selects a 16 bit modifier from the decode table This word modifies a specified set of bits in the least Significant 16 bits of the next microcommand read from control memory prior to execution The modifier and bit fields to be modified selected using the AO and BO fields of DCD an
82. ranch occurs SB Field a The K bit 47 is ignored b The T bit 43 specifies the ONE or ZERO state of both the bit test and the SB field test i e both must test the same state The SB field test conditions are given below The normal unconditional branch condition is treated as a no branch This no branch must be programmed if only the bit test condition is to be tested SB Field Code Test Condition 0 loop count equals zero 1 carry 2 overflow 3 zero 4 negative 5 positive 6 odd 7 unconditional branch treated as no branch in TSB Micro During the execution of TSB AU is set to copy AB onto condition MB leading to unpredictable generally meaningless Codes microcondition codes 5 5 5 Modify Macrostatus Optional When emulation enhancement circuitry is included the CPU contains in addition to the microlevel status in MS a processor status register PS that stores macrolevel conditions including link overflow negative C2518008 x0 QE 5 43 and zero well as other information the states of the emulated com puter These status conditions are generated at intermediate times by the emulation microroutines and must be transferred to PS by microcom mand Since PS update can differ for many types of instructions being emulated the update function can add an excessive number of microcom mands to the emulation microroutines To provide fast PS update the emulate table ca
83. s between CPU memory and peripheral elements 16 bits with byte capability 16 bits from Microbus can be extended within I O channel adapter least significant bit is for byte addressing Part of emulation enhancement circuitry o cos E hs ERE E c21518008 xo Table 2 1 Continued I O channel Four priority request levels with priorities and multiple requests per level requests nonprocessor request NPR level for direct device to device transfers CPU can set its own priority to any level except NPR Serial I O channel Serial I O controller option for rates up to 9600 baud RS 232 or cur rent loop interface Memory Magnetic core 8K or 16K words per module 16 bits per word Memory expansion Typically 124K words maximum Memory Management Unit option is required above 32K Memory interleave 8K word or 16K word Cal Data core mem ory pairs can be interleaved for in creased throughput rate Line frequency 50 60 Hz line clock clock PACKAGING Processor chassis 105 inches 26 7 cm high by 19 inches 48 cm wide by 24 inches 43 cm deep rack mounted slides or table top vertical top loaded boards contains Macropanel Engine MCA plus slots for memory and I O controllers internal power supply cooling fans internal power distribution Connectors 36 pin 0 6 inch 1 5 cm card inser tion depth mounted on printed circuit backplane Board size 8 9 by 15 7 i
84. s used the computer 21518008 Depending the microcommand the least significant 16 bits of CR can be gated via BB into AU Alternately a literal one value can placed on BB 4 2 4 Control Stack CS CS contains 16 l2 bit registers that are accessed via the four bit up down stack counter SC When a CC save is specified by a micro command the contents of CC are transferred to CS The contents of CC are always one greater than the location of the microcommand specifying the save Likewise a microcommand can specify a return operation that transfers the contents of the current CS location to CC The return microcommand can simultaneously transfer the incremented contents of CC to the CS register that contained the return address Incrementing and decrementing of SC can be specified independently of the save and return functions CS permits convenient implementation of re entrant and multilevel subroutines at the micro level Any microcommand branch condition can specify a save operation with an automatic return to the calling sequence using a Return microcommand SC counts up from zero modulo 16 and rolls over the boundary in either direction There is no indication given for a stack overflow It is the programmer 5 responsibility to maintain the stack within limits The contents of CS current location can be read by microcommand however CS cannot be directly loaded and SC is no
85. t directly accessible to the microprogram The contents of CS therefore cannot be saved in the event of a power interruption It is mandatory that provision be made to execute all returns in CS within the time available for power interruption Since several milliseconds are available this imposes no practical restriction on the use of the stack 4 2 5 Loop Counter LC A powerful feature of the Cal Data Engine is the eight bit LC that per mits a single microcommand or a group of microcommands to be automati cally repeated up to 256 times LC is loaded via MB and can be read with a microcommand In a repeat sequence LC can be tested for a zero or nonzero condition by any microcommand in the sequence with a branch operation executed if the condition is met LC is decremented each time it is tested Individual microcommands can also be gt repeated the number of times specified by LC 4 3 DATA SECTION C21518008 x0 A block diagram of the data section is shown in Figure 4 4 The data section contains the basic arithmetic logic and busing elements f the Engine required for manipulation and transfer of data throughout the computer 7 7 0X 8008TSTZO YOOTA 32 5 e3eq p onbT MICROSTATUS REGISTER 506 500 FILE AB15 ABO0 ARITHMETIC AU SHIFT Mp15 MB00 REGISTERS LOGIC UNIT ELEMENTS FR BB15 BBOO AU SHIFT REGISTER XR
86. tional or unconditional branch to a new pro gram location can occur based on the results of executing the current microcommand or on results previously stored In this type of microcommand both an A and B operand to AU are specified The destination of the resulting operation is also specified Arithmetic condition codes resulting from the microcommand execution can be saved or ignored If a branch condition is specified an ll bit branch address is provided that alters the microprogram sequence if the branch condition is met control bit is also provided that can cause the next CM address to be pushed into CS before the branch is made This permits the microprogram to later execute an automatic return to the microprogram sequence via CS It is not necessary to specify a branch condition even though the micro command is a branch type If no branch condition is specified an aux iliary set of control functions can be specified that are performed simultaneously with execution of the basic logical or arithmetic oper ation The remaining fields of the branch type microcommand provide special control functions that can modify execution and content of the next microcommand in sequence The operations performed by these fields are common to all microcommands regardless of class and type Skip Type The logical or arithmetic skip type microcommand performs the same basic operations as the branch type The differences in the skip type mi
87. ts 15 12 6 as specified in the Shift microcommand description Table 5 4 C21518008 XO C21518008 XO Operation The following operations are executed simultaneously by the MUS microcommand Shift left XR XR carry to shift gates Add MPR L shift sum left add XR carry LC 1 LC reset L Procedure Convert MCD to a positive number 15 14 13 12 11 10 09 08 07 O6 05 04 03 02 01 00 Convert MPR to positive number shift left and test MPR relative to zero 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 OO MPR Initial conditions XR 0 b 0 LC 15 for l6 bit multiplication Program MUS control fields as follows SB 10 dynamic branch lt O 19 MUS DN MPR address NX 3 inhibit next microcommand if branch MPR address 6 add and update L 0 no operation SO 6 double precision logical open left shift BF MUS location minus one The symbolic microassembler automatically sets up all fields except DN and AO For the final double length result the MPR register and XR must be shifted right one bit after the last iteration This can be performed using the standard SHF microcommand programmed for a double precision logical open right shift The sign of the product must also be determined and inserted C21518008 XO0 21518008 6 The basic microcommand sequence is illustrated below Entry Execute MUS
88. uted by the CPU The format for the logical and arithnetic classes is identical The general characteristics of each class and type are defined below 5 2 1 Logical and Arithmetic Classes the name implies the logical and arithmetic classes of microcommands perform logical and arithmetic functions of one or two variables as specified by the microcommand The specific logical or arithmetic 21518008 XO0 LOGICAL AND ARITHMETIC CLASSES Branch Type 4241 37 36 3 24 23 20 19 1615 12 11 Skip Type E mM se branch condition code bit 47 specifies microcommand type basic operation performed by the microcommand destination address of result from the arithmetic logic unit AU special control functions source address of A operand to AU microcondition code specification dispositions Special control functions source address of B operand to AU Special operation control functions branch address or auxiliary control functions literal value auxiliary control functions Figure 5 1 Microcommand Formats 522 21518008 operation is defined by the field total of 16 logical and eight arithmetic operations axe implemented The same set of operations is performed regardless of whether a branch or skip type microcommand is used Branch Type The logical or arithmetic branch type microcommand permits the program mer to specify that a condi
89. ve these assignments if full software compatibility is to be retained Table B l Interrupt Vectors Octal Address Reserved I O channel time out error Reserved instruction vector Debug trap vector Power failure trap vector Trap trap vector Serial channel in BR4 Serial channel out BR4 High speed reader BR4 High speed punch BR4 Line Frequency Clock BR6 Line printer BR4 Floating point error Memory management abort Macropanel interrupt Start of floating vectors C21518008 xo 1 OX 8008TSTZO Initialize Interrupt Data Data Data Data Data Data Data Data Parity Bit Low Ground Ground Ground Ground Ground Nonprocessor Grant Bus Grant 7 BUS INIT L BUS INTR L BUS DOO L BUS DO2 L BUS DO4 L BUS DO6 L BUS DO8 L BUS D10 L BUS D12 L BUS D14 L BUS PA L GND GND GND GND GND BUS NPG H BUS BG7 H DOl L D03 L D05 L D07 L D09 L D11 L D13 L D15 L PB L BBSY L SACK L NPR L BR7 L BR6 L 5 Vdc Ground Ground Data 01 Data 03 Data 05 Data 07 Data 09 Data 11 Data 13 Data 15 Parity Bit High Bus Busy Selection Acknowledgement Nonprocessor Request Bus Request 7 Bus Request 6 Ground These signals are assigned on the backplane but are not used on this assembly I O S HONOVW saQueuubrTssYV I032euuo SLNAWNDISSY HOLO3NNOO 9 XIaNaddv 0X B008TSTZO
90. ype microcommand is the same as the branch type and specifies the same operations except that a Instead of a branch condition a condition is specified under which execution of the microcommand at the next CM location can be inhibited skipped The CM address sequence itself is not altered b Since a branch address cannot be specified by this type of micro command and since a B operand is never used the space reserved for these is used to specify a set of auxiliary control func tions 5 3 LOGICAL MICROCOMMANDS The following paragraphs present a description of each logical micro command summary of all the basic microcommands executed by the CPU is given in Table 5 1 The description of each microcommand includes the mnemonic hexadecimal OP field code symbolic notation describing its operation where appli cable a description of the function performed and examples or other comments to clarify the description C21518008 x0 Table 5 1 Cal Data 100 Engine Microcommand Summary OP Field Mnemonic Hexadecimal LOGICAL Emulate optional Sign Extend A Move Move B Complement A Complement B AND A B AND A B AND B Not OR OR A B OR A B OR A B Not AND Exclusive OR Coincidence ARITHMETIC Add A B Subtract A B Add Carry Subtract Carry Increase A Decrease A Add Masked reserved SPECIAL Shift Multiply Step Divide Step Test Bit Modify Macrostatus optional

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