Eur1553 - ESA Microelectronics Section
Contents
1. T UK CN E WEIT 3 MM Ll xX 20 x o Ozzgt gt ay a configuration Figure 3 Structure and Usage of the IP core EADS Astrium SAS application I F Ref R amp D E53 NT 1206 V ASTR Eur1553 Edition 0 R v 01 Date 2009 10 23 Page 17 37 The RT53eur core is provided as a generic netlist Two versions of this netlist are provided A version with a synchronous reset in the file named source core rt53core_syne vhd A version with a synchronous reset in the file named source core rt53core async vhd The user has to select which core to use The following recommendation that has to be verified for each project can be given for an ATMEL ASIC in 0 35 um or 0 18 um it is recommended to have a synchronous reset since an SET can impact the asynchronous reset for an ACTEL RTAX or SX the asynchronous reset tree is protected against SET and thus the cote with the asynchronous reset could be used no recommendations are given for Xilinx in flight The quarantine buffer is 32 word of 16 bits internal memory used to keep the received words in the direct and indirect modes before delivering them to the application According to the technology the buffer can be a buffer made with flip flops that is coded in VHDL RTL a buffer made using the memories of the ACTEL AX family It is generated with smartgen2. Eur1553 Edition 0 R v 01 Date 2009 10 23 Page 9 37 23 DEFINITION OF TERMS Bus Controller BC The Bus Controller s task is to initiate and control all data transfer on the Mil Std 1553B Data Bus It is the sole device allowed to transmit Command Words Remote terminal RT The Remote Terminal is used to interface the subsystems to the Mil Std 1553B Data Bus system and perform data transmissions on the Mil Std 1553B Data Bus as controlled by the Bus Controller Bus Monitor The Bus Monitor s task is to listen to the Mil Std 1553B Data Bus traffic and to extract selected information to be used at a later time Mil Std 1553 Data Bus All the hardware including cables isolation resistors transformers etc required to provide a data path between the Bus Controller and all the associated Remote Terminals Message single Message is the transmission of a Command Wotd Status and Data Words if they are specified Mode Command Command Word in which the Subaddress Field is set to 00000 or 11111 and a Mode Code is transferred from the Bus Controller to the Remote Terminal Message with a data flow from the Bus Controller to the Remote Terminal Command Word in which the Subaddress Field is set different to 00000 or 11111 and the subsequent transfer of Data Word s from the Remote Terminal to he Bus Controller is initiated Message with a data flow from the Remote Terminal to the Bus Controller Vec
3. a buffer made using the memories of the XILINX libraries It is generated with coregen The following recommendation can be given In ACTEL RT54SU there is no internal memory The buffer has to be made with flip flops In ACTEL RT5AX the buffer can be made with flip flops or by using the internal memory of the ACTEL In ATMEL 0 35 um pure gate array there is no internal memory thus the buffer can be made with flip flops In ATMEL 0 35 um composite array or in ATMEL 0 18 um ATC18RHA it is not really recommended to create a hard block of memory of only 32 words of 16 bits thus the buffer can be made with flip flops EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eur1553 Edition 0 R v 01 Date 2009 10 23 Page 18 37 5 USING THE IP CORE 51 INSTANTIATING THE IP CORE The IP core is easy to instantiate An example of instantiation of the IP core 15 also depicted in Figure 3 At first two genetics have to be defined genefic GSYNC_RST boolean false asynchronous reset false synchronous reset true RAMTYPE natural 1 1 flip flops 2 Actel AX 3 Xilinx RAMTYPE selects the type of RAM used to make the quarantine buffer GSYN_RST selects the type of reset of the IP core The CLK and pins shall be connected to clock and inverted clock signals There are very few flip flops of the IP core that are controlled by the falling clock edge The inversion of the clock has been ma
4. anda 191 comb 1 and2a 186 comb 1 and2b 74 comb 1 and3 35 comb 1 and3a 52 comb 1 and3b 34 comb 1 26 comb 1 and4 12 comb 1 and4a 32 comb 1 and4b 35 comb 1 and4c 13 comb 1 buff 9 1 cm8 1616 comb 1 cm8inv 876 dfp1b 51 seq 1 inv 14 comb 1 Or2 36 comb 1 or2a 100 comb 1 or2b 87 comb 1 Or3 16 1 or3a 28 comb 1 or3b 34 comb 1 or3c 11 comb 1 or4 2 comb 1 or4a 19 comb 1 or4b 16 1 or4c 19 comb 1 or4d 9 comb 1 xal 12 comb 2 25 comb 1 XoOrE2 39 comb 1 df1 40 seq 1 767 seq 1 dfe3c 99 seq 1 EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eur1553 Edition 0 R v 01 Date 2009 10 23 Page 31 37 dfe4f 3 1 clkbuf 2 clock buffer inbuf 67 outbuf 60 clkint 1 clock buffer RAM64K36 1 XOR4 18 false 3016 true 3016 RAM ROM Usage Summary Block Rams 1 of 64 1 The critical paths are provided hereafter Requested Estimated Requested Estimated Clock Frequency Frequency Period Period Slack CK 24 0 MHz 55 5 MHZ 41 667 L9 3 172205 CK N 24 0 MHz 55 5 MHz 41 667 b s 12 296 9 3 SYNTHESIS IN ATMEL ATCI8RHA An example of synsthesis in ATMEL ATC18RHA is given in the synop atc18rha directory The synthesis tool used 15 Synopsys DC Compiler issue 2007 03 SP5 1 The SYN tcl file is provided The top level of the IP has been copied locally to modify the generics quarantine buffer made with flip flops
5. ctl FirstStackPointer reg 0 Q reg cp hdfcrb1 0 00 Sa r library setup time 0 58 31 42 data required time 31 42 data required time 31 42 data arrival time 15 05 slack MET 16 37 ns 9 4 SYNTHESIS IN An example of synthesis of the IP in Virtex 4 is also provided The Synplify synthesis tool does not recognize the Xilinx memory that will have to be provided duting the place and route as an edif file the files of the Xilinx memory are provided in the ram xilinx directory EADS Astrium SAS 1 1 553 Ref R amp D E53 NT 1206 V ASTR Edition O Rev 01 Date 2009 10 23 Resource Usage Report for rt53eur Mapping to part xc4vl1x100ff1148 10 Cell usage FD 40 uses FDC 746 uses FDCE 63 uses FDP 48 uses FDPE 3 uses MUXF 5 1 use sram xilinx 1 use LUT1 32 uses LUT2 426 uses LUT3 891 uses LUT4 1209 uses L O ports 129 I O primitives 127 IBUF 67 uses OBUF 60 uses BUFGP 2 uses I O Register bits 0 Register bits not including I Os 900 0 Global Clock Buffers 2 of 32 63 Total load per clock CK 896 CK N 6 Mapping Summary Total LUTs 2558 25 Worst slack in design 18 666 Requested Estimated Requested Clock Frequency Frequency Period CK 24 0 MHz 72 6 MHz 41 667 CK N 24 0 MHz 173 3 MHz 41 667 Page 35 37 Estimated Period Slack 13 773 18 737 5 769 18 666 EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eur1553 Edition 0 R v 01
6. std_signed std_developerskit Mentor Std_developerskit provided with Modelsim synplify Synplify package containing synplify attributes unisim unisim Xilinx package simprim simprim Virtex package modelsim_lib Mentor modelsim_lib that contains signal_spy etc axcelerator compiled ACTEL AX library xilinxcorelib compiled XILINX corelib library The user has to find the std_developerskit the Actel and the Xilinx libraries that cannot be distributed with the IP If the user wants to synthetize the IP using an ATMEL libray as ATCI8RHA then the synopsys_dc_setup file located in synop_atc18rha has to be modified to take into account the location of the ATMEL libraries in the user environment If the installation is correctly made typing bin MAKE in the simenvl directory should execute cotrectly the compilation of the IP model EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eur1553 Edition 0 R v 01 Date 2009 10 23 Page 12 37 3 2 STRUCTURE OF THE DELIVERY The delivery contains the following files e The bin directory containing procedures for running simulations The source directory contains the VHDL files for the top level the VHDL models for the memories and netlists for the IP core e The tbe directory contains the source code of testbench of the IP The scripte directory contains the scripts read by the testbench of the IP e The simenv 1 directory is used for sim
7. 02 1919 23 aor21d1 21 95 4 87 80 aor22d1 25 08 18 451 58 aor31d1 21 95 15 329 27 aor31d2 25 08 T 25 08 aor211d1 25 08 L 25 08 aor221d1 31 36 2 62 72 1191 25 08 7 175 61 buffdl 12 54 140 1756 15 buffd3 15 68 1 15 68 01 1 28 22 2 56 44 hdfcrb1 254 01 27 6858 43 n hdfnrb1 235 19 1394 327868 76 n hdfprb1 254 01 15 3810 24 n invOdO 6227 358 2245 37 1 091 9 40 130 2223 03 invod2 12 54 7 87 80 nd02d0 12 54 10 125 43 nd02d1i 12 54 292 3662 84 nd02d2 18 81 3 3 620 92 15 68 l 15 68 15 68 110 1724 80 nd03d2 20 22 13 366 91 nd04d1 18 81 98 1843 96 EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Edition 0 R v 01 Date 2009 10 23 Page 33 37 Eurl553 90442 1912940 12 1 nd12d2 ndi3d1 0240 2 1 nr02d2 nr03d1 nr03d2 nr04d1 nr04d2 nri3d1 oai21d1 0 12142 oai22d1 1 1 oa131d2 oai211d1 122191 oai222d1 131141 oa1321d1 oa1322d1 oaim21d1 oaim21d2 oaim22d1 oaim31d1 oaim211d1 oan211d1 or02d1 or03d1 or04d1 ora31d1 ora211d1 11 1 xn02d1 xr02d1 xr03d1 413 15 501 125 241 i75 2621 1771 2149 2088 5864 1094 2430 156 21431 1531 241 1467 592 096 407 SEL 413 34 SEL S0 75 1561 376 109i 150 2 S04 29 482 5048 1919 Total 81 references 419665 Startpoint core ifa edacc DataInR reg 2 Q reg rising edge triggered flip flop clocked by CK Endp
8. 2 SYNTHESIS IN ACTEL 30 9 3 SYN THEBSISTIN 31 9 4 34 10 CAO TOOLS CONFIGURATION eos anoo va ra FCR 36 11 VERSION OF THE SOURCE FILES 5 2 5 0560959 POS EP eae To Poco pu 36 EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eurl553 Edition 0 R v 01 Date 2009 10 23 Page 6 37 1 INTRODUCTION This document is written in the frame of ESA R amp D AO 1 5052 06 NL CP Europeanization of MIL STD 1553B Data Bus It is part of task 1 related to the development of a Digital RT IP performing a 1553B Remote Terminal This document is the User Manual of the IP core The IP is called RT53eur e stands for Remote Terminal 53isareminder for 1553B Data Bus e EUR reminds that the IP has been developed within the Europeanisation of Mil STD 1553B Data Bus Products Moreover the IP core includes some of the new features defined within the ECSS 5013 MIL STD 1553 B extension working group This document desctibes the usage of the IP database The functionality of the IP 15 described in AD10 The version of the IP tagged in CVS is V1 2 EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Edition O R v 01 E u 1 2 2 3 Date 2009 10 23 Page 7 37 2 DO
9. CUMENTS ACRONYMS AND CONVENTIONS 2 1 APPLICABLE DOCUMENTS ECSS Q60 02 Final Draft ASIC FPGA Development Standard http ww w estec esa nl microelectronics asic Final Draft ECSS MIL STD 1553B Notice 1 4 15 January 1996 Digital Time Division Command Response Multiplex Data Bus MIL HDBK 1553A Multiplex applications Handbook Nov http ams aeroflex com ProductFiles AppNotes milhbk1553a pdf SAE 54112 January 1989 Production Test Plan For the Digital Time Division Command Response Multiplex Data Bus Remote Terminals SAE AS4111 Issue 1998 10 Validation Test Plan For the Digital Time Division Command Response Multiplex Data Bus Remote Terminals RT53eur IP core data sheet Astrium reference R amp D E52 RP 01192 ASTR ASP54 Transceiver ASIC Specification Astrium R amp D E53 NT 00461 V ASTR EADS Astrium SAS Eurl553 2 2 ACRONYMS AD ASIC ASSP CDR CPPA CPU DDR DFF DRC DSP EDAC ESA ESTEC FDIR FPGA GEO I O ID IDR IEEE IP ITT JTAG LEO LET LVS PCB Applicable Document Application Specific Integrated Circuit Application Specific Standard Product Critical Design Review Central Part Procurement Agency Central Processor Unit Detailed Design Review D Type Flip Flop Design Rule Check Digital Signal Processor Error Detection And Correction European Space Agency European Space Research and Technology Centre Failure Detection Isolation an
10. D The core of RT53eur IP is provided as a generic netlist This generic netlist is based a generic library provided in the lib directory The library that contains all the cells required to synthesize the VHDL code to the IP core These cells are used ADD And Or gel o AOI22 And Or cell BUF2X buffer with a drive of 2 BUFAX buffer with a drive of 4 HDFF DFFR HDFFR DFFSB HDFFSB NAND2 cell NAND3 NANDJ cell NAND4 NAND4 cell NOR2 cell NOR3 NOR cell OAI22 Or And cell Figure 6 the generic library cells The RT53eur IP can be synthetized in any technology Example of synthesis are given for ACTEL RTAX2000 component using Synplify synthesis e ATMEL ATC18RHA using Synopsys DC compiler EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eur1553 Edition 0 R v 01 Date 2009 10 23 Page 30 37 9 2 SYNTHESIS IN ACTEL RTAX2000 An example of synsthesis in ACTEL RTAX2000 is given in the synplify ax2000 directory The synthesis tool used 15 Synplify issue 9 6 2 The prj file is provided The top level of the IP has been copied locally to modify the generics quarantine buffer made with ACTEL memory and asynchronous reset The number of cells of the synthesis 1s provided hereafter Resource Usage Report of RT53eur Combinational Cells 2782 of 21496 135 Sequential Cells 960 of 10752 95 Total Cells 3742 of 32248 125 Clock Buffers 3 IO Cells 129 Details
11. Date 2009 10 23 Page 36 37 10 CAO TOOLS CONFIGURATION The configuration of the tools used by Astrium to develop the spacewire core is the following e VHDL simulator Mentor Modelsim version 5 84 e Synthesis tool Synplify version 9 6 2 e Synopsys DC compiler 2007 03 11 VERSION OF THE SOURCE FILES cvs status at Wed Dec 2 14 37 04 CET 2009 directory home rt53eur rtb53eur rt53eur ip source packrt53eurcmp vhd Up to date work rev 1 1 1 1 rep rev 1 1 1 1 vod Up to date work fevsl l l l rep rev l 1 1 1 rt53eur wrapper vhd Up to date work rev 1 1 1 1 rep rev 1 1 1 1 sram ax vhd Up to date work rev 1 1 1 1 rep rev 1 1 1 1 sram_dff vhd Up to date work rev l l l l rep rev l l 1 1 sram xilinx vhd Up to date work 1 1 1 1 rep rev 1 1 1 1 directory core rt53core Up to date work rev 1 2 rep rev 1 2 rt53core async vhd Up to date work rev 1 2 rep rev 1 2 IU53COIO Up to date work rev 1 2 rep rev 1 2 rft53cOore Up to date work rev 1 2 rep 1 2 gt end of cvs status EADS Astrium SAS Alberto BOETTI Kostas MARINIS Arnaud WAGNER Marc SOUYRI Jean Marc TAINE Marc Daniel WEBER Nicolas BEHOT 1553 Asttium Astrium Astrium Astrium Astrium Ref R amp D E53 NT 1206 V ASTR Edition O 01 Date Page 2009 10 23 37 37 EADS Astrium SAS
12. NEO MIO pr E 6 2 DOCUMENTS ACRONYMS AND CONVENTIONG cccsccscssceccsceccsccscescscesceccsceses 7 2 1 APPLICABLE DOCUMENTS cccccccccssssscsssssssssssccccceceessssesssssesssssssccacsacccesessessceesssssssccsesccecesesesesseseecesssseaes T 2 2 ACRONYM s 9 25 DEFINEFION OF TERMS 9 2 4 AAAS 10 LE 10 DO ENTE E c 10 D 10 VEA Word IOI mihe TIIS 7 c 10 INSTALLING THE IP 11 3 1 INSTALLATION OF THE DELIV FEN ERE UNE diat une OPUS 11 3 2 STRUCTURE OF THE DELIVERY 52i cseccteccteseoecteszedeccqesetescteseneetetesese o evVcevs ver EY E Eve etr 12 4 DESCRIPTION OF RT53EUR 13 4 1 ENVIRONMENT 13 4 2 THE IP MODE CODE CDN 16 B USING RP 18 5 1 INSTANTIATING THE IP CORRE ertet ken a ten ne does Idus Sid dado eti nu tied unb cetera ide 18 5 2 CONFIG
13. Ref R amp D E53 NT 1206 V ASTR 1 553 Edition 0 R v 01 Date 2009 10 23 Page 1 37 Project contract n 20041 06 NL CP Europeanisation of Mil STD 1553B Data Bus Products Task 1 Digital Remote Terminal ASIC RT 53eur IP Core User Manual ASIC expert Verified by Arnaud Wagner 12 Nov 2009 1553B Expert Nicolas BEHOT Authorized by 1553 product Manager m UT 12 Nov 2009 EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR 1 553 Edition 0 R v 01 Date 2009 10 23 Page 2 37 SUMMARY This document is written in the frame of ESA R amp D AO 1 5052 06 NL CP Europeanisation of MIL STD 1553B Data Bus It is part of task 1 related to the development of the RT53eur IP This document is the User Manual of RT53eur IP that is a MIL STD 1553B Remote Terminal EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Edition 0 R v 01 Date 2009 10 23 Page 3 37 DOCUMENT CHANGE LOG Issue 00 00 29 2009 00 01 2 Dec 2009 new version of the synchronous IP model IP version is 1 2 add a source version chapter add Xilinx synthesis results PAGE ISSUE RECORD Issue of this document comprises the following pages at the issue shown EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eurl553 Edition 0 R v 01 Date 2009 10 23 Page 4 37 TABLE OF CONTENTS TABLE OF CONTENTS mE E REESE ee eee eee add 4
14. TO BITi being the most significant bit OXNIBi NIB0 indicates value hexadecimally coded in NIBi TO NIBO NIBI being the most significant nibble For instance 1111000010101010 and OxFOAA indicates the same word value 2 4 3 BIT definition A bit in a register is set when its value is 1 reset when its value is 0 2 4 4 Word numbering in the 1553 frame The first data word transmitted in a 1553B message shall be numbered as DW 1 the second transmitted shall be numbered as DW 2 and so on EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eur1553 Edition 0 R v 01 Date 2009 10 23 Page 11 37 3 INSTALLING THE IP MODEL 3 1 INSTALLATION OF THE DELIVERY The IP database 15 provided as a single file that has been generated on a unix workstation with a tar command followed by a gzip command The user must cteate a specific directory on unix and then type the following commands gt gunzip delivery gz gt tar xvf delivery The tar command should create the directories described in the next paragraph The database can be simulated using Modelsim and synthetized using Synplify for FPGA and Synopsys DC compiler for ASIC Other tools could be used but no command files are provided The user shall then modify the modelsim ini file of the simenv1 directory according to his CAD environment for std standard library ieee IEEE library synopsys Synopsys libraries std_arith std_unsigned and
15. UREN G TE de does erases DEDE YE ce ee 19 6 THE TESTBENCH OF THE RT53EUR IP 20 6 1 BERI UQIEmet 20 6 2 DINERO SETA 21 QUEE IU IRR 21 Go OI TRI 21 NEUES DU I 21 G2 Commands 100 7m Em 23 7 THE SCRIPT FILES DELIVERED WITH THE 24 7 1 SUID 24 12 DECRIPTION THE SCRIPTS PE ver evt Pe ete nee etes sentence egere tete bises 24 D p ee ie a 24 0 MOG On ee D sco oe Sakae aR es 25 cree tec cece ccc ac a ee deca ss ue 25 PD DOG I AINE 26 8 COMPILING AND SIMULATING THE IP ss cece cece cc ecccccccccccccccccccccsccccsccececs 27 8 1 PROCEDUR E EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eurl553 Edition 0 R v 01 Date 2009 10 23 Page 5 37 8 2 RESULTS ON RER RER RER 28 9 SYNTHESIS OF THE RT53EUR IP TO DIFFERENT TECHNOLOGY 29 9 1 AO a 29 9
16. ading the next command syntax WAIT T time PAUSE Function wait all other emulators syntax PAUSE IRACE dec Function Assign the signal TRACE that allows a visualisation of simulation progress in the waveform window syntax dec 6 2 3 Commands of the 1553 Emulator SEND COM RTAD E R SA CWC Function Fill array in order to Send a command word on 1553 bus RTAD Address of the remote terminal 0 30 or Broadcast Address 31 E R for Transmit or Receive SA Sub Address 1 30 or Mode Command 31 CWC Number of Data Words or Value of the Mode Command syntax SEND_COM dec str dec dec SEND_CC RTAD E R CODE Function Fill array in order to Send Mode command word on 1553 bus RTAD Address of the remote terminal 0 30 ot Broadcast Address 31 E R E or R for Transmit or Receive CODE Value of the Mode Command syntax SEND CC dec str dec SEND DATA NBDATA DATA1 DATA2 DATA8 EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eur1553 Edition 0 R v 01 Date 2009 10 23 Page 22 37 Function Fill array in order to send Data words on 1553 bus NBDATA Number of data words DATA1 DATA2 DATAS hexadecimal value of the data words 8 values shall be entered even if only e g 3 words are used The remaining ones shall be set to 0000 Sending 5 data words can be done by issuing 5 SEND DATA commands with one valid word ot by sending only one SEND DATA comm
17. and synchronous reset The number of cells of the synthesis is provided hereafter the result is given in um since it is a standard cell technology The critical path is also provided The IP runs at about 58 MHz but a derating of about 30 has to be taken for routing In any case the maximum frequency of the IP that is 24 MHz is largely exceeded kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Report reference Design RT53eur Version Z 2007 03 SP5 1 Date Mon Nov 9 14 07 24 2009 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkxk Attributes b black box unknown bo allows boundary optimization EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eur1553 Edition 0 R v 01 Date 2009 10 23 Page 32 37 dont touch mo map only h hierarchical n noncombinational r removable S synthetic operator u contains unmapped logic Reference Unit Area Count Total Area Attributes Reference Library Unit Area Count Total Area Attributes an02d1 15 68 94 1473 92 an03d1 18 81 47 884 35 an04d1 25 08 13 326 14 21 1 15 68 96 1505 28 12142 31 36 2 62 72 aoi22d1 18 81 48 903 16 13141 18 81 63 1185 40 aoi211d1i 18 81 45 846 71 40121142 34 49 2 68 99 aoi221d1 25 08 38 953 34 aoi222d1 31 36 9 282 24 131141 21 95 13 20543917 aoi321d1 31 36 9 282 24 aoi322d1 34 49 8 215496 aoim21d1i 18 81 14 263 42 aoim22d1 21 95 41 900 03 aoim31d1 21 95 LL 241 47 aoim211d1 21 95 7 153 66 aon211d1 28 81 1
18. and with 5 valid words Sending 32 words cane be done by sending 4 SEND DATA commands with 8 valid words syntax SEND DATA dec hex hex hex hex hex hex hex hex SEND BUS Function effectively send the command word and data if any on the bus syntax SEND BUS CHECK STATUS RTAD ERR DIFF OCC STATUS Function Receive and check of the status word RTAD Address of the remote terminal 0 30 or Broadcast Address 31 ERR OK or ERROR DIFF BROADCAST or SINGLE OCC BUSY or FREE SI ATUS The 8 bits of the reserved field of the status syntax STATUS dec str str str str READ DATA NBDATA Function Receive without checking NBDATA NBDATA Numbet of data words syntax READ DATA dec CHECK DATA NBDATA DATA1 DATA2 DATAS Function Receive and check of NBDATA data words NBDATA Numbet of data words DATA1 DATA2 DATAS hexadecimal value of the data words 8 values shall be entered even if only e g 3 words are received The remaining ones shall be set to 0000 and are not checked syntax CHECK DATA dec hex hex hex hex hex hex hex hex ECHO MESSAGE Function print a message in the log file of the simulator MESSAGE string to print syntax ECHO str EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eur1553 Edition 0 R v 01 Date 2009 10 23 Page 23 37 6 2 4 Commands of the Emuenv Emulator REG READ address exp data Function performs a read in an ASIC register read da
19. as an asynchronous reset and buffer made with flip flops bin SIME msg nominall ramax syncrt 10 Simulate IP with msg nominall script at 10 MHz in interactive mode IP has a synchronous reset and buffer made with ACTEL AX memories bin SIME all f 24 ref Simulate IP with all the scripts at 24 MHz in batch mode and save the log files in zzlog ref IP has an asynchronous reset and buffer made with flip flops bin SIME all f 24 Simulate IP with all the scripts at 24 MHz in batch mode IP has an asynchronous reset and buffer made with flip flops 8 2 RESULTS The IP is provided with the simulation results for the 3 buffer types the 2 reset types the 4 script files and 2 frequencies 10 and 24 MHz generating 48 log files stored in zzlog ref directory The name of a log file is built as described below Script name s frequency log The BATCH command located in simenv1 allows to run all the simulations described above A chkvslog perl procedure is provided in bin and checks the errors and warnings in the log files The initial error at 0 ps are removed for ACTEL AX Ram An AA summaty txt file is created that gives the number of errors No errors are reported in the provided files EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eur1553 Edition 0 R v 01 Date 2009 10 23 Page 29 37 9 SYNTHESIS OF THE RT53EUR IP TO DIFFERENT TECHNOLOGY 9 1 METHO
20. com 1155 Formal port rfdb declared in blkmemdp v6 3 is not in the component declaration Warning 8 source sram xilinx vhd 121 vcom 1155 Formal port douta declared in blkmemdp v6 3 is not in the component declaration warning is also issued when running It is normal Warning 8 tbe pack emu gene vhd 292 vcom 1009 Implicit amp operator uses 1993 rules when computing actual for formal s of subprogram print The simulation of the IP is made in simenv1 directory It 15 run with the SIME perl procedure bin SIME options reference testbench reference script configuration H options help detailed help ref reference simulations batch mode and save the log files in zzlog ref f xxx force IP frequency to 10 12 24 MHz if omitted the frequency used for the previous simulation is used since EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eur1553 Edition 0 R v 01 Date 2009 10 23 Page 28 37 it is stored in the freq file Quarantine buffer is made with ACTEL AX memories default flop ramxi Quarantine buffer is made with XILINX VIRTEX memories default flip flop syncrst Synchronous reset default asynchronous arguments reference script name of the script or ALL for example bin SIME msg nominall 24 Simulate IP with msg nominall script at 24 MHz in interactive mode IP h
21. d Recovery Field Programmable Gate Array Geosynchronous Equatorial Orbit Input Output Identification Initial Design Review Specification Requirement Review Institute of Electrical and Electronics Engineers Intellectual Property Invitation To Tender Joint Test Action Group refer to IEEE std 1149 1 Low Earth Orbit Linear Energy Transfer Layout Versus Schematic Printed Circuit Board PDF PDR PID PRT RT SCC SCoC SEE SEL SEP SET SEU SOC SRAM SRR SRT TC TID TM TRP VHDL VLSI VTP WP Ref R amp D E53 NT 1206 V ASTR Edition 0 R v 01 Date 2009 10 23 Page 8 37 Portable Document Format Preliminary Design Review Process Identification Document Packet Remote Terminal Reference Document 1533 Remote Terminal Space Components Co ordination group Spacecraft Controller on a Chip Single Event Effect or SEP Single Event Phenomena Single Event Latch up see SEE Single Event Transient Single Event Upset System On a Chip Static Random Access Memory Specification Requirement Review Initial Design Review Simple Remote Terminal TeleCommand Total Integrated Dose TeleMetry Technological Research Programme VHSIC Hardware Description Language IEEE standard 1076 Very Large Scale Integration component Validation Test Plan Standard 1553B Test Plan for Remote Terminal Work Package World Wide Web EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR
22. de outside the IP since it 15 sometimes required to separate the clock trees for example in case of scan insertion with some CAD tools The uset shall add an inverted before the pin as depicted The 1553 IF shall be connected to the input and output buffers of the ASIC or the FPGA driving the interface to the 1553 transceiver According to the type of your Transceiver Schmit or Harris the BUSLEVEL pin shall be defined refer to AD10 In order to have a symmetric signal it is important to route identically the and TXBi signals to get almost identical rise and fall times Refer to your Transceiver data sheet The application interface of the RT53eur IP is provided with split busses tri state output buffers have their enable signal provided and bidirectional pins are split in 3 in out and control The user shall connect the tri state and bidirectional buffers are shown in Figure 3 EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Edition O Rev 01 E u rl 2 2 3 Date 2009 10 23 Page 19 37 5 2 CONFIGURING THE IP CORE set of configuration signals is used to configure the IP They are described in the RT53eur IP Core DataSheet AD10 The configurations signals must be static either driven by external pins or forced in the VHDL code But they shall be defined at reset as explained in AD 10 These signals are select an Harris or Schmitt Transceiver Broadcast Enable w
23. disabled e All exchanges declared valid by setting ILLENAB in configuration register 1 e All characterization word are initialized in direct mode For each message a pseudo aleatoty subaddress ranging from 1 to 30 15 used Frames R send 32 receive messages e Send 22 messages with word count from 1 to 32 but not in sequence Check correctness of each exchange Frames send 32 transmit messages Send 22 messages with word count from 1 to 32 but not in sequence Check correctness of each exchange Frames send 32 broadcast messages e Send 22 messages with word count from 1 to 32 but not in sequence Check correctness of each exchange 7 2 3 test allwc indirect EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR EADS um Eur1553 Edition 0 R v 01 ol ee Date 2009 10 23 Page 26 37 General configuration of the test All IT unmasked except Tiover Endmsg e exchanges declared valid by setting ILLENAB in configuration register 1 All characterization word are initialized in indirect mode e For each message a pseudo aleatory subaddress ranging from 1 to 30 is used Same tests as allwc direct but in indirect mode 7 2 4 test allwc stacked General configuration of the test AIL IT unmasked except Tiover Endmsg e All exchanges declared valid by setting ILLENAB in configuration register 1 All characterization word are initialized in
24. e 2009 10 23 Page 16 37 42 THE IP MODEL DESCRIPTION The IP model structure 15 depicted in Figure 3 The user has to define the RT53eur core by selecting the following options e The RT53eur core that can have a synchronous an asynchronous reset e The quarantine buffer which can be made with flip flops ACTEL AX memories or XILINX Virtex memories FPGA or ASIC RTS53EUR ME ahis it 32w x 16b Quarantine buffer CSREG X X CSREG Bs 0i0 C CSREADYN 45 40 CSREADYN carn cHansn en m RW eS p eq RW BER lt Z LH T eee m DATAOUT 15 0 eq T E RXO RXO DATAIN 15 0 lt 47 X DATA 15 0 RXOB iom um lE ae NN RXOB Cuz 380 DATACOUT 5 0 eq lt lt lt lt L Es EE DATACIN 5 0 X DATAC 5 0 0 TXO a gt m lt M lt ENS TXOB DATAEN x g m g pe TXOINH TXOINH o ADOUT 15 0 L8 17 ADIN 15 0 X 4 M AD 15 0 E paies NT RX1B RX1B 2259 L EMEN EN SERAN 18 SERAN TX1B TX1B F SYNON LE re ee 9 gr 8 BN a is o UM 2 Ane INT x X INT 2 uzzszGQgLt 2 HO a O x EFES SS M SSFB X X SSFB D 9 aa BU EM
25. g nominal direct General configuration of the test e Current testbench e Characterization legalizes subaddtess tested Frame 10 Receive message in DIRECT mode e Direct mode is defined in characterization word e Senda 1553 message with reception of 2 data e Check the status emission Frame 20 Transmit message in DIRECT mode e Direct mode is defined in characterization word e Senda 1553 message with transmission of 2 data e Check the status emission Frame 30 Receive message in INDIRECT mode e Direct mode is defined in characterization word e Senda 1553 message with reception of 2 data e Check the status emission Frame 40 Transmit message in INDIRECT mode e Direct mode is defined in characterization word e Senda 1553 message with transmission of 2 data EADS Astrium SAS EADS Eur1553 ec Er iLI mi Hef R amp D E53 NT 1206 V ASTR Edition O 01 Date 2009 10 23 e Check the status emission Frame 50 Receive message in STACKED mode e Direct mode is defined in characterization word Senda 1553 message with reception of 2 data e Check the status emission Frame 60 Transmit message in STACKED mode e Direct mode is defined in characterization word Senda 1553 message with transmission of 2 data e Check the status emission 7 2 2 test allwc direct Page 25 37 General configuration of the test All IT unmasked except Endmsg RTC
26. hen set to 1 broadcast is allowed can also be configured by using BREN RT53eur IP register Time Out selection for an RT to RT exchange TIMEOUT 07 31 us 17 14 us LIEN Signal for loop function inhibition TXEN N Signal for encoder output inhibition TSTES Selection of Fail Safe test mode i e test of the 800 us inhibition timeout shall be set to Zero DYNREG Enable the dynamic load configuration register by the 1553 bus SCANMODE Shall be set to zero or possibly connected to the SCANMODE signal of the ASIC Figure 4 configuration signals of RT53eur IP see AD10 EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eur1553 Edition 0 R v 01 Date 2009 10 23 Page 20 37 6 THE TESTBENCH OF THE RT53EUR IP CORE 61 TESTBENCH OVERVIEW The ASIC testbench is written in full VHDL 93 It is depicted in Figure 5 It is composed of the following modules either used for stimuli s generation or for checking e The RT53eur IP core embedded in a wrapper that includes the IO buffers e Two 1553B emulators modelizing two 1553B Bus controller that are used to generate commands to generate data words and to check transmitted data and status e A memory model connected to the application interface of RT53eur IP This memory can be initialized by reading a file e An Environment emulator that is connected to the application bus as the memory It contains an arbiter that 15 able to g
27. oint core ifa ctl FirstStackPointer reg 0 Q reg rising edge triggered flip flop clocked by CK Path Group CK Path Type max Des Clust Port Wire Load Model Library EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eur1553 Edition 0 R v 01 Date 2009 10 23 Page 34 37 RT53eur 46KG ATC18RHA CELL slow 1p65v 145 Point Incr Path clock CK rise edge 0 00 0 00 clock network delay propagateg 0 00 0 00 core ifa edacc DataInR reg 2 0 reg cp hdfcrb1 0 00 amp 0 00 x core ifa edacc DataInR reg 2 0 reg qn hdfcrb1 Led t 12 r Us3 74 72 xr02dl 0 56 1 69 T U5619 z xr03d1 0 55 Zu XE U5618 z xr03d1 0 58 2 01 X U4986 zn nr02d1 0 35 3 16 dE U3324 zn aoi21d1l Dol 3457 U4782 zn invOd0 0 67 4 34 f U5022 zn nr03d1 0 70 5 04 r U3321 zn ao1321dl 0 40 5 45 f U5024 zn 21141 0 51 5 95 r U4974 zn inv0d0 0 47 6 42 U3319 zn 21141 0 29 6 71 r U4787 zn invOdO 0 66 7 38 f U4568 zn 131191 1 08 8 46 r U4783 zn invOd1l 0 72 9 18 U3184 zn 0 121191 0 59 9 77 U4784 zn invOdO 0 63 10 41 f U4796 zn 31141 0 93 10 94 U3177 zn 121 1 Dod 11426 U4781 zn invOdO 0 98 12 24 r U5005 z an03d1 1 20 13 44 r U4582 zn invOd1l 1 12 14 56 f U2731 zn oai22d1 0 50 15 05 core ifa ctl FirstStackPointer reg 0 0 reg d hdfcrb1 0 00 15 05 r data arrival time 1505 clock CK rise edge 32 00 32 00 clock network delay propagated 0 00 32 00 core ifa
28. rant the bus to the IP It 15 able to read and check the ASIC register and to read and check memory content All the emulators are able to read a script file that contains generation and check commands The memory of the application interface can be initialized by a file which is needed to define the characterization data for example The testbench is auto verifier By searching ERROR string in the log file the correctness of the response can be verified frequency Init file 7 generics l k Emu Rame Application DATA amp DATAC AD RT53EUR WRAPPER DMAREQN BUSBUSY Arbiter DMAACKN CSREGN RWREG Reg I F TROKN IT BREN SELCK TIMEOUT RTAD DYNREG RTPARITY SSFB LTEN_N EMUENV SREQ RESETN Configuration Figure 5 RTEURS53 testbench structure EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eur1553 Edition 0 R v 01 Date 2009 10 23 Page 21 37 62 THE EMULATOR COMMANDS 6 2 1 Introduction Each emulator has a set of commands allowing to define and check signals The commands are listed in the present section The scripts located in the scripte directory provide many examples of their usage 6 2 2 Synchronisation commands The following commands are used to synchronize the 3 emulators and to visualize signals WAIT T time Function wait for time before re
29. rface RESETN CLK CONFIGURATION PINS Figure 1 RT53eur IP functional description The RT53eur IP block diagram is depicted in Erreur Source du renvoi introuvable It can be functionally divided in 2 parts the 1553B interface and the Application Interface The RT53eur IP contains the following functions e Anominal and a redundant Manchester decoder e Anominal and a redundant Manchester encoder e A redundancy management function protocol management function e An application management function EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eur1553 Edition 0 R v 01 Date 2009 10 23 Page 14 37 EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR EADS d 155 3 Edition 0 R v 01 Date 2009 10 23 Page 15 37 rm RT53EC 1553 BREN DYNREG DMAACK RXO FSM amp DMAREQ r RXOB Management BUSBUSY CSREG RWREG TXO CSREADYN TXOB TXOINH Registers CSN CSN EN RW RW EN DATAOUT 15 0 DATAIN 15 0 DATACOUT 5 0 DATACIN 5 0 DATAEN Legali ADOUT 15 0 TX1B zation ADIN 15 0 AD_EN TX1INH Quarantine Meo Buffer SER 32wx16b SYNCN TROKN RESETRTN INT SSFB SREQ RX1 RX1B TX1 TSTFS SCAMODE RESETN SELCK 2 0 Figure 2 RT53eur IP block diagram EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eur1553 Edition 0 R v 01 Dat
30. stacked mode For each message a pseudo aleatoty subaddress ranging from 1 to 30 15 used Same tests as allwc direct but in stacked mode EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eur1553 Edition 0 R v 01 Date 2009 10 23 Page 27 37 8 COMPILING AND SIMULATING THE IP 8 1 PROCEDURE Simulation and compilation are only given for Modelsim simulator The compilation of the IP is made in the simenv1 directory The compilation of the IP is made by executing bin MAKE bin MAKETB Warnings are issued when compiling the xilinx models They are normal since the configuration provided by Xilinx does not contain the entity declaration Warning 8 source sram_xilinx vhd 121 vcom 1155 Formal port dinb declared in blkmemdp v6 3 is not in the component declaration Warning 8 source sram xilinx vhd 121 vcom 1155 Formal port ena declared in blkmemdp v6 3 is not in the component declaration Warning 8 source sram xilinx vhd 121 vcom 1155 Formal port enb declared in blkmemdp v6 3 is not in the component declaration Warning 8 source sram_xilinx vhd 121 vcom 1155 Formal port web declared in blkmemdp v6 3 is not in the component declaration Cie Warning 8 source sram_xilinx vhd 121 vcom 1155 Formal port rfda declared in blkmemdp v6 3 is not in the component declaration Warning 8 source sram xilinx vhd 121 v
31. ta shall be equal to exp_data syntax REG_READ hex hex REG WRITE addtess data Function performs a write in an ASIC register syntax REG_WRITE hex hex RAM READ addtess exp data Function performs a read in an the application memory read data shall be equal to exp_data syntax RAM_READ hex hex RAM WRITE address data Function performs a write in the application memory syntax RAM WRITE hex hex CHECK TROKN tmax check that TROKN signal rise before tmax syntax CHECK TROKN time VALUE SIGNAL VAL Function Set the value of the signal SIGNAL at VAL hex syntax VALUE str hex VALUE AFTER SIGNAL VAL TIME Function Set the value of the signal SIGNAL at VAL hex after time TIME syntax VALUE AFTER str hex time ECHO MESSAGE Function print a message in the log file of the simulator MESSAGE string to print syntax ECHO str EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eur1553 Edition 0 R v 01 Date 2009 10 23 Page 24 37 7 THE SCRIPT FILES DELIVERED WITH THE IP 71 INTRODUCTION The whole simulation plan of the RT53eur IP core is not delivered since it requires a more complex testbench to be used The IP is provided with 4 scripts that are e msg nominal direct basic exchanges allwc ditect all word count in direct mode allwc indirect all word count in indirect mode allwcc stacked all word cound in stacked mode 7 2 DECRIPTION OF THE SCRIPTS 7 21 ms
32. tor Word Data Word provided by the Remote Terminal subsequent to the Status Word in answer to a Mode Command Transmit Vector Word Bit Order The most significant bit shall be transmitted first with the less significant bits following in descending order of value in the Data Word Redundant Bus The redundant data bus implements a particular approach for obtaining multiple data paths to improve message arrival probability Bus Switching When an RT is receiving or operating on a message on one bus and another valid legal command to the RT occurs on the opposite bus later in time When an RT is processing a command a second valid command word sent to an RT shall take precedence over the previous command After the Transmit Command Superseeding Command minimum intermessage gap time has been exceeded the RT shall respond to the second valid command when it is not transmitting on that data bus EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eur1553 Edition 0 R v 01 Date 2009 10 23 Page 10 37 2 4 CONVENTIONS 2 4 1 numbering Bit n 0 refers to LEAST Significant Bit LSB Bit n 15 refers to MOST Significant Bit MSB For 1553 interface as given in RD4 the Bit 15 MSB in registers corresponds to the 4 bit of a 1553 word 2 4 2 DATA entity Word refers to 16 Bits data entity Byte refers to 8 Bits data entity BIT1 BITO indicates value binary coded in TO BI
33. ulating the IP e The gen_lib directory contains the source code of the generic library used to generate the generic netlist e The synplify_ax2000 provides an example of synthesis of the IP in ACTEL AX technology e The synplify_virtex provides an example of synthesis of the IP in Xilinx Virtex technology The synop_atcl8rha provides an example of the synthesis of the IP in ATMEL ATCI8RHA technology The gen ram actel is provided for information it is the result of the generation of the ACTEL ram by smartgen e The gen_ram_xilinx is provided for information it is the result of the generation of the XILINX tam by EADS Astrium SAS Ref R amp D E53 NT 1206 V ASTR Eur1553 Edition 0 R v 01 Date 2009 10 23 Page 13 37 4 DESCRIPTION OF RT53EUR IP 41 ENVIRONMENT The RT53eur IP is a 1553B Remote Terminal When used in nominal and redundant mode it is connected to the 1553B bus with the following elements as depicted in Figure 1 e Two single 1553B Transceivers a dual 1553B Transceiver e Two 1553 Transformers stable oscillator that delivers the IP clock frequency Nominal 1553B Bus FPGA or ASIC Redundant 1553B Bus RXO Transformer Transceiver mm d 3 RT53EUR TXOINH CORE TXOB RX1 RX1B WW ES gt IX4 TX1INH TX1B Transformer Transceiver Application Inte
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