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Datasheet - STMicroelectronics

1. Reset block XTAL 1 16 MHz Clock controller Reset Reset RCint 16 MHz Detector POR BOR a RCint 128 kHz Clock to peripherals and core L T Window STM8 WDG core Independent WDG SC eer Debug SWIM 8 Kbytes ebug interf Program Flash 640 bytes lt gt data EEPROM 3 a 400 Kbit s GC gt S 1 Kbyte 3 RAM o c o 8 Mbit s SPI 5 o lt Up to 4 CAPCOM liN mast r 1 16 bit advanced SE SPI emul UART1 control timer TM1 p ry outputs CE 16 bit general purpose c Up to 3 CAPCOM Timer TIM5 channels Unie 8 bit basic timer p to TIM6 channels ADCI i 1 2 4 kHz Beeper AWU timer beep MSv37453V1 ky DocID15590 Rev 10 11 121 Product overview STM8S903K3 STM8S903F3 4 4 1 12 121 Product overview The following section provides an overview of the basic features of the device functional modules and peripherals For more detailed information please refer to the corresponding family reference manual RM0016 Central processing unit STM8 The 8 bit STM8 core is designed for code efficiency and performance It contains 6 internal registers which are directly address
2. Address Block Register label Register name Reset status 0x00 50C3 CLK_CMSR Clock master status register OXE1 0x00 50C4 CLK_SWR Clock master switch register OxE1 0x00 50C5 CLK SWCR Clock switch control register OxXX 0x00 50C6 CLK CKDIVR Clock divider register 0x18 0x00 50C7 CLK PCKENR1 dis clock gating OxFF 0x00 50C8 CLK CLK CSSR Clock security system register 0x00 0x00 50C9 CLK CCOR a clock control Jean 0x00 50CA CLK_PCKENR2 SE clock gating OxFF 0x00 50CC CLK HSITRIMR En calibration trimming geng 0x00 50CD CLK_SWIMCCR SWIM clock control register ObXXXX XXX0 0x00 50CE to 0x00 50DO Reserved area 3 bytes 0x00 50D1 WWDG CR WWDG control register Ox7F WWDG 0x00 50D2 WWDG WR WWDR window register Ox7F 0x00 50D3 to 00 50DF Reserved area 13 bytes 0x00 50E0 IWDG KR IWDG key register 0xxx 0x00 50E1 IWDG IWDG PR IWDG prescaler register 0x00 0x00 50E2 IWDG RLR IWDG reload register OxFF 0x00 50E3 to 0x00 50EF Reserved area 13 bytes 0x00 50F0 AWU CSR1 AWU control status register 1 0x00 0x00 50F1 AUI AWU APR Mises a prescaler Gap 0x00 50F2 AWU TBR Eu selection 0x00 0x00 50F3 BEEP BEEP_CSR BEEP control status register 0x1F 0x00 50F4 to 0x00 50FF Reserved area 12 bytes 0x00 5200 SPI_CR1 SPI control register 1 0x00 0x00 5201 SPI_CR2 SPI control register 2 0x00 0x00 5202 SPI ICR SPI interrupt control register 0x00 0x00 5203 SPI SR SPI statu
3. Vpp STM8A Ee SE Rswitch AIN AINx xX VAINJ NNNN ee P Ts conversion nalo Cain K Vt alla SC LA 0 6V O IL Csamp 1 d Legend Ran external resistance Cam capacitors Csamp internal sample and hold capacitor DoclD15590 Rev 10 85 121 Electrical characteristics STM8S903K3 STM8S903F3 10 3 11 86 121 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization Functional EMS electromagnetic susceptibility While executing a simple application toggling 2 LEDs through UO ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs e ESD Electrostatic discharge positive and negative is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 61000 4 2 standard e FTB A burst of fast transient voltage positive and negative is applied to Vpp and Vss through a 100 pF capacitor until a functional disturbance occurs This test conforms with the IEC 61000 4 4 standard A device reset allows normal operations to be resumed The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 EMC design guide for STM microcontrollers Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a
4. In addition STice offers in circuit debugging and programming of STM8 microcontrollers via the STMB8 single wire interface module SWIM which allows non intrusive debugging of an application while it runs on the target microcontroller For improved cost effectiveness STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers STice key features e Occurrence and time profiling and code coverage new features e Advanced breakpoints with up to 4 levels of conditions e Data breakpoints e Program and data trace recording up to 128 KB records e Read write on the fly of memory during emulation e In circuit debugging programming via SWIM protocol e 8 bit probe analyzer e 1 input and 2 output triggers e Power supply follower managing application voltages between 1 62 to 5 5 V e Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements e Supported by free software tools that include integrated development environment IDE programming software interface and assembler for STM8 DoclD15590 Rev 10 113 121 STM8 development tools STM8S903K3 STM8S903F3 14 2 14 2 1 14 2 2 114 121 Software tools STM8 development tools are supported by a complete free software package from STMicroelec
5. PIN 1 Identifier A0B8_ME_V2 1 Drawing is not to scale DoclD15590 Rev 10 d STM8S903K3 STM8S903F3 Package information Table 55 UFQFPN32 32 pin 5x5 mm 0 5 mm pitch ultra thin fine pitch quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 0 500 0 550 0 600 0 0197 0 0217 0 0236 A1 0 000 0 020 0 050 0 0000 0 0008 0 0020 A3 0 152 0 0060 0 180 0 230 0 280 0 0071 0 0091 0 0110 D 4 900 5 000 5 100 0 1929 0 1969 0 2008 D1 3 400 3 500 3 600 0 1339 0 1378 0 1417 D2 3 400 3 500 3 600 0 1339 0 1378 0 1417 E 4 900 5 000 5 100 0 1929 0 1969 0 2008 E1 3 400 3 500 3 600 0 1339 0 1378 0 1417 E2 3 400 3 500 3 600 0 1339 0 1378 0 1417 e 0 500 0 0197 L 0 300 0 400 0 500 0 0118 0 0157 0 0197 ddd 0 080 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits Figure 49 UFQFPN32 32 pin 5x5 mm 0 5 mm pitch ultra thin fine pitch quad flat package recommended footprint 5 30 gt a 3 80 gt B d HOO Hes KJ El 4 L1 L1 L1 L1 5 30 LI 3 80 L1 L1 Oo 3 ox LO Y ii a CJ CJ 3 3 80 A0B8 FP V2 1 Dimensions are expressed in millimeters Section 11 7 UFQFPN recommended footprint shows the recommended footprints for UFQFPN with and without on board emulation a DoclD15590 Rev 10 93 121 P
6. 0x00 8068 Peserved 0x00 806C to 0x00 807C 1 Except PA1 44 121 DoclD15590 Rev 10 Ly STM8S903K3 STM8S903F3 Option bytes 8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device They are stored in a dedicated block of the memory Except for the ROP read out protection byte each option byte has to be stored twice in a regular form OPTx and a complemented one NOPTx for redundancy Option bytes can be modified in ICP mode via SWIM by accessing the EEPROM address shown in the table below Option bytes can also be modified on the fly by the application in IAP mode except the ROP option that can only be modified in ICP mode via SWIM Refer to the STM8S Flash programming manual PM0051 and STM8 SWIM communication protocol and debug module user manual UM0470 for information on SWIM programming procedures Table 11 Option bytes Option Option bits Factory Addr n byte default no 7 6 5 4 3 2 1 0 setting Read out 0x4800 protection OPTO ROP 7 0 0x00 ROP 0x4801 Userboot OPT1 UBC 7 0 0x00 code 0x4802 yBc NOPT1 NUBC 7 0 OxFF 0x4803 Alternate OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFRO 0x00 function 0x4804 SC D NOPT2 bagi deg Eum NAFR4 NAFR3 NAFR2 NAFR1 NAFRO OxFF HSI LSI IWDG WWDG WWDG 0x4805h aise OPT3 Res
7. DoclD15590 Rev 10 d STM8S903K3 STM8S903F3 Package information 11 Package information In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark 11 1 LQFP32 package information Figure 45 LQFP2 package outline SEATING PLANE DEET Ede Fel nT SOIC ey T Ke 0 25 mm GAUGE PLANE 5V_ME_V2 DoclD15590 Rev 10 89 121 d Package information STM85903K3 STM8S903F3 90 121 Table 54 LOFP32 package mechanical data mm inches Dim Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 300 0 370 0 450 0 0118 0 0146 0 0177 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 600 0 2205 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 600 0 2205 e 0 800 0 0315 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 5 7 0 0 0 3 5 7 0 ccc
8. HSE user ext clock fepu fMASTER 16 MHz 16 MHz 4 3 4 75 Supply current in HSI RC osc 16 MHz 3 7 4 5 IDD RUN ko i fopu fmasteR 2 MHz HSI RC osc 16 MHz 8 0 84 1 05 mA executed fcPu fuasrER 128 125 kHz HSI RC osc 16 MHz 0 72 0 9 from Flash f Se 128 CPU 7 IMASTER HSI RC 16 MHz 8 E 0 58 15 625 kHz ceo eee e fopu fMaster 128 kHz LSI RC osc 128 kHz 0 42 0 57 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off Table 24 Total current consumption with code execution in run mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 1 8 HSE user ext clock fepy MASTER 16 MHz 16 MHz 2 2 35 Supply HSI RC osc 16 MHz 1 5 2 current in l Run mode HSE user ext clock 0 81 e DD RUN code fopu fuAsrER 128 125 kHz 16 MHz executed HSI RC osc 16 MHz 0 7 0 87 from RAM fopu fmasTER 128 15 625 kHz HSI RC osc 16 MHz 8 0 46 0 58 fcpu fuasrER 128 kHz LSI RC osc 128 kHz 0 41 0 55 HSE crystal osc 16 MHz 4 HSE user ext clock fepy fMASTER 16 MHz 16 MHz 3 9 4 7 Supply current in HSI RC osc 16 MHz 3 7 4 5 eege oe fopu fuAsrER 2 MHz HSI RC osc 16 MHz 8 0 84 1 05 mA executed fopy faster 128 125 kHz HSI RC osc 16 MHz 0 72 0 9 from Flash f s 128 CPU 7 MASTER 15 625 kHz HSI RC osc 16 MHz 8 0 46 0 58 fcpPu fuasrER 128 kHz L
9. 5 V 20 20 factory calibrated 25 C lt Tas 85 C 2 95 V lt Vpps 5 5v 3 3 40 C x Ta lt 125 C K O ao HSI oscillator wakeup 2 su HS time including calibration de HS HSI oscillator power IDD HSI consumption g 170 250 pA 1 Refer to application note 2 Guaranteed by design not tested in production 3 Data based on characterization results not tested in production Figure 20 Typical HSI frequency variation vs Vpp 4 temperatures 140086 0 5086 0 00 HE accuracy 100 1 5086 Kl e 35 4 4 5 5 5 5 d 68 121 DoclD15590 Rev 10 STM8S903K3 STM8S903F3 Electrical characteristics d Low speed internal RC oscillator LSI Subject to general operating conditions for Vpp and Ta Table 37 LSI oscillator characteristics Symbol fi si Parameter Conditions Min Typ Max Frequency 110 128 150 Unit kHz tsu Lsi LSI oscillator wakeup time 7 us IDD LSI LSI oscillator power consumption 5 pA Figure 21 Typical LSI frequency variation vs Vpp 4 temperatures 5 00 400 3 00 200 1 00 0 00 acouracy 1 00 200 3 00 400 5 00 DoclD15590 Rev 10 69 121 Electrical characteristics STM8S903K3 STM8S903F3 10 3 5 70 121 Memory characteristics RAM and hardware registers Table 38 RAM and hardware registers
10. Symbol Conditions Min Typ Max Unit VIL NRST NRST input low level voltage 0 3 0 3 x Vpp Vuen NRST input high level voltage oz 2mA O07xVpp Vpp 0 3 V VOL NRST NRST output low level voltage log 7 3 MA 0 5 Rpeynrst NRST pull up resistor 30 55 80 kQ tirp nrRst NRST input filtered pulse 75 tinep vRst NRST Input not filtered pulse 500 ns top NRsT NRST output pulse 20 us 1 Data based on characterization results not tested in production 2 The Rpy pull up equivalent resistor is based on a resistive transistor 3 Data guaranteed by design not tested in production Figure 35 Typical NRST Vj and Vj vs Vpp 4 temperatures Mus ay DoclD15590 Rev 10 d STM85903K3 STM85903F3 Electrical characteristics Figure 36 Typical NRST pull up resistance Rpy vs Vpp 4 temperatures NRESET pull up esitarce ko VM Figure 37 Typical NRST pull up current lj vs Vpp 4 temperatures NRESET Pull Lip current The reset network shown in Figure 38 protects the device against parasitic resets The user must ensure that the level on the NRST pin can go below Vi men max see Table 44 NRST pin characteristics otherwise the reset is not taken into account internally For power consumption sensitive applications the external reset capacitor value can be reduced to limit the charge discharge current If NRST signal is used to
11. fe life augmented STM8S903K3 STM8S903F3 16 MHz STM8S 8 bit MCU up to 8 Kbytes Flash 1 Kbyte RAM 640 bytes EEPROM 10 bit ADC 2 timers UART SPI PC Features Core e 16 MHz advanced STMB8 core with Harvard architecture and 3 stage pipeline e Extended instruction set Memories e Program memory 8 Kbytes Flash data retention 20 years at 55 C after 10 kcycles e Data memory 640 bytes true data EEPROM endurance 300 kcycles e RAM 1 Kbytes Clock reset and supply management e 2 95 to 5 5 V operating voltage e Flexible clock control 4 master clock sources Low power crystal resonator oscillator External clock input Internal user trimmable 16 MHz RC Internal low power 128 kHz RC e Clock security system with clock monitor e Power management Low power modes wait active halt halt Switch off peripheral clocks individually e Permanently active low consumption power on and power down reset Interrupt management e Nested interrupt controller with 32 interrupts e Up to 28 external interrupts on 7 vectors Timers e Advanced control timer 16 bit 4 CAPCOM channels 3 complementary outputs dead time insertion and flexible synchronization March 2015 Datasheet production data Y LQFP32 7x7 mm TSSOP20 SO20 UFQFPN20 4 40 mm body 300 mils 3x3mm e 16 bit general purpose timer with 3 CAPCOM channels IC OC or PWM e 8 bit basic timer with 8 bi
12. 0 AFR7 remapping option inactive Default alternate functions 2 1 Port C3 alternate function TIM1_CH1N port C4 alternate function TIM1_CH2N AFR6 Alternate function remapping option 6 0 AFR6 remapping option inactive Default alternate function 2 1 Port D7 alternate function TIM1_CH4 AFR5 Alternate function remapping option 5 0 AFR5 remapping option inactive Default alternate function 2 1 Port DO alternate function CLK CCO AFRA Alternate function remapping option 4 0 AFR4 remapping option inactive Default alternate functions 1 Port B4 alternate function ADC_ETR port B5 alternate function TIM1 BKIN AFR3 Alternate function remapping option 3 0 AFR3 remapping option inactive Default alternate function 2 1 Port C3 alternate function TLI AFR2 Alternate function remapping option 2 0 AFR2 remapping option inactive Default alternate functions 1 Port C4 alternate function AIN2 port D2 alternate function AIN3 port D4 alternate function UART1_CK 2 1 Do not use more than one remapping option in the same port DoclD15590 Rev 10 47 121 Option bytes STM8S903K3 STM8S903F3 48 121 2 Refer to STM8S903K3 pin descriptions Table 14 STM8S903F3 alternate function remapping bits 7 2 for 20 pin packages Option byte no OPT2 Description AFR7 Alternate function remapping option 7 0 AFR7 remapping option inactive Default alternate functions
13. AFR1 0 PB5 I2C SDA 3 Port Timer 1 break 118 tit BKIN ESI ME KEE KA ps data input AFR4 PB4 DC SCL 3 Port ADC external 12 9 5c ETR Or ow X 11T p4 I2C clock trigger AFR4 Top level PC3 Port Timer1 interrupt AFR3 13 10 TIM1 CH3TLI VO X X X HS O3 X X es yer Timer 1 inverted TIM1 CH1N channel 1 AFR7 PC4 Timer 1 Analog input 2 TIM1_CH4 Port channel 4 Weer 14111 ork ccovain YO X X X HS 03 X X o liconfigurable Ge 2 TIM1 CH2 clock output WERT Timer 5 15 12 REA vo X X X HS OS x X dun SPI clock channel 1 AFRO PC6 16 13 SPI MOSI vo X X X HS OS x X GC Geer AER T T TIM1 CH1 SC Port SPI master in Timer 1 channel 17 14 SPI MISO OXI X xX HS oa X 8 lei sve out 2IAFRO TIM1 CH2 Ky DoclD15590 Rev 10 23 121 Pinouts and pin descriptions STM8S903K3 STM8S903F3 Table 5 TSSOP20 SO20 UFQFPN20 pin descriptions continued Input Output c 2 a S 2 2 a c De E a 2 E P Z o0 o0 Set e 2 a oD c2 TS cCEzotc L c S e s c g 2 So Deze 28 g Fl5lalx 5l iss 55 i I a 18 15 Po1 swim vo x x x Hs O4 x x Pot SWIM data e D1 interface Analog input 3 PD2 AIN3 Port AFR2 Timer 19 16 rius CH3 KOPA ee eden A UBE OY KALA ee 7 52 channel 3 AFR1 20 17 TIM5 CH2 UO X X X HS O03 X X D3 channel 2 ADC ADC ETR d external trigger Por Timer 5 4 1
14. L2 0 300 0 350 0 400 0 0118 0 0138 0 0157 Ky DoclD15590 Rev 10 95 121 Package information STM85903K3 STM8S903F3 96 121 Table 56 UFQFPN20 package mechanical data continued mm inches Dim Min Typ Max Min Typ Max L3 0 375 0 0148 L4 0 200 0 0079 L5 0 150 0 0059 b 0 180 0 250 0 300 0 0071 0 0098 0 0118 ddd 0 050 0 0020 1 Values in inches are converted from mm and rounded to 4 decimal digits Section 11 7 UFQFPN recommended footprint shows the recommended footprints for UFQFPN with and without on board emulation Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 52 UFQFPN20 marking example package top view Product identification e Revision code Date code Dot pin 1 MS37476V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity d DoclD15590 Rev 10 STM8S903K3 STM8S903F3 Package information 11 4 SDIP32 package information Figur
15. PB1 AIN1 Timer 1 20115 Tm cHoN lvo X X HS 03 X X Port Bl eed channel 2 Analog input 0 PBO AINO Timer 1 21116 Th CHIN jo X X X HS 03 X X Port BO eee channel 1 PE5 SPI NSS SPImaster slave Timer 1 22 17 TIM1 CHIN VO X X X HS 03 X X Port E5 select inverted channel 4 AFR1 0 um Timer 1 Timer 1 23 18 VO X X X HS 03 X X PortC1 channel 1 inverted channel VARTI COK UART1 clock 2 AFR1 0 TIM1_CH2N i ky DoclD15590 Rev 10 27 121 Pinouts and pin descriptions STM8S903K3 STM8S903F3 Table 6 STM8S903K3 UFQFPN32 LQFP32 SDIP32 pin descriptions continued N Input Output o 5 a EE S Sean SIS 2 SIS ER 25 BET 2 5 Pin name E B EI IT at sS a S T z R 2 a 8 a 5 5 555 JE 5 fiiio sf 35 EBS Sg cl mc D 2 w T B lt Timer 1 24 19 MUNA CHAN vo x X X Hs 03 X X Port C2 n P inverted channel 3 AFR1 0 Top level PC3 Timer 1 interrupt AFR3 25 20 TIM1 CHS TLU VO X X X HS O3 X X Port C3 channel 3 Timer 1 inverted TIM1 CH1N channel 1 AFR7 PC4 Timer 1 Analog input 2 TIM1 CH4 channel 4 AFR2 Timer 1 26 21 lex ccora2 YO X X X HS 03 X X Port C4 ngurable inverted channel TIM1 CH2N clock output 2 AFR7 PC5 SPI SCK Timer 5 channel 27 22 TIM5 CH1 lO X X X HSj O3 X X Pot C5 SPI clock 1 AFRO PC6 SPI MOSI SPI master Ti
16. SO20 mechanical data mm inches Dim Min Typ Max Min Typ Max A 2 350 2 650 0 0925 0 1043 A1 0 100 0 300 0 0039 0 0118 B 0 330 0 510 0 013 0 0201 C 0 230 0 320 0 0091 0 0126 D 12 600 13 000 0 4961 0 5118 E 7 400 7 600 0 2913 0 2992 e 1 270 0 0500 H 10 000 10 650 0 3937 0 4193 h 0 250 0 750 0 0098 0 0295 L 0 400 1 270 0 0157 0 0500 k 0 0 8 0 0 0 8 0 ddd 0 100 0 0039 1 Values in inches are converted from mm and rounded to 4 decimal digits Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Product identification Pin 1 identifier Standard ST logo Figure 59 SO20 marking example package top view Revision code Date code MS37471V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity DoclD15590 Rev 10 Ly STM8S903K3 STM8S903F3 Package information 11 7 UFQFPN recommended footprint Figure 60 UFQFPN recommended fo
17. Symbol VRM Parameter Data retention mode Conditions Halt mode or reset Min ViT max Unit 1 Minimum supply voltage without losing data stored in RAM in halt mode or under reset or in hardware registers only in halt mode Guaranteed by design not tested in production 2 Refer to Section 10 3 Operating conditions for the value of Vir may Flash program memory data EEPROM memory Table 39 Flash program memory data EEPROM memory Symbol Parameter Conditions Min Typ Max Unit Operating voltage VoD all modes execution write erase tepus 16 MHZ si SE E M Standard programming time including erase for byte word block 6 6 6 frog 1 byte 4 bytes 64 bytes Fast programming time for 1 block 3 3 33 ms 64 bytes terase Erase time for 1 block 64 bytes 3 3 33 Data retention program and data memory after 10k erase write cycles Tret 55 C 20 at Taz 55 C tRET year Data retention data memory after 300k erase write cycles at Tret 85 C 1 Taz 125 C Supply current Flash programming or 2 E HA DD erasing for 1 to 128 bytes 1 Data based on characterization results not tested in production DoclD15590 Rev 10 d STM8S903K3 STM8S903F3 Electrical characteristics 10 3 6 UO port pin characteristics General characteristics Subject to general operating conditions for Vpp and Ta
18. TIM1 CH2 OSCOUT PA2 33 13 71 PC6 HS SPI MOSI TIM1 CH1 VSS j4 12 17 PC5 HS SPI SCK TIM5 CH1 VCAP UJ Ei KI ki 5 11 C7 PC4 HS TIM1 CHA CLK CCO AIN2 TIM1 CH2N jo TIM1 BKIN DC SDA T PBS Ee ADC_ETR I2C_SCL T PB4 o TIM4 CH1N TLI TIM1_CH3 HS PC3 MSv37455V1 1 HS high sink capability 2 T True open drain P buffer and protection diode to VDD not implemented alternate function remapping option if the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function d 22 121 DoclD15590 Rev 10 STM8S903K3 STM8S903F3 Pinouts and pin descriptions 5 3 TSSOP20 SO20 and UFQFPN20 pin descriptions Table 5 TSSOP20 SO20 UFQFPN20 pin descriptions Input Output 2 a S 2 55 S E Ve E a S E s o 0 o0 ZBOEL o 2 o Q o co Iz croc LL c Ss c c o zu TO kO TO 99g S zg lkt las aje g 5S 2555 I a 4 1 NRST VO Ix 1 1 1 Reset 5 2 pavoscin2 vo x x x ot x x Port Resonator A1 crystal in 6 3 paz oscout vo X X x l ot x x Port Resonator A2 crystal out 7 4 VSS Digital ground 8 5 VCAP 1 8V regulator capacitor 9 6 VDD Digital power supply PAS ee TIM5 CH3 Port Timer 52 1017 spr Me jo ae 5 8S 103 XI XE ES a EU UART1 TX
19. 0 100 0 0039 1 Values in inches are converted from mm and rounded to 4 decimal digits Figure 46 LQFP32 recommended footprint NOUNUDOD t SAY A Tix 16 SEO LI ox kA E SIE 610 L Set LI 7 80 q LE 1 8 LLLI HI LES a 6 10 E P m 5V FP V2 1 Dimensions are expressed in millimeters DoclD15590 Rev 10 er STM8S903K3 STM8S903F3 Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 47 LQFP32 marking example package top view Product ec dc T identification Standard ST logo Revision code Pin 1 identifier MS37474V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity d DoclD15590 Rev 10 91 121 Package information STM8S903K3 STM8S903F3 11 2 92 121 UFQFPN32 package information Figure 48 UFQFPN32 32 pin 5x5 mm 0 5 mm pitch ultra thin fine pitch quad flat package outline kA Y e eaa c C SEATING PLANE
20. 0 5 mm pitch ultra thin fine pitch quad flat package mechanical data 93 UFQFPN20 package mechanical data 95 SDIP32 package mechanical data 97 TSSOP20 package mechanical data 99 SO20 mechanical data 102 Thermal characteristics 00000 c cece eee 105 Document revision history 116 DoclD15590 Rev 10 Ly STM8S903K3 STM8S903F3 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Ly STM8S903K3 F3 block diagram 11 Flash memory organization 14 STM8S903F3 TSSOP20 SO20 pinout es 21 STM8S903F3 UFQFPN20 pinout 0 Re 22 STM8S903K3 UFQFPN32 LQFP32 pinout 25 STM8S903K3 SDIP32 pinout 0 20 0 eee 26 Memory map EE EN Pin loading conditions lille Rr 51 Pin input Voltage 2 usce enndem ew acne cer das e enr baad as 52 fep max Versus VD aene sek A Ran RE ERR NINDA GG Acque qn MR RA Rae e A Ro e 55 External capacitor Cer 56 Typ Ipp Ruw VS Vpp
21. 121 Figure 24 Typical pull up resistance vs VDD 4 temperatures 40 25 C 60 85C 55 50 d 125 C Pull up resistance O W 4 4 5 VDD V MS37434V1 Table 41 Output driving current standard ports 1 Symbol Parameter Conditions Min Max Unit Output low level with 8 lio 10 mA i T7 pins sunk Vpp 25V i VoL Output low level with 4 lee 4 mA 4 0 pins sunk Vpp 3 3 V S e Output high level with 8 lio 10 mA 28 i pins sourced Vpp 25V VoH Output high level with 4 lee 4 mA 240 i pins sourced Vpp 3 3 V l Data based on characterization results not tested in production DoclD15590 Rev 10 d STM8S903K3 STM8S903F3 Electrical characteristics Table 42 Output driving current true open drain ports Symbol Parameter Conditions Min Max Unit Output low level with 2 lee 10 mA we pins sunk Vpp 25V VoL Output low level with 2 lio 10 mA i 150 pins sunk Vpp 3 3 V Output high level with 2 lio 10 mA 1 VoH 2 0 pins sourced Vpp 5V 1 Data based on characterization results not tested in production Table 43 Output driving current high sink ports Symbol Parameter Conditions Min Max Unit Output low level with 8 lio 10 mA e pins sunk Vpp25V lio 10 mA VoL 9 ds b 1 0 Output low level with 4 Vpp
22. 4 11 TIM5 16 bit general purpose mer 17 4 12 TIM6 8 bit basic timer 0 00000 ee 18 4 13 Analog to digital converter ADC1 lleessellreesne 18 4 14 Communication interfaces 19 44141 UART esd vend ux e dou KA ERE eR EE Yeahs I De Ree 19 Ang MEE CPP TT 20 KUA c 20 5 Pinouts and pin descriptions eee eee eee 21 5 1 STM8S903F3 TSSOP20 SO20 pinout a 21 5 2 STM8S903F3 UFQFPN20 pinout 0000 cee 22 5 3 TSSOP20 SO20 and UFQFPN20 pin descriptions 23 5 4 STM8S903K3 UFQFPN32 LQFP32 and SDIP32 pinouts 25 5 5 STM85903K3 UFQFPN32 LQFP32 SDIP32 pin descriptions 26 5 6 Alternate function remapping 000 e eee eee eee 30 2 121 DoclD15590 Rev 10 Ly STM8S903K3 STM8S903F3 Contents 10 11 d Memory and register map eee eee 31 6 1 Memory map ns 31 6 2 Register map AA AA AA 32 6 2 1 I O port hardware register map 0c eee 32 6 2 2 General hardware register map 33 6 2 3 CPU SWIM debug module interrupt controller registers 41 Interrupt vector mapping eee II 43 Option bytes Xa REN WE E AEN ERREUR de RR REN EET E ox 45 8 1 Alternate function remapping bis 47 Unique ID s saa aaa KM kun an hk EEN 50 Electrical characteristics eee eee 51 10 4 Parameter conditions 51 10 1 1 Minimum and maximum values 22222 essen 51 10 12 Typical values 51 10 1 3 Typic
23. 4 Iemperatures nananana aunan 7T Typical NRST pull up current lp vs Vpp 4 temperatures a 77 Recommended reset pin protection llli 78 SPI timing diagram where slave mode and CPHA 0 22200200 eee ees 80 SPI timing diagram where slave mode and CPHA 1 220202000 ee eee 80 SPI timing diagram master mode 81 Typical application with DC bus and timing diagram 82 ADC accuracy characteristics 0 0 eee 85 Typical application with ADC 000 222 85 LQFP2 package outline 89 LQFP32 recommended footprint 90 LQFP32 marking example package top view 91 UFQFPN32 32 pin 5x5 mm 0 5 mm pitch ultra thin fine pitch quad flat DoclD15590 Rev 10 7 121 List of figures STM85903K3 STM8S903F3 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 8 121 package outline NEE ENN KANG AG Iw rh Da RUE EEN ee es 92 UFQFPN32 32 pin 5x5 mm 0 5 mm pitch ultra thin fine pitch quad flat package recommended footprint 93 UFQFPN32 marking example package top view 94 UFQFPN20 package outline RII 95 UFQFPN20 marking example package top view 96 SDIP32 package outline lilii II 97 SDIP32 marking example package top view 98 TSSOP20 package outline 2l 99 TSSOP20 recommended package footprint 20 0 eee ee eee 100 TSSOP20 ma
24. 7F8F Reserved area 15 bytes d DoclD15590 Rev 10 41 121 Memory and register map STM8S903K3 STM85903F3 Table 9 CPU SWIM debug module interrupt controller registers continued Address Block Register label Register name nesel status 0x00 7F90 DM BKIRE DM breakpoint 1 register OxEE extended byte 0x00 7F91 DM BK1RH DM breakpoint 1 register ees high byte 0x00 7F92 DM BK1RL DM breakpoint 1 register eebe x low byte 0x00 7F93 DM BK2RE DM breakpoint 2 register ayer extended byte 0x00 7F94 DM_BK2RH DM breakpoint 2 register ayer high byte 0x00 7F95 DM DM BK2RL DM breakpoint 2 register OxFF low byte 0x00 7F96 DM CR1 DM debug module control 0x00 register 1 0x00 7F97 DM CR2 DM debug module control 0x00 register 2 0x00 7F98 DM CSR1 DM debug module 0x10 a control status register 1 0x00 7F99 DM_CSR2 DM debug module 0x00 control status register 2 0x00 7F9A DM ENFCTR DM enable function register OXFF 0x00 7F9B to 0x00 7F9F Reserved area 5 bytes 1 Accessible by debug module only d 42 121 DoclD15590 Rev 10 STM8S903K3 STM8S903F3 Interrupt vector mapping 7 Interrupt vector mapping Table 10 Interrupt mapping PHAT Wakeup from Wakeup from IRQ no Source block Description halt mode a tive halt mode Vector address
25. B PB DDR Port B data direction register 0x00 0x00 5008 PB CR1 Port B control register 1 0x00 0x00 5009 PB CR2 Port B control register 2 0x00 0x00 500A PC ODR Port C data output latch register 0x00 0x00 500B PB IDR Port C input pin value register 0xxx 0x00 500C Port C PC DDR Port C data direction register 0x00 0x00 500D PC CR1 Port C control register 1 0x00 0x00 500E PC CR2 Port C control register 2 0x00 0x00 500F PD ODR Port D data output latch register 0x00 0x00 5010 PD IDR Port D input pin value register Oxxx 0x00 5011 Port D PD_DDR Port D data direction register 0x00 0x00 5012 PD CR1 Port D control register 1 0x02 0x00 5013 PD CR2 Port D control register 2 0x00 0x00 5014 PE ODR Port E data output latch register 0x00 0x00 5015 PE IDR Port E input pin value register 0xxx 0x00 5016 Port E PE DDR Port E data direction register 0x00 0x00 5017 PE CR1 Port E control register 1 0x00 0x00 5018 PE CR2 Port E control register 2 0x00 0x00 5019 PF ODR Port F data output latch register 0x00 0x00 501A PF IDR Port F input pin value register 0xxx 0x00 501B Port F PF DDR Port F data direction register 0x00 0x00 501C PF CR1 Port F control register 1 0x00 0x00 501D PF CR2 Port F control register 2 0x00 1 Depends on the external circuitry d 32 121 DoclD15590 Rev 10 STM8S903K3 STM8S903F3 Memory and register map 6 2 2 General hardware register map Table 8 General hardware register map Address 0x00 501E
26. C W TJmax 75 C 60 C W x 464 mW 75 C 27 8 C 102 8 C This is within the range of the suffix 6 version parts 40 lt Ty lt 105 C Parts must be ordered at least with the temperature range suffix 6 d DoclD15590 Rev 10 STM8S903K3 STM8S903F3 Ordering information 13 d Ordering information Figure 62 STM8S903K3 F3 access line ordering information scheme Example STM8 Product class STMB8 microcontroller Family type S S Standard Sub family type 903 K 903 903 sub family Pin count K 32 pins F 20 pins Program memory size 3 8 Kbytes Package type 3 T 6 C TR B SDIP T LQFP U VFQFPN P TSSOP M SO Temperature range 3 40 to 125 C 6 40 to 85 C Package pitch Blank 0 5 to 0 65 mm C 0 8 mm Packing No character Tray or tube TR Tape and reel A dedicated ordering information scheme will be released if in the future memory programming service FastROM is required The letter P will be added after STM8S Three unique letters identifying the customer application code will also be visible in the codification Example STM8SP903K3MACTR UFQFPN TSSOP and SO packages LQFP package DoclD15590 Rev 10 107 121 Ordering information STM8S903K3 STM8S903F3 13 1 Note 108 121 For a list of available options for example memory size packa
27. EGR TIM1 event generation 0x00 register TIM1 CCMR1 TIM1 capture compare mode 0x00 E register 1 TIM1 CCMR2 TIM1 capture compare mode 0x00 RS register 2 TIM1 CCMR3 TIM1 capture compare mode 0x00 x register 3 TIM1 CCMR4 TIM1 capture compare mode 0x00 register 4 TIM1 CCER1 TIM1 capture compare enable 0x00 B register 1 TIM4 CCER2 TIM1 capture compare enable 0x00 register 2 TIM1 CNTRH TIM1 counter high 0x00 TIM1 CNTRL TIM1 counter low 0x00 TIM1 PSCRH TIM1 prescaler register high Ox00 TIM1 PSCRL TIM1 prescaler register low 0x00 TIM1 ARRH TIM1 auto reload register high OxFF TIM1 ARRL TIM1 auto reload register low OxFF TIM1 DCH TIM1 repetition counter 0x00 register TIM1 CCR1H TIMT capture compare 0x00 register 1 high TIM1 CCRIL TIM1 capture compare 0x00 B register 1 low TIM1 CCR2H KEE 0x00 register 2 high TIM1 CCR2L TIM1 capture compare 0x00 E register 2 low TIM1 CCR3H TIM1 capture compare 0x00 register 3 high 36 121 DoclD15590 Rev 10 d STM8S903K3 STM8S903F3 Memory and register map Table 8 General hardware register map continued Address 0x00 526A 0x00 526B 0x00 526C 0x00 526D 0x00 526E 0x00 526F Block TIM1 Register label Register name TIM1 capture compare Reset status TIM1 CCR3L 0x00 register 3 low TIM1 CCR4H ER 0x00 register 4 high TIM1 CCR4L TIM1 capture compare 0x00 B register
28. HSE user external clock fepy 16 MHZ a 62 Typ Ipp Ruw VS fcpu HSE user external clock Vpp 25V AA 62 Typ IDD RUN vs Vpp HSI RC osc fopu 16 Oe KEE 63 Typ Ipp wri VS Von HSE external clock fepy 16 MHZ 1 eee eee 63 Typ Ipp wri VS fcpu HSE external clock Von 25 VV ee eee 64 Typ IDD WEN vs Vop HSI RC osc fopy 16 MEZ 2214 iis vir be DAA GA END 64 HSE external clock source 65 HSE oscillator circuit diagram 0 teas 67 Typical HSI frequency variation vs Vpp 4 temperatures 68 Typical LSI frequency variation vs Vpp 4 temperatures 0000 eee 69 Typical Vj and Vi vs Vpp 4 temperatures 0 000 000 0000 72 Typical pull up current vs Vpp 4 temperatures 72 Typical pull up resistance vs VDD 4 temperatures 72 Typ Vo Vpp 3 3 V standard porte 73 VoL Vpp 5 0 V standard porte 73 Typ Vol Vpp 3 3 V true open drain ports 00 00 000000 74 Typ Vo Vpp 5 0 V true open drain porte 74 Typ VoL Vpp 3 3 V high sink porte 74 Typ VoL Vpp 5 0 V high sink porte 74 Typ Vpp Vou Vpp 3 3 V standard porte 75 Typ Vpp Vou Vpp 5 0 V standard ports 0 000 000 0002 0 02 o ee 75 Typ Vpp Vou Vpp 3 3 V high sink ports lees 75 Typ Vpp Vou Vpp 5 0 V high sink ports 000 0000 75 Typical NRST Vj and Vum vs Vpp 4 temperatures 76 Typical NRST pull up resistance Rpy vs Vpp
29. Kbytes of code For more information see www cosmic software com STM8 assembler linker Free assembly toolchain included in the STVD toolset used to assemble and link the user application source code d DoclD15590 Rev 10 STM8S903K3 STM8S903F3 STM8 development tools 14 3 d Programming tools During the development cycle STice provides in circuit programming of the STM8 Flash microcontroller on the application board via the SWIM protocol Additional tools include a low cost in circuit programmer as well as ST socket boards which provide dedicated programming platforms with sockets for the STM8 programming For production environments programmers will include a complete range of gang and automated programming solutions from third party tool developers already supplying programmers for the STM8 family DoclD15590 Rev 10 115 121 Revision history STM8S903K3 STM8S903F3 15 116 121 Revision history Table 61 Document revision history Date 30 Apr 2009 Revision 1 Changes Initial release 03 Jun 2009 Added bullet point concerning unique identifier to Features section on cover page Highlighted internal reference voltage in Section 4 13 Analog to digital converter ADC 1 Updated wpu and PP status of PB5 12C_SDA TIM1_BKIN and PB4 12C_SCL ADC_ETR pins in Section 5 Pinouts and pin descriptions Updated Section 6 1 Memory map Added Section 9
30. Parameter Conditions Typ Max Unit G SS current in reset Vpp 25V 400 s Vpp 3 3 V 300 eser eecht i 150 bs 1 Data guaranteed by design not tested in production 2 Characterized with all I Os tied to Vas Current consumption of on chip peripherals Subject to general operating conditions for Vpp and Ta HSI internal RC fcpy fuAsrER 16 MHz Vpp 5V Table 33 Peripheral current consumption Symbol Parameter Typ Unit IDD TIM1 TIM1 supply current 210 Ippctimsy TIMS supply current 130 Ipp TIM6 TIM6 supply current 50 Ipp uanr4 UART1 supply current 120 HA Ipp sPl SPI supply current 45 Ipp 2c 12C supply current 65 Ipp apct ADC1 supply current when converting 1000 1 Data based on a differential Ipp measurement between reset configuration and timer counter running at 16 MHz No IC OC programmed no I O pads toggling Not tested in production Current consumption curves The following figures show typical current consumption measured with code executing in RAM DoclD15590 Rev 10 61 121 Electrical characteristics STM8S903K3 STM8S903F3 62 121 Figure 12 Typ Ipp nuw VS Vpp HSE user external clock fopy 16 MHz D E 9 205 I 5 2 B is 1 9 185 14 2 25 3 is 4 45 5 55 5 VM Figure 13 Typ Ipp nuw VS fcpu HSE user external clock Vpp 5 V a 25 85 25 45 ki T 154 ul V a 3 cl 3
31. RESET Reset Yes Yes 0x00 8000 TRAP Software interrupt 0x00 8004 0 TLI External top level _ 7 0x00 8008 interrupt 1 AWU SECH Wakeup rom Yes 0x00 800C 2 CLK Clock controller 0x00 8010 3 EXTIO Port A external Kat Yes 0x00 8014 interrupts 4 EXTM Port Bextemal vas Yes 0x00 8018 interrupts 5 EXTI2 Port C external vag Yes 0x00 801C interrupts 6 EXTI3 Port D external Yes Yes 0x00 8020 interrupts 7 EXTI4 Port E extemal Wes Yes 0x00 8024 interrupts 8 EXTI5 pon F extemal 0x00 8028 interrupts 9 Reserved 0x00 802C 10 SPI End of transfer Yes Yes 0x00 8030 TIM1 update overflow 11 IA underflow trigger S SE break 12 TIM1 TIMI capture 0x00 8038 compare 13 TIM5 TIMS update 0x00 803C overflow trigger 14 TIM5 TMS Gapiira 0x00 8040 compare 15 Reserved 0x00 8044 16 Reserved 0x00 8048 17 UART1 Tx complete Ox00 804C Receive register 18 UART1 DATA FULL 0x00 8050 19 I2C I2C interrupt Yes Yes 0x00 8054 Ky DoclD15590 Rev 10 43 121 Interrupt vector mapping STM8S903K3 STM8S903F3 Table 10 Interrupt mapping continued Wakeup from Wakeup from IRQ no Source block Description halt mada active halt moda Vector address 20 Reserved 0x00 8058 21 Reserved Ox00 805C ADC1 end of 22 ADC1 conversion analog 0x00 8060 watchdog interrupt 23 TIM6 TU MEA 0x00 8064 overflow 24 Flash EOP WR PG DIS
32. Unique ID Added TBD values to Table 45 SPI characteristics Added max values to Table 48 ADC accuracy with RAIN 10 kW VDD 5 Vand Table 49 ADC accuracy with RAIN lt 10 kW VDD 3 3 V DoclD15590 Rev 10 d STM8S903K3 STM8S903F3 Revision history Table 61 Document revision history continued Date Revision Changes Added SO20W TSSOP20 SDIP32 and UFQFPN32 packages Added STM8S903F3 part number Updated the document status to full datasheet Updated the definition of alternate function remapping option in Table 4 Legend abbreviations for pinout tables Updated Px IDR reset value in Table 7 I O port hardware register map Removed ESR low limit and update high limit for CEXT conditions in Table 21 General operating conditions Updated VCAP and ESR low limit added ESL parameter as well as PD in Table 21 General operating conditions Changed ESD to FESD functional ESD added name of AN1709 replaced IEC 1000 with IEC 61000 in 22 Apr 2010 3 Table 50 EMS data Replaced IEC 1000 with IEC 61000 added title of AN1015 and added footnote to Table 51 EMI data Replaced J 1752 3 with IEC 61967 2 and updated data of Table 51 EMI data Removed note 3 related to Accuracy of HSI oscillator Updated O4 in Table 13 STM8S903K3 alternate function remapping bits 7 2 for 32 pin packages Changed j to 60 C W in Section 12 2 Selecting the product temperature range In Section 13 Ordering inf
33. Vppa fmaster and Ta unless otherwise specified Table 47 ADC characteristics Symbol Parameter Conditions Min Typ Max Unit Vpp 2 95 to 5 5 V 1 4 fADC ADC clock frequency Lt MHz Vpp 4 5 to 5 5 V 1 6 VAIN Conversion voltage range Vss Vpp V Internal sample and hold CADC capacitor B 9 li pr fADC 4MHz 0 75 tg Minimum sampling time US fADC 6MHz 0 5 teTAB Wakeup time from standby 7 Hs Minimum total conversion time fanc 4 MHz po Hs tconv including sampling time 10 fanc 6 MHz 2 33 US bit resolution 14 iiag 1 During the sample time the sampling capacitance Cam 3 pF max can be charged discharged by the external source The internal resistance of the analog source must allow the capacitance to reach its final voltage level within ts After the end of the sample time ts changes of the analog input voltage have no effect on the conversion result Values for the sample clock ts depend on programming d DoclD15590 Rev 10 83 121 Electrical characteristics STM8S903K3 STM8S903F3 84 121 Table 48 ADC accuracy with Rajn lt 10 kQ Vpp 5 V Symbol Parameter Conditions Typ Max fapc 2 MHz 1 6 3 5 EA Total unadjusted error fApc 4 MHz 22 4 fapc 6 MHz 24 4 5 fapc 2 MHz 1 1 2 5 IEol Offset error fApc 4 MHz 1 5 3 fapc 6 MHz 1 8 3 fApc 2 MHz 1 5 3 IEcl Gain error fApc
34. characterization results not tested in production 2 Default clock configuration measured with all peripherals off 58 121 DoclD15590 Rev 10 d STM8S903K3 STM8S903F3 Electrical characteristics Total current consumption in active halt mode Table 27 Total current consumption in active halt mode at Vpp 5 V Conditions Main Max at Max at Symbol Parameter voltage pa Typ 85 cf 95 ef Unit regulator Flash mode Clock source MVR 2 HSE crystal osc Operating mode 16 MHz 1030 Operating mode LSI RC osc 128 kHz 200 260 300 Supply On Power down HSE crystal osc 970 current in mode 16 MHz A DD AH active halt P mode PONOT GNI LSI RC osc 128 kHz 150 200 230 mode Operating mode LSI RC osc 128 kHz 66 85 110 Off Power down LSI RC osc 128 kHz 10 20 40 mode 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK ICKR register 3 Configured by the AHALT bit in the FLASH CR1 register Table 28 Total current consumption in active halt mode at Vpp 3 3 V Conditions Main Max at Max at i Symbol Parameter voltage ra Typ 85 cf 95 ef Unit regulator Flash mode Clock source MVR HSE crystal osc Operating mode 16 MHz 550 Operating mode LSI RC osc 128 kHz 200 260 290 Supply On Power down HSE crystal
35. low and high level in the application Table 60 Thermal characteristics Symbol Parameter Value Unit Oja ee ai junction ambient 110 C W Oja Weg COPIE junction ambient 20 C W Oja UE E 101 C W Bs ee Ee junction ambient 60 C W M keie a junction ambient 60 C W 1 Thermal resistances are based on JEDEC JESD51 2 with 4 layer PCB in a natural convection environment Reference document JESD51 2 integrated circuits thermal test method environment conditions natural convection still air Available from www jedec org DoclD15590 Rev 10 105 121 Thermal characteristics STM8S903K3 STM8S903F3 12 2 106 121 Selecting the product temperature range When ordering the microcontroller the temperature range is specified in the order code see Section 13 Ordering information The following example shows how to calculate the temperature range needed for a given application Assuming the following application conditions Maximum ambient temperature Tamax 75 C measured according to JESD51 2 Ippmax 8 MA Vpp 5 V maximum 20 I Os used at the same time in output at low level with lo 8 MA Vo 7 0 4 V Pintmax 8 MA x 5 V 400 mW Piomax 20 x 8 mA x 0 4 V 64 mW This gives PinTmax 400 mW and Pjomax 64 mW Ppmax 400 mW 64 mW Thus Ppmax 464 mW Using the values obtained in Table 60 Thermal characteristics on page 105 T max is calculated as follows For LQFP32 60
36. package footprint Figure 57 TSSOP20 marking example package top view Figure 59 SO20 marking example package top view 26 Mar 2015 Corrected the values for b dimensions in Table 55 UFQFPN32 32 pin 5x5 mm 0 5 mm pitch ultra thin fine pitch quad flat package mechanical data DoclD15590 Rev 10 d STM8S903K3 STM8S903F3 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections enhancements modifications and improvements to ST products and or to this document at any time without notice Purchasers should obtain the latest relevant information on ST products before placing orders ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product ST and the ST logo are trademarks of ST All other product or service names are the property of their respective owners Information in this document supersedes and replaces information previously supplied in any pri
37. reset external circuitry attention must be taken to the charge discharge time of the external capacitor to fulfill the external devices reset timing conditions Minimum recommended capacity is 100 nF d DoclD15590 Rev 10 77 121 Electrical characteristics STM85903K3 STM85903F3 Figure 38 Recommended reset pin protection Vas STM8 External reset NRST Upa Filter ins o circuit 0 1 uF Optional MSv36491V1 10 3 8 SPI serial peripheral interface Unless otherwise specified the parameters given in Table 45 are derived from tests performed under ambient temperature faster frequency and Vpp supply voltage conditions tMASTER 1 fMASTER Refer to I O port characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO Table 45 SPI characteristics Symbol Parameter Conditions Min Max Unit peene NY fsck SPI clock frequency d 78 121 DoclD15590 Rev 10 STM8S903K3 STM8S903F3 Electrical characteristics d Table 45 SPI characteristics continued Unit ns DoclD15590 Rev 10 Symbol Parameter Conditions Min Max tyscx SPI clock rise and fall Capacitive load 25 tySck time C 30 pF Games NSS setup time Slave mode 4 tMASTER trnss NSS hold time Slave mode 70 2 IWSCKH SCK high and lo
38. speed internal clock enable 0 LSI clock is not available as CPU clock source 1 LSI clock is available as CPU clock source IWDG HW Independent watchdog 0 IWDG Independent watchdog activated by software 1 IWDG Independent watchdog activated by hardware WWDG HW Window watchdog activation 0 WWDG window watchdog activated by software 1 WWDG window watchdog activated by hardware WWDG HALT Window watchdog reset on halt 0 No reset generated on halt if WWDG active 1 Reset generated on halt if WWDG active d DoclD15590 Rev 10 STM8S903K3 STM8S903F3 Option bytes 8 1 d Table 12 Option byte description continued Option byte no OPT4 Description EXTCLK External clock selection 0 External crystal connected to OSCIN OSCOUT 1 External clock signal on OSCIN CKAWUSEL Auto wake up unit clock 0 LSI clock source selected for AWU 1 HSE clock with prescaler selected as clock source for AWU PRSC 1 0 AWU clock prescaler Ox 16 MHz to 128 kHz prescaler 10 8 MHz to 128 kHz prescaler 11 4 MHz to 128 kHz prescaler OPT5 HSECNT 7 0 HSE crystal oscillator stabilization time 0x00 2048 HSE cycles OxB4 128 HSE cycles OxD2 8 HSE cycles OxE1 0 5 HSE cycles Alternate function remapping bits Table 13 STM8S903K3 alternate function remapping bits 7 2 for 32 pin packages Option byte no OPT2 Description AFR7 Alternate function remapping option 7
39. to 0x00 5059 Block Reserved are Register label a 60 bytes Register name Reset status 0x00 505A FLASH CR1 Flash control register 1 0x00 0x00 505B FLASH CR2 Flash control register 2 0x00 0x00 505C FLASH NCR2 Flash complementary control Gee x register 2 0x00 505D Flash FLASH FPR Flash protection register 0x00 0x00 505E FLASH _NFPR EE OxFF protection register 0x00 505F FLASH IAPSR Plast it apple 0x00 programming status register 0x00 5060 to 0x00 5061 Reserved area 2 bytes 0x00 5062 Flash FLASH PUKR Flash program memory 0x00 unprotection register 0x00 5063 Reserved area 1 byte 0x00 5064 Flash FLASH _DUKR Data EEPROM unprotection 0x00 register 0x00 5065 to 0x00 509F Reserved area 59 bytes 0x00 50A0 EXTI CR1 External interrupt control 0x00 register 1 ITC 0x00 50A1 EXTI CR2 External interrupt control 0x00 register 2 0x00 50A2 to 0x00 50B2 Reserved area 17 bytes 0x00 50B3 RST RST_SR Reset status register OxXX 1 0x00 50B4 to 0x00 50BF Reserved area 12 bytes 0x00 50C0 CLK ICKR Internal clock control register 0x01 CLK 0x00 50C1 CLK ECKR External clock control register 0x00 0x00 50C2 Reserved area 1 byte d DoclD15590 Rev 10 33 121 Memory and register map STM8S903K3 STM8S903F3 Table 8 General hardware register map continued
40. unless otherwise specified All unused pins must be kept at a fixed voltage using the output mode of the I O for example or an external pull up or pull down resistor Table 40 I O static characteristics Symbol Parameter Conditions Min Typ Max Unit Vu Input low level voltage 0 3 V E 0 3 x Vpp y Vin Input high level voltage Vpp 5 V 0 7 x Vpp Vpp 0 3 V Vhys Hysteresis 1 700 mV Rpu Pull up resistor Vpp 5 V Vin Vss 30 55 80 kQ Fast I Os 352 tot Rise and fall time Load 50 pF HE GK 1076 9076 Standard and high sink I Os 1252 Load 50 pF Fast I Os E 7 20 2 te t Rise and fall time Load 20 pF R IF 10 90 Standard and high sink I Os f s02 Load 20 pF Digital input leakage likg Geen S d Vss lt Vin lt Vpp s 10 pA Analog input leakage likg ana d p 9 Vss lt Vins Vpp 250 2 nA 7 Leakage current in At 2 likgtini adjacent I O Injection current 4 mA 1 HA 1 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results 2 Data based on characterization results not tested in production d DoclD15590 Rev 10 not tested in production 71 121 Electrical characteristics STM8S903K3 STM8S903F3 Figure 22 Typical Vj and Vj vs Vpp 4 temperatures VIL VIH V Figure 23 Typical pull up current vs Von 4 temperatures Pul up current pa 72
41. 00 5233 UART1 BRR2 UART 1 baud rate register 2 0x00 0x00 5234 UART1_CR1 UART1 control register 1 0x00 0x00 5235 UART1 UART1_CR2 UART1 control register 2 0x00 0x00 5236 UART1_CR3 UART71 control register 3 0x00 0x00 5237 UART1_CR4 UART1 control register 4 0x00 0x00 5238 UART1_CR5 UART71 control register 5 0x00 0x00 5239 UART1_GTR UART1 guard time register 0x00 0x00 523A UART1_PSCR UART1 prescaler register 0x00 0x00 523B to 0x00 523F Reserved are a 21 bytes d DoclD15590 Rev 10 35 121 Memory and register map STM85903K3 STM8S903F3 Table 8 General hardware register map continued Address 0x00 5250 0x00 5251 0x00 5252 0x00 5253 0x00 5254 0x00 5255 0x00 5256 0x00 5257 0x00 5258 0x00 5259 0x00 525A 0x00 525B 0x00 525C 0x00 525D 0x00 525E 0x00 525F 0x00 5260 0x00 5261 0x00 5262 0x00 5263 0x00 5264 0x00 5265 0x00 5266 0x00 5267 0x00 5268 0x00 5269 Block TIM1 Register label Register name Reset status TIM1 CR1 TIM1 control register 1 0x00 TIM1 CR2 TIM1 control register 2 0x00 TIM1 SMCR TIM1 slave mode control 0x00 a register TIM1_ETR TIM1 external trigger register 0x00 TIM1_IER TIM1 interrupt enable register 0x00 TIM1_SR1 TIM1 status register 1 0x00 TIM1_SR2 TIM1 status register 2 0x00 TIM1
42. 03F3 alternate function Refer to STM8S903K3 pin description remapping bits 1 0 for 20 pin packages AFR1 option bit value AFRO option bit value UO port ee 0 0 AFR1 and AFRO remapping options inactive Default alternate functions PC5 TIM5 CH1 0 1 PC6 TIM1 CH1 PC7 TIM1 CH2 PA3 SPI NSS PD2 TIM5_CH3 PD2 TIM5_CH3 PC5 TIM5_CH1 PC6 TIM1_CH1 PC7 TIM1_CH2 1 1 PC2 PC1 DES TIM1 CHIN PA3 UART1 TX PF4 UART1 RX 1 d Refer to STM8S903F3 pin descriptions DoclD15590 Rev 10 49 121 Unique ID STM8S903K3 STM8S903F3 9 50 121 Unique ID The devices feature a 96 bit unique device identifier which provides a reference number that is unique for any device and in any context The 96 bits of the identifier can never be altered by the user The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm The unique device identifier is ideally suited e For use as serial numbers e For use as security keys to increase the code security in the program memory while using and combining this unique ID with software cryptographic primitives and protocols before programming the internal memory e To activate secure boot processes Table 17 Unique ID registers 96 bits Address Brace Unique ID bits pjeysyjas syea tyo 0x4865 X co ordinate on U ID 7 0 0x486
43. 1 Port B4 alternate function ADC ETR port B5 alternate function TIM1 BKIN AFR5 Reserved AFR6 Reserved 0 Remapping option inactive Default alternate functions AFR7 used Refer to pinout description check only one option 1 Port C3 alternate function TIM1 CHIN port C4 alternate function TIM1 CH2N OPT3 watchdog WWDG HALT 0 No reset generated on halt if WWDG active check only one option 1 Reset generated on halt if WWDG active WWDG HW 0 WWDG activated by software check only one option 1 WWDG activated by hardware IWDG HW 0 IWDG activated by software check only one option 1 IWDG activated by hardware LSI EN 0 LSI clock is not available as CPU clock source check only one option 1 LSI clock is available as CPU clock source HSITRIM 0 3 bit trimming supported in CLK HSITRIMR register check only one option 1 4 bit trimming supported in CLK HSITRIMR register DoclD15590 Rev 10 111 121 Ordering information STM8S903K3 STM8S903F3 OPT4 watchdog for 16 MHz to 128 kHz prescaler for 8 MHz to 128 kHz prescaler for 4 MHz to 128 kHz prescaler PRSC check only one option CKAWUSEL LSI clock source selected for AWU check only one option HSE clock with prescaler selected as clock source for AWU EXTCLK External crystal connected to OSCIN OSCOUT check only one option External signal o
44. 121 Memory and register map STM8S903K3 STM85903F3 Table 8 General hardware register map continued Address Block Register label Register name Reset status 0x00 5400 ADC CSR ADC control status register 0x00 0x00 5401 ADC CR1 ADC configuration register 1 0x00 0x00 5402 ADC CR2 ADC configuration register 2 0x00 0x00 5403 ADC CR3 ADC configuration register 3 0x00 0x00 5404 ADC DRH ADC data register high OxXX 0x00 5405 ADC DRL ADC data register low OxXX 0x00 5406 ADC TDRH ADC Schmitt trigger disable 0x00 register high 0x00 5407 ADC TDRL ADC Schmitt trigger disable 0x00 register low 0x00 5408 ADC_HTRH Dh high threshold register 0x03 ADC1 0x00 5409 cont d ADC HTRL den high threshold register OxFF 0x00 540A ADC LTRH a low threshold register 0x00 0x00 540B ADC_LTRL GC low threshold register 0x00 0x00 540C ADC AWSRH ADC analog watchdog status 0x00 register high 0x00 540D ADC AWSRL ADC analog watchdog status 0x00 register low 0x00 540E ADC AWCRH ADC analog watchdog control Pasan register high 0x00 540F ADC_AWCRL ADC analog watchdog control d register low 0x00 5410 to 0x00 57FF Reserved area 1008 bytes 1 Depends on the previous reset source 2 Write only register 40 121 DoclD15590 Rev 10 Ly STM8S903K3 STM8S903F3 Memory and register map 6 2 3 CPU SWIM debug module interrupt controller regis
45. 2 1 Port C3 alternate function TIM1 CH1N port C4 alternate function TIM1 CH2N AFR6 Alternate function remapping option 6 Reserved AFR5 Alternate function remapping option 5 Reserved AFRA Alternate function remapping option 4 0 AFR4 remapping option inactive Default alternate functions 1 Port B4 alternate function ADC ETR port B5 alternate function TIM1 BKIN AFR3 Alternate function remapping option 3 0 AFR3 remapping option inactive Default alternate function 1 Port C3 alternate function TLI AFR2 Alternate function remapping option 2 Reserved 1 Do not use more than one remapping option in the same port 2 Refer to STM8S903K3 pin descriptions Table 15 STM8S903K3 alternate function remapping bits 1 0 for 32 pin packages AFR1 option bit value AFRO option bit value UO port a a a 0 0 AFR1 and AFRO remapping options inactive Default alternate functions PC5 TIM5_CH1 0 1 PC6 TIM1 CH1 PC7 TIM1 CH2 PA3 SPI NSS PD2 TIM5 CH3 d DoclD15590 Rev 10 STM8S903K3 STM8S903F3 Option bytes Table 15 STM8S903K3 alternate function remapping bits 1 0 for 32 pin packages continued AFR1 option bit value AFRO option bit value UO port EH PD2 TIM5 CH3 PC5 TIM5 CH1 PC6 TIM1_CH1 PC7 TIM1_CH2 PC2 TIM1_CH3N PC1 TIM1 CH2N PE5 TIM1 CHIN PA3 UART1 TX PF4 UART1 RX 1 Table 16 STM8S9
46. 3 11 a a 05 04 t i l i i 2 4 i 8 10 12 14 16 18 Foru MHz DoclD15590 Rev 10 d STM8S903K3 STM8S903F3 Electrical characteristics Figure 14 Typ Ipp nuw VS Vpp HSI RC osc fcpy 16 MHz 4H 2 4 H noes ee 17 a es Sp RE 9 9 IDD run HSI ma bari m DD WFI HSE mA DoclD15590 Rev 10 63 121 d Electrical characteristics STM8S903K3 STM8S903F3 Figure 16 Typ Ipp wen VS fcpu HSE external clock Vpp 5 V mA IDD WEI HSE Fcru MHz Figure 17 Typ Ipp wri VS Vpp HSI RC osc fopy 16 MHz mA IDD WFI Ha n tn o 2 25 3 3 5 4 4 5 5 Fcev MHz d 64 121 DocID15590 Rev 10 STM85903K3 STM8S9 03F3 Electrical characteristics 10 3 3 HSE user external clock Subject to general operating conditions for Vpp and T Table 34 HSE user external clock characteristics External clock sources and timing characteristics Symbol Parameter Conditions Min Max Unit ie Ee o 5 me Vusgu Edo pin high 0 7xVpp Vpp 0 3 V v Vusg ee ES Vss 0 3 x Vpp ILEAK HSE SS Ee Vss lt Vin lt Vpp 1 1 pA 1 Data based on characterization results not tested in production Figure 18 HSE external clock source d External clock source JUUL DoclD15590 Rev 10 MS36489V1 65 121 Electrical character
47. 3 3 V pins sunk lio 20 mA 150 Von 5V V Output high level with 8 lio 10 mA 40 pins sourced Vpp 25V lio 10 mA Von NG Ke kap 240 Output high level with 4 Vpp 3 3 V pins sourced lio 20 mA 330 Von 5V 1 Data based on characterization results not tested in production Figure 25 Typ Vo Vpp 3 3 V standard ports Figure 26 Vo Vpp 5 0 V standard ports d DoclD15590 Rev 10 73 121 Electrical characteristics STM8S903K3 STM8S903F3 Figure 27 Typ Vo 9 Vpp 3 3 V true open Figure 28 Typ Vo Vpp 5 0 V true open drain ports drain ports Figure 29 Typ Vo Vpp 3 3 V high sink Figure 30 Typ Vo 9 Vpp 5 0 V high sink ports ports d 74 121 DoclD15590 Rev 10 STM8S903K3 STM8S903F3 Electrical characteristics Figure 31 Typ Vpp Vou Vpp 3 3 V Figure 32 Typ Vpp Vou Vpp 5 0 V standard ports standard ports Figure 33 Typ Vpp Von Vpop 3 3 V high Figure 34 Typ Vpp Vou Vpop 5 0 V high sink ports sink ports d DoclD15590 Rev 10 75 121 Electrical characteristics STM8S903K3 STM8S903F3 10 3 7 76 121 Reset pin characteristics Subject to general operating conditions for Vpp and Ta unless otherwise specified Table 44 NRST pin characteristics
48. 4 MHz 2 1 3 fapc 6 MHz 22 4 fApc 7 2 MHz 0 7 1 5 Epl Differential linearity error fapc 4 MHz 0 7 1 5 fapc 6 MHz 0 7 1 5 fapc 2 MHz 0 6 1 5 JE Integral linearity error fapc 4 MHz 0 8 2 fApc 6 MHz 0 8 2 Data based on characterization results not tested in production Unit LSB ADC accuracy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for lj up and YliNJ piv in Section 10 3 6 does not affect the ADC accuracy Table 49 ADC accuracy with Rajy lt 10 KO Vpp 3 3 V Symbol Parameter Conditions Typ Max fApc 2 MHz 1 6 3 5 Ed Total unadjusted error fADC 4 MHz 1 9 4 fapc 2 MHz 1 2 5 Eol Offset error fapc 4 MHz 1 5 2 5 fApc 2 MHz 1 3 3 Ecl Gain error fADC 4MHz 2 3 fADC 2 MHz 0 7 1 Epl Differential linearity error fapc 4 MHz 0 7 1 5 fapc 2 MHz 0 6 1 5 Ei Integral linearity error fADC 4MHz 0 8 2 Unit LSB 1 Data based on characterization results not tested in production DoclD15590 Rev 10 d STM8S903K3 STM8S903F3 Electrical characteristics ADC accu
49. 4 low TIM1 BKR TIM1 break register 0x00 TIM1 DTR TIM1 dead time register 0x00 TIM1 OISR TIM1 output idle state register 0x00 0x00 5270 to 0x00 52FF Reserved area 147 bytes d DoclD15590 Rev 10 37 121 Memory and register map STM85903K3 STM8S903F3 Table 8 General hardware register map continued Address 0x00 5300 0x00 5301 0x00 5302 0x00 5303 0x00 5304 0x00 5305 0x00 5306 0x00 5307 0x00 5308 0x00 5309 0x00 530A 0x00 530B 0x00 530C 0x00 530D 0x00 530E 0x00 530F 0x00 5310 0x00 5311 0x00 5312 0x00 5313 0x00 5314 0x00 5315 0x00 5316 Block TIM5 Register label Register name Reset status TIM5 CR1 TIM5 control register 1 0x00 TIM5 CR2 TIM5 control register 2 0x00 TIM5 SMCR TIMS slave mode control 0x00 Ge register TIM5 IER TIM5 Interrupt enable register 0x00 TIM5 SR1 TIM5 status register 1 0x00 TIM5 SR2 TIMS status register 2 0x00 TIM5 EGR TIMS event generation 0x00 register TIM5 CCMR1 TIMS capture compare mode 0x00 n register 1 TIM5 CCMR2 TIMS capture compare mode 0x00 register 2 TIM5 CCMR3 TIMS capture compare mode 0x00 e register 3 TIM5 CCER1 TIMS capture compare enable 0x00 register 1 TIM5 CCER2 TIMS capture compare enable 0x00 register 2 TIM5_CNTRH TIM5 counter high 0x00 TIM5 CNTRL T
50. 48 TIMO LUN vol xi x xlus o3 x x POT channel HART clock BEEP pa 1 BEEP output AFR2 UART1_CK P Analog input 5 PD5 AIN5 Port 2 19 UART1 TX UO X X X HS O03 X X D5 UART1 data transmit Analog input 6 PD6 AIN6 Port 3 20 UART1 RX UO X X X HS O03 X X D6 See data 1 UO pins used simultaneously for high current source sink must be uniformly spaced around the package In addition the total driven current must respect the absolute maximum ratings see Section 10 2 Absolute maximum ratings 2 When the MCU is in Halt Active halt mode PA1 is automatically configured in input weak pull up and cannot be used for waking up the device In this mode the output state of PA1 is not driven It is recommended to use PA1 only in input mode if Halt Active halt is used in the application 3 In the open drain output column T defines a true open drain UO P buffer weak pull up and protection diode to VDD are not implemented 4 The PD1 pin is in input pull up during the reset phase and after internal reset release 24 121 DoclD15590 Rev 10 d STM8S903K3 STM8S903F3 Pinouts and pin descriptions 5 4 d STM8S903K3 UFQFPN32 LQFP32 and SDIP32 pinouts Figure 5 STM8S903K3 UFQFPN32 LQFP32 pinout NRST OSCIN PA1 OSCOUT PA2 vss VCAP VDD UART1_TX SPI_NSS TIM2_CH3 HS PA3 UART1_RX PF4 1 HS high sink capability UART1 CK AIN
51. 6 the wafer U ID 15 8 0x4867 Y co ordinate on U ID 23 16 0x4868 the wafer U ID 31 24 0x4869 Wafer number U ID 39 32 0x486A U ID 47 40 0x486B U ID 55 48 0x486C U ID 63 56 0x486D Lot number U ID 71 64 0x486E U ID 79 72 0x486F U ID 87 80 0x4870 U ID 95 88 d DoclD15590 Rev 10 STM85903K3 STM85903F3 Electrical characteristics 10 10 1 10 1 1 10 1 2 10 1 3 10 1 4 d Electrical characteristics Parameter conditions Unless otherwise specified all voltages are referred to Vss Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at Ta 25 C and Ta Tamax given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation mean x 3 2 Typical values Unless otherwise specified typical data are based on Ta 25 C Vpp 5 0 V They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusi
52. 8S903K3 STM8S903F3 Memory and register map 6 Memory and register map 6 1 Memory map Figure 7 Memory map 0x00 0000 RAM 1 Kbyte 513 bytes stack 0x00 03FF 0x00 0800 Reserved 0x00 3FFF 0x00 4000 640 bytes data EEPROM 0x00 427F 0x00 4280 Reserved 0x00 47FF 0x00 4800 Option bytes 0x00 480A 0x00 480B Reserved 0x00 4864 0x00 4865 i 0x00 4870 el 0x00 4871 Reserved 0x00 4FFF 0x00 5000 GPIO and periph reg 0x00 57FF 0x00 5800 Reserved 0x00 7EFF EE CPU SWIM debug ITC registers 0x00 7FFF 0x00 8000 32 interrupt vectors 0x00 807F 0x00 8080 Flash program memory 0x00 9FFF 8 Kbytes 0x00 A000 Reserved 0x02 7FFF x MSv36419V1 Ly DoclD15590 Rev 10 31 121 Memory and register map STM8S903K3 STM85903F3 6 2 Register map 6 2 1 UO port hardware register map Table 7 UO port hardware register map Address Block Register label Register name Reset status 0x00 5000 PA ODR Port A data output latch register 0x00 0x00 5001 PA IDR Port A input pin value register 0xxx 0x00 5002 Port A PA DDR Port A data direction register 0x00 0x00 5003 PA CR1 Port A control register 1 0x00 0x00 5004 PA CR2 Port A control register 2 0x00 0x00 5005 PB ODR Port B data output latch register 0x00 0x00 5006 PB IDR Port B input pin value register 0xxx 0x00 5007 Port
53. 903K3 STM8S903F3 100 121 3 Dimension E1 does not include interlead flash or protrusions Interlead flash or protrusions shall not exceed 0 25mm per side Figure 56 TSSOP20 recommended package footprint 0 25 d RI 1 0 25 7 10 4 40 Lom 3 10 0 40 0 65 YA FP V1 1 Dimensions are expressed in millimeters d DoclD15590 Rev 10 STM8S903K3 STM8S903F3 Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 57 TSSOP20 marking example package top view Standard ST logo Product a sous 1 identification Pin 1 identifier Revision code MS37472V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity 11 6 SO20 package information Figure 58 SO20 package outline hx45 Y FC 0 25 mm GAUGE PLANE Z7 ME V2 d DoclD15590 Rev 10 101 121 Package information STM8S903K3 STM8S903F3 102 121 Table 59
54. A TIM5 CH2 ADC ETR CLK CCO AIN3 TIMS CH3 SWIM TLI TIM1 CH4 UART1 RX UART1 TX BEEP TIM5 CH1 TIM1 BKIN HS HS HS HS HS HS HS HS PD7 PDE PD5 PD4 PD3 PD2 PD1 PDO ce 400 BB ON a 30 29 28 eco N zx N J N o N a o o EN N AR a E o PB7 PB6 HS PB2 HS PB1 HS PBO TIM1 CH1N AINO HS PB3 TIM1 CH3N AIN2 TIM1 CH2N AIN1 TIM1_ETR AIN3 TIM1_BKIN I2C SDA T PB5 ADC ETR I2C SCL T PB4 PC7 HS SPI MISO TIM1 CH2 PC6 HS SPI MOSI TIM1 CH1 PC5 HS SPI SCK TIM5 CH1 PC4 HS TIM1 CH4 CLK CCO AIN2 TIM1 CH2N PC3 HS TIM1 CH3 TU TIM1 CH1N PC2 HS TIM1_CH2 TIM1 CH3N PC1 HS TIM1 CH1 UART1 CK TIM1_CH2N PE5 SPI NSS TIM1 CH1N T True open drain P buffer and protection diode to Vpp not implemented alternate function remapping option if the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function DoclD15590 Rev 10 MSv37456V1 25 121 Pinouts and pin descriptions STM8S903K3 STM8S903F3 Figure 6 STM8S903K3 SDIP32 pinout AIN4 TIM5 CH2 ADC ETR PD3 HS TIM5 CH1 UART1 CK BEEP PD4 HS 2 AINS UART1 TX PD5 HS D 3 AING UART1 RX PD6 H5 D 4 TIM1 cH4 TLV PD7
55. EMC guidelines for STM8S microcontrollers d DoclD15590 Rev 10 STM8S903K3 STM8S903F3 Electrical characteristics d Electromagnetic interference EMI Based on a simple application running on the product toggling 2 LEDs through the I O ports the product is monitored in terms of emission This emission test is in line with the norm SAE IEC 61967 2 which specifies the board and the loading of each pin Table 51 EMI data Conditions Max fepu Symbol Parameter Monitored Unit General conditions frequency band 16 MHz 16 MHz 8 MHz 16 MHz Va 5V 0 1 MHZ to 30 MHz 5 5 DD H Peak level TA 25 C 30 MHz to 130 MHz 4 5 dBuV SEM LQFP32 package SAE EMI level EC 619672 SAE EMI level 2 5 2 5 y 1 Data based on characterization results not tested in production Absolute maximum ratings electrical sensitivity Based on two different tests ESD DLU and LU using specific measurement methods the product is stressed to determine its performance in terms of electrical sensitivity For more details refer to the application note AN1181 Electrostatic discharge ESD Electrostatic discharges a positive then a negative pulse separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts x n 1 supply pin One model can be simulated Human body model This te
56. HS 5 NRST 6 osciNiPA1 7 oscour PA2 8 vss 9 vcaP 10 vop 11 WART TXI SPI NSS TIM5 CH3 PA3 HS D 12 UART1 RXJ PF4 PB7 14 PD2 HS AIN3 TIM5 CH3 PD1 HS SWIM PDO HS TIM1_BKIN CLK CCO PC7 HS SPI MISO TIM1 CH2 PC6 HS SPI MOSI TIM1 CH1 PC5 HS SPI SCK TIM5 CH1 PC4 HS TIM1 CH4 CLK CCO AIN2 TIM1 CH2N PC3 HS TIM1 CH3 TLI TIM1 CHIN PC2 HS TIM1 CH2 TIM1 CH3N PC1 HS TIM1_CH1 UART1_CK TIM1 CH2N PE5 SPI NSS TIM1 CH1N PBO HS AINO TIM1_CH1N PB1 HS AIN1 TIM1 CH2N PB2 HS AIN2 TIM1_CH3N PBe 15 TIM1_BKIN I2C_SDA PB5 T PB3 HS AIN3 TIM1_ETR PB4 T I2C SCL ADC ETR MSv37457V1 HS high sink capability T True open drain P buffer and protection diode to Vpp not implemented 3 J alternate function remapping option if the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function 5 5 STM8S903K3 UFQFPN32 LQFP32 SDIP32 pin descriptions Table 6 STM8S903K3 UFQFPN32 LQFP32 SDIP32 pin descriptions a Input Output o c x c Hi 2 a os o San LL D zoo E e ER Sg 2 JE E 22 Ar 2 5 Pin name Sue pe E BK a 5 gt sS 225s EIS el Biel o n TO CHI ell ZS Ee amp oja 5 5 a E 28 G 2 EC t go a d 6 1 NRST wl XI bolo o Reset a 712 patroscin2 jo X x x lot x x Porta Resonator crys
57. HSI accuracy curve in High speed internal RC oscillator HSI Updated the value of recommended external capacitor to 100 nF in Table 44 NRST pin characteristics Updated the disclaimer 28 Jul 2011 6 Renamed internal reference voltage as internal bandgap reference voltage Updated notes related to VCAP in Table 21 General operating conditions Added values of tp tp for 50 pF load capacitance and updated note in Table 40 I O static characteristics Updated typical and maximum values of RPU in Table 40 I O static characteristics and Table 44 NRST pin characteristics Changed SCK input to SCK output in Table 45 SPI characteristics Modified Figure 51 UFQFPN20 package outline 04 Apr 2012 7 Restored Figure 44 Typical application with ADC Modified Figure 51 UFQFPN20 package outline 13 Jun 2012 8 d DoclD15590 Rev 10 119 121 Revision history STM8S903K3 STM8S903F3 120 121 Table 61 Document revision history continued Date 23 Feb 2015 Revision Changes Updated Section 11 5 TSSOP20 package information Section 11 3 UFQFPN20 package information Added Figure 46 LQFP32 recommended footprint Figure 47 LQFP32 marking example package top view Figure 50 UFQFPN32 marking example package top view Figure 52 UFQFPN20 marking example package top view Figure 54 SDIP32 marking example package top view Figure 56 TSSOP20 recommended
58. I O pins used simultaneously for high current source sink must be uniformly spaced around the package In addition the total driven current must respect the absolute maximum ratings see Section 10 Electrical characteristics 2 When the MCU is in Halt Active halt mode PA1 is automatically configured in input weak pull up and cannot be used for waking up the device In this mode the output state of PA1 is not driven It is recommended to use PA1 only in input mode if Halt Active halt is used in the application 3 In the open drain output column T defines a true open drain UO P buffer weak pull up and protection diode to Vpp are not implemented 4 The PD1 pin is in input pull up during the reset phase and after internal reset release d DoclD15590 Rev 10 29 121 Pinouts and pin descriptions STM8S903K3 STM85903F3 5 6 30 121 Alternate function remapping As shown in the rightmost column of the pin description table some alternate functions can be remapped at different I O ports by programming one of eight AFR alternate function remap option bits When the remapping option is active the default alternate function is no longer available To use an alternate function the corresponding peripheral must be enabled in the peripheral registers Alternate function remapping does not effect GPIO capabilities of the I O ports see the GPIO section of the family reference manual RM0016 d DoclD15590 Rev 10 STM
59. IM5 counter low 0x00 TIM5 PSCR TIM5 prescaler register 0x00 TIM5 ARRH TIM5 auto reload register high OxFF TIM5 ARRL TIM5 auto reload register low OxFF TIM5 CCR1H TIMS capt re compare 0x00 register 1 high TIM5 CCRIL TIMS capture compare 0x00 register 1 low TIM5_CCR2H TIMS capture compare reg 2 0x00 high TIM5 CCR2L TIMS capture compare 0x00 ES register 2 low TIM5 CCR3H TIMS capture compar 0x00 register 3 high TIM5_CCR3L TIM5 capture compare 0x00 register 3 low 0x00 5317 to 0x00 533F 38 121 Reserved area 43 bytes DoclD15590 Rev 10 d STM8S903K3 STM8S903F3 Memory and register map Table 8 General hardware register map continued Address Block Register label Register name Reset status 0x00 5340 TIM6_CR1 TIM6 control register 1 0x00 0x00 5341 TIM6_CR2 TIM6 control register 2 0x00 0x00 5342 TIM6_SMCR ee mode contral 0x00 0x00 5343 TIM6_IER TIM6 interrupt enable register 0x00 0x00 5344 TIM6 TIM6 SR TIM6 status register 0x00 0x00 5345 TIM6 EGR bin dia generation 0x00 0x00 5346 TIM6 CNTR TIM6 counter 0x00 0x00 5347 TIM6_PSCR TIM6 prescaler register 0x00 0x00 5348 TIM6_ARR TIM6 auto reload register OxFF 0x00 5349 to 0x00 53DF Reserved area 153 bytes 0x00 53E0 to 0x00 53F3 ADC1 ADC_DBxR ADC data buffer registers 0x00 0x00 53F4 to 0x00 53FF Reserved area 12 bytes d DoclD15590 Rev 10 39
60. SI RC osc 128 kHz 0 42 0 57 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off Ly DoclD15590 Rev 10 57 121 Electrical characteristics STM8S903K3 STM8S903F3 Total current consumption in wait mode Table 25 Total current consumption in wait mode at Vpp 5 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 1 6 HSE user ext clock fcPu fMASTER 16 MHz 16 MHz 1 1 1 3 Supply HSI RC osc 16 MHz 0 89 1 1 Ippwri current in mA wait mode fcpu fuasrER 128 125 kHz HSI RC osc 16 MHz 0 7 0 88 fcpu fmasTER 5128 2 HSI RC 16 MHz 8 45 0 57 15 625 kHz a ER fepy MASTER 128 kHz LSI RC osc 128 kHz 0 4 0 54 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off Table 26 Total current consumption in wait mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 1 1 HSE user ext clock fopu fmasTER 16 MHz 16 MHz 1 1 1 3 Supply HSI RC osc 16 MHz 0 89 1 1 Ipp wrl Current in mA wait mode fopu fuasrER 128 125 kHz HSI RC osc 16 MHz 0 7 0 88 fopu fmasTER S128 2 15 625 kHz HSI RC osc 16 MHz 8 0 45 0 57 fopu fuasrER 128 kHz LSI RC osc 128 kHz 0 4 0 54 1 Data based on
61. able in each execution context 20 addressing modes including indexed indirect and relative addressing and 80 instructions Architecture and registers e Harvard architecture e 3 stage pipeline e 32 bit wide program memory bus single cycle fetching for most instructions e Xand Y 16 bit index registers enabling indexed addressing modes with or without offset and read modify write type data manipulations e 8 bit accumulator e 24 bit program counter 16 Mbyte linear memory space e 16 bit stack pointer access to a 64 K level stack e 8 bit condition code register 7 condition flags for the result of the last instruction Addressing e 20 addressing modes e Indexed indirect addressing mode for look up tables located anywhere in the address space e Stack pointer relative addressing mode for local variables and parameter passing Instruction set e 80 instructions with 2 byte average instruction size e Standard data movement and logic arithmetic functions e 8 bit by 8 bit multiplication e 16 bit by 8 bit and 16 bit by 16 bit division e Bit manipulation e Data transfer between stack and accumulator push pop with direct stack access e Data transfer using the X and Y registers or direct memory to memory transfers d DoclD15590 Rev 10 STM8S903K3 STM8S903F3 Product overview 4 2 4 3 4 4 d Single wire interface module SWIM and debug module DM The single wire interface module and debug module per
62. aced 0 01 uF with 0 1 uF in Figure 38 Recommended reset pin protection Added Figure 42 Typical application with IPC bus and timing diagram Updated footnote 1 in Table 48 ADC accuracy with RAIN 10 kW VDD 5 Vand Table 49 ADC accuracy with RAIN lt 10 kW VDD 3 3 V Updated existing footnote and added three additional footnotes to Table 55 UFQFPN32 32 pin 5x5 mm 0 5 mm pitch ultra thin fine pitch quad flat package mechanical data Updated the special marking and OPT2 alternate function remapping sections in Section 13 1 STM8S903K3 F3 FASTROM microcontroller option list DoclD15590 Rev 10 d STM8S903K3 STM8S903F3 Revision history Table 61 Document revision history continued Date Revision Changes Added note for OPT1 option list Updated OPT2 option list for STM8S903K3 and created OPT2 option list for STM8S903F3 in Section 13 1 STM8S903K3 F3 FASTROM microcontroller option list Updated UART 1 interrupt vector addresses in Table 10 Interrupt mapping Updated note related to true open drain outputs in Table 6 STM8S903K3 UFQFPN32 LQFP32 SDIP32 pin descriptions and Table 5 TSSOP20 SO20 UFQFPN20 pin descriptions Added UFQFPN20 package Removed CLK CANCCR register from Table 8 General hardware register map Added note for Px IDR registers in Table 7 I O port hardware register map Updated the caption of Figure 62 STM8S903K3 F3 access line ordering information scheme 1 Removed Typical
63. ackage information STM8S903K3 STM8S903F3 Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 50 UFQFPN32 marking example package top view Product i identification 85903K3 Date code Standard ST logo ww Revision code Dot pin 1 MS37475V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity d 94 121 DoclD15590 Rev 10 STM8S903K3 STM8S903F3 Package information 11 3 UFQFPN20 package information Figure 51 UFQFPN20 package outline D Pin 1 E TOP VIEW ddd A3 A1 BOTTOM VIEW SIDE VIEW A0A5_ME_V3 1 Drawing is not to scale Table 56 UFQFPN20 package mechanical data mm inches Dim Min Typ Max Min Typ Max 3 000 0 1181 3 000 0 1181 A 0 500 0 550 0 600 0 0197 0 0217 0 0236 A1 0 000 0 020 0 050 0 0000 0 0008 0 0020 A3 0 152 0 0060 e 0 500 0 0197 L1 0 500 0 550 0 600 0 0197 0 0217 0 0236
64. al curves 0 RR I en 51 10 4 4 Loading capacitor II 51 10 1 5 Pin input voltage nh 52 10 2 Absolute maximum ratings selle 52 10 3 Operating conditions iue car ee ee dws RR a RR ere E 54 10 3 4 VCAP external capacitor 0 00 20 56 10 3 2 Supply current characteristics eee eee eee 56 10 3 3 External clock sources and timing characteristics 65 10 3 4 Internal clock sources and timing characteristics 68 10 3 5 Memory characteristics 0 220 eee 70 10 3 6 I O port pin characteristics eee eee 71 10 3 7 Reset pin characteristics 020 eee ee eee 76 10 3 8 SPI serial peripheral interface 78 10 3 9 I2C interface characteristics llli isses 82 10 3 10 10 bit ADC characteristics llle 83 10 3 11 EMC characteristics 0 0000 c cece eee 86 Package information 0 4 eee 89 11 4 LQFP32 package information a 89 DociD 15590 Rev 10 3 121 Contents STM8S903K3 STM8S903F3 11 2 UFQFPN32 package information 92 11 3 UFQFPN2O package information 95 11 4 SDIP32 package information 97 11 5 TSSOP20 package information 99 11 6 SO20 package information 0 00 ee 101 11 7 UFQFPN recommended footprint llle 103 12 Thermal characteristics x secs mn ao xs eae RC 6 CR es 105 12 4 Reference document 105 12 2 Selecting the produ
65. best compromise between lowest power consumption fastest start up time and available wakeup sources e Wait mode In this mode the CPU is stopped but peripherals are kept running The wakeup is performed by an internal or external interrupt or reset e Active halt mode with regulator on In this mode the CPU and peripheral clocks are stopped An internal wakeup is generated at programmable intervals by the auto wake up unit AWU The main voltage regulator is kept powered on so current consumption is higher than in active halt mode with regulator off but the wakeup time is faster Wakeup is triggered by the internal AWU interrupt external interrupt or reset e Active halt mode with regulator off This mode is the same as active halt with regulator on except that the main voltage regulator is powered off so the wake up time is slower D Halt mode In this mode the microcontroller uses the least power The CPU and peripheral clocks are stopped the main voltage regulator is powered off Wakeup is triggered by external event or reset Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications Activation of the watchdog timers is controlled by option bytes or by software Once activated the watchdogs cannot be disabled by the user program without performing a reset Window watchdog timer The window watchdog is used to detect the occurrence of a software fault usually g
66. ct overview STM8S903K3 STM8S903F3 4 14 2 4 14 3 20 121 SPI e Maximum speed 8 Mbit s IMASTER 2 both for master and slave e Full duplex synchronous transfers e Simplex synchronous transfers on two lines with a possible bidirectional data line e Master or slave operation selectable by hardware or software e CRC calculation e 1 byte Tx and Rx buffer e Slave master selection input pin e PC master features Clock generation Start and stop generation e PC slave features Programmable DC address detection Stop bit detection e Generation and detection of 7 bit 10 bit addressing and general call e Supports different communication speeds Standard speed up to 100 kHz A Fast speed up to 400 kHz d DoclD15590 Rev 10 STM8S903K3 STM8S903F3 Pinouts and pin descriptions 5 Pinouts and pin descriptions Table 4 Legend abbreviations for pinout tables Type I Input O Output S Power supply Input CM CMOS Level Output HS High sink O1 Slow up to 2 MHz O2 Fast up to 10 MHz O3 Fast slow programmability with slow as default state after reset OA Fast slow programmability with fast as default state after reset Output speed float floating Input wpu weak pull up Port and control configuration T True open drain Output OD Open drain PP Push pull Bold X pin state after internal reset release Reset state Unless otherwi
67. ct temperature range 106 13 Ordering information 107 13 4 STM8S903K3 F3 FASTROM microcontroller option list 108 14 STM8 development tools 113 14 1 Emulation and in circuit debugging tools 113 14 1 4 STice key features 113 14 2 Software tools 114 14 2 1 STMB8 toolset 0 000 ee 114 14 2 2 C and assembly toolchains 0 000 eee 114 14 3 Programming tools eee 115 15 REVISION history KA da ERR ECK RN kx kc doc a ROCA ri 116 4 121 DoclD15590 Rev 10 Ly STM8S903K3 STM8S903F3 List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Ly STM8S903K3 F3 access line features 10 Peripheral clock gating bit assignments in CLK_PCKENR1 2 registers 15 TIM timer features 18 Legend abbreviations for pinout tables 00 cece ee eee 21 TSSOP20 SO20 UFQFPN2O pin descriptions 23 STM85903K3 UFQFPN32 LQFP32 SDIP32 pin descriptions 26 I O
68. e 53 SDIP32 package outline d 76 ME Table 57 SDIP32 package mechanical data mm inches Dim Min Typ Max Min Typ Max A 3 556 3 759 5 080 0 1400 0 1480 0 2000 A1 0 508 0 0200 A2 3 048 3 556 4 572 0 1200 0 1400 0 1800 B 0 356 0 457 0 584 0 0140 0 0180 0 0230 B1 0 762 1 016 1 397 0 0300 0 0400 0 0550 0 203 0 254 0 356 0 0079 0 0100 0 0140 D 27 430 27 940 28 450 1 0799 1 1000 1 1201 9 906 10 410 11 050 0 3900 0 4098 0 4350 E1 7 620 8 890 9 398 0 3000 0 3500 0 3700 e 1 778 0 0700 eA 10 160 0 4000 DoclD15590 Rev 10 97 121 Package information STM8S903K3 STM8S903F3 98 121 Table 57 SDIP32 package mechanical data continued mm inches Dim Min Typ Max Min Typ Max eB 12 700 0 5000 L 2 540 3 048 3 810 0 1000 0 1200 0 1500 1 Values in inches are converted from mm and rounded to 4 decimal digits Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 54 SDIP32 marking example package top view Product identification Revision code STMBS303K3Bb Pin 1 identifier Date code Standard ST logo MS37473V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any cons
69. e master clock 1 16 MHz high speed external crystal HSE Up to 16 MHz high speed user external clock HSE user ext 16 MHz high speed internal RC oscillator HSI 128 kHz low speed internal RC LSI e Startup clock After reset the microcontroller restarts by default with an internal 2 MHz clock HSI 8 The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts e Clock security system CSS This feature can be enabled by software If an HSE clock failure occurs the internal RC 16 MHz 8 is automatically selected by the CSS and an interrupt can optionally be generated e Configurable main clock output CCO This outputs an external clock for use by the application Table 2 Peripheral clock gating bit assignments in CLK PCKENR1 2 registers Peripheral Peripheral 3 Peripheral Peripheral EM clock all clock Si clock Bil clock PCKEN17 TIM1 PCKEN13 UART1 PCKEN27 Reserved PCKEN23 ADC PCKEN16 TIM5 PCKEN12 Reserved 8 PCKEN26 Reserved PCKEN22 AWU PCKEN15 Reserved PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved PCKEN14 TIM6 PCKEN10 DC PCKEN24 Reserved PCKEN20 Reserved a DoclD15590 Rev 10 15 121 Product overview STM8S903K3 STM8S903F3 4 6 4 7 16 121 Power management For efficient power management the application can be put in one of four different low power modes You can configure each mode to obtain the
70. enerated by external interferences or by unexpected logical conditions which cause the application program to abandon its normal sequence The window function can be used to trim the watchdog behavior to match the application perfectly The application software must refresh the counter before time out and during a limited time window A reset is generated in two situations 1 Timeout At 16 MHz CPU clock the time out period can be adjusted between 75 us up to 64 ms 2 Refresh out of window The downcounter is refreshed before its value is lower than the one stored in the window register Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures Itis clocked by the 128 kHz LSI internal RC clock source and thus stays active even in case of a CPU clock failure DoclD15590 Rev 10 Ly STM8S903K3 STM8S903F3 Product overview 4 8 4 9 4 10 4 11 d The IWDG time base spans from 60 us to 1 s Auto wakeup counter e Used for auto wakeup from active halt mode e Clock source Internal 128 kHz internal low frequency RC oscillator or external clock e LSI clock can be internally connected to TIM1 input capture channel 1 for calibration Beeper The beeper function outputs a signal on the BEEP pin for sound generation The signal is in the range of 1 2 or 4 kHz The beeper output port is only available through the alternate functi
71. equences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity d DoclD15590 Rev 10 STM8S903K3 STM8S903F3 Package information 11 5 TSSOP20 package information Figure 55 TSSOP20 package outline D fo kh Cc SEATING PLANE C GAGE PLANE PIN 1 IDENTIFICATION O aaa C E A A2 A b e YA ME V3 Table 58 TSSOP20 package mechanical data mm inches Dim Min Typ Max Min Typ Max A 1 200 S p 0 0472 A1 0 050 x 0 150 0 0020 0 0059 A2 0 800 1 000 1 050 0 0315 0 0394 0 0413 b 0 190 S 0 300 0 0075 0 0118 c 0 090 0 200 0 0035 0 0079 p2 6 400 6 500 6 600 0 2520 0 2559 0 2598 E 6 200 6 400 6 600 0 2441 0 2520 0 2598 E16 4 300 4 400 4 500 0 1693 0 1732 0 1772 e V 0 650 gt 0 0256 E L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 B k 0 0 r 8 0 0 0 8 0 aaa s 0 100 3 S 0 0039 1 Values in inches are converted from mm and rounded to 4 decimal digits 2 Dimension D does not include mold flash protrusions or gate burrs Mold flash protrusions or gate burrs shall not exceed 0 15mm per side d DoclD15590 Rev 10 99 121 Package information STM8S
72. erved TRIM EN HW HW HALT 0x00 option NHSI NLSI NIWDG NWWDG NWWG 0x4806 NOPT3 Reserved TRIM EN HW HW HALT OxFF EXT CKAWU 0x4807 m OPT4 Reserved ak eid PRSC1 PRSCO 0x00 option NEXT NCKA 0x4808 NOPTA Reserved CLK w sEL NPRSC1 NPR SCO OxFF 0x4809 HSE clock OPT5 HSECNT 7 0 0x00 0x480A Startup NOPT5 NHSECNT 7 0 OxFF Ky DoclD15590 Rev 10 45 121 Option bytes STM8S903K3 STM8S903F3 46 121 Table 12 Option byte description Option byte no OPTO Description ROP 7 0 Memory readout protection ROP OxAA Enable readout protection write access via SWIM protocol Note Refer to the family reference manual RM0016 section on Flash EEPROM memory readout protection for details OPT1 UBC 7 0 User boot code area 0x00 no UBC no write protection 0x01 Page 0 defined as UBC memory write protected Page 0 and 1 contain the interrupt vectors Ox7F Pages 0 to 126 defined as UBC memory write protected Other values Pages 0 to 127 defined as UBC memory write protected Note Refer to the family reference manual RM0016 section on Flash write protection for more details OPT2 OPT3 AFR 7 0 Refer to following section for alternate function remapping descriptions of bits 7 2 and 1 0 respectively HSITRIM High speed internal clock trimming register size 0 3 bit trimming supported in CLK HSITRIMR register 1 4 bit trimming supported in CLK HSITRIMR register LSI EN Low
73. escription 1 Port D7 alternate function TIM1_CH4 AFR7 check only one option 0 Remapping option inactive Default alternate functions used Refer to pinout description 1 Port C3 alternate function TIM1 CHIN port C4 alternate function TIM1_CH2N DoclD15590 Rev 10 d STM8S903K3 STM8S903F3 Ordering information d OTP2 alternate function remapping for STM8S903F3 Do not use more than one remapping option in the same port AFR1 AFRO check only one option 00 Remapping options inactive Default alternate functions used Refer to pinout description 01 Port C5 alternate function TIM5 CH1 port C6 alternate function TIM1 CH1 and port C7 alternate function TIM1 CH2 10 Port A3 alternate function SPI NSS and port D2 alternate function TIM5 CH3 11 Port D2 alternate function TIM5 CH3 port C5 alternate function TIM5 CH1 port C6 alternate function TIM1 CH1 port C7 alternate function TIM1 CH2 port E5 alternate function TIM1 CHIN port A3 alternate function UART1 TX and port F4 alternate function UART1 RX AFR2 Reserved AFR3 check only one option 0 Remapping option inactive Default alternate functions used Refer to pinout description 1 Port C3 alternate function TLI AFR4 check only one option 0 Remapping option inactive Default alternate functions used Refer to pinout description
74. espected If Vi maximum cannot be respected the injection current must be limited externally to the lj j piny value A positive injection is induced by Viy gt Vpp while a negative injection is induced by Viy lt Vss For true open drain pads there is no positive injection current allowed and the corresponding Vjy maximum must always be respected 4 ADC accuracy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which ma otentially inject negative current Any positive injection current within the limits specified for IINJ PIN and linu Piny in the I O port pin characteristics section does not affect the ADC accuracy 5 When several inputs are submitted to a current injection the maximum IINJ PIN is the absolute sum of the positive and negative injected currents instantaneous values These results are based on characterization with IINJ PIN maximum current injection on four I O port pins of the device Table 20 Thermal characteristics Symbol Ratings Value Unit TsrG Storage temperature range 65 to 150 C Tj Maximum junction temperature 150 DoclD15590 Rev 10 53 121 Electrical characteristics STM8S903K3 STM8S903F3 10 3 54 121 Operating condit
75. eup times n 60 Total current consumption and timing in forced reset state 61 Peripheral current consumption 2 00 eee eee eee 61 HSE user external clock characteristics 000 eee 65 HSE oscillator characteristics lille 66 HSI oscillator characteristics liliis 68 LSI oscillator characteristics llli 69 RAM and hardware registers rn 70 Flash program memory data EEPROM memory 70 I O static characteristics 2l 71 Output driving current standard porte 72 Output driving current true open drain porte 73 Output driving current high sink ports c eee eee 73 NRST pin characteristics ns 76 oSPI characteristIcs o aie cd ANA d RO NGA AREE EN LC ddan eae 78 JG characteristics u onun Macte EE 82 ADC characteristics ENNER y oe oe NA ALAN We ea on 83 ADC accuracy with Rajns I0KiMnpnsbM annnars 84 DociD 15590 Rev 10 5 121 List of tables STM8S903K3 STM8S903F3 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 6 121 ADC accuracy with Rajns I0kiVops N eee 84 EMS datane oea a i a EEEE E EE E a Ea a S E EE E E E AE 86 EMI d l 51s 22 GA raaa de Ee td DANG S ERN BARRE 87 ESD absolute maximum ratings lille 87 Electrical sensitivities 88 LQFP32 package mechanical data 90 UFQFPN32 32 pin 5x5 mm
76. evious table and the va characteristics DoclD15590 Rev 10 for O ja given in Section 12 Thermal d STM8S903K3 STM8S903F3 Electrical characteristics q Figure 10 fcpumax Versus Vpp fceu MHz Functionality not guaranteed in 46 this area 12 Functionality guaranteed Ta 40 to 125 C 8 2 95 4 0 5 0 5 5 Supply voltage MSv36469V1 Table 22 Operating conditions at power up power down Symbol Parameter Conditions Min Typ Max Unit Vpp rise time rate 2 oo bp f m us V Vpp fall time rate 5 2 o tremp Reset release delay Vpp rising 1 7 ms Power on reset Vit threshold 2 6 2 7 2 85 y Brown out reset Vu threshold 2 5 2 65 2 8 Brown out reset VHYS BOR hysteresis 70 mV 1 Reset is always generated after a trgyp delay The application must ensure that Vpp is still above the minimum operating voltage Vpp min when the trgyp delay has elapsed DoclD15590 Rev 10 55 121 Electrical characteristics STM8S903K3 STM8S903F3 10 3 1 10 3 2 VCAP external capacitor The stabilization for the main regulator is achieved by connecting an external capacitor Cexr to the VcAp pin Cgxr is specified in Table 21 Care should be taken to limit the series inductance to less than 15 nH Figure 11 External capacitor Cex7 C ESL SH Ee ESR RLeak MSv36488V1 1 ESR is the equivalent series re
77. ge and orderable part numbers or for further information on any aspect of this device please go to www st com or contact the ST Sales Office nearest to you STM8S903K3 F3 FASTROM microcontroller option list last update April 2010 Customer Address Contact qj Hunwerdecuteie E a DU F ge s Coa N E EDI E ERE Phone number FASTROM code reference 1 The FASTROM code name is assigned by STMicroelectronics The preferable format for programing code is Hex s19 is accepted If data EEPROM programing is required a separate file must be sent with the requested data See the option byte section in the datasheet for authorized option byte combinations and a detailed explanation Do not use more than one remapping option in the same port It is forbidden to enable both AFR1 and AFRO Device type memory size package check only one option FASTROM device 8 Kbyte TSSOP20 STM8S903F3 SO20W STM8S903F3 UFQFPN20 STM8S903F3 LQFP32 STM8S903K3 UFQFPN32 STM8S903K3 Conditioning check only one option Tape and reel or Tray Special marking check only one option No Yes Authorized characters are letters digits and spaces only Maximum character counts are LQFP32 2 lines of 7 characters max and j TSSOP20 1 line of 10 characters max i SO20 1 line of 13 characters max UFQFPN32 1 line of 7 charac
78. h time 4 0 0 6 i tsu SDA SDA setup time 250 100 E tn sDA SDA data hold time 0 3 o 900 3 t SDA SDA and SCL rise time ns 1000 300 t scL Vpp 3to 5 5 V tSDA SDA and SCL fall time 300 300 tscL Vpp 3to 5 5 V th STA START condition hold time 4 0 0 6 tsu STA Repeated START condition setup time 4 7 0 6 tusro STOP condition setup time 4 0 0 6 pS t STOP to START condition time 4 7 13 W STO STA bus free g z 7 Cp Capacitive load for each bus line 400 400 pF 1 faster must be at least 8 MHz to achieve max fast UC speed 400 kHz 2 Data based on standard DC protocol requirement not tested in production The maximum hold time of the start condition has only to be met if the interface does not stretch the low time 4 The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL Figure 42 Typical application with I2C bus and timing diagram Von Von 4 7 KQ j 4 7 KQ i PC bus Repeated 7 N 4 stat START 1 un mag M 1 1 Pe ig f 1 tyspa tsDA tsu sDA thspa 1 STOP 1 lt 4 f 1 SCL 1 i 1 Wi i 1 1 1 1 d i Ai tot 1 th STA tw ScLH tw scLL trscL trscL tsusto MSv36492V1 d DoclD15590 Rev 10 STM85903K3 STM85903F3 Electrical characteristics 10 3 10 10 bit ADC characteristics Subject to general operating conditions for
79. ings VEsp Electrostatic discharge voltage electrical sensitivity on page 87 All power Vpp and ground Vss pins must always be connected to the external power supply cannot be respected the injection current must be limited externally to the liy up value A positive injection is induced by Vum gt Vpp while a negative injection is induced by Vu lt Vss For true open drain pads there is no positive injection current and the corresponding Vu maximum must always be respected DoclD15590 Rev 10 liNJ pin must never be exceeded This is implicitly insured if Vy maximum is respected If Vu maximum d STM8S903K3 STM8S903F3 Electrical characteristics d Table 19 Current characteristics Symbol Ratings Max DI Unit lyppi Total current into Vppjo power lines source 100 lvssio Total current out of Vss jo ground lines sink 80 Output current sunk by any UO and control pin 20 o Output current source by any I Os and control pin 20 Injected current on any pin t4 n lINJ PIN 3 4 Injected current on OSCIN pin 4 Injected current on any other pin t4 Zlinuctot Total injected current sum of all I O and control pins t20 1 Data based on characterization results not tested in production All power Vpp and ground Vgs pins must always be connected to the external supply IiNJ piN must never be exceeded This condition is implicitly insured if Vjy maximum is r
80. ints are at CMOS levels 0 3 Vpp and 0 7 Mon Figure 40 SPI timing diagram where slave mode and CPHA 1 NSS input f s CPHAe1 y V N V 2 CPOL 0 fi hd x CPHA 1 EEN mme H jm A i ii Soja th SO lt gt BC re tds SO 4 gt i ta S0 size Pr po ilf SCK i MISO 7 aan PURUS Ko aa OUT arre out Leon OUT EEN tt sit ths MOSI Sc INPUT MSB IN BITI N LSB IN 2i14135 1 Measurement points are at CMOS levels 0 3 Vpp and 0 7 Vpp d 80 121 DoclD15590 Rev 10 STM85903K3 STM85903F3 Electrical characteristics Figure 41 SPI timing diagram master mode High NSS input 1 tsc 3 CPHA 0 5 CPOL 0 i i i Ss o n I I T x CRHA 0 l f o f SCK Output OO 32 it gi LI l CPHA 1 i n CPOL 1 NAT Alien D 1 I l l tw SCKH i EE SCK Isu MI LE tw SckL Jak di ME MISO MSCKD tL E I M th CY BITE wear OUT BIT1 OUT isor OU ai14136V2 1 Measurement points are at CMOS levels 0 3 Vpp and 0 7 Vpp Ly DocID15590 Rev 10 81 121 Electrical characteristics STM8S903K3 STM8S903F3 10 3 9 82 121 I C interface characteristics Table 46 DC characteristics Standard mode IZC Fast mode CH Symbol Parameter Unit Min Max Min Max tw SCLL SCL clock low time 4 7 1 3 us tw SCLH SCL clock hig
81. ions Table 21 General operating conditions Symbol Parameter Conditions Min Max Unit fcpu Internal CPU clock frequency 0 16 MHz Vpp Vppio _ Standard operating voltage 2 95 5 5 V Cext capacitance of external 470 3300 nF capacitor 1 VCAP ESR of external capacitor 0 3 Q at 1 MHz ESL of external capacitor 15 nH TSSOP20 182 SO20W 1000 p 9 Power dissipation UFQFPN20 E 198 D 95 mW at TA 85 C for suffix 6 LQFP32 333 UFQFPN32 526 SDIP32 333 TSSOP20 45 SO20W 250 3 Power dissipation UFQFPN20 49 Pp dom mW at TA 125 C for suffix 3 LQFP32 83 UFQFPN32 132 SDIP32 83 Ambient temperature for suffix Maximum power TA REL 40 85 6 version dissipation Ta Ambient temperature for suffix Maximum power Ap 125 ge 3 version dissipation Suffix 6 version 40 105 Tj Junction temperature range Suffix 3 version 40 130 1 Care should be taken when selecting the capacitor due to its tolerance as well as the parameter dependency on temperature DC bias and frequency in addition to other factors The parameter maximum value must be respected for the full application range This frequency of 1 MHz as a condition for VcAp parameters is given by design of internal regulator To calculate Ppmax TA use the formula Ppmax TJmax TAYO dp see Section 12 Thermal characteristics ue with the value for T jmax given in the pr
82. istics STM8S903K3 STM8S903F3 HSE crystal ceramic resonator oscillator The HSE clock can be supplied using a crystal ceramic resonator oscillator of up to 16 MHz All the information given in this paragraph is based on characterization results with specified typical external components In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonator manufacturer for more details frequency package accuracy Table 35 HSE oscillator characteristics 1 Cis approximately equivalent to 2 x crystal Cload 2 The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value Refer to crystal manufacturer for more details Data based on characterization results not tested in production tsu Hse is the start up time measured from the moment it is enabled by software to a stabilized 16 MHz oscillation is Symbol Parameter Conditions Min Typ Max Unit External high speed fuse oscillator frequency S 7 1 MHz Rp Feedback resistor 220 kQ c t E load E 20 pF capacitance C 20 pF 6 start up HSE oscillator power fosc 16 MHz 1 6 stabilized Ipp HsE ti mA consumption C 10 pF 6 start up fosc 16 MHz 1 2 stabilized 9 Oscillator 9m transconductance O O O Lid tsu HsE Star
83. le prescaler ratio to any power of 2 from 1 to 128 e Clock source CPU clock e Interrupt source 1 x overflow update e Synchronization module to control the timer with external signals or to synchronize with TIM1 or TIM5 Table 3 TIM timer features Counter Counting CAPCOM Ext Timor Timer P Prescaler Complementary synchronization size bits mode channels trigger em outputs chaining Any integer TIM1 from 1 to Up down 4 3 Yes 65536 Any power of TIM5 2 from 1 to Up 3 0 No Yes 32768 Any power of TIM6 2 from 1 to Up 0 0 No 128 4 13 Analog to digital converter ADC1 The STM8S903K3 F3 family products contain a 10 bit successive approximation A D converter ADC1 with up to 7 external and 1 internal multiplexed input channels and the following main features e Input voltage range 0 to VDD e Conversion time 14 clock cycles e Single and continuous and buffered continuous conversion modes e Buffer size n x 10 bits where n number of input channels e Scan mode for single and continuous conversion of a sequence of channels e Analog watchdog capability with programmable upper and lower thresholds e Internal reference voltage on channel AIN7 e Analog watchdog interrupt e External trigger input e Trigger from TIM1 TRGO e End of conversion EOC interrupt Internal bandgap reference voltage Channel AIN7 is internally connected to the internal bandgap reference voltage The internal bandgap reference is constant and can be used for examp
84. le to monitor Vpp It is independent of variations in Vpp and ambient temperature Ty 18 121 DoclD15590 Rev 10 Ly STM8S903K3 STM8S903F3 Product overview 4 14 4 14 1 d Communication interfaces The following communication interfaces are implemented e UART1 Full feature UART synchronous mode SPI master mode SmartCard mode IrDA mode single wire mode LIN2 1 master capability e SPI Full and half duplex 8 Mbit s e lC Upto 400 kbit s UART1 Main features e One Mbit s full duplex SCI e SPI emulation e High precision baud rate generator e SmartCard emulation e IrDA SIR encoder decoder e LIN master mode e Single wire half duplex mode Asynchronous communication UART mode e Full duplex communication NRZ standard format mark space e Programmable transmit and receive baud rates up to 1 Mbit s fCPU 16 and capable of following any standard baud rate regardless of the input frequency e Separate enable bits for transmitter and receiver e Two receiver wakeup modes A Address bit MSB dle line interrupt e Transmission error detection with interrupt generation e Parity control Synchronous communication e Full duplex synchronous transfers e SPI master operation e 8 bit data communication e Maximum speed 1 Mbit s at 16 MHz fCPU 16 LIN master mode e Emission Generates 13 bit synch break frame e Reception Detects 11 bit break frame DoclD15590 Rev 10 19 121 Produ
85. mer 1 channel E out slave in 28 23 TIM1 CH1 lO X X X HS O3 X X Port C6 t sl 4 IAFRO PC7 SPI MISO SPI master in Timer 1 channel M slave ou 29 24 TIM1 CH2 lO X X X HS O3 X X Port C7 t 2 AFRO PDO Timer 1 break Configurable 30 25 TIM1 BKIN lO X X X HS O3 X X Port DO int clock output CLK CCO P AFR5 31 26 Pb swM vo x X x Hs 04 x X Portp1 SWIM data interface Analog input 3 PD2 AIN3 AFR2 Timer 5 O channe 32 27 TIM5 CH lO X X X HS O3 X X Port D2 h 13 AFR1 PD3 AIN4 EECHER 1 28 tims CH vol x x x Hs o3 x X Potpa Timers E ADC ETR channel 2 ADC external trigger dd Timer 5 TIM5 CH1 UART clock 2 29 BEEP lO X X X HS O3 X X Port D4 1 BEEP AFR2 UART4 CK P Analog input 5 3 30 jud lO X X X HS O3 X X PortD5 UART1 data transmit 28 121 DoclD15590 Rev 10 ky STM8S903K3 STM85903F3 Pinouts and pin descriptions Table 6 STM8S903K3 UFQFPN32 LQFP32 SDIP32 pin descriptions continued e Input Output s E 5o 3 S Sg Ble 55 55 FF amp H 1 g Oo 3 x eo 22 abt a2 Pin name S 2 3 E Ss BANA S sS eos a SI ale a d o z HEE NG 8 5 5 2 4 79 8 55 3 TE Lu r a d Analog input 6 PD6 AIN6 4 31 UART1 RX VO X X X HS 03 X X Port DG UART1 data E receive Timer 1 5 32 PD7 TLI vol XI X X Hs o3 x x PortD7 Top level eben TIM1 CH4 interrupt AFR6 1
86. mits non intrusive real time in circuit debugging and fast memory programming SWIM Single wire interface module for direct access to the debug module and memory programming The interface can be activated in all device operation modes The maximum data transmission speed is 145 bytes ms Debug module The non intrusive debugging module features a performance close to a full featured emulator Beside memory and peripherals also CPU operation can be monitored in real time by means of shadow registers e R W to RAM and peripheral registers in real time e R W access to all resources by stalling the CPU e Breakpoints on all program memory instructions software breakpoints e Two advanced breakpoints 23 predefined configurations Interrupt controller e Nested interrupts with three software priority levels e 32 interrupt vectors with hardware priority e Up to 28 external interrupts on 7 vectors including TLI e Trap and reset interrupts Flash program and data EEPROM memory e 8Kbytes of Flash program single voltage Flash memory e 640 bytes true data EEPROM e User option byte area Write protection WP Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction There are two levels of write protection The first level is known as MASS memory access security system MASS is always enabled and protects the main Flash p
87. n OSCIN OPT5 crystal oscillator stabilization HSECNT check only one option 2048 HSE cycles 128 HSE cycles 8 HSE cycles 0 5 HSE cycles OTP6 is reserved Oo 11 10 CN Supply operating range in the application sssssssssssssssseseeeseeene nennen enne Notes d 112 121 DoclD15590 Rev 10 STM85903K3 STM8S903F3 STM8 development tools 14 14 1 141 1 d STM8 development tools Development tools for the STM8 microcontrollers include the full featured STice emulation System supported by a complete software tool package including C compiler assembler and integrated development environment with high level language debugger In addition the STMB is to be supported by a complete range of tools including starter kits evaluation boards and a low cost in circuit debugger programmer Emulation and in circuit debugging tools The STice emulation system offers a complete range of emulation and in circuit debugging features on a platform that is designed for versatility and cost effectiveness In addition STMB8 application development is supported by a low cost in circuit debugger programmer The STice is the fourth generation of full featured emulators from STMicroelectronics It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application
88. n this family as low density They provide the following benefits performance robustness and reduced system cost Device performance and robustness are ensured by advanced core and peripherals made in a state of the art technology a 16 MHz clock frequency robust I Os independent watchdogs with separate clock source and a clock security system The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k write erase cycles and a high system integration level with internal clock oscillators watchdog and brown out reset Full documentation is offered as well as a wide choice of development tools Table 1 STM8S903K3 F3 access line features Device STM8S903K3 STM8S903F3 Pin count 32 20 ie number of GPIOs 28 1 162 Ext interrupt pins 28 16 Timer CAPCOM channels 7 Timer complementary outputs 3 2 A D converter channels 7 5 High sink I Os 21 12 Low density Flash program memory bytes ak Data EEPROM bytes 640 3 RAM bytes 1K Peripheral set Multipurpose timer TIM1 SPI I2C UART window WDG independent WDG ADC PWM timer TIM5 8 bit timer TIM6 1 Including 21 high sink outputs 2 Including 12 high sink outputs 3 No read while write RWW capability DoclD15590 Rev 10 d STM8S903K3 STM8S903F3 Block diagram 3 Block diagram Figure 1 STM8S903K3 F3 block diagram
89. om wait twu wrl mode to run mode 2 0 to 16 MHz 3 See note Wakeup time from run WUWF modal fopu fmaster 16 MHz 0 56 Wakeup time active halt MVR voltage mash it HSI after 6 6 tWu AH 2 4 operating 4 6 2 6 mode to run mode 2 regulator on 5 wakeup mode i Wakeup time active halt MVR voltage mn HSI after 6 WU AH mode to run mode regulator op P e wakeup mode Flash i m i Wakeup time active halt MVR voltage o KA HSI after 6 WU AH mode to run mode 2 regulator off 4 P 5 wakeup m mode Wakeup time active halt MVR voltage aL NM HSI after 6 E WUIAH mode to run mode regulator off POWELSOMN wakeup 5 t Wakeup time from Pat rett in operating mode 52 i i WU mode to run mode 2 p 3 t EEN Flash in power down modell 54 i e WIR mode to run mode 2 n 1 Data based on characterization results not tested in production 60 121 DoclD15590 Rev 10 d STM8S903K3 STM8S903F3 Electrical characteristics oa FON d Total current consumption and timing in forced reset state Measured from interrupt event to interrupt vector fetch twurwrl 2 X t fmaster 67 x 1 fcpu Configured by the REGAH bit in the CLK ICKR register Configured by the AHALT bit in the FLASH CR1 register Plus 1 LSI clock depending on synchronization Table 32 Total current consumption and timing in forced reset state Symbol
90. on lot over the full temperature range where 95 of the devices have an error less than or equal to the value indicated mean x 2 2 Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 8 Figure 8 Pin loading conditions STM8S PIN 50 pF MSv36480V1 DoclD15590 Rev 10 51 121 Electrical characteristics STM8S903K3 STM8S903F3 10 1 5 10 2 52 121 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 9 Figure 9 Pin input voltage STM8S PIN MSv36481V1 Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 18 Voltage characteristics Symbol Ratings Min Max Unit Vppx Vss Supply voltage including VppA and Vppio 0 3 6 5 V Input voltage on true open drain pins Vss 0 3 6 5 G Input voltage on any other pin Vss 0 3 Vpp 0 3 Vppx Vppl Variations between different power pins 50 IVssx Vss Variations between all the different ground pins 50 ini see Absolute maximum rat
91. on remap option bit AFRT TIM1 16 bit advanced control timer This is a high end timer designed for a wide range of control applications With its complementary outputs dead time control and center aligned PWM capability the field of applications is extended to motor control lighting and half bridge driver e 16 bit up down and up down autoreload counter with 16 bit prescaler e Four independent capture compare channels CAPCOM configurable as input capture output compare PWM generation edge and center aligned mode and single pulse mode output e Synchronization module to control the timer with external signals or to synchronize with TIM5 or TIM6 e Break input to force the timer outputs into a defined state e Three complementary outputs with adjustable dead time e Encoder mode e Interrupt sources 3 x input capture output compare 1 x overflow update 1 x break TIM5 16 bit general purpose timer e 16 bit autoreload AR up counter e 15 bit prescaler adjustable to fixed power of 2 ratios 1 32768 e 3individually configurable capture compare channels e PWM mode e Interrupt sources 3 x input capture output compare 1 x overflow update e Synchronization module to control the timer with external signals or to synchronize with TIM1 or TIM6 DoclD15590 Rev 10 17 121 Product overview STM85903K3 STM8S903F3 4 12 TIM6 8 bit basic timer e 8 bit autoreload adjustab
92. or versions of this document 2015 STMicroelectronics All rights reserved d DoclD15590 Rev 10 121 121
93. ormation replaced package pitch digit by VFQFPN UFQFPN package and added footnote regarding possible future release of a dedicated ordering information scheme Added SO20W TSSOP20 SDIP32 and UFQFPN32 Added Section 13 1 STM8S903K3 F3 FASTROM microcontroller option list Modified PD at TA 85 C for SO20W in Table 21 General operating conditions 30 Apr 2010 4 d DoclD15590 Rev 10 117 121 Revision history STM8S903K3 STM8S903F3 118 121 Table 61 Document revision history continued Date 08 Sep 2010 Revision Changes Removed VFQFPN32 package Updated the definition for reset state in Table 4 Legend abbreviations for pinout tables Updated pins 13 25 20 14 26 21 19 32 27 1 2 29 2 3 30 and 3 4 31 added footnote to PD1 SWIM pin in Table 6 STM8S903K3 UFQFPN32 LQFP32 SDIP32 pin descriptions Standardized all reset state values updated the reset state values of RST_SR CLK_SWCR CLK_HSITRIMR CLK_SWIMCCR IWDG_KR and ADC_DRx registers in Table 8 General hardware register map Changed the caption of Table 13 STM8S903K3 alternate function remapping bits 7 2 for 32 pin packages Added Table 14 STM8S903F38 alternate function remapping bits 7 2 for 20 pin packages Changed the caption of Table 15 STM8S903K3 alternate function remapping bits 1 0 for 32 pin packages Added Table 16 STM8S90SF3 alternate function remapping bits 1 0 for 20 pin packages Repl
94. osc 970 current in mode 16 MHz UA DD AH active halt moda Power down LSI RC osc 128 kHz 150 200 230 mode Operating mode LSI RC osc 128 kHz 66 80 105 Off Power down LSI RC osc 128 kHz 10 18 35 mode 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK_ICKR register 3 Configured by the AHALT bit in the FLASH CR1 register Ly DoclD15590 Rev 10 59 121 Electrical characteristics STM8S903K3 STM8S903F3 Total current consumption in halt mode Table 29 Total current consumption in halt mode at Vpp 5 V Max at Maxat Symbol Parameter Conditions Typ 85 ci gs ef Unit Flash in operating mode HSI 63 75 105 Supply current in halt clock after wakeup UA DD H qe mode Flash in power down mode 6 0 20 55 HSI clock after wakeup 1 Data based on characterization results not tested in production Table 30 Total current consumption in halt mode at Vpp 3 3 V Max at Max at Symbol Parameter Conditions Typ 85 ci 85 cl Unit Flash in operating mode HSI 60 75 100 Supply current in halt Clock after wakeup HA DD H en mode Flash in power down mode 45 17 30 HSI clock after wakeup i 1 Data based on characterization results not tested in production Low power mode wakeup times Table 31 Wakeup times Symbol Parameter Conditions Typ Max Unit Wakeup time fr
95. otprint for on board emulation 0 5m vn e 0 8mm T 0 032 4mm 0 157 1 65mm 0 065 c 0 9mm 0 035 0 3mm 0 012 4mm 0 157 Bottom view ai15319 Ly DoclD15590 Rev 10 103 121 Package information STM85903K3 STM8S903F3 104 121 Figure 61 UFQFPN recommended footprint without on board emulation Se poore Ke mga 7 m ma 2 30 c LT i Hrs 3 kK 330 E oso 1 ga MS36498V1 DoclD15590 Rev 10 STM85903K3 STM8S903F3 Thermal characteristics 12 12 1 d Thermal characteristics The maximum junction temperature T Jmax of the device must never exceed the values specified in Table 21 General operating conditions otherwise the functionality of the device cannot be guaranteed The maximum junction temperature T jmax in degrees Celsius may be calculated using the following equation TJmax Tamax PDmax X Oja Where e Tamax is the maximum ambient temperature in C e OjyAis the package junction to ambient thermal resistance in C W Ppmax is the sum of Pintmax and Pijomax PDmax Pintmax Promax e Pintmax S the product of Ipp and Vpp expressed in Watts This is the maximum chip internal power e Pyomax represents the maximum power dissipation on output pins Where Promax Vor Jo Vpp Vou lon taking into account the actual Ve lo and Voy loy of the I Os at
96. port hardware register map ne 32 General hardware register map 33 CPU SWIM debug module interrupt controller registers 41 Interrupt mapping RR 3 hs 43 Option bytes csi ce se ees EIERE a ENER der add EEN RR dn n RO DR cR dU 45 Option byte description 46 STM8S903K3 alternate function remapping bits 7 2 for 32 pin packages 47 STM8S903F3 alternate function remapping bits 7 2 for 20 pin packages 48 STM8S903K3 alternate function remapping bits 1 0 for 32 pin packages 48 STM8S903F3 alternate function remapping bits 1 0 for 20 pin packages 49 Unique ID registers 96 bits llle RII 50 Voltage characteristics llle 52 Current characteristics 000000 53 Thermal characteristics ls 53 General operating conditions 54 Operating conditions at power up power down 55 Total current consumption with code execution in run mode at Vpp 2 5 V 56 Total current consumption with code execution in run mode at Vpp 2 3 3V 57 Total current consumption in wait mode at Vpp zb 58 Total current consumption in wait mode at Vpp 2 32N 0 000002 58 Total current consumption in active halt mode at Vpp 25V a 59 Total current consumption in active halt mode at Vpp zc3 2N a 59 Total current consumption in halt mode at Vpp 75V 2 60 Total current consumption in halt mode at Vpp 2 33V 60 Wak
97. racy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for IINJ PIN and YliNJ piv in Section 10 3 6 does not affect the ADC accuracy Figure 43 ADC accuracy characteristics A dE 1022 4 ise sD P8 1021 IDEAL 1024 e 777 2 wa E 7 P eg 1 A 1 Zi 6 f M s di 5 1 zl ng E 7 SH ie 1 ze a AL Ep 24 nme lt gt NUN E 1 LSBipEaL al HILL ol 234567 1021102210231024 Vssa VDDA 1 2 3 Example of an actual transfer curve The ideal transfer curve End point correlation line ET Total unadjusted error maximum deviation between the actual and the ideal transfer curves Eo Offset error deviation between the first actual transition and the first ideal one Eg Gain error deviation between the last ideal transition and the last actual one Ep Differential linearity error maximum deviation between actual steps and the ideal one E Integral linearity error maximum deviation between any actual transition and the end point correlation line Figure 44 Typical application with ADC
98. rking example package top view 101 SO20 package outline 101 S020 marking example package top view cee eee eee eee 102 UFQFPN recommended footprint for on board emulation 103 UFQFPN recommended footprint without on board emulation 104 STM8S903K3 F3 access line ordering information scheme 107 d DoclD15590 Rev 10 STM8S903K3 STM8S903F3 Introduction 1 Introduction This datasheet contains the description of the device features pinout electrical characteristics mechanical data and ordering information e For complete information on the STM8S microcontroller memory registers and peripherals please refer to the STM8S microcontroller family reference manual RM0016 e For information on programming erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual PM0051 e For information on the debug and SWIM single wire interface module refer to the STM8 SWIM communication protocol and debug module user manual UM0470 e For information on the STM6 core please refer to the STM8 CPU programming manual PM0044 DoclD15590 Rev 10 9 121 d Description STM8S903K3 STM8S903F3 2 10 121 Description The STM8S903K3 F3 access line 8 bit microcontrollers offer 8 Kbytes Flash program memory plus integrated true data EEPROM The STM8S microcontroller family reference manual RM0016 refers to devices i
99. rogram memory data EEPROM and option bytes To perform in application programming IAP this write protection can be removed by writing a MASS key sequence in a control register This allows the application to write to data EEPROM modify the contents of main program memory or the device option bytes A second level of write protection can be enabled to further protect a specific area of memory known as UBC user boot code Refer to the figure below The size of the UBC is programmable through the UBC option byte in increments of 1 page 64 byte block by programming the UBC option byte in ICP mode DoclD15590 Rev 10 13 121 Product overview STM8S903K3 STM8S903F3 This divides the program memory into two areas e Main program memory Up to 8 Kbytes minus UBC e User specific boot code UBC Configurable up to 8 Kbytes The UBC area remains write protected during in application programming This means that the MASS keys do not unlock the UBC area It protects the memory used to store the boot program specific code libraries reset and interrupt vectors the reset routine and usually the IAP and communication routines Figure 2 Flash memory organization Data Data memory area 640 bytes EEPROM memory Option bytes Programmable area UBC area from 64 bytes Remains write protected during IAP 1 page up to 8 Kbytes in 1 page steps Low density Flash program memory 8 Kbytes i Program memor
100. s register 0x02 0x00 5204 xd SPI DR SPI data register 0x00 0x00 5205 SPI CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI RXCRCR SPI Rx CRC register OxFF 0x00 5207 SPI TXCRCR SPI Tx CRC register OxFF 34 121 DoclD15590 Rev 10 Ky STM8S903K3 STM8S903F3 Memory and register map Table 8 General hardware register map continued Address Block Register label Register name Reset status 0x00 5208 to 0x00 520F Reserved area 8 bytes 0x00 5210 I2C_CR1 I2C control register 1 0x00 0x00 5211 DC CR2 I2C control register 2 0x00 0x00 5212 DC FREQR I2C frequency register 0x00 0x00 5213 DC OARL I2C Own address register low 0x00 0x00 5214 GC OARH n address register eem 0x00 5215 Reserved 0x00 5216 DC DR I2C data register 0x00 0x00 5217 DC DC SR1 I2C status register 1 0x00 0x00 5218 DC SR2 I2C status register 2 0x00 0x00 5219 DC SR3 I2C status register 3 0x0X 0x00 521A I2C_ITR I2C interrupt control register Ox00 0x00 521B DC CCRL I2C Clock control register low 0x00 0x00 521C DC CCRH I2C Clock control register high Ox00 0x00 521D DC TRISER I2C TRISE register 0x02 0x00 521E GC PECH See error checking 0x00 0x00 521F to 0x00 522F Reserved area 17 bytes 0x00 5230 UART1 SR UART1 status register OxCO 0x00 5231 UART1 DR UART1 data register OxXX 0x00 5232 UART1 BRR1 UART baud rate register 1 0x00 0x
101. se specified the pin state is the same during the reset phase and after the internal reset release 5 1 STM8S903F3 TSSOP20 SO20 pinout Figure 3 STM8S903F3 TSSOP20 SO20 pinout TIM5_CH1 UART1_CK BEEP PD4 HS L AIN5 UART1_TX PD5 HS CI AIN6 UART1 RX PD6 HS c e 20 EI PD3 HS AINA TIM2 CH2 ADC ETR 19 FI PD2 HS AIN3 TIM2 CH3 18 EI PD1 HS SWIM 4 2 3 NRST CHA 17 L2 PC7 HS SPI_MISO TIM1 CH2 OSCIN PA1 C 5 16 1 PC6 HS SPI_MOSI TIM1 CH1 OSCOUT PA2 6 15 FI PC5 HS SPI SCK TIM2 CH1 Vss X7 14 FI PC4 HS TIM1_CH4 CLK_CCO AIN2 TIM1 CH2N VCAP L8 13 KI PC3 HS TIM1 CH3 TLI TIM1 CH1N Von CI 9 12 F3 PB4 T I2C SCL ADC ETR SPI NSSJ TIMS CH3 PA3 HS C 10 1 PB5 T TIM1 BKIN I2C SDA MSv37454V1 HS high sink capability T True open drain P buffer and protection diode to Vpp not implemented 3 J alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function Ly DoclD15590 Rev 10 21 121 Pinouts and pin descriptions STM8S903K3 STM85903F3 5 2 STM8S903F3 UFQFPN20 pinout Figure 4 STM8S903F3 UFQFPN20 pinout 5 CH2 ADC ETR PD2 HSYAIN3 TIM5 CH3 PD4 HS BEEP TIM5 CH1 UART1 CK PD6 HSYAIN6 UART1 RX PD5 HSyAINS UART1 TX PD3 HS AIN4 TIM S 5 20 1 5 NRST 1507 PD1 HS SWIM OSCIN PA1 N 14 71 PC7 HS SPI_MISO
102. sistance and ESL is the equivalent inductance Supply current characteristics The current consumption is measured as illustrated in Figure 9 Pin input voltage Supply current consumption in run mode The MCU is placed under the following conditions e A I O pins in input mode with a static value at Vpp or Vss no load e All peripherals are disabled clock stopped by peripheral clock gating registers except if explicitly mentioned Subject to general operating conditions for Vpp and Ty Table 23 Total current consumption with code execution in run mode at Vpp 5 V Symbol IDD RUN 56 121 Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 2 3 HSE user ext clock fopu fuaster 16 MHz 16 MHz 2 2 35 Supply HSI RC osc 16 MHz 1 7 2 current in Run mode HSE user ext clock P 16 MHz 0 86 mA code fopu fmasTER 128 125 kHz executed HSI RC osc 16 MHz 0 7 0 87 from RAM fopu fuasrER 128 HSI R 16 MHz 8 0 46 0 58 15 625 kHz SR St fcPu fmasTtER 128 kHz LSI RC osc 128 kHz 0 41 0 55 d DoclD15590 Rev 10 STM8S903K3 STM8S903F3 Electrical characteristics Table 23 Total current consumption with code execution in run mode at Vpp 5 V continued Symbol Parameter Conditions Typ Max 1 Unit HSE crystal osc 16 MHz 4 5
103. st conforms to the JESD22 A114A A115A standard For more details refer to the application note AN1181 Table 52 ESD absolute maximum ratings Maximum Symbol Ratings Conditions Class 1 Unit value V Electrostatic discharge voltage T a 25 C conforming to A 4000 ESD HBM Human body model JESD22 A114 a Ta 25 C conforming to V Electrostatic discharge voltage VESD CDM Charge device See aa Iv 1990 LQFP32 package 1 Data based on characterization results not tested in production Static latch up Two complementary static tests are required on 10 parts to assess the latch up performance e A Supply overvoltage applied to each power supply pin and e A current injection applied to each input output and configurable UO pin are performed on each sample DoclD 15590 Rev 10 87 121 88 121 Electrical characteristics STM8S903K3 STM8S903F3 This test conforms to the EIA JESD 78 IC latch up standard For more details refer to the application note AN1181 Table 53 Electrical sensitivities Symbol Parameter Conditions Class Ta 25 C A LU Static latch up class Ta 85 C A Ta 125 C A 1 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the JEDEC specifications that means when a device belongs to class A it exceeds the JEDEC standard B class strictly covers all the JEDEC criteria international standard
104. t prescaler e Auto wake up timer e Window watchdog and independent watchdog timers Communication interfaces e UART with clock output for synchronous operation SmartCard IrDA LIN master mode e SPlinterface up to 8 Mbit s e 2C interface up to 400 kbit s Analog to digital converter ADC e 10 bit 1 LSB ADC with up to 7 multiplexed channels 1 internal channel scan mode and analog watchdog Os e Up to 28 I Os on a 32 pin package including 21 high sink outputs e Highly robust I O design immune against current injection Unique ID e 96 bit unique key for each device DoclD15590 Rev 10 1 121 This is information on a product in full production www st com Contents STM85903K3 STM8S903F3 Contents 1 Introduction acu Ser EE BRR le a le AKA KB AMAG 9 2 Description aci ick x e ti ai ei ica Re REC a E Rc ded 10 3 Block diagram e EINEN uam ORE c aa od Ro ENNEN ee ee e 11 4 Product overview oie asinine eaten UR Imm oe ere we ae a ERR SEN 12 4 1 Central processing unit STM8 0 00 0 eee eee 12 4 2 Single wire interface module SWIM and debug module DM 13 4 3 Interrupt controller 13 4 4 Flash program and data EEPROM memory 0000 0 0 13 4 5 Clock controller ee 15 4 6 Power management AG 16 4 7 Watchdog timers us KABA MAAM EAR ER EE ee EE KAKA es 16 4 8 Auto wakeup counter les 17 4 9 Beeper m TET 17 410 TIM1 16 bit advanced control timer 17
105. tal in 8 3 PA2 OSCOUT vo X X X O1 X X PortA2 Pesonator crystal out 9 4 VSS S Digital ground 10 5 VCAP S 1 8 V regulator capacitor 11 6 VDD s Digital power supply 26 121 DoclD15590 Rev 10 Ly STM8S903K3 STM8S903F3 Pinouts and pin descriptions Table 6 STM8S903K3 UFQFPN32 LQFP32 SDIP32 pin descriptions continued a Input Output o c eo c Ki 9 E 95 2 Seon N G a 5o 96 Seo Pl 2 3 c9 s Foc 5 5 Pin name E e 3 5 g a EA S g oto 2 amp 2 Ki o n o Se ke JE Es 8 s E 8 0 q 5d g2 e23 s 2 E Fo got GIE a E SPI master PA3 TIM5_CH3 Timer 5 channel slave select 12 7 SPI_NSS lO X X X HS 03 X X Port A3 3 AFR1 UART1 UART1 TX data transmit AFR 1 0 DEA UART71 data TRI SUD ARTI RA die d JE 01 X jX PortF4 i receive AFR1 0 14 9 PB7 uo X X X 01 X X Port B7 15 10 PB6 uo X X X 01 X X Port B6 PB5 DC SDA Timer 1 break 161101 rima Bran n m 207 per de TI POMS 12G data input AFR4 PB4 12C SCL ADC external 17 12 ADC ETR IS XI IX 01 T Port BA I2C clock trigger AFR4 PB3 Analog input 3 18 13 AIN3 TIM1 ETR I O X X X Hs 03 X X Port B3 Timer 1 external trigger Analog input 2 PB2 AIN2 Timer 1 19 14 mW cH3N yo X ug O3 X X Port B2 verted channel 3 Analog input 1
106. ternate function TIM1 CH1 and port C7 alternate function TIM1_CH2 10 Port A3 alternate function SPI_NSS and port D2 alternate function TIM5 CH3 11 Port D2 alternate function TIM5 CH3 port C5 alternate function TIM5 CH1 port C6 alternate function TIM1 CH1 port C7 alternate function TIM1 CH2 port C2 alternate function TIM1 CH3N port C1 alternate function TIM1 CH2N port E5 alternate function TIM1 CHIN port A3 alternate function UART1 TX and port F4 alternate function UART1 RX AFR2 check only one option 0 Remapping option inactive Default alternate functions used Refer to pinout description 1 Port C4 alternate function AIN2 port D2 alternate function AIN3 port D4 alternate function UART1 CK AFR3 check only one option 0 Remapping option inactive Default alternate functions used Refer to pinout description 1 Port C3 alternate function TLI AFR4 check only one option 0 Remapping option inactive Default alternate functions used Refer to pinout description 1 Port B4 alternate function ADC ETR port B5 alternate function TIM1 BKIN AFR5 check only one option 0 Remapping option inactive Default alternate functions used Refer to pinout description 1 Port DO alternate function CLK CCO AFR6 check only one option 0 Remapping option inactive Default alternate functions used Refer to pinout d
107. ters Table 9 CPU SWIM debug module interrupt controller registers Address Block Register label Register name Heset status 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 0x00 7F05 cpu XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x03 0x00 7F09 SPL Stack pointer low OxFF 0x00 7FOA CCR Condition code register 0x28 0x00 7F0B to 0x00 7F5F Reserved area 85 bytes 0x00 7F60 CPU CFG_GCR Eed eech 0x00 register 0x00 7F70 ITC SPR1 Interrupt software priority eps register 1 0x00 7F71 ITC_SPR2 Interrupt software priority opf register 2 0x00 7F72 ITC SPR3 Interrupt software priority Jee register 3 0x00 7F73 ITC_SPR4 Interrupt software priority opf E register 4 ITC 0x00 7F74 ITC_SPR5 Interrupt software priority epp register 5 0x00 7F75 ITC_SPR6 Interrupt software priority nec E register 6 0x00 7F76 ITC SPR7 Interrupt software priority opf B register 7 0x00 7F77 ITC_SPR8 Interrupt software priority opf register 8 0x00 7F78 to 0x00 7F79 Reserved area 2 bytes 0x00 7F80 SWIM SWIM CSR GEIER 0x00 register 0x00 7F81 to 0x00
108. ters max UFQFPN20 1 line of 4 characters max d DoclD15590 Rev 10 STM8S903K3 STM8S903F3 Ordering information Three characters are reserved for code identification Temperature range 40 C to 85 C or 40 C to 125 C Padding value for unused program memory check only one option OxFF Fixed value 0x83 TRAP instruction code 0x75 Illegal opcode causes a reset when executed OTPO memory readout protection check only one option Disable or Enable OTP1 user boot code area UBC Ox __ fill in the hexadecimal value referring to the datasheet and the binary format below UBC bito 0 Reset det 1 Set 0 Reset UBC bit1 1 Set 0 Reset UBC bit2 1 Set UBC bit3 0 Reset E 1 Set 0 Reset UBC bit4 1 Set UBC bit5 0 Reset ge 1 Set 0 Reset UBC bit6 1 Set UBC bit7 0 Reset Pu 1 Set Note If the UBC area is not used please select all bits at reset states Ly DoclD15590 Rev 10 109 121 Ordering information STM8S903K3 STM8S903F3 110 121 OTP2 alternate function remapping for STM8S903K3 Do not use more than one remapping option in the same port AFR1 AFRO check only one option 00 Remapping options inactive Default alternate functions used Refer to pinout description 01 Port C5 alternate function TIM5 CH1 port C6 al
109. tronics that includes ST Visual Develop STVD IDE and the ST Visual Programmer STVP software interface STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8 which are available in a free version that outputs up to 16 Kbytes of code STM8 toolset The STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www st com This package includes ST visual develop Full featured integrated development environment from STMicroelectronics featuring e Seamless integration of C and ASM toolsets e Full featured debugger e Project management e Syntax highlighting editor e Integrated programming interface e Support of advanced emulation features for STice such as code profiling and coverage ST visual programmer STVP Easy to use unlimited graphical interface allowing read write and verification of the STM8 Flash program memory data EEPROM and option bytes STVP also offers project mode for the saving of programming configurations and the automation of programming sequences C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment making it possible to configure and control the building of user applications directly from an easy to use graphical interface Available toolchains include C compiler for STM8 Available in a free version that outputs up to 16
110. tup time Vpp is stabilized 1 ms reached This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer 66 121 DoclD15590 Rev 10 d STM8S903K3 STM8S903F3 Electrical characteristics Figure 19 HSE oscillator circuit diagram Resonator CL1 OSCIN fuse to core gt Resonator Consumption control CL2 OSCOUT STM8 MS36490V1 HSE oscillator critical g equation Imcri Rm Notional resistance see crystal specification Lm Notional inductance see crystal specification Cm Notional capacitance see crystal specification 0 2x1 x fysg x R 2Co 4 C Co Shunt capacitance see crystal specification C 4 Cj C Grounded external capacitance 9m Imcrit d DoclD15590 Rev 10 67 121 Electrical characteristics STM8S903K3 STM8S903F3 10 3 4 Internal clock sources and timing characteristics Subject to general operating conditions for Vpp and Ta High speed internal RC oscillator HSI Table 36 HSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fusi Frequency 16 MHz User trimmed with Accuracy of HSI oscillator CLE HSITRIMR registenior 12 given Vpp and Ta conditions Vpp 5 V ACCus TA 25 c 1 0 1 0 HSI oscillator accuracy Vpp
111. typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Prequalification trials Most of the common failures unexpected reset and program counter corruption can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring See application note AN1015 Software techniques for improving microcontroller EMC performance Table 50 EMS data Symbol Parameter Conditions Level class Vpp 3 8 V Ta 25 C Voltage limits to be applied on any I O pin fuAsrER 16 MHz HSI clock 1 YEESD lto induce a functional disturbance Conforms to IEC 61000 4 2 2 B SR Vpp 3 3 V Ta 25 C Fast transient voltage burst limits to be fmastER 16 MHz HSI clock i 1 Verre applied through 100 pF on Von and Vss Conforms to IEC 61000 4 4 4AM pins to induce a functional disturbance 1 Data obtained with HSI clock configuration after applying the hardware recommendations described in AN2860
112. w time Master mode tsck 2 15 tsck 2 15 tw SCKL t 2 Master mode 5 su MI Data input setup time Leute Slave mode 5 tana i Master mode 7 2 Data input hold time Iren Slave mode 10 taso Data output access time Slave mode 3 tMASTER tuis so Data output disable time Slave mode 25 2 Slave mode 5 tso Data output valid time after enable edge 65 2 LM Master mode after f two Data output valid time enable edge 30 2 Slave mode after 5 eo enable edge ar Data output hold time t 2 Master mode after 116 h MO enable edge 1 Parameters are given by selecting 10 MHz I O output frequency 2 Values based on design simulation and or characterization results and not tested in production 3 Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data 4 Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi Z 5 Data characterization in progress 79 121 Electrical characteristics STM8S903K3 STM8S903F3 Figure 39 SPI timing diagram where slave mode and CPHA 0 NSS input A ke tc SCK th NSS z CPHA 0 a CPOL 0 v CPHA 0 Y cPoL 1 ta SO th SO tr SCK tdis SO 4 ida tf SCK OUTP UT BIT6 OUT LSB OUT tsu SI MOSI Se X en X INPUT BI n IN LSB IN th Sl ai14134c 1 Measurement po
113. y area Write access possible for IAP MSv36479V1 Read out protection ROP The read out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode and debug mode Once the read out protection is activated any attempt to toggle its status triggers a global erase of the program and data memory Even if no protection can be considered as totally unbreakable the feature provides a very high level of protection for a general purpose microcontroller d 14 121 DoclD15590 Rev 10 STM8S903K3 STM8S903F3 Product overview 4 5 Clock controller The clock controller distributes the system clock MASTER coming from different oscillators to the core and the peripherals It also manages clock gating for low power modes and ensures clock robustness Features e Clock prescaler to get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler e Safe clock switching clock sources can be changed safely on the fly in run mode through a configuration register The clock signal is not switched until the new clock Source is ready The design guarantees glitch free switching e Clock management to reduce power consumption the clock controller can stop the clock to the core individual peripherals or memory e Master clock sources four different clock sources can be used to drive th

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