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1. 2 5 Table 2 9 Jumper Settings J14 J22 J26 J32 2 5 Table 2 10 J16 Stop Clock_ 2 6 Table 2 11 J17 Cache Policy 2 6 Table 2 12 719 Floppy Selection 2 6 Table 2 13 J21 Watchdog Enable Disable 2 7 Table 2 14 J24 Security Password Enable 2 7 Table 2 15 J29 CMOS Clear 2 7 Table 2 16 J30 Mouse IRQ Enable 2 8 Table 2 17 J31 Parallel PortDMA_ 2 8 Table 2 18 J33 IRQ11 Usage 2 8 Table 2 19 Connectors 2 9 Table 2 20 J1 IDE Connector 2 10 Table of Contents List of Tables Continued Table 2 23 J4 COM2 Port 2 13 Table 2 24 J5 COMI Port 2 14 Table 2 25 Serial Port Cable Wire List 2 15 Table 2 26 J7 SCSI Connector 2 16 Table 2 27 J8 Keyboard Connector 10 pin 2 17 Table 2 28 J10 Reset Connector 2 17 Table 2 29 J11 Speaker Connector 2 18 Table 2 30 J13 CPU Fan Connector 2 18 Table 2 31 J20 Keyboard mini DIN Connector 2 19 Table 2 32 J25 Mouse mini DIN Connector 2 19 Table 2 33 J27 External Hard Drive LED Connector 2 20 Table 2 34 J28 External Battery Connector 2 20 Table 3 1 Environm
2. o O Oo ALO Olc njo 1 amp 2 75 100 MHz a 2188 OFF 120 200 Mike E Table 2 8 J26 CPU Voltage Regulator Use the following table to determine the proper jumper settings for your specific board CPU Clock Clock CPU Voltage Internal Multiplier Speed Regulator pw wm OFF OFF None 1 amp 2 3 amp 4 1 amp 2 1 amp 2 1 amp 2 3 amp 4 1 amp 2 1 amp 2 1 amp 2 182 1 amp 2 3 amp 4 1 amp 2 1 amp 2 1 amp 2 Table 2 9 Jumper Settings J14 J22 J26 J32 2 5 Jumpers e J16 Stop Clock Select the following jumper positions for extra power savings dur ing the Green Mode Upon entering the Green Mode the CPU will be stopped It will resume operation when exiting the Green Mode Position Function Sh Extra power savings N Table 2 10 J16 Stop Clock e J17 Cache Policy J17 selects whether a cache line is to be invalidated on every DMA bus master cycle or on DMA bus cycle writes only In normal oper ation a jumper is placed on pins 1 and 2 Invalidate on writes O 2 Always invalidate e factory default setting Table 2 11 J17 Cache Policy e J19 Floppy Selection Select the density of the floppy disk drive enabled in the BIOS Three configurations are available two 2 88MB floppy drives two 1 2MB or two 1 44MB floppy drives one 1 2 MB and one 1 44 MB floppy drive 2 88 MB floppy drives cannot be configured with either a 1 2 MB or 1 44 MB fl
3. 4CYCLES burst WS system will wait for completion of a default PCI burst write 3 CYCLES 2 CYCLES Master Hetry Determine how long the CPU master 10 PCICLKs Timer attempts a PCI cycle before the cycle default is unmasked terminated 18 PCICLKs 84 PCICLKs 66 PCICLKs Table 4 5 PCI Configuration Setup Screen Entry Fields 4 22 Chapter 4 BIOS PCI Enable allows you to use external video Enabled Pre Snoop boards using frame grabbers to snoop Disabled VGA activity on the PCI bus default PCI Preempt Sets the length of time before one PCI Disabled Timer master preempts another when a service default request is pending See page 4 12 for 260 LCLKs an explanation of LCLK 182 LCLKs 68 LCLKs 36 LCLKs 20 LCLKs 12 LCLKs 5 LCLKs CPU to PCI Data from the CPU to the PCI bus can be POST POST BURST posted and or burst CON BURST default NONE NONE POST NONE 99 Ns 953 n ig 65 AS PCI CLK Select Sync to synchronize the PCI clock 1 Async with the CPU clock default Sync Onboard IDE Enable to use the system onboard IDE 1 Enable controller Disable if an IDE board is Disable installed in the system IDE HDD By enabling the block mode for hard Enabled Block Mode drive data transfer the system can read Disabled and write to the drive using large blocks of data instead of individual bytes IDE Primary Select the data transfer rate of the primary 1
4. 4MB 1MB x 36 4MB MB x36 16MB 4MB x 36 16MB 4MB x 36 4MB 1MB x 36 4MB 1MBx36 32MB 8MB x36 32MB 8MB x 36 4MB 1MB x 36 4MB MBx36 64MB 16MB x 36 64MB 16MB x 36 8MB 2MB x 36 8MB 2MB x 36 8MB 2MB x 36 8MB 2MB x 36 8MB 2MB x 36 8MB 2MB x 36 16MB 4MBx36 16MB 4MB x 36 8MB 2MB x 36 8MB 2MB x 36 32MB 8MBx36 32MB 8MB x 36 8MB 2MB x 36 8MB 2MB x 36 64MB 16MBx36 64MB 16MB x 36 16MB 4MB x36 16MB 4MBx36 16MB 4MBx36 16MB 4MB x 36 16MB 4MBx36 16MB 4MBx36 32MB 8MBx36 32MB 8MB x 36 16MB 4MBx36 16MB 4MBx36 64MB 16MB x36 64MB 16MB x 36 128MB 32MB 8MB x36 32MB 8MB x 36 32MB 8MB x 36 32MB 8MB x 36 192MB 32MB 8MB x 36 32MB 8MB x36 64MB 16MB x36 64MB 16MB x 36 256MB 64MB 16MB x36 64MB 16MBx36 64MB 16MBx36 64MB 16MB x 36 Table 1 1 DRAM Configurations SIMMs to be installed in matched pairs The following table shows some of the possible memory module configurations For other possible configurations contact I Bus e Multifunction Controller XIO The multifunction controller provides two high speed serial ports one bidirectional parallel port and a floppy disk controller e IDE Controller The Tigershark CPU board provides a PCI Integrated Drive Electronics IDE interface for up to two IDE hard disk drives through the header at J1 J1 accepts
5. 3 1990 2099 1 24 1 60 1 60 1 46 Type User None 1 None 2 360 5 25 in 1 2M 5 25 in 720K 3 5 in 6 2 88M 3 5 in Table 4 1 Standard CMOS Setup Screen Entry Fields Setup Screens Fields Video Description Select the type of video adapter used for the primary system monitor Select the condition that would cause the system to stop at boot up Choices 1 EGA VGA 2 CGA40 3 CGA80 4 MONO 1 No errors 2 All errors 3 All but keyboard 4 All but diskette 5 All but disk ke Table 4 1 Standard CMOS Setup Screen Entry Fields Cont 4 8 Chapter 4 BIOS e BIOS Features Setup Screen ROM PCI ISA BIOS 2A5UNA2I BIOS FEATURES SETUP AWARD SOFTWARE INC Virus Warning Disabled Video BIOS Shadow Enabled CPU Internal Cache Enabled C8000 CBFFF Shadow Disabled External Cache Enabled CC000 CFFFF Shadow Disabled D0000 D3FFF Shadow Disabled Boot Sequence A C D4000 D7FFF Shadow Disabled Swap Floppy Drive Disabled D8000 DBFFF Shadow Disabled DC000 DFFFF Shadow Disabled Boot Up NumLock Status On Onboard SCSI Controller Enabled Gate A20 Option Fast Delay For SCSI HDD Secs E 0 Typematic Rate Setting Disabled Typematic Rate Char Sec 6 Typematic Delay Msec 250 Security Option Setup Select Item PCI VGA Palette Snoop Disabled F1 Help PU PD Modify F5 Old Values Shift F2 Color F6 Load BIOS Defaults F7 Load Se
6. Keyboard Initialize Video Interface Detect CPU clock Test Video Memory Test DMA Controller 0 Test DMA Controller 1 Test DMA Page Registers Reserved Test Timer Counter 2 Test 8259 1 Mask Bits Test 8259 2 Mask Bits Test Stuck 8259 s Interrupt Bits Test 8259 Interrupt Functionality Test Stuck NMI Bits Parity UO Check Display CPU Clock Reserved Description Cyrix CPU Initialization Cache Initialization Initialize first 120 interrupt vectors with SPURIOUS_INT_HDLR and initialize INT 00h 1Fh according to INT_TBL Test CMOS RAM Checksum if bad or insert key pressed load defaults Detect type of keyboard controller optional Set NUM_LOCK status Read CMOS location 14h to find out type of video in use Test video memory write sign on message to screen Setup shadow RAM Enable shadow according to Setup BIOS checksum test Keyboard detect and initialization Test DMA Page Registers Test 8254 Timer 0 Counter 2 Verify 8259 Channel 1 masked interrupts by alternately turning off and on the interrupt lines Verify 8259 Channel 2 masked interrupts by alternately turning off and on the interrupt lines Turn off interrupts then verify no interrupt mask register is on Force an interrupt and verify the interrupt occurred Verify NMI can be cleared Table A1 10 Post Codes continued A1 10 Appendix 1 Technical Reference Post Code R
7. PCI Configuration Setup This setup screen is available only on systems that support PCI Load Setup Defaults This screen allows you to load the chipset defaults for maximum system performance Password Setting This screen allows you to configure the change set or disable functions of the password option IDE HDD Auto Detection Functions on this screen automatically detect and configure the hard disk parameters Save Exit Setup Save CMOS changes and exit setup Exit Without Saving Abandon all CMOS value changes and exit setup 4 5 Setup Screens ROM PCI ISA BIOS 2A5UNA2I STANDARD CMOS SETUP AWARD SOFTWARE INC Date mm dd yy Mon Jan 2 1995 Time hh mm ss 19 40 56 CYLS HEADS PRECOMP LANDZONE SECTORS Drive C None 0Mb 0 0 0 0 DriveD None OMb 0 0 0 0 Drive A None Drive B None Video EGANGA Base Memory 640K Extended Memory 7168K Halt On All Errors Other Memory 384K Total Memory 8192K Select ltem PU PD Modify F1 Help Shift F2 Change Color e Standard CMOS Setup Screen Figure 4 2 Standard CMOS Setup Screen Explanation The parameters in the Standard CMOS Setup Screen are divided into groups Each group includes one or more setup items Use the arrow keys to highlight the item and then use the PgUp or PgDn keys to select the value for each item Date The month is highlighted first then the date and year Day is automatically calculated when the
8. 5 7 5 4 5 9 7 Oga Table A1 11 Hard Disk Parameter Table A1 12 Appendix 2 Glossary of Terms B bidirectional parallel port An eight bit port that can be used for an input as well as an output device BIOS Basic Input Output Systems The on board firmware which communicates with the display keyboard printers and other peripheral devices bus A common pathway or channel between multiple devices consisting of one or more electrical conductors that transmit power or binary data to the various sections of a computer C cache A collection of the most recently accessed data or instructions CMOS Complementary Metal Oxide Semiconductor A technique of using PMOS and NMOS transistors in a complementary fashion where power is consumed only during the switching phase With the input statically high or low the power dissipa tion is essentially zero CMOS RAM Random Access Memory made from CMOS transistors D DMA Direct Memory Access Channel A channel for transferring data from host main memory to and from peripherals without direct involvement of the CPU resources DRAM Dynamic Random Access Memory The main memory in your computer It needs to be refreshed by a memory controller or it will lose its information A2 1 Appendix 2 Glossary of Terms E EPROM Erasable Prosrammable Read Only Memory A programmable device which stores information regardless of power The information can be
9. AT LO Map DMA DMA Channel Page Register and I O Addresses Controller 1 8 bit ports 000 00F Page Register UO Hex Address Channel 0 Channel 2 Channel 3 Table A1 2 DMA Channel Page Register and I O Addresses DMA Channel Assignments eme Tam Spare Reserved Spare Reserved Spare Reserved Table A1 3 DMA Channel Assignments Loe A1 2 Appendix 1 Technical Reference DMA Controller Register Functions Table A1 4 DMA Controller Register Functions A1 3 Interrupts Channel Function z Parity System Timer Output 0 KYBIRQ IRQ2 CTRL2 Interrupt IRQ8 IRQ15 IRQ3 Serial Port 2 COM2 IRQ4 Serial Port 1 COM1 IRQ5 Keyboard Output Buffer Full Parallel Port 2 Floppy Disk Controller IRQ7 RTCIRQ Parallel Port 1 Real Time Clock Software redirected to INT 0Ah IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 External ISA Bus Device Reserved External ISA Bus Device Reserved External ISA Bus Device Reserved External ISA Bus Device Reserved Math Coprocessor Hard Disk Controller tr mo emo 2 me 3 m os m s ma 6 mos o7 ma a mem o mo to sen ow man s moz s mos mn mo oss mas Table A1 5 Interrupts These interrupts exist on the system board and are not available on the ISA Bus Connectors A1 4 Appendix 1 Technical Reference CMO
10. Refresh When enabled a cycle 1s eliminated by hiding the refresh in the Hidden mode Not only is the Hidden mode faster and more efficient but it also allows the CPU to maintain the status of the cache even if the system goes into a power management suspend mode DRAM Posted Write When enabled a CPU write cycle to DRAM will not require the CPU to wait during the external DRAM cycle Byte Merge Support When enabled this allows 8 or 16 bit data sent from the CPU to the PCI bus to be held in a buffer where it is accumu lated or merged into 32 bit data for faster performance The chipset will then write the data in the buffer to the PCI bus when appropriate Tag RAM Size Tag bits are used by the system to determine the status of data contained in the cache Tag Dirty implement The system cache controller supports two meth ods of determining the state of data in the cache One implementation separates the tag signal from the dirty signal while the other combines the two to a single 8 if 7 bits are selected in Tag RAM Size or 9 bit 8 bits selected signal L1 Cache Policy This parameter sets the write policy for the CPU s internal or Level 1 cache L2 Cache Write Policy This parameter sets the write policy for the Level 2 cache cache not located in the CPU 1st 2nd Fast DMA Channels The chipset provides a form of com pressed timing on the DMA called Type F DMA This mode provides ISA compatible timing for
11. components or CPUs I Bus is not liable for any defects in material or workmanship of any peripherals products or parts which I Bus does not design or manufacture However I Bus will honor the original manufacturer s warranty for these products Bus will analyze the defective component and the customer will be charged in the following instances No problem found 75 U S dollars Damage parts and labor at 75 per hour with a 100 minimum charge U S dollars Receipt of damaged goods voids the I Bus warranty Repair parts and replacement products will be furnished on an exchange basis and will be either new or reconditioned All replacement parts and products shall become the property of I Bus if such parts or products are provided under this warranty agreement In the event a defect is not related to the I Bus manufactured product I Bus shall repair or replace the defective parts at pur chaser s cost and deliver the defective parts to the purchaser This Limited Warranty shall not apply if the product has been misused carelessly handled defaced modified or altered or if unauthorized repairs have been attempted by others The above warranty is the only warranty authorized by I Bus and is in lieu of any implied war ranties including implied warranty of merchantability and fitness for a particular purpose In no event will I Bus be liable for any such damage as lost business lost profits lost savings downtime or delay
12. erased and new information written F Floating Point Unit FPU A device which can perform calculations on numbers in floating point format as opposed to simple integers l IDE Integrated Drive Electronics A standard of signalling and communicating with a device interleave Multiple banks of memory that overlap to reduce the access time and eliminate wait states interrupt Temporarily halting the operation of a digital computer to respond to service an external event interval timer A device that can generate a pulse at a defined interval for background tasks IRQ Interrupt Request A signal channel used to trigger the CPU to temporarily change tasks K Kilobyte KB 1 024 bytes N ns nano seconds 1 x 109 seconds There are one billion nanoseconds in one second A2 2 Appendix 2 Glossary of Terms P page mode The ability to read a whole line page of memory to reduce access time parity A way to detect corrupted data in DRAM parallel port An eight bit port usually used for connecting a printer PCI Peripheral Component Interconnect Local bus for PCs that provide a high speed data path between the CPU and peripher als video disk network etc The PCI bus coexists in the PC with the ISA or EISA bus ISA and EISA boards still plug into an ISA or EISA slot while high speed PCI controllers plug into a PCI slot The PCI bus runs at 33 MHz supports 32 bit and 64 bit data paths a
13. interface is disabled when no keyboard is present on the system A six pin 1 8 Chapter 1 Introduction mini DIN connector is provided at J20 A ten pin header is also provided at J8 A keyboard adapter cable is provided for keyboards with a five pin DIN connector to connect to the PS 2 mini DIN Heal time Clock Calendar The Tigershark has a real time clock calendar backed by an on board battery It has 114 bytes of CMOS RAM included with the clock The battery has a two year life and is field replaceable Reset An external reset can be attached to the Tigershark at J10 Speaker The Tigershark provides an on board speaker and the capability of adding an external speaker at connector J11 EPROM The 27C010 EPROM contains the BIOS for the system The sys tem BIOS is mapped from EF000h to FFFFFh Bus Drivers The Tigershark uses buffered bus drivers capable of driving nine teen additional expansion cards Watchdog Timer The dual stage watchdog timer is enabled in 2 steps Step 1 The 2 Hz clock must first be started by writing the follow ing values to the indicated addresses OxOA to address 0x70 Ox2F to address 0x71 OxOB to address 0x70 OxOA to address 0x71 Step 2 Next a 1 must be written to I O address 0x160 Once the watchdog timer is enabled it will generate an IRQ11 after sixteen seconds After another sixteen seconds the board will reset To pre vent these exceptions from being generated the timer is
14. month and year are entered Drives C D C and D identify the hard disk drives installed on the system When numbers 1 to 46 are selected the drive parameters are automatically configured When Type User is selected the drive para meters must be entered directly from the keyboard Press Enter when the entry is complete Drives A B A and B identify the types of floppy disk drives installed on the system 4 6 Chapter 4 BIOS Video This selection pertains to the primary system monitor Secondary system monitors are supported but do not have to be selected in Setup Halt On After boot up and during POST Power On Self Test the system will stop when it encounters an error or device not present Select the the way the system will boot up Memory The memory is auto sensed during POST No user entry is allowed Base Memory is the amount of memory at or about the 640K boundary Extended Memory is above the IMB boundary Other Memory is the portion of memory usually 384K allocated for Shadow RAM or remapped to the Extended Memory pool Fields Date Description Format is day month day year Format is hour minute second on 24 hour clock Press PgUp or PgDn to move between numbers Press Enter to select type Select Type User to define individual parameters See Table A1 11 on page A1 12 Press PgUp or PgDn to move between choices Press Enter to select type 4 7 Choices 1 Jan Dec 2 1 81
15. of the board If no jumper is installed on either J14 or J32 standard operation the CPU operates at 1 5 x the speed of the board To set the CPU speed at 2 5 x the speed of the board place jumpers on both J14 and J32 OFF J14 amp J32 1 5 x CPU speed 1 1 amp 2 J14 only 2 x CPU speed O 2 1 amp 20f J14 amp J32 2 5 x CPU speed OFF J14 only 3 x CPU speed Table 2 5 J14 Internal Clock Multiplier e J32 Internal Clock Multiplier see Table 2 9 Placing a jumper only on J32 sets the CPU speed at 3 x the speed of the board If no jumper is installed on either J32 or J14 standard operation the CPU operates at 1 5 x the speed of the board To set the CPU speed at 2 5 x the speed of the board place jumpers on both J32 and J14 OFF J32 amp J14 1 5 x CPU speed O 2 OFF J32 only 2 x CPU speed a h di 1 amp 2 of J32 amp J14 2 5 x CPU speed 1 amp 2 J32 only 3 x CPU speed Table 2 6 J32 Internal Clock Multiplier 2 4 Chapter 2 Jumpers and Connectors e J22 CPU Clock Speed see Table 2 9 For a 50MHz CPU no jumpers are placed on J22 For a 6 0MHz CPU place jumpers on pins 1 and 2 and pins 3 and 4 Fora 66MHz CPU a jumper on pins 1 and 2 Base Speed None 50 MHz 1 amp 2 3 amp 4 60 MHz Table 2 7 J22 CPU Clock Speed J26 CPU Voltage Regulator see Table 2 9 When using a 75 100MHz CPU install a jumper on pins 1 and 2 When using a 120 200MHz CPU no jumper is installed
16. there are no floppy drives installed make sure the Diskette Drive selection in Setup is set to NONE KEYBOARD ERROR OR NO KEYBOARD PRESENT Cannot initialize the keyboard Make sure the keyboard is attached correctly and no keys are being pressed during the boot If you are purposely configuring the system without a keyboard set the error halt condition in Setup to HALT ON ALL BUT KEY BOARD This will cause the BIOS to ignore the missing keyboard and continue to boot Memory Address Error at Indicates a memory address error at a specific location You can use this location along with the mem ory map for your system to find and replace the bad memory chips 4 26 Chapter 4 BIOS Memory parity Error at Indicates a memory parity error at a specific location You can use this location along with the memory map for your system to find and replace the bad memory chips Memory Verify Error at Indicates an error verifying a value already written to memory Use the location along with your sys tem s memory map to locate the bad chip OFFENDING ADDRESS NOT FOUND This message is used in conjunction with the UO CHANNEL CHECK and RAM PARITY ERROR messages when the segment that has caused the problem cannot be isolated OFFENDING SEGMENT This message is used in conjunction with the I O CHANNEL CHECK and RAM PARITY ERROR mes sages when the segment that has caused the problem has been iso lated PRESS A KEY TO REBOOT This
17. transfers from memory to the parallel port Select DMA channels 1 or 3 to be used for the 1 amp 2 5 amp 6 LPT1 uses DRQ3 DACK3 310 Ol4 3 amp 4 7 amp 8 LPT1 uses DRQ1 DACK1 5JO Ol S 7 O OJ8 Table 2 17 J31 Parallel Port DMA parallel port J33 IRQ11 Usage IRQII can be configured to share with the ISA bus and the Watchdog timer To facilitate this sharing technique the IRQ11 sig nal on the backplane is pulled down to ground through a 10k resis IRQ11 for Watchdog timer only Share IRQ11 with ISA bus Les ee amp Watchdog timer IRQ11 for ISA bus only factory default setting Table 2 18 J33 IRQ11 Usage 2 8 Chapter 2 Jumpers and Connectors tor If any cards in the ISA backplane have a pullup resistor on IRQII this sharing technique cannot be used Connectors The following connectors can be located in Figure 1 1 Tigershark Description IDE Connector Floppy Disk Drive Connector CPU Board Jumpers Connectors and Components on page 1 4 and the fold out illustration on page A3 1 Table 2 19 Connectors 2 9 Connectors 2 10 Chapter 2 Jumpers and Connectors Table 2 21 J2 Floppy Disk Drive Connector J DheFtoppyeDishe DiiverBornsiatore GND oo0oo0o o SOCO 2 OOOCOCOCG e OOOO 1 Connectors e J3 Parallel Port s m See IE SNE A Data bit Data bite 4 Data bit 7 Table 2 22 J3 Parallel Port 2 26 OOOC
18. will be displayed at the bot tom screen when an error occurs that requires you to reboot Press any key and the system will reboot PRESS F1 TO DISABLE NMI F2 TO REBOOT When BIOS detects a Non maskable Interrupt condition during boot this will allow you to disable the NMI and continue to boot or you can reboot the system with the NMI enabled RAM PARITY ERROR CHECKING FOR SEGMENT Indicates a parity error in Random Access Memory SYSTEM HALTED CTRL ALT DEL TO REBOOT Indicates the present boot attempt has been aborted and the system must be rebooted Press and hold down the CTRL and ALT keys and press DEL 4 27 Troubleshooting This section contains questions that are most frequently asked of our Customer Support Department about the BIOS setup utility You may be able to diagnose any difficulty you have by referring to them prior to calling our Customer Support Q1 Q2 Q3 Q4 Q5 Q6 I ve made BIOS changes and saved them and now the system won t boot What can I do A A CMOS override can be invoked by pressing the Insert key when the computer is rebooted This resets the system to its defaults Do I have to use the on board IDE or floppy disk controllers A No Do you have to use the serial or parallel ports built onto the CPUs A No you may relocate or disable them What if you are using a different controller other than the one built into the CPU A This is not a problem if you adju
19. Adapter ROMs can be shadowed either way some permit only the RW or WP option and a rare few cannot be shadowed at all You may need to experiment a lit tle Shadow RAM is obtained from a gap in the otherwise contiguous mem ory space of the computer The 384K region between the 640K and 1MB boundaries is occupied not by memory but instead by ROMs video memory and possibly other system level devices The memory that should appear there is simply inaccessible and unused One way to make use of this lost memory is to activate it as Shadow RAM Certain designs can also remap a portion of this 384K into the Extended Memory pool provided it is not already enabled as Shadow RAM In most designs with this capability remap will be prevented if any Shadow segment is enabled in the D000 through E000 regions Description Enable to activate automatically when 1 Enabled system boots causing message to display 2 Disabled CPU Internal Enable to allow access to CPU internal 1 Enabled cache 2 Disabled Enter the drive sequence used to boot the 1 C A system 2 A C default Swap Floppy Enable to reassign floppy drive designation 1 Enabled if more than one floppy drive is installed in 2 Disabled 4 10 Chapter 4 BIOS Table 4 2 BIOS Features Setup Screen Entry Fields Char Sec Typematic Delay msec Security Video BIOS Shadow C8000 CFFFF7 D0000 DFFFF Shadow Enter the default state of the numeric keypad
20. Auto Master Slave master slave IDE drive Auto allows the Mode 0 PIO BIOS to query the drive s and select Mode 1 the optimum speed Mode 2 Mode 3 Mode 4 fastest Table 4 5 PCI Configuration Setup Screen Entry Fields Cont 4 23 Password Setting e Password Setting When this function is selected the following message will be displayed at the center of the screen ENTER PASSWORD Type the password up to eight characters in length and press Enter The entered password will clear any previously entered password from CMOS memory statement will be displayed requesting confirmation Type the password again and press Enter To abort this process press Esc To disable a password press Enter when prompted to enter the pass word The following message will be displayed at the center of the screen PASSWORD DISABLED Once the password is disabled the system will boot and Setup can be entered When a password has been enabled it will have to be entered every time Setup is entered This prevents an unauthorized person from changing any part of the system configuration Additionally when a password is enabled you can also require the BIOS to request a password every time your system is rebooted This would prevent unauthorized use of your computer You determine when the password is required within the BIOS Features Setup Menu and its Security option If the Security option is set to System the passwo
21. Compatible e Fast PCI SCSI II on board controller and interface e Two high speed serial ports with 16550 UARTs e One bidirectional parallel port with DMA access e Floppy disk interface PCI Integrated Drive Electronics IDE hard disk inter face e Real time clock with on board battery backup e Keyboard mouse speaker and reset ports e Watchdog timer The following are detailed descriptions of some of the above features Pentium CPU The Tigershark features the Pentium CPU operating at 75 90 100 120 133 150 166 or 200MHz This 32 bit CPU with a 64 bit bus of the same speed operates twice as fast as 486 CPUs for common operations Cache The Pentium CPU is equipped with two separate 8K caches one for storing code and the other for storing data In addition the Tigershark is equipped with 512K second level cache that can be configured in the BIOS to be write back or write through DRAM The Tigershark CPU board supports 8MB to 256MB of 70 ns x 36 1 5 Features DRAM SIMMs located in four sockets labeled SM1 SM2 SM3 and SM4 The Pentium CPU has a 64 bit bus which requires Total SM1 mB Umer 2MAIMBxS o o e 16MB 8MB 2MB x 36 8MB 2MB x 36 32MB 16MB 4MB x 36 16MB 4MB x 36 64MB 32MB 8MB x 36 32MB 8MB x 36 D IS 128MB 64MB 16MB x 36 64MB 16MB x 36 4MB 1MB x 36 4MB 1MB x 36 4MB 1MB x 36 4MB 1MB x 36 4MB 1MB x 36 4MB 1MB x 36 8MB 2MB x 36 8MB 2MB x 36
22. Dirty signals into a single 1 Combine Implement signal or Separate Tag and Dirty signals Separate Dirty pin I O selects bi directional input output VO selection IN selects input only IN Table 4 3 Chipset Features Setup Screen Entry Fields 4 14 Chapter 4 BIOS L1 Cache Write Back causes memory to be updated 1 Write Back Policy only under certain conditions such as read 2 Write Through requests to the memory whose contents are currently in the cache allowing the CPU to operate with fewer interruptions and increasing its efficiency Write Through means that memory is updated with data held in the cache whenever the CPU issues a write cycle L2 Cache Same as L1 Cache Policy 1 Write Back Policy 2 Write Through Cache Write Select the precise timing used during burst 1 2 1 1 1 to Burst writes to the cache by scrolling though the 5 4 4 4 choices Video BIOS When enabled the Video BIOS cache will 1 Enabled Cacheable cause access to video BIOS addressed at 2 Disabled C0000H to C7FFFH to be cached if the default cache controller is also enabled When disabled the video BIOS access is not cached System BIOS As with caching the Video BIOS above 1 Enabled Cacheable enabling allows accesses to the system 2 Disabled BIOS ROM addressed at F0000H default FFFFFH to be cached provided that the cache controller is enabled DRAM Set to the type of DRAM SIMMs installed in Timing the syste
23. Floppy Selection J23 Factory Test oooooocdoooooo nooooodoooooo Wen pan E N ES5S 556sg 56 J21 Watchdog d2 Enable Disable Floppy Disk Drive Connector il J27 External HD LED Connector 0000000000000000 0000000000000000 J7 SCSI Connector IS 0000000000000000000000000 01000000000000000000000000 0000000000000 0000000000000 J33 IRQ11 Usage BSsdssooool no6922224 J1 IDE Connector J9 Er E Cache Size Su CPU Clock Speed J12 is i Cache Size ge B J29 J26 CMOS Clear DE CPU Voltage Regulator 145 a SIMMs SM1 Fa SM2 e 99 as les zu Sank SM4 Sse So g HR 77 J18 wssples es Di I Factory Test 20 20 Too 28 3 Oo sa s i Soad ool los iz 1 i J17 s se oaea mem 47 le d Cache Policy lt 3 Es J16 Stop Clock As CPU Factory Tes J32 Internal Clock Multiplier J14 Internal Clock Multiplier DEN EH J13 CPU Fan Connector 1 4 Chapter 1 Introduction Figure 1 1 Tigershark CPU Board Jumpers Connectors and Components Features The key features of the Tigershark CPU board are e Supports the Pentium Central Processing Unit CPU e 512K standard cache memory e Supports up to 256MB DRAM e PCI interface PICMG
24. OOOOOCOCOCCO OOOOOCOOOOCODOCO 1 25 Chapter 2 Jumpers and Connectors The optional parallel port cable connects to J3 Its DB25 connector attaches to the I O panel on the back of the chassis J4 COM Port The secondary serial port is a ten pin header located at J4 The sec ondary serial port can be terminated in a DB9 connector by obtain ing the optional serial port cable from I Bus A wire list is also pro vided on page 2 15 for a third party cable Another optional cable from I Bus is Table 2 23 J4 COM2 Port equipped with a retaining bracket mounting a DB and a DB25 connector terminating in a ten pin and twenty six pin header respectively 2 13 Connectors e J5 COM 1 Port The primary serial port is a ten pin header located at J5 The prima ry serial port can be terminated in a DB9 connector by obtaining the optional serial port cable from I Bus A wire list is also provided on page 2 15 for a third party cable Table 2 24 J5 COM Port Another optional cable from I Bus is equipped with a retaining bracket mounting a DB9 and a DB25 connector ter minating in a ten pin and twenty six pin header respectively 2 14 Chapter 2 Jumpers and Connectors e Serial Port Cable Wire List Signal Connector Name Onboard 10 Pin Connectors J4 amp J5 Table 2 25 Serial Port Cable Wire List DB9 Connector 10 pin Connector 2 15 Connectors The following wire list is provid
25. QQ IRQ2 Redir Disable Doze Mode Disable IRQ10 Reserved Enable Standby Mode Disable IRQ11 Reserved Enable Suspend Mode Disable IRQ12 PS 2 Mouse Enable IRQ13 Coprocessor Enable PM Events IRQ14 Hard Disk Disable DMA Request Enable IRQ15 Reserved Enable Video Activity Disable HDD Port 1F0 170 Enable Select Item LPT 3BC 378 278 Enable F1 Help PU PD Modify COM Port 3F8 3E8 Enable F5 Old Values Shift F2 Color COM Port 2F8 2E8 Enable F6 joad BIOS Defaults PCI Masters Enable F7 joad Setup Defaults Figure 4 5 Power Management Setup Screen Explanation The Power Management Setup screen allows you to configure the sys tem to most effectively save energy Power Management The type of power saving selected here is direct ly related to the four PM Timers HDD Off After Doze Mode Standby Mode and Suspend Mode You can choose one of the fixed mode choices or disable it Min Power Saving HDD Off After 15 min Doze Mode 1 hr Standby Mode 1 hr Suspend Mode 1 min Max Power Saving is only available for SL CPUs HDD Off After 1 min Doze Mode 1 min Standby Mode 1 min Suspend Mode 1 min User Defined allows each mode to be set individually When not disabled each of the ranges are from 1 min to 1 hr except for HDD Off After which ranges from 1 min to 15 min and disable PM Timers The four parameters are Green PC power sav
26. S RAM Address Map Table A1 6 CMOS RAM Address Map These addresses are not verified by CHECKSUM A1 5 Real Time Clock Information Addresses 00 0D Minutes Seconds alarm Minutes alarm Day of month Table A1 7 Real Time Clock Information A1 6 Appendix 1 Technical Reference ISA Connector Pin Assignments GND EMCS16 RESETDRV IOCS16 5V IRQ10 ENDXFR DACKO 12 V DRQO GND DACK5 SMEMW DRQ5 SMEMR DACK6 DACK3 DRQ3 5 V DACK1 MASTER DRQ1 REFRSH PCI Connector Pin Assignments Assign AD16 AD17 43 3 V C BE2 FRAME GND IRDY 3 3 V DEVSEL B08 GND B09 5 V I O B10 INTD REQ3 B41 CLKD B11 B12 REQ1 1 GNT3 ND 42 B45 5 V I O B46 GNT0 GND C BEO 3 3 V ADO6 5 V I O 43 8 V 45 V I O REQ64 B23 B24 B25 B26 B27 B28 B29 B30 B31 ND AD21 ACK64 Table A1 9 PCI Connector Pin Assignments A1 8 Appendix 1 Technical Reference Post Code Turn Off Chipset Processor Test 1 Processor Test 2 Initialize Chips Test Memory Refresh Toggle Blank video Initialize keyboard Reserved Test CMOS Interface amp Battery Status Chipset Default Initialization Memory Presence Test Early Shadow Cache Prese
27. User Manual Tigershark PCI Pentium CPU Board with SCSI 7 TECHNOLOGIES ue OMPANV 109 40033 00 Rev Y3 1EUS198 I1 A ott ORE EE N Tigershark PCI Pentium CPU Board with SCSI User Manual 095 20046 00 Rev Y3 Copyright 1996 by I Bus Inc a Maxwell Technologies Company printed and bound in the United States All rights reserved No part of this manual may be reproduced in any form or by any electronic or mechanical means including information storage and retrieval systems without the written permission of I Bus All trademarks are the property of their respective companies Mailing Address Telephone FAX E mail Visit our site at Customer Service I Bus Inc A Maxwell Technologies Company P O Box 84239 San Diego CA 92123 619 974 8400 800 382 4229 in the U S 619 268 7863 info ibus com http www ibus com LIMITED WARRANTY Bus warrants this product to be free of defects in material and workmanship for an initial period of two 2 years from date of delivery to the original purchaser from I Bus During this period I Bus will at its option repair or replace this product at no additional charge to the purchaser except as set forth in this warranty agreement Bus will at its option repair or replace this product at no additional charge to the purchaser if the defect is related to the I Bus manufactured product such as power supply backplanes other chassis
28. When set to Enable default any 1 Enabled IRQ3 C2 event at any of these local devices 2 Disabled IRQ4 C1 will awaken the system IRQ5 LPT2 Enable is the default for all except IRQ6 Floppy IRQ14 IRQ7 LPT1 IRQ9 IRQ2 IRQ10 Rsvd IRQ11 Rsvd IRQ12 Mouse IRQ13 Coproc IRQ14 HD IRQ15 Rsvd Table 4 4 Power Management Setup Screen Entry Fields Cont 4 20 Chapter 4 BIOS e PCI Configuration Setup Screen ROM PCI ISA BIOS 2A5UNA2I PCI CONFIGURATION SETUP AWARD SOFTWARE INC PnP BIOS Auto Config Disabled Onboard IDE Enabled Slot 1 Using INT AUTO IDE HDD Block Mode Enabled Slot 2 Using INT AUTO IDE Primary Master PIO AUTO Slot 3 Using INT AUTO IDE Primary Slave PIO AUTO Slot 4 Using INT AUTO 1st Available IRQ 115 2nd Available IRQ 10 3rd Available IRQ 9 4th Available IRQ 5 PCI Read burst WS 2 Cycles PCI Write burst WS 2 Cycles Master Retry Timer 10 PCICLKs PCI Pre Snoop Disabled Select ltem F1 Help PU PD Modify PCI Preempt Timer Disabled F5 Old Values Shift F2 Color CPU to PCI POST BURST POST CON BURST F6 Load BIOS Defaults PCI CLK Async F7 Load Setup Defaults Figure 4 6 PCI Configuration Setup Screen Explanation This screen is for configuring the PCI bus PCI or Peripheral Component Interconnect is a local bus that provides a high speed data path between the CPU and peripheral devices such as graphic ad
29. a forty pin IDE connector e SCSI ll Controller The Tigershark features the 53C810A SCSI processor It has a high performance SCSI core and an intelligent 32 bit bus master 1 6 Chapter 1 Introduction DMA core integrated with a SCSI SCRIPTS processor The 53C810A is connected to internal SCSI devices through a 50 pin connector It can be directed to an external connector via one of several I Bus adapter assemblies Serial LO Interface There are two RS232 compatible serial communication ports with 16550 type UARTS a primary serial port located at J5 and a sec ondary serial port at J4 Parallel I O Interface The Tigershark CPU board provides a parallel I O interface at J3 While it is conventionally a printer port it can be reconfigured by software to be a bidirectional parallel port Contact I Bus for infor mation Floppy Disk Drive Interface Three configurations are available two 2 88MB floppy drives two 1 2MB or two 1 44MB floppy drives one 1 2 MB and one 1 44 MB floppy drive OPTi 820556 82C557 82C558 The OPTi 82C556 82C557 and 82C558 provide the major portion of the system controller Its features include cache interface buffer controller memory interface system and cache controllers Integrated Peripheral Controller IPC The 82C558 integrates two 8237 DMA controllers two 8259 inter rupt controllers and one 8254 timer counter Programmable Interrupt Controller The 82C558 provides 15 user se
30. apters disk controllers and network cards PnP BIOS Auto Config This parameter supports the Plug and Play Microsoft Intel standard for operating systems Windows 95 and expansion boards This feature should only be enabled when using an operating system that supports Plug and Play IDE Primary Master Slave PIO This parameter controls the data transfer rate of the IDE drive s Selections are from Mode 0 to Mode 4 and AUTO Mode 0 is the slowest Mode 4 the fastest AUTO allows the BIOS to query the drive s and select the optimum speed 4 21 Setup Screens Entry Fields Fields Description Choices PnP BIOS Enables or Disables the Plug and Enabled Auto Config Play feature Disabled default Slot x Using Each PCI slot is capable of activating up to 1 AUTO INT four interrupts INT A INT B INT C and default INT D Selecting AUTO allows the PCI controller to automatically allocate the interrupts 1st 2nd 3rd 4th Select which interrupt is associated with Available IRQ each PCI slot By default IRQ s 9 and 10 are mapped to PCI devices The IRQ settings must be the same as the jumper settings on the CPU board NA means the IRQ has been assigned to the ISA bus and is not available PCI Read Determine how long in CPU cycles the 4CYCLES burst WS system will wait for completion of a default PCI burst read 3 CYCLES 2CYCLES PCI Write Determine how long in CPU cycles the
31. at boot up Normal handles A20 gate through the keyboard Fast handles A20 gate through the chipset Enable to allow a key to repeat when pressed Disable to keep a key from repeating when it is pressed Enter the rate at which a key repeats when pressed Typematic Rate Setting must be enabled Enter the length of time a key can be pressed before it will begin to repeat Typematic Rate Setting must be enabled Enter System to require password to access system Enter Setup to require password to enter Setup Enable the VGA feature connector port Enabling video shadow copies video shadow to RAM increasing video speed Enable optional ROM to RAM in each of the defined areas Enable the onboard SCSI controller Disable if a high performance SCSI controller board is installed Enter the delay time in seconds to allow or hard drive spin up 1 On default 2 Off 1 Normal 2 Fast 1 Enabled 2 Disabled 1 8 6 8 10 12 15 20 24 30 250 500 750 1000 System Setup Enabled Disabled default Enabled Disabled Enabled Disabled Enabled Disabled 0 60 Setup Screens Table 4 2 BIOS Features Setup Screen Entry Fields Cont ROM PCI ISA BIOS 2A5UNA2I CHIPSET FEATURES SETUP AWARD SOFTWARE INC Auto Configuration Disabled 1st Fast DMA Channel NONE 2nd Fast DMA Channel NONE AT Bus Clock 8 MHz Onboard FDC Controller Ena
32. bled Hidden Refresh Enabled Onboard Serial Port 1 COM1 Onboard Serial Port 2 COM2 DRAM Posted Write Disabled Onboard Parallel Port LPT1 DRAM Slow Refresh Disabled CPU Addr Pipelining Disabled Byte Merger Support Disabled Tag RAM Size 8 bit Tag Dirty implement Separate Dirty pin selection IN L1 Cache Policy Write Back L2 Cache Write Policy Write Back Select Item Cache Write Burst 4 2 2 2 Help PU PD 4 Modify Video BIOS Cacheable Enabled Old Values Shift F2 Color System BIOS Cacheable Enabled Load BIOS Defaults DRAM Timing 70 ns Load Setup Defaults e Chipset Features Setup Screen Figure 4 4 Chipset Features Setup Screen Explanation The Chipset Features Setup screen manages bus speeds and access to system memory resources such as DRAM and the external cache It also coordinates communications between the conventional ISA bus and the PCI bus Normally these items never need to be altered The default settings provide optimum conditions for the system The only time changes would be warranted is if data was being lost during sys tem use AT Bus Clock The AT bus clock speed is the local speed at which the CPU communicates with memory The speed is measured in terms of a fraction of LCLK the timing of the local clock of the PCI bus DRAM Settings The first chipset settings deal with CPU access to DRAM dynamic random access memory 4 12 Chapter 4 BIOS Hidden
33. ctors 2 9 Chapter 3 Specifications System Components 3 1 Environmental Specifications 3 2 Chapter 4 BIOS Starting and Exiting the BIOS Setup 4 1 Setup SOIeells iss 066065060666 eneren enos no o e bed 4 2 Appendix 1 Technical Reference Standard PC AT I O Map A1 1 DMA Channel I O Addresses Al 2 DMA Channel Assignments Al 2 DMA Controller Register Functions A1 3 IntetF D S erate ERC eer red E AI 4 CMOS RAM Address Map_ A1 5 Real Time Clock Information Addresses 00 0D Al 6 ISA Connector Pin ssignments Al 7 PCI Connector Pin Assignments A1 8 Table of Contents Appendix 2 Glossary of Terms Appendix 3 lllustration Tigershark PCI Pentium CPU Board Index List of Tables Table 1 1 DRAM Configuratlons 1 6 Table 2 1 lumpers 2 2 Table 2 2 J6 IDE IRQ14 Disable 2 2 Table 2 3 J9 Cache S1ze 2 3 Table 2 4 J12 Cache S1ze 2 3 Table 2 5 J14 Internal Clock Multiplier 2 4 Table 2 6 J32 Internal Clock Multiplier 2 4 Table 2 7 J22 CPU Clock Speed 0 2 5 Table 2 8 J26 CPU Voltage Regulator
34. d Also be sure the disk is formatted as a boot device Then reboot the system DISKETTE DRIVES OR TYPES MISMATCH ERROR RUN SETUP Type of diskette drive installed in the system is different from the CMOS definition Run Setup to reconfigure the drive type correctly 4 25 Post Messages DISPLAY SWITCH IS SET INCORRECTLY Display switch on the CPU board can be set to either monochrome or color This indi cates the switch is set to a different setting than indicated in Setup Determine which setting 1s correct and then either turn off the sys tem and change the jumper or enter Setup and change the VIDEO selection DISPLAY TYPE HAS CHANGED SINCE LAST BOOT Since last powering off the system the display adapter has been changed You must configure the system for the new display type ERROR ENCOUNTERED INITIALIZING HARD DRIVE Hard drive cannot be initialized Make sure the adapter is installed cor rectly and all cables are correctly and firmly attached Also make sure the correct hard drive type is selected in Setup ERROR INITIALIZING HARD DISK CONTROLLER Cannot initialize controller Make sure the cord is correctly and firmly installed in the bus Be sure the correct hard drive type is selected in Setup Also check to see if any jumper needs to be set correctly on the hard drive FLOPPY DISK CNTRLR ERROR OR NO CNTRLR PRESENT Cannot find or initialize the floppy drive controller make sure the controller is correctly installed If
35. e in the BIOS will not be saved and the original configuration will remain unchanged 4 1 Setup Screens e All BIOS screens contain body consisting of the entry fields containing the utility s parameters bottom line indicating the keystrokes that you can use to manipulate the cursor in that screen e Manipulating the screens Basically the arrow keys are used to highlight items Enter is used to select the PageUp and PageDown keys are used to change entries F1 is pressed for help and Esc is pressed to quit e lt Uparrow gt Move to previous item Down arrow Move to next item Left arrow Move to the item on the left Right arrow Move to the item on the right e Esc key CMOS Setup Utility Screen Quit and do not save changes into CMOS All other screens return to CMOS Setup Utility Screen e PgUp key Increase the numeric value or make changes PgDn key Decrease the numeric value or make changes key Increase the numeric value or make changes key Decrease the numeric value or make changes e Fl key General help Press F1 to pop up a small help window that describes the appropriate keys to use and the possible selec tions for the highlighted item To exit press Esc or the F1 key again e F2key Change color from total 16 colors F2 to select color forward Shift F2 to select color backward e F3 key Calendar only for Standard CMOS Setup Screen e 5 key Restore the previ
36. ed for users who want to make a cable that connefabte 2 26ial CSliGonoecl ror J5 and termi nates with either a DB9 or DB25 RS232 connector 50 Te SGSIS CORBGeC ooooo0oo0o0000000 id I O00000000000 ee eee 2 16 Chapter 2 Jumpers and Connectors 2 4 6 8 10 C0080 leoooo 13579 68 Indicates connector key position Table 2 27 J8 Keyboard Connector 10 pin e J8 Keyboard Connector 10 pin e J pl 86t d0ifilaeglOynnector An external reset cable can be attached to the Tigershark at J10 Connectors e J11 Speaker Connector Table 2 29 J11 Speaker Connector Placing a jumper on pins 1 and 2 of J11 enables the on board speak er An external speaker can be used with the Tigershark CPU board by installing a four pin connector on J11 Table 2 30 J13 CPU Fan Connector e J13 CPU Fan Connector To connect a CPU fan to the board install a 4 pin connector on J13 2 18 Chapter 2 Jumpers and Connectors e J20 Keyboard mini DIN Connector View from end of board Table 2 31 J20 Keyboard mini DIN Connector J20 is a six pin mini DIN keyboard connector located on the retain ing bracket A standard PC AT compatible keyboard can be used when fitted with the keyboard adapter cable furnished with the CPU board The ten pin keyboard header at J8 can also be used View from end of board Table 2 32 J25 Mouse mini DIN Connector e J25 Mouse min
37. ental Specifications 3 2 Table 4 1 Standard CMOS Setup Screen Entry Fields 4 7 Table 4 2 BIOS Features Setup Screen Entry Fields 4 10 Table 4 3 Chipset Features Setup Screen Entry Fields 4 14 Table 4 4 Power Management Setup Screen Entry Fields 4 18 Table 4 5 PCI Configuration Setup Screen Entry Fields 4 22 Table A1 1 Standard PC ATI O Map Al 1 Table A1 2 DMA Channel Page Register and I O Addresses A1 2 Table A1 3 DMA Channel Assignments AI 2 Table A1 4 DMA Controller Register Functions AI 3 Table A1 5 Interrupts AI 4 Table A1 6 CMOS RAM Address Map A1 5 Table A1 7 Real Time Clock Information A1 6 Table A1 8 ISA Connector Pin Assignments A1 7 Table A1 9 PCI Connector Pin Assignments A1 8 Table of Contents List of Tables Continued Table 2 21 J2 Floppy Disk Drive Connector 2 11 Table 2 22 J3 Parallel Port 2 12 Table A1 10 Post Codes AI 9 Table A1 11 Hard Disk Parameters A1 12 List of Figures Figure 1 1 Tigershark CPU Board Jumpers Connectors and Components d Eege e x ee e e e 646006 Ke Ee e 1 4 Figure 4 1 CMOS Setup Utility Screen 4 4 Figure 4 2 Standard CMOS Setup Screen 4 6 Figure 4 3 BIOS Features Setup Screen 4 9 Figure 4 4 Ch
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39. eserved Reserved Reserved Manufacturing POST Loop or Display Messages Security Check Write CMOS Pre boot Enable Initialize Option ROMs Initialize Time Value Setup Virus Protect Set Boot Speed Setup NumLock Boot Attempt Spurious Unclaimed NMI Setup Pages Boot Description Reboot if Manufacturing POST Loop pin is set Otherwise display any messages i e any non fatal errors that were detected during POST and enter setup Ask password security optional Write all CMOS values back to RAM and clear screen Enable parity checker enable NMI enable cache before boot Initialize any option ROMs present from C8000h to EFFFFh NOTE When FSCAN option is enabled will initialize from C8000h to F7FFFh Initialize time value in 40h BIOS area Setup virus protect according to Setup Set system speed for boot Setup NumLock status according to Setup Set low stack boot via INT 19h If interrupt occurs in protected mode In unmasked NMI occurs display Press F1 to disable NMI F2 reboot E1 Page 1 E2 Page 2 EF Page 16 Table A1 10 Post Codes continued A1 11 Hard Disk Parameter Table Tvpe Size Cylinders Sectors Write Landing ype mB Y Track Precomp Zone 10 305 20 30 62 46 20 30 30 615 615 940 940 D JO Om E G bz I o bo 00 02 P A oa 20 35 49 20 42 0 20 40 56 59 30 42 30 10 40 76 F 3 5 7 8 7 0 4 5 7 F
40. fast DRAM slave devices Type F timing basically runs at 360ns cycle or three ISA clock cycles during the repeated portion of a Block or Demand mode transfer 4 13 Setup Screens Entry Fields Auto Enable to reset most of the chipset setup 1 Enabled Configuration parameters to their defaults preventing 2 Disabled them from being changed individually Disable to change the chipset setup parameters individually AT Bus Clock LCLK 1 same rate as the PCI clock 1 LCLK 1 LCLK 2 1 2 the rate of the PCI clock 2 LCLK 2 LCLK 8 1 3 the rate of the PCI clock 3 LCLK 3 LCLK 2 1 4 the rate of the PCI clock 4 LCLK 4 Hidden Enable allows DRAM refresh to use hidden 1 Enabled Refresh CPU cycles Disabled the DRAM 2 Disabled refresh uses normal CPU cycles default DRAM Enable to eliminate a wait state to DRAM 1 Enabled Posted Write Disable for CPU write cycles to wait for 2 Disabled DRAM cycle default DRAM Slow Enable to allow a slower refresh rate 1 Enabled Refresh providing a marginal increase in system 2 Disabled performance default CPU Adaress Enable results in increased throughput Enabled Pipelining Disable for no adaress pipelining Disabled default Byte Merge Enable buffers CPU to PCI writes When Enabled Support disabled writes are not buffered Disabled Tag RAM Enter 7 or 8 bits to be used for tag RAM 7 bit default Size information 6 bit Tag Dirty Combine Tag and
41. for the DRAM to complete the update write through cache The process where the CPU updates the cache and the DRAM simultaneously but the CPU waits for the DRAM to complete the update resulting in more time being consumed than in write back A2 4 L EV pleog NdI guinued I2d w J4S196 eiqesiq eiqeu3 o peeds J0joeuuo2 DopuojeM 4019 EN Aayeg jeuiex3 e qeu3 L t eBesn SCT OHI esnow tim 1009uU09 AJT LOHI 4o1eInBei o 401984 OH eua eer eDeyoA ndo y90IO jeuieju jeudi l m Ka Ler oer zer II MOO Eu1etu III Mh TI ve U wei OU d II l S ca 2008 BGO 0900996 piomsseq I oSooosso7 iooeososso Seeeececch dE m ver i 1 Nig tuiw o SE mm eo oh esnolN En d f ie L ser BEE E n dom Ett i E LER emer pom Bins m me mmm nmm mm L hie m a IT Les dE mer E me mn hom LN mui wl uid 01 il Bn gn ail SIE 10I0euuo2 dm TEE e E E N0 0N 0000011710010 017 preogkey EEA ES Es aj aa e e T er 0000000000000000 06000000000000 000poo isal MOd we oeuuo2j 9Iq SIq uonosjes 101929uuo2 J1B9 2 OID Aere 10199uuO2 ZO jesoy yLDHI 20 ddol4 Jal SONO F food dois gp aNd H our or
42. hapter 1 Introduction introduces you to this manual and to the Tigershark CPU board Chapter 2 Jumpers and Connectors describes the jumpers and connectors on the Tigershark CPU board First each jumper is described A table shows where to place the jumper for your specific configuration An illustration of the jumper indicates the pin numbers Then each connector is described A table shows the pin out descriptions and an illustration shows the pin numbers of each connector Chapter 3 Specifications provides the component data and environmental characteristics of the Tigershark CPU board Chapter 4 BIOS explains how to use the BIOS setup utility firmware of the Tigershark CPU board Appendix 1 Technical Reference provides additional information to help you configure your CPU board and attach external peripheral devices Included are I O Maps I O Channels Interrupts and Address Maps and ISA and PCI connector pin assignments Appendix 2 Glossary of Terms contains definitions of terms used in this manual as well as terms that refer to items discussed Appendix 3 Illustration provides a convenient fold out illustration of the Tigershark CPU 1 2 Chapter 1 Introduction board Index provides easy access to page numbers of items discussed Preparing the board Unpacking your CPU board The Tigershark CPU board is shipped in a sealed anti static shield ed bag Open the bag at a static free workstat
43. i DIN Connector The mouse and keyboard mini DIN connectors are identical Make sure the correct accessory is plugged into it s proper connector 2 19 Connectors J25 is a six pin mini DIN mouse connector located on the retaining bracket CAUTION o Cathode Table 2 33 J27 External Hard Drive LED e J27 External Hard Drive LED Connector An LED can be connected at J27 to indicate IDE or SCSI hard drive activity Pint Nam Positive Terminal ees ol 2 JC ola O 4 Negative Terminal Table 2 34 J28 External Battery Connector e J28 External Battery Connector If specific safety restrictions prevent the use of the on board lithium battery an external battery can be connected at J28 2 20 Chapter 3 Specifications System Components CPU Form Factor Interrupts Power Requirements Cache Dynamic RAM System ROM Clock Calendar External Connections Watchdog Timer 3 3V Pentium Standard full length AT 15 levels available Input Power 45V 9 3 5A 12V 50mA 12V 50mA 512K write back write through cache Supports up to 256MB on board 36 bit DRAM SIMM using 70ns x 36 SIMMs Contains system BIOS Real time clock backed by an on board lithium battery IDE amp floppy shrouded headers Bidirectional parallel port shrouded header Serial port 1 shrouded header Serial port 2 shrouded header Keyboard mini DIN on retaining bracket M
44. ing functions that are user configureable when User Defined is selected from the Power Management parameter 4 17 Setup Screens PM Events PM events are I O events whose occurrence can prevent the system from entering a power saving mode or can awaken the sys tem from a power saving mode In effect the system remains alert for any device configured as Enable even when the system is in a power down mode Entry Fields Beso L See Explanation page 4 17 1 Disable default 2 Min Pwr Sav 3 Max Pwr Sav 4 User Defined Yes to activate Advanced Power Mgmnt 1 Yes enhancing the Max Pwr Sav mode and stop 2 No the CPU internal clock Video Off Selects which combination of the PM Timers 1 Susp Stby Option modes causes video to turn off Selection 3 Off Always On means none See page 4 17 2 All Modes an explanation Off 3 Always On 4 Suspend gt Off Video Off Selecting 1 causes the system to turn off the 1 V H SYNC Method vertical and horizontal synchronization ports Blank and write blanks to the video buffer Selecting 2 Blank Screen 2 causes the system to only write blanks to the video buffer When enabled and after a set time of system 1 Enabled inactivity the hard disk drive will be powered 2 Disabled down while all other devices remain active When enabled and after the set time of 1 Enabled system inactivity the CPU clock will run ata 2 Disabled sl
45. ing the computer turning the power switch OFF and then ON or by pressing the RESET 4 3 Setup Screens button or by pressing Ctrl Alt and Delete ROM PCI ISA BIOS CMOS SETUP UTILITY AWARD SOFTWARE INC STANDARD CMOS SETUP INTEGRATED PERIPHERALS BIOS FEATURES SETUP SUPERVISOR PASSWORD CHIPSET FEATURES SETUP USER PASSWORD POWER MANAGEMENT SETUP IDE HDD AUTO DETECTION PNP PCI CONFIGURATION SETUP HDD LOW LEVEL FORMAT LOAD BIOS DEFAULTS SAVE amp EXIT SETUP LOAD SETUP DEFAULTS EXIT WITHOUT SAVING Esc Quit Select Item F10 Save amp Exit Setup Shift F2 Change Color Time Date Hard Disk Type e CMOS Setup Utility Screen Figure 4 1 CMOS Setup Utility Screen Explanation The CMOS Setup Utility screen allows selection of eight setup screens and two exit choices Use the arrow keys to move between choices and press Enter to select the highlighted choice Entry Fields Standard CMOS Setup This setup screen allows you to configure the calendar hard drives floppy drives video mode and the Halt On command BIOS Features Setup This setup screen allows you to configure virus warning cache boot sequence keyboard security shadowing and SCSI Chipset Features Setup This setup screen allows you to configure the system memory 4 4 Chapter 4 BIOS Power Management Setup This setup screen only displays if the system supports Power Management Green PC standards
46. ion while observing proper Electrostatic Discharge ESD practices When not installed in a computer chassis this board must be sealed in an ESD approved shielded bag This board must be shipped in a sealed ESD approved shielded bag and protected with anti static packaging material e g bubble wrap I Bus reserves the right to refuse warranty service on units not CAUTION Components on this board are sensitive to damage from Electrostatic Discharge ESD Handling of this board should ONLY be done by a properly trained technician in an approved ESD work area Packaged with your Tigershark CPU board is Tigershark PCI Pentiun CPU Board with SCSI User Manual Optional memory Keyboard adapter cable Optional cables If any of the items have been damaged in shipping notify the transit company and initiate an insurance claim If any items are missing contact I Bus Refer to the Limited Warranty in the back of this manual for further instructions 1 3 Features J8 J20 J25 Keyboard Mouse J24 Keyboard J11 TI har Connector 10 pin Speaker mini DIN mini DIN Security Password Enable Connector M J31 COM Port san O pei Parallel Port DMA J28 External Battery Connector 00000 noooo J10 Reset Connector ooodlo noodlo J5 COMI Port J6 IDE IRQ14 Disable J30 Mouse IRQ Enable J3 Parallel Port J19
47. ipset Features Setup Screen 4 12 Figure 4 5 Power Management Setup Screen 4 17 Figure 4 6 PCI Configuration Setup Screen 4 21 Chapter 1 Introduction Welcome to the LBus family of passive backplane CPU Central Processing Unit boards This manual contains information necessary to configure your CPU board to your specific needs The Tigershark PCI Pentium CPU board is IBM PC AT compatible utilizing the 3 3 V Pentium processor It provides a passive backplane interface for both PCI and ISA expansion It also provides a SCSI II on board controller and interface as well as provid ing conventional CPU board peripherals This chapter is divided into three sections e About this manual explains how this manual is laid out and what you can expect to find in it e Preparing the board describes the procedure for unpacking the Tigershark CPU board and preparing it for use in your system e Features of the board provides a brief overview of the major components of the Tigershark accompanied by an illustration showing its jumpers con nectors and components For convenient reference a fold out illus tration is also provided at the back of this manual M3 About this manual This manual contains four chapters pertaining specifically to your CPU board The appendices contain technical reference material a glossary of terms and a fold out illustration of the board followed by an index C
48. labor repair or material cost injury to person or property or any similar or dissimilar consequential loss or damage incurred by purchaser even if I Bus has been advised of the possibility of such losses or damages In order to obtain warranty service the product must be delivered to the I Bus facility or to an authorized I Bus service representative with all included parts and accessories as originally shipped along with proof of purchase and a Returned Merchandise Authorization RMA number The RMA number is obtained in advance from I Bus Customer Service Department and is valid for 30 days The RMA number must be clearly marked on the exterior of the original shipping container or equivalent Purchaser will be responsible and liable for any missing or damaged parts Purchaser agrees to pay shipping charges one way and to either insure the product or assume the liability for loss or damage during transit Ship to I Bus ATTENTION RMA REPAIR DEPT RMA 9174 Sky Park Court San Diego CA 92123 Bus may issue at its own discretion an advanced replacement AR on a product if it fails within fifteen 15 days from the date of delivery from I Bus Table of Contents Chapter 1 Introduction About this manual 2er 151515181306 1503150305003 46 Rud 1 2 Preparing the board 1 3 Peat res EET EE 1 5 Chapter 2 Jumpers and Connectors J mpetS A cesses es eee eee NNN EE C c ems 2 2 Conne
49. lectable interrupt channels Counter Timer The 82C558 provides three independent counter channels Counter 1 7 Features 0 is used as a system timer Counter 1 is used to generate pulses for DRAM refresh Counter 2 is a full function counter timer e Direct Memory Access DMA The 82C558 provides seven DMA channels The first four DMA channels are used for eight bit DMA transfers The remaining three channels are used for sixteen bit DMA transfers The sixteen bit DMA channels function identically to the eight bit DMA channels except that bit 0 of the address and the length fields are assumed to be zero All transfers must begin on an even address boundary and the length must be an even number of bytes The sixteen bit DMA channels transfer up to 128 KB while the eight bit DMA channels transfer up to 64 KB PCI The Tigershark CPU board is designed to drive up to but no more than 3 PCI slots Controller OPTi 82C556 and 82C557 PCI Bridge Chip set provides up to three PCI masters are available slots 1 2 and 3 on the backplane CAUTION e a central arbiter to arbitrate the bus requests between host CPU PCI masters DMA ISA masters and refresh a programmable priority scheme for both central arbiter and DMA channels fixed rotating or a combination of the two and combine host CPU sequential writes into PCI burst write cycles e Keyboard Interface The Tigershark uses the 8042 keyboard controller This
50. m 1st 2nd Fast Two DMA channels 0 or 1 can be DMA selected to support Type F timing Channels Table 4 3 Chipset Features Setup Screen Entry Fields Cont 4 15 Setup Screens Enable to use the system onboard floppy 1 Enabled disk controller Disable if FDC board is default Controller installed in system 2 Disabled Onboard Select the IRQ for serial port 1 or disable it 1 COM1 Serial Port 1 COM1 3F8 IRQ4 COM2 2F8 IRQ3 default COM3 2E8 IRQ3 COMA 3E8 IRQ4 COM2 COMS COM4 Disabled Onboard Select the IRO for serial port 2 or disable it COM1 Serial Port 2 COM1 3F8 IRQ4 COM2 2F8 IRQ3 default COM3 2E8 IRQ3 COM2 COMS Disabled Onboard Change the default port address of the 978 IRQ7 Parallel Port onboard parallel printer port or disable it default 1 standard LPT1 address 278 IRQ5 2 standard LPT2 address SBC IRQ7 3 alternate LPT1 address Disabled Table 4 3 Chipset Features Setup Screen Entry Fields Cont 4 16 Chapter 4 BIOS e Power Management Setup Screen ROM PCI ISA BIOS 2A5UNA2I POWER MANAGEMENT SETUP AWARD SOFTWARE INC Power Management Disable Local Devices Enable PM Control by APM Yes IRQ3 COM 2 Enable Video Off Option Susp Stby gt Off IRQ4 COM 1 Enable Video Off Method V H SYNC Blank IRQ5 LPT 2 Enable IRQ6 Floppy Disk Enable PM Timers IRQ7 LPT 1 Enable HDD Off After Disable IR
51. nce Test Setup Low Memory Description OEM Specific Cache control Cache Processor Status 1FLAGS verification Tests the following processor status flags carry zero sign overflow The BIOS will set each of these flags verify they are set then turn each flag off and verify it is off Read Write Verify all CPU registers except SS SP and BP with data pattern FF and 00 Disable NMI PIE AIE UEI SOWV Disable video parity checking DMA Reset math coprocessor Clear all page registers CMOS shutdown byte Initialize timer 0 1 and 2 including set EISA timer to a known state Initialize DMA controllers 0 amp 1 Initialize interrupt controllers 0 amp 1 Initialize EISA extended registers RAM must be periodically refreshed in order to keep the memory from decaying This function assures that the memory refresh function is working properly Keyboard controller initialization Verifies CMOS is working correctly detects bad battery Program chipset registers with power on BIOS defaults OEM Specific Test to size on board memory OEM Specific Early Shadow enable for fast boot External Cache size detection Early chip set initialization Memory presence test OEM chip set routines Clear low 64K of memory Test first 64K of memory Table A1 10 Post Codes A1 9 Post Codes Post Code Early Cache Initialization Setup Interrupt Vector Table Test CMOS RAM Checksum Initialize
52. nd bus mastering The first PCs with PCI buses became available toward the end of 1993 port Ports are used to connect peripheral devices such as external drives and printers to your computer R RAM Random Access Memory The memory used to execute applications while your computer is turned ON When you turn your computer OFF all data stored in RAM is lost real time clock RTC A CMOS counter used to maintain local time retaining bracket The bracket on the end of the board that attaches to the back of the chassis and contains connectors usually key board mouse serial port and or parallel port S serial port A two channel port one channel used for In transmis sions and one for Out transmissions A2 3 Appendix 2 Glossary of Terms SCSI Small Computer System Interface A high speed general pur pose interface to storage devices SRAM Static Random Access Memory As opposed to DRAM this memory does not need to be refreshed by a controller and holds its information as long as the power is on T tag comparator A memory that tells whether an address is available in the cache W wait states Extra time inserted to allow access to slower devices e g DRAM or EPROMS watchdog timer A device that watches for CPU inactivity and then resets the CPU after a specified duration of inactivity write back cache The process where the CPU updates the cache and the DRAM simultaneously but does not wait
53. nternal Clock Multiplier IRQ11 Usage Table 2 1 Jumpers e J6 IDE IRQ14 Disable Placing a jumper on J6 enables IRQ14 for an IDE drive If no jumper is installed on J6 IRQ14 is available for other system use O a OFF IRO14 available factory default setting Table 2 2 J6 IDE IRQ14 Disable 2 2 Chapter 2 Jumpers and Connectors J9 Cache Size Placing jumpers on pins 1 and 3 and pins 2 and 4 enables the 512 K cache Jumpers placed on pins 3 and 5 and pins 4 and 6 enables the 256 K cache This cache size setting must be the same as jumper J12 mee ae 1 amp 3 2 amp 4 512K O Oo AIO Olo njo W amp 3 amp 5 4 amp 6 256K Table 2 3 J9 Cache Size J12 Cache Size Placing a jumper on J12 sets the cache size at 512 K If no jumper is placed on J12 the cache size is set at 256 K This cache size set ting must be the same as jumper J9 Postion tem Table 2 4 J12 Cache Size J15 Factory Test For factory use only Do not use For standard operation no jumper is installed J18 Factory Test For factory use only Do not use For standard operation jumpers are installed on pins 1 amp 4 and 2 amp 3 NJO Oleo ll8 ol J23 Factory Test For factory use only Do not use For standard operation no jumper is installed 2 3 Jumpers e J14 Internal Clock Multiplier see Table 2 9 Placing a jumper only on J14 sets the CPU speed at 2 x the speed
54. oppy drive Position Gem Je o 1 amp 2 1 2MB 1 44 MB slo ola 3 amp 4 5 amp 6 2 88 MB 5lo ole Table 2 12 J19 Floppy Selection 2 6 Chapter 2 Jumpers and Connectors e J21 Watchdog Enable Disable To enable the watchdog timer place a jumper on pins 1 and 2 The address of the watchdog timer is I O 160 and cannot be relocated To free I O 160 for use with other devices the watchdog timer must be disabled To disable the watchdog timer remove the jumper from J21 1 factory default setting Table 2 13 J21 Watchdog Enable Disable e J24 Security Password Enable Placing a jumper on pins 1 and 2 of J24 enables the security pass word option in the BIOS Setup Utility With this jumper installed the password selection is available in the BIOS O M Enable Password a I Password not reguired Table 2 14 J24 Security Password Enable e J29 CMOS Clear To clear CMOS with power ON install a jumper on 1 and 2 wait five seconds remove the jumper from 1 and 2 and reset ro Function ch factory default setting Table 2 15 J29 CMOS Clear 2 7 Jumpers J30 Mouse IRQ Enable Placing a jumper on J30 enables IRQ12 for the mouse If no jumper is placed on J30 IRQ12 is available for other use C Poston Function Mouse on IRQ12 e O 2 IRQI2 available Table 2 16 J30 Mouse IRQ Enable J31 Parallel Port DMA Using DMA channels enables high speed
55. ous CMOS value from CMOS only for BIOS Features Setup Screen e F6 key Load the default CMOS value from BIOS default table only for BIOS Features Setup Screen e F7 key Load Setup defaults e F10 key Save all CMOS changes only for CMOS Setup 4 2 Chapter 4 BIOS Utility Screen This section describes each setup screen in the CMOS Setup Utility Screens and Commands identified on the CMOS Setup Utility Menu are e Standard CMOS Setup e Load Setup Defaults BIOS Features Setup e Password Setting e Chipset Features Setup e IDE HDD Auto Setting e Power Management Setup Save amp Exit Setup e PCI Configuration Setup e Exit Without Saving In this section each utility is represented by e Screen Illustration e Explanation e Entry Fields Screen Illustration The screens presented in this manual reflect the same format as your screens However entry values and selections shown on these screens are examples only Explanation The Explanation following each screen illustration describes the utility and the available choices Entry Fields Each entry field in the body of the screen is described and all available choices or parameters are listed e CMOS Override If the system fails to boot after changes are made to the BIOS Setup a CMOS override can be invoked by pressing the Insert key when the computer is rebooted This resets the system to its defaults The system can be restarted by power cycl
56. ouse mini DIN on retaining bracket Keyboard Ten pin header Speaker header Reset header Hard Drive LED header Two stage software programmable 3 1 Environmental Specifications Operating Non operating Humidity 5 to 95 40 C 5 to 95 40 C non condensing non condensing Table 3 1 Environmental Specifications 3 2 Chapter 4 BIOS The BIOS Setup Utility allows you to configure your CPU board to your system The BIOS or Basic Input Output System is the on board firmware that communicates with the display keyboard print ers and other peripheral devices Starting and Exiting the BIOS Setup When you turn on your computer a test is conducted called the Power On Self Test or POST During this test the system checks for certain hardware configurations and compares them to the BIOS Setup Utility If at boot the system status does not match the system configuration stored in CMOS you will be prompted to start the BIOS Setup Utility To Start the BIOS Setup e During a cold boot press Del when prompted To Exit the BIOS Setup and boot the computer e While in any utility screen press Esc to return to the CMOS Setup Utility Screen If SAVE amp EXIT SETUP is selected all configuration changes edited in the various screens are recorded in CMOS memory at this time If EXIT WITHOUT SAVING is selected or if power is turned off or the front panel reset but ton is pressed the changes mad
57. ower speed while all other devices still operate at full speed Table 4 4 Power Management Setup Screen Entry Fields 4 18 Chapter 4 BIOS When enabled and after the set time of 1 Enabled system inactivity the fixed disk drive and the 2 Disabled video would be shut off while all other devices Still operate at full speed When enabled and after the set time of 1 Enabled system inactivity all devices except the CPU 2 Disabled will be shut off When Enabled is selected any request 1 Enabled to the DMA controller will awaken default the system 2 Disabled If this is enabled any video activity will 1 Enabled awaken the system 2 Disabled default When set to Enable any event Enabled 1F0 170 occurring at a hard disk drive will awaken default the system Disabled LPT When set to Enable any event Enabled occurring at a printer port LPT 1 3 will default awaken the system 2 Disabled COM Port When set to Enable any event occurring Enabled 3F8 3E8 ata COM 1 or COM 3 port will awaken default the system Disabled COM Port When set to Enable any event occurring Enabled 2F8 2E8 at a COM 2 or COM 4 port will awaken default the system 2 Disabled PCI Masters When set to Enable any event from 1 Enabled a PCI bus master will awaken the system default 2 Disabled Table 4 4 Power Management Setup Screen Entry Fields Cont 4 19 Setup Screens Local Devices
58. rd will be required both at boot and at entry to Setup If set to Setup prompting only occurs when trying to enter Setup 4 24 Chapter 4 BIOS e POST Messages During the Power On Self Test POST if the BIOS detects an error requiring a fix it will either sound a beep code or display a mes sage However there is only one beep code in BIOS This code indicates that a video error has occurred and the BIOS cannot ini tialize the video screen to display any additional information This beep code consists of a single long beep followed by two short beeps When a POST message is displayed it will be accompanied by PRESS F1 TO CONTINUE DEL TO ENTER SETUP Error Messages One or more of the following messages may be displayed if the BIOS detects an error during the POST CMOS BATTERY HAS FAILED CMOS battery is no longer functional It should be replaced CMOS CHECKSUM ERROR Checksum of CMOS is incorrect This can indicate that CMOS has become corrupt This error may have been caused by a weak battery Check the battery and replace if necessary DISK BOOT FAILURE INSERT SYSTEM DISK AND PRESS ENTER No boot device was found This could mean that either a boot drive was not detected or the drive does not contain proper system boot files Insert a system disk into Drive A and press Enter If you assumed the system would boot from the hard drive make sure the controller is inserted correctly and all cables are properly attache
59. required to 1 9 Chapter 2 Jumpers and Connectors This chapter describes the Jumpers and connectors on the Tigershark CPU board Jumpers and connectors are identified by the label shown beside them on the board e g J1 followed by the descrip tion e g IDE Connector A table shows the jumper settings or connec tor pin outs for each jumper and connector Illustrations of jumpers and connectors are shown from the component side of the board Pin 1 is identified by the black pin All of the jumpers and connectors are shown on the illustration on page 1 4 Figure 1 1 Tigershark CPU Board Jumpers Connectors and Components and on the fold out illustration on page A3 1 Pin 1 can be identified on the solder side of the board by the square pad in a connector or jumper CAUTION Components on this board are sensitive to damage from Electrostatic Discharge ESD Handling of this board should ONLY be done by a properly trained technician in an approved ESD work area 2 1 Jumpers The following jumpers are factory set If the system is reconfigured some of the jumpers may need to be reconfigured IDE IRQ14 Disable Cache Size Cache Size Internal Clock Multiplier Factory Test Stop Clock Cache Policy Factory Test Floppy Selection Watchdog Enable Disable CPU Clock Speed Factory Test Security Password Enable CPU Voltage Regulator CMOS Clear Mouse IRQ Enable Parallel Port DMA I
60. st the BIOS to use an off board controller Can I use a SCSI controller and where should I set the address A1 You can use a SCSI controller You must set the card address for the primary controller in the system Then find an available appropriate address to set the SCSI BIOS to A2 YOU MUST DISABLE THE ON BOARD IDE CONTROLLER IF YOU WANT THE SCSI CONTROLLER TO BE THE BOOT DEVICE Can I use an ESDI controller and where should I set the address A1 You can use an ESDI controller The address should be set for the primary controller in the system Then find an available appropriate address to set the ESDI BIOS to 4 28 Chapter 4 BIOS A2 YOU MUST DISABLE THE ON BOARD IDE CONTROLLER IF YOU WANT THE ESDI CONTROLLER TO BE THE BOOT DEVICE Q7 What preventive maintenance steps can I take A Ensure all fans in the chassis are working Clean the filter with warm water or compressed air Replace brittle or torn filters Allow ample air circulation behind the chassis Keep all cables free from tangles CAUTION Electrostatic Discharge ESD may damage memory chips programmed devices and other electrical components ESD can be prevented by wearing a wrist strap attached to a ground post on a static mat Grounding can also occur by touching a chassis that is plugged into a power outlet 4 29 Appendix 1 Technical Reference Standard PC AT I O Map Sep Lee Color Graphics Display Adapter Table A1 1 Standard PC
61. tup Defaults Figure 4 3 BIOS Features Setup Screen Explanation This setup screen contains parameters that configure the system for basic operation Use the arrow keys to highlight the item and then use the PgUp or PgDn keys to select the value for each item Virus Warning You will need to disable this option while using cer tain fixed disk maintenance programs e g DOS FDISK because their actions would be interpreted as a violation Boot Sequence The BIOS assumes that Drive C is the hard disk drive and Drive A is the floppy disk drive Security Option To disable the Security Option select PASSWORD SETTING from the CMOS Setup Utility screen When prompted to enter a new password do not enter anything just press Enter This dis ables security Once security is disabled the system will boot and Setup can be entered Setup Screens Shadow RAM Shadow RAM is a mechanism that copies Read Only Memory into main memory then substitutes that memory image for the original ROM This increases the execution speed of programming that resides in ROM BIOS and VGA Adapters are two main examples of ROMs that demonstrate significant performance gains when they are shadowed Since ROMs are by definition Read Only it is usually desirable to write protect the Shadow RAM However Shadow RAM can also be used as general purpose memory by certain programs In this case it should be enabled as Read Write memory While most

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