User Manual - US Technologies
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1. 12 to 0 Always set to zero Page 6 28 Issue 1 Functional Description Radstone PMC ATMF Manual Transmit Status Queue Head Register TSQH sits Mnemonic Ee CS 31to13 Always set to zero 12 to2 TSQHA Transmit Status Queue H ead address offset This field is written by the device driver to indicate the last entry in the TSQ that the device driver has serviced At initialisation this register should be reset This field is used together with the TSQB field in the TSQT register to form a complete physical address i e on a longword boundary for the TSQ Head pointer to the host memory Page 6 29 Issue 1 Radstone PMC ATMF Manual Functional Description General Purpose Register GP The General Purpose register is used for three different types of operation 1 To dock information out of or into the external serial EEPROM 2 Toreset the PHY TC component 3 Accumulating the Tx negative credit count When clocking information out of or into the serial EEPROM the device driver controls the waveform of the EEPROM s clock input and the polarity level of the EEPROM s chip select input via bit fields in this register When reading information from the EEPROM the device driver reads the EEPROM Data In bit bit 16 of this register the value in this bit corresponds to the polarity level of the serial EEPROM s output pin When writing information to the EEPROM the device driver writes to the EEPROM Data Out bit bit 02. Transmit Schedule Table Base Register TSTB sie Mnemonic Ee 31to19 Always set to zero 18 to 2 TSTBA Transmit Schedule Table Base address The default is 0x0000 This register is written by the device driver to specify the base or start address of the TST in local SRAM This value should not be changed after the Tx operation is enabled Transmit Status Queue Base Register TSOB ae mnemo Ee 31 to 13 TSQBA Transmit Status Queue Base Address The default is 0x0000 This field specifies the start address for the TSQ in host memory This field is loaded with a default value during device initialisation after reset and may not be changed during runtime This field must be a multiple of 8192 bytes 12 to 0 Always set to zero Transmit Status Queue Tail Register TSOT ae mnemo Ee 31 to 13 Transmit Status Queue address or This field specifies the start address for the TSQ in the host memory This 31to12 field is the same as the TSQBA field in the TSQB register It is repeated here to help the host to get the complete Transmit Status Tail Pointer in or one read operation 31to11 Transmit Status Queue Tail Address This field is read together with the TSQB field above to form a complete physical address i e on a longword boundary for the TSQ Tail pointer to the host memory The tail always points to the address 0xXXXXXXO The NICStAR updates this Tail pointer offset to reflect the last valid entry intheTSQ
3. ccceessscsssseeeseeesees Level 2 Extended Temperature G stvlei Level 3 Rugged Air cooled RA style ccee Level 4 Rugged Conduction cooled RC style Chapter 3 Unpacking and Inspection Clint ot lel ur EE Beard Ee ai gtge 18 To EE Maia ME A E A EI Chapter 4 Connectors Lane P12 EE oe DEEG Chapter 5 Configuration and Installation ere aL ITT EE MSC AN AU ON EEN Contents i Issue 1 Radstone PMC ATMEFE Manual Radstone PMC ATMF Manual Chapter 6 Functional Description EE 6 1 EENEG 6 1 Confip raton Be 6 2 Vendor RE 6 2 Device ID REPED ics eivsicuis anata va EE EE 6 2 Commaod Reri aaa a E ean cadyeues sastaaeaunes NA 6 3 Sats EE 6 4 PEIL Configuraton RESIS E 6 5 e EE en 6 5 VO Base Geteste geseet 6 6 Memory Base Address Registers sinstncnannaccncrnrnacin mannan dinennmaptioruanin EE 6 6 IP Spansion ROM Base Address IR Geis lets cxsivisiivcnseznsenasis i A E maa ea 6 6 Bus Grant and Interne E 6 7 Klee SR EE 6 8 Data Repister Oto Data Register 3 vsscssssssssiesinasresivnsnnisinasavnsenivis KEE Eddie 6 9 Command REISER iupra an E EAN OAR EEA EAT 6 10 Conii uration RG SISter EES 6 16 SANSER Epa A E 6 20 Receive Status Queue Base R cistEisanneroin anina EA EA A 6 22 Receive Statis Queue Tail E EE 6 23 Receive Sote Orcus E E 6 24 Cell Drop Conn Reg Ste i beet dereen GEES 6 25 VPUVCL Lookup
4. 40 to 75 Air with airflow Cooled of 600 ft min 50 to 100 50 to 100 50 to 100 0 00292 H z from 10 to 2000 Hz random and 2g sinusoidal from 5 to 500 Hz 20g peak sawtooth 1lms duration 0 002g2 Hz from 10 to 2000 Hz random and 2g sinusoidal from 5 to 500 Hz 20g peak sawtooth 1lms duration 0 04g2 Hz from 10 to 2000 Hz with a flat response to 1000 Hz 6dB octave roll off from 1000 to 2000 Hz 20g peak sawtooth 1lms duration Conduction Cooled Boards Build Operating Storage Vibration Humidity Comments Style Temp C Temp C 40 to 75 at the thermal interface Rugged Conduction Cooled 50 to 100 Random 0 192 Hz from 5 to 2000 Hz per MIL ST D 810E 40g peak sawtooth Lin duration Radstone PMC ATMF Manual Up to 95 RH Up to 95 RH with varying temperature 10 cycles 240 hours Up to 95 RH with varying temperature 10 cycles 240 hours Up to 95 RH with varying temperature 10 cycles 240 hours Commercial grade cooled by forced air for use in benign environments and software development applications As standard but conformally coated and temperature characterised Wide temperature rugged cooled by forced air Conformally coated for additional protection Mechanically compliant with IEEE 1101 2 1992 Designed for severe environment applications with high levels of shock and vibration small space envelope and r
5. ATMF Manual Appendix A Specifications This appendix gives a specification of the PMC ATMF It also covers items such as the power requirements the MTBF the general measurements etc and lists the available variants General PCI Bus Interface Compliance Environment Type Stacking Height Dimensions PMC Slots Air Cooled Conduction Cooled Side Area not Occupied EEPROM Size Use Flash Size Use Connectors P12 P14 IEEE P1386 1 PMC standard 5V supply and signalling 33 MHz clock 32 bit slave only 10 mm 1 149 x 74mm 143 75 x 74mm Side 1 Side 2 256 K x 8 bit serial Program and data storage plus user data 512 K x 8 bit Contains code to execute BIT functions EIA E700 AAAB Provide control signals and address data of the PMC bus Appendix A 1 Issue 1 Radstone PMC ATMF Manual Electrical Power supplies and ground are shared between the connectors Current Consumption 1 2A maximum at 5V DC 0 15A at 12V Voltage Supply Requirements 5V 0 25V DC total excursion including all transients Vripple 5V 50mV RMS max contained within the total excursion Appendix A 2 Issue 1 Specifications Specifications Environmental Specifications Convection Cooled Boards Build Operating Storage Vibration Humidity Style Temp C Temp C Standard 0 to 55 with airflow of 300 ft min Extended Temp 20 to 65 with airflow of 300 ft min Rugged
6. Brrot Count Register iiisincnssnsncniinsmnicnciatniiannamnnnmnne ren 6 26 tere 6 27 LEE aa tid ts Ried dango rE cata 6 27 RTE 6 27 Transm Schedule Table Base Reeser nunnia a AAR ARTAR 6 27 L SCHT EE 6 28 Transm Stats wee Tal Re ISEE jae aa o EE EENE A A NEEN ENEE EEE EPEE 6 28 Transmit Sans Owes SE 6 29 General Purpose Register scneniasonianiiri i nAn NARA nei sani TAS a 6 30 KO RE EE 6 31 Boer SRAM Memory E 6 32 SEU EE 6 33 PIAS ngno Renee oR ERNE 6 33 UL EC 6 33 Chapter 7 Troubleshooting Appendix A Specifications Eeer A 1 Een A 2 Environmental Specwications prinsin as E E AR A RAR A 3 Mechanical EE EE perrieri ra rrer e n EA EER TEA AAA A 4 LE A 5 UE A 5 Glossary Index Page ii Issue 1 Introduction Radstone PMC ATMF Manual Chapter 1 Introduction Radstone s PMC ATMF is a 155 Mbits sec ATM adapter for use in OC 3 fiber networks PMC based the PMC ATMF is a fourth generation adapter that has been developed to address the need for reliable high performance ATM in embedded systems Applications for the PMC ATMF range from low cost LANs through enterprise level ATM backbones to edge devices for WANs providing added value services The PMC ATMF forms part of an expansion board range complementing Radstone s latest generation of PMC compatible PowerPC based single board processors adding industry leading price performance ATM functionality in a single VME slot Like all Radstone s VME produc
7. Count The default is 0x0000 The NICStAR increments this register if either of the following conditions occur 1 The received cell s VPI VCI field does not map into the Receive Connection Table or 2 The received cell s VPI VCI field maps into the Receive Connection Table but the Open Close field for the VC is set to Close If the VPIVVCI Error Cell Accept bit is set in the Configuration register each cell received is transferred directly into the Raw Cell Queue in host memory If the VPI VCI Error Cell Accept bit is dear the default this counter is incremented and each cell received with either of the above conditions is discarded they are not stored into the Raw Cell Queue This register is cleared after being read by the device driver Page 6 26 Issue 1 Functional Description Radstone PMC ATMF Manual Invalid Cell Count Register ICC sits Mnemonic Ee CS 31to 16 Always set to zero 15 to 0 IVCNT Invalid Cell Count The default is 0x0000 The NICStAR increments this register if both the GFC field of the received cell is not equal to zero and the Invalid Cell Accept bit in the Configuration register is set In this case the cell received is transferred directly to the Raw Cell Queue in host memory If the Invalid Cell Accept bit is clear the default this register is incremented but the cell received is discarded the cell is not stored into the Raw Cell Queue This register is cleared after being rea
8. LAN which allows up to 1024 nodes to communicate with one another Ethernet was originally developed by the Xerox Corporation in 1972 FBD Free Buffer Descriptor FDDI Fiber Distributed Data Interface A standard for fiber optic cable data transmission FIFO First In First Out A data queuing mechanism or the implementation of it in which the first item stored is the first item processed Flash A type of high capacity EEPROM Glossary ii Issue 1 Radstone PMC ATMF Manual GFC ID Identification IDT Interrupt Decriptor Table IEEE Institute of Electrical and Electronic Engineers UO Input Output IRQ Interrupt Request LAN Local Area Network Where several hosts and devices are near each other maximum distance about 500 m and physically connected by cables Typically these are Ethernet cables LED Light Emitting Diode A semiconductor diode that radiates light LEDs that emit in the visible region are used as indicators or warnings Little Endian Where a system stores bytes with most significant byte stored at lower address Longword A 32 bit data structure in VME systems Cf word halfword LSB Least Significant Bit Master A VMEbus master initiates bus cycles to transfer data between itself and a slave module MBPS Million Bits Per Second Mezzanine The American term for a daughter board Glossary iii Issue 1 Radstone PMC ATMF Manual MLT Master Latency Timer MSB
9. may not change or it during run time 31to11 Bit usage is defined as follows Size of RSQ Base Address Reserved Bit Field Each entry in the RSQ is four longwords or 16 bytes The RSQ size is set in bits 23 and 22 of the Configuration register 12 and 11 Ko S i May be zero See the above table for the actual bit field size Page 6 22 Issue 1 Functional Description Radstone PMC ATMF Manual Receive Status Queue Tail Register RSQT This register sets the tail address for the RSQ ee Leet SSC into O 31 to13 Receive Status Queue Base or This field specifies the starting address for the RSQ in the host memory 31to12 This field is the same value as the RSQBA field in the RSQB register It is repeated here to help the host get the complete RSQ Tail Pointer in one or read operation Bit usage depends on the size of the RSQ 31to11 Receive Status Queue Tail Pointer Offset This field is read together with RSQB field to form a complete physical address i e on a longword boundary for the RSQ Tail pointer to the host memory Bit usage is defined as follows The RSQ size is set in the Configuration register bits 23 and 22 The NICStAR updates this tail pointer offset to reflect the last entry valid inthe RSQ Page 6 23 Issue 1 Radstone PMC ATMF Manual Functional Description Receive Status Queue Head Register RSQH This register sets the head address for the RSQ ais meest Ee 31 to 13 or Reserved Al
10. of this register the value of this bit determines the polarity of the serial EEPROM s input pin The register has the following layout ae meest SSC nto Sd 31 to 24 TXNCC Tx Negative Credit Count This field specifies the number of cell times the NICStAR s 9 cell Tx Cell Out FIFO is empty It counts up to OxF F and wraps around 23 to17 Always set to zero 16 EEDI EEPROM Dataln The value in this bit corresponds to the polarity level of the NICStAR s input pin which should be connected to the serial EEPROM s output pin 15 BIGE Big Endian operation 0 PCI Data transferred in Little Endian 1 PCI Data transferred in Big Endian 14 to 4 Always set to zero 3 PHYRST PHY Reset If clear the default the PHY_RST pin is set high If set the PHY_RST pin is set low i e asserted 2 EESCLK EEPROM Clock The value in this bit corresponds to the polarity level of the serial EEPROM s clock input To clock information out of or into the serial EEPROM the device driver needs to send a 0 1 0 1 etc transition to this bit field while simultaneously carrying out the EEPROM access 1 EECS EEPROM Chip select The value of this bit determines the polarity of the serial EEPROM s chip select input pin EEDO EEPROM Data Out The value in this bit determines the polarity of the NICStAR s output pin which should be connected to the serial EEPROM s data input pin Page 6 30 Issue 1 Functional Description Radsto
11. operation These bits are read only and always read as 01 for medium decode time one wait state 28 TGABT Target Abort The default is 0 0 NICStAR Master bus cycles are not aborted by a target device 1 NICStAR Master bus cycles are aborted due to target aborting This bit is deared by writing a 1 toit 29 MRABT Master Abort The default is 0 0 NICStAR Master bus cycles were completed successfully 1 DEVSEL signal from target was not activated after seven PCI clocks This bit is deared by writing a 1 toit 31 PARER Parity Error The default is 0 0 No parity error was detected 1 At least one parity error was detected This bit is set regardless of the setting of bit 6 in the Control register This bit is deared by writing a 1 toit Page 6 4 Issue 1 Functional Description Radstone PMC ATMF Manual PCI Configuration Register 1 The contents of this read only register are not changed by a PCI bus reset or software reset This register has the following layout sits Mnemonic Ee O O 31 to 24 Base Class code Reads as 0x02 23 to 16 Sub class code Reads as 0x03 15 to 8 Prog Interface Programmable Interface Reads as 0x00 Revision ID Reads as 0x02 PCI Configuration Register 2 This register has the following layout sits mnemonic Ee O O 31 to 24 BIST Reads as 0x00 BIST is not used 23 to 16 Header Type Reads as 0x00 to indicate the layout of the above configuration space format 15 to 8 Laten
12. seseeeeeeeeeeee 6 26 VPI V CIMasK cerier og tbvcsseteasicte caeessooss 6 31 L Related Documents 1 6 LEEDS E 6 33 Reliability ect A 5 Dank ssc HPs Nia ennai acai 3 2 Revision State cccccccceseeeceseneesesens See Board ID M Mechanical Overview 2 4 Memory Man 6 32 RRE See Reliability Index i Issue 1 Radstone PMC ATMF Manual A Serial Number See Board ID EE See Dimensions SPECUA CATIONS g2s se sebcesses levee Enae Eerie Sei a A 1 leben user ae e ats A 2 Environmental c cccccccccsesscccececsesseeeeeeeeenes A 3 Gren ral AET EE see Se erased tastes A 1 Storage Environment See Specifications Environmental T Technical Help Line Number 7 1 Troubleshooting ccceeesceeseceereeeneeceneeenseceneees 7 1 U Unpacking gerne EENS 3 1 H Voltage Supply Requirements 0 0 0 0 eee A 2 WwW KE TE 1 4 KEE A 4 World Wide Web tes 1 6 Index ii Issue 1
13. stand offs are in position on the PMC ATMF module 2 Remove the PMC slot filler from the host s front panel in the position where you want the PMC ATMF to go 3 Pass the bezel front panel of the PMC ATMF through the vacant PMC slot opening in the host s front panel Press the PMC ATMF s connectors into the corresponding connectors on the host Refer to Figure 5 1 overleaf 4 When the PMC ATMF board is correctly positioned secure it to the host board using the supplied screws into the stand offs CAUTION THIS PRODUCT IS CLASS 1 ELECTROSTATIC DISCHARGE SENSITIVE USE ESD PRECAUTIONARY MEASURES WHEN HANDLING IT Connection to the PMC ATMF in build levels 1 and 2 is by an industry standard SC optical connector Page 5 1 Issue 1 Radstone PMC ATMF Manual Configuration and Installation The connection of the PMC ATMF toa conduction cooled PowerPC host board e g the PPC2 604RC conforms with the Draft Standard for Conduction Cooled PMCs and is similar to the procedure for connection to an air cooled host To connect the PMC ATMF to a conduction cooled host 1 2 Before connection check that the stand offs arein position on the PMC ATMF module As there is no bezel front panel on the conduction cooled PMC ATMF simply press the PMC ATMF s connectors into the corresponding connectors on the host Refer to Figure 5 2 When the PMC ATMF board is correctly positioned secure it to the host board using the
14. to zero 29 RXPTH Receive path Enable The default is 0 0 Disable receive path No RX cells are accepted from the PHY by the NICStAR 1 Enable receive path Allow RX cells to enter the RX cell FIFO If disabling during a receive cell operation the NICStAR will completely receive the cell and then stop the receive operation 28 and 27 SMBUF Small Receive Buffer Size Specifies the size of each buffer in the Small Buffer Pool 00 48 bytes Default 01 96 bytes 10 240 bytes 11 2 Kbytes 26 and 25 LGBUF Large Receive Buffer Size Specifies the size of each buffer in the Large Buffer Pool 00 2048 bytes Default 01 4096 bytes 10 8192 bytes 11 16384 bytes 24 EFBIE Empty Free Buffer Queue Interrupt Enable The default is 0 0 No interrupt to the host when the Small and or Large F ree Buffer Queue is empty 1 Generate an interrupt to the host when the Small and or Large F ree Buffer Queue is empty 23 and 22 RXSTQ Receive Status Queue size Specifies the size of the RSQ 00 2048 bytes Default 01 4096 bytes 10 8192 bytes 11 Reserved Page 6 16 Issue 1 Functional Description Radstone PMC ATMF Manual ae Leer SSC nto Sd 21 ICAPT Invalid Cell Accept The default is 0 0 Invalid cells GFC is non zero in the cell header are discarded and the Invalid Cell Counter is incremented 1 Invalid cells are received into the Raw Cell Queue and the Invalid Cell Counter is not incremented 20 IGGFC Ignore GFC The defau
15. 20 Cp C16 C14C013C12 R27 R26 a St z 3 2 cae BE De P ad oe a SH 8 g R20 Rot C24 ee Giel Hez u3 BE C25 U g c37 O O c36 i P P E C 0 ge MFR K7034 PMCATMF 2BB 2 REY H U cal Se o R39 S Gres O c50 O C55 Page 4 1 Issue 1 Radstone PMC ATMF Manual Connectors P11 and P12 Pinouts P11 32 bit PCI P12 32 bit PCI Pin Signal Name Signal Name Pin Signal Name Signal Name ma 4 9 INTD PCI RSVD PCI RSVD PCI RSVD 7 9 Pin EA ER EA EJ EA D E EA 10 12 14 16 18 0 al geg uock ao a9 rere Grane La el mm con ae a een Gran ae el us ms as as abner Lan Le el em Lan a crane Lamm Le el moa a so aw aa La al og Lan a so Grama pcrsvo La el cron reo o seg ecrsvd Le Page 4 2 Issue 1 Configuration and Installation Radstone PMC ATMF Manual Chapter 5 Configuration and Installation This chapter describes the configuration of the PMC ATMF and its connection toa PowerPC based host board e g Radstone s PPC1 or PPC2 Configuration There are no user configurable links on the PMC ATMF All configuration is defined via software Installation The connection of the PMC ATMF to an air cooled PowerPC host board e g the PPC1 conforms to the IEEE P1386 1 standard To connect the PMC ATMEF to an air cooled host 1 Before connection check that the
16. 7E8 to 1E7F3 1E7E8 to 1E7F3 SCD1 48 bytes 48 bytes VBR 1E7DC to 1E7E7 1E7DC to 1E7E7 SCD2 48 bytes 48 bytes TST and 1C000 to 1E 7DB 1C000 to 1E7DB TBD 4 CBR SCDs 40 816 bytes 40 816 bytes SCD 12 Not used 10000 to 1BF FF 192 K bytes Rx Connection 00000 to 03F F F 00000 to OF F FF Table 64 K bytes 256 Kbytes Note The addresses provided here are individual 32 bit longword addresses the physical byte address is as above but with 2 least significant zeros Page 6 32 Issue 1 Functional Description Radstone PMC ATMF Manual EEPROM The PMC ATMF is fitted with a 256 x 8 bit serial EEPROM device This is used to store non volatile data such as network addresses etc The device driver software must drive the pins of the EEPROM as explained in the description of the General Purpose Register Flash The PMC ATMF is fitted with a 512 Kbyte x 8 bit Flash device This is used as a standard PCI expansion ROM It contains code to execute BIT functions on the PMC ATMF To access the ROM the transmitter and receiver functions must be disabled This is necessary since the ROM is mapped into main memory and timing is controlled by the PCI master LEDs Levels 1 and 2 of the PMC ATMF havea yellow status LED that when lit shows the link is active Page 6 33 Issue 1 Troubleshooting Radstone PMC ATMF Manual Chapter 7 Troubleshooting Radstone does not anticipate that you will have any problems with your product H
17. Audience This manual is written to cover as far as possible the range of people who will handle or use the PMC ATMF from unpackers inspectors through system managers and installation technicians to hardware and software engineers Most chapters assume a certain amount of knowledge on the subjects of single board computer architecture interfaces peripherals systems cabling grounding and PCI Thereis a glossary provided at the back of this manual that explains some of the terms used and expands all abbreviations Documentation Scope This manual describes all variants and build standards of the PMC ATMF Application software operating systems and drivers are described in separate manuals The Radstone host processor is also described in a separate manual Page 1 2 Issue 1 Introduction Radstone PMC ATMF Manual Documentation Structure This manual is structured in a way that will reflect the sequence of operations from receipt of the PMC ATMF up to getting it working with your host processor Each topic is covered in a separate chapter and each chapter begins with a brief introduction that tells you what the chapter contains In this way you can skip any chapters that are not applicable or with which you are already familiar The chapters are Chapter 1 this chapter gives a brief introduction this manual s objectives audience and scope the structure some warnings conventions and related documentation Chapter 2 is a s
18. CI bus support and 128 K bytes of on board buffer RAM The PMC ATMF supports 32 bit burst mode bus master scatter gather DMA and block transfers up to 12 words to achieve unprecedented performance levels AALO AAL 3 4 and AAL 5 are supported on hardware as are Raw Cell formats ATM cell processing conforms to ANSI T1S1 5 92 002R3 ITU 1 361 and the ATM Forum UNI 3 0 3 1 specifications Architecture Fiber The PMC ATMF is based on the NICStAR which has a 33 MHz PCI 2 1 compliant bus interface that supports bus master DMA ATM SAR functions are provided together with support for 128 Kbytes of buffer RAM PHY functions are contained in the PM5346 OC 3 connectivity is contained within the SC connectors for levels 1 and 2 and by custom designed optical circuits for levels 3 and 4 and Connectors The PMC ATMF is designed to operate with duplex 62 5 125y multimode fiber 2 000 metres maximum 10 GB loss Connection to the PMC ATMF in build levels 1 and 2 is by an industry standard SC optical connector Build levels 3 and 4 are delivered with 1 5 m pig tail connectors terminated with MIL T 29504 14 multimode long pin termini Field proven these are suitable for use with MIL C 28876 connectors for Naval applications and MIL C 38999 connectors for avionics shipboard or ground deployment Performance Capable of transmitting over 11 000 512 byte UDP packets per second when used with a Radstone PowerPC 603 CPU the PMC ATMF brings
19. MF PCI Interface The PMC ATMF s PCI interface is compliant with the PCI local bus specification The interface uses the DT 77201 77211 NICStAR chip set All data alignment in this manual refers to the PCI bus How data appears to the processor depends entirely on the configuration of the host card and whether it is big or little endian PCI Commands PMC ATMF responds to the following PCI bus commands e Memory Read e Memory Write e Configuration Read e Configuration Write e Memory Read Multiple aliased to Memory Read e Memory Read Line aliased to Memory Read e Memory Write and Invalidate aliased to Memory Write Page 6 1 Issue 1 Radstone PMC ATMF Manual Functional Description Configuration Space The following table shows the PCI Configuration Register space Shaded areas are not used and return 0 when accessed 31 16 15 0 0x40 Reserved OxF C Vendor ID Register This holds the value 0x111D indicating IDT Device ID Register This holds the value 0x0001 indicating a NICStAR Page 6 2 Issue 1 Functional Description Radstone PMC ATMF Manual Command Register This has the following layout sits mnemonic Ee CS IOEN 1 O access to NICStAR Enable The default is 0 0 NICStAR does not respond to PCI bus I O access 1 NICStAR does respond to PCI bus I O access 1 MEMEN Memory access to NICStAR Enable The default is 0 0 NICStAR does not respond to PCI bus memory access 1 NICStAR do
20. Most Significant Bit MTBF Mean Time Between F ailures NDI Non Developmental I tem NIC Network Interface Chip OAM Oc 3 Optical Carrier 3 PCB Printed Circuit Board PCI Peripheral Component Interconnect PDU Plug Distribution Unit PMC PCI Mezzanine Card PTI PROM Programmable ROM A program in a PROM is electronically hard wired and once the program is inserted into the PROM it cannot be altered without using a new PROM RAM Random Access Memory Memory that can be read from or written to at any time RH Relative Humidity Glossary iv Issue 1 Radstone PMC ATMF Manual ROM Read Only Memory Semiconductor memory whose components are not alterable by computer instructions RSQ Receive Status Queue RX Receive SAR Segment and Reconstruct SCD Standard Colour Display Slave A slave detects VME bus cycles initiated by a master and when these cycles specify its participation transfers data between itself and the master Slot A position where a board can be inserted into a backplane If the system has both aJ 1 and al 2 backplane or a combination J LI 2 backplane each slot provides a pair of 96 pin connectors SRAM Static RAM Memory that needs no refresh cycle once the information has been stored Power does however need to be applied constantly to the memory to maintain its integrity TBD To Be Determined To Be Decided and Transmit Buffer Descriptor TSI T
21. PCB Big Endian Where a system stores bytes with most significant byte at higher address See Little Endian BIST Built In Self Test BIT Built In Test Byte An 8 bit data structure CBR Continuous Bit Rate CCPMC Conduction cooled PMC Chassis See enclosure CMC Common Mezzanine Card COTS Commercial Off The Shelf Glossary i Issue 1 Radstone PMC ATMF Manual CS Chip Select A signal used to enable a memory device or peripheral chip DMA Direct Memory Access A direct rapid link between a peripheral and main memory that avoids the use of the processor to transfer each item of data E2PROM or EEPROM Electrically Erasable PROM PROM whose contents can be erased electrically so allowing the device to be re used with new data EIA Electronic Industries Association A body set up to establish serial communication standards for data communications equipment Enclosure A rigid framework that provides mechanical support for boards inserted into the backplane ensuring that the connectors mate properly and that adjacent boards do not touch each other It also guides the cooling airflow through the system and ensures that inserted boards do not disengage themselves from the backplane due to vibration or shock ESD Electrostatic Sensitive Device ESS Environmental Stress Screening Ethernet Ethernet or IEEE 802 3 is a network based on an access method called CMSA CD A baseband CSMA CD
22. Radstone PMC ATMEFE Manual Issue 1 Publication No PMC ATMF OHH Radstone Technology PLC 1997 All rights reserved This publication is issued to provide outline information only which unless agreed by the Company in writing may not be used applied or reproduced for any purpose or form part of any order or contract or be regarded as a representation relating to products or services concerned The Company reserves the right to alter without notice the specification design price or conditions of supply of any product or service November 1997 Front i Issue 1 Trademarks Radstone and the Radstone symbol are trademarks of Radstone Technology PLC All other company and product names are acknowledged as being the trademarks or registered trademarks of their respective companies Document History Important For future reference please record your PMC ATMF s serial MIC and IP numbers Front ii Issue 1 Contents Chapter 1 Introduction Documentation Objectives 0 ee eee ceeeeeeeeeeeteeeneeeeees Documentation Audlence Documentation SCO evi sss cdisassetss tie sccteriendSeieectaes dass Documentation Structure ccccccccccssssseseessesesesssseeneeeess Eegeregie Documentation Cotwventlons Ee e DIE World Wide Web Gite ccccccseessseeeseeseesssssseneueneess Chapter 2 General Description ENEE SUD DON sie ca see vee Aere dee edel ie Mechanical EE Level 1 Standard S style
23. StAR has transferred a complete Raw Cell to the Raw Cell Queue in the host memory The device driver clears this bit by writing a 1 toit Small Buffer Queue Empty The default is 0 0 Small Buffer Queue is not empty 1 Small Buffer Queue is empty When this bit is set if the Empty Free Buffer Queue Interrupt Enable bit in the Configuration register is set an interrupt is generated to the host 2 LBFQE Large Buffer Queue E mpty The default is 0 0 Large Buffer Queue is not empty 1 Large Buffer Queue is empty When this bit is set if the Empty Free Buffer Queue Interrupt Enable bit in the Configuration register is set an interrupt is generated to the host 1 RSQAF Receive Status Queue Almost Full The default is 0 0 Receive Status Queue is not 7 8 full 1 Receive Status Queue is 7 8 full When this bit is set if the Receive Queue Almost Full Interrupt Enable bit in the Configuration register is set an interrupt is generated to the host Reserved Reads as zero Page 6 21 Issue 1 Radstone PMC ATMF Manual Functional Description Receive Status Queue Base Register RSOB This register sets the start address for the RSQ ee Leet SSC inten Sd 31 to 13 Receive Status Queue Base Address or This field specifies the start address for the RSQ in the host memory This 31 to12 field is loaded with a default value after reset Device drivers can load a different value during device initialisation after reset but
24. a registers to exchange parameters with the NICStAR hardware This includes writing and reading the local SRAM through the NICStAR An SRAM read operation can only be carried out on one longword at a time while a write operation can be carried out on up to 4 longwords at a time When passing parameters to the NICStAR the host first loads the Data registers then issues a command to the Command register When reading parameters from the NI CStAR the host first issues a read command to the Command register then polls the Command Busy bit in the Status register When the Command Busy bit becomes clear 0 the host can read the data from the Data register Page 6 9 Issue 1 Radstone PMC ATMF Manual Functional Description Command Register CMD This register is used to issue commands to the NI CStAR It consists of an op code field and a parameter field Some commands require additional parameters in one or more of the Data registers Before any command is issued the device driver must ensure that the Command Busy bit in the Status register is clear This ensures that there is no previous command pending ae Mnemonic Jee i ro fofolo o noom ofo RSR mn Reever Tn roto fa of 2 operetee cman rofo a ifs renew SS ofa oo e wrresram of o s resan ofa a o e wiere opi a 7 Reeve afo oloje keau apopo e me e ah pepe re ce _ _ 27 toO Parameter Used with the command opcode to form a complete com
25. a to the Utility bus which interfaces to the PHY TC component The device driver should load the Data Register 0 bits 7 to 0 with the data to be written and then issue this command which causes the data to be transferred to the Utility bus Parameter Reserved UTCS1 UTCSO UTLADD Where sie nemne CS eription O O 27 to 10 Reserved Always set to zero UTCS1 UTL_CS1 signal 0 Utility bus UTL_CS1 is not selected 1 Utility bus UTL_CS1 is selected and remains active for the duration of the write operation UTCSO UTL_CSO signal 0 Utility bus UTL_CSO is not selected 1 Utility bus UTL_CSO is selected and remains active for the duration of the write operation 7to0 UTLADD Utility Bus Address Specifies the byte address for the information on the Utility bus Page 6 15 Issue 1 Radstone PMC ATMF Manual Functional Description Configuration Register The Configuration Register consists of many fields that control different aspects of the NICStAR operation ae meest Ee 31 SWRST Software reset The default is 0 0 No rese 1 Reset NICStAR All internal registers except PCI Configuration Registers are reloaded with the default values When set this function is equivalent to the PCI bus hardware reset To effect a reset the device driver must wait at least 2 PCI clocks before clearing this bit The chip must be re initialised after software reset before returning to its normal operation Reserved Always set
26. allation Inspection Assuming that the PMC ATMF is not obviously damaged you can now go on to inspect it It is possible for components connectors links socketed chips etc to work loose or be dislodged in transit or in the process of unpacking although this is extremely unlikely A quick visual inspection should reveal any obviously loose components Report any defects you detect to Radstone There are no user selectable links or socketed components on the PMC ATMF The following diagram shows the approximate component layouts of both air and conduction cooled versions of the PMC ATMF O L D D 3 B BE d c2 Ro B c3 R2 EC D I Saal Ein WW H H H BABE an goad SE E C22 c20 C18 C18 C14 013812 R4 R12 D BG r20 R21 C24 C31 C30 C29 C28 R24 Hes u3 3 Ke Kar R320 D ORe MADE IN UK Page 3 2 Issue 1 Connectors Radstone PMC ATMF Manual Chapter 4 Connectors The PMC ATMF connects directly to the host through two connectors designated P11 and P12 These connectors contain signals for the 32 bit PCI bus Figure 4 1 Connector Positions C21 C19 C17 alg H HR Ha R16 o D R0 Ep a H H E SE Le C22 C
27. ctive 1 PHY device interrupt signal active This bit is cleared by first clearing the PHY interrupt and then by writing a 1tothis bit CMDBZ NICStAR Command Busy flag The default is 0 0 NICStAR Data register is ready to be read written 1 NICStAR Data register is not ready to be read written Each time the host issues a command to the NICStAR the host must poll this flag until it is cleared before another command can be issued Page 6 20 Issue 1 Functional Description Radstone PMC ATMF Manual ee Leet SSCs Sd Small Buffer Queue F ull The default is 0 0 Small Buffer Queue is not full at least 2 sets of buffers 1 Small Buffer Queue is full This bit is deared by the NICStAR Large Buffer Queue Full The default is 0 0 Large Buffer Queue is not full at least 2 sets of buffers 1 Large Buffer Queue is full This bit is deared by the NICStAR Receive Status Queue Full The default is 0 0 RSQ is not full 1 RSQ is full This bit is deared by the NICStAR End of PDU flag The default is 0 0 A complete PDU has not been transferred to the host buffer by the NICStAR for either AALO AAL 3 4 or AAL 5 1 A complete PDU has been transferred to the host buffer by the NICStAR for either AALO AAL 3 4 or AAL5 The device driver dears this bit by writing a 1 toit Raw Cell Flag The default is 0 0 The NICStAR has not transferred a complete Raw Cell to the Raw Cell Queue in the host memory 1 The NIC
28. cy Timer This bit field is used to control the size of the Master Latency Timer The NICStAR s MLT is used in multiples of 32 PCI clocks The MLT starts counting down by one PCI clock when the NI CStAR is bus master and asserts FRAME signal If the GNT signal is de asserted the NI CStAR continues bus transactions In this way the PCI bus minimum latency is guaranteed Bits 15 to 13 are read write accessible The power up or reset value is 0x0 The default value of 0x03 is loaded after power up or reset Bits 12 to 8 are hard wired to 0x00 and are read only Page 6 5 Issue 1 Radstone PMC ATMF Manual Functional Description UO Base Address Register This register has the following layout ae meest Ee 31to2 NICStAR I O Thehost reads this field to get the I O base address Base Address The default value of Ox00000000 is loaded at PCI bus or software reset Po eserves Resa Memory Base Address Register This register has the following layout ae meest Ee NICStAR The host writes to this register to set the NICStAR memory base address Memory Base and reads this field for the memory base address Address The default value of 0x00000000 is loaded at PCI bus reset or software reset Expansion ROM Base Address Register This register has the following layout ae mnemo Ee 31to17 Expansion The host writes to this register to set the NICStAR expansion ROM base ROM address and reads this field for the ex
29. d components As software compatibility throughout the build styles is absolute a system intended for final implementation in a severe tactical environment can be developed and debugged at low cost switching over to the target style only in the final stages of system integration Level 2 Extended Temperature X style As S style but conformally coated and 100 tested in manufacture to provide an extended operating range Page 2 4 Issue 1 General Description Radstone PMC ATMF Manual Level 3 Rugged Air cooled RA style RA style boards are intended for applications that have extended temperature shock and vibration requirements but can be served by conventional forced air cooled racking systems These rugged boards comprise IEEE P1386 size assembly fitted with wide temperature range industrial grade components and are conformally coated as standard Level 4 Rugged Conduction cooled RC style Designed primarily for use in sealed ATR chassis and other conduction cool ed environments the RC style board features wide temperature range industrial grade devices an integral thermal management layer and incorporates a central stiffening bar for additional strength Cooling is achieved through conduction of heat from the thermal management layer to the cold wall of the rack to which the boards are secured by screw driven wedgelocks RC style boards are 100 temperature characterised and conformally coated during manufacture RC style is m
30. d by the device driver Raw Cell Tail Register RAWCT ae meest Ee 31 to6 RAWCTA Raw Cell Tail Address The default is 0x0000 This register contains the value written by the NICStAR as the current tail pointer for the Raw Cell Queuein host memory i e the tail pointer specifies the next available memory location in the queue The device driver reads this register for the tail value and compares it with its value of the Raw Cell Head to determine if there are unserviced entries in the Raw Cell Queue If the values are equal no unserviced entries exist in the Raw Cell Queue At initialisation this register is loaded by the NICStAR with the DMA address of the first Free Buffer descriptor in the local SRAM s Large Free Buffer Queue Timer Register TMR sits mnemonic LEE O 31 to 24 Always set to zero 23 to0 TMRCNT Timer Count The NICStAR increments this register by one every 333 SAR clocks 13 3us when using a 50 MHz clock When the value reaches the terminal count of OxFFFFFF it rolls over to Ox000000 at which point the NICStAR writes a Timer Roll Over descriptor into the Transmit Status Queue The timer rolls over approximately once every 3 72 minutes when using a 50 MHz dock When this register rolls over the NICStAR generates an interrupt to the host if the Timer Roll Over Interrupt Enable is set bit 7 in the Configuration register Page 6 27 Issue 1 Radstone PMC ATMF Manual Functional Description
31. describes the board in more detail The PMC ATMF provides a 32 bit PCI interface and fibre optic connections are made using an SC connection on the front panel on build levels 1 and 2 and as a pig tailed assembly on build levels 3 and 4 Features e Complete 155 Mbps ATM network interface card e Multimode fiber optical interface e Supports up to 16 384 receive connections e Supports more than 20 000 transmit connections e Serial EEPROM for system information storage e Optional Flash device for BIT BIST code storage e Build options Level 1 S Level 2 X Level 3 RA and Level 4 RC e VxWorks driver from End to End Systems e SC connectors on build levels 1 to 3 e MIL T 29504 14 terminated fiber pig tails on build level 4 e 32 bit 33 MHz PCI 2 1 interface e 32 bit scatter gather DMA support e Highly integrated design e Singleslot PMC IEEE P1386 form factor e ForeThought 4 ATM internetworking software for Tornado e UNI 3 0 3 1SVCs Page 2 1 Issue 1 General Description Radstone PMC ATMF Manual Figure 2 1 PMC ATMF Block Diagram A fy N Optical SUNI ite J NICSTAR 1 Interface PHY 1 SAR 5v 32 Bit PCI Bus oi N Y Page 2 2 Issue 1 General Description Radstone PMC ATMF Manual Functional Overview The highly integrated design of the PMC ATMF comprises a 32 bit 33 MHz PCI 2 1 compliant NIC with on board SAR and P
32. ean aeaa EEE eens 4 1 Current Consumption 0 0 0 eee eeeeeeeeeeeeeeeeeee A 2 RESISTET S n elk a ara AERE S en 6 2 D Bus Grant And Interrupt eee 6 7 Cell Terro edd 6 25 IR EE ER A 4 Commands eene 6 3 6 10 Documentation Audience ceeeeeeeceeeeereeeerees 1 2 Confeurapon eee eeeeceeeeeeeeeeceeeeeeeees 6 16 Documentation Conventions sseseseeseseseeeee 1 5 Data 0 E WE 6 9 Documentation Objectives 0 0 0 ce eeeeeeeeeeeees 1 2 Device WD E 6 2 Documentation Scope 0 cc eseesesseeeeceeecseeeseenes 1 2 Expansion ROM Base Address 6 6 Documentation Structure 1 3 General Durpose cece eeeeeeeeeeeeeeesees 6 30 E VO Base Address 6 6 Invalid Cell Count eeeeesceeeseeceereeeneeees 6 27 EEPROM 60 30 ca Dee e a a ls 6 33 Memory Base Address 6 6 F PCI Configuration 1 EI 6 5 Raw Cell Eat cise 3 ses stets soeisceabtacoes ees 6 27 l eTa EI RSA E heh Ee eg 2 1 Receive Status Queue Base 6 22 Flas Bon EE 6 33 Receive Status Queue Head 6 24 Functional Overview ccccesseceessceeseseeeseeeeees 2 3 Receive Status Queue Ta 6 23 KE EE 6 4 6 20 S BI EE 6 27 General Description 0 0 cece ceeeeeeseeereeeeeeees 2 1 Transmit Schedule Table Base 6 28 Transmit Status Queue Base osnnsoeeeeseeeee 6 28 Transmit Status Queue Head 6 29 INSPECtlON 20 3 2 Transmit Status Queue Tail 0 6 28 Installation ss eege dek SES Een DEER ANE 5 1 Nendor eelere 6 2 Introductton 1 1 VPI VCI Lookup Error Count
33. echanically compliant with the proposed CCPMC standard Page 2 5 Issue 1 Configuration and Installation Radstone PMC ATMF Manual Chapter 3 Unpacking and Inspection This chapter gives guidelines on unpacking and inspecting the PMC ATMF Unpacking Radstone boards are protected by an antistatic envelope Observe antistatic precautions and work at an approved antistatic work station when unpacking the board The PMC ATMF is shipped in an individual reusable shipping box When you receive the shipping container inspect it for any evidence of physical damage If the container is damaged request that the carrier s agent is present when the carton is opened Keep the contents and packing materials for the agent s inspection and notify Radstone s customer service department of the incident Retain the packing list for reference Assuming that there is no obvious damage you may still want to keep the shipping carton in case you want to ship the PMC ATMF on elsewhere CAUTION THIS PRODUCT IS CLASS 1 ELECTROSTATIC DISCHARGE SENSITIVE USE ESD PRECAUTIONARY MEASURES WHEN HANDLING IT Board Identification The PMC ATMF has labels attached to the solder side of the PCB i e the side of the PCB visible when the PMC ATMF is fitted to the host These labels give the revision state e g Rev A and the module s serial number These are also given in bar code form Page 3 1 Issue 1 Radstone PMC ATMF Manual Configuration and Inst
34. enerate an interrupt when the Timer register rolls over 6 Reserved Reserved Always set to zero 5 TXEN Transmit operation E nable The default is 0 0 Transmit section is disabled However the state of the transmit section iS preserved 1 Transmit section is enabled This is the normal operation If the NICStAR is enabled again from being disabled the transmit section resumes operation from where it was last disabled TXINT Transmit status nterrupt Enable The default is 0 0 Nointerrupt is generated after the NICStAR writes a Transmit Status Indicator into the TSQ 1 Generate an interrupt after the NICStAR writes a Transmit Status Indicator into the TSQ only if the interrupt bit in the TSR is also set Page 6 18 Issue 1 Functional Description Radstone PMC ATMF Manual er Leet Ee E TXUIE Transmit Under run Interrupt Enable The default is 0 0 Nointerrupt when the NICStAR starts aCS_PDU and runs out of transmit buffers before End_of_PDU occurs 1 Generate an interrupt when the NICStAR starts a CS_PDU and runs out of transmit buffers before End_of_PDU occurs 2 UMODE UTOPIA Mode select The default is 0 0 UTOPIA interface is in cell mode 1 UTOPIA interface is in byte mode 1 TXFSI Transmit status Full Interrupt Enable The default is 0 0 Nointerrupt when the TSQ is 7 8 full 1 Generate an interrupt when the TSQ is 7 8 full PHYIE PHY Interrupt Enable The default is 0 0 PHY_INT signal does not inter
35. es respond to PCI bus memory access 2 MSTEN NICStAR Master Enable The default is 0 0 NICStAR cannot generate master cycles 1 NICStAR can generate master cycles PARDE Parity error Detect Enable The default is 0 0 Ignore any parity error and continue normal operation the parity error signal is still generated 1 Take action when a parity error is detected SERRE SERR pin Enable The default is 0 0 SERR pin driver is disabled 1 SERR pin driver is enabled FSCYS Fast back to back host Cycle The default is 0 0 Fast back to back transfers are allowed to the same agent when the NICStAR is a bus master 1 Fast back to back transfers are allowed to different agents when the NICStAR is a bus master Page 6 3 Issue 1 Radstone PMC ATMF Manual Functional Description Status Register This has the following layout ae meest Ee 23 FSACC Fast back to back Access Always reads as 1 This read only bit indicates to the host that the NICStAR as a target can accept fast back to back bus transactions when they are not to the NICStAR 24 PARED Parity Error Detected The default is 0 0 Noparity error detected 1 Both of the following conditions have occurred a NICStAR is bus master and PERR is asserted by the NICStAR or the target b The parity error response bit bit 6 of the Control Register is set 25 and 26 IOSPD 1 O access decode Speed These bits specify how fast the NICStAR can assert a DEVSEL signal ina target
36. escription of the size of memory areas when K M and G mean 210 220 and 230 respectively When describing transfer rates k M and G mean 103 10 and 109 not 210 220 and 230 Bits are numbered from 0 ton where 0 is the LSB and n is the MSB Signal names follow the IEEE P1386 1 Signal names ending with a tilde denote active low signals all other signals are active high PCI PMC is a little endian environment i e data is stored with the least significant byte at the lowest address Page 1 5 Issue 1 Radstone PMC ATMF Manual Introduction Related Documents e EEE P1386 1 Draft Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC Draft 2 0 4 Apr 95 e EEE P1386 Draft Standard for a Common Mezzanine Card Family CMC Draft 2 0 4 Apr 95 e Draft Standard for Conduction cooled PMC Modules e PCI Local Bus Specification Revision 2 1 1 J un 95 e DT77211 NICStAR User Manual Version 1 0 26 F eb 97 e Radstone PPC1 60x Manual publication number RT 26358 e Radstone PPC1A 60x Manual publication number PPC1A OHH e Radstone PPC2 60x Manual publication number RT5070 World Wide Web Sites Radstone on the world wide web is available at http Awww radstone co uk or http www radstone com Page 1 6 Issue 1 General Description Radstone PMC ATMF Manual Chapter 2 General Description This chapter contains a general description of the PMC ATMF Chapter 6
37. estricted cooling supplies Conformally coated as standard Optional Environmental Stress Screening Provided that the build style of the PMC ATMF and host are the same for Radstone hosts or the environmental specifications of the PMC ATMF and host are more or less equivalent for non Radstone hosts the PMC ATMF will operate and may be stored or transported without damage within the same limitations as the host The Rugged Air Cooled vibration specification is only valid in systems using backplane 1 0 Appendix A 3 Issue 1 Radstone PMC ATMF Manual Specifications Mechanical Specifications Weight The approximate weights of the different styles of the PMC ATMF are Dimensions Each build standard of the PMC ATMF card complies with the PMC Specification This allows all styles of assembly to be fitted to any PMC compatible host Dimensions are shown in millimetres with inches in parentheses for general guidance only 149 mm 5 96 4 gt 74mm 2 96 gay LI P Air cooled PMC ATMF 143 75 mm 5 75 e gt e e O ii 74mm 2 96 kd C d Conduction cooled PMC ATMF Appendix A 4 Issue 1 Specifications Radstone PMC ATMF Manual Reliability Using MIL HBK 217F Notice 1 as a data base and the parts count method the following estimates have been made of the MTBF for the PMC ATMF Ground Ground Ground Naval Airborne Benign Fixed Mobile S
38. heltered Inhabited Cargo topes S X style Compatible Failure Rate Failures millions hrs MTBF Hrs 167 645 42 42 924 RC Compati m Failure Rate TBD TBD TBD TBD TBD Failures millions hrs Ordering Information ATMF TOROOI1UF ForeThought Tornado device driver V1 0 Right To Use License for Radstone PowerPC Includes one Run Time License with object on TAR compressed floppy ATMF TOROO2UF Forel hought Tornado device driver V1 0 Right To Use License for Motorola PowerPC Includes one Run Time License with object on TAR compressed floppy ATMF TOROOIRF ForeThought Tornado device Driver V1 0 Run Time License for Radstone PowerPC Object supplied as TAR archive on floppy ATMF TOROO2RF ForeThought Tornado device Driver V1 0 Run Time License for Motorola PowerPC Object supplied as TAR archive on floppy Appendix A 5 Issue 1 Radstone PMC ATMF Manual Glossary ANSI American National Standards I nstitute ATM Asynchronous Transfer Mode Backplane VMEbus A PCB with 96 pin connectors and signal paths that bus the connected pins Some systems have a single PCB called the 1 backplane This provides the signal paths needed for basic operation Other systems also have a second PCB called the 2 backplane This provides the additional 96 pin connectors and signal paths needed for wider data and address transfers The 1 and J 2 sections may be combined into a single J 14 2 backplane
39. lightly more detailed but still general product description Chapter 3 contains unpacking and inspection instructions Chapter 4 describes the PMC ATMF s connectors and signals used Chapter 5 describes fitting the module to a host Chapter 6 is a functional description Chapter 7 gives troubleshooting guidelines Appendix A is a board specification There are also a glossary and an index provided Page 1 3 Issue 1 Radstone PMC ATMF Manual Introduction Warnings Do not exceed the maximum rated input voltages or apply reversed bias to the assembly f such conditions occur toxic fumes may be produced due to the destruction of components CAUTION THIS PRODUCT IS CLASS 1 ELECTROSTATIC DISCHARGE SENSITIVE USE ESD PRECAUTIONARY MEASURES WHEN HANDLING IT Page 1 4 Issue 1 Introduction Radstone PMC ATMF Manual Documentation Conventions All numbers are expressed in decimal except addresses and memory or register data which are expressed in hexadecimal Where confusion may occur decimal numbers have a D subscript and binary numbers have a B subscript The prefix Ox shows a hexadecimal number following the C programming language convention Information of particular importance is highlighted by Note The multipliers k M and G have their conventional scientific and engineering meanings of 103 10 and 109 respectively The only exception to this is in the d
40. lt is 0 0 The GFC field in the receiving cells is checked according to the CAPT bit 21 setting 1 The GFC field in the receiving cells is ignored 19 and 18 VPVCS VPINVCI Select The default is 00 This field is used with the Receive Connection Table Size bits 17 and 16 to select the VPI and VCI bit range to index the Receive Connection Table vPvcs Table Size VPI bits VCI bits 4K The VPI field in the receiving cell header is 8 bit 7 0 and the VCI field is 16 bit 15 0 The remaining portion of the VPI and VCI is checked against the VPI VCI Mask Register to make a complete VPI VCI comparison on the receiving cells 17 and 16 RXCNS Receive Connection Table Size The default is 00 00 4096 4 K entries 01 8192 8 K entries 10 16384 16 K entries 11 Reserved 15 VPECA VPIMVCI Error Cell Accept The default is 0 0 Discards cells where either VPI VCI do not map into the entries in the Receive Connection Table or VPI VCI do not have open connection 1 Accepts cells into the Raw Cell Queue where VPI VCI do not map into the entries in the Receive Connection Table or VPI VCI do not have open connection Page 6 17 Issue 1 Radstone PMC ATMF Manual Functional Description ee Leet Ee 14 to 12 RXINT End of Receive PDU interrupt handling The default is 000 This field specifies how an interrupt is generated to the host at the end of receiving a CS_PDU for AALO AAL3 4 and AAL5 000 No interr
41. mand to the NICStAR Certain commands require additional parameters using the Data registers Page 6 10 Issue 1 Functional Description Radstone PMC ATMF Manual The following is a list of all the NICStAR commands and the required parameters No_operation Opcode 0x0 Parameter Reserved Always set to zero Open close_connection Opcode 0x2 This command is used to open or close a VC in the Receive Connection Table Parameter Where sits mnemonic Igel 27 to 20 Always set to zero 19 OPEN 0 Close a VC in the Receive Connection Table 1 Open a VC in the Receive Connection Table 18 to 2 SRAD SRAM Address Specifies the SRAM address of the VC entry in the Receive Connection Table in the range 0x00000 to Ox1F FFF 128K longwords total Since each VC entry is four longwords each VC number must be an increment of four e g VCO is location 0x00000 VC3 is location Ox0000C etc Page 6 11 Issue 1 Radstone PMC ATMF Manual Functional Description Write_SRAM Opcode Parameter 0x4 The device driver uses this command to write one to four longwords into the local SRAM Where sits Mnemonic CS serintion O 27 to 19 Reserved Always set to zero landO BSI ZE Read_SRAM Opcode Parameter SRAM Address Specifies the first address of a burst operation If the burst size is more than one word the NICStAR auto increments the SRAM address up to the burst size The range is 0x00000
42. n DR2 Buffer Handle of Free Buffer n 1 DR3 DMA Address of Free Buffer n 1 Two Free Buffers must be written at a time Parameter Where sits nemoe SC serintion O O 27to1 Reserved Always set to zero LBUF Large Buffer Indicator 0 Small Free Buffer Queue 1 Large Free Buffer Queue Page 6 13 Issue 1 Radstone PMC ATMF Manual Functional Description Read_Utility Opcode 0x8 This command allows the device driver to read one byte of data from the Utility bus which interfaces to the PHY TC component The device driver should issue the command and then poll the Command Busy bit bit 6 in the Status register until it equals 0 at which time the driver may access the desired information in Data Register 0 bits 7 to 0 Parameter Reserved UTCS1 UTCSO UTLADD Where sits nemon SC serintion O 27 to 10 Reserved Always set to zero UTCS1 UTL_CS1 signal 0 Utility bus UTL_CS1 is not selected 1 Utility bus UTL_CS1 is selected and remains active for the duration of the read operation UTCSO UTL_CSO signal 0 Utility bus UTL_CSO is not selected 1 Utility bus UTL_CSO is selected and remains active for the duration of the read operation 7to0 UTLADD Utility Bus Address Specifies the byte address for the information on the Utility bus Page 6 14 Issue 1 Functional Description Radstone PMC ATMF Manual Write_Utility Opcode 0x9 This command allows the device driver to write one byte of dat
43. ne PMC ATMF Manual VPI VCI Mask Register VPM sits Mnemonic LEE O 31to 12 Always set to zero 11to0 VPCMK VPI VCI MSB Mask The device driver writes the MSB portions of both the VPI and VCI fields for all VCs into this register These portions become a mask which is compared with the corresponding MSB portions of a received cell s VPI and VCI fields The Receive Connection Table contains the LSB portions of both the VPI and VCI fields for all open VCs This register should normally be cleared as OAM cells are received along with the VPI VVCI value Setting a non zero value in this field may not receive OAM cells defined by the ATM Forum Page 6 31 Issue 1 Radstone PMC ATMF Manual Functional Description Local SRAM Memory Map PMC ATMF is fitted with either 32K or 128K longwords of memory 128 K bytes or 512 Kbytes respectively To simplify memory accesses the functional components are accessed at the addresses used by the larger SRAM variant The following table shows the memory map Functional 32K longword SRAM 128K longword SRAM Entry Size Component location and size location and size bytes Rx Large Free 1F C00 to 1F FFF 1F C00 to 1FFF Buffer Queue 4 Kbytes 4 Kbytes Rx Small Free 1F 800 to 1F BFF 1F 800 to 1F BFF Buffer Queue 4 Kbytes 4 Kbytes Rx Cell FIFO 1E 800 to 1F 7F F 1E 800 to 1F 7FF 25 Cell Buffers 16 K bytes 16 K bytes VBR 1E7F 4 to 1E 7FF 1E7F 4 to 1E 7FF SCDO 48 bytes 48 bytes VBR 1E
44. new levels of performance to embedded ATM solutions With larger messages the full ATM line rate is virtually sustained 149 Mbits per second These performance levels represent a fivefold performance increase over existing embedded ATM products Software Support ForeThought 4 ATM Internetworking Software is available for the PMC ATMF Developed by industry leader FORE Systems F oreThought 4 is a layered software solution that provides high performance scaleable networking services for applications in both LAN and WAN environments Radstone Technology as a FORE development partner has ported F oreThought 4 to VxWorks 5 3 Tornado bringing unparalleled levels of networking application development and support to real time embedded systems Forelhought 4 from FORE is today s leading ATM internetworking software Licensed by over 140 of FORE s vendors and partners it has become the industry de facto standard and wide deployment of F oreThought 4 solutions mean that the developer is assured that their system will integrate seamlessly onto the network F oreThought 4 presents a layered architecture to the programmer that allows the development of networking services that take advantage of the benefits of ATM in LAN and WAN environments Page 2 3 Issue 1 General Description Radstone PMC ATMF Manual Mechanical Overview PMC cards use both single and double sided component mounting depending on the product Where the application require
45. ng the PMC ATMF to a Radstone host If you are fitting the PMC ATMF to another manufacturer s host board although the suggestions still apply in general there may be different or additional requirements for the PMC ATMF host combination See the appropriate manufacturer s host board documentation for more details To make doubly sure that it is not the host that is causing the problem if you have not already done so ensure that the host operates successfully in isolation i e without the PMC ATMF fitted Page 7 1 Issue 1 Radstone PMC ATMF Manual Troubleshooting Having satisfied yourself that the source of the problem is the PMC ATMF try the following suggestions e Ensure that there is no damage to the PMC ATMEF e g broken or missing components as mentioned in Chapter 2 e Ensure that the PMC ATMF is properly connected to the host with the connectors properly located and firmly fitted Ensure that the PMC ATMF is firmly attached to the host using the supplied screws into the stand offs e On conduction cooled hosts to avoid overheating ensure that the PMC ATMF is firmly attached to the central and front stiffening bars These suggestions only apply if you are fitting the PMC ATMF to a host board yourself If your PMC ATMF has been fitted by Radstone it will have been extensively factory tested to provide correct operation Please contact Radstone if this is not the case Page 7 2 Issue 1 Specifications Radstone PMC
46. owever in the unlikely event that you do experience problems for assistance please contact Radstone s Technical Help Line on 44 0 1327 359804 When you phone for technical support please be prepared to provide e Your contact details name work address work telephone and fax numbers and e mail address if appropriate e A detailed description of the problem e Any messages and error messages being generated e What has been tried so far e The software revision level hardware platform hardware revision and operating system level of all boards in the enclosure e If you are reporting a bug give detailed instructions on how to reproduce the problem and sample code if possible if the bug occurs in an application Your query will be allocated a unique Call Reference Number CRN for use in future correspondance If you are experiencing a problem with your product and are awaiting a response from Radstone s technical support there follow some rudimentary suggestions that you may also like to try to get your product operational If you are fitting the PMC ATMF to a Radstone host you should also follow any troubleshooting suggestions in the host s Manual e g Chapter 11 in the PPC1A Manual publication number PPC1A OHH By doing this you can eliminate the host as being the source of the problem and narrow the scope to the PMC ATMF itself or the PMC ATMF host connection The following suggestions mainly apply if you are fitti
47. pansion ROM base address Reading Base Address this field does not change its content The default value of 0x0000 is loaded at PCI bus reset ROM is not accessible when the NICStAR receive is enabled 16to 1 Reserved Reads as 0x0000 Writing to this field does not alter its content ADDEN Address Decode Enable The default is 0 0 The NICStAR does not allow expansion ROM access 1 TheNICStAR does allow expansion ROM access if the MEMEN bit is also set in the Control register Page 6 6 Issue 1 Functional Description Radstone PMC ATMF Manual Bus Grant and Interrupt Register This register has the following layout ae meeste 31 to 24 MAX_LAT This field specifies how often the NICStAR needs to gain burst access to the PCI bus assuming a 33 MHz PCI bus clock The period is measured in 0 25 usec units Reading and writing this field does not change its value The default value of 0x05 is loaded into this field at PCI bus reset The worst case is when 353 773 cells are transmitted and another 353 773 cells are received simultaneously This gives 1 353773 2 4 5 6 units 23 to 16 MIN_GNT This field specifies the desired minimum period of the NICStAR on the PCI bus assuming a 33 MHz PCI bus clock The period is measured in 0 25 usec units Reading and writing this field does not change its value The default value of 0x05 is loaded into this field at PCI bus reset The worst case is one Tx and one Rx cell transfer
48. ransmit Status Indicator TSQ Transmit Status Queue TSR Timer Status Register TST Transmit Schedule Table Glossary v Issue 1 Radstone PMC ATMF Manual TX Transmit UDP User Datagram Protocol vc Virtual Circuit VCI VITA VFEA VMEbus and Futurebus Extended Architecture International Trade Association VME Versa Module Europe Often used as an abbreviation for VME bus VPI WAN Wide Area Network Computers with long distances between them are connected by means of for example telephone lines See LAN Word In PowerPC terminology a 32 bit structure Also often refers to a 16 bit data structure in VME systems Cf halfword longword Glossary vi Issue 1 Radstone PMC ATMF Manual Index A O Antistatic Drecautons cece esecseeseeeeeneeeee 3 1 Operating Environment B See Specifications Environmental Ordering Information A 5 Block Diagram nnna ar 2 2 P Boars EE TOT steele 3 1 Build Styles cscecssteesescostnedeevschvssepssfevcvserstnedeeesstesty 1 1 Part Number See Board ID LN EE 6 1 C Commands Seiri e a T 6 1 Conti euration r a i e E E 5 1 Interface siniora e eea r Ea aer 2 1 Configuration Space esseeeeseeeeseesereererrerrereerereee 6 2 PMG resins besa AGE oa sees testo dee 2 4 Connectors ee te ANERE RS 4 1 Power UP eniten oere e iee teasee iaeei 1 4 PUL Pin OUts seniii i 4 2 Product Identification 0 eee See Board ID EIS Pin Out eere aee ia nee 4 2 R POSIUONS 2 06 coins
49. red back to back with a 33 MHz bus clock the burst time 30 12 16 4 4 56 units 15 to 8 Interrupt Pin This field shows that the NICStAR is using PCI bus pin INTA as its interrupt pin Reading and writing this field does not change its value The default value of 0x01 is loaded into this bit field at PCI bus reset Interrupt Line The default is 0x00 The host uses this field to initialise the nterrupt Line routing information i e the NICStAR s IRQ number The host reads from this field to determine the NI CStAR s interrupt level Reading this field does not change its value Page 6 7 Issue 1 Radstone PMC ATMF Manual NICStAR Network Operation Device Functional Description The PMC ATMF is based around the NICStAR chip set from IDT This provides all the segmentation and re assembly of packets to be sent and received The device accesses host memory directly to provide as little load on the system CPU as possible The device provides support for AALO AAL 3 4 AAL5 and Raw Cell packet types To enable this level of operation the NICStAR uses 128 or 512 Kbytes of local SRAM The NICStAR has the following set of registers for configuring and operating the network interface 0x00 0x04 31 0 Data Register 0 R W Where Read write Write Read Read clear Page 6 8 Issue 1 Functional Description Radstone PMC ATMF Manual Data Register 0 to Data Register 3 DRO to DR3 The host uses the Dat
50. rupt the host 1 PHY_INT signal interrupts the host Page 6 19 Issue 1 Radstone PMC ATMF Manual Functional Description Status Register STAT The Status Register returns the many indicators of the NICStAR operation ae meest Ee 31 to 24 SBFQC Small Buffer Queue Count These are the eight MSBs of the Small Buffer Queue maximum 512 The LSB is not read ape Actual value SBFQC x 2 lor 0 23 to 16 LBFQC Large Buffer Queue Count These are the eight MSBs of the Large Buffer Queue maximum 512 The LSB is not read wm Actual value LBFQC x 2 1 or 0 15 TSIF Transmit Status Indicator Flag The default is 0 0 NoTSI is written to the TSQ by the NICStAR 1 A TSI is written to the TSQ by the NICStAR ae This bit is deared by writing a 1 toit 14 TXICP Transmit Incomplete PDU The default is 0 0 Noincomplete CS PDU has been transmitted by the NICStAR 1 Incomplete CS PDU has been transmitted by the NICStAR If the SAR runs out of TBDs before an end of PDU counter this bit is set This bit is deared by writing a 1 toit 12 TSQF Transmit Status Queue Full The default is 0 0 TSQ is less than 7 8 full 1 TSQ is 7 8 full This bit is deared by the NICStAR 11 TMROF Time Overflow The default is 0 0 The Timer register has not overflowed 1 The Timer register has overflowed When set the host must write a 1 to this bit to clear it 10 PHYI PHY device Interrupt flag The default is 0 0 PHY device interrupt signal not a
51. s only a single side larger components e g PGA devices or DIL packages are used For more complex applications that require greater board space surface mount devices are used allowing components to be mounted on both sides of the board yet still keep within the specified profile The PMC ATMF is available in four electrically compatible build styles Each style is carefully tailored to a particular set of requirements and environments All four styles fully support the power and versatility of PMC sono matter how large or diversified your project absolute compatibility is assured at all stages of development The four build styles have two basic mechanical configurations convection cooled in accordance with IEEE P1386 and conduction cooled in accordance with the proposed CCPMC standard being prepared by VITA Convection cooled boards include Standard PMCATMF 100 Level 1 Extended Temperature PMCATMF 200 Level 2 Rugged Air Cooled PMCATMFR 300 Level 3 Conduction cooled boards include Rugged Conduction cooled PMCATMF 400 Level 4 A brief description of each build style follows See the Environmental Specifications section in Appendix A for more details Level 1 Standard S style Intended for use in benign environments the S style also provides the ideal cost effective method of complete system development The S style assembly comprises IEEE P1386 size assembly with high quality commercial grade plastic encapsulate
52. screws supplied in the fixing kit into the stand offs and the tapped holes in the central and front panel stiffening bars Metal to metal connections at the two stiffening points provide the heat transfer points for the conduction cooling You are recommended to secure the screws into the tapped holes with a fixative such as Loctite 242 Nutlock ThePMC ATMF fibers must be carefully attached at suitable points within the enclosure F ailure to do so may cause damage to the fiber and eventual failure of the module Build levels 3 and 4 are delivered with 1 5 m pig tail connectors terminated with MIL T 29504 14 multimode long pin termini Field proven these are suitable for use with MIL C 28876 connectors for Naval applications and MIL C 38999 connectors for avionics shipboard or ground deployment Page 5 2 Issue 1 Configuration and Installation Radstone PMC ATMF Manual Figure 5 1 PMIC ATMF Connection to Air cooled Host M2 5x6 Screws P a Four positions M2 5x10 Spacer Two positions Ce EE EE la po e MMMM WWM WIN cs Me A f S23 Page 5 3 Issue 1 Radstone PMC ATMF Manual Configuration and Installation Figure 5 2 PMIC ATMF Connection to Conduction cooled Host Drawing TBD Page 5 4 Issue 1 Functional Description Radstone PMC ATMF Manual Chapter 6 Functional Description This chapter gives a functional description of the PMC AT
53. to Ox1F FFF The actual SRAM address space depends on how much SRAM is installed See the SRAM Memory map for address allocations Burst Size Specifies the number of data words the NICStAR transfers from the Data register s to local SRAM 00 1 word write from Data Register 0 01 2 words write from Data Registers 0 and 1 10 3 words write from Data Registers 0 1 and 2 11 4 words write from Data Registers 0 1 2 and 3 0x5 The device driver uses this command to read one longword from the local SRAM Where sits nemon SC serintion O O 27 to 19 Reserved Always set to zero 7 SRAM Address Specifies the longword address of the local SRAM for this read operation in the range 0x00000 to Ox1F FFF The actual SRAM address space depends on how much SRAM is installed See the SRAM Memory map for address allocations Reserved Always set to zero Page 6 12 Issue 1 Functional Description Radstone PMC ATMF Manual Write_FreeBufQ Opcode 0x6 The device driver must use this command to add Small or Large Free Buffers to the Free Buffer queues in local SRAM The device driver should load the four Data Registers with either two small FBDs or two large F BDs each FBD includes a Buffer Handle and a DMA address and then issue this command which causes the NICStAR to transfer the contents of the Data Registers into the appropriate buffer queue DRO Buffer Handle of Free Buffer n DR1 DMA Address of Free Buffer
54. ts the PMC ATMF is available in a compatible range of increasingly more rugged build styles In this case Level 1 Standard suitable for a benign office like environment right through to Level 4 Rugged Conduction Cooled capable of withstanding the harshest of environments All products are COTS NDI and make maximum use of low cost plastic packaged integrated circuits to ensure the most cost effective solution whatever the market In its air cooled build levels the PMC ATMF conform with the IEEE P1386 1 PMC standard and in the conduction cooled build level it conforms with the latest Draft standard for Conduction Cooled PMCs Radstoneis a key member of the VITA standards committee setting the standards for rugged conduction cooled PMCs On build levels 1 and 2 fiber optic connections are made using an industry standard SC connector through the front panel On level 3 and 4 build standards the fiber optic cable is provided in a pig tailed assembly The PMC ATMF s form factor approximately 149 x 74 mm uses only one PMC slot on the host and can easily be plugged onto any host processor VME or otherwise that supports PMC and has appropriate drivers for example Radstone s PPC1 PPC1A or the rugged PPC2 Page 1 1 Issue 1 Radstone PMC ATMF Manual Introduction Documentation Objectives This manual provides the user with sufficient information to configure install and use the Radstone PMC ATMF expansion board Documentation
55. upt is generated 001 Generates an interrupt after Ous 010 Generates an interrupt after 314us 011 Generates an interrupt after 624us 100 Generates an interrupt after 899us 101 Reserved 110 Reserved 111 Reserved 11 RAWI E Raw cell queue Interrupt Enable The default is 0 This bit field is used as a global enable for generating interrupts to the host for the VCs In addition to this global enable bit each VC has a separate Raw Cell Interrupt Enable bit in the Receive Connection Table Raw Cell Interrupts are generated per VC This bit and the Raw Cell Interrupt Enable bit in the Receive Connection Table must both be set to generate an interrupt to the host 0 No interrupt is generated to the host when a raw cell is received 1 Generates an interrupt to the host when a raw cell is received into the Raw Cell Queue and the Raw Cell Interrupt Enable bit in the Receive Connection Table for the VC is set 10 RQFIE Receive Queue almost Full Interrupt Enable The default is 0 0 No interrupt is generated when the Receive Queue is 7 8 full 1 Generate an interrupt when the Receive Queue is 7 8 full RXRM Receive RM cells The default is 0 0 Discard cell when header PTI field 110 or 111 1 Put cells in Raw Cell Queue when cell header PTI field 11x 8 Reserved Reserved Always set to zero 7 TMOIE Timer roll Over Interrupt Enable The default is 0 0 No interrupt is generated when the Timer register rolls over 1 G
56. ways set to zero 31 to 12 or The actual number of reserved bits depends on the size of the RSQ See below for bit size of this field 31to11 Receive Queue Status Head Pointer Offset This field is written by the device driver to indicate the last entry in the RSQ that the device driver has serviced This register is cleared at initialisation This field is used together with RSQB field in the RSQT register to forma complete physical address i e on a longword boundary for the RSQ Head pointer to the host memory Bit usage is defined as follows ent Seen Juste OOOO O Page 6 24 Issue 1 Functional Description Radstone PMC ATMF Manual Cell Drop Count Register CDC This register holds the number of dropped cells sits mnemonic Ee O O 31to 16 Always set to zero 15 to 0 CDCNT Cell Drop Count The default is 0x0000 The NICStAR increments this register whenever the 315 cell Rx FIFO is full and is unable to accept a new received cell This register contains a non zero value when the PCI bus use of other PCI bus masters is excessively high so delaying the NI CStAR from transferring received cell payloads in the 315 cell Rx FIFO to host memory The value of this register is cleared each time after being read by the device driver Page 6 25 Issue 1 Radstone PMC ATMF Manual Functional Description VPI VCI Lookup Error Count Register VPEC sits Mnemonic Ee CS 31to 16 Always set to zero VPIACT Lookup Error
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