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CoCentric™ SystemC Compiler Behavioral Modeling Guide

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1. 3 2 Characteristics of the Clocked Thread Process 3 2 Using the wait Statement 3 3 Using the wait until Statement 3 3 Controlling a Clocked Thread Process 3 4 Simple Clocked Thread Example aaa 3 4 Using Inputs and Outputs ree RET SER TAE ES 3 6 Registered Outputs CEU APRES RESON Set tS 3 6 Inputs and Outputs Within Cycles 3 6 Specifying I O Read and Write 0c eee 3 7 Specifying P O Gycles ee ERES eae tma Su 3 7 O Schedulirg MOd6S zs xx dee KR 8 ew wewewe onwards 3 8 Cycle Fixed Scheduling Mode 3 8 Superstate Fixed Schedule Mode 3 8 Comparing I O Scheduling Modes 3 9 Behavioral Coding Style Rules a 3 10 Definition of Coding Rule Terms GG 3 10 General Coding RUules saba THA BABY SR oe UE PI da 3 11 Cycle Fixed Mode Coding Rules 3 12 Superstate Fixed Mode Coding Rules 3 12 General Coding Rules Examples aaa 3 13 General Coding Rule 1 3 13 General Coding Rule 2 3 14 General Coding Rule 3 3 15 General Coding Rule 4 3 16 General Coding Rule 5 a 3 20 Cycle Fixed Mode Coding Rules Examples 3 23 Cycle Fixed Coding Rule 1 aaa 3 23 Cycle Fixed Coding Rule 2 AA lll a 3 26 Cycle Fixed Coding Rule 3 4 0A AA
2. Kab a LAN Simple Clocked Thread Multiplier xvii Example 3 3 Example 3 4 Example 3 5 Example 3 6 Example 3 7 Example 3 8 Example 3 9 Example 3 10 Example 3 11 Example 3 12 Example 3 13 Example 3 14 Example 3 15 Example 3 16 Example 3 17 Example 3 18 Example 3 19 Example 3 20 xviii Error in Use of General Coding Rule 1 3 13 Correct General Coding Rule 1 3 13 Error in Use of General Coding Rule 2 3 14 Correct General Coding Rule 2 3 14 Error in Use of General Coding Rule3 3 15 Correct General Coding Rule 3 3 15 Error in Use of General Coding Rule 4 If Conditional 3 ase ea eec es 3 17 Correct General Coding Rule 4 If Conditional 3 17 Error in Use of General Coding Rule 4 If Conditional With Implied Else 3 18 Correct General Coding Rule 4 If Conditional 3 18 Error in Use of General Coding Rule 4 Switch Conditional APP 3 19 Correct General Coding Rule 4 Switch Conditional 3 19 Error in Use of General Coding Rule 5 3 21 Correct General Coding Rule 5 3 22 Error in Use of Cycle Fixed Mode Coding Rule 1 OL Ko o AA AA p eb 3 23 Correct Cycle Fixed Mode Coding Rule 1 for Loop 3 23 Error in Use of Cycle Fixed Mode Coding Rule 1 while LOOP nakaasa Tan NG hh LAG LAAN taie d biag 3 24 Correct Cycle Fixed Mode Coding Rule 1 wh
3. Sc in lt int gt data in sc in bool reset Sc out int data out sc out bool full sc out bool empty int buffer BUFSIZE sc uint LOGBUFSIZE headp sc uint lt LOGBUFSIZE gt tailp The clock Indicate read from FIFO Indicate write to FIFO Data written to FIFO Reset the FIFO Data read from the FIFO Indicate FIFO is full Indicate FIFO is empty FIFO buffer Pointer to FIFO head Pointer to FIFO tail Counter for number of elements Sc uint LOGBUFSIZEPLUSONE num in buf void read write FIFO process SC CTOR circ buf SC CTHREAD read write clk pos watching reset delayed true ROR KKK kok kok k Ck KK kok kok ke kk ke ke ke ke ke e x fifo bhv cc implementation file include systemc h include fifo bhv h void circ buf read write Reset operations headp 0 tailp 0 num_in_buf 0 full false empty true data_out 0 Introduction 1 12 wait Main loop while true if read_fifo read Check if FIFO is not empty if num_in_buf 0 num_in_buf data out buffer headp full false if num_in_buf 0 empty true Ignore read request otherwise wait else if write_fifo read Check if FIFO is not full if num_in_buf BUFSIZE buffer tailpt data in num_in_buf mpty fal
4. address 0 wait while true data tmp into read switch data tmp determine opcode case NOP wait do nothing break case RDBYT wait address into read get address wait wait one to mimic latency data tmp memory address get data out of memory outof write data tmp wait break case WIBYT wait address into read get address wait data tmp into read get data memory address data tmp write data wait break case WIBIK wait address into read get address wait for short 10 i 4 i data tmp into read get data Memory Controller Example C 12 memory addressti data tmp write data wait break default wait break end switch end while end entry Example C 7 Behavioral Synthesis to Gates Script top unit search_path synthetic_library le analysis info true bc enab target library link library mem_controller search_path ram dwOl sldb ram sldb tc6a cbacore db target library synthetic library compile systemc mem controller cpp write f db hier o top unit elab db create clock p 20 0 bc time design write f db hier o Schedule io super write f db hier o compile write f db hier o cik top unit time db top unit rtl db top unit gate d
5. FIFO read d fifo write false SS 0 lt lt 0 lt 0 lt lt 0 FIFO read te fifo write true cout FIFO write 1 FIFO write 2 FIFO write 3 e fifo write false read fifo write true read fifo write false FIFO read data in read cout wai cout wai writ cout wai cout lt lt 0 0 da da da da La Out La Out La Out La Out monitor write 1 monitor write 2 monitor write 3 monitor write 4 monitor monitor da da da ta in ta in ta in wait da ta in wait read monitor read monitor read monitor read monitor data out write 1 monitor data out write 2 monitor data out write 3 monitor monitor monitor FIFO read data in read e fifo write true lt lt 0 FIFO write 4 FIFO write 5 First In First Out Example B 12 wait 2 wait 4 monitor monitor data out write 4 monitor data out write 5 monitor wai cout wai wri rea wai cout wai cou wai cou rea cout mon wai SC void testb f cou cou cou c0 FIFO write 6 data out write 6 monitor c0 te fifo write false monitor wai
6. wait gcd_seen false wait KOR KR KR KK kok k KR RK KK RK KK gcd4_main simulation executable include systemc h include gcd4 h include gcd4 test h int main f sc signal lt int gt data gcd sc signal bool reset data seen data ready gcd ready gcd seen Using Handshaking in the Circuit and Testbench 6 33 se clock Elocki Clock 20 0 5 gcd mod G GCD G clock reset data data seen data ready gcd ready gcd seen gcd testbench TB TB TB clock data seen data ready gcd ready gcd seen gcd reset data sc trace file tf sc create vcd trace file gcd sc trace tf clock signal Clock Sc trace tf reset Reset Sc trace tf data seen Data Seen Sc trace tf data ready Data Ready Sc trace tf data In sc trace tf gcd ready Out Ready sc trace tf gcd seen Out Seen Sc trace tf gcd ready Out sc start 1 return 0 The following steps describe how the input handshaking protocol works 1 The testbench asserts the handshake signal data ready high to indicate that it has new data to process 2 The behavioral module waits until it sees the data ready signal Then it asserts high the data seen signal and reads the first piece of data in the same cycle 3 The testbench waits until it sees the data seen signal asserted high Then it sends the second piece of data and de asserts data rea
7. e Synopsys Behavioral Compiler e Synopsys Design Compiler e Synopsys Scirocco VHDL Simulator Synopsys Verilog Compiled Simulator VCS Related Publications In addition to the CoCentric SystemC Compiler Behavioral Modeling Guide see the following manuals The CoCentric SystemC Compiler Behavioral User Guide which provides information about synthesize a refined SystemC behavioral module into an RTL or a gate level netlist The CoCentric SystemC Compiler RTL User and Modeling Guide which provides information about how to synthesize a SystemC RTL module It also describes the coding guidelines and how to develop a SystemC RTL module for synthesis The SystemC HDL Cosimulation User Guide which provides information about cosimulating a system with mixed SystemC and HDL modules The CoCentric SystemC Compiler Quick Reference which provides a list of commands with their options and a list of variables The SystemC User s Manual available from the Open SystemC Community web site at http www systemc org For additional information about SystemC Compiler and other Synopsys products see Synopsys Online Documentation SOLD which is included with the software Documentation on the Web which is available through SolvNET on the Synopsys Web page at http www synopsys com The Synopsys Print Shop from which you can order printed copies of Synopsys documents at http docs synopsys com xxvii You can also re
8. a 1 5 Behavioral Model evan Seid nil 1 9 Behavioral Coding Style lt 1 10 Refining From Functional to Behavioral Model 1 10 Register Transfer Level Model lt 1 14 RTL Coding Style e MESI E ed 1 15 Refining Jo Obss scit PA tp ped t idt 1 15 Choosing the Right Abstraction for Synthesis 1 19 Identifying Attributes Suitable for Behavioral Synthesis 1 19 Identifying Attributes Suitable for RTL Synthesis 1 21 Comparison of Behavioral and RTL Synthesis 1 22 2 Refining for Behavioral Synthesis Refinement Overview es 2 3 Creating and Refining the Structure From a C C Model 2 6 Define V O PONS uvae urea d eR RES 2 6 Specify Internal Structure 0 00 cee eee eee 2 6 Specify the Internal Communication 2 7 Specify the Detailed Architecture 2 8 Atomic and Hierarchical Blocks G 2 9 NIOGUIGS NAPARAN ea ew ETE RS 2 12 Module Header File c eee eee ees 2 13 Mod le PoS ss nian dieu e ae Phe d AA de di ete ode doe 2 14 Internal Signals ett dec b d ein ce 2 16 Reading and Writing Ports aaa 2 17 Internal Data Variables llle 2 18 PrOCeSSeS eee te esp aire Aa yee ees so aUa P dE Ge aad dan dr 2 20 Types of Processes iioc isa dH xac sede ace eb los 2 21 Creating a Process in a Module 2 22 Member FUN
9. shows the top level RTL simulation file Example B 10 RTL Top Level Simulation File main rtl cc simulation run file include systemc h include fifo rtl h include fifo rtl test h int main f Sc signal lt bool gt reset write fifo read fifo full empty sc signal lt int gt data in data out sc clock clock Clock 20 0 0 5 testbench T Testbench T clock data out full empty read fifo write fifo data in reset circ buf FIFO FIFO FIFO clock read fifo write fifo data in reset data out full empty Sc trace file tf SC create vcd trace file bhv tf reset Reset tf write fifo WRITE tf read fifo READ tf full FULL tf empty EMPTY t t t Sc trace Sc trace Sc trace sc trace sc trace data in DATA IN f data out DATA OUT fF clock signal Clock 1 Sc trace Sc trace Sc trace return 0 First In First Out Example B 20 Memory Controller Example This appendix provides a simple memory controller example It contains the following sections Memory Controller Description e Functional Simulation Model Refined Behavioral Model Memory Controller Example C 1 Memory Controller Description The memory controller handles all internal memory accesses in a system and provides a simple command based interface that lets the testbench
10. The following sequential constructs are not allowed in preserved functions Sequential DesignWare parts such as memories and pipelined parts although the preserved function itself can be pipelined Wait statements Signal reads and writes Rolled loops Preserved functions no nesting of preserved functions Using Functions and DesignWare Components 4 5 Creating Preserved Functions To preserve a function annotate it with the preserve function compiler directive as shown in bold in Example 4 2 This example also shows the declaration definition and the call to the preserved member function in bold Note that the preserve function directive must be the first line in the function body A preserved function may be either a member function or a nonmember function If it is a member function define the function in the implementation file Using Functions and DesignWare Components 4 6 Example 4 2 Creating Preserved Functions cmult hs h header file SC MODULE cmult hs Declare ports Declare processes in the module void entry Declare member functions sc int lt 19 gt my prefunc sc int lt 8 gt aa sc int 8 bb sc int 8 cc Constructor l KKK k k k k k k k k k k k k Ck Ck Ck Ck ck ckckck cmult func cc implementation file include systemc h include cmult func h void cmult hs entry sc int lt 8 gt a b c dj sc int lt 19 gt e sc int lt 8
11. a O wait return a Using Handshaking in the Circuit and Testbench 6 24 KOK KR k KK kok kok k kok kok k kok KAKA ke ke ke ke e x kk gcd3 test h header file SC MODULE testbench l SC in clk GIk Sc in bool send data Sc out bool data ready sc in bool gcd ready sc out lt bool gt gcd seen Sc in lt int gt gcd Sc out lt bool gt reset Sc out lt int gt data Process void do run Internal function void do handshake int a int b SC CTOR testbench SC CTHREAD do run clk pos KOK KR KR KK kok k kok k kok k k kk KK sk ke ke ke xe kk gcd3_test cc testbench implementation file include systemc h include gcd3 test h void testbench do run reset false gcd_seen false data_ready false wait reset wait reset wait me true me false cout lt lt Reset Don Begin Testing n do handshake 12 6 do handshake 172 36 do handshake 36 172 do handshake 19 5 do handshake 2584 4712 Using Handshaking in the Circuit and Testbench 6 25 do handshake 15 0 cout lt lt Testing Done n sc_stop void testbench do_handshake int a int b cout lt lt GCD of lt lt a lt lt and lt lt b lt lt is Receiver initiated handshake Wait until receiver is ready wait until send data delayed true
12. 3 1 RTL 1 15 command bc check design 3 31 IN 2 compile preserve functions 4 8 compile systemc 3 14 5 9 ignore array precedences 5 15 read preserve function netlist 4 8 schedule 3 8 3 26 3 31 set behavioral reset 3 48 set cycles 6 19 set memory input delay 5 17 set memory output delay 5 17 compare design attributes 1 22 I O schedule modes 3 9 compile preserve functions command 4 8 compile systemc command 3 14 5 9 compiler directive 2 31 A 2 elif else endif A 9 if ifdef ifndef A 9 ifdef C language 2 31 C C A 9 inout_param 4 10 A 5 line_label 3 34 A 3 map_to_operator 4 11 A 3 preserve_function 4 6 A 4 resource 5 9 A 6 return_port_name 4 11 A 4 synthesis_off 2 31 A 7 synthesis on 2 31 A 7 translate_off A 7 translate_on A 7 unroll 3 37 A 8 components DesignWare 4 11 conditional statements 3 32 constrain cycles handshake 6 19 constructor 2 24 control refinement 2 3 2 47 cycle fixed coding rules 3 12 schedule 3 8 D data aggregate type 2 43 C C types 2 43 enumerated type 2 43 lifetime of value 3 54 nonsynthesizable types 2 38 recommended types 2 46 resource sharing 3 53 Sc bigint 2 42 sc biguint 2 42 sc bit 2 41 sc bv 2 41 sc int 2 42 sc uint 2 42 synthesizable types 2 37 2 39 SystemC bit types 2 41 integer types 2 42 variable 2 18 data refinement 2 3 2 30 2 37 C C 2 32 SystemC 2 32 define process 2 20 design behavioral attributes 1 19 compare attributes 1 22 RTL attri
13. Operators specify the computation to perform In the following code fragment A and B are operands is an operator and A Bis an expression Expressions are often enclosed within parentheses but they do not have to be C A B You can use expressions in many places in a design description You can e Assign them to variables or signals or use them as initial values of constants Use them as operands to other operators Use them for the return value of functions Use them as input parameters in a function call e Use them to control the actions of statements such as if loop and case For complex expressions enclose the expression in parentheses and use nested parentheses to specify the order of evaluation Expressions and Operations F 2 Operator Precedence Typical operations in an expression are e Arithmetic operations such as 7 and e Equality relational and logic operations lt lt gt gt I 88 and where the result is either a 1 true or a O false e User defined operations such as functions SystemC Compiler evaluates expressions in the same precedence and order of evaluation as C Table F 1 shows the C operator precedence from highest to lowest the nonsynthesizable operators are excluded from this list Expressions and Operations F 3 Table F 1 Operator Precedence Operator Function Use Class scope class name Member selectors object memb
14. Overall Functionality Loop OKCKCKCKCKCkCkCk Ck kk kok Ck kCk I kk Ck k k Ck kck ck kck I ck ck ck ck ke kk while true wait KOR RR KK k kok ok Koko k kok k kok k kok k kkk k kkk ke ke ke k k Read Input Samples Look COKCKCKCKCkCKCK KAKA I kk KAKA KAKA ke ke cout endl Reading in the samples Fast Fourier Transform Example D 12 lt lt endl while index lt 16 data req write 1 wait until data valid delayed 1 real index in real read imag index in imag read indextt data req write 0 wait Initialize index 0 M 4 N 16 len N gt gt 1 stage 0 len N incr 1 cout lt lt Computing lt lt endl KOK KKK KK kok k kok k Koko k kok k kok k kok K kk kok kok kkk Stages Loop KOKCKCKCKCkCkCK Ck k X kCk Ck kCk ck kck ck kck ck ckck ck kok ck RK ke e ke Loop iterates over the number of stages There are M stages where M log2 N already defined above Loop control variable is stages For every iteration stage it is incremented by 2 and incr is multiplied by 2 while stage M f len len gt gt 1 i 0 O kok k kok k kok k kok k kok k kok k kok k kok k kkk k kkk k k First Pass Loop KOKCKCKCKCkCkCK Ck k X kCk Ck kCk ck kck ck kck ck ckck ck ckok ck kok ck ke ke e kx Loop does the following a loop execute condition checked befor xecuting anything is i lt N b i is updat
15. Unit Unit Default Constant Scale code Scale type IQ Behavioral Model Example E 1 shows the header file and Example E 2 shows the implementation file for the IQ behavioral model Example E 3 shows a command script to synthesize the model to gates Inverse Quantization Example E 4 Example E 1 IQ Header File SC MODULE VD iq Declare ports Sc in clk CLK sc in lt bool gt reset sc in lt bool gt iq start sc in bool slice sc in lt bool gt load intra quantizer matrix sc in lt bool gt load non intra quantizer matrix sc in lt sc uint lt 8 gt gt W sc in lt bool gt run level valid Sc in lt sc uint lt 5 gt gt quantizer scale code sc in lt sc uint lt 2 gt gt intra dc precision sc in lt sc uint lt 5 gt gt dct dc size Sc in lt sc uint lt 11 gt gt dct dc differential sc in lt bool gt q scale type sc in lt bool gt alternate scan sc in lt bool gt end of block sc in lt bool gt mblock intra sc in lt sc uint lt 4 gt block count sc in lt sc uint lt 6 gt gt run sc in lt sc uint lt 12 gt gt level sc out lt sc int lt 12 gt gt f sc out lt bool gt f valid Sc out lt sc uint lt 6 gt gt f addr sc out bool iq block ready sc out bool iq calc ready sc in lt bool gt iq write block sc out lt bool gt iq error sc in lt bool gt iq skip sc_in lt bool gt iq clear Internal signals sc signal lt bool gt
16. acknowledge data sc signal lt bool gt valid data sc signal lt sc uint lt 8 gt gt error sc signal lt bool gt skip block out Data members sc uint 7 q scale 32 sc uint 6 scan zigzag 64 sc uint lt 6 gt scan alternate 64 Sc uint 7 default intra quant 64 bool iq sleep bool eob tmp sc uint lt 4 gt wait for ack bool previous tmp Inverse Quantization Example E 5 sc uint 5 sc uint 7 bool bool bool bool Sc int 12 quantizer scale code inp current address macroblock intra q scale type inp alternate scan inp reset dct pred inp level inp Sc uint 6 Sc uint 4 run inp dct size inp Sc uint lt 11 gt dct diff inp Sc int 12 sc int lt 26 gt sc int 12 Sc uint 2 Sc uint 3 sc uint 7 Sc uint 7 Sc uint 2 Sc uint 4 bool Sc uint 7 sc uint 7 bool sc int 12 Sc uint 6 bool bool Sc uint 8 sc int 12 dc dct pred 3 feb f ti corrector block count tmp quantizer scale matrix value intra dc precision inp block count inp mismatch control intra matrix ram 64 non intra matrix ram 64 next value 64 f out f addr out use load intra matrix inp use load non intra matrix inp offset f mat 64 sc signal lt bool gt CLK iqgate Declar implementation functions void entry void generate valid SC CTOR V
17. but timing constraints on the inner loops affect scheduling of the outer loops Therefore specify timing constraints on inner loops rather than on outer loops When a design contains successive loops at the same level SystemC Compiler preserves the source code ordering of these loops even if there are no data dependencies between them This means that the first loop in the source code will be fully executed in hardware before the loop that follows it is entered Behavioral Coding Guidelines 3 33 Labeling a Loop To simplify setting constraints on loops give each loop a label If you do not assign labels SystemC Compiler assigns a default name to each loop Example 3 35 shows in bold how to label a loop with either a C language line label or a synopsys compiler directive If both are applied to a line of code SystemC Compiler uses the C line label for scheduling constraints and in generated reports Example 3 35 Labeling a Loop my modulel entry C style line label reset loopl while true wait wait my_module2 entry Synopsys compiler directive while true snps line_label reset_loop2 wait wait In reports generated by SystemC Compiler commands the label is reflected in report hierarchy as my_modulel entry reset_loopl Behavioral Coding Guidelines 3 34 Using while Loops A while loop has a conditional exit that can be dynamic which means it is data
18. data ack write true wait until data ready delayed false data ack write false Fast Fourier Transform Example D 20 Example D 8 FFT Testbench Top Level Model Filename main fft cc This file instantiates all modules and ties them together with signals include systemc h include fft h include source h include sink h int sc main int ac char av f sc signal lt sc int lt 16 gt gt in real sc signal lt sc int lt 16 gt gt in imag sc signal lt bool gt data valid sc signal lt bool gt data ack sc signal lt sc int lt 16 gt gt out real sc signal lt sc int lt 16 gt gt out imag sc signal lt bool gt data reg sc signal lt bool gt data ready sc signal lt bool gt reset sc clock clock CLOCK 10 0 5 0 0 fft module FFT1 FFTPROCESS FFTl in real in real FFTI in imag in imag FFT1 data valid data valid FFT1 data ack data ack FFTl out real out real FFTl out imag out imag FFTl data req data req FFT1 data ready data ready FFT1 reset reset FFTl clk clock source module SOURCE SOURCEPROCESS SOURCE1 data req data reg SOURCEl out real in real SOURCEl out imag in imag SOURCE1 data valid data valid SOURCE1 reset reset SOURCE1 CLK clock sink module SINK1 SINKPROCESS SINK1 data_ready data ready SINK1 data ack data ack SINK1l in real out re
19. data read Now do the algorithm c do gcd a b Now write the output using sender initiated handshake gcd ready write true gcd write c wait WRITE LATENCY gdc ready write false wait int gcd mod do gcd int a int b int temp if a 0 86 b 0 while b 0 while a gt b 1 a a b wait temp a a b b temp wait else a 0 wait Using Handshaking in the Circuit and Testbench 6 7 return a kok k kok k kok kok k kok k kok k kok k kk kk kk gcdi test h header file ifndef READ LATENCY define READ LATENCY 2 endif ifndef WRITE LATENCY define WRITE LATENCY 2 endif SC MODULE testbench l sc in clk clk sc in lt bool gt send data sc in lt bool gt gcd ready sc in lt int gt gcd sc out lt bool gt reset sc out lt int gt data Process void do run Internal function void do handshake int a int b SC CTOR testbench SC CTHREAD do run clk pos KOR KKK KK kok k KAKAK KAKA k I KK ke ke ke ke e x kx gcdi test cc implementation file include systemc h include gcdl test h void testbench do run reset write false wait reset write true wait Using Handshaking in the Circuit and Testbench 6 8 reset write false wait cout l
20. except the classes Replace overloading overloading overloaded by SystemC with unique function calls Operator sizeof sizeof Not allowed Determine size statically for use in synthesis Pointer i Pointers are allowed only in Replace all pointers hierarchical modules which are with access to array not supported in SystemC elements or individual Compiler version elements 2000 05 SCC1 0 A char is treated as a string not as a pointer to memory Pointer type Not allowed Do not use pointers conversions Use explicit variable reference this pointer this Not allowed Replace Refining for Behavioral Synthesis 2 35 Table 2 2 Nonsynthesizable C C Constructs continued Category Construct Comment Corrective action Reference C amp Reference conversion User defined template class Type casting at runtime Type identification at runtime Explicit user defined type conversion Unconditional goto branching Unions Global variable Member variable Volatile variable Allowed only for passing parameters to functions Reference conversion is supported for implicit conversion of signals only Only SystemC templates classes such as sc int lt gt are supported Not allowed Not allowed The C built in types and SystemC types are supported for explicit conversion Not allowed Not allowed Not supported for synthesis Member variables accessed by two or more SC
21. i synopsys unroll operations wait The code in Example 3 44 does not have a statically determinable exit condition because the value of count depends on the value of an input which cannot be determined at compile time In this situation SystemC Compiler ignores the unro11 directive keeps the loop rolled and issues a warning that it cannot unroll the loop Consecutive Loops Each loop is a level of scheduling hierarchy According to general coding rule 5 you need to place a wait statement immediately after each loop to exit the level of scheduling hierarchy the loop creates When your design contains consecutive loops there is an overhead of one clock cycle latency to exit the loop hierarchy as shown in bold in Example 3 45 Behavioral Coding Guidelines 3 42 Example 3 45 Consecutive Loops With Overhead for int i 0 i 4 it e a 2 wait while i 0 e data in read wait wait Extra cycle while i 1 e b 3 wait wait real out write e wait wait If your design has consecutive loops you can improve the latency by modifying your code to collapse consecutive loops as shown in Example 3 46 Behavioral Coding Guidelines 3 43 Example 3 46 Collapsed Consecutive Loops Collapse the consecutive loops for int i 0 154 i wait e a 2 wait while i 0 i 1 wait
22. sc int 8 temp sc int 4 i a 5 write temp write with a constant index a i write temp write with non constant index i Using Arrays Register Files and Memories 5 4 Accessing Slices of an Array Location SystemC Compiler generates decoding hardware for each read and write access to an array location even if you are accessing a single bit or a range of bits called a slice of the data contained in that array location If you access multiple slices of the same array location by using separate reads to that location decode hardware is generated for each read Example 5 7 shows accesses to multiple slices within the same array location Example 5 7 Multiple Accesses to Slices in the Same Array sc int lt 8 gt a 16 sc int 4 templ temp2 sc int 4 i templ a i range 3 0 array read of first slice in location a i temp2 a i range 7 4 array read of second slice in location a i a i range 3 0 temp array write of first slice in location a i a i range 7 4 temp2 array write of second slice in location a i To improve the efficiency of the hardware created copy the array location into a temporary variable and access the various slices from the temporary variable This coding style requires just one array access and creates one instance of decode hardware Example 5 8 shows an example of this alternate coding style Us
23. tmp imag2 i 3 ps 5 imag2 in F m9 13 205 2 49 6 102 2 5 105 lt s 6 10 gt lt s 5 10 gt tmp real3 tmp real2 w real tmp imag2 w imag lt s 13 20 gt lt s 6 10 gt lt s 5 10 gt lt s 6 10 gt lt s 5 10 gt tmp_imag3 tmp_real2 w_imag tmp_imag2 w_real Fast Fourier Transform Example D 10 assign the reall out 15 imagl out 15 assign the reall out range 14 0 imagl out range 14 0 sign bit MSB tmp reall 16 tmp imag1 16 rest of the bits tmp reall tmp imagl assign the sign bit MSB real2 out 15 imag2 out 15 assign the rest of the bits real2 out range 14 0 imag2 out range 14 0 yi end func butterfly tmp real3 33 tmp imag3 33 tmp real3 tmp imag3 range 14 0 range 14 0 range 24 10 range 24 10 KOK KR kok k kok kok ok k kok k kok k kok k kok k k kok ck ko ke ke Gk k Process Definition Begin OKCKCKCKCCKCk k k kk kk kk X kk ckok ck X kk ke ke e x void fft module fft process KOR KR kok KAKA KAKAK KAKA k kok k kok k k kok kk ke kok Variable Declarations OKCKCKCKCKCKCk Ck k k kk kk kck ck kok ck ckok ck ckok ck ko sk e ke ke e x sc i s 3 SC SC SC OHS Ye FU Pb m sc i sc i Sc i sc i Sc i sc i Sc i Sc i t lt 16 gt t lt 16 gt p n A 16 gt p 0 A 16 gt t 16 t 16
24. 2 38 subset 2 30 SystemC constructs 2 33 O one way handshake 6 4 example 6 4 6 12 operand F 2 operation F 3 arithmetic F 3 equality F 3 logic F 3 relational F 3 user defined F 3 operator F 2 precedence F 3 SystemC bit types 2 41 integer types 2 42 output 3 6 registered 3 6 write 3 7 P pipelining handshake restrictions 6 40 loops 3 45 port 2 14 3 6 data types 2 15 read and write 2 17 sc in 2 14 sc in clk 2 14 sc inout 2 14 sc out 2 14 syntax 2 15 pragma See compiler directive precedence of operators F 3 IN 5 preserve function compiler directive 4 4 4 6 A 4 nonmember 4 9 restrictions 4 5 using 4 5 process 2 12 2 20 creating 2 22 method 2 21 refine 2 28 SC CTHREAD 2 21 3 2 SC THREAD 2 21 synchronizing with clock 3 2 R read array 5 3 input 3 7 port 2 17 signal 2 17 read preserve function netlist command 4 8 reducing runtime 5 7 refine advanced techniques 2 5 2 48 behavioral from architectural 1 10 C C model 2 6 control 2 3 2 47 data 2 3 2 30 2 37 data type recommendation 2 46 detailed architecture 2 8 for behavioral synthesis 2 1 internal communication 2 7 internal structure 2 6 overview 2 3 process 2 28 recommended practices 2 49 RTL from behavioral 1 15 B 15 structure 2 3 2 6 SystemC model 2 28 register file 5 1 access 5 15 IN 6 array mapping 5 9 A 6 registered output 3 6 relational operation F 3 reset behavior 3 46 resource compiler directive 5 9 A 6 resource
25. 26 do while 3 4 for 3 4 IN 4 SC CTHREAD 2 26 types 3 4 while 3 4 3 35 initialize variable 3 49 inout param compiler directive 4 10 A 5 input 3 6 nonregistered 3 6 read 3 7 interrupt behavior 3 46 introduction 1 1 introduction to refinement 2 3 IQ behavioral example E 4 example E 1 L label C line label 3 34 A 9 source code 3 34 large array 5 7 lifetime of data value 3 54 line label compiler directive 3 34 A 3 local memory declaring 5 11 example 5 11 logic operation F 3 loop conditional 3 10 continue 3 10 do while 3 33 3 36 for 3 33 3 36 for unrolled 3 37 infinite while 2 26 3 33 3 35 iteration 3 10 label 3 34 pipelining 3 45 pipelining handshake protocol 6 40 unroll 3 37 A 8 while 2 26 3 33 3 35 M map to module attribute A 6 map to operator compiler directive 4 11 A 3 map to registerfiles attribute 5 9 A 6 mapping arrays 5 1 member function 2 23 4 2 variables 2 18 memory 5 1 access 5 15 access bit slice 5 19 access redundancy 5 18 array mapping 5 11 contention 5 18 explore types 5 14 local 5 11 multiple array access 5 13 resources 5 11 timing 5 17 memory controller example C 1 behavioral C 9 functional C 5 method process 2 21 module 2 12 constructor 2 24 header file 2 13 implementation file 2 26 port 2 14 signal 2 16 syntax 2 13 variable 2 18 N nonmember function 4 4 preserve function 4 9 nonregistered inputs 3 6 nonsynthesizable C C constructs 2 34 data types
26. 26 gt VD iq quantization synopsys preserve function int tmpl sc int 26 tmp2 tmpl level inp 1 corrector tmp2 tmpl matrix value quantizer scale proper rounding if tmp2 amp 0x1f 0 amp amp tmp2 0 tmp2 tmp2 gt gt 5 1 else tmp2 tmp2 gt gt 5 cout lt lt test lt lt tmpl lt lt lt lt tmp2 xx endl return tmp2 sc_int lt 12 gt VD_iq mismatch synopsys preserve function int tmp bool ft bit f tbrb E60 tmp f t if mismatch control false if f t bit false tmp f t 1 else tmp f t 1 Inverse Quantization Example E 12 return tmp void VD iq reset prediction dc dct pred 0 0 dc dct pred 1 0 dc dct pred 2 0 void VD iq generate valid bool tmp false wait while 1 SC i tmp run level valid read end of block read eob tmp end of block read previous tmp tmp valid data write tmp if tmp true amp amp previous tmp true wait for ack 0 if wait for ack MAX WAIT FOR ACK wait for ack if wait for ack MAX WAIT FOR ACK 1 cout Error VD iq generate valid Valid without acknowledge at time lt lt sc time stamp lt lt endl wait for ack MAX WAIT FOR ACK if acknowledge data read true amp amp wait for ack MAX WAIT FOR ACK wait for ack MAX WAIT FOR ACK wait nt
27. AG A 4 INOUL DAFA cts sas wed eu ee RET wis KAAU LEGO DAL ES A 5 K iegie fe PI PPP A 6 synthesis off and synthesis 0n l l 4 A 7 translate off and translate 0N lt A 7 LOU So end ANG m ROPE DBA eed Se bed eke p A 8 C C Compiler Directives llle A 9 C Ine babel 2 AA boze t S S pede ed A 9 C Conditional Compilation lt lt A 9 Appendix B First In First Out Example FIPODSSGBNOM S Sa aka eu Bode KANA po de S o SO EA B 2 Architectural Model 5x sn bod NERD EK ADAN ALAALA LS B 2 Baliavieral Model gas lute x d TD yall Gio PR ER B 6 Ports and Signals ade bud raa betas B 6 Behavioral Description 2c eee ees B 8 Behavioral Testbench 45s z eagle dok SS B 11 Alb Models cu irt DLE Irem tee es eee oooh Ce e RR Ret c eb B 15 RTE Description aisi a KARO de ee et pee qp p B 16 RTE Te SIDOD CIL 5 pasama treni war mace rait bie ctus B 20 Appendix C Memory Controller Example Memory Controller Description ee eeee C 2 COMMANGS uae Toce ns mse mAh DER ERI C 2 PONS RE T Tm C 3 Communication Protocol aa C 4 Functional Simulation Model eee eee eee C 5 Refined Behavioral Model 0 c eee eee ee eee C 9 Date HR enu et ponet Pre ee RE T UE C 9 Communication Protocol a C 9 Glock PIACement su aaa an BENG anga an NIDA GAN C 10 Behavioral Model a C 10 Appendix D Fast Fourier Transform Example EET DSSEFIDHOB PORTS qe tarde
28. B 3 Behavioral Implementation File fifo bhv cc implementation file include systemc h include fifo bhv h void circ buf read write Reset operations headp 0 tailp 0 num in buf 0 full false empty true data out 0 wait Main loop while true if read fifo read Check if FIFO is not empty if num in buf 0 num in buf data out buffer headp full false if num in buf 0 empty tru Ignore read request otherwise wait else if write_fifo read Check if FIFO is not full if num in buf BUFSIZE buffer tailp data in num in buf mpty false if num in buf BUFSIZE full Ignore write request otherwise wait else wait true First In First Out Example B 9 Example B 4 Behavioral Synthesis to Gates Script search path search path SSYNOPSYS libraries syn target_library tc6a cbacore db synthetic library dw01 sldb dw02 sldb link_library target library synthetic library bc enable analysis info false effort level medium io mode super top_unit fifo_bhv sh date compile systemc top unit cc create clock clk p 10 bc time design schedule io io mode effort compile write hier f db o top unit t First In First Out Example B 10 effort level gate db Behavioral Tes
29. LATENCY cycles within which to sample the result of GCD 3 This process repeats each time the behavioral block can send new output data Looking at the testbench code in Example 6 1 you can see that the handshaking for the testbench is done in the do handshake function To send data to the behavioral block the testbench waits until the send data signal is asserted high To model the testbench latency for a read the code has a wait READ LATENCY 1 statement At the end of this wait the testbench writes two consecutive values on the data port which the behavioral block reads To get the output of the behavioral block the testbench waits until the behavioral block asserts the gcd ready signal high To model the testbench latency for a write the code contains a wait WRITE LATENCY 1 statement At the end of this wait the testbench reads the output of the behavioral block from the gcd port Using Handshaking in the Circuit and Testbench 6 11 One Way Handshake Initiated From Testbench Figure 6 2 shows a timing diagram for the GCD behavioral block with a slightly different handshaking mechanism than Figure 6 1 In this example the testbench initiates the handshake to the GCD block before sending new input After computing the output the GCD block initiates sending the output to the testbench Example 6 2 shows the code for the GCD block the testbench and the top level simulation executable Figure 6 2 Testbench Initiat
30. Synthesis 2 19 Processes Electronic systems are inherently parallel but programming languages such as C and C execute sequentially SystemC provides processes for describing the parallel behavior of hardware systems This means processes execute concurrently rather than sequentially like C functions The code within a process however executes sequentially Processes use signals to communicate with each other One process can cause another process to execute by assigning a new value to a signal that interconnects them Do not use data variables for communication between processes to avoid causing nondeterminism order dependency during simulation Defining a process is similar to defining a C function A process is declared as a member function of a module and registered as a process in the module s constructor You can declare and instantiate more than one process in a module but processes cannot contain other processes or modules A process is registered inside the module s constructor Registering a process makes it recognizable by SystemC Compiler as a process rather than as an ordinary member function You can register multiple different processes but it is an error to register more than one instance of the same process A process can read from and write to ports and internal signals Refining for Behavioral Synthesis 2 20 Types of Processes SystemC provides three process types SC CTHREAD SC METHOD and SC
31. SystemC model the design functionality of your hardware is already described as a software algorithm In that case you need little additional refinement of the behavioral code to implement the design in hardware using behavioral synthesis Converting to a Synthesizable Subset As the next stage in refinement you need to convert all nonsynthesizable code into synthesizable code This is required only for functionality that is to be synthesized Although you can use any SystemC class or C construct for simulation and other stages of the design process many C and C language constructs and SystemC classes are not relevant for synthesis Because these constructs cannot be synthesized into hardware SystemC Compiler does not support them and it displays anerror message if itencounters any of these constructs in your code You can comment out code that is needed only for simulation such as print statements for debugging Refining for Behavioral Synthesis 2 30 Excluding Simulation Specific Code SystemC Compiler provides compiler directives you can use in your code e To include synthesis specific directives e Toexclude or comment out simulation specific code so it does not interfere with synthesis You can isolate synthesis specific or simulation specific code with a compiler directive either the C language ifdef or a comment starting with the word synopsys Or snps and synthesis off Example 2 6 shows compiler directives in b
32. alala 3 28 Superstate Fixed Mode Coding Rules Examples 3 29 Superstate Fixed Coding Rule1 3 29 Superstate Fixed Coding Rule2 3 30 Finding the Cause of Timing Dependent Coding Errors 3 31 Using Conditional StatementS a 3 32 USING EOOPS 5d beber APA 3 33 Understanding How Loops Are Scheduled 3 33 Labeling a LOOP xxu a ER pa e 3 34 USING WHIIG LOODS us qub ag ee p mutus aae des bs 3 35 Using an Infinite while Loop lt 3 35 Using do while LOOpS EPIPSPPREXDUEEe 3 36 Using for LOOPS aed Re Soe aaa 3 36 Rolled Versus Unrolled Loops a 3 36 Rolled for Loops ag NA NG sva aig hanes OO NANG 3 37 Unrolling Ter EOODSs sib SEE kame S OUS ates 3 37 Comparing Rolled and Unrolled Loops 3 39 Selectively Unrolling Loop Iterations 3 40 Ensuring a Statically Determinable Exit Condition 3 41 Consecutive LoOpS tad da Re G koho tea 3 42 Pipelining Loop Rules 3 45 USING Resets ang ah pea eee i pee eee ea E EE 3 46 Describing a Global Reset 00 00 eee eee 3 46 Specifying the Reset Behavior lt 3 46 Specifying a Reset Implementation 3 48 Using Variables and Signals 0 eee eae 3 49 Initializing Variables RR eR hy esteem hs 3 49 Using Signals and Wait Statements a 3 50 vii viii Using Var
33. an RTL model instead of a behavioral model you need to do the following Separate the control logic and data path Define an explicit FSM for the control logic e Refine the module to be cycle accurate internally Example B 8 shows the header file for the RTL version of the FIFO and Example B 9 shows the implementation file This RTL example shows the level of detail you need in order to describe an RTL model which is automatically created by SystemC Compiler from a behavioral description The RTL coding style has separate processes for the FSM control and data path The FIFO RTL model has the following separate processes ns logic The process for describing the next state logic Update regs The process for updating all the FIFO registers e gen full The process for generating a buffer full signal gen empty The process for generating a buffer empty signal First In First Out Example B 15 RTL Description The I O communication for the RTL model is identical to the I O for the behavioral model Because the FIFO RTL description has four separate processes the RTL description has extra internal signals to communicate between the processes Example B 8 RTL Header File fifo rtl h header file define BUFSIZE 4 define LOGBUFSIZE 2 define LOGBUFSIZEPLUSONE 3 SC MODULE circ buf Same I O as behavioral sc in lt bool gt clk sc in lt bool gt read fifo sc in lt bool gt write fifo S
34. available for the specified data types Table 2 5 SystemC Integer Data Type Operators Operators sc int sc uint sc bigint sc biguinit Bitwise amp and or xor and not Yes Bitwise shift left and 55 shift right Yes Assignment 8 and Yes Equality Yes Relational lt lt gt and gt Yes Autoincrement and autodecrement Yes Bit selection x Yes Part selection range x y Yes Concatenation x y Yes Reduction and reduce or reduce and Yes xor reduce Refining for Behavioral Synthesis 2 42 Using Enumerated Types SystemC Compiler interprets an enumerated enum data type as a numerical value where the first element is equal to zero Appendix C Memory Controller Example shows an example of using an enumerated data type Using Aggregate Data Types To group data types into a convenient aggregate type define them as a struct type similar to Example 2 7 You need to use all synthesizable data types in a struct in order for the struct to be synthesizable SystemC Compiler splits the struct type into individual elements for synthesis Example 2 7 Aggregate Data Type struct package sc_int lt 8 gt command sc_int lt 8 gt address sc_int lt 12 gt data bi Appendix C Memory Controller Example shows an example of using an aggregate data type Using C Types The native C data types such as bool char
35. block ends if end of block read true break acknowledge data write true Sample inputs of normal block behavior and compensate for run level inp level read run inp run read if run inp 0 current address current addresstrun inp next value current address true Correct the values for dequantization corrector corrector calc quantizer scale quantizer Memory access matrix value W lookup Multiplications and correction f t t quantization Saturation ft saturation Mismatch control if f t 0 1 mismatch control mismatch control if current address MAX ADDRESS 1 f out mismatch else fout ft Address assignment f addr out inverse scan Inverse Quantization Example E 9 Output assignment f addr write f addr out f write f out f valid write true f mat f addr outtoffset f out wait 0 Prepare for next iteration current addresstt else wait iq calc ready write true wait This part isn t necessary when skipping a block and the output is already cleared if skip inp false clear inp true acknowledge data write false Fill the the empty spots otherwise positions of the second block are not correct as written in the previous cycle This could be done mor fficiently if the RAM has a res
36. creates an input port x and an output port x for the x reference parameter so it can perform the read and write Using Functions and DesignWare Components 4 10 Using DesignWare Components The map to operator compiler directive performs an action similar to the preserve function compiler directive except that it enables use of standard DesignWare components Using map to operator Example 4 5 shows code in bold that uses a DesignWare component The map to operator and return port name compiler directives must be the first line in the function body Example 4 5 Using DesignWare Parts Code fragment sc int lt 16 gt my mult const sc int lt 8 gt A const sc int lt 8 gt B snps map to operator MULT2 TC OP snps return port name Z Function code block return A B After you execute the SystemC Compiler compile systemc command this function is replaced by the DesignWare component MULT2 TC OP provided it exists in a synthetic library See the DesignWare Developer Guide for information on using DesignWare components Using Functions and DesignWare Components 4 11 Guidelines for Using map to operator Functions with the map to operator compiler directive require special consideration The following guidelines apply Inthe declaration of the function s prototype specify the map to operator compiler directive in the first line of the function body for example int xyz int a intb snp
37. d wait while e 0 Behavioral Coding Guidelines 3 24 Example 3 21 shows a do while loop without a wait statement before the loop which causes an HLS 52 error To correct this error insert a wait statement as shown in bold in Example 3 22 Example 3 21 Error in Use of Cycle Fixed Mode Coding Rule 1 do while Loop e a c d no wait do er a Ke s 1 wait while e 0 Example 3 22 Correct Cycle Fixed Mode Coding Rule 1 do while loop e da ud wait do Bout de AG ga LG wait while e 0 Behavioral Coding Guidelines 3 25 Cycle Fixed Coding Rule 2 With n representing the number of cycles required to evaluate a loop iteration condition 1 Inside the loop place nwait statements immediately after the loop conditional is evaluated 2 Outside the loop place n wait statements immediately after the loop exit The value of n must be at least one Do not place I O read or write statements between the n wait statements in either case Example 3 23 shows a while loop with a loop iteration condition that takes several clock cycles to evaluate For this example the conditional evaluation takes seven clock cycles To correct this error insert wait statements as shown in bold in Example 3 24 You can determine n number of cycles from the report created by the bc time designcommand Tocalculate n divide the time required for loop iteration and computation by the availa
38. determine the appropriate data type as well as the appropriate widths of each data type The following sections recommend the appropriate data type to use and when Selecting the data widths is a design decision and it is typically a tradeoff between the cost of hardware and the required precision This decision is therefore left to you Synthesizable Data Types C is a strongly typed language Every constant port signal variable function return type and parameter is declared as a data type such as bool or sc bit and can hold or return a value of that type Therefore it is important that you use the correct data types in expressions Refining for Behavioral Synthesis 2 37 Nonsynthesizable Data Types All SystemC and C data types can be used for behavioral synthesis except the following types Floating point types such as float and double Fixed point types sc fixed sc ufixed sc fix and sc ufix Access types such as pointers File types such as FILE I O streams such as stdout and cout which are ignored by SystemC Compiler SystemC sc logic and sc Iv are used for RTL synthesis only not for behavioral synthesis Refining for Behavioral Synthesis 2 38 Recommended Types for Synthesis For the best synthesis use appropriate data types and bit widths so SystemC Compiler does not build unnecessary hardware Use the SystemC data types listed in Table 2 3 in place of the equivalent C native type to restrict bit si
39. directive int xyz int a const int amp b snps map to operator XYZ OP snps return port name P See Using DesignWare Components on page 4 11 preserve function Use the preserve function compiler directive to preserve a function as a separate level of hierarchy Place the compiler directive in the first line of the function body Define my func int my func int y int amp x synopsys preserve function X X y return x void my module entry int a b c c my func a b Compiler Directives A 4 During synthesis the level of hierarchy is compiled into a component that is treated exactly the same way as any other combinational component such as an adder or a multiplier Only functions that describe purely combinational RTL designs can be preserved See Using Preserved Functions on page 4 4 inout param Use the inout param compiler directive with the preserve function compiler directive SystemC Compiler maps nonconstant C reference parameters to the output ports of the design corresponding to a preserved function If the preserved function contains a read from a reference parameter SystemC Compiler assumes that you are trying to read an output port and issues an error message unless you use the inout_param compiler directive Notice that the inout_param is placed immediately after the reference parameter and is inside the parentheses The preserve_function dir
40. for int i 0 154 i e a 2 wait while i 0 e b 2 wait do wait e b 2 if i 0 break while i 0 wait wait e a 2 wait Behavioral Coding Guidelines 3 22 Cycle Fixed Mode Coding Rules Examples Following are the cycle fixed coding rules and an example of each Cycle Fixed Coding Rule 1 Place at least one wait statement before a conditional for while or do while loop except the main infinite loop Example 3 17 shows a for loop without a wait statement before the loop which causes an HLS 52 error To correct this error insert a wait statement as shown in bold in Example 3 18 Example 3 17 Error in Use of Cycle Fixed Mode Coding Rule 1 for Loop EF la BB dq no wait for int i 0 i 4 i e a ua od i wait Example 3 18 Correct Cycle Fixed Mode Coding Rule 1 for Loop e lay c d wait for int i 0 i 4 i e a c XAH 1 wait Behavioral Coding Guidelines 3 23 Example 3 19 shows a while loop without a wait statement before the loop which causes an HLS 52 error To correct this error insert a wait statement as shown in bold in Example 3 20 Example 3 19 Error in Use of Cycle Fixed Mode Coding Rule 1 while Loop gom a ctum xo no wait while e 0 poe A ONT ue S wait Example 3 20 Correct Cycle Fixed Mode Coding Rule 1 while loop e a c
41. for Behavioral Synthesis 2 48 Refinement Recommendations We recommend the following practices during refinement After each step in refinement reverify your design to ensure that you did not introduce errors during that step Although it is recommended that you thoroughly refine at each refinement stage it is not necessary For example during data refinement you can refine one data type at a time and evaluate the impact on synthesizability and QOR using SystemC Compiler Similarly you may want to replace one non synthesizable construct with a synthesizable construct and reverify the design before replacing the next non synthesizable construct Thoroughly refine the control at one time Control refinement affects the I O behavior of the block and the blocks that interact with it Itis easier to fix the I O timing of all hardware blocks during structure refinement and use that I O timing during control refinement Refining for Behavioral Synthesis 2 49 Refining for Behavioral Synthesis 2 50 Behavioral Coding Guidelines This chapter describes the behavioral coding style guidelines you can use to ensure successful synthesis with SystemC Compiler This chapter contains the following sections Using Clocked Thread Processes Using Inputs and Outputs Behavioral Coding Style Rules Using Conditional Statements Using Loops Using Resets Using Variables and Signals Behavioral Coding Guidelines 3 1 Us
42. in Example 2 9 Example 2 9 Unknown Variable Bit Size int i for 4140 1 lt Y I loop code Refining for Behavioral Synthesis 2 44 Data Members of a Module It is strongly recommended that you do not use data members for storage Use variables local to the process for all storage requirements in a process Example 2 10 shows a data member x that is used by the process entry Rewrite this code in the style shown in Example 2 11 This prevents inadvertent use of the data member variable for interprocess communication Example 2 10 Incorrectly Using a Data Member as a Variable SC MODULE module name int x Data member l KKK k k k k Ck Ck Ck Ck Ck Ck ck ck ck module entry if x O for int i20 i lt 7 itt loop code Example 2 11 Correct Use of Local Variables KKK k k k k k k Ck Ck Ck Ck ck ck ck Implementation file x module entry int x Local variable declaration if x 0 for int i20 i lt 7 itt loop code Refining for Behavioral Synthesis 2 45 Recommendations About Data Types For a single bit variable use the native C type bool or the SystemC type sc bit For variables less than 64 bits wide use sc intor sc uint data types Use sc uint for all logic and unsigned arithmetic operations Use sc int for signed arithmetic operations as well as for logic operations For variables larger than 64 bits use sc bigint or
43. in lt bool gt output seen Output is seen Sc out int gcd out Port to send GCD value Process void gcd algo The process that does GCD Internal functions int do gcd int a int b Function of gcd algorithm SC CTOR gcd mod SC CTHREAD gcd algo clk pos watching reset delayed true l KOR KKK kok k kok KAKA K kok k kok k kok k kok ke kok kok gcd3 cc two way handshake implementation file include systemc h include gcd3 h void gcd mod gcd algo f int a b Two variables to compute gcd int c The GCD Reset operations gcd out 0 send input false output ready false wait while true Using Handshaking in the Circuit and Testbench 6 23 First get the two inputs using receiver initiated handshake send input write true wait wait until data ready delayed true Read data and deassert send input send input write false a data in read wait b data in read Now do the algorithm c do gcd a b Now write the output using sender initiated handshake output ready true gcd out c wait wait until output seen delayed true output ready false wait int gcd mod do gcd int a int b int temp if a 0 amp amp b 0 while b 0 while a gt b a a b wait temp a a b b temp wait else
44. in the SC CTHREAD process Appendix E Inverse Quantization Example shows an example that uses numerous member functions A member function that is not a process can return any data type but a member function that is a process can return only a void type See Using Member Functions on page 4 2 for further information Refining for Behavioral Synthesis 2 23 Module Constructor For each module you need to create a constructor which is used to Register processes Define a sensitivity list for each SC METHOD process Define an optional global reset For synthesis other statements are not allowed in the constructor Note A single global reset is supported for synthesis which is explained in Describing a Global Reset on page 3 46 Multiple global resets are not allowed Example 2 3 shows the header file for a complex number multiplier with a global reset In this example the constructor registers an SC CTHREAD process and defines a global reset which is shown in bold Refining for Behavioral Synthesis 2 24 Example 2 3 Module Constructor cmult hs h header file SC MODULE cmult hs Declare ports sc in lt bool gt reset sc in sc bv lt 8 gt gt data in SC in clik clk sc out lt sc int 16 gt real out sc out lt sc int lt 16 gt gt imaginary out Declare internal variables and signals Declare processes in the module void entry Co
45. include gcd2 test h void testbench do run f reset write false data ready write false wait reset write true wait reset write false wait cout Reset Don Begin Testing n Using Handshaking in the Circuit and Testbench 6 15 do handshake 12 6 do handshake 172 36 do handshake 36 172 do handshake 19 5 do handshake 2584 4712 do handshake 15 0 cout lt lt Testing Done n sc stop void testbench do handshake int a int b f cout lt lt GCD of lt lt a lt lt and lt lt b lt lt is We Sender initiated handshake send data ready signal data ready write true wait READ LATENCY Wait for latency Now write data in 2 consecutive cycles data write a data ready write false wait data write b wait Sender initiated handshake wait until sender is ready wait until gcd ready delayed true wait WRITE LATENCY 1 Wait for latency Now read data cout lt lt gcd read lt lt endl wait KOR KKK KK kok KR KR KK OK ke ke ke ke KK gcd2_main cc top level simulation model include systemc h include gcd2 h include gcd2 test h int main f sc signal lt int gt data gcd sc signal bool reset data ready gcd ready sc clock clock Clock 20 0 5 Using Handshaking in the Cir
46. intra matrix ram inverse scan else if macroblock intra false amp amp use load non intra matrix inp false matrix value tmp 16 else if macroblock intra true amp amp use load non intra matrix inp true matrix value tmp intra matrix ram inverse scan else matrix value tmp default intra quant inverse scan return matrix_value_tmp Inverse Quantization Example E 15 Example E 3 Behavioral Synthesis to Gates Script search path search path SSYNOPSYS libraries syn ram target library tc6a cbacore db synthetic library dw01 sldb ram sldb link library target library synthetic library bc enable analysis info false effort level medium jo mode super top unit VD iq sh date define design lib RAMS path ram define design lib DBS path db compile systemc top unit cc compile preserved functions create clock CIK p 20 bc time design schedule io io mode effort effort level compile map low write hier f db o top unit gate db Inverse Quantization Example E 16 m Expressions and Operations This appendix provides basic information about using expressions and operators in a SystemC behavioral description Expressions and Operations F 1 Using Expressions In C an expression is a combination of operators and operands that can be evaluated according to the semantic rules of the language
47. of wait statements in the branches Example 3 9 shows if else conditional branching The if branch has a wait statement and the else if and else branches do not have wait statements This causes an HLS 233 error in cycle fixed mode and an HLS 47 error in superstate fixed mode To correct this error insert a wait statement as shown in bold in Example 3 10 Notice that Example 3 10 has two wait statements in the if branch and only one wait statement in each of the other branches This is valid code because the number of wait statements does not need to be the same in each conditional branch Behavioral Coding Guidelines 3 16 Example 3 9 Error in Use of General Coding Rule 4 If Conditional if a lt b e a c d wait else if a b e b c d no wait else e c d no wait Example 3 10 Correct General Coding Rule 4 If Conditional if a lt b e a c d wai wai else if a b e b c d wait else e c d wait Behavioral Coding Guidelines 3 17 Example 3 11 shows if else conditional branching with an implicit else branch The if branch and the else if branches have wait statements An if else conditional statement implies an else branch by default The implicit else branch causes an HLS 233 error in cycle fixed mode and an HLS 47 error in superstate fixed mode To correctthis error insert an else branch wit
48. operations anyplace in the schedule if doing so does not violate data and control dependencies e SystemC Compiler allocates a dedicated register for each signal used in the process variables can share registers if the variable lifetimes do not overlap Signal reads and writes are constrained by wait statements depending on the I O scheduling mode variable reads and writes are not constrained by wait statements Initializing Variables SystemC Compiler supports initialization of ports signals or variables only during global reset as shown in Example 3 47 on page 3 47 Use a global reset to define initial values to ensure that pre synthesis and post synthesis simulation results match Behavioral Coding Guidelines 3 49 Using Signals and Wait Statements Figure 3 5 shows a segment of code that reads data from signals performs a calculation and writes to the output port Rather than storing the read data in variables the code reads again from the signals to perform the second calculation Seven or more clock cycles are required to execute this segment of code The operations happen sequentially because the read operations create data dependencies Figure 3 5 illustrates the design s data flow graph where circles represent operations and lines represent dependent data relationships A circle containing an r represents a port read operation a w is a port write x is a multiply and so forth The dashed lines represent clock cyc
49. or other modules read to and write from memory Commands The memory controller responds to the following four commands other commands are illegal e WTBYT The WTBYT command writes a byte of memory It is a 3 byte sequence of the WTBYT command address and data e WTBLK The WTBLK command writes a block of memory It is a 6 byte sequence of the WTBLK command address and 4 bytes of data e RDBYT The RDBYT command reads a byte of memory It is a 3 byte sequence of the RDBYT command address and getting the new data e NOP The NOP command is an idle or no operation state Memory Controller Example C 2 Ports The memory controller has the following ports into An sc in port for reading the command address and data outof An sc out port for returning the data read from memory clk An sc_in_clk port for the process reset Ansc_inportfor global reset which de asserts the com_complete signal new_command An sc_in port handshake signal that asserts high when a new command is available for processing com_command An sc_out port handshake signal that asserts high when a command is complete and the memory controller can accept a new command Memory Controller Example C 3 Communication Protocol The communication protocol between the memory controller and a testbench or another module executes in the following sequence 1 Atestbench or module communicating with the memory controller write
50. reads in real and imaginary samples from files named in real and in imag which are ASCII files containing values The source block interacts with the FFT behavioral block using two way handshake The sink cc file reads the real and imaginary components of the output transform values from the FFT block It writes the values to output files named out real and out imag which are ASCII format files of the output values The sink block also interacts with the FFT block by using two way handshake Example D 6 shows the source block Example D 7 shows the sink block and Example D 8 shows the top level simulation executable main fft cc Fast Fourier Transform Example D 17 Example D 6 FFT Testbench Source source h header fil SC MODULE source module sc in bool data reg sc out lt sc int lt 16 gt gt out real Sc out sc int lt 16 gt gt out imag sc out bool data valid sc out lt bool gt reset sc in clk CIK void source process SC CTOR source module f SC CTHREAD source process CLK pos l ROR KKK kk kok kok X kk ke e ke ke e e e e x source cc implementation file include systemc h include source h void source module source process FILE fp real fp imag int tmp val fp real fopen in real r fp imag fopen in imag r reset write true wait 5 reset write false data valid write false while true f wait until data
51. sc biguint if you want to do arithmetic operations with these variables If you want to do logic operations use sc bv instead Usesc logicorsc lvonly when you need to model three state signals or buses When you use these data types avoid comparison with X and Z values because such comparisons are not synthesizable Use native C integer types for loop counters or when you need a variable of the size defined by the native C type For example on most platforms a char is 8 bits wide a short is 16 bits wide and an int and a long are each 32 bits wide Use the C enum for all enumerated types for example state variables Use the C struct for all aggregate types Refining for Behavioral Synthesis 2 46 Refining Control To refine control you specify I O behavior and latency At this point in the refinement process your code still looks like the original software algorithm To refine control you need to insert wait statements in your code to clearly specify the relative ordering of I O operations the cycles in which I O happens and the latency of your design The placement of wait statements is governed by the coding style rules for the I O scheduling mode you plan to use Chapter 3 Behavioral Coding Guidelines describes the coding style rules that govern the placement of wait statements in your code Follow the coding style rules in order to insert the minimal number of wait statements to schedule your design wi
52. sc signal lt int gt data out next Declare processes void ns logic Next state logic void update regs Update all registers void gen full Generate a full signal void gen empty Generate an empty signal Constructor SC CTOR circ buf SC METHOD ns logic sensitive read fifo write fifo lt lt data in lt lt num in buf SC METHOD update regs sensitive pos clk SC METHOD gen full sensitive num in buf next Introduction 1 16 SC METHOD gen empty sensitive num in buf next l RRR RK kok kok kok k kok kok kk kk KK ke ke ke ke e kk fifo rtl cc implementation file include systemc h include fifo rtl h void circ buf gen full if num in buf next read BUFSIZI full next 1 else full next 0 Gl void circ buf gen empty if num in buf next read 0 empty next 1 else empty next 0 void circ buf update regs if reset read 1 full 0 empty 1 num in buf 0 buf0 0 buf1 0 buf2 0 buf3 0 data_out 0 else full full next empty empty_next num_in_buf num_in_buf_next buf0 buf0 next bufl bufl next buf2 buf2 next buf3 buf3 next data out data out next void circ buf ns logic f Introduction 1 17 De buf0_ buti buf2_ buf3_ num_i data_ if E 4f el
53. t 16 t 16 t 16 t 16 t 16 t 16 ps resource p to regist n n a n n resource ap to regist n n resource ap to regist nt n a n n n n n n n n p to regist real 16 reg a variables rfiles 6 reg b rfiles imag 1 W_real 7 reg_c rfiles W_imag 7 ps resource reg_d rfiles w_real w_imag reall_in imagl_in real2_in imag2 in reall out imagl out real af imag Bf W real W imag A Fast Fourier Transform Example D 11 sc int lt 16 gt real2 out Sc int 16 imag2 out sc int 4 stage sc int lt 6 gt N Sc int 4 M sc int 6 len sc uint 4 bits i Sc uint 4 bits index short i short j short index short index2 short windex short incr ROR KKK kok k IK I RK RK k k k k k k k k k Reset Initializion of signals and variables OKCKCKCKCKCkCkCk Ck kk kok k KAKA KAKA ck kck ck I ck kk data req write 0 data ready write 0 index 0 W real 0 942 Precomputed twiddle factors for 16 point FFT W imag 0 389 W real 1 718 W imag 1 716 W real 2 388 W imag 2 932 W real 3 2 W imag 3 1005 W real 4 380 W imag 4 926 W real 5 702 W imag 5 708 W real 6 915 W imag 6 385 wait KOR KKK KK KK KK kk kkk kkk kok k kok AKK KAKA ko kk ke kk
54. testbench to get the data ready At the end of this wait the testbench writes two consecutive values on the data port which the behavioral block reads The handshaking for the output of the behavioral block is identical to that in Example 6 1 on page 6 6 Using Handshaking in the Circuit and Testbench 6 18 Constraining the Width of Handshake Strobes Because SystemC Compiler can insert clock cycles in the superstate fixed scheduling mode you need to constrain the number of clock cycles used to raise or lower handshake signals and you also need to constrain the number of cycles between raising a handshake signal and reading or writing data For example in Example 6 1 on page 6 6 you need to constrain the number of cycles between reading a and reading b to one cycle And you also need to constrain the number of cycles between assertion of send data and reading the value of a Figure 6 3 shows the section of code with the input handshaking where you need to constrain the cycles Line labels are added to make it more convenient to use the set cycles command Figure 6 3 Constraining Input Handshake Signals Constrain to send d send data write true READ LATENCY wait cycles wait READ LATENCY send data write false read dl a data read wait read d2 b data read Constrain to one cycle Use the set cycles and find commands described in the CoCentric SystemC Compiler User Guide to set these cons
55. the set memory output delay and set memory input delay commands See the CoCentric SystemC Compiler User Guide for information about these commands Using Arrays Register Files and Memories 5 17 Eliminating Redundant Memory Accesses Every array access infers a memory read or memory write operation Redundant memory operations result in longer schedules to avoid memory contention Example 5 16 creates a redundant memory read Example 5 16 Redundant Memory Read X a i 5 a i 11 y A more efficient coding style assigns the array location to a temporary variable as shown in Example 5 17 Example 5 17 Array Location Assigned to Temporary Variable temp alil x temp 5 y temp 11 Using Arrays Register Files and Memories 5 18 Accessing Bit Slices of Memory Data Variable and signal accesses such as assignment or use in an expression operate on the entire value When a single bit or a bit slice of a variable or signal is assigned a value the following steps occur 1 The original value of the variable or signal is retrieved 2 The new bit value is patched in 3 The resulting value is assigned to the variable or signal This process is inefficient when you need to access only a bit or slice of memory data For example assume that e Ris an array of struct types with fields red green and blue lt R maps to a memory with one cycle read and write operations The following assign
56. the United States of America Disclosure to nationals of other countries contrary to United States law is prohibited It is the reader s responsibility to determine the applicable regulations and to comply with them Disclaimer SYNOPSYS INC AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Registered Trademarks Synopsys the Synopsys logo AMPS Arcadia CMOS CBA COSSAP Cyclone DelayMill DesignPower DesignSource DesignWare dont use EPIC ExpressModel Formality in Sync Logic Automation Logic Modeling Memory Architect ModelAccess ModelTools PathBlazer PathMill PowerArc PowerMill PrimeTime RailMill Silicon Architects SmartLicense SmartModel SmartModels SNUG SOLV IT SolvNET Stream Driven Simulator Synopsys Eagle Design Automation Synopsys Eaglei Synthetic Designs TestBench Manager and TimeMill are registered trademarks of Synopsys Inc Trademarks ACE BC View Behavioral Compiler BOA BRT CBA CBAII CBA Design System CBA Frame Cedar CoCentric DAVIS DC Expert DC Expert Plus DC Professional DC Ultra DC Ultra Plus Design Advisor Design Analyzer Design Compiler DesignTime Direct RTL Direct Silicon Access dont touch dont touch network DW8051 DWPCI ECL Compiler ECO Compiler Floorplan Manager FoundryModel FPGA Compiler FPGA Compiler Il
57. token into sc in bool reset sc in bool new command sc out lt token gt outof Sc out lt bool gt com complete Internal variables unsigned char memory 256 void entry SC CTOR mem controller SC METHOD entry sensitive new command reset endif Memory Controller Example C 6 Example C 2 Memory Controller Implementation File mem controller cpp implementation file include systemc h include memc types h include token h include mem controller h void mem controller entry token com pkt if reset true com complete write false else if new command posedge com pkt into read switch com pkt command opcode case NOP break case RDBYT get data out of memory com pkt data 0 memory com pkt address outof write com pkt break case WIBYT memory com pkt address com pkt data 0 break case WTBLK for short i 20 i 4 i memory com pkt addressti com pkt data i break default cout lt lt Illegal opcode lt lt com_pkt command lt lt endl break end switch com complete write true handshake end else if Memory Controller Example C 7 else if new command negedge com complete write false handshake end else if els end entry Example C 3 Token Header File token h header file struct token command_t comm
58. use registerfiles variable to true You can quickly compare the runtime of the compile systemc command with this variable set to true and then to false to see if your design would benefit from mapping arrays to register files or memories For details about using register files see the CoCentric SystemC Compiler User Guide Mapping Specific Arrays to Register Files To map specific arrays to register files use the synopsys resource compiler directive and the map to registerfiles attribute in your code to specify the arrays that are to be mapped to register files Example 5 10 shows a section of code that uses the synopsys resource compiler directive and the map to registerfiles attribute shown in bold to map an array named mem In this example R1 is a resource in the synthetic library Using Arrays Register Files and Memories 5 9 Example 5 10 Mapping Specific Arrays to Register Files sc int 16 mem 16 sc int 32 mem 16 synopsys resource RI variables mem map to registerfiles TRUE The following are all mapped to memory Write to mem mem 0 a mem 1 b and so forth Read from mem a mem 0 b mem 1 and so forth Using Arrays Register Files and Memories 5 10 Mapping Arrays to Memories You can map read or write operations of arrays to memory read or write operations A memory RAM contains accessing logic that is transparent to your design Map arrays of variab
59. version was refined into the fixed point behavioral version The data ports were refined from an infinite precision representation to a finite bit width representation The computations were refined to fixed point arithmetic Data Read Two Way Handshake The FFT block initiates reading of a data sample by assertion of the data req signal Next it waits for the data valid signal to assert Then it de asserts the data req signal and reads from the in real and in imag ports The FFT block reads 16 samples of data Data Write Two Way Handshake After the FFT calculation is performed the block writes the transformed values to a sink block in the testbench It writes the real and imaginary components of the transformed value on the out real and out imag ports Next it asserts the data ready signal indicating that the FFT is ready to read data from its ports It waits for the data ack signal to assert then it sends the next set of 16 values Fast Fourier Transform Example D 3 FFT Functional Model Example D 1 shows the header file and Example D 2 shows the implementation file of the 16 point FFT functional model This model uses floating point data types which are refined to fixed point data types for the behavioral model Example D 1 FFT Functional Header File struct fft sc module SC in lt sc int lt 16 gt gt in real Sc in sc int lt 16 gt gt in imag sc in bool data valid Sc in bool data ack Sc out lt sc int
60. wait If you pipeline the loop with an initiation interval of one clock cycle the three loop iterations overlap as shown in Figure 6 10 Using Handshaking in the Circuit and Testbench 6 40 Figure 6 10 Incorrect Loop Pipeline With Handshake Iteration 1 0 Iteration i 1 Iteration i 2 Initiation interval 1 Clock 1 send_data write TRUE a cycles Conflicting writes to port send data 2 send data write FALSE send data write TRUE lt at clock cycle 2 send data write FALSE send data write TRUE send data write FALSE Figure 6 10 shows an incorrect handshake protocol for a pipelined loop that causes resource contention on the send data port when the initiation interval is one clock cycle In clock cycle 2 the send data port writes a FALSE in iteration 1 and a TRUE in iteration 2 In clock cycle 3 the situation is similar SystemC Compiler reports a resource contention error on the send data port You can resolve this resource contention by extending the initiation interval to two clock cycles as shown in Figure 6 11 Using Handshaking in the Circuit and Testbench 6 41 Figure 6 11 Correct Loop Pipeline With Extended Initiation Interval Iteration i20 Iteration 1 1 Iteration 1 2 Clock 1 send data write TRUE Initiation interval 2 2 send data write FALSE send data write TRUE send data write FALSE send data write TRUE
61. wed em Sd ahha add D 2 FET GompU ldtlObl sz eae PUPPES ERE tees D 2 Refining From Functional to Behavioral D 3 Data Read Two Way Handshake liiis D 3 Data Write Two Way Handshake anaana D 3 FFT Functional Model so sicura kaan bw ane wh tes D 4 FFT Behavioral Model di ee E EG 9 ee Saar D 9 BEN JESIDENG DEED D 17 Appendix E Inverse Quantization Example IG DDeSCHDUOET s cuni ce KAN cakal dv b ro Se e d E 2 IQ Data FloW PD RA o T E E 3 Xi IQ Block Diagram AT E 4 IQ Behavioral Model s s s s aa E 4 Appendix F Expressions and Operations Using EKPressi0nNs Ph OR Pen EN Vra freed d F 2 Operator Precedence x Lebe sud maaakit pde Eb F 3 Index Xii Figures Figure 1 1 Figure 1 2 Figure 1 3 Figure 1 4 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 2 6 Figure 2 7 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 System Design Levels of Abstraction 1 3 Architectural Model na ER eere o aha 1 4 Behavioral Model 6338 038838 x Y EI RR PR ed 1 9 RTE Model rc PEE 1 14 Refinement Stages and Activities 2 4 MPEG Decoder Functional Structure 2 7 MPEG Decoder Top Level Architecture 2 8 MPEG Decoder Detailed Architecture 2 9 Moduler s iar On a xb aca dh ok M In um ene de a d 2 12 Module POLIS aac dbz e oa e ee oco e h 2 14 Processes an
62. wrapper generation tool address and data bus waveforms were fixed to the first cycle For information about this enhancement see the CoCentric SystemC Compiler Behavioral User Guide Known Limitations and Resolved STARs Information about known problems and limitations as well as about resolved Synopsys Technical Action Requests STARs is available in the CoCentric SystemC Compiler Release Note in SolvNET To see the CoCentric SystemC Compiler Release Note 1 Go to the Synopsys Web page at http www synopsys com and click SolvNET If prompted enter your name and password If you do not have a SOLV IT user name and password you can obtain them at http www synopsys com registration Click Release Notes then open the CoCentric SystemC Compiler Release Note XXV About This Guide xxvi The CoCentric SystemC Compiler Behavioral Modeling Guide describes system level design terminology and explains how to develop or refine a SystemC model for behavioral synthesis with SystemC Compiler For information about SystemC see the Open SystemC Community web site at http www systemc org Audience The CoCentric SystemC Compiler Behavioral Modeling Guide is for system and hardware designers and electronic engineers who are familiar with the SystemC Class Library and the C or C language and development environment Familiarity with one or more of the following Synopsys tools is advantageous but not required
63. you pass the same object by reference to different parameters For example this problem occurs in the following Definition void abc int a const int amp b int amp c snps map to operator ABC OP void xyz function call that causes alias abc x y y In above example parameters b and c are bound to the same y variable causing an error Another more subtle alias can result from the following function call abc x a i mpl Using Functions and DesignWare Components 4 13 In the above function call a potential alias occurs based on the value of i and j In such a situation you can use a temporary variable to avoid the problem for example abc x a i temp a j temp Using Functions and DesignWare Components 4 14 Using Arrays Register Files and Memories This chapter describes how to use arrays including how to map arrays to register files and memories It also provides coding guidelines for efficiently accessing register files and memories This chapter contains the following sections Using Arrays Array Implementations Mapping Arrays to Register Files Mapping Arrays to Memories Accessing Register Files and Memories Efficiently Using Arrays Register Files and Memories 5 1 Using Arrays SystemC Compiler supports single dimension arrays and multidimensional arrays Variable indexing into arrays creates decoding logic in hardware and sharing of array index ope
64. 1 1 integer data types 2 42 integer operator types 2 42 language elements 2 1 nonsynthesizable constructs 2 33 refine model 2 28 synthesizable subset 2 32 T testbench FFT D 17 FIFO example B 20 handshake 6 1 process types 2 21 timed model 1 5 timing errors 3 31 timing of memories 5 17 translate off compiler directive A 7 translate on compiler directive A 7 two way handshake example 6 21 6 29 U unroll compiler directive 3 37 A 8 untimed model 1 5 user defined operation F 3 V variable 3 49 bc use registerfiles 5 9 guidelines for using 3 49 initializing 3 49 mapping to register 3 53 member 2 18 module 2 18 IN 7 W write array 5 3 wait statement 3 2 3 3 3 7 output 3 7 wait until statement 3 2 3 3 port 2 17 watching 3 46 signal 2 17 while loop 2 26 3 33 3 35 IN 8
65. 5 produces the timing diagram shown in Figure 6 7 Two cycles are required between the assertion of the ready for data signal and the new data available signal Using Handshaking in the Circuit and Testbench 6 36 Figure 6 7 Timing Diagram of while Loop a JU UUUU UU ready_for_data c x data Old data New data new data available lt Using if else You can use an infinite while loop that contains an if else conditional branch to accomplish the handshake in one cycle This method moves the wait statement required for loop exit into the loop Example 6 6 shows a fragment of code for this alternative code with the wait statement in bold and Figure 6 8 shows the timing diagram Example 6 6 Fast Two Way Handshake Using while Loop new data available write 0 while true if ready for data read 0 wait else new data available write 1 data write wait break wait Using Handshaking in the Circuit and Testbench 6 37 Figure 6 8 Timing Diagram Using if else ready for data data Old data New data new data available PEE lt gt SystemC provides an convenient alternative syntax for fast handshaking the wait_until statement described in the next section Using Handshaking in the Circuit and Testbench 6 38 Using wait until You can use a wait until statement rather than a while loop to accomplish a fast handshake as shown in bold in the code fragment in Ex
66. A Behavioral Input Data Flow FFT Ports and Data Types IQ Blocks IO Data FlOW paa paaa o nee c peti rH Rd eases IQ Block Diagram Tables Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Table A 1 Table F 1 Nonsynthesizable SystemC Classes 2 33 Nonsynthesizable C C Constructs 2 34 Synthesizable Data Types a 2 39 SystemC Bit and Bit Vector Data Type Operators 2 41 SystemC Integer Data Type Operators 2 42 SystemC Compiler Compiler Directives A 2 Operator Precedence eee F 4 XV Xvi Examples Example 1 1 Example 1 2 Example 1 3 Example 2 1 Example 2 2 Example 2 3 Example 2 4 Example 2 5 Example 2 6 Example 2 7 Example 2 8 Example 2 9 Example 2 10 Example 2 11 Example 3 1 Example 3 2 FIFO Functional Model GG FIFO Behavioral Coding BA BOLO pl EN dete T oer sive Pes Using read and write Methods Creating a Clocked Thread Process in a Module Module Constructor llle Module Behavior A Eo Basic Reset Action and Main Loop Excluding Simulation Only Code Aggregate Data Type a Implicit Bit Size Restriction Unknown Variable Bit Size Incorrectly Using a Data Member as a Variable Correct Use of Local Variables Infinite LoopS
67. A 9 ifndef compiler directive A 9 operator 3 32 A abstraction level architectural 1 3 1 4 behavioral 1 3 1 9 choosing for synthesis 1 19 RTL 1 3 1 14 access memory 5 15 memory bit slice 5 19 multiple arrays 5 13 register file 5 15 aggregate data type 2 43 architectural FIFO example B 2 model 1 4 architecture refinement 2 8 arithmetic operation F 3 array assigning 5 5 declaring 5 2 implementation 5 7 large 5 7 mapping 5 1 memory 5 11 register file 5 9 A 6 reading 5 3 writing 5 3 atomic block 2 9 attribute map to module A 6 map to registerfiles 5 9 A 6 B bc check design command 3 31 bc use registerfiles variable 5 9 behavioral coding style 1 10 3 1 design attributes 1 19 FFT example D 9 FIFO example B 6 IQ example E 4 memory controller example C 9 model 1 9 refine architectural model 1 10 for synthesis 2 1 block atomic 2 9 hierarchical 2 9 C C line label 3 34 A 9 C C compiler directives A 9 data types 2 43 language elements 2 1 nonsynthesizable constructs 2 34 refine model 2 6 synthesizable subset 2 32 case 3 32 clock 3 2 3 7 clocked thread example 3 4 process 2 26 code simulation specific 2 30 synthesis specific 2 30 coding rules 3 10 cycle fixed 3 12 cycle fixed examples 3 23 finding timing errors 3 31 general examples 3 13 pipelined loop 3 45 superstate fixed 3 12 superstate fixed examples 3 29 terms 3 10 coding rules general 3 11 coding style behavioral 1 10
68. CIONS tabe E bha hak bh hh 2 23 Module Constructor e dot b a odo dus 2 24 Module Implementation File 2 26 Using an Infinite Loop lt we ed ped ink 2 26 Refining the Structure From a High Level SystemC Model 2 28 Creating and Refining Processes nuana naaa 2 28 Converting to a Synthesizable Subset 2 30 Excluding Simulation Specific Code 2 31 SystemC and C Synthesizable Subset 2 32 Nonsynthesizable Subset of SystemC 2 33 Nonsynthesizable C C Constructs 2 34 RelihingDatan gala exer ote Kh GAAN LPS 2 37 Synthesizable Data Types 0 0000 eee 2 37 Nonsynthesizable Data Types 2 38 Recommended Types for Synthesis 2 39 Using SystemC Types ote Ate a 2 41 Bit and Bit Vector Data Type Operators 2 41 Fixed and Arbitrary Precision Data Type Operators 2 42 Using Enumerated Types DA RE Rees 2 43 Using Aggregate Data Types 2 43 Using C TYPES cue c tube anu een eee E eed 2 43 Recommendations About Data Types 2 46 Relining Contt0l s lt 2ceeeetcceee NAN dada le 6 r ke DAGA 2 47 Advanced Refinement Techniques aa 2 48 Refinement Recommendations a 2 49 Behavioral Coding Guidelines Using Clocked Thread Processes
69. CkCkCkCk Ck Ck Ck ckck ck Implementation file for module include systemc h include example h void example entry Code to handle reset out_valid write true outl1 write 0 out2 write 11111111 wait wait required before while loop Behavioral Coding Guidelines 3 47 Infinite while loop with process behavior while true process behavior Specifying a Reset Implementation You can define only a synchronous reset It is possible to force asynchronous reset behavior in the gate level description by specifying a specific implementation using the set behavioral reset command during synthesis The command can also be used to set other properties of the reset behavior of the design Fora discussion of reset implementation see the CoCentric SystemC Compiler User Guide or the man page for the set behavioral reset command Behavioral Coding Guidelines 3 48 Using Variables and Signals Storing data values that are internal to a SystemC process as signals or variables can significantly affect coding flexibility and the quality of results QOR Store intermediate results in variables SystemC Compiler can use one register to store multiple variables if the lifetimes of the variables do not overlap Register sharing reduces design costs Use variables instead of signals whenever possible to store intermediate results because e SystemC Compiler can move variables non l O
70. CoCentric SystemC Compiler Behavioral Modeling Guide Version 2000 11 SCC1 March 2001 Comments E mail your comments about Synopsys documentation to doc synopsys com SYNOPSYS Copyright Notice and Proprietary Information Copyright 2000 Synopsys Inc All rights reserved This software and documentation contain confidential and proprietary information that is the property of Synopsys Inc The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement No part of the software and documentation may be reproduced transmitted or translated in any form or by any means electronic mechanical manual optical or otherwise without prior written permission of Synopsys Inc or as expressly provided by the license agreement Right to Copy Documentation The license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only Each copy shall include all copyrights trademarks service marks and proprietary rights notices if any Licensee must assign sequential numbers to all copies These copies shall contain the following legend on the cover page This document is duplicated with the permission of Synopsys Inc for the exclusive use of and its employees This is copy number Destination Control Statement All technical data contained in this publication is subject to the export control laws of
71. D iq SC CTHREAD entry CLK pos SC CTHREAD generate valid CLK pos watching reset delayed Declare Sc uint 2 Sc uint 7 sc int 12 sc int lt 26 gt tru member functions corrector calc quantizer saturation quantization 0 Inverse Quantization Example E 6 sc int 12 mismatch sc int lt 26 gt intra mult Sc uint 6 inverse scan void reset prediction void reset action sc uint 7 W lookup Gl End of SC MODULI Example E 2 IQ Implementation File VD iq ce implementation file define MAX WAIT FOR ACK 10 define MAX ADDRESS 64 include lt systemc h gt include VD_iq h void VD_iq entry Define local variables sc_uint lt 7 gt next_hit bool ET bool skip inp bool clear inp sc uint 6 mblock intra inp Synthesis attributes synopsys resource RAM A variables intra matrix ram map to module Isi 6 7 synopsys resource RAM B variables non intra matrix ram map to module Isi 6 7 Reset behavior in member function reset action wait Main functionality while true This start signal comes from the stream parser iq block ready write false acknowledge data write false wait until iq start delayed true wait Inverse Quantization Example E 7 Skip inp iq skip read iq clear r
72. Design Figure 1 1 shows the traditional levels of abstraction in system design system architectural level behavioral level and RTL This section describes the traditional levels of abstraction their purpose characteristics and coding style Figure 1 1 System Design Levels of Abstraction IN Untimed functional IN Timed functional Software System Architectural level Nonsynthesizable abstractions h Behavioral c 6 level o G 5 o Q G a G N o Register a transfer level Define and simulate system Partition system Synthesize hardware modules Introduction 1 3 Architectural Level In a typical top down design flow you start with a purely functional model of your system This functional model is a software program that describes the system functionality so that it can be validated This functional model is then mapped into a system architectural model In addition to the system functionality the system architectural model describes its architecture buses memory processors peripherals and so forth A system architectural model illustrated in Figure 1 2 is algorithmic in nature It may be an untimed or timed model The model is an accurate description of the system behavior although the description is abstract The interfaces between modules are transaction oriented and event driven rather than cycle accurate Figure 1 2 Architectural Mo
73. Each SC CTHREAD process must have at least one wait statement Thewait n statement suspends process execution for n active edges of the clock The default value of nis 1 The outputs of an SC CTHREAD process are modeled as being registered When an SC CTHREAD process writes to an output signal the value appears after the next active edge of the clock Using the wait until Statement The wait until cond statement suspends the process until the next active edge If the cond expression is false at the active edge the process remains suspended and the expression is tested at the next active edge When the condexpression is true the process execution resumes at the statement immediately following the wait until statement The wait until argument is an expression for testing the value of a port or signal the port or signal must be type bool or sc bit The expression is evaluated at the next active edge of the clock This is called a delay evaluated expression and it must use the delayed method of the signal For example wait until data ready delayed 1 You can define complex expressions by using equal not equal and and or 88 operators For example wait until data ready delayed nable delayed 0 Behavioral Coding Guidelines 3 3 For further details about using the wait and wait until statements see the SystemC User s Guide Controlling a Clocked Thread Process Hardware typically executes co
74. FPGA Express Frame Compiler General Purpose Post Processor GPP HDL Advisor HDL Compiler Integrator Interactive Waveform Viewer Liberty Library Compiler Logic Model MAX ModelSource Module Compiler MS 3200 MS 3400 Nanometer Design Experts Nanometer IC Design Nanometer Ready Odyssey PowerCODE PowerGate Power Compiler ProFPGA ProMA Protocol Compiler RMM RoadRunner RTL Analyzer Schematic Compiler Scirocco Shadow Debugger SmartModel Library Source Level Design SWIFT Synopsys EagleV Test Compiler Test Compiler Plus Test Manager TestGen TestSim TetraMAX TimeTracker Timing Annotator Trace On Demand VCS VCS Express VCSi VERA VHDL Compiler VHDL System Simulator Visualyze VMC and VSS are trademarks of Synopsys Inc Service Marks TAP in is a service mark of Synopsys Inc All other product or company names may be trademarks of their respective owners Printed in the U S A Document Order Number 37581 000 JB CoCentric SystemC Compiler Behavioral Modeling Guide v2000 11 SCC1 Contents Preface What s New in This Release lt XXIV About This Guides o 00K 20 Oud KA a be aga erbem Bo boss ac adele xxvi Customer SUPPON 0a bee tb Ue EEEET TERREA RENE XXX 1 Introduction Defining Levels of Abstraction in System Design 1 3 Architectural Levels sa Sg wee aoe ote Se Lee 1 4 Untimed Functional Model 1 5 Timed Functional Model e a 1 5 Functional Coding Style
75. Indicate data is ready and write data in 2 consecutive cycles data ready true data a wait data ready false Deassert data ready data b wait Sender initiated handshake Wait until sender is ready wait until gcd ready delayed true Now read data cout lt lt gcd read lt lt endl gcd_seen true wait gcd_seen false wait KOR KKK KK kok k KK kok k RK I RK KK gcd3_main cc simulation executable include systemc h include gcd3 h include gcd3 test h int main f sc signal int data gcd sc signal lt bool gt reset send data data ready gcd ready gcd seen sc clock clock Clock 20 0 5 Using Handshaking in the Circuit and Testbench 6 26 gcd mod G GCD G clock reset data send data data ready gcd ready gcd seen gcd testbench TB TB TB clock send data data ready gcd ready gcd seen gcd reset data sc trace file tf sc create vcd trace file gcd sc trace tf clock signal Clock Sc trace tf reset Reset Sc trace tf send data Send Data Sc trace tf data ready Data Ready Sc trace tf data In sc trace tf gcd ready Out Ready sc trace tf gcd seen Out Seen sc trace tf gcd ready Out sc start 1 return 0 The following steps describe how the input handshaking protocol Works 1 The behavioral block asserts the handshake sign
76. SIZE headp Pointer to head of FIFO Sc uint LOGBUFSIZE tailp Pointer to tail of FIFO int num in buf Number of buffer elements Routine to initialize the FIFO void init num in buf 0 headp 0 tailp 0 Constructor ciro but 4 init void status Status of the FIFO int read To read from the FIFO void write int data To write to the FIFO bool is_full To determine if FIFO is full bool is empty To determine if FIFO is empty int circ buf read if num in buf num in buf return buffer headp Otherwise ignore read request Introduction 1 6 void circ buf write int data if num in buf BUFSIZE buffer tailpt data num_in_buf Otherwise ignore write request bool circ buf is full return num in buf BUFSIZE bool circ_buf is_empty return num_in_buf 0 void circ_buf status GONE XU ETFO as Us if is_empty cout lt lt empty n else if is full cout lt lt full n else cout lt lt neither full nor empty n int main f c r c buf fifo instantiate buffer This is the testbench for the FIFO fif cou cou cou fif cou fif cou fif cout cou cou o status lt lt FIFO write 1 n t lt lt FIFO write 2 n t lt lt FIFO write 3 n o status t lt lt FIFO write 4 n o status t lt
77. Sc out lt sc int 16 gt out imag Sc out bool data req Sc out bool data ready Clock Declaration sc in clk clk Declare implementation functions void fft process Constructor SC CTOR fft module f SC CTHREAD fft process clk pos watching reset delayed true Fast Fourier Transform Example D 9 Example D 4 FFT Implementation File fft cc FFT implementation file include systemc h include fft h KOR KR oko k kok k KK KR kkk k k k I kk k k KK KK Function Definition for butterfly computation OKCKCKCKCKCkCkCkCk A I I I kk OK ke KK f void func_butterfly const sc_int lt 16 gt amp w real const sc int lt 16 gt 6 w imag const sc int 16 5 amp reall in const sc int 16 5 amp imagl in const sc int 16 5 amp real2 in const sc int 16 5 amp imag2 in Sc int 16 amp reall out sc int 16 amp imagl out sc int 16 amp real2 out Sc int 16 amp imag2 out 1 Nariable declarations Sc int 17 tmp reall Sc int 17 tmp imagl Sc int 17 tmp real2 Sc int 17 tmp imag2 Sc int 34 tmp real3 Sc int lt 34 gt tmp imag3 Begin Computation tmp reall reall in real2 in ss 6 105 lt s 5 10 gt lt s 5 10 gt tmp_imagl imagl_in imag2 in lt s 6 10 gt lt s 5 10 gt lt s 5 10 gt tmp_real2 reall_in real2 in lt s 6 10 gt lt s 5 10 gt lt s 5 10 gt
78. Synthesis 2 16 SC MODULE module name Module port declarations sc in port type port name sc outsport type port name Sc in clk port name Internal signal variable declarations sc signal lt signal type signal name Data variable declarations Clocked thread processes Member function declarations Module constructor SC CTOR module name Register processes Declare sensitivity list Define global watching l Signal Data Types A signal s bit width is determined by its corresponding data type Specify the data type as any of the synthesizable SystemC or C data types listed in Synthesizable Data Types on page 2 37 Signals and the ports they connect must have compatible data types Reading and Writing Ports When you read a port itis recommended to use the read and write methods to distinguish ports from variable assignments Example 2 1 shows in bold how to use these methods rather than simple assignments Refining for Behavioral Synthesis 2 17 Example 2 1 Using read and write Methods Na wait address into read read from into port wait wait one clock data tmp memory address get data from memory outof write data tmp write to outof port wait d EOS You need to read or write all bits of a port You cannot read or write the individual bits regardless of its type To select a bit on a port read the port data
79. THREAD that execute whenever their sensitive inputs change A process has a sensitivity list that identifies which inputs trigger the code within the process to execute when the value on one of its sensitive inputs change For simulation you can use any of the process types For synthesis you can use only the SC CTHREAD and SC METHOD processes The SC THREAD process is used mainly for testbenches although the SC CTHREAD and SC METHOD processes can also be used for testbenches Clocked Thread Process The SC CTHREAD clocked thread process is sensitive to one edge of one clock Use a clocked thread process to describe functionality for behavioral synthesis with SystemC Compiler The SC CTHREAD process models the behavior of a sequential logic circuit with nonregistered inputs and registered outputs A registered output comes directly from a register flip flop in the synthesized circuit Method Process The SC METHOD process is sensitive to a set of signals and executes when one of its sensitive inputs change Use a method process to describe a hierarchical behavioral design or register transfer level hardware For information about RTL modeling see the CoCentric SystemC Compiler RTL User and Modeling Guide Refining for Behavioral Synthesis 2 21 Note Although you can create an RTL model in SystemC SystemC Compiler version 2000 05 SCC1 0 does not synthesize RTL models RTL synthesis is planned for a future release of Sy
80. THREAD processes are not supported However access to member variable by only one process is supported Not allowed Replace in all other cases Replace in all other cases Replace Replace Replace Replace in all other cases Write structured code with breaks and continues Replace with structs Replace with local variables Use signals instead of variables for communication between processes Use only nonvolatile variables Refining for Behavioral Synthesis 2 36 Refining Data A pure C C model or a high level SystemC model typically uses native C types or aggregates structures of such types Native C types such as int char bool and long have fixed platform dependent widths which are often not the correct width for efficient hardware For example you might need only a 6 bit integer for a particular operation instead of the native C 32 bit integer In addition C does not support four valued logic vectors operations such as concatenation and other features that are needed to efficiently describe hardware operations SystemC provides a set of limited precision and arbitrary precision data types that allows you to create integers bit vectors and logic vectors of any length SystemC also supports all common operations on these data types During the data refinement step you need to evaluate all variable declarations formal parameters and return types of all functions to
81. Top Level Simulation File B 14 RTL HeaderFile EXER B 16 xxi Example B 9 Example B 10 Example C 1 Example C 2 Example C 3 Example C 4 Example C 5 Example C 6 Example C 7 Example D 1 Example D 2 Example D 3 Example D 4 Example D 5 Example D 6 Example D 7 Example D 8 Example E 1 Example E 2 Example E 3 xxii RTL Implementation File B 17 RTL Top Level Simulation File B 20 Memory Controller Header File C 6 Memory Controller Implementation File C 7 Token Header File ee en RYE Wwe C 8 Memory Controller Command Types C 8 Behavioral Header File Ls C 11 Behavioral Implementation File C 12 Behavioral Synthesis to Gates Script C 13 FFT Functional Header File D 4 FFT Functional Description File D 5 FFT Header mE E Pn ee D 9 FFT Implementation File D 10 Behavioral Synthesis to Gates Script D 16 FFT Testbench Source D 18 FFT Testbench Sink ze aet oet reb bes D 20 FFT Testbench Top Level Model D 21 IQ Header File cu e e x XR C E 5 IQ Implementation File a E 7 Behavioral Synthesis to Gates Script E 16 Preface This preface includes the following sections e Whats New in This Release About This Guide Custo
82. aking in the Circuit and Testbench 6 43 Figure 6 12 Correct Loop Pipeline Without Handshake Signal De assertion Iteration 1 0 Iteration i 1 Iteration i 2 send_data write TRUE Initiation interval 1 send_data write TRUE 4 send data write TRUE After loop exit send data write FALSE These two writes do not cause send data to toggle but testbench assumes a toggle For coding rules about pipelining loops see Pipelining Loop Rules on page 3 45 Using Handshaking in the Circuit and Testbench 6 44 Compiler Directives This appendix provides a list of the compiler directives you can use with SystemC Compiler and it tells you where you can find further details about using them Compiler Directives A 1 Synthesis Compiler Directives To specify a compiler directive in your SystemC code insert a comment in which the first word is either synopsys Or snps You can use either a multiple line comment enclosed in and characters or a single line comment beginning with two slash characters Table A 1 lists the compiler directives in alphabetical order Table A 1 SystemC Compiler Compiler Directives Compiler Directive Details snps inout_param page A 5 snps line_label string page A 3 snps map to operator dw part page A 3 snps preserve function page A 4 snps resource name variables var page A 6 map to modul
83. al SINK1 in imag out imag SINK1 reset reset Fast Fourier Transform Example D 21 SINK1 CLK clock Sc start clock 1 return 0 Fast Fourier Transform Example D 22 Inverse Quantization Example This appendix provides an inverse quantization IQ example that shows you a complex behavioral model This model uses many member functions to describe the functionality which makes it easier to understand the functional complexity This chapter contains the following sections IQ Description e Q Behavioral Model Inverse Quantization Example E 1 IQ Description The IQ is a block in an MPEG 2 that contains subblocks for inverse quantization arithmetic saturation and mismatch control as shown in Figure E 1 Figure E 1 IQ Blocks Inverse Quantization Arithmetic Mismatch Control W w v u Quant scale code Inverse Quantizer Inverse Quantization Example E 2 IQ Data Flow Figure E 2 shows the IQ arithmetic block and the data flow into the saturation and mismatch control blocks Figure E 2 IQ Data Flow f input f input table f input D HOO Input Output into RAM Mismatch Control m Saturation Inverse Quantization f input Arithmetic Inverse Quantizer Inverse Quantization Example E 3 IQ Block Diagram Figure E 3 shows the IQ block diagram Figure E 8 IQ Block Diagram Saturation gt Mismatch 1
84. al send data high to indicate that it can process new data It waits until it sees a data ready signal from the testbench When it sees the data ready signal asserted it reads the first piece of data 2 In the next cycle the module de asserts low the send data signal and reads the second piece of data 3 The behavioral block proceeds to compute the GCD of the two numbers it has read This computation can take an indeterminate but finite number of cycles 4 This process repeats each time the behavioral block is ready to accept new data Using Handshaking in the Circuit and Testbench 6 27 The following steps are used to implement the output handshake protocol 1 The behavioral block asserts the gcd ready signal to indicate that it can send new output data and writes the output to the gcd port The testbench waits until it sees the gcd ready signal reads the output on the gcd port and asserts high the gcd seen signal The behavioral block waits until it sees the gcd seen signal and de asserts low the gcd ready signal The testbench also de asserts the gcd seen signal This process repeats each time the behavioral block can send new output data Using Handshaking in the Circuit and Testbench 6 28 Two Way Handshake Initiated From Testbench Figure 6 6 shows a timing diagram for a GCD behavioral block that uses two way handshake protocols to get data and to write data out The testbench initiates the inp
85. ample 6 7 This method eliminates the extra wait statement required to exit the while loop hierarchy and it produces the timing diagram shown in Figure 6 9 Example 6 7 Fast Two Way Handshake Using wait until new data available write 0 wait until rdy for data delayed 0 new data available write 1 data write wait Figure 6 9 Timing Diagram Using wait until ready for data data Old data New data new data available EXT Using Handshaking in the Circuit and Testbench 6 39 Using a Pipeline Handshake Protocol Loop pipelining has two restrictions that affect how handshake protocols are implemented 1 The pipelined loop can contain only unrolled loops Therefore pipelined loops use only one way handshake protocols because two way handshake requires a rolled loop 2 During execution iterations of a pipelined loop overlap You cannot have a signal write operation in one loop iteration within the same clock cycle as a write operation to the same signal in any overlapping iteration Example 6 8 shows in bold a pipelined loop with a handshake signal assertion in the first clock cycle of the loop This is followed by a de assertion of the same signal in the next clock cycle of the loop Example 6 8 Incorrect Loop Pipeline With Handshake while true Loop to pipeline with handshake for int i 0 i lt 3 itt send data write true wait send data write false
86. and unsigned char address unsigned char data 4 Define the operator inline bool operator const token rhs const return command rhs command amp amp address rhs address amp amp data 0 rhs data 0 amp amp data 1 rhs data 1 amp amp data 2 rhs data 2 amp amp data 3 rhs data 3 hi Example C 4 Memory Controller Command Types memc types h ifndef MEMC TYPES _ define MEMC TYPES _ enum command t NOP RDBYT WTBYT WTBLK endif Memory Controller Example C 8 Refined Behavioral Model Refining the functional simulation model to a behavioral synthesizable model means clarifying the data types and the communication protocol The process type is changed to a SC CTHREAD clocked thread process instead of an SC METHOD process Data Types To refine the abstract data types in Example C 3 to specified bit width data types Example C 5 shows e The into and outof data ports are declared as Sc in sc uint 8 gt and sc out sc uint 8 gt types instead of the abstract token type e The memory is declared as an array of type sc int 8 instead of an array of type unsigned char Communication Protocol Figure C 1 illustrates the data flow into and out of the memory controller Memory Controller Example C 9 Figure C 1 Behavioral Input Data Flow WTBLK RDBYT WTBYT 9 E E G E E E E E E o o o i cycle boundari
87. andshake uses an acknowledgement signal rather than using a fixed latency like a one way handshake Two Way Handshake Initiated From Behavioral Block Figure 6 5 shows a timing diagram for a GCD behavioral block that uses two way handshake protocols to get data and to write data out The GCD block initiates the handshake with the testbench Example 6 3 shows the code for the GCD block the testbench and the main routine for simulation Note The number of cycles needed to compute the GCD is not fixed because it depends on the value of the two numbers for which the GCD is computed Therefore this example requires the use of handshaking Using Handshaking in the Circuit and Testbench 6 21 Figure 6 5 Two Way Handshake Protocol send_data data ready data ged ready ng Y PON P i T gcd seen EE m Number of cycles to perform GCD is dependent on the input value gcd Using Handshaking in the Circuit and Testbench 6 22 Example 6 8 Two Way Handshake Protocol From GCD Block gcd3 h Two way handshake header fil SC MODULE gcd mod Ports sc in clk clk Clock input Sc in lt bool gt reset Reset input Sc in lt int gt data in Port for getting data Handshake signals Sc out bool send input Request input Sc in lt bool gt data ready Data is ready sc out lt bool gt output ready Output is ready sc
88. automatically places them in non overlapping address spaces in the memory Using Arrays Register Files and Memories 5 12 Multiple Arrays Accessing One Memory You can use one memory for multiple arrays Example 5 12 shows two arrays mapped to one memory resource The memory must be as large as or larger than the combined size of the arrays mapped to it Example 5 12 Multiple Arrays Accessing One Memory Mapping arrays to a RAM void my proc sc int 8 amem 256 sc int 8 bmem 256 synopsys resource RAM A variables amem bmem map to module raml s d Ef When you map multiple arrays to one memory SystemC Compiler automatically places them in non overlapping address spaces in the memory Figure 5 2 shows a representation of the address space mapping of Example 5 12 with two arrays accessing the same memory resource Address space is allocated in the order the variables are declared Figure 5 2 Multiple Array Address Space Mapping 31 0 0 amem 255 59 lbmem 511 Using Arrays Register Files and Memories 5 13 Exploring Alternative Memory Types You can explore the tradeoffs of using various memory types such as single port dual port or pipelined memories If the synthetic library descriptions are available for each memory type you can explore the impact of the different memory types by changing only the map to module attribute as shown in bold in Example 5 13 Example 5 13 Changing Me
89. avior of the block is described in a cycle accurate fashion Therefore wait statements are inserted into the algorithmic description to clearly delineate clock cycle boundaries and when I O happens Unlike register transfer level RTL descriptions the behavior of the block is still described algorithmically rather than in terms of a finite state machine FSM and a data path Therefore behavioral descriptions are more compact and easier to understand and because of the higher level of abstraction they simulate faster than RTL Figure 1 3 shows a block diagram for a behavioral model Figure 1 3 Behavioral Model CPU Memory Clock um Driver WO I F Storage Bus I F Bus Clock Driver arbiter Bus I F Introduction 1 9 Behavioral Coding Style The general characteristics of the behavioral coding style for synthesis are the following The behavior is described like an algorithm a software program and functions can be used to manage complexity Although the initial model may have float or integer data types you need to refine these types to synthesizable types described in Recommended Types for Synthesis on page 2 39 You specify the I O protocol of the design by defining in which clock cycle the I O happens Note that only the I O not the operations described in the algorithm is bound to clock cycles It uses the synthesizable subset of the SystemC language d
90. ayed true KOR KKK KK OK KK I KK KK OK gcd4 cc behavioral module implementation file include systemc h include gcd4 h void gcd mod gcd algo f int a b Two variables to compute gcd int c The GCD Reset operations gcd out 0 data seen false output ready false wait Using Handshaking in the Circuit and Testbench 6 30 while ANG true First get the two inputs using sender initiated handshake gt CU wait until data ready delayed Read data and assert data seen data seen true a data in read wait 2 b data in read data seen false wait Now do the algorithm c do gcd a b Now write the output using sender initiated handshake output ready true gcd out c wait Two cycles for new data to arrive wait until output s output ready false wait n delayed gcd mod do gcd int a int b int temp if a 0 amp amp b 0 while b 0 while a gt b a a b wait return a true Using Handshaking in the Circuit and Testbench 6 31 kok k kok k kok kok k kok k kok k kok kk X kk kk gcd4 test h testbench header fil SC MODULE testbench l sc in clk clk sc in lt bool gt data seen sc out lt bool gt data ready sc in lt bool gt gcd ready sc out lt bool gt gcd seen sc in lt int gt gcd
91. b Memory Controller Example C 13 Memory Controller Example C 14 Fast Fourier Transform Example This appendix provides a 16 point fast Fourier transform FFT example that shows you a functional floating point model and a behavioral fixed point model that uses numerous arrays and bit manipulations This chapter contains the following sections e FFT Description e FFT Functional Model FFT Behavioral Model e FFT Testbench Fast Fourier Transform Example D 1 FFT Description Figure D 1 shows the input and output ports and data types for the 16 point FFT Figure D 1 FFT Ports and Data Types C data req data ready gt data valid data ak K out real Fe out imag lt gt FFT Computation The FFT block computes a 16 point FFT on a sequence of complex inputs by using a radix 2 decimation in frequency algorithm The input data is read as a signed 16 bit fixed point number with 10 fractional bits Twiddle factors and output values are in the same representation Internally in the block computation is performed with fixed point arithmetic The input samples and output transformations are externally inferred as 16 bit integers Fast Fourier Transform Example D 2 Refining From Functional to Behavioral The floating point functional version of the FFT was developed to prove the algorithm and verify the results working at the highest level of abstraction To use behavioral synthesis the floating point
92. ble clock period clock period minus any margin Example 3 23 causes an HLS 52 error during schedule command execution See Finding the Cause of Timing Dependent Coding Errors on page 3 31 Example 3 23 Error in Use of Cycle Fixed Mode Coding Rule 2 while e a b c d a d wait 3 insufficient wait statements for condition evaluation e a b c d a a wait 3 insufficient wait statements after loop Behavioral Coding Guidelines 3 26 Example 3 24 Correct Cycle Fixed Mode Coding Rule 2 while e a b c d a d wait 7 e dat be TA a GAN wait 7 Example 3 25 shows a while loop with a loop iteration condition that takes seven clock cycles to evaluate I O statements are not allowed during the clock cycles required for condition evaluation The write statement in this example is a coding error To correct this error insert wait statements as shown in bold in Example 3 26 Example 3 25 causes an HLS 52 error during schedule command execution Because the coding rule violation is directly related to operator timing the be check design command cannot catch this coding rule violation See Finding the Cause of Timing Dependent Coding Errors on page 3 31 Example 3 25 Error in Use of Cycle Fixed Mode Coding Rule 2 Write while e a b c d a d wait 3 insufficient wait statements for condition evaluation e a b wait 2 real ou
93. butes 1 19 1 21 DesignWare components 4 11 do while loop 3 33 3 36 E else 3 32 enumerated data type 2 43 equality operation F 3 example architectural FIFO 1 5 B 2 behavioral FFT D 9 FIFO 1 11 B 6 IQ E 4 memory controller C 9 clocked thread 3 4 cycle fixed coding rules 3 23 fast handshake 6 36 FFT D 1 FIFO B 1 functional FFT D 4 memory controller C 5 general coding rules 3 13 IQ E 1 local memory 5 11 memory controller C 1 one way handshake 6 4 6 12 RTL FIFO 1 15 B 15 superstate fixed coding rules 3 29 testbench FIFO B 11 B 20 two way handshake 6 21 6 29 expression F 2 F fast handshake 6 36 FFT behavioral example D 9 example D 1 functional example D 4 testbench example D 17 FIFO architectural example 1 5 B 2 behavioral example 1 11 B 6 example B 1 RTL example 1 15 B 15 testbench example B 11 for loop 3 33 3 36 unrolled 3 37 function member 2 23 4 2 IN 3 nonmember 4 4 preserve 4 4 process 2 21 using 4 1 functional model 1 4 timed 1 5 untimed 1 5 G global reset 3 46 H handshake constrain cycles 6 19 fast 6 36 loop pipelining 6 40 one way protocol 6 4 protocols 6 1 6 3 signals 6 3 two way protocol 6 21 hardware allocation F 3 behavioral synthesis process 2 21 header file module 2 13 hierarchical block 2 9 VO read and write 3 7 schedule mode 3 8 specify 3 7 if 3 32 ignore array precedences command 5 15 implementation file module 2 26 infinite loop 2
94. c in lt int gt data in sc in lt bool gt reset Sc out lt int gt data out Sc out lt bool gt full sc out lt bool gt empty Internal signals Sc signal lt int gt buf0 buf0 next sc signal lt int gt bufl bufl next sc signal lt int gt buf2 buf2 next sc signal lt int gt buf3 buf3 next sc signal lt sc uint lt LOGBUFSIZEPLUSONE gt gt num in buf num in buf next sc signal lt bool gt full next empty next sc signal lt int gt data out next Declare processes void ns logic Next state logic void update regs Update all registers void gen full Generate a full signal void gen empty Generate an empty signal Constructor SC CTOR circ buf First In First Out Example B 16 SC METHOD ns logic sensitive lt lt read fifo lt lt write fifo data in xx num in buf zal SC sensitive pos clk SC METHOD gen full THOD update regs sensitive num in buf next SC METHOD gen empty sensitive num in buf next bi Example B 9 RTL Implementation File fifo rtl cc implementation file include systemc h include fifo rtl h void circ buf gen full if num in buf next read BUFSIZI GI full next 1 else full next 0 void circ buf gen empty if num in buf next read 0 empty_next 1 else empty_next 0 void circ_buf update_re
95. constant index 5 taig a i read nonconstant index i Example 5 4 shows in bold declaring a variable array and writing to it with a constant index and a nonconstant index Example 5 4 Writing to a Variable Array sc int 8 a 16 sc int 8 temp sc int 4 i a 5 temp write constant index 5 temp write nonconstant index i ali Using Arrays Register Files and Memories 5 3 Reading From and Writing to Signal Arrays You can declare an array of signals as sc signal sc out or sc in types Use signal arrays to communicate data between different processes in your design Access signal arrays in the same way that you access l O ports and other signals in your design and adhere to the coding style rules described in Behavioral Coding Style Rules on page 3 10 As with variable arrays SystemC Compiler creates significantly less hardware for decoding a constant index Example 5 5 shows in bold declaring a signal array and reading from it with a constant and nonconstant index Example 5 5 Reading From a Signal Array sc signal lt sc int lt 8 gt gt a 16 sc int 8 temp sc int 4 i temp a 5 read read constant index 5 temp a i read read nonconstant index I Example 5 6 shows in bold declaring a signal array and writing to it with a constant index and a nonconstant index Example 5 6 Writing to a Signal Array sc signal lt sc int lt 8 gt gt a 16
96. cribed in the following sections to determine whether behavioral or RTL synthesis is applicable Identifying Attributes Suitable for Behavioral Synthesis Look for the following design attributes when identifying a hardware module that is suitable for behavioral synthesis with SystemC Compiler e Itis easier to conceive the design as an algorithm than as an FSM and a data path for example an FFT filter IQ or DSP e The design has a complex control flow for example a network processor The design has memory accesses and you need to synthesize access to synchronous memory Introduction 1 19 Applications that are suitable for behavioral modeling and synthesis are Digital communication applications such as cable modems cellular phones cordless phones two way pagers wireless LANS satellite DSPs and XDSL modems e mage and video processing applications such as digital cameras printers set top boxes 3 D graphic devices and video capture devices Networking applications such as ATM switches fast networking switches and packet routers Digital signal processing applications such as filters codecs IQ IDCT and channel equalizers e Computers applications such as cache controllers hardware accelerators and fixed point arithmetic units Introduction 1 20 Identifying Attributes Suitable for RTL Synthesis Some designs are more appropriate for RTL synthesis than for behavioral synthesis The fol
97. cuit and Testbench 6 16 gcd mod G GCD G clock reset data data ready gcd ready gcd testbench TB TB TB clock data ready gcd ready gcd reset data sc trace file tf sc create vcd trace file gcd sc trace tf clock signal Clock Sc trace tf reset Reset sc trace tf data ready Data Ready Sc trace tf data In sc trace tf gcd ready Out Ready sc trace tf gcd ready Out sc start 1 return 0 The following steps describe how the input handshaking protocol works 1 The testbench asserts the data ready signal high to indicate that it can send new data in READ LATENCY cycles In this example READ LATENCY is 2 2 The behavioral block waits until it sees the data ready signal Then it waits a further READ LATENCY cycles before it can read the data 3 Atthe end of this wait the behavioral block reads two consecutive values from the data port 4 This process repeats each time the testbench can send the next data set The steps for implementing the output handshake protocol are identical to the steps in Example 6 1 on page 6 6 Using Handshaking in the Circuit and Testbench 6 17 Looking at the testbench code in Example 6 2 you see that the handshaking for the testbench is done in the do handshake function To send data to the behavioral block the testbench asserts data ready high and then waits READ LATENCY cycles This models the time it takes the
98. d Signals liliis 2 16 Simple Multiplier WO Protocol 3 7 Rolled and Unrolled for Loops 3 39 Loop Latency and Initiation Interval 3 45 LOOP EXIT e used LAAN deeper dd Ga 3 45 Comparing Signal Use and Data Flow 3 51 xiii Figure 3 6 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure 6 6 Figure 6 7 Figure 6 8 Figure 6 9 Figure 6 10 Figure 6 11 Figure 6 12 Figure C 1 Figure D 1 Figure E 1 Figure E 2 Figure E 3 Xiv Variable Use and Data Flow Register File Architecture Multiple Array Address Space Mapping Memory Access Time Specification Bit Slice ACCESSES coo s ddd pe aa a One Way Handshake Protocol Testbench Initiated One Way Handshake Constraining Input Handshake Signals Constraining Output Handshake Signals Two Way Handshake Protocol Two Way Handshake Protocol Timing Diagram of while Loop Timing Diagram Using if else Timing Diagram Using wait until Incorrect Loop Pipeline With Handshake Correct Loop Pipeline With Extended Initiation MONA maana oa eid Dana Bhari ate e NAA bd Correct Loop Pipeline Without Handshake Signal De asserlion be Red NEN k
99. default This strategy means e Shorter elaboration times e Serial execution of each iteration Less area e Shorter scheduling times Rolled for loops have their own level of hierarchy for scheduling This means that the scheduled loop is treated as a subdesign of the entire design Unrolling for Loops You can force a for loop to unroll by using the synopsys unroll compiler directive Place the synopsys unroll compiler directive as a comment in the first line in the body of the for loop as shown in bold in Example 3 40 Example 3 40 Unrolled for Loop Compiler Directive for int i20 i lt 8 itt synopsys unroll loop operations Behavioral Coding Guidelines 3 37 The advantages to unrolling are the following e The iterations are performed in parallel to reduce latency if there are no data dependencies Loop overhead is eliminated reducing loop counting hardware e Execution of consecutive loop iterations has the potential to overlap e Execution of operations before and after the loop can overlap with loop execution e Constants can propagate to the operations in the loop body Data dependencies between loop iterations allow overlapping of their schedules Unrolling for loops can sometimes improve the quality of scheduling by reducing latency but it can also produce longer SystemC Compiler runtimes and larger designs Example 3 41 shows an unrolled for loop Example 3 41 Unrolled for Loo
100. del CPU Memory VO EEE Storage Bus arbiter Introduction 1 4 Untimed Functional Model An untimed functional model is an executable specification of the system The system is described as a set of processes communicating through abstract communication links The system may be described in a sequential form concurrent form or a combination of both Time is expressed as causality Timed Functional Model A timed functional model is a performance model at a high level of abstraction The processes and communication links in the untimed functional model are assigned execution times specified in clock cycles or actual time Functional Coding Style A functional model uses a coding style that is abstract concise easy to write and functionally accurate You can use the SystemC classes and data types or you can code the functionality by using only the C C language Example 1 1 shows a functional model of a simple first in first out FIFO circular buffer The complete description and set of files for the available in Appendix B First In First Out Example Introduction 1 5 Example 1 1 FIFO Functional Model fifo cc executable specification This model works for a FIFO with a size that is a power of 2 Ay include systemc h define BUFSIZE 4 define LOGBUFSIZE rj N struct circ buf int buffer BUFSIZE The FIFO buffer Sc uint LOGBUF
101. dependent and not determinable at compile time A while loop is always rolled and has its own level of hierarchy Example 3 36 shows the structure of a while loop Example 3 36 Structure of a while Loop SystemC while cond operations Using an Infinite while Loop An infinite while loop is one with a condition that is always true as shown in Example 3 37 SystemC Compiler requires that you enclose a clocked thread process body within an infinite while loop Example 3 37 Infinite while Loop while true operations of clocked thread Behavioral Coding Guidelines 3 35 Using do while Loops You can use the do while loop construct in situations where you want to guarantee that the loop is executed once before evaluation of the while condition test Example 3 38 shows the structure of the do while loop Example 3 38 Structure of do while Loop do operations while cond Using for Loops A for loop executes a certain number of iterations by using an iteration counter as shown in Example 3 39 Example 3 39 for Loop for int i 0 i lt 7 i 4 operations Rolled Versus Unrolled Loops SystemC Compiler keeps all loops rolled by default An unrolled loop replicates the code body for each loop iteration If you unroll a loop it is no longer considered a loop during synthesis Behavioral Coding Guidelines 3 36 Rolled for Loops SystemC Compiler keeps for loops rolled by
102. dule port declarations sc in port data type port name sc out port data type port name sc in clk port name Mandatory sc in lt bool gt reset Highly recommended Signal variable declarations Data variable declarations Clocked thread processes Member function declarations Module constructor SC CTOR module name Register processes Declare sensitivity list Define global watching l Port Data Types Ports connectto signals and like signals have a data type associated with them For synthesis declare each port as one of the synthesizable data types described in Synthesizable Data Types on page 2 37 An sc in clk is a special port that connects to the clock signal to trigger one or more SC CTHREAD processes Each SC CTHREAD process requires one sc in clk port You can use the same clock port for all processes in a module or you can declare a separate sc in clk port for each SC CTHREAD process Refining for Behavioral Synthesis 2 15 Internal Signals Modules use ports to communicate with other modules Internal signals are used by processes to communicate with other processes within the same module as shown in Figure 2 7 Figure 2 7 Processes and Signals sc in clk Ports Process Process Signals e Signal Syntax Declare signals by using the syntax shown in bold in the following example Refining for Behavioral
103. dy low Using Handshaking in the Circuit and Testbench 6 34 4 Because the testbench needs to see the data seen signal before it sends the next piece of data which takes two cycles the behavioral module waits two cycles before reading the second piece of data and it de asserts low the data seen signal to indicate that it has finished reading the data set 5 The behavioral block proceeds to compute the GCD of the two numbers it has read This computation can take an indeterminate but finite number of cycles 6 This process repeats each time the testbench has the next data to send to the behavioral module The output handshake protocol is the same as Example 6 3 on page 6 23 which initiates the output handshake from the behavioral module Using Handshaking in the Circuit and Testbench 6 35 Fast Handshaking Example 6 5 shows a fragment of code for a behavioral block that needs to wait for a ready for data handshake signal before it can assert a new data available signal and write the new data in the same clock cycle General coding rule 5 General Coding Rule 5 on page 3 20 requires a wait statement shown in bold immediately after a while loop Example 6 5 Two Way Handshake Using a while Loop new data available write 0 while ready for data read 0 wait wait Wait required after loop new data available write 1 data write wait Therequirement of general coding rule
104. e memory module name memory address ports port name snps resource name variables var page A 6 map to registerfiles TRUE snps return port name port page A 4 snps synthesis off and page A 7 snps synthesis on snps translate off and Use synthesis off and synthesis on snps translate on instead of translate off and translate on snps unroll page A 8 Compiler Directives A 2 line label Use the line label compiler directive to label a loop or a line of code In SystemC Compiler generated reports the label is reflected in the report hierarchy my module2 entry Synopsys compiler directive while true snps line label reset loop2 wait wait See Labeling a Loop on page 3 34 map to operator Use the map to operator compiler directive to use a standard DesignWare synthetic operator to implement a function Place the compiler directive in the first line of the function body sc int lt 16 gt my mult const sc int lt 8 gt A const sc int lt 8 gt B snps map to operator MULT2 TC OP snps return port name P Function code block return A B See Using DesignWare Components on page 4 11 Compiler Directives A 3 return port name When you use the map to operator compiler directive the name of the return port if any is Z by default You can override the name by using the return port name compiler
105. e quantizer Inverse discrete cosine transformer Controller MPEG Video Decoder Motion compensation Specify the Detailed Architecture After the top level architecture is complete you can take a closer look at each block of the design to decide if you want to apply the same principles of structure refinement to all the blocks For example you might want to decompose the MPEG stream parser block into a slice decoding SD block and a header decoding HD block You might also want to insert buffers B between the IQ and IDCT and between the IDCT and MC This further refines your architecture and creates Output port Video picture hierarchy in your design as shown in Figure 2 4 Figure 2 4 MPEG Decoder Detailed Architecture 1010 1010 Input port Slice Inver Input decoding Inverse discrete buffer Header quantizer cosine decoding transformer Motion compensation Controller p MPEG Video Decoder Output port Video picture Continue this type of structure refinement until you are satisfied with the final architecture In your final architecture all blocks their ports and all communication resources are defined Though it is not required to have the communication protocols defined at this stage itis highly recommend that you define the bus pro
106. e m O A CS RP 5 11 Multiple Arrays Accessing One Memory 5 13 Exploring Alternative Memory Types 5 14 Accessing Register Files and Memories Efficiently 5 15 ACCESSING Memory zs aaa eee eee en 5 16 Allowing for Vendor Memory Timing aa 5 17 Eliminating Redundant Memory Accesses 5 18 Accessing Bit Slices of Memory Data 5 19 Using Handshaking in the Circuit and Testbench Using Handshake Protocols 3d wa date heehee kdo dea xus 6 3 Using One Way Handshake Protocols 6 4 One Way Handshake Initiated From Behavioral Block 6 4 One Way Handshake Initiated From Testbench 6 12 Constraining the Width of Handshake Strobes 6 19 Using Two Way Handshake Protocols 6 21 Two Way Handshake Initiated From Behavioral Block 6 21 Two Way Handshake Initiated From Testbench 6 29 Pasimahashakinaa paanakin te bo ener eine eae bataan 6 36 Using else vs wen ier diet REDE Pea qas viU oe IE 6 37 Using Wai Uni ass a ER ik ke ee oq e b as etse qid 6 39 Using a Pipeline Handshake Protocol anaana 6 40 Appendix A Compiler Directives Synthesis Compiler Directives ees A 2 lie Tabelle 2G R A ar a S CER PRAG EE CS A 3 Map Jo operator seus or up rowel ae d RUE SER god A 3 return_port name 25 5 bbs S xar es e bsec bns A 4 preserve TUNGIION Rar RR ECC Rl ond
107. e preserve function compiler directive in the first line in the block of code that defines the nonmember function as shown in bold in Example 4 3 Example 4 3 Nonmember Preserved Function Declaration my module h header file SC MODULE my module SC CTOR my module SC CTHREAD entry clk pos ie my_module cc implementation file include my_module h Define my_func int my func int y int amp x synopsys preserve function X X y return x void my module entry TINE ug by Ce c my func a b Using Functions and DesignWare Components 4 9 Using Reference Parameters in Preserved Functions SystemC Compiler maps nonconstant C reference parameters to the output ports of the design corresponding to a preserved function If the preserved function contains a read from a reference parameter SystemC Compiler assumes that you are trying to read an output port and issues an error message unless you use the inout param compiler directive shown in bold in Example 4 4 Notice that the inout param is placed immediately after the reference parameter and is inside the parentheses The preserve function directive is the first line in the function body Example 4 4 Preserved Function With Reference Parameter void my func int y int amp x snps inout param snps preserve function X X ty When you use the inout_param compiler directive SystemC Compiler
108. ead clear inp wait if iq write block read true offset else offset MAX ADDRESS 0 if skip inp false Sample data that are b mblock intra inp macroblock intra alternate scan inp quantizer scale code inp quantizer scale code q scale type inp intra dc precision inp block count inp lock constant mb lock intra read mblock intra inp alternate scan read read q scale type read intra dc precision read block count read Initial values for a block mismatch control 0 Special treatment for dc values in intra pictures see 7 4 1 in MPEG spec if dct diff inp dct diff inp dct size inp pet intra mult Saturation Rc saturation 0 Mismatch control if f t 0 1 mismatch control f out tt Output assignment f addr out 0 f addr write f addr out f write f out f valid write true macroblock intra true f mat f addr outtoffset current address else 1 dct dc differential read dct dc size read Imismatch control fous If we don t have a intra block current address 0 Inverse Quantization Example E 8 wait Pipeline that does the main computation main loop while 1 f valid write false acknowledge data write false Wait for a valid signal for end of the block wait until valid data delayed true wait Checking if
109. ective is placed in the first line of the function body void my func int y int amp x snps inout paran snps preserve function X X y When you use the inout_param compiler directive SystemC Compiler creates an input port x and an output port x for the x reference parameter so it can perform the read and the write Compiler Directives A 5 resource Use the resource compiler directive and the map to module attribute in your code to specify the array that is to be mapped to a memory See Mapping Arrays to Memories on page 5 11 while true sc_int lt 32 gt amem 16 synopsys resource RAM A variables amem map to module my mem model array amem mapped to a single RAM amem i ser in a amem j Use the synopsys resource compiler directive and the map_to_registerfiles attribute in your code to specify the array thatis to be mapped to a register file See Mapping Arrays to Register Files on page 5 8 Compiler Directives A 6 sc int 32 mem 160 synopsys resource R1 variables mem map to registerfiles TRUE The following are all mapped to memory Write to mem mem 0 a mem 1 b and so forth Read from mem a mem 0 b mem 1 l and so forth synthesis off and synthesis on Use the synthesis off and synthesis on compiler directives to isolate simulation specific code and prevent the code from being interpreted for synthesi
110. ed One Way Handshake data ready i T NEN o data a b y 4 E gcd ready MB i mi e e oO Number of cycles to perform GCD is dependent on the input value Using Handshaking in the Circuit and Testbench 6 12 Example 6 2 Behavioral Block Responding to One Way Handshake gcd2 h header file define READ LATENCY 2 define WRITE LATENCY 3 SC MODULE gcd mod Ports sc in clk clk sc in bool reset sc in int data sc in lt bool gt data ready sc out bool gcd ready sc_out lt int gt gcd Process void gcd_algo Internal functions Function to compute gcd int do_gcd int a int b SC_CTOR gcd_mod Clock inpu Reset inpu Port to get data Handshake signal to indicate input ready Handshake signal to indicate output is ready Port to send GCD value ct ct Process to do GCD algorithm SC CTHREAD gcd algo clk pos watching reset delayed l true kok k kok kok k kok k kok k kok kok KAKA kk ke e x gcd2 cc implementation file include systemc h include gcd2 h void gcd mod gcd algo f int a b Two variables to compute GCD int c The GCD Reset operations gcd write 0 gcd ready write false Using Handshaking in the Circuit and Testbench 6 13 wait while true First get the two inputs us
111. ed for every next iteration as i i len 2 while i lt N index i index2 i len reall_out real index real index2 imagl_out imag index imag index2 Fast Fourier Transform Example D 13 real index2 real index real index2 imag index2 imag index imag index2 real index reall out imag index imagl out i i len xx 1 wait j 1 windex incr 1 KOR KR KKK RK KKK I kkk RK kok k kkk k k Remaining Passes Loop OKCKCKCKCkCkCK Ck kk kk I RK KK KK eK This loop executes N 2 times at the first stage N 2 times at the second and once at last stage while j lt len i J while i lt N index i index2 i len Read in the data and twiddle factors w real W real windex w imag W imag windex reall in real index imagl in imag index real2 in real index2 imag2 in imag index2 Call butterfly computation function func butterfly w real w imag reall in imagl in real2 in imag2 in reall out imagl out real2 out imag2 out Store back the results real index reall out imag index imagl out real index2 real2 out imag index2 imag2 out i i len xx 1 windex windex incr Fast Fourier Transform Example D 14 j stagett incr incr lt lt 1 bits_i 0 bits_index 0 i 0 cout lt lt Writing the transform values lt l
112. er Subscript variable expr Function all name expr list Postfix increment Ivalue Postfix decrement Ivalue typeid Type identification typeid type const cast Type conversion const cast lt type gt expr static cast Type conversion static cast type expr Prefix increment lvalue Prefix decrement value x Bitwise NOT expr Logical NOT lexpr Unary minus expr Unary plus expr amp Address of amp expr parameter passing only Type conversion type expr i Multiply expr expr Divide expr expr Expressions and Operations F 4 Yo Modulo remainder expr Yo expr Table F 1 Operator Precedence continued Operator Function Use Add expr expr Subtract expr expr lt lt Bitwise shift left expr lt lt expr gt gt Bitwise shift right expr gt gt expr lt Less than expr lt expr lt Less than or equal expr lt expr gt Greater than expr gt expr gt Greater than or equal expr gt expr Equality expr expr Inequality expr expr amp Bitwise AND expr amp expr Bitwise XOR expr expr Bitwise OR expr expr amp amp Logical AND expr amp amp expr Logical OR expr expr B Assignment value expr Compound assignment value expr and similar for od gt gt amp each operator Conditional expression expr expr expr Comma expr expr Expressions and Operation
113. error in cycle fixed scheduling mode To correct this error insert a wait statement as shown in bold in Example 3 4 Example 8 3 Error in Use of General Coding Rule 1 for int i 0 i 4 itt e s la c dd 1 Error no wait in loop Example 3 4 Correct General Coding Rule 1 for int i 0 i gt 4 i W eS tha Pe e d Ag wait Behavioral Coding Guidelines 3 13 General Coding Rule 2 Place at least one wait statement between successive writes to the same output Example 3 5 shows a loop without a wait statement between two successive writes In either cycle fixed or superstate fixed scheduling mode SystemC Compiler removes the first signal write because it is eclipsed by the second write It issues an SCC 142 warning during execution of the compile systemc command Therefore when you violate this coding rule no error is issued when the bc check design Or schedule command is executed However the first write to the output is not executed To correct this situation insert a wait statement as shown in bold in Example 3 6 Example 3 5 Error in Use of General Coding Rule 2 for int i 0 154 i real out write e i Error no wait between successive writes real out write e i 1 wait Example 3 6 Correct General Coding Rule 2 e lay c d for int i 0 154 itt real_out write e i wait real out write e i i wait Beha
114. es Clock Placement Notice the placement of wait statements in the implementation file Example C 6 that implicitly define the control Behavioral Model Example C 5 shows the header file and Example C 6 shows the implementation file for the refined behavioral model of the memory controller Example C 7 shows a command script for behavioral synthesis to gates The functional and behavioral abstraction levels use the same memc types h file to define the memory controller commands shown in Example C 4 Memory Controller Example C 10 Example C 5 Behavioral Header File mem controller h header file ifndef MEM CONTROLLER H define MEM CONTROLLER H SC MODULE mem controller sc in lt sc uint lt 8 gt gt into sc in bool reset sc out sc uint lt 8 gt gt outof sc in clk clk Internal variables sc_int lt 8 gt memory 32 snps resource RAM_A variables memory map_to_registerfiles TRUE void entry SC_CTOR mem_controller SC_CTHREAD entry clk pos watching reset delayed 7 true l endif Memory Controller Example C 11 Example C 6 Behavioral Implementation File mem controller cpp implementation file finclude lt math h gt include systemc h de memc types h incl include mem controller h QE Ga En void mem controller entry sc uint 8 data tmp sc uint 8 address data tmp 0
115. escribed in SystemC and C Synthesizable Subset on page 2 32 Refining From Functional to Behavioral Model To refine a functional model into a behavioral model Introduction 1 10 Restrict constructs to the synthesizable subset of C See the Nonsynthesizable Subset of SystemC on page 2 33 Refine ports from abstract data types to synthesizable data types and refine all other data types to synthesizable data types which are described in Synthesizable Data Types on page 2 37 Define a clock port for the module Specify the I O interface by adding wait statements to your description and put signal and port read and write operations with the correct wait statements described in Chapter 3 Behavioral Coding Guidelines e If required manage complexity by using functions Chapter 2 Refining for Behavioral Synthesis describes the refinement activities in more detail Example 1 2 shows a behavioral description of the FIFO that was refined from the algorithmic description in Example 1 1 on page 1 6 The design description and complete set of files for the FIFO are available in Appendix B First In First Out Example Introduction 1 11 Example 1 2 FIFO Behavioral Coding fifo bhv h header file define BUFSIZE 4 define LOGBUFSIZE 2 define LOGBUFSIZEPLUSONE n Ww SC MODULE circ buf sc in clk clk Sc in bool read fifo sc in bool write fifo
116. esis is required How to create hierarchical modules and integrated behavioral and RTL modules is described in the CoCentric SystemC Compiler RTL User and Modeling Guide Refining for Behavioral Synthesis 2 10 When creating the hardware structure adhere to the following guidelines Ahierarchical module contains instances of other modules and the interconnections between the instances The hierarchical module can contain RTL processes but it cannot contain behavioral processes e Each atomic module for behavioral synthesis can contain only clocked thread processes e For behavioral synthesis if SystemC Compiler runtime is excessive you can break your module into smaller modules Refining for Behavioral Synthesis 2 11 Modules The basic building block in SystemC is a module A SystemC module is a container in which processes and other modules are instantiated Figure 2 5 shows a typical module with several processes The processes within a module are concurrent Figure 2 5 Module Process Process BB Note For synthesis with SystemC Compiler version 2000 05 SCC1 0 a module cannot contain instances of other modules As a recommended coding practice describe a module by using two separate files a separate header file module name h and an implementation file module name cpp or module name cc Refining for Behavioral Synthesis 2 12 Module Header File Each module header file contai
117. esizable SystemC Classes Category Construct Comment Corrective action Thread process SC THREAD Used for modeling a Change to testbench but not supported SC CTHREAD for synthesis Method process SC METHOD Used for simulation and modeling at the RT level but not supported for synthesis in SystemC Compiler version 2000 05 SCC1 0 RTL synthesis is planned for a later release Channels sc channel Used only in initial stages of Replace with modeling system functionality sc signal Clock sc start Used for simulation Comment out generators Bidirectional sc inout Bidirectional ports are not Changeto separate port allowed sc in and sc out ports Local watching W BEGIN Local watching is not W END supported W DO W ESCAPE Multiple global Multiple One global reset is supported Combine multiple resets watching for synthesis Multiple resets resets into a single are not supported reset using an AND operator Tracing sc trace Creates waveformsofsignals Comment out for sc create channels and variables for synthesis trace file simulation Refining for Behavioral Synthesis 2 33 Nonsynthesizable C C Constructs SystemC Compiler does not support the C and C constructs listed in Table 2 2 for behavioral synthesis Table 2 2 Nonsynthesizable C C Constructs Category Construct Comment Corrective action Local class Not allowed Replace declaration Nested class Not allowed Replace declaration Derived class On
118. ess requires one or more clock cycles which has an effect on design latency For example if a memory read takes two clock cycles the circuit needs time to access the memory In superstate fixed I O scheduling mode clock cycles are automatically inserted In cycle fixed scheduling mode you need to insert wait statements in your code Example 5 14 shows a memory read that requires a second clock cycle which is inserted correctly in Example 5 15 in bold Example 5 14 Incorrect Memory Read Timing for Cycle Fixed while true wait one cycle addr input port read Need another cycle before write to output output port write memory addr wait Example 5 15 Correct Memory Read Timing for Cycle Fixed while true wait one cycle addr input port read wait second cycle needed output port write memory addr wait Using Arrays Register Files and Memories 5 16 Allowing for Vendor Memory Timing Unlike with arithmetic operations SystemC Compiler does not reserve time in the clock period for vendor timing specifications such as read write off chip or BIST logic access see Figure 5 3 Figure 5 8 Memory Access Time Specification Assumes memory outputs NOT Registered i p227 E ir moha P Cycle Boundary I I 1 DATAPATH I DATAPATH 4 wai I Structural HDL Wrapper 1 tcy tread STATE N You need to provide this timing information using
119. et current address 0 iq calc ready write false f out 0 wait do current addresst if next value current address true 68 clear inp false ETTI false else fill true next value current address false if fill true f addr out inverse scan f addr write f addr out ft O if current address MAX ADDRESS 1 f out mismatch else fout f_t Inverse Quantization Example E 10 f write f out f valid write true f mat f addr outtoffset f out wait while current_address lt MAX ADDRESS 1 else wait One block is done iq block ready write true f valid write false wait Define member functions Sc uint 2 VD iq corrector calc synopsys preserve function unsigned tmp if macroblock intra true level inp 0 tmp 0 else if level inp gt 0 tmp 1 else tmp 2 return tmp sc_uint lt 7 gt VD_iq quantizer synopsys preserve function unsigned tmp if q scale type inp true tmp q scale quantizer scale code inp else tmp quantizer scale code inp lt lt l return tmp Sc int 12 VD iq saturation Inverse Quantization Example E 11 synopsys preserve function int tmp int divide divide f t t if divide lt 2048 tmp 2048 else if divide gt 2047 tmp 2047 else tmp divide return tmp sc_int lt
120. ex 0 while index lt len 1 f w temp w rec real w real w rec imag w imag w rec imag w rec real w imag w rec imag w real w rec real w temp W index 0 w rec real W index 1 w rec imag index t float tmp real tmp imag tmp real2 tmp imag2 unsigned int stage i j index2 windex incr Begin Computation stage 0 len N incr 1 while stage lt M f len len 2 First Iteration With No Multiplies i 0 while i lt N index i index2 index len tmp_real sample index 0 sample index2 0 tmp_imag sample index 1 sample index2 1 sample index2 0 sample index 0 sample index2 0 sample index2 1 sample index 1 sample index2 1 sample index 0 tmp real sample index tmp imag p e Fast Fourier Transform Example D 6 i i 2 len Remaining Iterations Use Stored W j 1 windex incr 1 while j lt len This loop executes N 2 times at first stage and once at last stage i j while i lt N index i index2 index len tmp real sample index 0 sample index2 0 tmp imag sample index 1 sample index2 1 tmp real2 sample index 0 sample index2 0 tmp imag2 sample index 1 sample index2 1 sample index2 0 tmp real2 W windex 0 tmp imag24W windex 1 sample i
121. fer to the documentation for the following related Synopsys products Design Compiler Scirocco VHDL Simulator Verilog Compiled Simulator xxviii Conventions The following conventions are used in Synopsys documentation Convention Description Courier Indicates command syntax Courier italic Indicates a user defined value in Synopsys syntax such as object name A user defined value that is not Synopsys syntax such as a user defined value in a Verilog or VHDL statement is indicated by regular text font italic Courier bold Indicates user input text you type verbatim in Synopsys syntax and examples User input that is not Synopsys syntax such as a user name or password you enter in a GUI is indicated by regular text font bold Denotes optional parameters such as pini pin2 pinN Indicates a choice among alternatives such as low medium high This example indicates that you can enter one of three possible values for an option low medium or high Connects terms that are read as a single term by the system such as set annotated delay Control c Indicates a keyboard combination such as holding down the Control key and pressing c N Indicates a continuation of a command line Indicates levels of directory structure Edit Copy Indicates a path to a menu command such as opening the Edit menu and choosing Copy XXix Customer Support XXX Customer support is ava
122. ger to represent individual characters and small integers typically O through 255 A signed integer typically 32 bits depending on the platform An unsigned integer typically 32 bits depending on the platform A user define aggregate of synthesizable data types A user defined enumerated data type associated with an integer constant Refining for Behavioral Synthesis 2 40 Using SystemC Types The following sections describe the operations that are supported by the SystemC data types Bit and Bit Vector Data Type Operators Table 2 4 provides a list of operators available for the SystemC sc bit andsc bv data types In Table 2 5 Yes indicates that the operator is available for the specified data type Table 2 4 SystemC Bit and Bit Vector Data Type Operators Operators sc bit sc bv Bitwise amp and or xor and not Yes Yes Bitwise shift left and 55 shift right No Yes Assignment amp and Yes Yes Equality Yes Yes Bit selection x No Yes Part selection range x y No Yes Concatenation x y No Yes Reduction and reduce or reduce and No Yes xor reduce Refining for Behavioral Synthesis 2 41 Fixed and Arbitrary Precision Data Type Operators Table 2 5 provides a list of operators available for the SystemC sc int and sc uint fixed precision and sc bigint and sc biguint arbitrary precision integer data types In Table 2 5 Yes indicates that the operator is
123. ghout the design process it is strongly recommended that you use handshaking in both the design and the testbench Using handshaking also ensures that the block you are designing can communicate with other blocks regardless of the number of clock cycles introduced during scheduling This chapter contains the following sections Using Handshake Protocols Using One Way Handshake Protocols Using Handshaking in the Circuit and Testbench 6 1 Using Two Way Handshake Protocols e Fast Handshaking Using a Pipeline Handshake Protocol Using Handshaking in the Circuit and Testbench 6 2 Using Handshake Protocols The I O scheduling mode you use to schedule a design affects your simulation methodology SystemC Compiler can allocate additional cycles in the superstate fixed I O scheduling mode so you need to use handshake protocols to test and verify the functionality at the register transfer and gate levels Handshake protocols allow you to use the same testbench to test the circuit at the behavioral register transfer and gate levels of abstraction You do not have to modify the testbench to compare the behavioral simulation results with the RTL simulation results after scheduling Use handshake signals to communicate between the behavioral block and the other blocks in the system The behavioral block can use handshake signals to notify the other blocks in the system when e The behavioral block can accept new data The ou
124. gs if reset read 1 full 0 empty 1 num_in_buf 0 buf0 0 buf1 0 buf2 0 buf3 0 First In First Out Example B 17 else fu em da 11 full next pty empty next m in buf num in buf next f0 buf0 next fl bufl next f2 buf2 next f3 buf3 next ta out data out next void circ buf ns logic De buf0 next bufl next buf2 next buf3 next num i fault assignments buf0 buf1 buf2 buf3 n_buf_next data_out_next 0 Lt fr TE else ead_fifo read num_in_buf read data_out_next buf0 next bufl buf1 next buf2 buf2 next buf3 num in buf next if write fifo read switch int num in buf read case 0 buf0 next da num in buf nex break case 1 bufl next da num in buf nex break case 2 buf2 next da num in buf nex break case 3 buf3 next da num in buf nex First In First Out Example B 18 num in buf Ld MEL buf0 num in buf read scd ud yy t ta in read ta in read ta in read ta in read t num in buf t num in buf t num in buf t num in buf read read read read default ignore the write command break First In First Out Example B 19 RTL Testbench The RTL testbench is identical to the behavioral testbench Example B 5 on page B 11 and Example B 6 on page B 11 Example B 10
125. gt vall val2 val3 Initialize and reset if reset asserts while true e my prefunc vall val2 val3 real out write e wait end while end entry Definition of preserved function sc int 19 cmult hs my prefunc sc int lt 8 gt aa Sc int 8 bb sc int lt 8 gt cc snps preserve function Sc int 19 temp Using Functions and DesignWare Components 4 7 temp aa bb temp cc return temp SystemC Compiler automatically synthesizes preserved functions into components using adefault compile strategy You can implement finer control of the compile strategy by using the compile_preserved_functions command prior to using the bc_time_design command You can direct the compile preserved functions command to save the synthesized components as db files Then you can use the read preserved function netlist command to read in the previously synthesized component as a preserved function This means you do not have to resynthesize the preserved functions every time you use SystemC Compiler For information aboutusingthe compile preserved functions and read preserved function netlist commands see the CoCentric SystemC Compiler User Guide Using Functions and DesignWare Components 4 8 Nonmember Preserved Functions You can define a nonmember function as a preserved function Define the nonmember function in the same file as the module that uses it Place th
126. h a wait statement as shown in bold in Example 3 12 Example 8 11 Error in Use of General Coding Rule 4 If Conditional With Implied Else if a lt b e a c d wait else if a b e b c d wait Example 3 12 Correct General Coding Rule 4 If Conditional if a lt b e a c d wait wait else if a b e b c d wait else e c d wait Behavioral Coding Guidelines 3 18 Example 3 13 shows switch case conditional branching The case 1 branch and the default branch are missing wait statements This causes an HLS 233 error in cycle fixed mode and a HLS 43 error in superstate fixed mode To correct this error insert wait statements as shown in bold in Example 3 14 Example 3 13 Error in Use of General Coding Rule 4 Switch Conditional switch case case case case defau 0 1 2 3 1 sel t real real real real re bre ou ou ou ou al o ak t write a wait break t write b break no wait t write c wait 3 break t write d wait break ut write a b no wait Example 3 14 Correct General Coding Rule 4 Switch Conditional switch case case case case defau H WN H O sx GE sel real real real real re _out write a wait break out write b wait break Oout write c wait 3 break _out wri
127. h consists of two distinct sections the reset action and the main functionality as shown in Example 2 5 Refining for Behavioral Synthesis 2 28 Example 2 5 Basic Reset Action and Main Loop my module h header file include systemc h SC MODULE SOME MODULE Ports data t is a struct defined elsewher sc in lt data t in data Input port Sc out data t out data Output port SC in clk clk Mandatory sc in lt bool gt reset Highly recommended Process void work Constructor SC CTOR SOME MODULE rj SC CTHREAD work clk pos Declare process watching reset delayed 1 Specify reset li my module cpp implementation file Process void SOME MODULE work Reset actions fosa wait Required wait Main loop while true Main functionality d Refining for Behavioral Synthesis 2 29 In the reset action section you specify the reset behavior of the circuit When the reset signal is asserted the reset code is executed Writing reset functionality is explained in Using Resets on page 3 46 To ensure that a process executes infinitely enclose its functionality in an infinite while loop which is designated as the main loop in Example 2 5 Put the functionality of your process inside this main loop If you started with a C C model of your hardware or a high level
128. hecked at every active clock edge in the process Specifying the Reset Behavior Specify the reset behavior before the infinite while loop as shown in Example 3 47 in bold In the reset behavior define the appropriate constant values for ports internal signals and variables needed to reset the design The reset behavior must not contain e Conditional branches such as an if else or switch case statements or the operator e Rolled loops such as a for while or do while loop Operations that require more than the mandatory wait statement Behavioral Coding Guidelines 3 46 A wait statement also shown in bold in Example 3 47 is required before the infinite while loop that contains the main process body For details about the reset coding rule and an example of it see General Coding Rule 3 on page 3 15 Place initialization or operations that require one or more wait statements at the beginning of the main behavioral process body rather than making it part of the reset behavior Example 3 47 Global Reset Watching Interface file for module SC MODULE example sc in lt bool gt reset sc in clik clk sc out bool out valid Sc out lt sc uint lt 8 gt gt outl out2 fother ports void entry Constructor SC_CTOR example SC_CTHREAD entry clk pos Declare global watched signal here watching reset delayed true hi f ROKCKCKCKCKCKCKkCkCkCKCkCkCKCKCkCKCK
129. iables and Wait Statements 3 52 Using Variables for Register Allocation Efficiency 3 53 Determining the Lifetime of Variables 3 54 Using Functions and DesignWare Components Using Member Functions aNG wate ne Rema SERE 4 2 Using Nonmember Functions a 4 4 Using Presarved FUlDctlonso css mee pee RES ER es 4 4 When to Preserve Functions anaa aaaea 4 5 Preserved Function Restrictions lt 4 5 Creating Preserved Functions a 4 6 Nonmember Preserved Functions lt 4 9 Using Reference Parameters in Preserved Functions 4 10 Using DesignWare Components a 4 11 Using map 10 operator vw EE hana nadama dna 4 11 Guidelines for Using map to operator 4 12 Using Arrays Register Files and Memories USING ATAS naaa maa nn an an age a Ad to se ad da Us 5 2 Declaring Aay S aa bandos t tr KA peed WEN REPE RS 5 2 Reading From and Writing to Variable Arrays 5 3 Reading From and Writing to Signal Arrays 5 4 Accessing Slices of an Array Location 5 5 Array Implementations ye ae ees dry 5 7 Mapping Arrays to Register Files 5 8 Mapping All Arrays to Register Files 5 9 Mapping Specific Arrays to Register Files 5 9 Mapping Arrays to Memories 0c eee eee 5 11 Local MEMO a usce
130. ices education e Telephone 800 793 3448 xxxi xxxii Introduction CoCentric SystemC Compiler synthesizes a SystemC behavioral hardware module into an RTL description or a gate level netlist A future release of SystemC Compiler will provide synthesis of RTL descriptions After synthesis you can use other Synopsys tools for verification test insertion power optimization and physical design This modeling guide defines system design terminology and explains how to develop and refine SystemC behavioral models for synthesis with SystemC Compiler Before reading this modeling guide read the CoCentric SystemC Compiler User Guide to learn about behavioral synthesis concepts and how to run the tool This modeling guide assumes you are knowledgeable about the SystemC Class Library available from the Open SystemC Community at http www systemc org Introduction 1 1 Synthesizable behavioral design examples are available in Appendix B First In First Out Example Appendix C Memory Controller Example Appendix D Fast Fourier Transform Example and Appendix E Inverse Quantization Example for an MPEG 2 decoder These examples show you various coding styles and design techniques used with SystemC Compiler This chapter contains the following sections Defining Levels of Abstraction in System Design Choosing the Right Abstraction for Synthesis Introduction 1 2 Defining Levels of Abstraction in System
131. ider the operations A Band A B as mutually exclusive because they appear in different if statements Example 3 33 Operations That Are Not Mutually Exclusive if A lt 0 out A B if A gt 0 out A B You can combine both operations into an else if statement as shown in Example 3 34 so SystemC Compiler considers the operations mutually exclusive Example 3 34 Mutually Exclusive Operations if A lt 0 out A B else if A gt 0 1 out A B Behavioral Coding Guidelines 3 32 Using Loops Loops repeat a sequence of operations SystemC Compiler synthesizes hardware based on while loops do while loops and for loops Understanding How Loops Are Scheduled If a design contains nested loops SystemC Compiler schedules the innermost loop first then successively schedules the next outward loop until all the loops are scheduled After scheduling an inner loop to a number of cycles SystemC Compiler treats the loop as though it is fixed which means the inner loop operations must remain scheduled relative to each other The latency of the inner loop reported by SystemC Compiler equals the longest path through all the inner loop s iterations Similarly the latency reported by SystemC Compiler of an outer loop equals the longest path through the loop including the latency of any inner loops Timing constraints on the outer loops do not affect scheduling of the inner loops
132. if i 0 e data in read else if i 1 e b 3 else e a 2 wait real out write e wait wait Behavioral Coding Guidelines 3 44 Pipelining Loop Rules Loops can be automatically pipelined For information about using the loop pipeline command see the CoCentric SystemC Compiler User Guide The pipeline rules are the following Only rolled loops can be pipelined e Pipelined loops cannot contain other loops except unrolled for loops e Pipelined loops cannot contain a wait until statement Looplatency must be an integer multiple of the initiation interval as illustrated in Figure 3 3 Loopexits can occur only within the initiation interval as illustrated in Figure 3 4 Figure 3 3 Loop Latency and Initiation Interval Latency Behavioral Coding Guidelines 3 45 Using Resets A reset for SystemC Compiler is a global signal that resets the FSM registers and other registers in the design to a known state Describe the global reset behavior explicitly in the SystemC code so you can simulate the reset behavior at the behavioral level Describing a Global Reset You can define only one global reset signal per process for synthesis To define global reset behavior you need to specify an input signal to watch as shown in Example 3 47 in bold Notice that the reset port is an sc in port of type bool Use the delayed method in the constructor so reset assertion is c
133. ilable through SOLV IT and through contacting the Synopsys Technical Support Center Accessing SOLV IT SOLV IT is the Synopsys electronic knowledge base which contains information about Synopsys and its tools and is updated daily To access SOLV IT 1 Go to the SolvNET Web page at http solvnet synopsys com 2 lf prompted enter your user name and password If you do not have a SOLV IT user name and password you can obtain them at http www synopsys com registration If you need help using SOLV IT click SolvNET Help in the column on the left side of the Sol vNET Web page Contacting the Synopsys Technical Support Center If you have problems questions or suggestions you can contact the Synopsys Technical Support Center in the following ways Openacallto your local support center from the Web by going to http solvnet synopsys com SOLV IT user name and password required then clicking Enter a Call e Send an e mail message to support center synopsys com Telephone your local support center Call 800 245 8005 from within the continental United States Call 650 584 4200 from Canada Find other local support center telephone numbers at http www synopsys com support support ctr Training For SystemC and SystemC Compiler training and private workshops contact the Synopsys Customer Education Center in one of the following ways Go to the Synopsys Web page at http www synopsys com serv
134. ile Example 3 21 Example 3 22 Example 3 23 Example 3 24 Example 3 25 Example 3 26 Example 3 27 Example 3 28 Example 3 29 Example 3 30 Example 3 31 Example 3 32 Example 3 33 Example 3 34 Example 3 35 Example 3 36 Example 3 37 Example 3 38 Example 3 39 Error in Use of Cycle Fixed Mode Coding Rule 1 do While LOOP a5 wi ace nana KKK PA 3 25 Correct Cycle Fixed Mode Coding Rule 1 doswnlle IoOD AA eS ERE 3 25 Error in Use of Cycle Fixed Mode Coding Rule 2 3 26 Correct Cycle Fixed Mode Coding Rule 2 3 27 Error in Use of Cycle Fixed Mode Coding Rule 2 WING sts PC re 3 27 Correct Cycle Fixed Mode Coding Rule 2 Write 3 28 Error in Use of Cycle Fixed Mode Coding Rule 3 3 29 Correct Cycle Fixed Mode Coding Rule 3 3 29 Error in Use of Superstate Fixed Mode Coding RUC Tema ERE A Rds bee ERRASSE nd 3 30 Correct Superstate Fixed Mode Coding Rule 1 3 30 Error in Use of Superstate Fixed Mode Coding RUEZ 8 pak ht OP io RR UA ara ve tu NG ato ALAN 3 31 Correct Superstate Fixed Mode Coding Rule 2 3 31 Operations That Are Not Mutually Exclusive 3 32 Mutually Exclusive Operations 3 32 Labeling a Loop lt lt lt ee Es 3 34 Structure of a while Loop 3 35 Infinite while OOP OO aeta 3 35 Structure of do while Lo0p 3 36 TO LOOP s 233 430 ie eer Duda EUR 3 36 xix Examp
135. ing Arrays Register Files and Memories 5 5 Example 5 8 Multiple Array Accesses Using a Variable sc int lt 8 gt a 16 sc int 8 temp sc int 4 templ temp2 sc int 4 i temp alil templ temp range 3 0 temp2 temp range 7 4 temp range 3 0 temp1 temp range 7 4 temp2 a i temp Unlike a variable array you cannot access slices of array locations in asignal array Itis not allowed Example 5 9 shows the coding style you need to use to access slices of signal array locations Example 5 9 Accessing Slices of a Signal Array Location sc signal lt sc int lt 8 gt gt a 16 sc int 8 temp sc int 4 templ temp2 Sc int 4 i temp a i read templ temp range 3 0 temp2 temp range 7 4 temp range 3 0 templ temp range 7 4 temp2 a i write temp Using Arrays Register Files and Memories 5 6 Array Implementations By default SystemC Compiler generates registers and logic for indexing into the arrays including multidimensional arrays in the behavioral code SystemC Compiler generates dedicated logic for each read from or write to an array This can result in a large amount of logic You can improve the synthesis of designs that have large arrays by mapping an array to a register file or memory If your design includes large arrays more than 1024 elements that are not mapped to a register file or memor
136. ing Clocked Thread Processes A clocked thread process SC CTHREAD is the basic unit for behavioral synthesis with SystemC Compiler For general information about processes see Processes on page 2 20 Each process is synthesized independently Characteristics of the Clocked Thread Process An SC CTHREAD process uses wait statements in the SystemC code to synchronize reading from and writing to signals and ports in the process The SC CTHREAD process is associated with a single clock and is sensitive to either the clock s positive or negative edge which is called the active edge The clock and its active edge are defined in the module s constructor When the SC CTHREAD process is invoked it executes statements in the process until either a wait n or a wait until cond statement is encountered The process is then suspended until the next active edge or itis suspended until the next active edge where the condition of wait until is satisfied All variables that are local to the process are saved when the process is suspended which means that the process state is implicitly saved When the process restarts execution continues at the statement that follows the wait or wait until statement The clock referenced by wait and implicitly referenced by wait until is the clock specified as an sc in clk port which is defined as the active edge in the module s constructor Behavioral Coding Guidelines 3 2 Using the wait Statement
137. ing sender initiated handshake layed true wait until data ready del Wait READ LATENCY cyc wait READ LATENCY a data read wait b data read Now do the algorithm do gcd a b Now write the output les for the first data using sender initiated handshake gcd ready write true gcd write c wait WRITE LATENCY gcd ready write false wait int gcd mod do gcd int a int f int temp if a 0 amp amp b 0 while b 0 while a gt b a wait temp a b b temp wait o po a a else a wait return a 0 r b Using Handshaking in the Circuit and Testbench 6 14 Oko kok k kok kok k kok kok kk kk gcd2 test h header file ifndef READ LATENCY define READ LATENCY 2 endif ifndef WRITE LATENCY define WRITE LATENCY 3 endif SC MODULE testbench SC im clk clk sc out bool data ready Sc in bool gcd ready Sc in lt int gt gcd Sc out lt bool gt reset Sc out lt int gt data Process void do run Internal function void do handshake int a SC CTOR testbench int b SC CTHREAD do run clk pos l ROKR KR kok k kok kok k kok k kk K kk k ke ke ke e kk gcd2_test cc testbench implementation file include systemc h
138. int long short unsigned char unsigned int unsigned long and unsigned short have a platform specific size SystemC Compiler synthesizes variables of these types to have the width dictated by your platform Refining for Behavioral Synthesis 2 43 for Loop Counter In some situations SystemC Compiler can determine that fewer bits are required in hardware than is specified by the data type which produces a higher quality result after synthesis For example if a unique integer variable is declared as a for loop counter SystemC Compiler can determine the number of bits and build only the required hardware Example 2 8 shows a unique loop counter variable in bold SystemC Compiler can determine that 3 bits are required and itwould build a 3 bit incrementer for variable Example 2 8 Implicit Bit Size Restriction for int 120 i lt 7 i loop code If a variable is declared outside of the for loop SystemC Compiler cannot determine the bit size because the intended use of the variable is not known at the time of declaration In this situation SystemC Compiler builds hardware for the platform specific bit size Example 2 9 shows code in bold where the loop counter variable is declared outside the loop In such a situation SystemC Compiler infers that a variable of 32 or 64 bits is required depending on the platform Therefore it is strongly recommended that you use the coding style shown in Example 2 8 instead of the style
139. into a temporary variable and select a bit in the temporary variable Reading and Writing Signals You can read or write a signal using either the read and write methods or by assignment You cannot read or write the individual bits regardless of its type To select a bit on a signal read the signal data into a temporary variable and select a bit in the temporary variable Internal Data Variables Inside a module you can define data variables of any synthesizable SystemC or C type These variables are typically used for internal storage in the module Do not use them for interprocess communication because it can lead to nondeterminism order mismatch during simulation and can cause possible mismatches between the results of synthesis and simulation Refining for Behavioral Synthesis 2 18 Declare internal data variables by using the syntax shown in bold in the following example SC MODULE module name Module port declarations sc in port type port name sc outsport type port name Sc in clk port name Internal signal variable declarations sc signal signal type signal name Data variable declarations int count val Internal counter sc int 8 mem 1024 Array of sc int Clocked thread processes Member function declaration Module constructor SC CTOR module name Register processes Declare sensitivity list Define global watching Refining for Behavioral
140. ion evaluates to true Loop iteration condition A loop iteration condition if else switch case or the operator is evaluated within a loop If the condition evaluates to true the next iteration of the loop is executed If the condition evaluates to false the loop is exited Loop continue A loop continue means the loop continues with execution of another iteration of the loop Behavioral Coding Guidelines 3 10 General Coding Rules The general coding rules are the following 1 Place atleast one wait statement in every loop except an unrolled for loop Place at least one wait statement between successive writes to the same output Place at least one wait statement after the reset action and before the main infinite loop Do not include either a conditional branch or a rolled loop in the reset behavior description If one branch of a conditional if else switch case or the operator has at least one wait statement then place at least one wait statement in each of the other branches including the default branch You can have a different number of wait statements in each branch Place at least one wait statement immediately after each loop to exit the level of scheduling hierarchy created by the loop Behavioral Coding Guidelines 3 11 Cycle Fixed Mode Coding Rules In addition to the general coding rules the cycle fixed scheduling mode rules are the following 1 Place atleastone wa
141. it statement immediately before a conditional loop for while or do while With n representing the number of cycles required to evaluate a loop iteration condition a Inside the loop place n wait statements immediately after the loop conditional is evaluated b Outside the loop place n wait statements immediately after the loop exit The value of n must be at least one Do not place I O read or write statements between the n wait statements With nrepresenting the number of cycles to perform computations and memory access between reading from an input and writing to an output place n wait statements between reading from and writing to the ports Superstate Fixed Mode Coding Rules In addition to the general coding rules the superstate fixed scheduling mode rules are the following 1 Place at least one wait statement after the last write inside a loop and before a loop continue or exit 2 Placeatleast one wait statement after the last write before a loop Behavioral Coding Guidelines 3 12 General Coding Rules Examples The general coding rules apply when you are using the schedule command with an I O mode i0 mode option of either cycle fixedOrsuperstate fixed modes Following are the general coding rules and an example of each General Coding Rule 1 Place at least one wait statement in every loop except an unrolled for loop Example 3 3 shows a loop without a wait statement which causes an HLS 52
142. ite a d b qd wait Refining for Behavioral Synthesis 2 27 Refining the Structure From a High Level SystemC Model When you start from a high level SystemC model your model might or might not already have the structure required for your hardware If your model does not have the structure you need follow the steps beginning at Creating and Refining the Structure From a C C Model on page 2 6 to create the hardware structure A high level SystemC model unlike a pure C C model may contain abstract ports Abstract ports are types that are not readily translated to hardware For each abstract port you need to define a signal port to replace each terminal of the abstract port You also need to replace all accesses to the abstract ports or terminals with accesses to the newly defined signal ports For more information about abstract ports see the SystemC User s Guide Creating and Refining Processes After you create the detailed architecture of your hardware and decompose the functionality into hierarchical and atomic modules you needto create behavioral and RTL processes inside the modules For information about RTL process creation see the CoCentric SystemC Compiler RTL User and Modeling Guide The description of defining a module and declaring a clocked thread process for behavioral synthesis begins at Modules on page 2 12 To implement the behavior define the process body The process body whic
143. le 3 40 Example 3 41 Example 3 42 Example 3 43 Example 3 44 Example 3 45 Example 3 46 Example 3 47 Example 4 1 Example 4 2 Example 4 3 Example 4 4 Example 4 5 Example 5 1 Example 5 2 Example 5 3 Example 5 4 Example 5 5 Example 5 6 Example 5 7 Example 5 8 Example 5 9 Example 5 10 Example 5 11 XX Unrolled for Loop Compiler Directive 3 37 Unrolled for Loop and Its Execution 3 38 When to Use urntroll tv reet ees eim 3 40 Selective Unrolling of a for Loop 3 41 for Loop Without Static Exit Condition 3 42 Consecutive Loops With Overhead 3 43 Collapsed Consecutive Loops 3 44 Global Reset Watching 3 47 Member Function 4 3 Creating Preserved Functions 4 7 Nonmember Preserved Function Declaration 4 9 Preserved Function With Reference Parameter 4 10 Using DesignWare Parts eaaa 4 11 Data Member Array lt 5 2 Array Local to a Process Aa 5 2 Reading From a Variable Array 5 3 Writing to a Variable Array 5 3 Reading From a Signal Array 5 4 Writing to a Signal Array 5 4 Multiple Accesses to Slices in the Same Array 5 5 Multiple Array Accesses Using a Variable 5 6 Accessing Slices of a Signal Array Location 5 6 Mapping Specific Arrays to Register Files 5 10 Declari
144. les Behavioral Coding Guidelines 3 50 Figure 3 5 Comparing Signal Use and Data Flow wait Cw real out write port a read port a port b port c port b read port c read p i real out wait real out write port a read port c read port b read wait Mc real out SystemC Compiler implements the following functionality forthe code snippet in Figure 3 5 1 Read port a port b and port c Compute the result of port a port b port c Write the result to real out at the end of the clock cycle Read port a port b and port c again in the next clock cycle Compute the result of port a port c port b D nl e xe m Write the result to real out in the next clock cycle Behavioral Coding Guidelines 3 51 Note that this design schedules in superstate fixed mode but fails to schedule in cycle fixed mode unless the operations between a read and write can be computed in one clock cycle See Cycle Fixed Mode Coding Rules on page 3 12 Using Variables and Wait Statements Figure 3 6 shows a data flow graph and a modified version of the code segment in Figure 3 5 In this version variables store intermediate results The ports are read and assigned to variables Because the operations based on variables can happen as soon as the variable data becomes available data availability rather than the wait statements constrain operations When you use variables SystemC Compiler pr
145. les to memories You can declare memory locally which means the memory is accessed only by the process in which it is declared You can alternatively declare memory as a data member so that the memory is shared by all processes in a design To map a specific array to a local or shared memory use the synopsys resource compiler directive and the map to module attribute in your code to specify the array that is to be mapped to memory Local Memory Example 5 11 shows a section of code that maps the array named amem to a memory local to the process In a local memory declaration place the compiler directives immediately after the array declaration as shown in bold Using Arrays Register Files and Memories 5 11 Example 5 11 Declaring Local Memory Resources SystemC code fragment while true sc_int lt 32 gt amem 16 synopsys resource RAM A variables amem map to module my mem model array amem mapped to a single RAM amem i ser in a amem j The statements in Example 5 11 collectively declare a resource named RAM A Accesses to array amem map to this memory The my mem model is the memory wrapper interface described in CoCentric SystemC Compiler User Guide DesignWare libraries provide some synchronous memory models suchas DW ram r w s dff that you can use The address range declarations must match the actual memory address range If multiple arrays map to one memory SystemC Compiler
146. level SystemC model Create and refine architecture v Structure Create and refine processes refinement v Convert to synthesizable subset of C Data Refine data types and bit widths refinement Specify design latency throughput and cycles for I O Apply advanced refinemeni Behavioral technigues to synthesizable improve QoR model Control refinement For structure refinement you create the architecture of your design which is the hierarchical structure and the communication your design uses Refining for Behavioral Synthesis 2 4 For data refinement you restrict the model to use only the synthesizable subset of C and you choose appropriate data types and bit widths For control refinement you specify the latency of the design and the cycles in which I O happens You also need to ensure that your model adheres to the coding rules required for synthesis After synthesis you can use advanced refinement techniques such as preserved functions Using Preserved Functions on page 4 4 and loop recoding Using Loops on page 3 33 to further refine your design and achieve a higher quality of results QoR You typically perform the refinement activities in the order shown in Figure 2 1 You do not need to complete each stage before going on to the next stage You may want to partially complete stages and iterate over the entire set of stages seve
147. llelism between operations in different loop iterations Selectively unrolling loop iterations helps balance the advantages of rolling and unrolling Example 3 43 shows a for loop and how you can convert it to a group of nested for loops Behavioral Coding Guidelines 3 40 Example 3 43 Selective Unrolling of a for Loop Rolled for loop for k 0 k lt 7 k loop_operations that are dependent on k The same for loop converted to a group of nested for loops selectively unrolled loop1 for i20 i lt 1 itt loop2 for j 0 j lt 3 j 4 synopsys unroll k 4 i 4 loop operations that are dependent on k To unroll the inner loop while keeping the outer loop rolled place an unroll directive on the inner loop This change results in scheduling two loop iterations rather than the eight in the original code Each iteration of the outer loop contains four iterations of the inner Use this methodology to explore the most efficient implementation while retaining design simplicity Ensuring a Statically Determinable Exit Condition SystemC Compiler requires that unrolled for loops have a statically determinable exit condition at compile time Example 3 44 is an example of code that does not have a statically determinable exit condition Behavioral Coding Guidelines 3 41 Example 3 44 for Loop Without Static Exit Condition if x count 12 else count in port read for i 0 i lt count
148. lowing design attributes indicate that the design is suitable for RTL synthesis The design is asynchronous Itis easierto conceive the design as an FSM and a data path than as an algorithm for example a microprocessor The design is very high performance and the designer therefore needs complete control over the architecture The design contains complex memory such as SDRAM or RAMBUS Introduction 1 21 Comparison of Behavioral and RTL Synthesis The following are benefits of behavioral synthesis compared to RTL synthesis A behavioral description Promotes communication of design intent Is usually smaller than RTL code Promotes greater design reuse because the design is technology and architecture independent Accommodates late design specification changes because the code is architecture independent Cuts implementation time significantly increasing designer productivity Increases verification speed and decreases verification time Promotes exploration of alternative architectures Automatically creates the control FSM and data path Pipelines critical parts of the design such as loops Shares operators and registers Automatically synthesizes memory accesses This modeling guide tells you how to develop descriptions for behavioral synthesis with SystemC Compiler Introduction 1 22 2 Refining for Behavioral Synthesis This chapter explains how to refine a high level SystemC model or a purely C C
149. lt FIFO read lt lt o status lt lt FIFO read lt lt t lt lt FIFO read lt lt t lt lt FIFO read lt lt fifo write 1 fifo write 2 fifo write 3 fifo write 4 fifo read fifo read fifo read fifo read lt lt lt lt lt lt lt lt LA endl endl endl endl Introduction 1 7 fif cou cou cou fif cou fif cou cou fif cout O fif cou fif cou cou fif cou fif o O cout O O O o od S tatus lt lt FIFO write 1 n fifo write 1 lt lt FIFO write 2 n fifo write 2 lt lt FIFO write 3 n fifo write 3 S lt lt S tatus FIFO FIFO tatus read xx fifo read lt lt endl read xx fifo read lt lt endl lt lt FIFO write 4 n fifo write 4 lt lt FIFO write 5 n fifo write 5 status status lt lt FIFO status lt lt FIFO lt lt FIFO status lt lt FIFO Status return 0 Introduction 1 8 lt lt FIFO write 6 n fifo write 6 read lt lt fifo read lt lt endl read lt lt fifo read lt lt endl read lt lt fifo read lt lt endl read lt lt fifo read lt lt endl Behavioral Model A behavioral model of a block in a system is an algorithmic description of the block s behavior Unlike a pure software program however the I O beh
150. lt 16 gt gt out real Sc out lt sc int 16 gt out imag Sc out bool data req Sc out bool data ready sc in lt bool gt reset SC in clk CLK SC CTOR fft f SC CTHREAD entry CLK pos watching reset delayed true void entry bi Fast Fourier Transform Example D 4 Example D 2 FFT Functional Description File fft cpp floating point functional model include include include void fft systemc h Ett n math h entry float sample 16 2 unsigned int index while true data req write false data ready write false index 0 Reading in the Samples cout lt lt endl lt lt Reading in the samples lt lt endl while index lt 16 data_req write true wait until data_valid delayed true sample index 0 in real read sample index 1 in imag read index data req write false wait index 0 Computation sy 1D Complex DFT In Place DIF Computation Algorithm Size of FFT N 2 M unsigned int N M len f f loat theta loat W 7 2 w real w imag w rec real f loat w rec imag w temp Initialize M 4 N 16 len N 2 theta 8 0 atan 1 0 N cout lt lt Computing lt lt endl Calculate the W values recursively w_real cos theta Fast Fourier Transform Example D 5 w imag sin theta w rec real 1 w rec imag 0 ind
151. lt 26 gt VD_iq intra_mult synopsys preserve_function sc int 16 tmp Sc uint 14 half range Sc int lt 14 gt dot diff dct diff 0 Inverse Quantization Example E 13 tmp 0 if dct_size_inp 0 half range 1 lt lt dct size inp 1 if dct diff inp half range dct diff range 10 0 dct diff inp else dct diff dct diff inpt1 half rangexx1 if block count inp 4 dc dct pred 0 dc dct pred 0 dct diff tmp int dc dct pred 0 else if block count inp 4 dc dct pred 1 dc dct pred 1 dct diff tmp int dc dct pred 1 else dc dct pred 2 dc dct pred 2 dct diff tmp int dc dct pred 2 intra multiplication tmp tmp lt lt 3 intra dc precision inp return tmp Sc uint 6 VD iq inverse scan unsigned tmp if alternate scan inp false tmp scan alternate current address else tmp scan zigzag current address return tmp void VD iq reset action EG 0 fet 0 f out 0 level_inp 0 run_inp 0 corrector 0 quantizer_scale 0 ll o matrix_value Inverse Quantization Example E 14 iq sleep false f addr write 0 f write 0 f valid write false iq calc ready write false acknowledge data write false sc uint 7 VD iq W lookup unsigned matrix value tmp if macroblock intra false amp amp use load non intra matrix inp true matrix value tmp non
152. ly SystemC modules and Replace processes are supported Dynamic malloc malloc free new new Use static memory storage free new delete and delete are not allocation allocation new supported delete Exception try catch Not allowed Comment out handling throw Recursive Not allowed Replace with iteration function call Function Not allowed except the classes Replace with unique overloading overloaded by SystemC function calls C built in The math library O library file Comment out functions VO and similar built in C Virtual function Inheritance Multiple inheritance Refining for Behavioral Synthesis 2 34 functions are not allowed Not allowed Not allowed Not allowed Replace with a nonvirtual function Replace Replace Table 2 2 Nonsynthesizable C C Constructs continued Category Construct Comment Corrective action Member access public Allowed in code but are ignored Change to public control protected for synthesis All member access or ignore the specifiers private access is public compiler warnings friend Accessingstruct gt operator Not allowed Replace with access members with using the period the 5 operator operator Static member Not allowed Replace with nonstatic or member variable Dereference and amp Not allowed Replace operator operators dereferencing with direct access to the variable or array Operator Not allowed
153. ment requires two cycles one to read the original value of R i and one to write back the new value of R i R i red v red SystemC Compiler first reads the array location from memory because when SystemC Compiler is writing the full array location is updated see Figure 5 4 Using Arrays Register Files and Memories 5 19 Figure 5 4 Bit Slice Accesses red green blue red green blue R 1 R 2 Rlil R i Read complete Replace bit slice with Write poa array location R i red v red array location 1 cycle 1 cycle The following code takes six cycles to execute two cycles for each line of code R i red v red R i green v green R i blue v blue You can accomplish this task by using a variable to collect the bit or slice values prior to writing the complete array location This method requires only one memory write which executes in one cycle In the following example v is a variable of the appropriate struct type v red v red v green v green v blue v blue R i v Using Arrays Register Files and Memories Using Handshaking in the Circuit and Testbench In the superstate fixed scheduling mode SystemC Compiler may insert clock cycles in addition to those you specify in order to properly schedule the design Therefore a testbench that you use for verification at the behavioral level may no longer work at the RTL or gate level To ensure that the same testbench can be used throu
154. mer Support xxiii What s New in This Release XXIV This section describes the new features enhancements and changes included in SystemC Compiler version 2000 11 SCC1 Unless otherwise noted you can find additional information about these changes later in this book New Features SystemC Compiler version 2000 11 SCC1 includes the following new features e T hewrite rt1 command generates either a synthesizable RTL model or an RTL model optimized for simulation This command provides a single interface to generate RTL models that replaces setting severaldc shell variables and using the write command e Using either the write rt1 or write command you can write an RTL SystemC model optimized for simulation For information about these commands see the CoCentric SystemC Compiler Behavioral User Guide Enhancements SystemC Compiler version 2000 11 SCC1 includes the following enhancements e Synthesizable RTL models now contain operators such as which are used instead of instantiations of Synopsys DesignWare components like DWO1 add Substitutions are made when possible This eliminates the dependency on Synopsys specific components for synthesizable RTL models unless the behavioral description specifies them The memory wrapper generation tool now allows you to specify a memory write latency in addition to a read latency You can now customize the address and data bus waveforms In previous versions of the memory
155. model into a behavioral model that can be synthesized with SystemC Compiler The SystemC and C C language elements that are important for synthesis are also described This chapter contains the following sections Refinement Overview Creating and Refining the Structure From a C C Model Refining the Structure From a High Level SystemC Model Creating and Refining Processes Converting to a Synthesizable Subset Refining Data Refining Control Refining for Behavioral Synthesis 2 1 e Advanced Refinement Techniques e Refinement Recommendations Refining for Behavioral Synthesis 2 2 Refinement Overview Assuming that you have decided on the architecture for your system and have identified the functionality you want to synthesize with SystemC Compiler you need to refine the functional model for synthesis For information about deciding on an system architecture and other design methodology tradeoffs refer to books and other information sources about design methodology Starting with either a purely C C model or a high level SystemC model the stages for refining the high level model into a behavioral model for synthesis with SystemC Compiler are e Structure refinement e Data refinement e Control refinement Figure 2 1 shows the three major stages for refining the model and the activities in each stage Refining for Behavioral Synthesis 2 3 Figure 2 1 Refinement Stages and Activities v High
156. mory Types Single port memory while true sc_int lt 32 gt amem 16 synopsys resource RAM A variables amem map to module my single port mem model ng array amem mapped to a single port RAM amem i ser in a amem j Change to dual port memory while true sc_int lt 32 gt amem 16 synopsys resource RAM A variables amem map to module my dual port mem model si array amem mapped to a dual port RAM amem i ser in a amem j Using Arrays Register Files and Memories 5 14 Accessing Register Files and Memories Efficiently Minimize the number of array read and write operations accessing a register files or a memory to improve the latency of your design By default SystemC Compiler constrains all accesses to a memory or register file so that they occur one at a time This prevents multiple accesses from reading or writing the same array location simultaneously Redundant memory accesses however can inflate the latency of your design so you should avoid them You can prevent SystemC Compiler from constraining reads and writes so that they occur one at a time by using the ignore array precedences command for register files and the ignore memory precedences command for memories See the CoCentric SystemC Compiler User Guide for information about using this command Using Arrays Register Files and Memories 5 15 Accessing Memory Each memory acc
157. mpiler greater flexibility to determine an optimum design Using cycle fixed scheduling mode requires that you fully define the I O schedule with wait statements which is more difficult than writing the equivalent schedulable description for the superstate fixed scheduling mode The superstate fixed I O scheduling mode allows you to use SystemC Compiler commands and constraints to quickly perform tradeoff analysis of clock period latency and resources without modifying your source code Latency tradeoff analysis for cycle fixed scheduling descriptions is not possible It is recommended that you use superstate fixed scheduling mode because the majority of designs are well suited for superstate fixed scheduling The verification methodology for a design synthesized with superstate fixed scheduling mode that uses handshake is described in Chapter 6 Using Handshaking in the Circuit and Testbench Behavioral Coding Guidelines 3 9 Behavioral Coding Style Rules Wait statements define the boundaries of clock cycles or a superstate depending on the scheduling mode The behavioral coding style rules for placing wait statements in your code are summarized in the following three sections Examples of using these coding rules begin on page 3 13 Definition of Coding Rule Terms Terms used in the coding rules have the following meanings Conditional loop A conditional loop is a for while or do while loop that is executed only if the condit
158. n in bold The semantics of C allow you to define a member function before or after the function is called You can define and use any number of member functions A member function can contain wait statements but you are not required to have a wait statement in a function Appendix E Inverse Quantization Example shows an example that uses numerous member functions to ensure that the complex functionality is easy to understand Using Functions and DesignWare Components 4 2 Example 4 1 Member Function member_example h file SC MODULE member example Member function declaration sc_int lt 19 gt mac func sc int lt 8 gt x sc int lt 8 gt y sc int lt 8 gt z SC CTOR member example SC CTHRFAD entry clk pos KKK k k k k kk ck ck ck member example cpp file include lt systemc h gt include member example h gt Member function definition sc int lt 19 gt member example mac func sc int lt 8 gt x sc int lt 9 gt y sc int lt 19 gt z sc int lt 19 gt temp temp x y temp z return temp void member example entry sc int lt 19 gt tmp out sc int lt 8 gt vall val2 val3 Calling the member function tmp out mac func vall val2 real out write tmp out wait val3 Using Functions and DesignWare Components 4 3 Using Nonmember Functions You declare a nonmember function outside of a class Nonmember functions are
159. n inverse quantizer IQ block an inverse discrete cosine transformer IDCT block an MPEG stream parser SP block a motion compensation MC unit block input and output buffers IBs and OBs and a controller CT that controls all the other blocks Figure 2 2 shows an initial structure of an MPEG design with these blocks Figure 2 2 MPEG Decoder Functional Structure 1010 1010 Input port Input Stream Inverse Aue buffer parser quantizer cosine transformer Motion vectors Frame Motion buffer compensation MPEG Video Decoder Output port Video picture Specify the Internal Communication After you determine the blocks of your design you need to decide how these blocks communicate with one another You can use dedicated communication resources between blocks or you can use a shared communication resource such as a bus For the blocks in your design you need to decide what ports they use and what communication resources are used to connect them For the MPEG example assume that a bus was chosen The blocks and the communication between them determines the top level architecture of your design as shown in Figure 2 3 Refining for Behavioral Synthesis 2 7 Figure 2 8 MPEG Decoder Top Level Architecture Refining for Behavioral Synthesis 2 8 1010 1010 Input port Input buffer Stream parser Invers
160. nd the relationships between I O operations The description of the complex number multiplier in Example 3 2 on page 3 5 implies the I O protocol in Figure 3 1 Specifying I O Cycles The wait statements in your behavioral SystemC code constrain I O during scheduling In the I O protocol specification in Example 3 2 on page 3 5 each read operation is followed by a wait statement Therefore the read operations must occur in the described sequence and are separated by at least one clock cycle The wait statement after the last read operation means the write operations occur at least one clock cycle after all read operations are complete Because there is no wait statement between the write operations both write operations must occur in the same clock cycle Behavioral Coding Guidelines 3 7 VO Scheduling Modes The effect of the wait statements in your code depends on the I O scheduling mode which defines how I O operations are scheduled or fixed in specific clock cycles and dictates how other operations are scheduled around the I O operations You can specify an I O scheduling mode to be either cycle fixed or superstate fixed for the SystemC Compiler schedule command For a description of how to select scheduling modes with the schedule command see Chapter 3 Scheduling in the CoCentric SystemC Compiler User Guide Cycle Fixed Scheduling Mode In cycle fixed scheduling mode the I O behavior of your synthesized design matches y
161. ndex2 1 tmp real2 W windex 1 tmp imag2 W windex 0 sample index 0 tmp real sample index 1 tmp imag i i 2 len windex windex incr j stagett incr 2 incr U TT Writing out the normalized transform values in bit reversed order sc uint lt 4 gt bits i sc uint lt 4 gt bits index bits i 0 Fast Fourier Transform Example D 7 i 0 cout lt lt Writing the transform values lt lt endl while i lt 16 bits_i i bits_index 3 bits 1 0 bits index 2 bits i 1 bits index 1 bits i 2 bits index 0 bits 1 3 index bits index out real write sample index 0 out imag write sample index 1 data ready write true wait until data ack delayed true data ready write false itt wait index 0 cout lt lt Done lt lt endl Fast Fourier Transform Example D 8 FFT Behavioral Model Example D 3 shows the header file and Example D 4 shows the implementation file of the 16 point FFT model Example D 5 shows a command script for behavioral synthesis to gates Example D 3 FFT Header File fft h fft module header fil SC MODULE fft module Input ports Declaration SC in lt sc int lt 16 gt gt in real Sc in sc intx165 gt in imag sc in lt bool gt data valid sc in bool data ack sc in lt bool gt reset Output ports Declaration Sc out lt sc int 16 gt out real
162. ndshaking in the Circuit and Testbench 6 5 Example 6 1 One Way Handshake Protocol Behavioral Block gcdi h header file define READ LATENCY 2 define WRITE LATENCY 3 SC MODULE gcd mod Ports sc in clk clk Clock input sc in lt bool gt reset Reset input sc in lt int gt data Port to get data Sc out bool send data Handshake signal to request input sc out bool gcd ready Handshake signal to indicate output is ready Sc out lt int gt gcd Port to send GCD value Process void gcd algo The process that does GCD Internal functions int do gcd int a int b Function of actual gcd algorithm SC CTOR gcd mod SC CTHREAD gcd algo clk pos watching reset delayed true bi kok k kok kok kok k kok k k kk kok kk KAKAK AK gcdl cc implementation file include systemc h include gcdl h void gcd mod gcd algo f int a b The two variables to compute gcd int c The GCD Reset operations gcd write 0 send data write false gcd ready write false Using Handshaking in the Circuit and Testbench 6 6 wait while true First get the two inputs using receiver initiated handshake send data write true wait Wait READ LATENCY cycles before getting first data wait READ LATENCY send data write false a data read wait b
163. ng Local Memory Resources 5 12 Example 5 12 Example 5 13 Example 5 14 Example 5 15 Example 5 16 Example 5 17 Example 6 1 Example 6 2 Example 6 3 Example 6 4 Example 6 5 Example 6 6 Example 6 7 Example 6 8 Example 6 9 Example B 1 Example B 2 Example B 3 Example B 4 Example B 5 Example B 6 Example B 7 Example B 8 Multiple Arrays Accessing One Memory 5 13 Changing Memory Types 5 14 Incorrect Memory Read Timing for Cycle Fixed 5 16 Correct Memory Read Timing for Cycle Fixed 5 16 Redundant Memory Read 5 18 Array Location Assigned to Temporary Variable 5 18 One Way Handshake Protocol Behavioral Block 6 6 Behavioral Block Responding to One Way Handshake doe PPP YT VEN eI mS S P PEE 6 13 Two Way Handshake Protocol From GCD Block 6 23 Two Way Handshake Protocol From Testbench 6 30 Two Way Handshake Using a while Loop 6 36 Fast Two Way Handshake Using while Loop 6 37 Fast Two Way Handshake Using wait_until 6 39 Incorrect Loop Pipeline With Handshake 6 40 Correct Handshake in a Pipelined Loop 6 43 Architectural Simulation Model B 3 Behavioral Header File B 8 Behavioral Implementation File B 9 Behavioral Synthesis to Gates Script B 10 Behavioral Testbench Header File B 11 Behavioral Testbench Implementation File B 11 Behavioral
164. ns the module declaration which includes e Port declarations e Internal signal variable declarations e Internal data variable declarations e Process declarations lt Member function declarations e Constructor of the module Module Syntax Declare a module by using the syntax shown in bold in the following example SC MODULE module name Module port declarations variable declarations Signal Data variable declarations Clocked thread process declarations Member function declarations Module constructor module name Register processes SC CTOR l Note M Declare sensitivity list A Define global watching SC MODULE and SC CTOR are C macros defined in the System Class library Refining for Behavioral Synthesis 2 13 Module Ports Each module has any number of input and output ports Figure 2 6 which determine the direction of data into or out of the module Figure 2 6 Module Ports Module Ports Process Process A A port is a data member of SC MODULE You can declare any number of sc in or sc out ports For a module with a behavioral SC THREAD process you must declare one sc in clk port Note SystemC sc inout ports are not used for behavioral synthesis Refining for Behavioral Synthesis 2 14 Port Syntax Declare ports by using the syntax shown in bold in the following example SC MODULE module name Mo
165. nstructor SC CTOR cmult hs Register processes and define active clock edge SC CTHREAD entry clk pos Watching for global reset watching reset delayed true Refining for Behavioral Synthesis 2 25 Module Implementation File As a recommended coding practice write the module s behavior in a separate implementation file Name the file with either a cpp or cc file extension for example my module cpp Using an Infinite Loop When using a clocked thread process enclose the module behavior within an infinite loop while true in the module s implementation file This ensures that the process runs continuously like hardware In addition each clocked thread process must have at least one wait statement which is explained further in Chapter 3 Behavioral Coding Guidelines Example 2 4 shows the implementation file for the complex number multiplier header file shown in Example 2 2 on page 2 22 The required infinite loop is shown in bold Refining for Behavioral Synthesis 2 26 Example 2 4 Module Behavior cmult cc implementation file include systemc h include cmult h void cmult entry SC 1nt 8 a b cy d while true Read four data values from input port a data in read wait b data in read wait c data in read wait d data in read wait Calculate and write output ports real out write a c b d imaginary out wr
166. ntinuously To model this place the behavior of the hardware inside an infinite loop within the clocked thread process as shown in bold in Example 3 1 This ensures that the behavior executes continuously You can use the following types of infinite loops Example 3 1 Infinite Loops while true loop operations do loop operations while true Dez AEF A loop operations Simple Clocked Thread Example Example 3 2 shows a complete clocked thread example of a complex number multiplier design This example uses the port assignment methods port read and port write to differentiate port reads and writes from variable reads and writes The port read and write methods are shown in bold Behavioral Coding Guidelines 8 4 Example 3 2 Simple Clocked Thread Multiplier cmult h header file SC MODULE cmult Declare ports Sc in sc int lt 8 gt gt data in sc in clik clk SC out lt sc intx165 gt real out SC out lt sc int lt 16 gt gt imaginary out Declare internal variables and signals Declare processes in the module void entry Constructor SC CTOR cmult Register processes and define the active clock edge SC CTHREAD entry clk pos RCKCKCKCKCKCKkCKCkCkCKCKCKCKCkCKCkCKCkCkCkCk Ck Ck ck ck cmult cc implementation file include systemc h include cmult h void cmult entry sc_in
167. o correct this error add a wait statement before the loop statement as shown in bold in Example 3 32 Behavioral Coding Guidelines 3 30 Example 3 31 Error in Use of Superstate Fixed Mode Coding Rule 2 e a c d 1 real out write e Error no wait before loop for int i 0 i 4 itt real out write e wait c data in read e a c qd Example 3 32 Correct Superstate Fixed Mode Coding Rule 2 e a c d real out write e wait Add wait before loop for int i 0 i 4 itt real out write e i wait c data in read e a c d Finding the Cause of Timing Dependent Coding Errors Use the SystemC Compiler be check design command to detect coding errors that are not dependent on operator timing You can use the bc check design command prior to using the bc time design Or schedule commands The schedule command checks for all errors including those dependent on operator timing For details about these commands see the CoCentric SystemC Compiler User Guide Behavioral Coding Guidelines 3 31 Using Conditional Statements Use conditional statements if else switch case and the operator in your code to specify your control flow SystemC Compiler uses the structure of conditional blocks to determine mutually exclusive operations Mutually exclusive operations can share hardware which reduces design costs In Example 3 33 SystemC Compiler does not cons
168. ocesses operations in parallel rather than sequentially Figure 3 6 Variable Use and Data Flow wait dz b real wait real wait port a port b port c port a read port b read port c read out write a b c _out write a c b SystemC Compiler implements the following functionality forthe code in Figure 3 6 Behavioral Coding Guidelines 3 52 1 Readport a port b and port c and assigns their values to variables a b and c 2 Compute the result of a b c and write the result to the real out port 3 Compute the result of a c b and write the resultto the real out port Note that the functionality of Figure 3 5 is different from the functionality of Figure 3 6 if the values of port a port b and port c change in successive cycles As a general recommendation read ports store their values in variables and read the ports when you need new data Using Variables for Register Allocation Efficiency The efficiency of register allocation depends on how the SystemC design description uses variables SystemC Compiler can map a variable to many registers or many variables to a single register Registers store multiple variables if the lifetimes of the variables do not overlap A register can store different variables and the same variable can be stored in different registers at different times SystemC Compiler minimizes the number of registers needed for the de
169. ock Sc trace tf reset Reset Sc trace tf send data Send Data Sc trace tf data In sc trace tf gcd ready Out Ready sc trace tf gcd ready Out sc start 1 return 0 The following steps describe how the handshaking protocol works 1 The behavioral block asserts the handshake signal send data high to indicate that it can process new data It waits for READ LATENCY cycles which gives the testbench time to respond In this example READ LATENCY is 2 2 he testbench sees the send data signal and responds with the first piece of data after READ LATENCY cycles 3 The behavioral block reads the first piece of data and in the cycle immediately following it de asserts send data low and reads the second piece of data 4 This process repeats each time the behavioral block can process the next data set Using Handshaking in the Circuit and Testbench 6 10 5 The behavioral block proceeds to compute the GCD of the two numbers it has read This computation can take an indeterminate but finite number of cycles The following steps are used to implement the output handshake protocol 1 The behavioral block asserts the handshake signal gcd ready high to indicate that it can send new output data and it waits WRITE LATENCY cycles where WRITE LATENCY is 3 in this example This gives the testbench time to read the output 2 After the testbench sees the gcd ready signal it has WRITE
170. old that exclude simulation code from synthesis Example 2 6 Excluding Simulation Only Code C directive ifdef SIM Simulation only code endif SystemC Compiler directive synopsys synthesis off Simulation only code snps synthesis on Synthesis Compiler Directives in Appendix A provides a list of the SystemC Compiler directives Refining for Behavioral Synthesis 2 31 SystemC and C Synthesizable Subset The synthesizable subsets of SystemC and C are provided in the sections that follow Wherever possible a recommended corrective action is indicated for converting nonsynthesizable constructs into synthesizable constructs For many nonsynthesizable constructs there is no obvious recommendation to convert them into synthesizable constructs or there are numerous ways to convert them In such cases a recommended corrective action is not indicated Familiarize yourself with the synthesizable subset and use the synthesizable subset as much as possible in your pure C C or high level SystemC models to minimize the effort of data refinement for synthesis You can use any SystemC or C construct for a testbench You do not need to restrict your code to the synthesizable subset in the testbench Refining for Behavioral Synthesis 2 32 Nonsynthesizable Subset of SystemC SystemC Compiler does not support the SystemC constructs listed in Table 2 1 for behavioral synthesis Table 2 1 Nonsynth
171. on by behavioral synthesis It is scheduled and has hardware allocated for it register sharing Register sharing means variables with sharing non overlapping lifetimes can share the same register resource allocation Resource allocation is the process for deciding how many and what kind of resources are used or needed for a given design resource sharing Resource sharing is a synthesis optimization technique that allows multiple operations to be executed on the same resource RTL RTL is an acronym for register transfer level RTL synthesis RTL synthesis also known as logic synthesis is the process of transforming an RTL description into a gate level technology specific netlist scheduling Scheduling is the synthesis process of assigning each operation to a control step superstate A superstate represents one or more clock cycles for the schedule command in the superstate fixed scheduling mode unrolled loop Loop unrolling means the code body for each loop iteration is replicated as many times as there are iterations wait statement A wait statement causes a wait for the next active clock edge which defines a clock cycle in cycle fixed scheduling mode or the boundary of a superstate in the superstate fixed scheduling mode Glossary 5 Glossary 6 Index Symbols elif compiler directive A 9 else compiler directive A 9 endif compiler directive A 9 if compiler directive A 9 ifdef compiler directive 2 31
172. ontrol portion of the design represents the FSM or control structure which is implied from the conditional constructs and loops cycle accurate model A cycle accurate model of a design is an abstract model that represents the cycle to cycle behavior of a design It is not necessarily the exact structure of the hardware that implements the design data flow graph DFG A DFG depicts the data dependencies the inputs and outputs of a design the operations used in the design and the flow of data from the inputs to the outputs data path A data path is the portion of the design that operates on data that is flowing into the design Typically the data path is controlled by the control portion of the design or FSM enumerated data type An enumerated data type is an abstract type with a discrete set of values When an enumerated type is synthesized a unique bit pattern is assigned to each possible value of the enumerated type high level synthesis High level synthesis HLS is synthesis from a behavioral description of the design into a clocked netlist of components See behavioral synthesis latency delay Latency means the number of clock cycles for performing a calculation lifetime analysis Lifetime analysis is the process for determining how many clock cycles need to be reserved for resources or registers to execute a particular operation or how many clock cycles to hold the value of a particular variable memory infe
173. ool that indicates a write to the FIFO First In First Out Example B 6 full An sc out port of type bool that indicates that the FIFO is full empty An sc out port of type bool that indicates that the FIFO is empty First In First Out Example B 7 Behavioral Description Example B 2 shows the header file Example B 3 shows the implementation file and Example B 4 shows a command script to synthesize to gates for the behavioral model of the FIFO Example B 2 Behavioral Header File fifo bhv h header file define BUFSIZE 4 define LOGBUFSIZE 2 define LOGBUFSIZEPLUSONE 3 SC MODULE circ buf sc in clk clk sc in bool read fifo Sc in bool write fifo Sc in int data in ff sc in bool reset bh Sc out lt int gt data out sc out bool full Sc out bool empty int buffer BUFSIZE SC uint LOGBUFSIZE headp SC uint LOGBUFSIZE tailp The clock Indicate read from FIFO Indicate write to FIFO Data written to FIFO Reset the FIFO Data read from the FIFO Indicate FIFO is full Indicate FIFO is empty FIFO buffer Pointer to FIFO head Pointer to FIFO tail Counter for number of elements SC uint lt LOGBUFSIZEPLUSONE gt void read write FIFO SC CTOR circ buf num in buf process SC CTHREAD read write clk pos watching reset delayed true First In First Out Example B 8 Example
174. ou cou fif cou fif o o od O S lt lt FIFO write 1 n lt lt FIFO write 2 n lt lt FIFO write 3 n S lt lt S lt lt FIFO write 4 n lt lt FIFO write 5 n tatus tatus FIFO FIFO tatus lt lt FIFO write 6n Status Status FIFO status FIFO FIFO status FIFO Status return 0 fifo write 1 fifo write 2 fifo write 3 fifo read fifo read read read endl endl fifo write 4 fifo write 5 fifo write 6 read lt lt fifo read lt lt endl read lt lt fifo read lt lt endl read lt lt fifo read lt lt endl read lt lt fifo read lt lt endl First In First Out Example B 5 Behavioral Model The behavioral description of the FIFO has one SC CTHREAD clocked thread process Ports and Signals Several signals are added for the hardware description The FIFO has the following ports and signals data in An sc in port of type int to write 32 bit data into the FIFO data out An sc out port of type int to read 32 bit data from the FIFO clk An sc_in_clk port for the SC_CTHREAD process reset An sc in port of type bool to clear the data from the buffer which is specified as a global reset read info An sc in port of type bool that indicates a read from the FIFO write info An sc in port of type b
175. our behavioral description cycle by cycle I O is fully scheduled based on the wait statements in the behavioral description In cycle fixed scheduling mode you may need to add wait statements to your code to allow SystemC Compiler to properly construct the FSM and schedule the design A testbench monitors I O at the clock boundaries and handshake is not required Verification before and after synthesis is straight forward Superstate Fixed Schedule Mode In the superstate fixed scheduling mode SystemC Compiler can add clock cycles as needed to schedule the design The region between any two consecutive wait statements in the behavioral code is a Behavioral Coding Guidelines 3 8 superstate In the behavioral code the superstate is one cycle long In the synthesized design however SystemC Compiler can add more clock cycles to the superstate In the behavioral code the I O reads and writes between the two consecutive wait statements belong to the superstate I O writes always take place in the last cycle of the superstate I O reads that belong to a superstate can happen in any clock cycle of that superstate I O constraints are not implicit from the behavioral description For verifying the design before and after synthesis a testbench with handshake is required See Chapter 6 Using Handshaking in the Circuit and Testbench Comparing I O Scheduling Modes Using the superstate fixed I O scheduling mode allows SystemC Co
176. p and Its Execution SystemC x4 times for i 0 i lt 3 i synopsys unroll ali bla elil Behavioral Coding Guidelines 3 38 When the for loop in Example 3 41 is unrolled the loop appears as Comparing Rolled and Unrolled Loops Figure 3 2 shows a comparison of rolled and unrolled loops Figure 3 2 Rolled and Unrolled for Loops rolled loop efi ali bli wait PA NE unrolled loop for int 150 i lt 7 i synopsys unroll clir ali b i wait end unrolled loop Behavioral Coding Guidelines 3 39 When to Use Unroll When the cycle budget for implementing the entire for loop is less than the number of iterations multiplied by the latency of the loop use the unro11 directive shown in Example 3 42 Example 3 42 When to Use unroll for i 0 i lt 5 i synopsys unroll Loop body takes 2 cycles a i b i c i d i end of unrolled loop If the cycle budget is greater than 10 the for loop in Example 3 42 should not be unrolled because the number of iterations times the latency of the loop is 10 Keeping the loop rolled gives SystemC Compiler extra cycles to schedule operations which can reduce design costs while meeting the latency specifications Selectively Unrolling Loop Iterations Keeping a for loop rolled simplifies the scheduling process but unrolling the loop allows exploration of para
177. ral times to develop a synthesizable model Refining for Behavioral Synthesis 2 5 Creating and Refining the Structure From a C C Model A pure C C model of your hardware describes only what the hardware is intended to do When you start with a C C model the goal of the first refinement stage is to create the hardware structure To synthesize the hardware you need to Define I O ports for the hardware module e Specify the internal structure as blocks e Specify the internal communication between the blocks Define the clock and reset signals described in Chapter 3 Behavioral Coding Guidelines Define I O Ports To define I O ports for the hardware you need to determine input ports for reading data into the module and output ports for writing data out from the module Ports are communication resources and they can be shared You can define any number of ports dedicate a port for each I O or share ports for I O based on the requirements of your design Specify Internal Structure Next you need to specify the internal structure of your design as blocks Structuring the hardware depends on the way you conceptualize your design and how you intend to synthesize the design with SystemC Compiler For example consider an MPEG decoder You can conceptualize an MPEG decoder to consist of an input port that accepts an MPEG stream an output port that produces Refining for Behavioral Synthesis 2 6 a decoded MPEG stream a
178. rations creates multiplexing hardware Array accesses can have an impact on SystemC Compiler runtimes area estimates and timing estimates Declaring Arrays You can declare an array of variables or signals as a data member which allows all processes in a module to access the array Example 5 1 shows a single dimension data member array declaration in bold Example 5 1 Data Member Array SC MODULE my module int arr1 64 SC CTOR my module SC CTHRFAD process1 clk pos SC CTHREAD process2 clk pos You can also declare an array local to a process which allows only that process to access the array Example 5 2 shows a multidimensional array declaration local to a process in bold Example 5 2 Array Local to a Process void process1 sc int 8 arr2 64 32 Using Arrays Register Files and Memories 5 2 Reading From and Writing to Variable Arrays SystemC Compiler creates dedicated decode hardware for each read from or write to an array location The hardware decodes the index used to reference the array location If SystemC Compiler can statically determine that the array access index is a constant it creates significantly less decode hardware Example 5 3 shows in bold declaring a variable array and reading from it with a constant index and a nonconstant index Example 5 3 Reading From a Variable Array sc int 8 a 16 sc int 8 temp sc int 4 i temp a 5 read
179. rencing Memory inferencing is a synthesis technique implementing an array in the behavioral description to a memory component keeping the memory technology independent from design development multicycle operation Multicycle operation is a combinational operation that requires more than one clock cycle to execute nonabstract data type A nonabstract data type is a data type that can be easily translated into hardware operation An operation is an instance of an operator in a design Glossary 3 Glossary 4 operator An operator is an abstract representation of a design function such as for addition pipelined loop Loop pipelining is a synthesis technique for partially overlapping loop iterations at circuit runtime to improve design performance pipelined component A pipelined component is a component that executes an operation over several clock cycles It differs from a multicycle component in that it is sequential The internal registers break the logic that implements the operation into multiple stages of combinational logic Each stage executes within a clock cycle The output of a stage is stored in a register and passed onto the next stage at the next clock cycle preserved function A preserved function is a function that is preserved as a level of hierarchy in synthesis A preserved function is pre compiled into a logic netlist prior to behavioral synthesis Each call to the function is treated as a single operati
180. req delayed true if fscanf fp real d amp tmp val cout End of Input Stream Simula sc stop break bi out real write tmp val if fscanf fp imag d amp tmp val Fast Fourier Transform Example D 18 EOF tion Stops lt lt endl cout xx End of Input Stream Simulation Stops xx endl sc stop break bi out imag write tmp val data valid write true wait until data req delayed false data valid write false wait Fast Fourier Transform Example D 19 Example D 7 FFT Testbench Sink sink h header file SC MODULE sink module sc in bool data ready sc out bool data ack Sc in sc int 16 in real Sc in sc int lt 16 gt gt in imag sc in lt bool gt reset sc in clk CIK void sink process SC CTOR sink module SC CTHREAD sink process CLK pos watching reset delayed 1 bi KKK kk kk kok X kk kk kk kk sink cc implementation file include systemc h include sink h void sink module sink process FILE fp real fp imag Sc int 16 tmp int tmp out Gl fp real fopen out real w fp imag fopen out imag w data ack write false while true wait until data ready delayed true tmp in real read tmp out tmp fprintf fp real An tmp out tmp in imag read tmp out tmp fprintf fp imag An tmp out
181. s synopsys synthesis off Simulation only code snps synthesis on translate off and translate on Use synthesis off and synthesis on compiler directives instead Compiler Directives A 7 unroll Use the synopsys unroll compiler directive to unroll a for loop Place the synopsys unroll compiler directive as a comment in the first line in the body of the for loop See Unrolling for Loops on page 3 37 for int i20 i lt 8 itt synopsys unroll loop operations Compiler Directives A 8 C C Compiler Directives You can use C C compiler directives instead of or in addition to the equivalent synopsys compiler directives C Line Label Use the C line label instead of the line label compiler directive See Labeling a Loop on page 3 34 my modulel entry C style line label reset loopl while true wait wait C Conditional Compilation Use the C C language if ifdef ifndef elif else and endif conditional compilation directives to isolate blocks of code and prevent them from being included during synthesis C directive ifdef SIM Simulation only code endif Compiler Directives A 9 Compiler Directives A 10 First In First Out Example This appendix provides a simple first in first out FIFO circular buffer example that shows you a behavioral model with a testbench and the equivalent RTL model that uses the same testbench Thi
182. s F 5 Expressions and Operations F 6 Glossary abstract data type An abstract data type is a data type such as a floating point number that does not readily translate to hardware aggregate data type An aggregate data type contains multiple data types that are grouped together in a C C structure struct allocation Allocation means assignment of hardware resources such as components memory and registers to scheduled operations and variables behavioral synthesis Behavioral synthesis is the process of transforming a behavioral description at the unclocked algorithmic level with few or no implementation details into a clocked netlist of components Behavioral synthesis automatically schedules the operations in the behavioral description into clock cycles allocates hardware to execute them and generates a state machine representing the control logic Glossary 1 Glossary 2 chained operation A chained operation is two or more data dependent operations scheduled in the same clock period without the need to register the intermediate results clock cycle A clock cycle represents one clock period compiler directive A compiler directive is a user specified directive to SystemC Compiler that is placed in the source code as a comment constraint Constraint are user specified parameters such as the clock period I O timing number and type of data path elements and desired number of clock cycles control The c
183. s a token defined in Example C 4 on the into port and then it asserts the new command signal The memory controller reacts to the assertion of the new command in the following sequence a Reads the token from the into port b Executes the WTBYT WRBLK or RDBYT command In the case of a NOP command it does nothing and skips step 3 C Asserts the com complete signal The testbench or communicating module reacts to the com complete assertion and de asserts the new command signal The memory controller reacts to the de assertion of the new command signal by de asserting the com complete signal Memory Controller Example C 4 Functional Simulation Model Example C 1 shows the header file and Example C 2 shows the implementation file for the functional simulation model of the memory controller At the functional level of abstraction the input and output data is a user defined token defined in Example C 3 A token is 8 bits wide and implemented with a struct The token consists of a command t defined in Example C 4 with an address of type unsigned char and a four element array of type unsigned char defined in Example C 3 In Example C 1 notice that the process isan SC METHOD sensitive to the new command and reset signals Memory Controller Example C 5 Example C 1 Memory Controller Header File mem controller h header file ifndef MEM CONTROLLER H define MEM CONTROLLER H SC MODULE mem controller sc in
184. s chapter contains the following sections FIFO Description Architectural Model e Behavioral Model e RTL Model First In First Out Example B 1 FIFO Description The FIFO is a circular buffer that accepts a 32 bit integer value from the input and writes an integer to the output A reset port clears all data in the buffer Architectural Model The architectural model describes the FIFO algorithm The size of the FIFO is specified with the BUFSIZE macro The number of bits required to address the FIFO is specified with the LOGBUFSIZE macro Example B 1 shows the architectural simulation model which works for a FIFO with a size that is a power of 2 First In First Out Example B 2 Example B 1 Arc fifo cc executable hitectural Simulation Model Specification This model works for a FIFO with a size that is a power of 2 Ay include systemc h define BUFSIZE 4 define LOGBUFSIZI struct circ buf int buffer BUFSIZ 1 sc_uint lt LOGBUFSIZI sc_uint lt LOGBUFSIZI int num_in_buf Routine to ini Gl N E The FIFO buffer E headp Pointer to head of FIFO E tailp Pointer to tail of FIFO Number of buffer elements tialize the FIFO void init num in buf 0 headp 0 tailp 0 Constructor circ buf qne void status int read Status of the FIFO To read from the FIFO void write int data To write to the FIFO bool i
185. s full bool is empty l int circ buf read if num in buf num in buf o To determine if FIFO is full To determine if FIFO is empty return buffer headp Otherwise ignore read request First In First Out Example B 3 void circ buf write int data if num in buf lt BUFSIZE buffer tailp data num in buf Otherwise ignore write request bool circ buf i is full y 4 return num in buf BUFSIZE bool circ_buf is_empty return num_in_buf 0 void circ_buf status cout lt PIRO ast if is_empty cout lt lt empty n else if is_full cout lt lt full n else cout lt lt neither full nor empty n int main circ_buf fifo instantiate buffer This is the testbench for the FIFO fifo status cout lt lt FIFO write 1 n fifo write 1 cout lt lt FIFO write 2 n fifo write 2 cout lt lt FIFO write 3 n fifo write 3 fifo status cout lt lt FIFO write 4 n fifo write 4 fifo status cout lt lt FIFO read lt lt fifo read lt lt endl fifo status cout lt lt FIFO read lt lt fifo read lt lt endl cout lt lt FIFO read lt lt fifo read lt lt endl cout lt lt FIFO read lt lt fifo read lt lt endl First In First Out Example B 4 fif cou cou cou fif cout cou fif cou cou fif cou fif cou fif c
186. s map to operator XYZ OP Declare input parameters as either pass by value or constant qualified references For example if a and b are inputs int xyz int a const int amp b snps map to operator XYZ OP Declare output parameters as nonconstant qualified references For example if a and b are inputs and c is an output void abc int a const int amp b int amp c snps map to operator ABC OP If you have a C simulation model you need to ensure that your code only writes to output c and does not read from it Ensure that the parameter names for inputs and outputs exactly match the DesignWare operator port names which is required by the linker of the Design Compiler tool DesignWare operator port names are case sensitive SystemC Compiler issues an error if the names do not match Using Functions and DesignWare Components 4 12 The name of the return port must exactly match an output port of the DesignWare component which is Z by default You can override the name by using the return port name compiler directive for example int xyz int a const int amp b snps map to operator XYZ OP snps return port name C If the DesignWare synthetic operator does not have a port Z you need to include the return port name directive to specify its name If you use reference parameters you need to ensure that you are not using an alias by mistake You create an alias when
187. sc out lt bool gt reset sc out lt int gt data Process void do run Internal function void do handshake int a int b SC CTOR testbench SC CTHREAD do run clk pos KOR KKK kok k KK kok k kok k KK KK ke ke ke ke e x gcd4 test cc testbench implementation file include systemc h include gcd4 test h void testbench do run false false false reset gcd_seen data_ready wait reset wait reset wait Il me true false cout lt lt do handshake 12 do handshake 172 do handshake 36 Reset Don Begin Testing n 6 36 172 Using Handshaking in the Circuit and Testbench 6 32 do handshake 19 5 do handshake 2584 4712 do handshake 15 0 cout lt lt Testing Done n sc stop void testbench do handshake int a int b f cout lt lt GCD of lt lt a lt lt and lt lt b lt lt is Sender initiated handshake Send data ready signal and first data data_ready true data a wait wait until data seen delayed true Now send the second data and deassert data ready data ready false Deassert data ready data b wait Sender initiated handshake Wait until sender is ready wait until gcd ready delayed true Now read data cout lt lt gcd read lt lt endl gcd_seen true
188. se fault assignments next buf0 next buf1 next buf2 next buf3 n buf next out next 0 ead fifo read data out next buf0 next buf1 buf1 next buf2 buf2 next buf3 num in buf next if write fifo read switch int num in buf read case 0 buf0 next da num in buf nex break case 1 buf1 next da num in buf nex break case 2 buf2 next da num in buf nex break case 3 buf3 next da Introduction 1 18 num in buf nex default num in buf erue 4 num in buf read buf0 num in buf read dew yy t ta in read t num in buf ta in read t num in buf ta in read t num in buf ta in read t num in buf ignore the write command break read read read read Choosing the Right Abstraction for Synthesis You can implement a hardware module by using behavioral level synthesis or RTL synthesis Behavioral descriptions are smaller make it easier to capture complex algorithms are faster to simulate accommodate late specification changes and are more intuitive to write and understand and therefore maintain than RTL descriptions At this level of abstraction the model s architecture refers to its hardware implementation which is not yet specified Behavioral synthesis however is not suitable for all modules of a design Evaluate each design module by module and consider each module s attributes des
189. se if num_in_buf BUFSIZE full true Ignore write request otherwise wait else wait Introduction 1 13 Register Transfer Level Model An RTL model describes registers in your design and the combinational logic between the registers As such the functionality of your system is specified as an FSM and a data path Because register updates are tied to a clock the model is cycle accurate both at the interfaces and also internally Internal cycle accuracy means the clock cycle in which each operation is performed is specified This is different from a behavioral model that is cycle accurate at the interface and the operation execution is not cycle accurate Figure 1 4 shows a block diagram for a cycle accurate model Figure 1 4 RTL Model CPU Memory WO Storage i Bus arbiter Introduction 1 14 RTL Coding Style The general characteristics of the RTL coding style for synthesis are the following Implements the design as combinational logic between registers The finite state machine and the data path are explicitly specified e Uses only the synthesizable data types described in Synthesizable Data Types on page 2 37 Uses the synthesizable subset of the C language described in Sys
190. send data write FALSE Changing the initiation interval to 2 as shown in Figure 6 11 however is not acceptable if the initiation interval must be one clock cycle To resolve a pipelined loop handshake resource contention with an initiation interval of 1 assert the handshake signal in the first iteration of the pipelined loop and de assert it after the pipelined loop exits from the outer loop Example 6 9 shows in bold this method of correctly handshaking in a pipelined loop Using Handshaking in the Circuit and Testbench 6 42 Example 6 9 Correct Handshake in a Pipelined Loop while true Loop to pipeline with handshake for int i 0 i lt 3 itt send data write true Assert handshake wait send data write false De assert For Example 6 9 create a testbench that detects assertion of send data and assume that the next assertion of the signal happens after the initiation interval This assumption is valid because of the periodicity of loop pipelining When the testbench detects de assertion of send data it recognizes that the pipelined loop has exited There are no more loop iterations for the testbench to process and therefore no more assumed assertions of send data Figure 6 12 illustrates loop pipelining of Example 6 9 with an initiation interval of 1 clock cycle Resource contention is prevented by de asserting send data after the loop rather than inside the loop Using Handsh
191. sharing 3 53 restrictions pipeline handshake 6 40 return port name compiler directive 4 11 A 4 rolled and unrolled loops 3 37 A 8 RTL coding style 1 15 design attributes 1 19 1 21 model 1 14 synthesis process 2 21 S sc bigint 2 42 sc biguint 2 42 sc bit 2 41 sc bv 2 41 SC CTHREAD 2 21 3 2 infinite loop 2 26 SC CTHREAD process 2 21 SC CTOR 2 24 sc in 2 14 sc in clk 2 14 sc inout port 2 14 sc int 2 42 SC METHOD 2 21 SC MODULE 2 12 SC MODULE syntax 2 13 sc out 2 14 SC THREAD process 2 21 sc uint 2 42 schedule command 3 8 compare I O modes 3 9 cycle fixed 3 8 O mode 3 8 superstate fixed 3 8 schedule command 3 26 3 31 set behavioral reset command 3 48 set cycles command 6 19 set memory input delay command 5 17 set memory output delay command 5 17 signal 3 6 3 49 data types 2 17 internal 2 16 read and write 2 17 syntax 2 16 wait statement 3 50 writing to 5 5 simulation specific code 2 30 snps compiler directive 2 31 A 2 struct GL 1 structure GL 1 structure refinement 2 3 2 6 superstate fixed coding rules 3 12 schedule 3 8 switch 3 32 synopsys compiler directive 2 31 A 2 syntax module 2 13 port 2 15 signal 2 16 synthesis choosing abstraction level 1 19 synthesis off compiler directive 2 31 A 7 synthesis on compiler directive 2 31 A 7 synthesis specific code 2 30 synthesizable data types 2 37 2 39 subset 2 30 SystemC bit data types 2 41 bit operator types 2 41 class library
192. sign Behavioral Coding Guidelines 3 53 Determining the Lifetime of Variables SystemC Compiler automatically determines the lifetime of variables The way you write your design description however affects variable lifetime The lifetime of a variable starts with the cycle it is first assigned to and ends at the end of the cycle when it is last used The last use of a variable is the latest reference to its value Multiple assignments to the same variable are equivalent to single assignments to different variables with different lifetimes Behavioral Coding Guidelines 3 54 Using Functions and DesignWare Components Use functions to increase code readability and to reduce scheduling complexity Using functions to encapsulate combinational and sequential behavior allows you to reuse these structures in multiple places in your code Functions are also useful for grouping bit manipulating logic or timing critical operations This chapter contains the following sections Using Member Functions Using Nonmember Functions Using Preserved Functions Using DesignWare Components Using Functions and DesignWare Components 4 1 Using Member Functions In C a function defined inside a class is called a member function These member functions have access to all the class data variables and they provide a powerful means for describing functionality Example 4 1 illustrates declaring defining and calling a member functio
193. standard C functions that you can use for any purpose Nonmember functions can contain wait statements but they do not need a wait statement Note that nonmember functions do not have access to the data members of a class Using Preserved Functions Preserved functions allow you to create complex components By default SystemC Compiler creates inline code for functions and removes the level of hierarchy the functions might represent You can direct SystemC Compiler to preserve a function instead of inlining it For each preserved function SystemC Compiler creates a level of hierarchy during elaboration During synthesis the level of hierarchy is compiled into a component that is treated exactly the same way as any other combinational component such as an adder or a multiplier Only functions that describe purely combinational RTL designs can be preserved Using Functions and DesignWare Components 4 4 When to Preserve Functions Use a preserved function when you want to do the following Preserve a complex function as an operator Group components that belong in the same cycle into one operation so SystemC Compiler treats the encapsulated function as a single operator Incorporate custom netlists into your design for example preexisting combinational and pipelined parts Precompile parts and enable more accurate timing estimation Use the preserved function as a resource that can be shared Preserved Function Restrictions
194. stemC Compiler Creating a Process in a Module SystemC processes are declared in the module body and registered as processes inside the constructor of the module as shown in bold in Example 2 2 You must declare a process with a return type of void and no arguments which is also shown in bold in Example 2 2 Example 2 2 Creating a Clocked Thread Process in a Module cmult h header file SC MODULE cmult Declare ports Sc in sc int lt 8 gt gt data in sc in clk clk out sc int 16 real out out sc int 16 gt imaginary out SCA SC LY if Dec are internal variables and signals Dec lare processes in the module void entry Constructor SC CTOR cmult Register processes and define the active clock edge SC CTHREAD entry clk pos Refining for Behavioral Synthesis 2 22 To register a function as a process use the SC CTHREAD macro that is defined in the SystemC Class library The SC CTHREAD macro takes two arguments 1 The name of the process 2 The edge of the clock that triggers the process which is also called the active edge Member Functions In a module you can declare other member functions that are not processes They are not registered as processes in the module s constructor These functions can be called from within a process Member functions can contain any synthesizable C or SystemC statement allowed
195. t d fifo write true monitor c 2 FIFO read data in read monitor c0 t FIFO read data in read monitor c0 t FIFO read data in read monitor d fifo write false wait FIFO read data in read monitor itor E Ch057 stop ench monitor t FULL lt lt full read t lt lt EMPTY lt lt empty read t lt lt endl First In First Out Example B 13 Example B 7 Behavioral Top Level Simulation File main cc simulation file for behavioral fifo testbench include systemc h include fifo bhv h include fifo bhv test h int main f sc signal lt bool gt reset write fifo read fifo full empty sc signal lt int gt data in data out sc clock clock Clock 20 0 0 5 testbench T Testbench T clock data out full empty read fifo write fifo data in reset circ buf FIFO FIFO FIFO clock read fifo write fifo data in reset data out full empty sc trace file tf sc create vcd trace file bhv sc trace tf reset Reset sc trace tf write fifo WRITE Sc trace tf read fifo READ Sc trace tf full FULL sc trace tf empty EMPTY sc trace tf data in DATA IN Sc trace tf data out DATA OUT sc trace tf clock signal Clock sc start 1 return 0 First In First Out Example B 14 RTL Model To create
196. t endl KOK KKK KK KKK KK k kok k k kok k koe kkk k k Write Transform Values Loop OK I RK RK KK Write loop that writes the transform values to output ports out_real and out_imag while i lt 16 bits_i i bits_index 3 bits index 2 bits i bits index 1 bits index 0 index bits index out real write real index out imag write imag index data ready write 1 wait until data ack delayed true data ready write 0 itt wait index 0 cout lt lt Done lt lt endl KOR KR KK kok kok ok k kok k kok k kok k KAKA KAKA KAKAK k k k End Process Definition OKCKCKCKCkCkCk Ck k kk kCk Ck kCk ck kk k kk kk k kk kk kk ke x Fast Fourier Transform Example D 15 Example D 5 Behavioral Synthesis to Gates Script search path target_library synthetic_library link_library bc enable analysis info effort_level io mode top_unit sh date compile systemc top unit create clock clk p 25 bc time design schedule io io mode effort compile write hier f db o top unit t Fast Fourier Transform Example D 16 search path SSYNOPSYS libraries syn tc6a cbacore db dw01 sl target library synthetic library db dw02 sldb false medium super mere effort level gate db FFT Testbench The FFT testbench consists of three files source cc sink cc and main fft cc e The source cc file
197. t lt Reset Done Begin Testing n do handshake 12 6 do handshake 172 36 do handshake 36 172 do handshake 19 5 do handshake 2584 4712 do handshake 15 0 cout lt lt Testing Done n sc stop void testbench do handshake int a int b cout lt lt GCD of lt lt a lt lt and lt lt b lt lt Mm is ai aus Receiver initiated handshake Wait until receiver is ready wait until send data delayed true wait READ LATENCY 1 Wait for latency Now write data in 2 consecutive cycl data write a wait data write b wait Sender initiated handshake Wait until sender is ready wait until gcd ready delayed true wait WRITE LATENCY 1 Wait for latency Now read data cout lt lt gcd read lt lt endl KOR KKK KK kok kok k kok kok RK OR KK gcdl main cc top level simulation model include systemc h include gcdl h include gcdl test h ING main Using Handshaking in the Circuit and Testbench 6 9 sc signal lt int gt data gcd Sc signal bool reset send data gcd ready sc clock clock Clock 20 0 5 gcd mod G GCD G clock reset data send data gcd ready gcd testbench TB TB TB clock send data gcd ready gcd reset data sc trace file tf sc create vcd trace file gcd1 sc trace tf clock signal Cl
198. t lt 8 gt a b c d while true Read four data values from input port a data_in read wait b data_in read wait c data_in read wait d data_in read wait Calculate and write output ports Behavioral Coding Guidelines 3 5 real out write a c b d imaginary out write a d b d wait Using Inputs and Outputs SystemC Compiler creates I O when you write to or read from a port or signal For describing behavioral coding guidelines this manual treats ports and signals as identical Registered Outputs SystemC Compiler registers outputs which means that outputs come from registers rather than directly from combinational logic SystemC Compiler does not register inputs and does not support bidirectional I Os for behavioral synthesis Inputs and Outputs Within Cycles Input signals are read at the beginning of a clock cycle Because outputs are registered outputs appear at the beginning of the next cycle as shown in Figure 3 1 Behavioral Coding Guidelines 3 6 Figure 3 1 Simple Multiplier O Protocol clk data_in a N b y c d M real out a c b d imaginary out a d b d Specifying I O Read and Write In a behavioral description the placement of port read and write operations and wait statements in the code defines the I O access rate the sequencing of I O operations the I O groupings a
199. t write e No I O allowed here wait wait 3 insufficient wait statements after loop Behavioral Coding Guidelines 3 27 Example 3 26 Correct Cycle Fixed Mode Coding Rule 2 Write while e a b c d a d wait 7 e a b wait 2 real out write e wait wait 7 Cycle Fixed Coding Rule 3 With n representing the number of cycles to perform computations and memory access between reading from an input and writing to an output place n wait statements between reading from and writing to the ports You can determine n number of cycles from the report created by the bc time designcommand Tocalculate n divide the time required for loop iteration and computation by the available clock period clock period minus any margin Example 3 27 shows a computation that takes several clock cycles but the code allows only one clock cycle To correct this error insert the appropriate number of wait statements to allow the computation to complete before writing the output as shown in bold in Example 3 28 Example 3 27 causes an HLS 52 error during schedule command execution See Finding the Cause of Timing Dependent Coding Errors on page 3 31 Behavioral Coding Guidelines 3 28 Example 3 27 Error in Use of Cycle Fixed Mode Coding Rule 3 data in read d data in read e c d c d d d wait insufficient wait statements or computation real out wri
200. tbench Example B 5 shows the header file for the FIFO testbench Example B 6 shows the implementation file and Example B 7 shows the top level simulation file main cc Example B 5 Behavioral Testbench Header File fifo bhv test h header file SC MODULE testbench sc in clk clk Sc in lt int gt data in sc in lt bool gt full sc in lt bool gt empty sc out lt bool gt read fifo sc out lt bool gt write fifo sc out lt int gt data out sc out lt bool gt reset void stim void monitor SC CTOR testbench SC CTHREAD stim clk pos bi Example B 6 Behavioral Testbench Implementation File fifo bhv test cc testbench implementation file include systemc h include fifo bhv test h void testbench stim f reset write 0 write fifo write false read fifo write false wait First In First Out Example B 11 reset write true wai E 27 reset write false lt lt Reset Done starting test n cout wai wri cou wai cou wai cou wai cou wai wri 0 Ss 0 0 0 0 te fifo write true FIFO write 1 FIFO write 2 FIFO write 3 FIFO write 4 te fifo write false rea wai cout wait cou wai cou rea cou wait wri wait cout wai cout wai wri lt lt 0 0 es d fifo write true 2 FIFO read FIFO read
201. te d wait break al out write a b wait break Behavioral Coding Guidelines 3 19 General Coding Rule 5 Place at least one wait statement immediately after each loop to exit the level of scheduling hierarchy the loop creates Each loop except an unrolled for loop is a level of scheduling hierarchy Example 3 15 shows a for loop with a nested while loop Both loops are missing a wait statement immediately after the loop body which causes an HLS 52 error in cycle fixed mode To correct this error insert wait statements as shown in bold in Example 3 16 In superstate fixed mode SystemC Compiler adds clock cycles to exit the loop hierarchy Therefore not placing a wait statement immediately after the loop does not cause an error To avoid a mismatch with post synthesis simulation you need to add a wait statement after the loop You can exit from a local loop by using a conditional break statement Example 3 15 shows a conditional if statement with a break to exit from the do while loop Behavioral Coding Guidelines 3 20 Example 3 15 Error in Use of General Coding Rule 5 for int i 0 154 itt e a 2 wait while i 0 e b 2 walt do wait e b 2 if i 0 break while i 0 wait no wait real_out write e wait no wait real_out write e wait Behavioral Coding Guidelines 3 21 Example 3 16 Correct General Coding Rule 5
202. te e wait Example 3 28 Correct Cycle Fixed Mode Coding Rule 3 data in read d data in read e c d c d d d wait 8 wait for computation real out write e wait C Superstate Fixed Mode Coding Rules Examples Following are the superstate fixed coding rules and an example of each Superstate Fixed Coding Rule 1 Place at least one wait statement after the last write inside a loop and before a loop continue or exit Example 3 29 shows a for loop without a wait statement after a write to an output and before the loop continue or break which causes an HLS 46 error To correct this error move the wait statement from after the if statement to before the if statement as shown in bold in Example 3 30 Behavioral Coding Guidelines 3 29 Example 3 29 Error in Use of Superstate Fixed Mode Coding Rule 1 for int i 0 i 4 i S pep o Ae NS QS M real out write e no wait after last write and before continue or exit if i data in read break wait Example 3 30 Correct Superstate Fixed Mode Coding Rule 1 for int i 0 i gt 4 i d e a c d i real_out write e wait move the wait before the if if i data_in read break Superstate Fixed Coding Rule 2 Place at least one wait statement after the last write before a loop Example 3 31 shows a write to an output without a wait statement before the loop This causes an HLS 44 error T
203. temC and C Synthesizable Subset on page 2 32 Refining into RTL To refine a behavioral model into a RTL model Separate the control logic and data path Determine the data path architecture Define an explicit FSM for the control logic Example 1 3 shows the RTL version of the FIFO behavioral model in Example 1 2 The RTL coding style has separate processes for the FSM control and data path Notice that the RTL version of the FIFO is much longer and more detailed than the equivalent behavioral version and it is harder to follow than the behavioral description For details about refining a functional or behavioral model into an RTL model see the SystemC Compiler RTL Modeling Guide Introduction 1 15 Example 1 3 RTL Coding fifo rtl h header file define BUFSIZE 4 define LOGBUFSIZE 2 define LOGBUFSIZE ro E31 c ep O z xj w SC_MODULE circ_buf Same I O as behavioral sc_in lt bool gt clk sc_in lt bool gt read_fifo sc_in lt bool gt write_fifo sc_in lt int gt data in sc in lt bool gt reset Sc out lt int gt data out Sc out lt bool gt full sc out bool empty Internal signals sc signal lt int gt buf0 buf0 next Sc signal lt int gt buf1 bufl next sc signal lt int gt buf2 buf2 next sc signal lt int gt buf3 buf3 next sc_signal lt sc_uint lt LOGBUFSIZEPLUSONE gt gt num_in_buf num_in_buf_next sc signal lt bool gt full next empty next
204. th SystemC Compiler For cycle fixed mode the total number of waits in the longest path through the code dictates the latency of the design For superstate fixed mode the scheduler determines the latency of the design Therefore the latency of your design is specified indirectly through the number of wait statements in the code Note that when you specify the I O behavior of one module you are constraining the I O behavior of the modules that interact with it Similarly the I O behavior of your module may be constrained by the I O behavior of the modules that interact with it You respect these constraints by properly placing wait statements in your code Examples of different communication protocols are provided in Chapter 6 Using Handshaking in the Circuit and Testbench and several coding examples appear in Appendix B through E Refining for Behavioral Synthesis 2 47 Advanced Refinement Techniques If you are not satisfied with the QoR obtained from synthesis after your first pass through refinement you can use the following techniques to refine your design further to improve the QoR Use preserved functions See Using Preserved Functions on page 4 4 e Collapse consecutive loops into a single loop See Consecutive Loops on page 3 42 Rewrite loops to selectively unroll them See Selectively Unrolling Loop Iterations on page 3 40 Use fast handshaking See Fast Handshaking on page 6 36 Refining
205. tocols and protocols used on dedicated links You will use the protocol later during the control refinement stage to specify when I O happens Atomic and Hierarchical Blocks In your final architecture blocks can be atomic which means they do not contain other blocks You can also have blocks that are hierarchical which means they contain other blocks In the MPEG example the MPEG decoder and the SP blocks are hierarchical and the other blocks are atomic Refining for Behavioral Synthesis 2 9 You need to create a SystemC module for each atomic block and a SystemC signal for each communication resource which is described in Modules on page 2 12 A SystemC module can contain only SystemC behavioral or RTL processes This document describes only behavioral processes For information about RTL processes see the CoCentric SystemC Compiler RTL User and Modeling Guide For each atomic block you Create a SystemC module Define input and output ports Define the clock and reset ports the clock port is mandatory and the reset port is highly recommended Create a behavioral clocked thread process Declare reset watching For each hierarchical block you create a SystemC module in which you can define processes as well as instantiations of other modules SystemC Compiler synthesizes processes in a module and their interconnection is inferred from the module instantiation To synthesize hierarchical modules RTL synth
206. tputs of the behavioral block are ready This ensures that the behavioral block operates the same way before and after scheduling in the context of other blocks in the design Using Handshaking in the Circuit and Testbench 6 3 Using One Way Handshake Protocols Use one way handshake protocols to communicate with other blocks in the system that have a fixed response time A block with fixed response time is one that can grant a request after a fixed number of cycles from the time the behavioral block issues the request and the behavioral block does not need an acknowledgement signal from the other block One Way Handshake Initiated From Behavioral Block Figure 6 1 shows a timing diagram for a greatest common divisor GCD behavioral block that uses one way handshake protocols to get data and to write data out The GCD block initiates the handshake with the testbench Example 6 1 shows the code for the GCD block the testbench and the main routine for simulation Note The number of cycles needed to compute the GCD is not fixed because it depends on the value of the two numbers for which the GCD is computed Therefore this example requires the use of handshaking Using Handshaking in the Circuit and Testbench 6 4 Figure 6 1 One Way Handshake Protocol s SUL send_data ij u data EMEN a b I d ux gcd ready et Ta Ca CG Number of cycles to perform GCD is dependent on the input value Using Ha
207. traints before scheduling For example dc shell data find cell send data send d hier dc shell a find cell a read di hier dc shell b find cell b read d2 hier gt gt dc shell set cycles 2 from data to a dc shell set cycles 1 from a to b Using Handshaking in the Circuit and Testbench 6 19 Similarly you need to constrain the number of cycles for the output handshake Figure 6 4 shows the output handshake section of code from Example 6 1 with line labels added Figure 6 4 Constraining Output Handshake Signals Constrain to WRITE LATENCY cycles readyl gcd ready write true gcd write c wait WRITE LATENCY yready0 gcd ready write false wait You can use the set cycles command to constrain the output handshake cycles For example dc shell dc shel dc shell gt rl find cell gcd ready readyl hier gt set cycles 15 r0 find cell gcd ready ready0 hier 3 amp RBrom r l to EO Using Handshaking in the Circuit and Testbench 6 20 Using Two Way Handshake Protocols Use two way handshake protocols for modules that do not have a fixed response time and are scheduled with the superstate fixed I O scheduling mode A two way handshake protocol means the block requesting to send or receive data waits for an acknowledgement signal from the other block Therefore two way h
208. ut handshake with the GCD block and the GCD block initiates the output handshake to send the GCD output to the testbench Example 6 4 shows the code for the GCD block the testbench and the main routine for simulation Note The number of cycles needed to compute the GCD is not fixed because it depends on the value of the two numbers for which the GCD is computed Therefore this example requires the use of handshaking Figure 6 6 Two Way Handshake Protocol data ready m data seen EJ data EN a b E gcd ready l H i gcd 3 x c gcd seen r Number of cycles to perform GCD is dependent on the input value Using Handshaking in the Circuit and Testbench 6 29 Example 6 4 Two Way Handshake Protocol From Testbench gcd4 h Two way handshake from testbench header fil SC MODULE gcd mod Ports sc in clk clk Clock input Sc in bool reset Reset input SC in int data in Port to get data Handshake signals Sc out lt bool gt data seen Data read Sc in bool data ready Data ready sc out lt bool gt output ready Output is ready sc in lt bool gt output seen Output is seen Sc out int gcd out Port to send GCD value Process void gcd algo The GCD process Internal functions int do gcd int a int b GCD algorithm function SC CTOR gcd mod SC CTHREAD gcd algo clk pos watching reset del
209. vioral Coding Guidelines 3 14 General Coding Rule 3 Place at least one wait statement after the reset action and before the main infinite loop Do not include either a conditional branch or a rolled loop in the reset behavior description For more information about resets see Using Resets on page 3 46 Example 3 7 shows reset statements without a wait statement before the infinite loop that implements the process behavior This causes an HLS 354 error To correct this error insert a wait statement as shown in bold in Example 3 8 Example 3 7 Error in Us Initialize e of General Coding Rule 3 and reset if reset asserts ready for data write false output data ready write false real out write 0 imaginary out write 0 Error need wait after reset while true Implement process behavior Example 3 8 Correct General Coding Rule 3 Initialize ready for dal and reset if reset asserts ta write false output data ready write false real out wri imaginary out wait while true Implement te 0 t write 0 process behavior Behavioral Coding Guidelines 3 15 General Coding Rule 4 If one branch of a conditional if else switch case or the operator has at least one wait statement then place at least one wait statement in each branch including the default branch You can have a different number
210. y SystemC Compiler will issue a warning because large unmapped arrays can cause long runtimes It is generally more efficient to map arrays to memory than to map them to register files However unless you have ready access to the appropriately sized memory and all the models you need a timing model for synthesis and a behavioral model for simulation it is easier to map arrays to register files For details about how to use memories constrain designs with memories obtain reports about memories and generate a memory wrapper interface see the CoCentric SystemC Compiler User Guide SystemC Compiler can use only synchronous memories For information about converting an asynchronous memory to a synchronous memory see the CoCentric SystemC Compiler User Guide Using Arrays Register Files and Memories 5 7 Mapping Arrays to Register Files Register files are similar to memories except that SystemC Compiler builds the read and write operators and the register array on the fly Figure 5 1 shows the architecture of a register file Figure 5 1 Register File Architecture Data Array Write Array Master Data Array Read Address Adaress DT Data Data Array Read Address Address Y Dr Using Arrays Register Files and Memories 5 8 Mapping All Arrays to Register Files To map all the arrays in your code to register files set the bc
211. ze for synthesis for example change an int type to an sc intens type where n specifies the number of bits Table 2 3 Synthesizable Data Types SystemC and C type Description sc_bit A single bit true or false value sc_bv lt n gt An arbitrary length bit vector sc_logic A single bit 0 1 X or Z for RTL synthesis only sc_lv lt n gt An arbitrary length logic vector for RTL synthesis only sc_int lt n gt Fixed precision integers restricted in size up to 64 bits sc_uint lt n gt Fixed precision integers restricted in size up to 64 bits unsigned sc_bigint lt n gt Arbitrary precision integers recommended for sizes over 64 bits sc_biguint lt n gt Arbitrary precision integers recommended for sizes over 64 bits unsigned bool A single bit true or false value int A signed integer typically 32 or 64 bits depending on the platform unsigned int An unsigned integer typically 32 or 64 bits depending on the platform long A signed integer typically 32 or 64 bits or longer depending on the platform Refining for Behavioral Synthesis 2 39 Table 2 3 Synthesizable Data Types continued SystemC and C type Description unsigned long char unsigned char short unsigned short struct enum An unsigned integer typically 32 or 64 bits or longer depending on the platform A signed integer to represent individual characters and small integers typically 128 through 127 An unsigned inte

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