TC1766 Documentation Addendum V1.2
Contents
1. LTC Groups LTCGO LTCG1 LTCG2 LTCG3 LTCG4 LTCG5 LTCG6 LTCG7 8 l PDL 3 0 INTO 24 8 FPC 5 0 INT 3 0 4 Output Multiplexer GPTA Module Kernel ea ff 1 0 Groups IOGO 10G1 10G2 10G3 10G4 10G5 10G6 OUT 111 56 MCA06382_c Figure 22 59 Input Output Line Sharing Unit Overview Documentation Addendum 40 V1 2 2007 04 Infineon TC1766 User s Manual Peripheral Units Part Volume 2 Page 22 90 Figure 22 60 should be updated with the below figure with the example for OG2 corrected Example for an Example for an LTC Group GTC Group LTCG3 GTCG1 LTC24IN LTC24 LTC240UT GTCO8IN gt G 8 GTCOB8OUT LTC25IN Ag LTC25 a LTC250UT GTCO9IN id El GTCO9OUT LTC26IN i TC26 LTC260UT GTC10IN M GTC100UT LTC27IN gt LTC27 E LTC270UT GTC11IN id El GTC110UT LTC28IN gt LTC28 El LTC280UT GTC12IN id l GTC120UT LTC29IN H LTC29 E LTC290UT GTC13IN E GTC130UT LTC30IN id LTC30 7 LTC300UT GTC14IN i A GTC140UT LTC31IN id LTC31 FJ L TC310UT GTC15IN GTC150UT Example for an Example for an 1 O Group Output Group IOG5 OG2 IN40 Pin 1040 OUT40 OUT72 IN41 jd Pin 1041 E OUT41 OUT73 IN42 id Pin 1042 O OUT42 OUT74 IN43 ld Pin 1043 al OUT43 OUT75 IN44 M Pin 1044 Fl OUT44 OUT76 IN45 i Pin 1045 a OUT45 OUT77 IN46 i Pin 1046 E OUT46 OUT78 IN47 gt Pin 1047 a O2. Page 18 19 The following note must be inserted after the first note of the page Note This error can occur after any transfer if the communication is stopped This is due to the fact that SSC supports back to back transfers for multiple transfers In order to handle this the baud rate detection logic expects a next clock cycle immediately for a new transfer after a finished transfer Page 18 23 In the STIP bit description the sentence This bit determines must be replaced by the following sentence This bit determines the logic level of the Slave Mode transmit signal when the SSC slave select input signals are inactive PISEL SLSIS 000 Page 18 25 The bit description of bit EN must be extended by the following sentence Note that EN should only be reset by software while no transfer is in progress STAT BSY 0 Page 18 29 The note paragraph at the bottom of the page must be replaced by the following note paragraph Note The SSOC register content is latched by each TB register write operation and remains latched during the consecutive serial transmission Page 18 30 In the bit description of register SSOTC a footnote must be added to the bit combinations 00 of bit fields LEAD TRAIL and INACT 1 For getting a best case timing with no timing delays see Figure 18 8 this bit field value should be set when the SLSOn outputs are disabled SSOC OENnh bits set to 0 Page 18 30 The
3. Page 10 98 In the syntax description of the ST PI instruction of the PCP the register name Ra should be replaced by Rb Documentation Addendum 20 V1 2 2007 04 Cinfineon td User s Manual System Units Part Volume 1 Page 11 9 The wordings SHADROn with CHCROn SHCT 01 on the left of the first waveform from the bottom of Figure 11 5 must be replaced with SHADROn with ADRCROn SHCT 015 CHSROn TCOUNT tot Xto1 1 C1 X 0 X tc2 Mic 1022 CHCROn TREL tc1 tc2 tc3 savon EEEE ADRCRON SHCT 01 o sa 0000 0000 XK sas tc1 transfer count 1 1 3 writing to CHCROn and SADROn tc2 transfer count 2 2 start of new DMA transaction with sa1 source address 1 shadow transfer of source address sa2 source address 2 MCT06153_c Figure 11 5 Shadow Source Address and Transfer Count Update Documentation Addendum 21 V1 2 2007 04 Cinfineon mene User s Manual System Units Part Volume 1 Page 11 10 Figure 11 6 must be updated as per the corresponding changes on pages 11 35 and 11 50 CHCROn Suspend Request CHMODE Suspend Control SUSPMR End of Transaction SUSENOn Pattern Match CHOn_REQIO CHOn_REQI1 CHOn_REQI2 CHOn_REQI3 CHOn_REQI4 CHOn_REQI5 CHOn_REQI6 Transfer CHOn_REQI7 End of Transaction Transfer Request To Channel Arbiter Transfer Set Request PRSEL TRLOn Lost CHCROn CHCROn CHRSTR ERRSR Interrup
4. Page 11 35 The following paragraphs should be added after the last paragraph for a specific value of CHDW under Section 11 1 9 Pattern Detection Depending on CHCROn PATSEL and on the positive result of the comparison two actions follow if CHCROn PATSEL 00 no action will be taken when a pattern match is detected so the wrap interrupt can be used e The activation of the interrupt corresponding to the current active channel On using the Interrupt Pointer defined in CHICROn WRPP e Reset TRSR HTREOn and TRSR CHOn in order to stop the current transaction Hardware and Software request enable The value of CHSROn TCOUNT can be read out by the interrupt SW The software will have to service the interrupt and to activate again the channel Page 11 50 The description of bit field CHOn must be extended by the following sentence CHOn is reset when a pattern match is detected The description of bit field HTREOn must be extended by the following sentence HTREOn is reset when a pattern match is detected Page 11 79 The second sentence of the last paragraph should be replaced with If DMA channel On is active when writing to SADROn the source address will not be written into SADROn directly but will be buffered in the shadow register SHADROn until the start of the next DMA transaction Page 11 80 The second sentence of the last paragraph should be replaced with If DMA channel On is active when writing to DA
5. PANCTR 01C4 MCR 01C8 MITR 01CC Page 20 75 In Table 20 6 the two sentences in column Signification for LEC value 111B at the bottom of the page must be replaced by the following two sentences Whenever the CPU writes the value 111B to LEC it takes the value 111B Whenever the CPU writes another value to LEC the written LEC value is ignored Page 20 85 In the first row of Table 20 8 column CAN Bus State the wording reserved bits must be deleted In the second row of Table 20 8 column CAN Bus State the wording reserved bits must be inserted at RTR reserved bits IDE Documentation Addendum 33 V1 2 2007 04 Cinfineon TAGG User s Manual Peripheral Units Part Volume 2 Page 20 109 The paragraph after Equation 20 2 must be replaced by the following Equation 20 1 applies to normal divider mode CAN_FDR DM 01 of the fractional divider Equation 20 2 applies to fractional divider mode CAN_FDR DM 10 Page 20 116 The first sentence of the second paragraph must be replaced by Each of the 136 hardware initiated interrupt sources is controlled by a 4 bit interrupt pointer that directs the interrupt source to one of the six interrupt outputs INT _Om m 0 5 Documentation Addendum 34 V1 2 2007 04 Infineon User s Manual Peripheral Units Part Volume 2 Documentation Addendum Page 20 117 Figur
6. The referenced documents to this addendum are located at the Internet page e www infineon com tc1766 e TC1766 System Units User s Manual Vol 1 V1 1 Aug 2005 e TC1766 Peripheral Units User s Manual Vol 2 V1 1 Aug 2005 Documentation Addendum 5 V1 2 2007 04 Cinfineon Teee User s Manual System Units Part Volume 1 2 User s Manual System Units Part Volume 1 This section describes corrections for the System Units part of the User s Manual Page 1 10 The second bulleted point under Interrupt System must be corrected to Flexible interrupt prioritizing scheme with 255 interrupt priority levels Page 1 11 The bulleted point under Package must be corrected to PG LQFP 176 2 package 0 5 mm pitch Documentation Addendum 6 V1 2 2007 04 Infineon Tease User s Manual System Units Part Volume 1 Page 1 33 Figure 1 12 should be replaced with the below figure lt o ER 55 99ga 22 se e255 ee ee 559292 23 0 PA SOE Sake SSEEREER B322 gt a TEJIDO g000 55092 S S 55900000 UUSA 338 a Basaaqrs ee SOFF Unm W SOFFFEEE Sa fa zee 2833 ffs 55833333 SS T ea ga o o ee 22 253 Q Q909029 x x SOS S995 954 3 SoSsssss LE ge S508 Ssessnek a BSPG8R0R gs 35 S266 S256560SS E258 SS5666666 aF 23 QQSsS QVSSKSxrKLES QQSSSSSS OG lt 8ss909 2 20 230022 az ESPERE agaaga zZz 9 ZZS OE0 ZZS SURK QUQQXX 2222 222210 72225 803 22222z22e0F SLR EE
7. Bese Basen RECREA scsi KSKESS SUNG A LEONEL ALAN TO KUM FE AO One SSSSBBABSSSSANANNNNOOOOBBAESSSSSSSSGGGEGBAGA MAO e000 gt gt gt 00060606000000N0LL gt gt gt 00000000000 gt gt gt 000000 PAA AAG OSAMA OAM VOFPNTOD DOI ROMTOANK SDOR CILANTRO SS eeeeee ee ee Se LS e e OCDSDBGO OUT40 IN40 P5 0 lt 4 gt P3 4 MTSRO OCDSDBG1 OUT41 IN41 P5 1 O P3 7 SLSIO SLSO02 SLSO12 OCDSDBG2 0UT42 1N42 P5 2 gt P3 3 MRSTO OCDSDBG3 0UT43 1N43 P5 3 OCDSDBG4 0UT44 1N44 P5 4 OCDSDBG5 0UT45 1N45 P5 5 OCDSDBG6 OUT46 IN46 P5 6 OCDSDBG7 OUT47 IN47 P5 7 gt P3 2 SCLKO gt P3 8 SLSO06 TXD1A gt P3 6 SLSO01 SLSO11 SLSO01 amp SLSO11 P3 5 SLSO00 SLSO10 SLSO008SLSO10 VCOJDAALN TRCLK R Voor Voo R Voo Voor gt HORST Vss PORST OCDSDBG8 TDATA1 RDATA0B P5 8 R NMI OCDSDBG9 TVALID1 RVALIDOB P5 9 gt BYPASS OCDSDBG10 RREADY0B TREADY1 P5 10 TESTMODE OCDSDBG11 TCLK1 RCLKOB P5 11 gt BRKIN OCDSDBG 12 TDATAOB RDATA1 P5 12 BRKOUT OCDSDBG13 TVALIDOB RVALID1 P5 13 F TCK OCDSDBG14 RREADY 1 TREADYOB P5 14 gt TRST OCDSDBG15 TCLKOB RCLK1 P5 15 TDO Ne R TMS SSAF R TDI Vopar TC 1 766 R P1 7 IN23 0UT23 OUT79 Vopme R P1 6 IN22 0UT22 OUT78 VssmF R P1 5 IN21 0UT21 0UT77 VEAREF P1 4 IN20 EMG_IN OUT20 OUT76 Veacno Voposca AN35 J gt Vonosc AN34 J F gt Vssosc AN33 7 gt XTAL2 AN32 J F XTAL1 AN31 J ss AN30 SJ gt Voor AN29 57 F Von AN28 J R P1 3 IN19 0UT19 OUT75 AN7 57 R P1 11 IN27 IN51 SCLK1B OUT27 OUT51 AN27 SJ R P1 10 IN26 IN50 OU
8. ADC channels 0 15 GRPS 0 is always related to the reference input pin the programmed selection is not taken into account The measurement of the ADC channels 16 31 GRPS 1 is always related to the programmed reference the programmed selection is taken into account Page 24 6 The two heading paragraphs must be corrected in the following way Replace Configuration 3 with Configuration 2 Replace Configuration 4 with Configuration 3 Page 24 7 The text in the leftmost column of Table 24 1 must be corrected in the following way Replace Configuration 2 with Configuration 1 Replace Configuration 3 with Configuration 2 Replace Configuration 4 with Configuration 3 The last row of Table 24 1 FAINXN FAINxP XX 512 must be deleted Page 24 8 The second formula of equation 24 1 should be corrected into VeaREEM Wi Veneno pi Vearer Veaonp 2 Documentation Addendum 52 V1 2 2007 04
9. For example based on Figure 22 67 each of the eight LTC input multiplexer output lines to LTC group LTCG2 is connected via five LIMGn2 n 0 4 with the eight outputs of two I O group IOG2 and OG6 one GTC group GTCG2 the clock group and the PDL INT group Page 22 108 In Table 22 12 the text OG3 of LTCG2 row should be replaced by lIOG6 Page 22 125 The text else DCMk Timer must be included between the last two endif lines on the bottom Page 22 132 Below the second last line of the page GTCk Cell_ Enable 1 the following line must be added GTCk Enable_Of_ Action 0 Pages 22 173 and 22 174 The long name of register LTCCTRk must be corrected as Local Timer Cell Control Register k Page 22 178 The long name of register LTCCTR63 must be corrected as Local Timer Cell Control Register 63 Page 22 184 The text for Section Output Multiplexer Control Registers should be replaced by Two registers OMCRL and OMCRH are assigned to each I O Group IOG 6 0 and each Output Group OG 6 0 OMCRL 6 0 OMCRH 6 0 are assigned to IOG 6 0 and OMCRL 13 7 OMCRH 13 7 are assigned to OG 6 0 OMCRL controls the connections of group pins O to 3 OMCRH controls the connections of group pins 4 to 7 Documentation Addendum 49 V1 2 2007 04 Cinfineon Teee User s Manual Peripheral Units Part Volume 2 Page 22 200 The first sentence of the first paragraph of Section 22 4 3 1 sh
10. Input Output Group Controlled by Multiplexer Selectable Control Register Groups via OMGng IOG3 IN 27 24 0UT 27 24 OMCRL3 GTGG3 LTCG3 IN 31 28 0UT 31 28 OMCRH3 LTCG7 lOG6 IN 51 48 OUT 51 48 OMCRL6 GTGG2 LTCG2 IN 55 52 0UT 55 52 OMCRH6 LTCG6 OGO OUT 59 56 OMCRL7 GTGG3 LTCG3 OUT 63 60 OMCRH7 LTCG7 0G1 OUT 67 64 OMCRL8 GTGGO LTCGO OUT 71 68 OMCRH8 LTCG4 OG2 OUT 75 72 OMCRL9 GTGG1 LTCG1 OUT 79 76 OMCRH9 LTCGS 0G3 OUT 83 80 OMCRL10 GTGG2LTCG2 0UT 87 84 OMCRH10 LTCG6 OG4 OUT 91 88 OMCRL11 GTGG3 LTCG3 OUT 95 92 OMCRH11 LTCG7 OG5 OUT 99 96 OMCRL12 GTGGO LTCGO OUT 103 100 OMCRH12 LTCG4 OG6 OUT 107 104 OMCRL13 GIGG1 L 166i OUT 111 108 OMCRH13 LTCGS Documentation Addendum 45 V1 2 2007 04 Infineon mene User s Manual Peripheral Units Part Volume 2 Page 22 99 Figure 22 64 should be updated with the below figure GTCGO GTCG1 GTCG2 GTCG3 GTC 07 00 GTC 15 08 GTC 23 16 GTC 31 24 8 8 8 8 GIMG 01 GIMG e 02 Ej 2 GI 0 Q GIMG 11 GIMG 12 LTC 07 00 LTCG1 GIMG LTC 15 08 21 LTCG2 8 GIMG LTC 23 16 22 8 LTcG3 8 GIMG 3 LTC 31 24 23 lo O 5 LTc Input LTCG5 GIMG Multiplexer LTC 47 40 31 8 LTCG6 LT C 55 48 LTCG7 LT C 63 56 MCA06387_c Figur
11. es eae 8 Page 227 wee hua E es aus ewe es eae 8 Page 2 20 caia hua uae ak Gash ees aus ewe es pares 9 Pade JG ase y suse uae ak Guess Use oe ewe eee eae 9 Page 425 A ves ye ek ewe A ee OU oe a ewe a eared 9 Page 4 26 des ta osana BS a bw a baler BS ie Rae a Be 10 Page 5 18 20103 ns brains oh bow eek OS eee ie hee a a l 10 Page 5 20 ass tase es oh ho bo eee o os a a i 10 Page 5 21 4 usu ta arana es oh hw bode eee we hae Sa a i 10 Page 5 22 4 osu Ramee es ah ho bod eee os a ee 10 Page 5 28 ue varia a bo hed Bee bs a od 11 Page 548 O ocd pawns ean hea bea eee een eee EG 11 Page O ee e Be Rea td eee beer eee oe eee 11 clo e cae ae ere eer en ee cee a ere ee ee we ee ere er 12 Page teas Bet ie a ee e Bae ee hd bee eee eee ce eee 12 Page 00 er het ye ad eae e Chea een dd e da spore 12 A E een bees wae 12 Page 6 19 2 ia dee aca a 12 Page 6 20 o e aa a eh ee Soe eee Be 13 Page 6 29 E ee ee ee ae eee a ee rr me De ee eT eae 13 Page 7 16 a ee ee ee re eee a er ee ee re ee a 13 Page ne ee re er ee eee an ee er ee ee ee ree 14 Page 7 49 to 7 51 cece ee eee bee ee eee 14 Page 8 5 to 8 7 and 8 13 to 8 14 0 ee 14 Page Gali cstadesriidieucdetd ad sedan naa are ence 16 Page O10 enredo e e Ada e dd ada dd la che de 16 Page 9 25 estaran dae Ada e cda dd la che de 16 Page 262 eosnerorta debera bes dae dd dd la ends 17 Page QAT a ctedosseteeeneteaserSerthasidadedscdanee dhe A 17 Pade 9 42 abrira rr ranas oad rada eee 17 Documentation Addendum 1 V1 2 200
12. loader mode 3 is identical to bootstrap loader mode 1 Documentation Addendum 9 V1 2 2007 04 Cinfineon TEIGE User s Manual System Units Part Volume 1 Page 4 26 The first sentence of the note at the top of the page must be extended by For CRC generation and error checking the BootROM software uses the TC1766 on chip memory checker module with an initial value of FFFF FFFF for the memory checker result register before the checksum is generated Page 5 18 The bit description of case 1 for EICRO RENO must be replaced by The detection of a rising edge of INO generates a trigger event INTFO becomes set Page 5 20 The bit description of case 1 for EICRO REN1 must be replaced by The detection of a rising edge of IN1 generates a trigger event INTF1 becomes set Page 5 21 The bit description of case 1 for EICR1 REN2 must be replaced by The detection of a rising edge of IN2 generates a trigger event INTF2 becomes set Page 5 22 The bit description of case 1 for EICR1 REN3 must be replaced by The detection of a rising edge of IN3 generates a trigger event INTF3 becomes set Documentation Addendum 10 V1 2 2007 04 Cinfineon td User s Manual System Units Part Volume 1 Page 5 28 The first sentence of the bit description of GEEN1 must be replaced by Bit GEEN1 enables the generation of a trigger event for output channel 1 when the result o
13. note paragraph after the SSOTC register description table must be replaced by the following note paragraph Note The SSOTC register timing parameters are latched by each TB register write operation and remain latched during a consecutive serial transmission Documentation Addendum 32 V1 2 2007 04 Cinfineon TAGG User s Manual Peripheral Units Part Volume 2 Page 19 20 The following sentence should be added at the end of the Section 19 1 2 6 Note that in this case no time frame finished interrupt is generated any more Page 19 42 Description of bit field NDBH for bit combination NDBH 00000 the text No SRH bit shifted should be replaced by No SRH bit shifted no selection bit is generated the SRH active phase is completely skipped Page 20 49 The following paragraph should be added after the last paragraph In order to avoid direct reception of a message by a slave message object as if it was an independent message object and not a part of a FIFO the bit RXEN of each slave object must be cleared The setting of the bit RXEN is don t care only if the slave object is located in a list not assigned to a CAN node Page 20 50 The first paragraph should be extended by a second sentence A transmit FIFO consists of one base message object and one or more slave message objects Page 20 54 Table 20 4 The offset addresses of the four registers must be corrected as follows MSIMASK 01C0
14. 0 08F4 of Table 16 7 are split 30 Typo in Slave Select Output Control and the description for Slave Select Register Update section are corrected 32 A new note is added for SSOC and SSOTC registers a new footnote is added to SSOTC LEAD SSOTC TRAIL and SSOTC INACT bit description 33 A new paragraph is added to Receive FIFO section the description when LEC 111B is improved the CAN Bus State Information is updated in Table 20 8 34 35 36 The typo for number of CAN interrupt outputs is corrected 36 MLI receive clock max frequency is corrected 52 The formula for the timer period is corrected Trademarks TriCore is a trademark of Infineon Technologies AG We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to mcdocu comments infineon com I Cinfineon TEG Table of Contents Table of Contents 1 2 Introduction 0 o AA a 5 User s Manual System Units Part Volume 1 6 Page lO anima aa A a a 6 Page I II A UU E a K 6 Page F33 rc Bec idoni penpe He Ae O a 7 A RO 7 Page 1 46 A NO O wy age ec ee ee 8 Page 1 47 AA On ok Mev ar ae ee dct deed wy age ect eo 8 AAA O a ee dn Sek O ee ce 8 Page 2 19 duncan II eee ee ere 8 A wears EREE ak Gee eee aes ewe
15. 0000 Page 11 29 In Section 11 1 8 2 the register name EERSR must be replaced by ERRSR in the third sentence of the first paragraph first sentence of the second paragraph and within Figure 11 18 The corresponding text must be replaced by If such a transaction request lost condition occurs bit ERRSR TRLOn is set and A transaction request lost condition of DMA channel On is indicated by status flag ERRSR TRLOn which can be reset by setting bit CLRE CTLOn or CHRSTR CHOn Figure 11 18 must be replaced by CHRSTR CHOO Transaction Lost Interrupt 00 n 0 7 Transaction Interrupt 07 MCA06166_c Figure 11 18 Transaction Lost Interrupt Documentation Addendum 23 V1 2 2007 04 Cinfineon TAGG User s Manual System Units Part Volume 1 Page 11 30 In Section 11 1 8 3 the register name EERSR must be replaced by ERRSR in the first sentence of the third paragraph and within Figure 11 19 The corresponding text must be replaced by A source error of Move Engine 0 is indicated by the status flag ERRSR MEOSER Source Error Figure 11 19 must be replaced by EER EMEOSER Interrupt re EER EMEODER Interrupt pe MCA06167_c EER MEOINP Move Engine 0 Move Engine 0 Destination Error Figure 11 19 Move Engine Interrupts Documentation Addendum 24 V1 2 2007 04 Cinfineon TAGG User s Manual System Units Part Volume 1
16. 12 Port lines P4 15 4 are not available Therefore PC bit fields PC 15 4 in registers P4 IOCR4 P4_IOCR8 P4_IOCR12 are not connected Page 10 58 Bit 5 in the register image of register PCP_ES must be changed into 0 r instead of ME rh Page 10 59 The column Description for bit 5 must be corrected into Reserved read as 0 Page 10 73 The second row RCO of Table 10 12 must be replaced by the following row CNTO Counter Reload Value COPY The COPY instruction uses an implicit counter to generate multiple data transfers The CNTO value given in the instruction specifies how many data transfers are to be performed by the instruction See also Figure 10 13 on Page 10 73 CNTO Perform 1 7 data transfers 001 111 CNTO 000 Perform 8 data transfers Block Size BCOPY selects the FPI block size used for a BCOPY instruction CNTO 000 Use block size of 8 words CNTO 010 Use block size of 2 words CNTO 011 Use block size of 4 words Others Reserved Documentation Addendum 19 V1 2 2007 04 Cinfineon mene User s Manual System Units Part Volume 1 Page 10 77 Figure 10 14 must be replaced by the following figure block DATA Transfer has been changed BCOPY Instruction DATA Transfer Block size determined by CNTO field CNT1 CNT1 1 CNT1 CNT1 1 Next Instruction Figure 10 14 Counter Operation for BCOPY Instruction MCA06148
17. 21 4 Documentation Addendum 36 V1 2 2007 04 Cinfineon Page 21 116 TC1766 User s Manual Peripheral Units Part Volume 2 In the register table P5_IOCR8 and P5_IOCR12 should be updated as below Field PC8 PC9 PC10 PC11 Bits 7 4 15 12 23 20 31 28 Type rw Description Port Input Output Control for Port 5 11 8 x Port input output control for P5 8 RDATAOB TDATA1 Port input output control for P5 9 RVALIDOB TVALID1 Port input output control for P5 10 RREADYOB TREADY 1 Port input output control for P5 11 RCLKOB TCLK1 1 For coding of bit field see Table 21 9 Shaded bits and bit fields are don t care for MLI I O port control Field Bits Type Description rw Port Input Output Control for Port 5 15 12 PC12 7 4 Port input output control for P5 12 TDATAOB RDATA1 PC13 15 12 Port input output control for P5 13 TVALIDOB RVALID1 PC14 23 20 Port input output control for P5 14 TREADYOB RREADY1 PC15 31 28 Port input output control for P5 15 TCLKOB RCLK1 1 For coding of bit field see Table 21 9 Shaded bits and bit fields are don t care for MLI I O port control Page 21 117 In the register table P5_PDR should be updated as below Field Bits Type Description PDMLIO 18 16 Tw Pad Driver Mode for P5 15 P5 13 12 and P5 10 PDMLI1 22 20 rw Pad Driver Mode for P5 14 P5 11 and P5 9 8 Documentati
18. 4 Page 222807 aia AAA A ee ae ad ga 45 Documentation Addendum 3 V1 2 2007 04 Cinfineon Yeo Table of Contents Page 22 99 on ees yee ek eed eae a 46 Page 22 100 abet dad one eee ee AAA 47 Page 22 101 ub ixtatidwd oe eee ante ee en eee ee 47 Page 22 103 uc ixteaidwd oe aed ante ee ee ee ew ee 47 Page 22 104 vice xcuidad oo een ane cee ae oe aed ee 48 Pade 22 100 xx cates al dee eee ee heed ew een Y Y 48 Page 22 106 socorristas de he eek See os Bee 49 Page 22108 orar daa ds hei eee kee eam Bee 49 Page 222125 caca da E het eek See eam Cee 49 Page 222102 sven ds Meee haere ewes ee ee eee eee om Oe 49 Pages 22 173 and 22 174 errada Ea 49 Page 22 178 a td Re a a Y 49 Page 22 184 su ia a hate sees i aa a 49 Page 22 200 ar wah a hw BE aa A 50 Page 22 205 sr eave oid wash a hs Be ad 51 Page 22 209 so eae eid A BE A ad 51 Page 23 9 o tars mee wach wa doh wa hws aa a a aa a E Ra cee A 52 Page 23 90 ao a a a en eeu a eee eae anus 52 Page 23 97 aiii area ados 52 A O corsa Seas eee es 52 Page 24AT orar RO un et eure a Paes eee eee 52 Page 24 8 nissan 52 Documentation Addendum 4 V1 2 2007 04 Cinfineon reves Introduction 1 Introduction This document describes corrections changes and improvements for the two parts of the TC1766 User s Manual V1 1 2005 08 the System Units book Volume 1 and the Peripheral Units book Volume 2 These corrections will be considered with the next update of these User s Manual documents
19. 7 04 Cinfineon TEIG Table of Contents Page 9 49 to 9 50 2 eee eee 18 Page 9 55 a o u ea ae la ae ae Sa ee AA ee a 19 o een lan tee oe ea tee 19 Page 10 58 sucia at bats d tweed eee ee eee Waa ees 19 Page 10 59 ax lt b ek Di hte aac ww ee ea ae a et 19 Fage 1073 ue eater ites ae ew ek eee ee ee aan e 19 Page 1057 aaa A dew es ees cutee aad DAA 20 Page 10 90 24 cease ena O Vomit EE E oes 20 Page TIFO AA aul ieosaeen ease eu eae Se ewes toe 21 Page TFIO yeramen a a paid EE neues da 22 Page TERIO A e a tae a E EE a eos 22 Page 11 35 erasi Mince ade ieta iaaa Sa we i a Ee A ae 25 Page TIS asados a oh ba een ee ds oe da ee 25 Page 11 80 airada ha ew Sak a ee a ee 25 Page T11 rd a oo ha ee Sa a ee a ee 26 Page 12 20 sra eisai oo hoe A Sad a hw nee 27 Page 14 4 ssc cae week va ase kk A AA a 27 AAA es eee eee eae teeter ee tae aes 28 Page 10 16 Se cane dt eee eta bee wee tee ous 28 Page 16 20 to 16 25 chicken dentate past a dd 28 Page csc ee ahd seme eta ead ee eee ee te ee eae 28 Page 16 79 2e caerak eden II ee baew aus 28 Documentation Addendum 2 V1 2 2007 04 Cinfineon YEG Table of Contents 3 User s Manual Peripheral Units Part Volume 2 29 Page 17 28 ov ceed aoe ee ee A bad ea eo 29 Page 18 15 a5 lt i et A Dae ees 29 Page 18 16 a5 lt i eta awed A A bad ees 30 Page 18 17 o 40 a bee aed wwe aa ae awed 30 Page HOI 0000 paa dara ed Seales atada 31 Page 10 10 aa A AA a ca da 32 Page 10 19 ia
20. 95 88 OG5 OUT 103 96 OG6 OUT 111 104 Documentation Addendum 42 V1 2 2007 04 Cinfineon Teee User s Manual Peripheral Units Part Volume 2 Page 22 94 The first paragraph of Section 22 2 4 2 should be replaced by The output multiplexer shown in Figure 22 59 and Figure 22 61 below connects the 32 GTC output lines and the 64 LTC output lines with the I O groups 7 x 8 56 input output lines and the output groups 7 x 8 56 output lines Figure 22 61 should be updated with the below figure I O Groups Output Groups ee f foo oo om 8 8 8 8 8 8 8 8 8 8 8 8 8 8 amp LJOMG OMG OMG OMG GTC 07 00 f 00 04 08 oc wn e crc 8 OMG OMG OMG OMG 3 GTC 15 08 01 05 09 0D oO o crea 18 OMG OMG OMG GTC 23 16 02 06 0A GTCG3 8 OMG OMG OMG GTC 31 24 03 07 0B itcco 18lL fome OMG OMG OMG LTC 07 00 10 14 18 1C LTCGI 8 OMG OMG OMG OMG LTC 15 08 f 11 15 19 1D LTCG2 8 OMG OMG OMG LTC 23 16 12 16 1A 2 LTCG3 8 OMG OMG OMG 3 LTC 31 24 13 17 1B o o LTcG 8 OMG OMG OMG OMG 5 LTC 39 32 20 24 28 2C LTCG5 8 OMG OMG OMG OMG LTC 47 40 21 25 29 2D LTCGS 8 OMG OMG LT C 55 48 i 22 26 2A Output
21. DROn the source address will not be written into DADROn directly but will be buffered in the shadow register SHADROn until the start of the next DMA transaction Documentation Addendum 25 V1 2 2007 04 Cinfineon Teee User s Manual System Units Part Volume 1 Page 11 91 Figure 11 29 must be corrected as below Control Register DMA Interrupt MLI Interrupt System interrupt DMA Bus Time Out Registers Registers Registers Register DMA_CLC DMA_SRCO DMA_MLIOSRC DMA_SYSSRCO DMA_TOCTR DMA_SRC1 DMA_MLIOSRC DMA_SYSSRC1 DMA_SRC2 DMA_MLIOSRC DMA_SYSSRC DMA_SRC3 DMA_MLIOSRC DMA_SYSSRC DMA_MLI1SRC DMA_SYSSRC DMA_MLI1SRC MCA06177a Figure 11 29 DMA Implementation specific Registers Documentation Addendum 26 V1 2 2007 04 Cinfineon mene User s Manual System Units Part Volume 1 Page 12 26 Figure 12 5 must be updated with the following corrected drawing Entry in Trap Handler Routine V1 SCU_PETSR V2 NMISR yes V1 SCU_PETSR V2 NMISR A Execute Parity Error NMI Reg Handler Execute Watchdog NMI Req Handler yz Exit Trap Handler A Routine 1 This test is for the case that a parity error occurs after the first read of SCU_PETSR MCA06449a Figure 12 5 NMI Trap Handler Routine for Parity Error Handling Page 14 4 The below note must be added to the end of the last sentence of the page Note The resetting
22. Documentation Addendum V1 2 Apr 2007 1C1766 32 Bit Single Chip Microcontroller Microcontrollers _ ald Never stop thinking Edition 2007 04 Published by Infineon Technologies AG 81726 M nchen Germany Infineon Technologies AG 2007 All Rights Reserved Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics Beschaffenheitsgarantie With respect to any examples or hints given herein any typical values stated herein and or any information regarding the application of the device Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind including without limitation warranties of non infringement of intellectual property rights of any third party Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of
23. F800 05F0 y U SV E U SV Reserved F800 05F4 BE BE Reserved F800 05F8 BE E U SV 32 Reserved F800 O5FC U SV BE 1 Which Resets affect the register see Table 4 2 2 Do not read from or write to these address locations Documentation Addendum 28 V1 2 2007 04 Cinfineon Teee User s Manual Peripheral Units Part Volume 2 3 User s Manual Peripheral Units Part Volume 2 This section describes corrections for the Peripheral Units part of the User s Manual Page 17 28 Figure 17 12 should be updated with the below figure Clock Jasc Control PY P3 0 RXDOA RXD_I0 PA P3 1 ASCO RXD_11 NA TXDOA Module RXD O Kernel Px P3 12 TXD_O RXDOB PY P3 13 TXDOB Interrupt Control ASCO_RDR ASCO_TDR lt Port3 Control PN P3 9 RXD1A RXD_10 iad A2 r ASC1 RXD_I1 A2 TXD1A Module RXD O Kernel TXD_O P3 14 EIR d RXD1B TBIR mea P3 15 Interrupt AN f Control A2 TXD1B RIR ASC1_RDR DMA lt MEER MCB06211c Figure 17 12 ASCO ASC1 Module Implementation and Interconnections Page 18 15 In Figure 18 8 the description at the bottom of the figure CON PH CON PO 1 must be replaced by CON PH 0 CON PO 1 Documentation Addendum 29 V1 2 2007 04 Cinfineon TAGG User s Manual Peripheral Units Part Volume 2 Page 18 16 After the first sentence on the
24. MU_CON must be changed to MMU Configuration Register Page 2 15 The bit description of bit CPU_SRCn TOS is wrong For TOS 1 the description must be changed from Reserved to Service Provider PCP Page 2 17 In Table 2 4 the register long name for D11 D12 D13 D14 and D15 must be changed to Data Register 11 Data Register 12 Data Register 13 Data Register 14 and Data Register 15 Page 2 23 The offset address for register CMP1 must be corrected in Table 2 6 from 2200 into 2280 Documentation Addendum 8 V1 2 2007 04 Cinfineon CAOS User s Manual System Units Part Volume 1 Page 2 26 Figure 2 11 should be replaced with the below figure Program Memory Interface PMI 64 To From NN CPU PMEM CPU Interface 8 KB Data Switch ICACHE 8 amp 16 KB Interface Control SPRAM PMI Control Registers Slave Master LMB Interface Parity Control Check PMEM Program Memory in PMI ICACHE Instruction Cache To SCU To From SPRAM Scratch Pad RAM PMI Memory Parity Errors Local Memory Bus LMB Local Memory Bus CPS CPU Slave MCBO06078_c Figure 2 11 PMI Block Diagram Page 3 18 Section 3 2 2 5 Point 3 of the actions should be executed after point 5 and not after point 2 Page 4 25 The first sentence of Section 4 4 3 must be replaced by Except for different connections to serial port lines of ASCO the bootstrap
25. Multiplexer LTCG7 8 OMG OMG OMG j LTC 63 56 23 27 2B MCA06384_c Figure 22 61 Output Multiplexer The third sentence onwards for the paragraph below Figure 22 61 should be replaced by In the same way I O groups and output groups are grouped into 14 groups seven I O groups and seven output groups with 8 lines each OGO and OGO share the same physical pins similarly for OG1 and OG1 OG2 and OG2 10G3 and IOG6 share the same physical pins for inputs and outputs Documentation Addendum 43 V1 2 2007 04 Cinfineon TIG User s Manual Peripheral Units Part Volume 2 Page 22 96 The second sentence of the third bulleted point should be replaced by I O groups IOG0 to IOG6 are assigned to index variable g O to 6 and output groups OGO to OG6 are assigned to index variable g 7 to 13 Figure 22 63 should be updated with the below figure MRACTL OMCRLg OMCRHg g 0 13 To input of I O Group g or Output Group g 7 MCA06386_c Figure 22 63 Output Multiplexer Group Programmer s View Documentation Addendum 44 V1 2 2007 04 Cinfineon TC1766 Page 22 97 In Table 22 10 the input and output lines assigned for I O Groups IOG3 and Output Groups OGO to OG7 should be replaced by User s Manual Peripheral Units Part Volume 2 Table 22 8 Output Multiplexer Control Register Assignment
26. N1 5 OUT101 OG5 5 ALTINO 6 OUT86 OG3 6 ALTIN1 6 OUT102 OG5 6 ALTINO 7 OUT87 OG3 7 ALTIN1 7 OUT103 OG5 7 ALTINO 8 OUT88 OG4 0 ALTIN1 8 OUT104 OG6 0 ALTINO 9 OUT89 OG4 1 ALTIN1 9 OUT105 OG6 1 ALTINO 10 OUT90 OG4 2 ALTIN1 10 OUT106 OG6 2 ALTINO 11 OUT91 OG4 3 ALTIN1 11 OUT107 OG6 3 ALTINO 12 OUT92 OG4 4 ALTIN1 12 OUT108 OG6 4 ALTINO 13 OUT93 OG4 5 ALTIN1 13 OUT109 OG6 5 ALTINO 14 OUT94 OG4 6 ALTIN1 14 OUT110 OG6 6 ALTINO 15 OUT95 OG4 7 ALTIN1 15 OUT111 OG6 7 Page 22 209 The following attention paragraph must be added at the bottom of the page Attention Documentation Addendum 51 If the frequency of the module timer clock f prao is configured to be smaller than the control clock fo as programmed in register GPTAO_FDR or even disabled as programmed in register GPTAO_EDCTR an action initiated by a write access to a module register could be significantly delayed because the register write access is clocked by fc and the register content is evaluated by hardware using the slower or disabled module timer clock fgprao V1 2 2007 04 Cinfineon TIG User s Manual Peripheral Units Part Volume 2 Page 23 9 The formula on the bottom of the page must be corrected into 20 ADC ttperiop TRLD x 23 1 Page 23 96 Footnote 1 must be deleted from AN24 to AN31 cells Page 23 97 The below text must be inserted before Figure 23 30 For safety reasons the measurement of the
27. T26 OUTS50 SLSO17 AN26 SJ F gt P1 9 IN25 IN49 MRST1B OUT25 OUT49 AN25 J P1 8 IN24 IN48 MTSR1B OUT24 OUT48 AN24 57 R P1 2 IN18 0UT18 OUT74 AN23 7 F gt P1 1 IN17 0UT17 OUT73 AN22 57 R P1 0 IN16 0UT16 OUT72 AN21 57 R P4 3 1N31 1N55 0UT31 0UT55 SYSCLK ADOEMUX2 P1 14 lt 71 TVALIDOA OUT3 TDATA0A OUT35 1 OUT36 RCLKOA RREADYOA OUT37 1 OUT38 RVALIDOA OUT39 RDATADA OUT52 0UT28 HWCFGO IN52 1N28 P4 0 lt 4 86 OUT53 OUT29 HWCFG1 IN53 IN29 P4 1 2 OUT54 0UT30 HWCFG2 IN54 1N30 P4 2 2 88 SLSO13 SLSO03 OUT33 TREADYOA IN33 P2 1 4 75 MCP06067_c Figure 1 12 TC1766 Pinning for PG LQFP 176 2 Package Page 1 44 The pad driver class of pin HDRST is A2 instead of A1 The pad driver class of pin NMI and PORST are grouped as A2 Documentation Addendum 7 V1 2 2007 04 Cinfineon TIG User s Manual System Units Part Volume 1 Page 1 46 The footnotes 2 and 4 of Table 1 3 should be deleted Page 1 47 The following section has to be added after section 1 4 2 1 4 3 Pull Up Pull Down Behavior of the Pins Table 1 5 List of Pull up Pull down Reset Behavior of the Pins Pins PORST 0 PORST 1 All GPIOs TDI TMS TDO Pull up HDRST Drive low Pull up BYPASS Pull up High impedance TRST TCK High impedance Pull down TRCLK High impedance BRKIN BRKOUT TESTMODE Pull up NMI PORST Pull down Page 2 13 The long register name of register M
28. Timer Overflow Event Documentation Addendum 38 V1 2 2007 04 Cinfineon Teee User s Manual Peripheral Units Part Volume 2 Page 22 76 The first three sentences of the first paragraph on the top must be replaced by three extended sentences Old Normally an LTC is enabled by writing LTCCTRk EOA Enable Of Action with 0 Note that bit EOA is hardware protected Therefore any bit operation on EOA will result in a read modify write access New An LTC is enabled by writing ST byte word halfword operation LTCCTRk EOA Enable Of Action with 0 in Capture Mode or Compare Mode Because bit EOA is hardware prodected read modify write operations LDMST ST X only enable the LTC if bit EOA is modified from 1 to O in Capture Mode or Compare Mode If switching to Timer Mode the LTC cell is enabled If in Timer Mode every write operation into bit 0 7 will enable the LTC Documentation Addendum 39 V1 2 2007 04 Cinfineon TC1766 Page 22 89 User s Manual Peripheral Units Part Volume 2 The last sentence of the first paragraph should be replaced by The GPTA module provides a total of 56 input lines and 112 output lines assigned to seven I O groups IOG 6 0 and seven output groups OG 6 0 Figure 22 59 should be updated with the below figure GTC Input Multiplexer GTC Groups GTCGO GTCG1 GTCG2 GTCG3 LTC Input Multiplexer
29. UT47 OUT79 FPC INT PDL INT Clock Group Group Group CLKO SOLO PDLO CLK1 SOL 1 PDL1 CLK2 SOL2 PDL2 CLK3 SOL3 PDL3 Distribution CLK4 SOL4 INTO gt INTO Logic CLK5 SOL5 INT1 gt INT1 CLK6 INTO gt INTO INT2 gt INT2 CLK7 INT1 gt INT1 INT3 gt INT3 MCA06383_c Figure 22 60 Group Definitions For I O Line Sharing Unit Documentation Addendum 41 V1 2 2007 04 Cinfineon Page 22 91 The third and fourth paragraphs should be replaced by TC1766 User s Manual Peripheral Units Part Volume 2 An I O group combines eight GPTA I O lines connected to bi directional device pins with its input and output lines This results in seven I O groups OGO to IOG6 supporting 56 I O lines An output group combines eight GPTA output lines connected to device pins as an output This results in seven output groups OGO to OG6 supporting 56 output lines In Table 22 8 the input and output lines assigned for I O Groups and Output Groups should be replaced by Table 22 8 Group to I O lines Cell Assignment Group Module Cell Line Input Output I O Group IOGO IN O7 00 OUT 07 00 10G1 IN 15 08 OUT 15 08 IOG2 IN 23 16 OUT 23 16 lOG3 IN 31 24 OUT 31 24 10G4 IN 39 32 OUT 39 32 IOG5 IN 47 40 OUT 47 40 IOG6 IN 55 48 OUT 55 48 Output Group OGO OUT 63 56 OG1 OUT 71 64 0G2 OUT 79 72 OG3 OUT 87 80 OG4 OUT
30. as GPIO pins depending on the specific TC1766 device version Table 9 8 Reserved Port 0 Lines of TC1766 Devices TC1766 Device Versions SWOPTx Bits x 0 15 PO PO P0 5 P0 4 P0 3 PO 15 8 7 6 2 0 TC1766 user user user 1 user TC1766ED Emulation device XX 2 0 or 1 1 The PO 2 0 bits are only used in alternate boot modes see Table 4 7 If alternate boot modes are not required or used in an application PO 2 0 can also be used for user program software configuration selection purposes during a hardware reset operation or as GPIO pins 2 005 11 The USB interface of the TC1766ED is not connected to device pins 01 The USB interface of the TC1766ED is connected to JTAG I O lines 10 The USB interface of the TC1766ED is connected to P2 5 0 lines 3 0 Emulation device functionality is not available 1 Emulation device functionality is fully supported Page 9 32 The reset value for P1_lIOCR12 should be corrected as 0020 2020 Page 9 41 P2_lOCRO should not be linked to footnote 1 Page 9 42 The reset value for P2_IOCR12 should be corrected as 0000 2020 Documentation Addendum 17 V1 2 2007 04 Cinfineon TAGG User s Manual System Units Part Volume 1 Page 9 49 to 9 50 In Table 9 13 P3 12 and P3 14 Input rows should be updated as below Table 9 13 Port 3 Functions Port I O Pin Functionality Ass
31. ddendum 14 V1 2 2007 04 Cinfineon TC1766 User s Manual System Units Part Volume 1 Table 8 2 SPB Address Map of Segment 0 to 14 cont d Seg Address Size Description Access Type ment Range Read Write 10 AFE1 4000 48 Kbyte Reserved LMBBE 8 ignore AFE1 FFFF SPBBE AFE2 0000 1 Mbyte Reserved LMBBE 8 ignore AAFF1 FFFF SPBBE AFF2 0000 256 Reserved for TC 1766 AFF5 FFFF Kbyte emulation device memory AFF6 0000 624 Reserved AFFF BFFF _ Kbyte AFFF C000 16 Kbyte Boot ROM BROM access AFFF FFFF Table 8 4 LMB Address Map Seg Address Size Description Action ment Range Read Write 8 8FE1 4000 48 Kbyte Reserved LMBBET LMBBET 8FE1 FFFF 8FE2 0000 1 Mbyte Reserved LMBBET LMBBET 8FF1 FFFF 8FF2 0000 256 Kbyte Reserved for TC1766 8FF5 FFFF emulation device memory 8FF6 0000 624 Kbyte Reserved 8FFF BFFF 8FFF C000 16 Kbyte Boot ROM BROM access 8FFF FFFF Documentation Addendum V1 2 2007 04 Cinfineon mene User s Manual System Units Part Volume 1 Table 8 4 LMB Address Map cont d Seg Address Size Description Action ment Range Read Write 10 AFE1 4000 48 Kbyte Reserved LMBBET LMBBET AFE1 FFFF AFE2 0000 1 Mbyte Reserved LMBBET LMBBET AFF1 FFFF AFF2 0000 256 Kbyte Reserved for TC1766 AFF5 FFFF emu
32. e 20 27 should be updated with the below figure Interrupt Pointer Control 4 bit Interrupt Pointer Interrupt Output Control Interrupt Interrupt 16 72 Request Source Outputs Inputs Output INT_Om gt 1 INT_OO gt 1 INT_O1 Interrupt Wiring Matrix gt 1 INT_O4 gt 1 INT_O5 MCA06284_c Figure 20 27 Interrupt Compressor 35 V1 2 2007 04 Cinfineon Towne User s Manual Peripheral Units Part Volume 2 Page 20 118 The first sentence of the page must be replaced by Each of the six interrupt outputs INT_Om of the MultiCAN module is controlled by its service request control registers Page 21 2 The bullet paragraph Programmable baud rate under Features must be changed as follows e Programmable baud rates MLI transmitter baud rate max fy 2 40 0 Mbit s Y 80 MHz module clock MLI receiver baud rate max fy Page 21 30 The following sentence must be added at the end of section 21 1 5 MLI Receiver Operation The MLI receiver is able to operate with a maximum receive clock RCLK frequency up to the frequency of the module clock ful Page 21 79 In the register table of register RPXBAR the row for bits 3 0 should be deleted The range for ADDR bit field must be extended to 31 0 Page 21 108 The following paragraph with the formula must be added after the last paragraph The receiver baud rate is defined by the following formula Baud ratercikmax ui
33. e 22 64 GTC Input Multiplexer Documentation Addendum 46 V1 2 2007 04 Cinfineon TEIGE User s Manual Peripheral Units Part Volume 2 Page 22 100 The second sentence of the first paragraph should be replaced by GTC input Multiplexer Group are grouped into seven IOGs IOG 6 0 with seven blocks of eight lines each and eight LTC groups LTCG 7 0 with 8 cells each Page 22 101 The second bulleted point should be replaced by Index n is a group number I O groups IOG 3 0 have group number 0 I O groups IOG 6 4 have group number 1 local timer cell groups LTCG 3 0 have group number 2 Local Timer Cell Groups LTCG 7 4 have group number 3 and the FPC INT group has group number 4 The last sentence of the next paragraph should be replaced by For example based on Figure 22 64 each of the eight GTC input multiplexer output lines to GTC group GTCG2 is connected via five GIMGn2 n 0 4 with the eight outputs of two I O group IOG2 and 10G6 two LTC groups LTCG2 and LTCG6 and the FPC INT group Page 22 103 In Table 22 11 the text OG3 of GTCG2 row should be replaced by IOG6 Documentation Addendum 47 V1 2 2007 04 Infineon da User s Manual Peripheral Units Part Volume 2 Page 22 104 Figu
34. e replaced with AFEO 55F4 in Cycle 2 Documentation Addendum 13 V1 2 2007 04 Cinfineon td User s Manual System Units Part Volume 1 Page 7 41 The first paragraph of column Description for bit FABUSY should be changed as follows This status flag is a flag for test purposes that should not be used by software drivers It indicates whether any of the Flash arrays is in busy state FABUSY is cleared by any reset operation Page 7 49 to 7 51 The following footnote must be added to the following FCON bits and bit fields WSPFLASH WSECPF WSWLHIT WSDFLASH and WSECDF 1 These bits and bit fields can be changed at any time also with code fetched from Program Flash A modified wait state parameter will be taken into account with the next corresponding access Page 8 5 to 8 7 and 8 13 to 8 14 The respective address ranges in bold for Segment 8 and 10 of Table 8 2 and Table 8 4 must be updated as the following Table 8 2 SPB Address Map of Segment 0 to 14 Seg Address Size Description Access Type ment Range Read Write 8 8FE1 4000 48 Kbyte Reserved LMBBE amp LMBBE 8FE1 FFFF SPBBE 8FE2 00004 1 Mbyte Reserved LMBBE amp LMBBE 8FF1 FFFF SPBBE 8FF2 00004 256 Reserved for TC1766 B8FF5 FFFF Kbyte emulation device memory SFF6 00004 624 Reserved BFFF BFFF Kbyte 8FFF C000 16 Kbyte Boot ROM BROM access 8FFF FFFF Documentation A
35. eaea AAA AA a cta da 32 A E ae eden eo eee ce hee ae Re 32 Page 10 20 aaa nei tae eae AAA ca ds 32 Page 18 29 A E ee ea sou 32 Page 18 30 A IA 32 Page 18 30 sra baie ees ola dd a do a a ea A 32 Page 19 20 isa a a A ae ee a a a 33 Page 19 42 ira a ha o eee a a eee 33 Page 20 49 iia a oo ha do he a a eee 33 Page 20 50 scsi daar pe air he ot i OR he a ee eB 33 Page 20 54 toa gee erie Eten era eee eee eae tau 33 Page AA ence etea aad ee eue bee ee tee ses 33 Page 20 83 ai e E bee EE ea ade 33 Page 205109 ged es ob ede e e a e E E E EE AEE 34 Page 20 116 bie ion oe A E D EE nese 34 Page 20 sucursal 35 Page 20 118 cc ea Ea Aia ene acia de 36 Page A Se Sete ie heath ee asain BW aE A ons shows hed ee ence A da 36 Page 21 30 esa is Sa ea A ms dae ae ee he Ce eee 36 Page 21 79 sacks det de 4 occ Bhar arose II 36 Page 21 108 0 a Moca on Se Sa Ae wens cd wh pec ee ee a a 36 Page 21 116 0 pia vd oh me Wee woe ae dew ee eee 37 Page 2 leila has o a ro eae sea bs detec 4b do a det i 37 Page 22 00 a aiaa se a ala Ea dde dadi jad a bar adn Da aa e 38 Page 22 00 a sia aa na ala bios pde ja a ii e aa a nae x 38 Page 22 70 a eia asa na aa e a di aa nda ja la i De o s 38 Page 22274 cenar brad rd edad da ead a sd a ane e 38 IIA A 38 A AAA II 38 Page 22 70 urea dove riega riada di 39 Page 22 09 A O 40 Pade 22 90 urinarios dianas wed 41 Page 22987 sa ttitutav aad ea nee eee awe ean sd wed ude wed 42 Page 22 94 uri diria caian 43 Page 22790 dra E E RR od 4
36. f the pattern detection changes Page 5 48 Figure 5 11 should be replaced with the figure shown as below The below note must be added to the end of the last sentence of the page SCU ASCO _REQ gt To DMA Controller ASCI REQ gt To DMA Controller SSCO_REQ To DMA Controller SSC1_REQ gt To DMA Controller SELO to SEL3 are bit fields of the DMA Request Select Register MCA06453 Figure 5 11 DMA Request Selection Logic Note By default TIR line is selected for both ASC and SSC modules For RIR line to be selected SELO DMARS to SEL3 DMARS should be set accordingly See DMARS register Page 5 58 The bit description of ENON on the bottom of the page must be corrected to 1 Setting of EMSF by hardware is enabled Documentation Addendum 11 V1 2 2007 04 Cinfineon do User s Manual System Units Part Volume 1 Page 5 64 The sentence This bit is set with any reset in the description of bit PARAV must be changed into This bit is set after a power on reset Page 6 4 Figure 6 2 should be replaced with the below figure Bus Cycle 1 2 3 Request Address Data Request Address Data Grant Cycle Cycle Address Data MCA06109_c Transfer 2 Transfer 3 Figure 6 2 Basic LMB Transactions Page 6 6 In the second paragraph of Section 6 2 3 second bulleted point the register short name for LMB Error Data Registers shou
37. lation device memory AFF6 0000 624 Kbyte Reserved AFFF BFFF AFFF C000 16 Kbyte Boot ROM BROM access AFFF FFFF 1 Cached area 2 Non cached area Page 8 17 In Table 8 5 the four of Double word column and CRAM and PRAM rows must be replaced by w CRAM must be replaced with CMEN Footnote 1 must be added to the PMI and DMI memory cells as The module also supports LMB 2 Word and 4 Word Block read and write accesses Footnote 2 must be added to the PCP memory cell as The module also supports FPI 4 Word and 8 Word Block read and write accesses Page 9 15 The following sentence must be added at the end of paragraph Port O is a general purpose 16 bit software later Note that some of the PO 7 0 lines are used for configuration purposes too see Page 9 25 Page 9 25 Section 9 3 3 3 must be changed as described below 9 3 3 3 Reserved Port 0 Pins Depending on the TC1766 device version used in an application several Port O lines meaning several SWOPT bits are reserved and cannot be used for user system purposes during a HDRST reset operation Table 9 8 defines the reserved Port 0 lines indicated by O or 1 as well as the Port O lines that can be used by a user program Documentation Addendum 16 V1 2 2007 04 Cinfineon td User s Manual System Units Part Volume 1 indicated by user for software configuration selection or
38. ld be replaced with LEDATL LEDATP Page 6 7 In the bit description of bit LEC the text When writing a 0 to LEC must be replaced by When writing a 1 to LEC Page 6 19 The second sentence of the first paragraph of Section 6 4 3 should be replaced with The requesting FPI Bus master releases the FPI Bus for one cycle after the FPI Bus transaction request in order to allow the FPI Bus slave to indicate if it is ready to handle the requested FPI Bus transaction Documentation Addendum 12 V1 2 2007 04 Cinfineon renee User s Manual System Units Part Volume 1 Page 6 20 Figure 6 7 should be replaced with the below figure Bus Cycle Transfer 1 Transfer 2 Request Address Data Grant Cycle Cycle Address Data MCA06109_c Transfer 3 Figure 6 7 Basic FPI Bus Transactions Page 6 29 Figure 6 12 should be replaced with the below figure SBCU_DBCNTL CONCOM2 CONCOM1 CONCOMO Ld Address 1 Trigger AND OR Trigger Selection Address 2 Trigger AND OR Selection Signal Status Trigger Bcu Breakpoint Trigger AND OR Selection Grant Trigger Tl MCA06117_c Figure 6 12 BCU Breakpoint Trigger Combination Logic Page 7 16 In Table 7 7 32 bit Load Page Buffer Command the DFLASH address for DB1 AFE1 55F4 must be replaced with AFE1 55F0 in Cycle 1 and DFLASH address for DBO AFEO 55F0 must b
39. ociated Reg Port I O Control Select Pin I O Line Reg Bit Field Value P3 12 General purpose input P3_IN P12 P3_IOCR12 OXXX CAN node 0 receive input 0 RXDCANO mele CAN node 1 receive input 1 ASCO input Asynchronous RXDOB Mode Synchronous Mode O General purpose output P3_OUT P12 1X00 ASCO output Synchronous RXDOB 1X01 Mode ASCO output Synchronous RXDOB 1X10 Mode Reserved 1X11 P3 14 General purpose input P3_IN P14 P3_ IOCR12 OXXX CAN node 1 receive input 0 RXDCAN1 PC14 CAN node 0 receive input 1 ASC1 output RXD1B Asynchronous Mode Synchronous Mode O General purpose output P3 OUT P14 1X00 ASC1 output RXD1B RXDO Synchronous Mode ASC1 output RXD1B RXDO Synchronous Mode Reserved 1 The ALT1 and ALT2 for this pin are connected together There are no dependencies Either one can be chosen In Table 9 13 the text of the associated Reg I O Line TCDOB of P3 13 with P3_lOCR12 PC13 1X10 must be changed to TXDOB Documentation Addendum 18 V1 2 2007 04 Cinfineon mene User s Manual System Units Part Volume 1 Page 9 55 In Table 9 15 the text of Pin Functionality SCU input of Pin 4 3 with P4_IOCRO PC3 1X11 must be replaced with SCU output In Table 9 16 P4_IOCRO should not be linked to footnote 1 Page 9 57 Section 9 7 3 3 should be updated as below 9 7 3 3 Port 4 Input Output Control Register x x 4 8 and
40. of the ENDINIT bit takes some time Accesses to Endinit protected registers after the resetting of the ENDINT bit must only be done when ENDINIT is really reset As a solution WDT_CONO the register with the ENDINIT bit should be read back once before Endinit protected registers are accessed the first time after ENDINIT has been reset Documentation Addendum 27 V1 2 2007 04 Cinfineon do User s Manual System Units Part Volume 1 Page 16 15 The read and write access modes for address location F000 0804 of Table 16 7 must be changed from nBE to BE Page 16 16 The Reserved column for address location FOOO 0850 to FOOO 08F4 of Table 16 7 must be separated to two different rows of access rights The read and write access rights for FOOO 0850 F000 0854 are both nBE and F000 0858 F000 08F4 are both BE Page 16 20 to 16 25 The write accesses for all Px_OMR registers x 0 5 are corrected from U SV into U SV 32 Page 16 69 The long name of register MMU_CON must be changed to MMU Configuration Register Page 16 79 The contents for the short name description and reset value columns for Table 16 26 at address locations F800 05F0 F800 O5F8 and F800 O5FC must be replaced as shown in Table 16 26 Table 16 26 Address Map of PMU Short Name Description Address Access Mode Reset 1 Read Write Value Program Memory Unit PMU Reserved
41. on Addendum 37 V1 2 2007 04 Cinfineon mene User s Manual Peripheral Units Part Volume 2 Page 22 60 The first three sentences of the first paragraph on the top must be replaced by three extended sentences Old Normally a GTC is enabled by writing GTCCTRk EOA Enable Of Action with 0 Note that bit EOA is hardware protected Therefore any bit operation on EOA will result in a read modify write access New A GTC is enabled by writing ST byte word half word operation GTCCTRk EOA Enable Of Action with 0 Because bit EOA is hardware protected read modify write operations LDMST ST X SWAP only enable the GTC if bit EOA is modified from 1 to 0 Page 22 69 In the first sentence the wording adjacent GTCs must be replaced by adjacent LTCs Page 22 70 Fourth bullet paragraph in section Free Running Timer Mode GTCkOUT must be replaced by LTCkOUT Page 22 71 Second bullet from the top GTCkOUT must be replaced by LTCKOUT Third bullet paragraph in section Compare Mode GTCkOUT must be replaced by LTCkOUT The last note paragraph must be deleted Page 22 74 Paragraph above the figure GTCs must be replaced twice by LTCs Paragraph below the figure title paragraph GTCCTRk OCMO must be replaced by LTCCTRk OCMO Page 22 75 The header text Local Capture or Compare Event of the second column in Table 22 4 must be replaced by Local Capture Compare or
42. ould be replaced by In the TC1766 the seven I O groups and three output groups of GPTAO with their input lines IN 55 0 and output lines OUT 79 0 are assigned to five 8 bit port groups and two 4 bit port groups as shown in Figure 22 75 Figure 22 75 should be updated with the below figure Port Control OUT 79 0 from GP TAO 8 15 CA 8 15 Tock C 71 64 8 7 01 K gt 7 4 P4 11 8 K 31 24 1063 31 24 1063 55 48 10G6 4 55 48 10G6 P4 3 0 K gt MCA06398_c Figure 22 75 I O Port Line Assignment Documentation Addendum 50 V1 2 2007 04 Cinfineon TC1766 User s Manual Peripheral Units Part Volume 2 Page 22 205 The following sentence should be added above Table 22 22 Table 22 22 also shows the assignment of the GPTA module s four OGx output group lines OGx y to the output signals OUT 111 80 Table 22 22 GPTAO to MSC Interconnection Assignment MSCO Assigned MSCO Assigned Input Line GPTAO Output Line Input Line GPTAO Output Line ALTINO O OUT80 OG3 0 ALTIN1 0 OUT96 OG5 0 ALTINO 1 OUT81 OG3 1 ALTIN1 1 OUT97 OG5 1 ALTINO 2 OUT82 OG3 2 ALTIN1 2 OUT98 OG5 2 ALTINO 3 OUT83 OG3 3 ALTIN1 3 OUT99 OG5 3 ALTINO 4 OUT84 OG3 4 ALTIN1 4 OUT100 OG5 4 ALTINO 5 OUT85 OG3 5 ALTI
43. re 22 67 should be updated with the below figure LTC Groups LTCGO LTCG1 LTCG2 LTCG3 LTCG4 LTCG5 LTCG6 LTCG7 LTC o7 00 LTC 15 08 LTC 23 16 LTCT31 24 LTC 39 32 LTC 47 40 LTC 55 48 Lreres 56 8 8 8 8 8 8 8 8 LIMG 04 LIMG LIMG 01 05 LIMG LIMG 02 06 1 a 2 LIMG LIMG O 03 07 e LIMG 14 LIMG LIMG 11 15 LIMG LIMG 12 16 gt LTC LIMG Input 24 Multiplexer 7 2 LIMG LIMG 3 21 25 g LIMG LIMG O 22 26 LIMG LIMG 23 27 8 LIMG LIMG LIMG LIMG LIMG LIMG LIMG LIMG ak FZ o Fla PA Flow Fla PA s Fos HA 2 PDL 3 0 8 LIMG LIMG LIMG LIMG LIMG LIMG LIMG LIMG NTB HN a FT a FT e FPL a MA a MA as HA ss HA 7 MCA06390_c Figure 22 67 LTC Input Multiplexer Page 22 105 The second sentence of the first paragraph should be replaced by IOGs and GTCs are grouped into seven lOGs IOG 6 0 with seven blocks of eight lines each and four GTC groups GTCG 3 0 with 8 cells each Documentation Addendum 48 V1 2 2007 04 Cinfineon Towne User s Manual Peripheral Units Part Volume 2 Page 22 106 The second bulleted point of the first paragraph should be replaced by Index n is a group number I O groups IOG 3 0 have group number 0 I O groups IOG 6 4 have group number 1 Global Timer Cell Groups GTCG 3 0 have group number 2 clock bus lines CLK 7 0 have group number 3 and the PDL INT group has group number 4 The last sentence of the next paragraph should be replaced by
44. t MCA06154c Figure 11 6 Channel Request Control The last sentence of the second last paragraph should be replaced with A software request can be generated by setting bit STREQ SCHOn Page 11 16 The paragraphs below When CHRST CHOn is set to 1 must be replaced by the following paragraphs e Bits TRSR HTREOn TRSR CHOn ERRSR TRLOn INTSR ICHOn INTSR IPMOn WRPSR WRPDOn WRPSR WRPSOn CHSROn LXO and bit field CHSROn TCOUNT are reset e Source and destination address register will be set to the wrap boundary SHADROn will be cleared e All automatic functions are stopped for channel On Documentation Addendum 22 V1 2 2007 04 Cinfineon do User s Manual System Units Part Volume 1 A user program must execute the following steps for resetting a DMA channel 1 If hardware requests are enabled for the DMA channel On disable the DMA channel On hardware requests by setting HTREQ ECHOn 0 2 Writing a 1 to CHRST CHOn 3 Waiting polling until CHRST CHOn 0 A user program should execute the following steps for restarting a DMA channel after it was reset 1 Optionally re configuring the address and other channel registers 2 Restarting the DMA channel On by setting HTREQ ECHOn 1 for hardware requests or STREQ SCHOn 1 for software requests The value of CHCROn TREL is copied to CHSROn TCOUNT when a new DMA transaction is requested and shadow address register contents is not equal 0000
45. that device or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered 1C1766 32 Bit Single Chip Microcontroller Cinfineon Never stop thinking TC1766 Documentation Addendum Revision History V1 2 2007 04 Previous Version V1 1 Page Subjects major changes since last revision 7 Figure 1 12 is updated 8 The register long names for MMU_CON and D11 to D15 are corrected 10 The desription for CRC generation and error checking is improved the typo is corrected for EICRO RENO EICRO REN1 EICR1 REN2 and EICR1 REN3 11 The typo of bit description GEEN1 is corrected 19 The bit name and access type is corrected for bit 5 of PCP_ES register the instruction field definition of Table 10 12 is updated 20 Figure 10 14 is updated the typo in the syntax description of the ST PI instruction of the PCP is corrected 21 The typo in Figure 11 5 is corrected 22 The description for Channel Reset Operation is improved 23 The typo in Transaction Lost Interrupt section is corrected 24 The typo in Move Engine Interrupt section is corrected 28 The read and write access modes for address location FOOO 0804 of Table 16 7 are corrected the reserved column for address location F000 0850 to F00
46. top of this page the following sentence must be added With a TB write operation all timing parameters stored in register SSOTC as well as the SSOC register are latched and remain valid for the consecutive transmission In the first line of the paragraph below Slave Select Output Control the text SSOC OENn 0 must be replaced by SSOC OENn 1 Page 18 17 In the first line below heading Slave Select Register Update the text in brackets with the activation of SLSOn must be replaced by the text with the TB register write operation Documentation Addendum 30 V1 2 2007 04 Cinfineon maize User s Manual Peripheral Units Part Volume 2 Page 18 18 Figure 18 11 should be updated with the below figure N TEN Transmit Error EFM SETTE EFM CLRTE Set Reset CON REN STAT RE Receive Error EFM SETRE ae T Reset F Error EFM CLRRE Interrupt EIR CON PEN Phase Error Set E g EFM SETPE Set l EFM CLRPE Reset CON BEN Baud Rate Error Set E STAT BE EFM SETBE Set EFM CLRBE Reset MCA05789_ Figure 18 11 SSC Error Interrupt Control i 3 E Documentation Addendum 31 V1 2 2007 04 Cinfineon TAGG User s Manual Peripheral Units Part Volume 2 Page 18 19 In the first note which is located at the upper part of the page the text CON REN 1 must be replaced by CON AREN 1
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