SH7455 Group, SH7456 Group User`s Manual Hardware Errata Rev.A
Contents
1. 1 PL2 to PL6 PL8 PL9 Re Page 2 of 3 sKENESAS RENESAS TECHNICAL UPDATE TN SH7 A827A E Date December 27 2011 Table 38 25 RSPI Timing Incorrect description corrected Error Adds Table 38 25 setup time 38 23 RSPI Timing REV A Correct Item Max Figures setup time 38 23 Adds 38 27 Table 38 28 Table 38 28 DRI Timing When Special Mode is On Incorrect by DRI Timing description corrected REV A When Special Error Mode is On DIN3 DIN4 sampling edge tar ns 38 25 to undefined time before 38 28 DIN1 initialization level release when direct reset is selected DIN3 DIN4 sampling edge tbr 12 ns undefined time before DIN1 initialization level release Correct DIN3 DIN4 sampling edge tar ns 38 25 to undefined time before 38 28 DIN1 initialization level release DIN3 DIN4 sampling edge tbr 12 ns undefined time after DIN1 initialization level release Adds 38 28 Figure 38 28 Figure 38 28 Minimum Edge Count at DIN1 Initialization Level in by Minimum Edge Delayed Reset Mode Minimum Width at Initialization Level Incorrect REV A Count at DIN1 description corrected Initialization Error DINn n 2 3 4 Level in Correct DINn n 3 4 Delayed Reset Mode Adds 38 34 Table 38 34 Table 38 34 AUDR Module Timing Vcc 5 0V Incorrect description by AUDR Module corrected REV A Timing Error Vcc 5 0V mre Pai e time before AUDRCLK AUDRD Correct mamma ase e e e time after AUDRCLK AU2. Status Vector Register FRCCSV corrected y 32 76 REVA Status Vector Register Correct Set to B 000000 when leaving HALT state Table 38 6 DC Characteristics Output Level Voltage When 3 3 V is Used with Driving Ability Set to Increased Incorrect description corrected Error Output PAO to PA13 PBO PB1 PB3 VoH Vee Il V high level PCO to PC3 PC5 PC6 PC14 voltage PDO to PD10 PE15 PFO PF1 normal PF4 PF5 PGO to PG4 PHO to output and PH15 PJO to PJ7 PJ10 to PJ15 driving PKO PK5 PK6 PK8 to PK14 ability 1 PL2 to PL6 PL8 PL9 Correct Output PAO to PA13 PBO PB1 PB3 Von Vcc 0 5 V Table 38 6 high level PCO to PC3 PC5 PC6 PC14 DC voltage PDO to PD10 PE15 PFO PF1 Characteristics normal PF4 PF5 PGO to PG4 PHO to Output Level output and PH15 PJO to PJ 7 PJ10 to PJ15 Adds Voltage driving PKO PK5 PK6 PK8 to PK14 by 38 6 ge ability PL2 to PL6 PL8 PL9 REV A When 3 3 Vis Used with Sette item Ts yimbo Ma e n Output PAO to PA13 PBO PB1 PB3 VoL V HCI Ge eC low level PCO to PC3 PC5 PC6 PC14 voltage PDO to PD10 PE15 PFO PFI1 normal PF4 PF5 PGO to PG4 PHO to output and PH15 PJO to PJ7 PJ10 to PJ15 driving PKO PK5 PK6 PK8 to PK14 ability 1 PL2 to PL6 PL8 PL9 Correct Output PAO to PA13 PBO PB1 PB3 VoL 0 4 V low level PCO to PC3 PC5 PC6 PC14 voltage PDO to PD10 PE15 PFO PF1 normal PF4 PF5 PGO to PG4 PHO to output and PH15 PJO to PJ 7 PJ 10 to PJ15 driving PKO PK5 PK6 PK8 to PK14 ability
3. DRD Adds 38 35 Table 38 35 Table 38 35 AUDR Module Timing Vcc 3 3V Incorrect description by AUDR Module corrected REV A Timing Error Vcc 3 3V AUDRD output delay td AUDRCLKH ns 38 38 time before AUDRCLK AUDRD Correct Item Symbol AUDRD output delay td AUDRCLKH ns 38 38 time after AUDRCLK AUDRD R Page 3 of 3 lt ENESAS
4. Date 12 27 2011 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product Document SH7455 Group SH7456 Group User s Manual Information Hardware Errata Rev A Category Technical Notification SH7455 Group SH7456 Group User s Manual Hardware Rev 1 10 ROLUHOO30E J 0110 Applicable Product Reference SH7455 Group SH7456 Group Document Since we changed the following contents of SH7455 Group SH7456 Group User s Manual Hardware Rev 1 10 Published on September 22 2011 we announce you Please use attached errata in the case of use of SH7455 Group SH7456 Group User s Manual Hardware Rev 1 10 Appending Document SH7455 Group SH7456 Group User s Manual Hardware Rev 1 10 errata REV A 2 sheets c 2011 Renesas Electronics Corporation All rights reserved Page 1 of 3 lt CENESAS RENESAS TECHNICAL UPDATE TN SH7 A827A E Date December 27 2011 In the following the portion of net credit or an underline is a portion with an addition change Incorrect description corrected the 12 line Adds 25 4 6 3 Error 4 To stop receiving when MST bit 1xx set RCVD bit in the by 25 23 Receive REV A Operation Correct 4 To stop receiving when MST bit 1 set RCVD bit in the CCR1 register to 1 then read the ICDRR register ade 32 7 1 Description of the bit 29 to 24 PSL5 to PSLO bit in the FlexRay CC b FlexRay CC
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