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iSBC 80/05 SINGLE BOARD COMPUTER HARDWARE

1. Connect BPRN to ground in single master systems 2 10 SBC 80 05 Preparation for Use Table 2 6 Multibus Signal Functions SIGNAL FUNCTIONAL DESCRIPTION ADRO ADRF BCLK BPRN BPRO BREQ BUSY CCLK DATO DAT7 INIT INTO INT7 IORC IOWC MRDC MWTC XACK Address These 16 address lines transmit the address of the memory location or I O port to be accessed ADRF is the most significant bit Bus Clock Used to synchronize bus control circuit on all master boards BCLK from the SBC 80 05 has a period of 101 72 nanoseconds 9 8304 MHz frequency with a 35 65 percent duty cycle Bus Priority In Indicates to a particular master board that no higher priority master board is requesting use of the bus BPRN is synchronized with BCLK Bus Priority Out In serial daisy chain priority resolution schemes BPRO must be connected to the BPRN input of the master board with the next lower bus priority Bus Request Used with a parallel bus priority resolution scheme to indicate that a particular master board requires use of the bus for one or more data transfers BREQ is synchronized with BCLK Busy Indicates that the bus is in use and prevents all other master boards from gaining control of the bus BUSY is synchronized with BCLK Constant Clock Provides a clock signal of constant frequency 9 8304 MHz for use by system boards CCLK from the SBC 80 05 coincides with BC
2. e on Service Inf SBC 80 05 SRE AD REN ST cux 2 1 CHNG rm SEF SEPARATE PARTS LISTAND WIRE UST SEE HISTORY FOR PREVIOLS REVISIONS 5 2 3345 ZONE fb y iu Vi 5 p L3 ig tu unu Np NAH o anna o d 6 Q a O n E gt 1 ngunt apaga o O Oo o um 108808 sandy r Q o panam X e 6 9 glo d amp Q tit m d finned gnumaagnm O ine lt EN t a nnpaa o o p yananug O o ug e 26 a 190000 N PLACES S PLACES puni Vu BOOBS RARE 3 Til sS T i oc o c dcm ded i f lt w oe 5 Bes lt lt 5 LE an Gaoonee 8n mE ota te ae ioa 000 A pot eE a ar s x oanpart 88 Je Poly GT g got EC te 8 BH nna a N dena Te ps Oe c Ru o x 2 3 PRINTED WIRING ASSY SINGLE BOARD AAi COMPUTER 2 AN ome sr 4 aP DETAIL A 5 D 5 LOCATION AIS SO THAT PADS ARE FREE OF LABEL AND ADHESIVE S d z
3. drivers and terminators to provide the required sink current polarity and drive termination characteristics for each application The 22 programmable I O lines and single ground lines are brought out to a 50 pin edge connector J1 that mates with flat woven or round cable The SBC 80 05 includes the resources for supporting a variety of OEM system requirements For those appli cations requiring additional processing capacity and the benefits of multiprocessing i e several CPU s and or controllers logically sharing systems tasks with communi cation over the Multibus the SBC 80 05 provides full bus arbitration control logic This control logic allows up to three bus masters i e any combination of SBC 80 05 SBC 80 20 DMA controller diskette controller etc to share the Multibus in serial daisy chain fashion or up to 16 bus masters to share the Multibus using an ex ternal parallel priority resolving network The Multibus arbitration logic operates synchronously with the bus clock which is derived from the SBC 80 05 or can be optionally generated by some other bus mas ter Data however is transferred via a handshake be tween the controlling master and the addressed slave module This arrangement allows different speed con trollers to share resources on the same bus and trans fers via the bus proceed asynchronously Thus the transfer speed is dependent on transmitting and receiving devices only This design pr
4. i iy Preparation for Use SBC 80 05 ports to the appropriate pins J1 as listed in line pairs are used table 2 9 The transmission path from the SBC 80 05 to the parallel I O ports should be limited to 3 meters 10 a Cable flat 50 conductor 3M 3306 50 feet maximum The dc characteristics of the SBC 80 05 t with und plane 3M parallel I O ports are presented in table 2 11 The fol b Cable flat 50 conductor with gro plane i 380 50 lowing bulk cable types or equivalent are recommended for interfacing with the parallel I O ports assuming 25 c Cable woven 25 pair 3M 3321 25 Table 2 9 Connector J1 Pin Assignments FUNCTION EI FUNCTION Port 02 bit 3 GND Port 02 bit 2 GND Port 02 bit 1 GND Port 02 bit 0 GND Port 03 bit 3 GND Port 03 bit 2 Port 01 Strobe GND Port 03 bit 1 Port 01 Buffer Full GND Port 03 bit 0 GND Reserved TTL level SOD Serial Out Data TTL level SID Serial In Data GND GND Port 03 bit 4 Port 02 Buffer Full 2 Port 02 bit 7 GND 3 GND Port 03 bit 5 Port 02 Strobe 4 Port 02 bit 6 GND 5 GND TTL level SOD Serial Out Data 6 Port 02 bit 5 GND 7 GND TTL level SID Serial In Data 8 Port 02 bit 4 GND GND Port 01 bit 7 GND Port 01 bit 6 GND Port 01 bit 5 GND Port 01 bit 4 GND Port 01 bit 3 GND Port 01 bit 2 GND Port 01 bit 1 GND Port 01 bit O GND EXT INTR1 E
5. iSBC 80 05 SINGLE COMPUTER HARDWARE REFERENCE MANUAL Manual Order Number 9800483 03 Copyright 1977 1980 Intel Corporation Intel Corporation 3065 Bowers Avenue Santa Clara California 95051 This manual provides general information installation programming information principles of operation and service information for the Intel SBC 80 05 Single Board Computer Additional information is available in the following doc ments Intel MCS 85 User s Manual part no 121506 e Intel 8080 8085 Assembly Language Programming Manual part 98 301 Intel MULTIBUS Interfacing Application Note A P 28 111 CHAPTER 1 GENERAL INFORMATION Introduction Description System Expansion System Software Development Equipment Supplied I Equipment Required But Not Supplied Specifications CHAPTER 2 PREPARATION FOR USE Introduction Unpacking and n Installation Considerations User Furnished Components Power Requirements Cooling Requirements Physical Dimensions Component Configuration RS232C Serial Input Output Line Driver Receiver Connector TTL Level Serial aul O iat Parallel Input Output Ports Input Port Terminators Output Port Drivers Read Only Memory Power Supply Filters Alternative 5 V Input Jumper Configuration CPU Interrupts TRAP Interrupt RST 7 5 Interrupt i RST 6 5 and 5 5 Multibus Interrupts Multibus Configuration Signal Characteristics Serial Priority Resol
6. writers and other 20 mA current loop equipment an Intel SBC 530 Teletypewriter TTY Adapter or equiva lent is required Refer to Appendix B Figure 2 8 illustrates the cabling required for inter facing connector J2 to a TTL level serial I O device the dc characteristics of the TTL serial I O port are given in table 2 11 Notice in figure 2 8 that the transmission path from J2 to the TTL device connector should be SBC 80 05 Preparation for Use limited to 3 meters 10 feet The TTL level serial I O 2 32 PARALLEL I O WIRING device can also be interfaced to the SBC 80 05 via connector J1 Refer to paragraph 2 32 and table 2 9 The individual wires connected to 11 for TTL level The SBC 80 05 interfaces to the three parallel I O ports serial I O should be two pair of wires of the cable used via connector J1 Using 50 conductor cable and a mating for interfacing the parallel I O channels connector for J1 table 2 1 item 4 interface the para MOLEX 09 50 7071 RS232C CONNECTOR RS232C SERIAL OUT DATA SOD RS232C SERIAL IN DATA SID TO P3 OF TO SBC 80 05 J2 RS232C READER CONTROL SBC 530 50 FEET 45 25 MAXIMUM Figure 2 7 RS232C Serial I O Device Interface Cabling MOLEX 09 50 7071 CONNECTOR DENOTES TWISTED PAIR AS REQUIRED TTL LEVEL SERIAL IN DATA SID TO SBC 80 05 TOTTL LEVEL J2 SERIAL 1 O DEVICE Figure 2 8 TTL Level Serial I O Device Interface Cabling 2 17
7. 1 27 0 50 inch 2 8 COMPONENT CONFIGURATION Instructions for installing various components on the SBC 80 05 to satisfy a particular configuration require ment are presented in following paragraphs The fol lowing are recommended for installing those compo nents that must be soldered in place a Ungar or equivalent soldering iron with a 40W heating element and pencil shaped tip b Multicore rosin flux 60 40 solder After the component is soldered in place clean all traces of flux from the soldered area using Freon TF Degreaser or equivalent 2 9 RS232C SERIAL INPUT OUTPUT The SBC 80 05 can employ RS232C or TTL level serial I O operation but not both simultaneously If RS232C serial I O operation is to be used install the line driver line receiver and connector as described in following paragraphs Preparation for Use SBC 80 05 Table 2 1 User Furnished and Installed Components NO ITEM DESCRIPTION USE l SBC 604 2 SBC 614 Connector mates with P1 4 Connector mates with J1 5 Connector J2 Connector J3 Modular Backplane and Card cage Includes four slots with bus terminators See figure 5 3 Provides power inputs and Multibus interface between SBC 80 05 and three addi tional boards in a multiple board system Provides four board exten sion of SBC 604 Modular Backplane and Card cage Includes four slots with out bus terminator
8. B A L2 A C B A OFFH D 34H WAIT L3 D 36H WAIT A B B A 40H OCOH DELAY D 38H WAIT A 40H D 76H WAIT woe Mot Nee wot wee Nee wee woe Ne 6 wee we t woe we wo x Nes SET UP FOR START BIT INSTRUCTION SET COUNTER FOR NUMBER OF DATA BITS BEGIN START BIT IF DATA IN C DON T LOOK IN MEMORY GET DATA FROM MEMORY GET DATA IN C REGISTER COMPLEMENT DATA A 1 IN THE ACC WILL PUT A 0 ON THE RS232 LINE STORE IN B REGISTER DUMMY INSTRUCTION FOR TIMING DELAY SET UP D REGISTER FOR TIME DELAY 2400 BAUD SET UP D REGISTER FOR TIME DELAY 2400 BAUD PUT LSB INTO BIT 7 FOR SIM INSTR STORE DATA IN REGISTER PUT A l IN BIT 6 FOR SIM INSTR MASK ANY OTHER BITS AFFECT RSTS DECREMENT COUNT REGISTER CONTINUE OUTPUT FOR 7 DATA BITS SET UP D REGISTER FOR DELAY 2400 BAUD SET UP A REGISTER FOR STOP BITS SET UP TWO STOP BIT DELAY 2400 BAUD DESCRIPTION ACCEPTS DATA IN THE D REGISTER WHICH DETERMINES THE NUMBER OF TIMES THE LOOP WILL BE EXECUTED THE LOOP INVOLVES TWO INSTRUCTIONS OR 14 CLOCK STATES WAIT DCR JNZ RET D WAIT 3 5 Programming Information SBC 80 05 Table 3 6 Serial Output Data Routine Non Interrupt Driven Continued FUNCTION MESOUT INPUTS CHARACTER STRING DATA IN MEMORY SPECIFIED BY amp REGISTERS OUTPUTS POINTER ADDRESS IS LOADED IN H amp L REGISTERS CALLS CO DESCRIPTION THE PLM PROGRAM CALLS MESOUT WITH AN ADDRESS PA
9. DRIVER RECEIVER 4 15 RAM ADDRESSES ARE 3F00 3FFF Figure 4 1 SBC 80 05 Block Diagram The Parallel I O Interface consists of three general pur pose ports provided by the Intel 8155 RAM IO Timer Each of the three ports can be programmed to be either an input port or an output port One of the three ports Port 03 can be programmed to be status pins thus allowing the other two ports Ports 01 and 02 to operate in a handshake mode The I O portion of the 8155 con tains four internal registers one register for command and status and one data register for each of the three ports Sockets are provided for the installation of input terminators or output drivers as required by the user s configuration The 8155 timer is a programmable 14 bit binary down counter that counts the input pulses and outputs either a square wave or a pulse when the terminal count is reached The count length and the timer output mode 4 2 are loaded under program control The four selectable timer modes are as follows a Timer Out goes low during the second half of count Therefore the count loaded in the Count Length Reg ister should be twice the timeout desired Timer Out remains high until the first half of the count has been completed and goes low for the sec ond half of the count The count length is automati cally reloaded when the terminal count is reached c A single low pulse is generated upon reaching the ter minal coun
10. and notice that each parallel input port re quires either two Intel SBC 901 Divider IC s or two SBC 902 Pull Up IC s Plug terminators into the appropriate IC sockets Ensure that each IC is installed so that pin 1 is oriented toward connector 11 on the upper edge of the board 2 15 OUTPUT PORT DRIVERS Table 2 1 item 9 lists four typical types of IC s which may be selected as line drivers depending on the user s application Two driver IC s are required for each dedicated output port Ensure that each IC is installed so that pin 1 is oriented toward connector J1 on the upper edge of the board 2 16 READ ONLY MEMORY Sockets are provided to accommodate either two EP ROM s or two ROM s as specified in table 2 1 item 7 Plug EPROM s or ROM s in IC locations A16 and 17 figure 5 1 grid coordinates C4 Ensure that each EPROM or ROM is installed so that pin 1 is oriented to ward connector J1 the upper edge of the board Refer to paragraph 2 17 for installation of filter capacitors NOTE If only one EPROM or ROM chip is being in stalled ie a or 2K configuration install the one chip in socket A17 Socket A17 accom modates the lower addresses 0000 03FF for 1K chips and 0000 07FF for 2K chips Preparation for Use 2 17 POWER SUPPLY FILTERS Filter capacitors must be installed if a power supply other than a 15 supply is required Capacitors that must be installed by the user are specified in table 2 3
11. sented in figure 3 2 SBC 80 05 AD ADg ADs AD4 AD gt AD xX TiMER INTE 02 INTRIINTE INTR 02 02 01 01 PORT 01 INTERRUPT REQUEST PORT 01 BUFFER FULL EMPTY INPUT OUTPUT PORT 01 INTERRUPT ENABLE PORT 02 INTERRUPT REQUEST PORT 02 BUFFER FULL EMPTY INPUT OUTPUT PORT 02 INTERRUPT ENABLED TIMER INTERRUPT THIS BIT IS LATCHED HIGH WHEN TERMINAL COUNT IS REACHED AND 1 RESET TO LOW UPON READING C S REGISTER OR STARTING NEW COUNT Figure 3 2 Status Register Format Port 00 3 7 PORT 01 REGISTER The Port 01 register can be programmed to be either an input port or an output port depending on Command register bit 0 See figure 3 1 Also depending on the Command this port can operate in either the basic in put output mode or strobed mode depending on the al ternative ALT mode programmed for Port 03 Refer to paragraph 3 9 3 8 PORT 02 REGISTER The Port 02 register can be programmed to be either an input port or an output port depending on Command register bit 1 See figure 3 1 Also depending on the Command this port can operate in either the basic in put output mode or strobed mode depending on the al ternative ALT mode programmed for Port 03 ae to paragraph 3 9 3 9 PORT 03 REGISTER The Port 03 register can be programmed as an input port output port as control signals for Port 01 and Port 02 depending on the hardware configuration and
12. stiie counta 151 lengths required for various baud rates are given in table bs highduringlarger Bai lot count 3 4 Timer interrupt routines are presented in paragraph 3 13 Figure 3 3 Timer Format 3 3 Table 3 4 Baud Rates Vs Count Lengths BAUD RATE Programming Information DECIMAL COUNT SBC 80 05 3 11 SERIAL 1 0 COMMUNICATION Tables 3 5 and 3 6 respectively provide examples of serial input and serial output routines using the SID and SOD instructions of the 8085A CPU Both routines which provide programmed timing loops at 2400 baud operate in the non interrupt driver mode The examples are included for illustration purposes only and are not intended to demonstrate the optimum way to program the serial I O port ERROR FRAME Table 3 5 Serial Input Data Routine Non Interrupt Driven FUNCTION CIWAIT INPUTS NONE OUTPUTS NONE CALLS WAIT DESCRIPTION THIS ROUTINE WAITS FOR AN INPUT FROM THE CONSOLE BY READING CIWAIT BEGIN NEXT CHKW FUNCTION MVI MVI RIM ANI JZ MVI CALL RIM ANI JZ DCR JZ MVI CALL RIM ANI ORA RRC MOV JMP MOV CPI JNZ RET WAIT THE SID INPUT LINE WHEN IT DETECTS A START BIT IT THEN READS THE INPUT CHARACTER AND RETURNS TO THE PLM CALLING PRO GRAM WHEN THE INPUT CHARACTER IS W B 00H CLEAR OUT CHARACTER STORAGE REGISTER C 08H SET COUNT REGISTER 80H CHECK FOR START BIT BEGIN CONTINUE LOOKING UNTI
13. 408 987 8080 From locations within California call toll free 800 672 3507 From all other U S locations call toll free 800 538 8014 TWX 910 338 0029 or 910 338 0255 TELEX 34 6372 Always contact the MCSD Technical Support Center before returning a product to Intel for service or repair You will be given a Repair Authorization Number shipping instructions and other important information which will help Intel provide you with fast efficient service If the product is being returned because of damage sustained during shipment from Intel or if the product is out of warranty a purchase order is necessary in order for the MCSD Technical Support Center to initiate the repair In preparing the product for shipment to the MCSD Technical Support Center use the original factory pe kaging material if available If the original packaging is not available wrap the product in a cushioning material such as Air Cap TH 240 or equivalent manufactured by the Sealed Air Corporation Hawthorne N J and enclose in a heavy duty corrugated shipping carton Seal the carton securely mark it FRAGILE to ensure careful handling and ship it to the address specified by MCSD Technical Support Center personnel NOTE Customers outside of the United States should contact their sales source Intel Sales Office or Authorized Intel Distributor for directions on obtaining service or repair assistance 5 1 5 2
14. O Write Machine Cycles SBC 80 05 Parts Location Diagram SBC 80 05 Schematic Diagram SBC 604 Schematic Diagram SBC 614 Schematic Diagram Page 3 3 4 2 4 4 4 4 4 5 4 6 4 7 5 3 5 5 5 11 5 13 v vi CHAPTER 1 GENERAL INFORMATION 1 1 INTRODUCTION The SBC 80 05 Single Board Computer which is a mem ber of Intel s complete line of SBC 80 computer pro ducts is a computer system on a single printed circuit assembly The SBC 80 05 includes a central processor unit CPU system clock random access memory RAM read only memory ROM one serial and three parallel I O ports a programmable timer priority interrupt and Multibus control logic and bus expansion buffers 1 2 DESCRIPTION The SBC 80 05 Single Board Computer figure 1 1 is controlled by an Intel 8085 CPU which includes six 8 bit general purpose registers and an accumulator The six general purpose registers may be addressed individ ually or in pairs which allows both single precision and double precision operations The minimum on board execution time is 2 03 microseconds The 8085A CPU has a 16 bit program counter which allows direct addressing of up to 65 536 bytes of mem ory An external stack located within any portion of read write memory may be used as a last in first out storage area for the contents of the program counter flags accumulator and all six general purpose registers A 16 bit stack pointer controls the addressing
15. Refer to figure 5 1 and install the capacitors as follows Figure 5 1 Component Supply Capacitors Grid Ref RS232 12V C26 ZB5 Drivers 12V C7 C24 ZD3 ZB8 Intel 8708 EPROM s C11 C24 ZC3 ZB8 C12 C23 ZD3 ZB8 Observe polarity as shown in figure 5 1 2 18 ALTERNATIVE 5V INPUT Connector J3 table 2 1 item 6 provides an alterna tive economical means of inputting 5V power to the SBC 80 05 Note that connector J3 is to be installed only if the SBC 80 05 is used in a single board confi guration i e the Multibus is not required and no power other than 5V power is required Install connector J3 as shown in figure 5 1 grid reference B8 Pin 2 adja cent to bus controller A19 is the 5V input pin is ground 2 19 JUMPER CONFIGURATION The SBC 80 05 jumper selectable options are listed and described in table 2 4 Grid references are provided to lo cate each jumper on the parts location diagram figure 5 1 and schematic diagram figure 5 2 Grid references to figure 5 2 are four alphanumeric characters for ex ample grid reference 3ZB3 signifies sheet 3 Zone B3 Carefully study table 2 4 while making reference to fig ure 5 2 and configure each jumper or jumper combi nation as required With the exception of jumper pad W5 CPU interrupts and jumper pad W9 Multibus in terrupts the information presented in table 2 4 is con sidered adequate to properly co
16. The TRAP interrupt which is not maskable is jumpered at the factory to GND ground to prevent the possibility of false interrupts from being generated by noise spikes Since this interrupt is Table 2 3 Power Requirements MAXIMUM SUPPLY CURRENT COMMENTS With no ROM EPROM or parallel I O ports With two Intel 2716 EPROM s or 8316E ROM s and six Intel SBC 901 or SBC 902 I O terminators in the low state See table 2 1 items 7 and 10 lec 1 8A 90 mA IDD 137 mA IAA 23 mA If power supply other than 5V supply is required the user must furnish and install the following capacitors refer to paragraph 2 17 for details 5V supply C12 C23 12V supply 7 11 C24 12V supply C26 5V 5 5N 15 Required only when Intel 8708 EPROM s or 8308 ROM s are used instead of 2716 s or 8316E s See table 2 1 items 7 and 11 and notes below 12V 15 Required for Intel 8708 EPROM s 8308 ROM s and RS232C line driver and receiver See table 2 1 items 7 8 and 11 and notes below 12V 15 Required only for RS232C line driver and receiver See table 2 1 items 8 and 1 1 and notes below Notes pA Capacitor specifications are C7 C11 C12 ceramic disc 0 01 uF 80 2046 25 Sprague C092B250C1037 or equivalent C23 C24 C26 tantalum 22 uF 20 15V Sprague 150D226X9015B2 or equivalent 3 Installation procedures are given
17. an I O read IO Mis driven high to identify that the current machine cycle is referencing an I O port One other minor ex ception is that the address used for an I O read cycle is derived from the second byte of an IN instruction this address is duplicated onto both the A8 A15 and ADO AD7 lines The data read from the I O port is always placed in the accumulator specified by the IN instruc tion Note that a may be imposed by slower I O devices as described for slower memory devices MR OR IOR o W M 0 MR OR 1 IOR 51 1 50 0 X Figure 4 5 Memory Read or I O Read Machine Cycles SBC 80 05 4 10 MEMORY WRITE TIMING Figure 4 6 shows the timing of two successive memory write machine cycles the first without a Tyg state Again disregarding the states of the SO and 1 lines the timing during is identical to the timing of an opcode fetch memory read and I O read cycles The difference occurs however at the end of For instance a memory read cycle the ADO AD7 lines are disabled high impedance at the beginning of T gt in anticipation of the returned data In a memory write cycle the ADO AD7 lines are not disabled and the data to be written into memory is placed on these lines at the beginning of T The Write WR line is driven low at this time to enable the addressed memory device During the READY input is checked to determine if a Tai stat
18. beyond that there are no specific rules For instance the IN input and OUT out put instructions each require three machine cycles fetch to obtain the instruction memory read to obtain the I O address of the peripheral and an input or output machine cycle to complete the transfer Each machine cycle consists of a minimum of three and a maximum of six states designated T through Tg A state is the smallest unit of processing activity and is de fined as the interval between two successive falling edges of the CPU clock Each state or CPU clock cycle has a duration of 508 nanoseconds derived by dividing the crystal frequency by 10 Every machine cycle normally consists of three T states with the exception of an opcode fetch which consists of either four or six T states The actual number of states required to execute any instruction depends on the in struction being executed the particular machine cycle within the instruction cycle and the number of wait states inserted into the machine cycle The wait state is initiated when the READY input to the CPU is pulsed low 4 3 Principles of Operation There is no wait state imposed when the CPU is ad dressing on board I O or memory As discussed later in this chapter the wait state occurs only while waiting for XACK to be pulled low in response to an off board I O or memory read or write operation Thus the wait state depends on how quickly the Multibus can be access
19. in subsequent paragraphs SBC 80 05 Preparation for Use Table 2 4 Jumper Selectable Options FIG 5 1 FIG 5 2 JUMPER GRID GRID DESCRIPTION W1 ZC6 3ZB3 W 1 is used in conjunction with W6 to define four modes of resolving bus W6 ZC7 2205 contention three of which are for use in multiple master systems According to the selected mode the SBC 80 05 can gain access to the Multibus as follows Mode 1 Can request Multibus as needed multiple master system Mode 2 Always requesting Multibus lowest priority in a multiple master sytem Mode 3 Programmable override of Multibus multiple master sys tem During an override condition the SBC 80 05 will not relinquish bus control until programmed to do so Mode 4 Always overriding Multibus single master system Jumper positions for configuring each of these four modes are as follows for example to configure W1 for Mode 3 remove jumpers from positions A D and B C and install jumper only in position A B A D and A B B C only only W6 1ZB7 B C is used as a Port 03 input output bit or as a Port 02 interrupt signal depending on how the 8155 is programmed If the Port 02 strobed input or output mode is used the INTR PORT 02 signal must be connected to the CPU interrupt input via jumper pad 5 Connects INTR PORT 02 to interrupt an alternative system master via jumper 9 W3 ZC
20. is given in 8080 8085 Assembly Lan guage Programming Manual part no 98 310 3 2 MEMORY ADDRESSING Addresses for on board read write memory RAM and read only memory ROM or EPROM are given in table 3 1 Note in table 3 1 that the address space listed for ROM EPROM depends on how the SBC 80 05 is confi gured by the user When on board memory is addressed a Memory Ad vanced Acknowledge MEM AACK signal is generated which allows the CPU to operate at maximum speed When system memory is addressed the CPU must first gain control of the Multibus and then wait for a Trans fer Acknowledge XACK to be received from the sys tem memory device if a non existent memory location is addressed the CPU will hang up in a wait state until reset It should be noted in table 3 1 that it is possible to configure ROM EPROM such as to create illegal addresses If an illegal address is used a MEM AACK signal is generated as described for a legal address and the CPU will continue executing If a Table 3 1 One 8308 8708 chip Two 8308 8716 chips One 2716 8316E chip Two 2716 8316E chips read is attempted from an illegal address erroneous data will be returned if a write is attempted to an illegal ad dress the data byte is lost When power is initially applied to the SBC 80 05 or when a reset is otherwise initiated the CPU program counter PC and instruction register are set to zero Thus the CPU initially fe
21. or combination boards Input output capacity may also be increased by adding SBC 80 Analog boards Mass storage may be added by selecting the appropriate single or double density diskette subsystem Modular expandable backplanes and cardcages are avail able to support multiboard systems 1 4 SYSTEM SOFTWARE DEVELOPMENT The development cycle of SBC 80 05 based products may be significantly reduced using the Intellec Micro computer Development System The resident macro assembler text editor and system monitor greatly simplify the design development and debug of SBC 80 05 system software An optional Diskette Operating System provides a relocating macroassembler relocating loader and linkage editor and a Library Manager A uni que In Circuit Emulator ICE 85 option provides the capability of developing and debugging software directly on the SBC 80 05 Table 1 1 WORD SIZE Instruction Data 8 bits CYCLE TIME General Information Intel s high level programming language PL M is also available as a resident Intel Microcomputer Develop ment System option PL M provides the capability to program in a natural algorithmic language and elimi nates the need to manage register usage or allocate mem ory PL M programs can be written in a much shorter time than assembly language programs for a given appli cation 1 5 EQUIPMENT SUPPLIED The following is supplied with the SBC 80 05 Single Board Computer a Sch
22. to observe this pre caution can result in damage to the board 2 26 SIGNAL CHARACTERISTICS As shown in figure 1 1 connector P1 provides the means of interfacing the SBC 80 05 to the Multibus Pin assignments for connector P1 are listed in table 2 5 the functions of the bus signals are described in table 2 6 AC characteristics of the SBC 80 05 bus interface are presented in table 2 7 and figures 2 3 and 2 4 DC characteristics are specified in table 2 8 2 27 SERIAL PRIORITY RESOLUTION In a multiple master system bus contention can be re solved in an SBC 604 Modular Backplane and Cardcage by implementing a serial priority resolution scheme as shown in figure 2 5 Due to the propagation delay of the signal path this scheme is limited to a maximum of three devices masters capable of acquiring and con W2 REFER TO TABLE 2 4 a C B INTR PORT 02 LN a r D L M Nw lt LO N P Z Z Z Z Z 2 gt 2 MULTIBUS Figure 2 2 Multibus Interrupt Jumpers Preparation for Use trolling the Multibus In the configuration shown in fig ure 2 5 the SBC 80 05 installed in slot J2 has the highest priority and is able to acquire the Multibus at any time because its BPRN input is enabled tied to ground through jumpers B and N on the SBC 604 back plane See figure 5 3 If the master in slot J2 desires control of the Multibus it drives its BPRO outp
23. vary the address data type and sequence of operations it is capable of per forming only a basic read or write operation With the exception of a few control lines such as Address Latch Enable ALE these read and write operations are the only communication necessary between the processor and the other components to execute any instruction An instruction cycle is the time required to fetch and ex ecute an instruction During the fetch phase the selected instruction consisting of up to three bytes is read from memory and stored in the operating registers of the CPU During the execution phase the instruction is decoded by the CPU and translated into specific processing activi ties Each instruction cycle consists of up to five machine cycles A machine cycle is required each time the CPU accesses memory or an I O port The fetch phase re quires one machine cycle for each byte to be fetched Some instructions do not require any machine cycles other than those necessary tofetch the instructions from memory other instructions however require an addi tional machine cycle s to write or read data to or from memory or O devices Every instruction cycle has at least one reference to memory during which time the instruction is fetched An instruction cycle must always have a fetch even if the execution of that instruction requires no reference to memory The first machine cycle in every instruction cycle is therefore a fetch and
24. 1 grid refer ence ZD3 2 12 TTL LEVEL SERIAL INPUT OUTPUT The SBC 80 05 can employ RS232C or TTL level serial I O operation but not both simultaneously Provision is made on connector Jl for intetfacing the parallel I O ports and the TTL level serial I O device If using con nector J1 for both functions is impractical connector J2 must be installed Refer to table 2 1 item 5 Solder this 7 pin male connector in position as shown in figure 5 1 grid reference 703 2 3 for Use 2 13 PARALLEL INPUT OUTPUT PORTS Parallel I O Ports 01 and 02 must be individually con figured as either a dedicated input port or a dedicated output port Port 03 may also be configured as either a dedicated input port or a dedicated output port or used SBC 80 05 as control signals for Ports 01 and 02 when these ports are to be used in the strobed input or strobed output mode For use as a dedicated output port line drivers table 2 1 item 9 must be installed for use as a dedi cated input port I O terminators table 2 1 item 10 must be installed The following six IC sockets two for Table 2 2 User Furnished Connector Details Function No of Centers Connector Vendor Vendor Intel Pairs Inches Type Part No Part No Parallel 3415 0001 102211 003 I O 25 50 0 1 Flat Crimp 88083 1 Connector 609 5015 J 1 S06750 Series Parallel GTE Sylvania 6AD01 25 1A1 DD 102237 001 I O 25 50 0 1 So
25. 3 3ZA7 W4 ZC3 3ZA7 W3 loaded with jumper block accommodates Intel 2716 EPROM s or 8316E ROM s W4 loaded with jumper block accommodates Intel 8708 EPROM s or 8308 ROM s If 2716 s or 8316E s are used leave jumper block installed in W3 if 8708 s or 8308 s are used remove jumper block from W3 and reinstall in W4 refer to paragraphs 2 16 and 2 17 Priority jumper pad for connecting selected interrupts to CPU The CPU has three maskable interrupts RST 5 5 RST 6 5 and RST 7 5 and one nonmaskable interrupt TRAP These four interrupts are characterized as follows refer to paragraphs 2 20 through 2 24 for jumper selectable inputs W5 ZC8 1ZB6 Edge and level sensitive Rising edge sensitive High level sensitive High level sensitive Highest Priority 2nd 3rd Lowest Priority A B Routes Bus Clock signal BCLK to the Multibus Remove this jumper only if some other module is used to generate BCLK A B Routes Constant Clock signal CCLK to the Multibus Remove this jumper only if some other module is used to generate CCLK Preparation Use SBC 80 05 Table 2 4 Jumper Selectable Options Continued FIG 5 1 FIG 5 2 JUMPER GRID DESCRIPTION REF 1ZC7 Interfaces 80 05 with the eight interrupt request lines INT0 through INT7 on the Multibus Refer to paragraph 2 24 for details W10 2ZD3 A B Routes Bus Priority Out signal BPRO to the Multibus
26. 5 22 yd s A S sut Z Lisy I T 55 BC SINGLE BOARD COMPUTER 2001600 gt dc R gt s ne ss i m Des Fie ere a SSO i ase as 2 EC le L C LIS SCHEMATIC umi h l s pues I m 4 2 Figure 5 2 SBC 80 05 Schematic Diagram Sheet 1 of 3 5 5 5 6 mantaua eram na 1 bci cil acd iau RE manere genna m 1 L t m maneta TT ee BPRNY 5 z 2 RDS iZB2 2652 WRT CT RESET 1752 OFF BD ROT 1282 CMD IZA2 OFF BD ZA OVERRIDE ZD2 BUS coca ee 0BMHI 1202 Pu 4722 TIMER Cix 1252 DBE LD zc ABG seno NE N NE ENE SN AA CINA fit Bow a cf i saca 3 2 21 20 wwTc NONE mal 205 D haf ezocieoc c 1 LE Figure 5 2 SBC 80 05 Schematic Diagram Sheet 2 of 3 5 7 5 8 Timin 22 88 m I AM WAR _a m d 1252 Tow 1262 WRT 1752 mD Di 1282 ALE PORT 21 tn 5 1 1782 052 07 _ C EN MEE E NICI IRI ee E OT IZC2 ABB ABF LLLA PORT 22 I BIB jap L iZB2 MEM PORT IB amp j A15 b ui hj V 1252 INTR PORT gi 12 INTR PO
27. A current loop interface provides signal translation for transmitted data received data and a paper tape reader relay The iSBC 530 TTY adapter interfaces an Intel iSBC 80 computer system to a teletypewriter as shown in figure 8 The iSBC 530 TTY adapter requires 12V at 98 mA and 12V at 98 mA An auxiliary supply must be used if the iSBC 80 system does not supply this power A schematic diagram of the iSBC 530 TTY adapter is supplied with the unit The following auxiliary power connector or equivalent must be procured by the user Connector Molex 09 50 7071 Pins Molex 08 50 0106 Polarizing Key Molex 15 04 0219 1 Teletypewriter Modifications ISBC 80 05 MERE e TOP VIEW MOUNT CIRCUIT CARD D KEYBOARD TAPE READER CAPACITOR PRINTER UNIT PUNCH DISTRIBUTOR RESISTOR TRIP 2 ASSEMBLY POWER JUUU carp SUPP LY jo TERMINAL BLOCK i N TELETYPE MODEL 33TC Figure A 1 Teletype Component Layout Figure A 2 Current Source Resistor Figure A 3 Terminal Block A 2 isBC 80 05 Teletypewriter Modifications TERMINAL BLOCK 151411 e 25 PIN EXTERNAL 2 CONNECTOR RECEIVE 1 1 S y TAPE READER CONTROL ALTERNATE CONTACT PROTECTION CIRCUIT 4709 Y 0 1 200V i POTTER amp BRUMFIELD lnevay ci CUIT CAR m i m w e aan s
28. Command register bits 2 and 3 Figure 3 1 shows that bits 2 and 3 specify four alternative modes for Port 03 ALT 1 ALT 2 ALT 3 and ALT 4 As noted in table 3 3 for ALT 3 mode bits 0 2 are control bits for Port 01 and bits 3 5 depend on the user s jumper selected op tions SBC 80 05 Programming Information Table 3 3 Port 03 Programmable Modes PORT 03 BIT ALT 1 ALT 2 ALT 3 ALT 4 Input Port Output Port Port 01 Interrupt Port 01 Interrupt Input Port Output Port Port 01 Buffer Full Port 01 Buffer Full Input Port Output Port Port 01 Strobe Port 01 Strobe Input Port Output Port Note 1 Port 02 Interrupt Input Port Output Port Note 2 Port 02 Buffer Full Input Port Output Port Note 3 Port 02 Strobe Notes If W2 is in position B C bit 3 is output bit If W12 is in position bit 4 is output bit if W12 is in position A C bit 4 is RS232C Reader Control CTL signal 3 If W1 is in position only and W6 is in position bit 5 is used to provide the program mable bus override mode i e the SBC 80 05 will not relinquish the Multibus until Port 03 bit 5 is cleared If the override function is not Jumpered bit 5 is not functional 3 10 TIMER SECTION I O ADDRESS 04 The timer is a 14 bit down counter that counts the 122 88 kHz timer clock input and outputs either a square wave or a pulse when the terminal count TC is reached The timer outp
29. FIGURE 2 2 Figure 2 1 CPU Interrupt Input Jumpers 2 8 SBC 80 05 2 24 MULTIBUS INTERRUPTS The eight Multibus interrupt lines INT0 through INT7 are applied to one side of jumper block W9 See fig ure 2 2 Four of these interrupts may jumpered and applied via the inverters to jumper pad 5 for distri bution to the selected CPU interrupts Refer to table 2 4 and figure 2 2 and note that W2 may be jumpered and applied to W9 through the inverter This allows the INTR PORT 02 to be connected to an alternative sys tem master by the selected Multibus interrupt line 2 25 MULTIBUS CONFIGURATION For system applications the SBC 80 05 is designed for installation in a standard Intel SBC 604 614 Modular Backplane and Cardcage Refer to table 2 1 items 1 and 2 Alternatively the SBC 80 05 may be interfaced toa user designed system backplane by means of an 86 pin connector Refer to table 2 1 item 3 Bus signal characteristics and methods of implementing a serial or parallel priority resolution scheme for resolving bus con tention in a multiple master system are described in fol lowing paragraphs t BUS RO x INTRS po xc N O Lu PART OF W5 SEE FIGURE 2 1 J K BUS INTERRUPTS H Preparation for Use A A A A a 4 CAUTION gt wwwww Always turn off the power supply before in stalling the board in or removing the board from the backplane Failure
30. HER ROUTINES THIS PROGRAM SETS THE TIME TO COUNT 122 TIMER IN PULSES BEFORE OUT PUTTING A TIMER PULSE THAT WILL GENERATE AN INTERRUPT USING MODE 3 THE TIMER WILL AUTOMATICALLY RELOAD AND BEGIN ANOTHER COUNTDOWN MVI A 7CH OUT 4 OUTPUT LSB OF COUNT LENGTH MVI A 0COH OUT 5 OUTPUT MSB AND TIMER MODE MVI A 18H SIM UNMASK RESTART INTERRUPTS EI ENABLE PROCESSOR INTERRUPTS MVI A 0COH OUT 0 START TIMER COUNTDOWN MAIN PROGRAM CONTINUES END MAIN PROGRAM FUNCTION INTR75 DESCRIPTION WHEN A RST 7 5 IS GENERATED BY THE 8155 DETERMINED BY THE MAIN PROGRAM THIS ROUTINE STORES THE STATUS WORD AND THEN INCREMENTS A COUNT VARIABLE IT MAY THEN CALL A REAL TIME COUNT AND DISPLAY ROUTINE WHICH INCREMENTS VARIABLES FOR MILLISECONDS SECONDS ETC AT THE PROPER TIME FINALLY THE INTERRUPT ROUTINE WILL RESET RST 7 5 RESTORE PROCESSOR STATUS WORD AND ENABLE INTERRUPTS BEFORE RE TURNING TO THE MAIN PROGRAM ORG 003CH COUNT EQU 00 SET TIMER DELAY SAVE PUSH PSW SAVE STATE OF MACHINE PUSH B PUSH D PUSH H INTR75 LXI H COUNT LOAD H amp L WITH LOCATION OF COUNT INR M INCREMENT THE COUNT CALL RTC CALL REAL TIME COUNT AND DISPLAY ROUTINE MVI A 10H NOT SHOWN SIM RESET RST 7 5 RSTORE POP H RESTORE STATE OF MACHINE POP D POP B POP PSW EI RET 3 7 4 PRINCIPLES OF OPERATION 4 1 INTRODUCTION This chapter provides a functional description and a cir cuit analysis of the SBC 80 05
31. Ih BLK GRN WHT BRN RED GRN WHT YEL WHT BLK WHT BLU BRN YEL FULL DUPLEX gt ap GRY WHT RED BLK BLK WHT DISTRIBUTOR TRIP CONNECTOR Wer MAGNET WIRE A YEL J 1 GE BRN 117 VAC DS 6RS20 COMMON SP4B4 0 114 4709 RELAY 12 0 60052 COIL 1A NORMAL CONTACTS OPEN MODE SWITCH FRONT VIEW WIRE B Figure A 4 Teletypewriter Modifications MOUNT IN FOR CIR G POSITION CUIT CARD A oA URS Figure A 5 Relay Circuit UU Teletypewriter Modifications iSBC 80 05 Figure A 7 Distributor Trip Magnet J1 FROM K SERIAL IN OUT P3 p i TO TERMINAL BLOC PORT SEE FIGURES A 3 AND A 4 CINCH DB 25S CINCH DB 25P Figure A 8 TTY Adapter Cabling A 4
32. L FOUND D 1BH SET UP DELAY WAIT 80H CHECK FOR VALIDITY OF START BIT BEGIN C DECREMENT COUNT REGISTER CHKW CHECK TO SEE IF INPUT CHARACTER IS A W D 38H SET UP DELAY WAIT 80H CHECK REGISTER A BIT 7 B LOAD PREVIOUS BITS INPUT INTO B A STORE DATA IN REGISTER NEXT A B 28H COMPARE CI TO COMPLEMENT OF W CIWAIT DESCRIPTION ACCEPTS DATA IN THE D REGISTER WHICH DETERMINES THE NUMBER WAIT DCR JNZ RET OF TIMES THE LOOP WILL BE EXECUTED THE LOOP INVOLVES TWO INSTRUCTIONS OR 14 CLOCK STATES WAIT SBC 80 05 FUNCTION CO INPUTS OUTPUTS CALLS Programming Information Table 3 6 Serial Output Data Routine Non Interrupt Driven ACCEPTS A BYTE OF DATA IN THE C REGISTER OR FROM MEMORY LOCATION SPECIFIED BY H amp L REGISTERS OUTPUTS SERIAL DATA VIA THE SOD LINE TO CONSOLE WAIT DESCRIPTION CO ACCEPTS AN ASCII BYTE FROM THE PLM SYS4 PROGRAM DIRECTLY OR FROM THE MESOUT ROUTINE WHICH IS INVOKED BY THE PLM SYS4 PROGRAM IT FIRST OUTPUTS THE START BIT THEN SEVEN DATA BITS FOLLOWED BY TWO STOP BITS THE PROPER DURATION BETWEEN SOD OUTPUTS IS DETERMINED BY THE VALUE PASSED TO THE WAIT ROUTINE VIA THE D REGISTER CO 11 L2 DELAY L3 FUNCTION WAIT MVI MVI SIM MVI CMP JNZ MOV CMA MOV JMP MOV CMA MOV ANI MVI CALL JMP MVI CALL MOV RRC MOV ORI ANI SIM DCR JNZ MVI CALL MVI SIM MVI CALL RET A 0COH E 07H A 00H C L1 A M
33. LK and has a period of 101 72 nanoseconds with a 35 65 percent duty cycle Data These eight bidirectional data lines transmit and receive information to and from the addressed memory location or I O port DAT7 is the most significant bit Initialization Resets the entire system to a known internal state Interrupt These eight lines are used for system interrupt requests I O Read Command Indicates that the address of an I O port is on the system address lines and that the output of that port is to be read placed onto the system data lines I O Write Command Indicates that the address of an I O port is on the system address lines and that the contents on the system data lines are to be accepted by the addressed port Memory Read Command Indicates that the address of a memory location is on the system address lines and that the contents of that location are to be read placed onto the system data lines Memory Write Command Indicates that the address of a memory location is on the system address lines and that the contents on the system data lines are to be written onto that location Transfer Acknowledge Indicates that the addressed memory location or I O port has completed the specified read or write operation That is data has been placed onto or accepted from the system data lines 2 11 Tr Preparation for Use SBC 80 05 F tew we F lt tew BCLK SUUUUUU UU Ud UU UU uu BREQ e BP
34. MENTAL REQUIREMENTS Operating Temperature 0 to 550C 320 to 1319F Relative Humidity To 90 without condensation PHYSICAL CHARACTERISTICS Width 30 48 cm 12 00 inches Height 17 15 cm 6 75 inches Thickness 1 27 cm 0 50 inch Weight 340 gm 12 ounces 2 PREPARATION USE 2 1 INTRODUCTION The chapter provides instructions for preparing the SBC 80 05 Single Board Computer for use in a multiple mas ter bus system and use in single board environment It is advisable that the contents of Chapters 1 and 3 be fully understood before beginning the configuration and installation procedures contained in this chapter 2 2 UNPACKING AND INSPECTION Inspect the shipping carton immediately upon receipt for evidence of mishandling during transit If the shipping carton 1 severely damaged or waterstained request that the carrier s agent be present when the carton is opened If the carrier s agent is not present when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s in spection For repairs to a product damaged in shipment contact the Intel Technical Support Center see paragraph 5 3 to obtain a Return Authorization Number and further instructions A purchase order will be required to com plete the repair copy of the purchase order should be submitted to the carrier with your claim It is suggested that salvageable shipp
35. NSTRUCTION OPCODE STA DIRECT ADDRESS Figure 4 2 Typical CPU SIGNAL for inus E 0 1 1 0 Y MEMORY READ 4 T3 T T2 T3 Ti T2 T3 MEMORY READ MEMOR Y WRITE THE ADDRESS PC 1 POINTS THE ADDRESS 2 POINTS THE ADDRESS IS THE DIRECT PROGRAM COUNTER POINTS TO THE TO THE SECOND BYTE OF TO THE THIRD BYTE OF THE INSTRUCTION ADDRESS ACCESSED IN 2 AND M3 OF THE HIGH ORDER BYTE OF THE DIRECT ADDRESS CONTENTS OF THE ACCUMULATOR Instruction Cycle ERG Ha Figure 4 3 Opcode Fetch Machine Cycle SBC 80 05 Places low order bits PCL of program counter onto address data lines ADO AD7 These address bits will remain true for only one clock cycle after which ADO AD7 go to their high impedance state as indi cated by the dashed line in figure 4 3 d Activates the Address Latch Enable ALE signal At the beginning of the CPU pulls the RD line low to enable the addressed memory device The device will then drive the ADO AD7 lines After a period of time as determined by the access time of the addressed memory device valid data the DCX instruction in this example will be present on the ADO AD7 lines During the CPU loads the data on DCO DC7 into its instruction register and drives RD high disabling the addressed memory device During T4 the CPU decodes the opcode and decides whether or not to enter Ts on the next
36. Port 03 can be used to invoke the override function to prevent losing control of the Multibus at a critical time Refer to para graph 4 13 The override function is invoked by first de fining Port 03 as an output port and then performing a write operation to Port 03 with data bit 5 set The over ride function will remain in effect PCS set until cleared by the program This function is also useful where the SBC 80 05 is the only master module in the system In this application the SBC 80 05 can save the time it would otherwise take to gain control of the bus It should be noted that W6 2705 must be installed in position B C along with W1 in position when it is desired to have the SBC 80 05 always requesting the bus 4 23 TIMER ADDRESSING The timer section requires two address bytes address 04 for the low order byte and address 05 for the high order byte During a write operation the Count Length Register bits 13 0 and the timer mode bits 15 14 are loaded During a read opera tion the contents of the counter the present count and the mode bits are read There are four modes selectable by bits 15 14 SBC 80 05 Timer Out goes low during the second half of count Therefore the count loaded in the Count Length Re rister should be twice the timeout desired b Timer Out remains high until the first half of the count has been completed and goes low for the sec half of the count The count length is automa
37. RAMETER PLACED IN THE B AND C REGISTERS MESOUT LOADS THIS ADDRESS INTO THE H AND L REGISTERS AND THEN CALLS THE CO ROUTINE WHICH WILL OUTPUT THE ASCII DATA LOCATED IN MEMORY SPECIFIED BY THESE REGISTERS MESOUT WILL THEN i INCREMENT H amp L AND CONTINUE TO CALL CO UNTIL A ZERO IS FOUND IN MEMORY MESOUT MOV H B MOV D C LOOP MVI C 00H INDICATE TO CO THAT DATA IS IN MEMORY CALL INX H GET ADDRESS OF NEXT CHARACTER IN STRING MOV A M CHECK FOR END OF STRING ORI 00H oa LOOF CONTINUE UNTIL ZERO FOUND IN MEMORY 3 12 INTERRUPTS The SBC 80 05 CPU includes four vectored interrupts TRAP RST 7 5 RST 6 5 and RST 5 5 Jumpers may be installed to allow interrupts from parallel I O Ports 01 and 02 the programmable timer one or more devices via the Multibus or an external source Each of the three RST inputs 7 5 6 5 and 5 5 has a programmable mask TRAP is not maskable The priority and vector location for each of these restart interrupts are given in table 3 7 3 13 TIMER INTERRUPTS Timer interrupt routine examples are presented in table 3 8 These examples include a timer initialization which is performed as part of the main program a routine to service an RST 7 5 interrupt and a subroutine to save the state of the machine upon being interrupted and to restore the state of the machine after servicing the in terrupt These examples are included for illustration pur poses only and are not intended to demonstrate t
38. RIORITY RESOLUTION A paralle priority resolution scheme allows up to 16 masters to acquire and control the Multibus Figure 2 6 illustrates one method of implementing such a scheme for resolving bus contention in a system containing eight master modules installed in an SBC 604 614 In this example the priority encoder is a Texas Instru ments 74148 and the priority decoder is an Intel 8205 Input connections to the priority encoder determine the bus priority with input 7 having the highest priority and input O having the lowest priority Here the J3 master has the highest priority and the J4 master has the lowest priority IMPORTANT In a parallel priority resolution scheme the output signal must be disabled all master modules On the SBC 80 05 disable the BPRO output signal by removing jumper W 10 If a similarjumper is not provided on the other master modules to disable the BPRO output signal either clip the IC pin that supplies the BPRO output signal to the Multibus or cut the trace 2 29 SINGLE BOARD CONFIGURATION A A A A 4 CAUTION www ww Always turn off the power supply before connecting or disconnecting power leads Fail ure to observe this precaution can result in damage to the board If the SBC 80 05 is used in a single board configuration and power other than 5V is specified in table 2 2 an 86 pin connector must be provided to input power to the board A description of the connector is give
39. RN BUSY a anus DBY ADRO ADRF STABLE ADDRESS 7 tas WRITE DATA STABLE DATA 7 tps tAH DH WRITE COMMAND tcp READ COMMAND c zm ERR ET READ DATA READ XACK Figure 2 3 SBC 80 05 Bus Exchange Timing OnE STABLE ADDRESS WRITE DATA STABLE DATA tas 05 be tAH tpH WRITE COMMAND M x READ COMMAND ON Ne ee a CEAR ORA LL XSTABLE DATA READ XACK NR ANNIE r aa Figure 2 4 SBC 80 05 Bus Control Timing 2 12 SBC 80 05 HIGHEST PRIORITY MASTER J2 15 BPRN BPRO b SBC 80 05 16 SBC 501 DIRECT MEMORY ACCESS CONTROLLER LOWEST PRIORITY MASTER J4 15 4 BPRN Table 2 7 SBC 80 05 Bus Interface AC Characteristics OVERALL PARAMETER MIN MAX MIN MAX ns ns ns ns See figures 2 3 and 2 4 for timing diagrams WRITE MIN MAX ns ns Address Setup T ime to Command Address Hold Time from Command Data Setup Time to Command Data Hold Time from Command CPU Cycle Time Command Width Command Separation Command Separation Command Separation Parallel Priority Resolution Delay XACK Turn Off Delay Bus Clock Low or High Intervals BPRN to BCLK Setup Time BCLK to Busy Delay BPRN to BPRO Delay Bus Clock Period BCLK Bus Clock Low or High Intervals Initialization Width BPRO D SBC 201 DISKETTE CONTROLLER Preparat
40. RT 22 17585 OVER RIDE 2708 TMR INTR iZBB A MEM AACK 1288 I O 12353 32 1 5 65232 CTL 3 Tu 1 325 D led Pzoo eoo je f _ g 7 6 5 4 3 2 Figure 5 2 SBC 80 05 Schematic Diagram Sheet 3 of 3 5 9 5 10 x APPENDIX TELETYPEWRITER MODIFICATIONS 1 INTRODUCTION This appendix provides information required to modify a Model ASR 33 Teletypewriter for use with certain Intel iSBC 80 computer systems A 2 INTERNAL MODIFICATIONS Hazardous voltages are exposed when the top cover of the teletypewriterisremoved To prevent accidental shock disconnect the teleprinter power cord before proceeding beyond this point Remove the top cover and modify the teletypewriter as follows a Remove blue lead from 750 ohm tap on current source reslstor reconnect this lead to 1450 ohm tap Refer to figures A 1 and A 2 b On terminal block change two wires as follows to create an internal full duplex loop refer to figures A 1 and 3 1 Remove brown yellow lead from terminal 3 this lead to termina 5 2 Remove white blue lead from terminal 4 re connect this lead to termina 5 c On termina block remove violet lead from terminal 8 reconnect this lead to terminal 9 This changes the receiver current level from 60 mA to 20 mA A relay circuit card must be fabricated and connected to the paper tape reader drive circuit The relay circuit card t
41. Remove this jumper only in a multiple master device system employing a parallel priority bus resolution scheme Refer to paragraph 2 28 3ZD5 Routes ground true Chip Enable signal to Intel 8155 chip Do not remove jumper from this position W12 ZC4 3ZB3 is used as a Port 03 input output bit or as a Port 02 Buffer Full status bit depending on how the 8155 is programmed PC4 used as an RS232C Reader Control output signal W13 1ZC5 Jumper installed in this position at the factory 2 23 RST 6 5 AND 5 5 INTERRUPTS The RST 6 5 c Multibus interrupt lines refer to paragraph 2 24 and RST 5 5 interrupts are level sensitive and may be driven from the following interrupt sources As shown in figure 2 1 two of these interrupt sources may be jumpered to the J 2nd K inputs of an OR gate a PORT 1 and PORT 2 from the on board 8155 which in turn may be Jump gt red to either the RST 6 5 or RST 5 5 interrupt When this feature is used the inter rupting source must be identified by executing a polling b EXT 1 from an external source via connector J1 subroutine A B Routes output of 5 counter to X1 clock input of CPU Do not remove jumper from this position D LO PU INTERRUPTS O BIS INS GND F O P M O 39 EXT1 GO TRAP AND RST 7 5 INTERRUPTS ARE FACTORY JUMPERED TO GND GROUND AND TMR TIMER RESPECTIVELY PORT1 O N P CC E L FOR BUS INTRS INTERFACE WITH W9 SEE
42. Single Board Computer The circuit analysis is presented with the assumption that the reader has access to the Intel MCS 85 User s Manual part 98 366 which describes in detail the Intel 8085A Microprocessor CPU and the 8155 RAM IO Timer 4 2 FUNCTIONAL DESCRIPTION As shown in figure 4 1 the SBC 80 05 is composed of the following functional blocks a Clock Generator including power up reset b CPU including interrupt control c Bus Interface address bus drivers data bus drivers and bus controller Random Access Memory RAM Read Only Memory ROM EPROM Serial I O Interface Parallel I O Interface including programmable timer Crystal controlled Clock Generator provides stable time base for the SBC 80 05 as well as for the Multibus The Clock Generator also generates a power up reset signal to initialize the entire system to a known internal state The 8 bit parallel CPU which is the heart of the system performs all the system processing functions and gene rates the address and control signals required to access memory and I O ports The CPU multiplexes the 8 bit data bus and the lower eight bits of the address bus During the first part of the machine cycle the lower eight address bits on the address data bus are latched into Demultiplexer A18 and RAM IO Timer A15 During the remainder of the machine cycle the bus is used for memory and I O data transfers The CPU resp
43. Vo 0 4V Capacitive Load Output Low Voltage Out High Voltage Input Low Voltage Input High Voltage 59 5 mA loH 3mA Input Curremt at Low V Input Current at High V Capacitive Load VIN 0 45 V VIN 5 25V BCLK OPEN COLLECTOR DATO DAT7 INIT SYSTEM RESET Output Low Voltage Output High Voltage V Capacitive Load 10 pF Output Low Voltage 0 45 V Output High Voltage V Capacitive Load Output Low Voltage Capacitive Load Output Low Voltage Output High Voltage Capacitive Load 3 mA Output Low Voltage Output High Voltage Input Low Voltage Input High Voltage loH _10 mA Input Current at Low V VIN 0 45V Output Leakage High Ve 5 25V Output Leakage Low Vo 0 45 V Capacitive Load Output Low Voltage Output High Voltage Input Low Voltage Input High Voltage Input Current at Low V Input Current at High V Capacitive Load lor 44 mA Open Collector VIN 0 4V VIN 2 4 2 15 Preparation for Use SBC 80 05 Table 2 8 SBC 80 05 Bus Interface DC Characteristics Continued PARAMETER DESCRIPTION SIGNALS SYMBOL INTO INT7 XACK Input Low Voltage Input High Voltage TEST CONDITIONS Input Current at Low V Input Current at High V Capacitive Load MRDC MWTC IORC IOWC Capacitive load values are approximations 2 28 PARALLEL P
44. able 2 1 item 8 a line driver and a line receiver must be in stalled to accommodate RS232C serial I O operation Refer to figure 5 1 and install a type 1488 line driver in IC socket All Orient pin 1 of 1488 adjacent to capa citor C6 Install a type 1489 line receiver in IC socket A10 Orient pin 1 of 1489 adjacent to capacitor CS 2 11 CONNECTOR As specified in table 2 1 item 5 connector J2 must be installed to interface the RS232C serial I O device to the SBC 80 05 Solder this 7 pin male Type National DS1488 or TI SN75188 serial I O data to and from RS232C line re Type National DS1489 or RS232C device ceiver TI SN75189 Line Driver Requires two line driver IC s for each parallel out SN7403 LOC put port Requires only SN7400 I one line driver IC for Port SN7408 NI 03 if Port 03 is to be used SN7409 NI OC Types selected as ty pical I inverting NI non inverting and OC open Intel SBC 901 Divider or SBC 902 Pull Up 5 V SBC 901 220 330 5 V SBC 902 IK See table 2 3 DESCRIPTION USE Transmitting and receiving as control signals for Ports 01 and 02 Requires two 901 s or two 902 s for each parallel in put port Requires only one 901 or 902 for Port 03 if Port 03 is to be used as control signals for Ports 01 and 02 Required only if power supply other than 5 supply is needed connector in position as shown in figure 5
45. al SBC 80 I O boards SERIAL I O PORT SID and SOD functions of the 8085A CPU are used for serial I O communication controlled by software through RIM and SIM instructions Baud rate is determined by system time available for serial I O handling On board timer may be used to greatly ease serial I O timing re quirements INTERRUPTS Four level interrupt routed to 8085A CPU interrupt inputs Each interrupt automatically vectors the processor to a unique memory location Interrupt Memory Priority Type Input Address Highest Non Maskable 2nd Maskable 3rd Maskable Lowest Maskable NOTE Caution must be exercised in the use of the TRAP interrupt when utilized concurrently with maskable interrupts i e RST 7 5 RST 6 5 and RST 5 5 For further details refer to Chapter 3 TIMER Input Freq Reference 122 88 kHz 20 1 8 14 usec period nominal Outputs Operating modes vs output frequencies and timing intervals Programmable Pulse 8 14 usec 66 67 msec Square Wave Rate Generator 7 50 Hz 61 44 kHz Rate Generator 7 50 Hz 61 44 kHz Programmable Strobe Indication 8 14 usec 133 33 msec INTERFACE COMPATIBILITY All TTL compatible sockets provided for RS232C line drivers and receivers MULTIBUS CLOCK 9 8 MHz 0 1 derived from on board crystal clock may be generated externally POWER REQUIREMENTS DC power requirements depend on user installed options Refer to table 2 2 ENVIRON
46. an be pro grammed to be an input port an output port or as con trol signals for Ports 01 and 02 Refer to Chapter 3 When used as a control port three bits PCO PC2 are assigned for Port O1 and three bits PC3 PC5 are as signed for Port 02 PCO and are interrupts PC1 and 4 are buffer status buffer full and PC2 and PC5 are port strobe inputs When it is desired to use Port 01 in the strobed input mode Port 03 is programmed as control signals in the ALT 3 or ALT 4 mode Refer to Chapter 3 Thus the device inputs data to the PAO through PA7 inputs and then drives the Strobe STB signal low at PC2 Port 01 then drives the Buffer Full BF signal high at PCI to acknowledge receipt of the data Next Port 01 drives PCO high to generate an interrupt request INTR PORT 01 After the CPU services the interrupt Port 01 pulls the BF signal low at PCI to signify that it is ready to ac cept data When it is desired to use Port 02 in the strobed output mode Port 03 is programmed as control signals in the ALT 4 mode Refer to Chapter 3 Thus the CPU first performs an I O write to Port 02 and when data is ac cepted by Port 02 it drives the BF signal high at PC4 The output device then drives the STB input low to PCS and accepts the data After accepting the data the out put device drives STB high and then Port 02 drives PC3 to generate an interrupt request INTR PORT 02 If jumper W1 is installed in position
47. ch Machine Cycle With Wait 4 5 Principles of Operation 4 8 MEMORY READ TIMING Figure 4 5 shows the timing of two successive memory read machine cycles the first without a state and the second with one Twait State Disregarding the states of the SO and 1 lines the timing during T through T3 is identical with the opcode fetch machine cycle shown in figure 4 3 The major difference between the opcode fetch and memory read cycles is that an opcode fetch machine cycle requires four or six T states whereas the memory read machine cycle requires only three T states One minor difference between the two cycles is that the memory address used for the opcode fetch cycle is al ways the contents of the program counter PC which points to the current instruction the address used for a memory read cycle can be one of several origins Also the data read from memoryis placed into the appropriate register instead of the instruction register Note that a MR OR IOR SIGNAL 0 MR OR 1 1 1 0 0 acus C p D DE qu a pops AA SBC 80 05 Tyait can be imposed by slower memory devices as pre viously described 4 9 READ TIMING Figure 4 5 also illustrates the timing of two successive I O read machine cycles the first without a T4 state and the second with one Tya t state With the exception of the IO M status signal the timing of a memory read cycle and an I O read cycle is identical For
48. clock cycle or start a new machine cycle and enter T In the case of the DCX instruction the CPU will enter Ts and then Tg before beginning a new machine cycle SIGNAL IO M 0 1 1 0 1 hi PCL Of il N pee koci DoD DCX w 5 ___ lt Principles of Operation Figure 4 4 is identical to figure 4 3 with one exception which is the use of the READY input to the CPU As shown in figure 4 4 the CPU examines the state of the READY input during the READY input is high the CPU will proceed to T3 as shown in figure 4 3 If the READY input is low however the CPU will enter the Twajt state and stay there until READY goes high When READY goes high the CPU will exit the state and enter The external effect of using the READY in put is to preserve the exact state of the CPU signals at the end of T3 for an integral number of clock periods be fore finishing the machine cycle This stretching of the system timing in effect increases the allowable access time for memory or I O devices By inserting states the CPU can accommodate slower memory or slower I O devices A common use of the READY input is to single step the CPU using a manual switch It should be noted however that access to the on board memory and I O ports does not impose Ty state M4 OF we s n m m RAAT SOFT I Figure 4 4 Opcode Fet
49. d to RS232C level by A11 3 It is possible to transmit data simultaneously to both a TTL and an RS232C device however it is not possible to receive data simultaneously from the two different sources 4 11 4 12 5 SERVICE INFORMATION 5 1 INTRODUCTION This chapter provides service diagrams and reshipment Instructions for the SBC 80 05 5 2 SERVICE DIAGRAMS The SBC 80 05 parts location diagram and schematic diagram are given in figures 5 1 and 5 2 respectively The schematic diagram consists of three sheets each of which Includes grid coordinates Signals that transverse from one sheet to another are assigned grid coordinates at both the signal source and signal destination For example the grid coordinates 2ZD8 locate a signal source or signal destination on sheet 2 in Zone D8 A signal mnemonic that ends with a virgule slash slant solidus denotes that the signal is active low lt 0 4V Conversely a signal mnemonic without a virgule denotes that the signal is active high lt 2 0V Included for reference are schematic diagrams of the SBC 604 termination backplane figure 5 3 and the SBC 614 expansion backplane figure 5 4 5 4 SERVICE AND REPAIR ASSISTANCE United States customers can obtain service and repair assistance from Intel by contacting the MCSD Technical support Center in Santa Clara California at one of the following numbers Telephone From Alaska or Hawaii
50. ddress block for 2K of ROM EPROM using two IK chips is 0000 07FF the address block for 4K of ROM EPROM using two 2K chips is 0000 0FFF If 4K of ROM EPROM is installed in sockets A16 A17 325A the address jumper block is installed in position W3 Socket 17 contains the lower 2K address block 0000 07FF and socket A16 contains the upper 2K ad dress block 0800 0FFF The upper and lower address blocks are selected by decoding address bits ABB A BF To select either block of ROM EPROM ABC ABF must be false low When address bit ABB is low the lower 2K block is selected otherwise the upper 2K block is selected The target address within the selected 2K block is selected by address bits ABO ABA If 2K of ROM EPROM is installed in sockets A16 A17 the address jumper block is installed in position W4 Socket A17 contains the lower IK address block 0000 03FF and socket A16 contains the upper 1K ad dress block 0400 07FF The upper and lower address blocks are selected by decoding address bits ABA ABF To select either block of ROM EPROM ABB ABF must be false When address bit ABA is low the lower 1K block is selected otherwise the upper 1K block is select ed The specific address within the selected 1K block is selected by address bits and ABO ABO The actual read operation is initiated during T when the CPU pulls the RD line low The RD and IO M signals and ANDed by A23 3 IZB2 to produce the Memory Read MEM RD s
51. e is re o EN Principles of Operation quired If the READY input is low states are in serted until READY goes high During the WR line is driven high to disable the addressed memory device and terminate the memory write operation Note that the contents on the address and data lines do not change until the next state 4 11 I O WRITE TIMING Figure 4 6 also illustrates the timing of two successive I O write machine cycles the first without a state and the second with one state With the exception of the IO M status signal the timing of a memory write cycle and an I O write cycle are identical MW OR IOW TB Figure 4 6 Memory Write or I O Write Machine Cycles Principles o Operation 4 12 MULTIPLEXED ADDRESS DATA BUS The lower eight bits AD0 AD7 of the memory address I O address depending on whether a memory ref erence machine cycle or an reference machine cycle Is in progress are output by the CPU during the first clock cycle The ADOAD7 lines become the data bus during the second and third cycles T and T3 The trailing edge of the Address Latch Enable ALE signal issued by the CPU during T strobes these eight address bits into Demultiplexer A18 1ZC3 and into RAM IO Timer A15 3ZB6 The low order address bits ABO AB7 from 18 are placed on the SBC 80 05 address bus together with the
52. ead operation the CPU drives the RD output low during and waits for the addressed register to output data onto the data bus When the data is valid during T4 the CPU accepts the data and drives the RD output high During a write operation the CPU drives the WRT output low during T5 and outputs the data byte on the data bus The addressed register latches in the data during T4 when the CPU drives the WRT out put high 4 19 Command Status Register A command is written into the C S register during a write operation A com mand is used to specify either an input or output opera tion for Ports 01 and 02 define the input output or control assignment for Port 03 enable or disable the Port 01 and Port 02 interrupts and output the timer command The status of Ports 01 and 02 and the timer are read from the C S register during a read operation The contents of the C S register are not accessible ex cept through software 4 20 Port 01 Register This eight bit register can be pro grammed to be either an input port or an output port depending on the command contents of the C S register Also depending on the contents of the C S register this register can operate either in the basic mode or strobed and latched mode as described in Chapter 3 4 10 Gw e ee Tw SBC 80 05 4 21 Port 02 Register This eight bit register functions the same as described for Port 01 4 22 Port 03 Register This six bit register c
53. ed and the speed of the addressed memory or I O device Figure 4 2 is presented to show the relationship between an instruction cycle machine cycle and T state This example shows the execution of a Store Accumulator Direct STA instruction involving on board memory Notice that for this instruction the opcode fetch mach ine cycle requires four T states and the remaining three cycles each require three T states The opcode fetch is the only machine cycle that re quires more than three T states This is because the CPU SBC 80 05 must interpret the requirements of the opcode fetched during through before it can decide what must be done in the remaining T state s 4 7 OPCODE FETCH TIMING Figure 4 3 shows the timing relationship of a typical op code fetch machine cycle At the beginning of of every machine cycle the CPU performs the following a Pulls IO M low to signify that the machine cycle is a memory reference operation The CPU also drives status lines SO and S1 however these lines are not used by the SBC 80 05 Places high order bits PCH of program counter onto address lines A8 A15 These address bits will remain true until at least T4 INSTRUCTION CYCLE MACHINE CYCLE M2 T STATE T Ta TA T2 CLK TYPE OF MACHINE CYCLE MEMORY READ THE ADDRESS CONTENTS OF THE ADDRESS BUS FIRST BYTE OPCODE OF THE THE INSTRUCTION INSTRUCTION LOW ORDER BYTE TA BU PATENS I
54. ee I O ports The timer is 14 bit down counter that counts the 122 88 kHz timer clock input and outputs either a square wave or a pulse when the Terminal Count TC is reached The three I O ports and the timer can each be programmed to operate in one of four modes details of how these modes are used are presented in Chapter 3 During a machine cycle in which the on board I O sec tion or timer is accessed an I O Advanced Acknowledge 4 9 Principles of Operation AACK signal is generated to prevent the CPU from entering a Twajt state During a machine cycle involving system I O the CPU must acquire bus control and enter state until a Transfer Acknowledge XACK signal is received from the addressed I O device via the Multibus 4 18 REGISTER ADDRESSING The address assign ments of the four registers are as follows Command Status C S Port 01 Port 02 Port 03 The CPU timing for I O read and write machine cycles are described in paragraphs 4 9 and 4 11 respectively During T the Chip Enable CE input to A15 is driven low via NAND gate A28 3 3ZC6 when IO M is high and address bits AB3 and ABC ABF are low When NAND gate A28 3 is enabled the I O AACK signal is enabled and drives the CPU READY input high When 15 is thus enabled for an I O operation the trailing edge of the Address Latch Enable ALE signal latches in the register address specified by data bus bits DBO DB7 During a r
55. ematic diagram dwg no 2001600 1 6 EQUIPMENT REQUIRED BUT NOT SUPPLIED Because the SBC 80 05 is designed to satisfy a variety of applications the user must purchase and install only those components required to satisfy his particular needs A list of components required to configure all the in tended applications of the SBC 80 05 is provided in table 2 1 1 7 SPECIFICATIONS Specifications of the SBC 80 05 Single Board Computer are listed in table 1 1 Specifications 8 16 24 bits 2 03 usec 0 1 for fastest executable instruction 1 four clock cycles MEMORY ADDRESSING On Board ROM EPROM On Board RAM MEMORY CAPACITY On Board ROM EPROM 0000 0FFF 3E00 3FFF 4K bytes with Intel 8316 ROM s or 2716 EPROM s 2K bytes with Intel 8308 ROM s 8708 EPROM s Off Board Expansion 512 bytes Up to 65K bytes less on board memory in any combination of RAM ROM and EPROM I O ADDRESSING wes w wje e w _ On board I O addressing of parallel I O ports are as follows 8155 1815518155 8155 8155 Timer 8155 Time Command Port Port Port Low Order High Order Status 01 02 03 Byte Byte 606666 g General Information SBC 80 05 Table 1 1 Specifications Continued PARALLEL CAPACITY 22 programmable lines from the three 8155 I O ports can be expanded to 1102 programmable lines by using option
56. equest can be automati cally generated by the programmable interval timer upon completion of the selected function Two jumper select able interrupt requests can be automatically generated by the I O ports section of the 8155 when Ports 01 and 02 of the 8155 are programmed to operate in the latched and strobed mode Refer to Chapter 3 Nine jumper selectable interrupt request lines are available to the user for direct interfaces to user designated peripher al devices one via the I O edge connector and eight via the Multibus The 12 interrupt request lines may each be selectively routed to any of four 8085A CPU interrupt in puts ie TRAP RST 7 5 RST 6 5 and RST 5 5 via jumpers 1 3 SYSTEM EXPANSION Processing power memory and I O capacity may be in creased in SBC 80 05 based systems with single 5V M a a SBC 80 05 power adding standard Intel expansion boards High speed integer and floating point arithmetic capabilities may be added by using the SBC 310 High Speed Mathe matics Unit Memory for these systems may be expanded using the SBC 094 4K Byte CMOS RAM board Input output capacity may be increased by adding SBC 80 Digital boards In addition to these expansion op tions SBC 80 05 based systems equipped with multiple voltages may be expanded with many memory and I O options Memory may be expanded to 65 536 bytes by adding user specified combinations of RAM boards PROM boards
57. events slow master modules from being handicapped in their attempts to gain con trol of the bus but does not restrict the speed at which faster modules can transfer data via the same bus The most obvious applications for the master slave capabili ties of the bus are multiprocessor configurations high speed direct memory access operations and high speed peripheral control but are by no means limited to these three The Intel 8155 RAM IO Timer includes a programmable 4 bit interval timer which is configured by software to meet the system requirements Whevener a given time delay is needed software commands to the timer select the desired operating mode The current contents pre sent count of the timer counter and the timer mode bits may be read at any time during system operation There are four timer operating modes a Timer Out goes low during the second half of count Therefore the count loaded in the Count Length Register should be twice the timeout de sired b Timer Out remains high until the first half of the count has been completed and goes low for the SBC 80 05 second half of the count The count length is auto matically reloaded when the terminal count is reached single low pulse is generated upon reaching the terminal count this function is useful for gene rating real time clocks d A Divide by N Counter generatesa repetitive Timer Out low pulse a new pulse train 1 initiated
58. every time the terminal count is reached Serial 1 O capability is provided through the Serial Input Data SID and Serial Output Data SOD functions of the CPU These functions are controlled exclusively by software through the execution of RIM and SIM instruc tions The baud rate for the serial I O interface is deter mined by the system time available for the execution of serial I O support software Hence the maximum baud rate supported by the SBC 80 05 is solely dependent on the overall system real time software requirements Serial I O signals are TTL compatible and sockets are provided on the board for optional installation of RS232C line drivers and receivers The SBC 80 05 provides jumper selectable interrupts to the four interrupt request inputs of the 8085 CPU i e TRAP RST 7 5 RST 6 5 and RST 5 5 each of which generates a unique memory address A jump JMP in struction at each of these addresses can provide the link age to an interrupt handling subroutine for the appro priate interrupting device All interrupts except TRAP may be masked by software The TRAP interrupt should be used for conditions such as a power down sequence that require the immediate attention of the CPU Caution should be exercised when using the TRAP interrupt in conjunction with the maskable interrupts For further details refer to Chapter 3 of this manual SBC 80 05 interrupts may originate from 12 sources One jumper selectable interrupt r
59. he SBC 80 05 If the bus command is either an IOWC or a MWTC RDD is driven low and data is transferred from the SBC 80 05 to the Multibus The SBC 80 05 can lose control of the Multibus if its BPRN input goes high or when the CMD is completed This causes the Bus Controller Transfer Complete XCP input to go low In no case however will the SBC 80 05 lose control of the bus if the transfer is not complete or if the override function isinvoked The override function is discussed under paragraph 4 22 The timing of the bus signals is presented in figures 2 3 and 2 4 4 14 ON BOARD MEMORY The on board RAM and ROM EPROM are discussed in following paragraphs During a machine cycleinvolving on board memory a Memory Advanced Acknowledge MEM AACK signal is generated to maintain the CPU READY input high and prevent the CPU from entering a Twait state During a matching cycleinvolv ing system memory the CPU must acquire bus control and enter a Twait state until a Transfer Acknowledge XACK signal is received from the addressed memory device via the Multibus SBC 80 05 4 15 READ ONLY MEMORY The SBC 80 05 includes two sockets 16 A 17 to accommodate either two IK by 8 bit or two 2K by 8 bit masked read only memory ROM or programmable ROM EPROM chips A jumper block is installed in position W3 or W4 as re quired to accommodate the address decoding and power requirements of the particular ROM EPROM type in stalled The a
60. he op timum way of programming these functions Table 3 7 Interrupt Vector Memory Locations VECTOR LOCATION INTERRUPT PRIORITY Highest 2nd 3rd Lowest 3 14 TRAP INTERRUPTS There are special considerations that must be made when the TRAP interrupt is used The fact that the TRAP in terrupt is non maskable can present problems in at least two areas Interrupt driven systems often contain parameters that must be modified only within critical regions A critical region can be roughly defined as a section of code that once begun must complete execution before it or another critical region that corresponds to the same system parameter s can be executed A TRAP interrupt handler cannot safely alter such parameters either di rectly or indirectly by causing the execution of proce dures or tasks that may alter such parameters If the hardware generates a TRAP interrupt on power up or power fail the system must be able to process the TRAP interrupt before it is completely initialized It should also take into account that an interrupt routine that runs with interrupts disabled can still be interrupted by a TRAP Because of these considerations it is recommended that the TRAP interrupt only be used for system startup and or catastrophic error handling SBC 80 05 Programming Information Table 3 8 Timer Interrupt Routines MAIN PROGRAM INITIALIZES THE 8155 COUNTER AND STARTS THE COUNT BEFORE CONTINUING WITH ITS OT
61. high The BREQ output from the master modules is used by the Multibus when the bus priority isresolved by a parallel priority scheme as described in paragraph 2 28 BPRO is used by the Multibus when the bus priority is resolved in a serial priority scheme as described in para graph 2 27 The SBC 80 05 gains control of the Multibus when the BPRN input to the Bus Controller is driven low which on the next falling edge of BCLK drives its BUSY and ADEN outputs low The BUSY output indicates to all master devices that the bus is in use and prohibits any SBC 80 05 other master from acquiring control of the bus the ADEN output enables the Address Bus Drivers and Data Bus Drivers The ADEN output also activates the Bus Control BUS CTL signal which is applied to the input of gate A23 8 1ZB6 As discussed later the BUS CTL signal is used in conjunction with Transfer Acknowledge XACK to activate the READY input to the CPU The Bus Controller now examines the IO M RD and WT inputs and then outputs the appropriate command signal as follows Memory Read Command MRDC Memory Write Command MWTC Read Command IORC I O Write Command IOWC If the bus command is either an IORC or a the Bus Controller drives its Read Data RDD signal high to the Direction Input Enable DIEN input of bidirect ional Data Bus Drivers A34 A35 When DIEN is driven high data is transferred from the Multibus to t
62. high order address bits 7 This 16 bit address bus ABO ABF is distributed to Address Bus Drivers A31 A33 2ZA2 ROM EPROM A16 A17 3ZA5 and RAM A39 A40 3ZB6 4 13 MULTIBUS INTERFACE The Multibus interface consists of unidirectional Address Bus Drivers A31 A33 2ZA2 bidirectional Data Bus Drivers A34 A35 2ZB4 and Bus Controller A19 2ZD4 Bus Controller 19 arbitrates all requests for control of the Multibus When the SBC 80 05 acquires control of the Multibus the Bus Controller generates the appro priate memory or I O command and enables the address onto the Multibus by enabling the Address Bus Drivers The Bus Controller also enables the Data Bus Drivers which depending on whether the operation is a read or write transfers data from or to the Multibus The RC network R8 and C13 connected to the DLYADJ input of the Bus Controller provides a 70 nanosecond delay to ensure an adequate setup and hold relationship between the address data lines and the appropriate control sig nals The falling edge of the BCLK signal provides a timing reference for the bus arbitration logic Bus arbitration begins when the CPU needs access to an external mem ory or I O port When this requirement occurs the Com mand CMD and Off Board Request OFF BD REQ are both high at the Transfer Start Request XSTR input to the Bus Controller The Bus Controller drives Bus Re quest BREQ low and forces Bus Priority Out BPRO
63. ich is internal to Clock Generator A3 The Schmitt trigger converts the slow transition appearing at pin 2 into a clear fast rising synchronized RESET out put signal at pin 1 The RESET signal is inverted by open collector gate A24 3 to produce Initialize signal INIT which is distributed as shown in figure 4 1 The INIT signal clears the CPU program counter instruction regis ter and interrupt enable flip flop initializes the three I O ports of A15 to the input mode and sets Bus Con troller A19 to a known internal state 4 5 CLOCK CIRCUITS The time base for the SBC 80 05 is provided by Clock Generator 1ZC7 and crystal Y 1 The 19 6608 MHz output of A3 is divided by A12 2ZC6 to produce a 9 8304 MHz signal which is driven through gate A30 to produce Multibus clocks BCLK and CCLK Jumpers W7 and W8 are provided so that when removed some other master module can be used to generate one or both of these clocks if desired The 19 6608 MHz output of A3 is divided by A2 1ZD6 to produce 3 93216 MHz clock input to CPU Al which internally divides this into a 1 96608 MHz clock output This output 15 further divided by A14 2ZB6 to produce the 122 88 kHz timer input to A15 3ZD4 Principles of Operation 4 6 INSTRUCTION TIMING The execution of any program consists of read and write operations where each operation transfers one byte of data between the CPU and a particular memory or I O address Although the CPU can
64. ignal which is driven through A27 8 or A27 12 to the chip select C S input of the appro priate ROM EPROM chip When either type of ROM EPROM is installed and ad dressed NAND gate A38 3 3ZA6 is enabled and gene rates a Memory Advanced Acknowledge MEM signal which drives the CPU READY input high 4 16 RANDOM ACCESS MEMORY The SBC 80 05 in cludes 512 bytes of static read write memory 256 bytes in A39 A40 3ZB6 and 256 bytes in A15 3ZC4 Mem ory address block 3E00 3EFF is contained in A39 A40 and memory address block 3F00 3FFF is contained in A15 Memory address block 3E00 3EFF is selected when the CE1 and CE2 chip enable inputs to A39 A40 are driven low The CE1 inputs are driven low when IO M is low address bits AB9 ABD are high and address bits ABE w O O O I i Ti s Principles of Operation ABF are low The CE2 inputs are low when address bit ABS is low Memory address block 3F00 3FFF is selected when the JO M input signifying a memory operation and the CE chip enable input to A15 are driven low The CE input to A15 is driven low when IO M is low address bits AB8 ABD are high and address bits ABE ABF are low When either of the two blocks of RAM memory is ad dressed NAND gate 8 6 isenabled and generates MEM AACK which drives the CPU READY input high When A39 A40 is enabled the target address is specified by address bits ABO AB7 A memory read or write opera tion is s
65. ing cartons and pack ing material be saved for future use in the event the pro duct must be reshipped 2 3 INSTALLATION CONSIDERATIONS Important installation and interfacing criteria for fabri cating an SBC 80 05 computer based system and for using the SBC 80 05 in a single board environment are presented in following paragraphs 2 4 USER FURNISHED COMPONENTS Because the SBC 80 05 15 designed to satisfy a variety of applications the user must purchase and install only those components required to satisfy his particular needs A list of components required to configure all the in tended applications of the SBC 80 05 is provided in table 2 1 Table 2 2 lists alternative types and vendors of the connectors referenced in table 2 1 2 5 POWER REQUIREMENTS Power requirements for the SBC 80 05 are listed in table 2 3 Note that the power requirements not only depend on the intended application but on the user installed EPROM type as well Note also that filter capacitors must be furnished and installed by the user if any power supply other than a 5V supply is required 2 6 COOLING REQUIREMENT The SBC 80 05 dissipates 196 gram calories minute 0 79 BTU minute and adequate circulation of air must be provided to prevent a temperature rise above 559C 1319F 2 7 PHYSICAL DIMENSIONS Physical dimensions of the SBC 80 05 are as follows a Width b Height c Thickness 30 48 cm 12 00 inches 17 15 cm 6 75 inches
66. ion for Use BPRO AND PINS NOT USED BY NON MASTERS e N HC SBC 604 L BACKPLANE id aa BOTTOM Sema N IEN EE EEN RE SII G C m m Figure 2 5 Serial Priority Resolution Scheme DESCRIPTION REMARKS ASSUME BUS AVAILABLE Read to Read Write to Write Override Read to Write Mode Write to Read BREQ to BPRN Supplied by system From SBC 80 05 wften properly terminated After all voltages have stablized 2 13 Preparation for Use SBC 80 05 HIGHEST LOWEST PRIORITY PRIORITY J2 J3 J4 15 BPRN OBPRN NOTE NOTE NOTE NOTE 18 BREQ Pp BREQ D OU SBC 604 T Q BACKPLANE L __ _ _ _y BOTTOM BUS PRIORITY RESOLVER lt lt Zm O BREO INPUTS FROM MASTERS IN SBC 614 O BPRN OUTPUTS TO MASTERS IN SBC 614 NOTE REFER TO IMPORTANT INFORMATION PROVIDED IN 2 28 Figure 2 6 Parallel Priority Resolution Scheme 2 14 Preparation for Use 0 4 SBC 80 05 Table 2 8 SBC 80 05 Bus Interface DC Characteristics SIGNALS SYMBOL TEST CONDITIONS PARAMETER DESCRIPTION ADRO ADRF Output Low Voltage Io 32 mA Output High Voltage 5 2 mA Output Leakage High Vo Output Leakage Low
67. ldered Masterite NDD8GR25 DR H X Connector Micro Plastics MP 0100 25 DP 1 J1 Viking 3KH25 9JN5 J1 Parallel Viking 3KH25 JND5 I O TI H421011 25 NA Connector ITT Cannon EC4A050A1A Soldered PCB Mount Multibus Connector P1 Multibus Connector P1 43 86 0 156 43 86 0 156 Wire Wrap No Ears Unregu lated 5V J3 7 i Notes ii i Elfab Viking BS1562043PBB 2KH43 9AMK12 102247 001 102248 001 Edac Elfab 337 086 0540 201 BW1562D43PBB 09 66 1071 male 09 50 7071 female 87194 6 male 3 87025 4 female 09 66 1021 male 09 50 7071 female 89194 1 male 2 87025 5 female Connector heights are not guaranteed to conform to OEM packaging equipment Wirewrap pin lengths are not guaranteed to conform to OEM packaging equipment Pin Part number is 08 50 0106 key part number is 15 04 0219 Pin part number is 87023 1 key part number is 87116 2 Connector J3 does not accept key Connector numbering convention may not agree with board connector numbers 2 4 SBC 80 05 bach port are provided to accommodate the line drivers and I O terminators Parallel I O Figure 5 1 Port No IC Sockets Grid Ref 01 02 03 If Port 03 is to be used as control signals for Ports 01 and 02 install a line driver in socket A8 and an I O termina tor in socket A9 2 14 INPUT PORT TERMINATORS Refer to table 2 1 item 10
68. lt I z N 6 INSTALL ITEM 34 ON SOLDER SIDE OF BOARD NON CONDUCTIVE KX KSSYPL AND WL 5 ASSY VENDOR ID WITH CONTRASTING PERM ARE TRACKING DOCUMENTS NOTES UNLESS OTHERWISE SPECIFIED 96 275 FREE APPROX WHERE SHOWN 4 WORKMANSHIP PEK 99 0007 O01 AZ INCH WGH 3 Ju vo BE LEFT saner CONTRASTING PERM COLOR L ASSY PART NO 15 100299 2 ASSY DASH NO AND REV LEVEL WITH A Figure 5 1 SBC 80 05 Parts Location 5 3 5 4 I Perak R PU 22 amp amp TIMER CLK 2755 BUS CLOCK zzC RESET RESETS 2ZD8 ABZ ABF TZAR C 1 INIT INTT 36 INT amp 35 INTS 3 40 1 INT2 A INT 1 NTZ 4 3ZAZ TR PORT Qi one in ALE 3zD8 SZA INTR PORT 82 DBG 0R7 22498 3zZc3 8 aza2 TMR INTR RD 2208 SZDB B WRT 2208 3725 EXT INTR T dpud Iom 22D amp 22D8 3zA2 MEM AACK MEM RD 3288 BUS CTL WF ZD5 BZA pA OFF BD ACK 27205 NOTESY GND i RESISTANCE VALUES ARE IN OHMS sta tL 5 595 1 4 w slo cig 2 CAPACITANCE VALUES ARE IN MICROFARADS 419 Te ste Piz B gt PINS ARE GND ON 31 TI 12 4 i gt E gt cup IS Io 22H E zl B gt INSTALLED BY USER 42 laa 12 Ce A SYMBOLS SHOWN FOR CLARITY vec a E gt HEE DD ee G REV OF E e PWB ARE THE SAME c2
69. n in table 2 1 item 3 and power job connections are listed in table 2 5 Assuming that all the necessary components have been installed and that the jumpers have been 2 16 Output Low Voltage Output High Voltage Output Leakage High Vo Output Leakage Low Capacitive Load IOL 32 mA 2 mA 55V Vo 0 45V appropriately configured proceed with interfacing peri pheral equipment to the SBC 80 05 as described in fol lowing paragraphs 2 30 PERIPHERAL INTERFACING An RS232C or a TTL level serial I O device but not both and three TTL level parallel I O ports may be in terfaced to the SBC 80 05 as described in following paragraphs If a Teletype Model ASR 33 is to be used as the RS232C serial I O device it must be modified as described in Appendix B 2 31 SERIAL I O WIRING 5232 serial I O device must be interfaced to the SBC 80 05 via connector J2 A TTL level serial I O de vice may be interfaced to the SBC 80 05 via connector Jl or J2 Pin assignments for connectors J1 and J2 are listed in tables 2 9 and 2 10 respectively Figure 2 7 illustrates the cabling required for inter facing connector J2 to an RS232C serial I O device Notice that the transmission path from J2 to the RS232C device connector should be limited to 15 25 meters 50 feet In an extremely noisy electrical environment twisted pair wires may be used in a fashion similar to that shown in figure 2 8 For interfacing with teletype
70. nd the ad dress bus drivers are unidirectional This allows the SBC 80 05 full control of the Multibus but prevents other modules from accessing the SBC 80 05 memory and I O ports The SBC 80 05 provides 512 eight bit words of static Random Access Memory RAM Two Intel 8111 A4 devices provide 256 words in locations 3E00 3EFF The Intel 8155 RAM IO Timer provides 256 eight bit words of static RAM in locations 3F00 3FFF This 512 word RAM storage area requires neither refreshing nor clock inputs thereby providing the CPU immediate ac cess to the addressed location Two IC sockets are provided to allow the user to install either 2 or 4K bytes of Read Only Memory ROM The user may install two Intel 2716 2K x 8 or 8708 1K x 8 ultraviolet erasable and reprogrammable ROM s EPROM s for program development or install two In tel 8316E 2K x 8 or 8308 IK x 8 masked ROM s containing a dedicated program Depending on the type of ROM or EPROM installed the address locations are 0000 07FF two 1K x 8 bit chips or 0000 0FFF two 2K x 8 bit chips The Serial I O Interface is accomplished via the Serial Input Data SID and Serial Output Data SOD pins on the CPU Data on the SID line is loaded into the CPU by a RIM instruction data on the SOD line is set or cleared by a SIM instruction Data buffers are provided for TTL level interface Sockets are provided for the installation of level converters for RS232C interface Principle
71. nfigure the SBC 80 05 for your particular application Clarification of jumper pads Wd and W9 15 presented in paragraphs 2 20 through 2 24 2 5 for Use 2 20 CPU INTERRUPTS As described in table 2 4 jumper pad W5 is used for necting selected interrupts to the CPU TRAP RST 7 5 RST 6 5 and RST 5 5 The TRAP interrupt highest SBC 80 05 non maskable cannot be disabled by the program and has the highest interrupt it may be used to detect catas trophic system errors such as a power failure or bus failure The logic for detecting such catastrophic system errors must be developed by the system designer and priority is both edge and level sensitive and the RST 7 5 interrupt second highest priority is rising edge sensi tive The RST 6 5 and RST 5 5 interrupts are both high level sensitive RST 5 5 is the lowest priority For pur pose of examples jumper pad WS is illustrated in figure 2 1 2 22 RST 7 5 INTERRUPT The RST 7 5 interrupt is jumpered at the factory to the TMR Timer output of the 8155 It is recommended that the jumper remain in this position because the RST 7 5 interrupt is rising edge sensitive and the 8155 outputs a single ground true pulse when the terminal count is reached The trailing rising edge of this pulse is used to trigger the RST 7 5 interrupt preferably input to the SBC 80 05 CPU via the Multi bus interrupt line Refer to paragraph 2 24 2 21 TRAP INTERRUPT
72. o be fabricated requires a relay a diode a thyractor a small vector board for mounting the components and suitable hardware for mounting the assembled relay card A circuit diagram of the relay circuit card is included in figure A 4 this diagram also includes the part numbers of the relay diode and thyractor Note that a 470 ohm resistor and 0 1 F capacitor may be substituted for the thyractor After the relay circuit card has been assembled mount it in position as shown in figure A 5 Secure the card to the base plate using two self tapping screws Connect the relay circuit to the distributor trip magnet and mode switch as follows a Refer to figure 4 and connect a wire Wire from relay circuit card to terminal L2 on mode switch See figure A 6 b Disconnect brown wire shown in figure 7 from plastic connector Connect this brown wire to terminal L2 on mode switch Brown wire will have to be extended c Refer to figure A 4 and connect a wire Wire B from relay circuit board to terminal L1 on mode switch A 3 EXTERNAL CONNECTIONS Connect a two wire receive loop a two wire send loop and a two wire tape reader control loop to the external device as shown in figure A 4 The external connector pin numbers shown in figure A 4 are for interface with an RS232C device A 4 iSBC 530 TTY ADAPTER The 1SBC 530 TTY adapter which converts RS232C signal levels to an optically isolated 20 m
73. of this external stack which allows subroutine nesting that is bounded only by the system memory size Two Intel 8111 A4 RAM chips provide 256 bytes of static read write memory an Intel 8155 combination RAM IO Timer provides an additional 256 bytes of static read write memory Two sockets are provided for in stalling up to 4K bytes of nonvolatile read only memory ROM which may be added in 2K byte increments using Intel 2716 Ultraviolet Erasable and Reprogram mable ROM s EPROM s or 8316E Masked ROM s Optionally if only 2K bytes are required ROM may be added in 1K byte increments using Intel 8708 EPROM s or 8308 Masked Twenty two programmable parallel I O lines are imple mented using the I O ports of the Intel 8155 RAM IO Timer The system software is used to configure the I O lines in any combination of unidirectional input or out put ports The I O interface may be customized to meet specific peripheral requirements In order to take full ad vantage of the large number of possible I O configu rations sockets are provided for interchangeable I O 1 0 POR TS 41 52 07 c MULTIBUS CONNECTOR RAM 1 0 PORTS AND TIMER ADDRESS LATCH NOT USED Figure 1 1 SBC 80 05 Single Board Computer 1 1 General Information line drivers and terminators Hence the flexibility of the 1 O interface is further enhanced by the capability of selecting the appropriate combination of optional line
74. onds to interrupt requests originating from jumper selectable sources As shown in figure 4 1 these interrupt re quests may be generated by the on board timer and parallel I O ports by one or more devices v a the Multi bus or by an external source The Bus Interface allows the SBC 80 05 to use a system bus that is common to other master devices e g CPU s and DMA controllers thus allowing system memory and I O devices to be shared on a priority basis The pri mary element of the Bus Interface is Bus Controller A19 which operates synchronously with the bus clock BCLK and consists of the following functional sec tions a Bus arbitration logic to resolve bus contention in multiple master systems b Timing logic initiated by the bus arbitration logic to ensure adequate setup and hold times for the ad dress and data placed on the Multibus also gene rates read write control signals c Output drive logic for driving the bus memory and I O command control lines When the SBC 80 05 gains control of the Multibus to perform a write operation the Bus Controller gates the device address and data onto the Multibus and is sues a Write command In performing a read opera tion the Bus Controller gates the device address onto the Multibus and issues a Read command Operations between the CPU and the on board memory and I O ports do not require the Multibus Notice in figure 4 1 that the data bus drivers are bidirectional a
75. pecified by the R W input During a read opera tion the CPU Write WRT output is false high and a read occurs by default During a write operation the CPU WRT output is true and a write occurs The data output of A39 A40 is disabled during a write operation by the false MEM RD signal applied to the OD inputs When A15 is enabled for a memory operation the trailing edge of the Address Latch Enable ALE signal latches in the target address bits specified by data bus bits DBO DB7 During a write operation the CPU WRT output is true and a write occurs during a read opera tion the CPU RD output is true and a read occurs Data is read from and written into A15 via its address data pins ADO AD7 4 17 ON BOARD I O PORTS AND TIMER The SBC 80 05 includes three parallel I O ports each of which can be hardware configured as an input port or an output port but not both One of the three ports Port 03 can be programmed to provide status information to allow Port 01 and Port 02 to operate in a handshake mode Whether these three ports are used as input ports or output ports depends on whether the user installs in put terminators or output drivers in sockets A4 through A9 See figure 5 2 sheet 3 These three I O ports 256 bytes of RAM and a 14 bit binary down counter timer are contained in 15 3ZC4 The I O section of A15 consists of four regis ters a Command Status C S register and one register for each of the thr
76. ponents User Furnished Connector Details Power Requirements Jumper Selectable Options Connector Pl Pin Assignments Multibus Signal Functions SBC 80 05 Bus Interface AC SBC 80 05 Bus Interface DC Characteristics Connector J1 Pin Assignments Connector J2 Pin Assignments Figure Title SBC 80 05 Single Board Computer CPU Interrupt Input Jumpers Multibus Interrupt Jumpers SBC 80 05 Bus Exchange Timing SBC 80 05 Bus Control Timing Serial Priority Resolution Scheme Parallel Priority Resolution Scheme RS232C Serial I O Device Interface Cabling TTL Level Serial I O Device Interface Cabling Command Register Format Port 00 Status Register Format Port 00 Page 1 3 252 2 6 2 1 2 10 2 11 2 13 2 15 2 18 2 18 Page 1 1 2 8 2 9 2 12 242 2 13 2 14 2 17 25157 3 2 20 Table Title Parallel I O and TTL Level Serial I O DC Characteristics SBC 80 05 Memory I O Register Addresses Port 03 Programmable Modes Baud Rates Vs Count Lengths Serial Input Data Routine Non Interrupt Driven Serial Output Data Routine Non interrupt Driven Interrupt Vector Memory Locations Timer Interrupt Routines Page 2 19 3 1 3 2 3 3 3 4 ILLUSTRATIONS Figure Title Timer Format SBC 80 05 Block Diara Typical CPU Instruction Cycle Typical Opcode Fetch Machine Cycle Opcode Fetch Machine Cycle With Wait Memory Read or I O Read Machine Cycles Memory Write or I
77. s See fig ure 5 4 See Multibus connector de tails in table 2 2 Power inputs and Multibus interface Not required if 1 SBC 80 05 is installed in an SBC 604 614 or 2 if SBC 80 05 is used ina single board configuration that needs 5V power only see item 6 See parallel I O connector details in table 2 2 Interfaces parallel I O de vices and TTL level serial I O device to SBC 80 05 Interfaces RS232C or TTL level serial I O device to SBC 80 05 Either RS232C or TTL level serial I O can be accommodated but not both Male and female connector required See table 2 2 for description Male and female connector required See table 2 2 for description Provides alternative SV power input when SBC 80 05 is used in a single board configuration that needs 5V power only Refer to table 2 3 EPROM s or ROM s One or two each of one of the following types of EPROM s ROM 5s Intel 2716 2K x 8 or 8708 1K x 8 EPROM On board UV erasable PROM s for program development Intel 8316E 2K x 8 or 8308 1K x 8 ROM On board masked ROM s for dedicated program SBC 80 05 Preparation for Use Table 2 1 User Furnished and Installed Components Continued ITEM RS232C line driver collector I O Terminators Capacitors 2 10 LINE DRIVER RECEIVER As specified in t
78. s of Operation pr 19 6608 MHz CLOCK A3 d RESIN RESET AN CLK 5 A2 ALE CLK IN 2 3 93216 MHz RS232C SERIAL I O PORT NOTE 3 SOD SID TTL PARALLEL 1 0 PORT TRAP RST 5 5 RST 6 5 CONTROL RST 7 5 CLK OUT TO FROM ADO AD7 SYSTEM BUS INTERRUPT SELECT 122 88 KHz RESET EXT INTERRUPT TIMER OUT PORT 01 7 1 0 NOTE 2 PORTS Eos EE T ALAS 4 NOTE 2 PORT 03 ARAS Lo 6 NOTE 2 A15 NOTE 4 DATA BUS CONTROL BUS INTR PORT 01 INTR PORT 02 RAM IO TIMER SBC 80 05 INIT 9 8304 MHz 9 8304 MHz ADDRESS BUS DRIVERS A31 A32 A33 ADDRESS BUS ENABLE ABO AB7 ROM EPROM A16 A17 L DATO DAT7 damn BIDIRECTIONAL DATA BUS DRIVERS A34 A35 MULTIBUS IN OUT BUS BPRN CONTROLLER D A19 BPRO ISC CONTROL RESET W1 ax BUS OVERRIDE TO FROM INTERRUPT SELECT INTO INT7 NOTES 1 IC SOCKETS ONLY USER MUST INSTALL 2716 or 8708 EPROM OR 8316E 8308 ROM 8716 8316 0000 0FFF 8708 8308 0000 07FF 2 SOCKETS ONLY USER MUST INSTALL DRIVERS SN7400 740B ETC OR TERMINATORS INTEL 901 OR SBC 902 IC SOCKETS ONLY USER MUST INSTALL RS232C
79. t this function is useful for generating real time clocks A Divide by N Counter generates a repetitive Timer Out low pulse a new pulse train is initiated every time the terminal count is reached SBC 80 05 4 3 CIRCUIT ANALYSIS The schematic diagram for the SBC 80 05 is given in figure 5 2 The schematic diagram consists of three sheets each of which includes grid coordinates Signals that transverse from one sheet to another are assigned grid coordinates at both the signal source and signal des tination For example the grid coordinates 2ZB1 locate a signal source or signal destination as the case may be on sheet 2 Zone Bl Both active high and active low signals are used A signal mnemonic that ends with a virgule e g DAT7 denotes that the signal is active low lt 0 4V Conversely a signal mnemonic without a virgule e g ALE denotes that the signal is active high gt 2 0V 4 4 INITIALIZATION When power is applied in a start up sequence the con tents of the CPU program counter instruction register and interrupt enable flip flop are subject to random fac tors and cannot be predicted For this reason a power up sequence is used to set the CPU as well as Bus Con troller A19 and the I O ports of A15 to a known in ternal state When power is initially applied to the SBC 80 05 capa citor Cl 1ZC7 begins to charge through resistor R4 The charge developed across Cl is sensed by a Schmitt trigger wh
80. tches the instruction in loca tion 0000 It is expected that this location in ROM EPROM will reference a user defined routine such as automatic bootstrap loader for a paper tape reader mag netic type disc etc 3 3 PARALLEL I O SECTION The Intel 8155 includes two 8 bit parallel I O ports Port 01 and Port 02 and one 6 bit parallel I O port Port 03 Each of these three ports can be individually hardware configured as either an input port or an output port but not both Port 03canbe programmed toallow Port 01 and Port 02 to operate in a handshake mode with their associated input or output device In this case Port 03 must be specifically hardware configured to per form this function and cannot be used as an input port or as an output port 3 4 I O REGISTER ADDRESSING The I O section consists of a Command Status C S regi ster and one register for each of the three I O ports Addresses for these four registers are provided in table 3 2 SBC 80 05 Memory Addresses CONFIG LEGAL ADDRESSES ILLEGAL ADDRESSES 0000 03FF 0000 07FF 0400 07FF 0000 07FF 0000 0FFF 0800 0FFF 3 1 Programming Information Table 3 2 1 O Register Addresses Command Status Port 01 Port 02 Port 03 LSB of Timer Count MSB of Timer Count Unused Unused 3 5 PROGRAMMING THE COMMAND REGISTER PORT 00 The Command register consists of eight l bit latches Four bits 0 3 define the mode of Port 01 and Port 02 two bi
81. ti cally reloaded when the terminal count 1 reached c A single low pulse is generated upon reaching the terminal count this function is useful for generating real time clocks d A Divide by N Counter generates a repetitive Timer Out low pulse a new pulse train 15 initiated every time the terminal count is reached Bits 7 6 of the Command Status C S register are used to start and stop the timer Details concerning program ming the timer section are given in Chpater 3 4 24 INTERRUPTS As mentioned in paragraph 4 22 when Port 03 is used as control bits PC0 and PC3 are used for Port 01 and Port 02 interrupts These inter rupts plus the TIMER out signal are routed to inter Principles o Operation rupt select jumper pad 5 From W5 these interrupts may be connected to the CPU interrupt inputs or to the Multibus via jumper pad W9 See paragraphs 2 20 through 2 24 4 25 SERIAL I O COMMUNICATION Serial in and serial out communication is implemented by software RIM and SIM instructions respectively For TTL level serial I O input data is received at the SID in put of the CPU via inverter A22 2 1ZD6 data from the SOD output of the CPU is transmitted via inverter 22 4 For RS232C serial I O serial input data is inverted and converted to TTL level by A10 3 the output of A10 3 is applied to the SID input of the CPU via inverter A22 2 For RS232C serial output the output of A22 4 is in verted and converte
82. ts 4 5 enable or disable the Port 01 and Port 02 interrupts in the strobed input output mode and two bits 6 7 define the programmable timer com mand Refer to paragraph 3 10 The Command register can be altered at any time by performing an write to location 00 The specific meaning of each register command bit is shown in fig ure 3 1 TM TM DEFINES PORT 01 0 1 OUTPUT DEFINES PORT 02 00 ALT 1 11 2 01 ALT 3 10 ALT 4 _ _ DEFINES PORT zl ENABLE PORT 02 0 DISABLE ENABLE PORT 01 INTERRUPT 1 ENABLE INTERRUPT s 00 NOP DO NOT AFFECT COUNTER OPERATION 01 STOP NOP IF TIMER HAS NOT STARTED STOP COUNTING IF TIMER IS RUNNING 10 STOP AFTER TC STOP IMMEDIATELY AFTER PRESENT TC IS REACHED IF TIMER HAS NOT STARTED TIMER COMMAND START LOAD MODE AND CNT LENGTH AND START IMMEDIATELY AFTER LOADING IF TIMER IS NOT PRESENTLY RUNNING IF TIMER IS RUNNING START THE NEW MODE AND CNT LENGTH IMMEDIATELY AFTER PRESENT TC IS REACHED Figure 3 1 Command Register Format Port 00 3 6 READING THE STATUS REGISTER PORT 00 The Status register consists of seven 1 bit latches Bit 0 5 define the status of the ports and bit 6 defines the status of the timer The contents of the Status register can be obtained at any time by performing an I O read to location 00 The format of the Status register is pre
83. ut high and inhibits the BPRN input to all lower priority mod GND GND 5 VDC 5 VDC 5 VDC 5 VDC 12VDC 12VDC 5 VDC 5 VDC GND GND BCLK INIT BPRN BPRO BUSY BREQ MRDC MWTC IORC IOWC XACK SBC 80 05 ules When finished using the bus the J2 master pulls its BPRO output low and passes control to the J3 master If the J3 master does not desire to control the bus at this time it pulls its BPRO output low and passes con trol to the J4 master The serial priority scheme can be implemented in a user designed system bus if the chaining of BPRN and BPRO signals are wired as shown in figure 5 3 Table 2 5 Connector P1 Pin Assignments SIGNAL FUNCTION IE SIGNAL FUNCTION Ground Power input Power input Power input Ground Bus Clock 9 8304 MHz System Initialize Bus Priority In Bus Priority Out Busy Bus Request Memory Read Command Memory Write Command I O Read Command I O Write Command Transfer Acknowledge Constant Clock 9 8304 MHz Interrupt request line 6 Interrupt request line 7 Interrupt request line 4 Interrupt request line 5 Interrupt request line 2 Interrupt request line 3 Interrupt request line O Interrupt request line 1 Address bus Address bus Data bus Ground Power input Power input Ground All unassigned pins are reserved do not use
84. ut must be connected by the user to the selected CPU interrupt via a jumper wire LSB OF CNT LENGTH I O TiaiTuolTaalT Tal T The timer includes a 16 bit register for holding the count Maj 13 12 11 10 uv length 14 bits and the operating mode 2 bits The I O address for the low order byte least significant bits of a SS count length and high order byte most significant bits TIMER MSB OF CNT LENGTH of count length and timer mode is 04 and 05 respective MODE ly Figure 3 3 shows the timer format and I O addresses The timer I O addresses serve a dual purpose During a I O Write operation the count length bits 0 13 and mode bit 14 15 are loaded into the 16 bit register 0 OUTPUT LOW DURING SECOND HALF OF during an I O Read operation the present count the COUNT SEE NOTE count at the time of the I O Read operation and the SQUARE WAVE OUTPUT I E THE PERIOD mode bits are read To ensure that the correct count is OF THE SQUARE WAVE EQUALS THE COUNT read it is preferable to stop counting read the counter LENGTH PROGRAMMED WITH AUTOMATIC and then reload the counter and continue counting RELOAD AT TERMINAL COUNT SINGLE PULSE OUTPUT UPON TC BEING REACHED AUTOMATIC RELOAD I E SINGLE PULSE OUTPUT EVERY TIME TC IS REACHED By connecting the counter output to the RST 7 5 input of the CPU the CPU can be interrupt driven at the baud rate desired for serial I O communication The count Gas OF an asym
85. ution Parallel Priority Resolution Single Board Configuration Peripheral Interfacing Serial Wiring Parallel I O Wiring CHAPTER 3 PROGRAMMING INFORMATION Introduction Memory Addressing Page 1 1 1 1 1 2 1 3 1 3 1 3 1 3 Page 2 1 2 1 2 1 2 1 2 1 2 1 251 2 1 CONTENTS Parallel I O Section I O Register Addressing Programming the Command Register Port 00 Reading the Status Register Port 00 Port 01 Register Port 02 Register Port 03 Register Timer Section Serial Communication Interrupts Timer Interrupts TRAP Interrupts CHAPTER 4 PRINCIPLES OF OPERATION Introduction Functional Circuit Analysis Initialization Clock Circuits Instruction Timing Opcode Fetch Timing Memory Read Timing I O Read Timing Memory Write Timing I O Write Timing Multiplexed Address Data Bus Multibus Interface On Board Memory Read Only Memory Random Access Memory On Board I O Ports and Timer Register Addressing Timer Addressing Interrupts Serial Conimuiftication 5 SERVICE INFORMATION Introduction Service Diagrams Service and Repair Assistance APPENDIX A TELETYPEWRITER MODIFICATIONS 3 1 3 1 3 2 3 2 3 2 3 2 3 2 3 3 3 4 3 6 3 6 3 6 Page 4 1 4 1 4 3 4 3 4 3 4 3 4 4 4 6 4 6 4 7 4 7 4 8 4 8 4 9 4 9 4 10 4 10 4 11 4 11 5 1 5 1 5 1 1 Table Title Specifications User Furnished and Installed Com
86. xternal Interrupt 1 1 These pins are used as control signals when Ports 01 and 02 are used in the latched and strobe mode 2 Pin numbers refer to board connector pins only they are not necessarily the same on the mating connectors Table 2 10 Connector J2 Pin Assignments RS232C leve RDR CTL Reader Control RS232C level SID Serial In Data RS 232 level SOD Serial Out Data SBC 80 05 Preparation for Use Table 2 11 Parallel I O and TTL Level Serial I O DC Characteristics PARAMETER TEST SIGNALS SYMBOL DESCRIPTION CONDITIONS UNITS 8155 Output Low Voltage DRIVER Output High Voltage RECEIVER Input Low Voltage Input High Voltage Input Current at Low V Input Current at High V Capacitive Load TTL SID Input Low Voltage Input High Voltage Input Current at Low Input Current at High TTL SOD Output Low Voltage Output High Voltage Capacitive load value is approximate loL 2 0 mA log 400 VIN 0 45 VIN 5 0 loL 20 mA loH 0 mA 2 19 2 20 CHAPTER 3 PROGRAMMING INFORMATION 3 1 INTRODUCTION This chapter lists the SBC 80 05 on board memory address assignments provides programming details for the parallel I O section timer section and serial I O port and describes the 8085A CPU interrupt structure The 8085A CPU instruction set is provided in Appendix A a complete description of programming with Intel s assembly language

iSBC 80/05 SINGLE BOARD COMPUTER HARDWARE

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