UM10752 OM13489 16-bit GPIO Daughter Card User Manual
Contents
1. 7 4 5 PCA9673 PCAL9539A PCA9539A PCA9539R PCA9539 5 tiniceeiiue tinere teres 8 4 6 PCAL6416A 64 8 5 Connector Pinout 9 5 1 GPIO Target Board Connector 9 5 2 CN5 Fm Development Board Connector 9 5 3 CN4 Tester 10 6 Legal information eee 13 6 1 Definitions ssssssseseeeeenee 13 6 2 Disclaitfiers oiii ne f ente tees 13 T List of figures 14 8 List of tables 15 9 CONMLCIUS me 16 Please be aware that important notices concerning this document and the product s described herein have been included in the section Legal information NXP B V 2014 All rights reserved For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 09 January 2014 Document identifier UM107522. INT CNSG CNSG 3 CNEGg2 CN5G 1 lt Fm BOARD ADDR UDDI a 1 m 1 n amp H Ch419 L HNT cge cN4 8 CN4 7 lt UDDP LTST Ci5BkGkTCGRN I2C TESTER H1 HDLINT PARD POUND 3 2 Document Number GND Dates 12 13 2013 11 08 57 AM Sheet 2 2 1 UDDP 5SOKRETCRED lt LTSTA La z NXP SEMICONDUCTORS NOUNT PAD ROUND 3 2 0 13489 1 08 Jenue y 195 0139 19 91 6875 CSZOLINN SJ10 onpuooiuleS dXN NXP Semiconductors UM10752 6 Legal information 6 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 6 2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information In no event shall NXP Semiconductors be liable for any indirect incidental punitive special o
3. 2920 pamasa syu 102 dXN PKG VARIABLES FOR PINS 1 2 3 jPS 1 gt 1 9 3 MT 00 de gt 100 ih I0 S oy gt 188n BNO CNL 16 5 42 10 CNI 3 cN I0 See 5 CNi 7 Iie N2 7 21 5 2 6 ENL 5 12 5 CNL 4 TOL es 2 4 CNL 3 1 Soy CcN2 3 2 gt pM CN2 2 EN1 1 CN2 1 10912 1008 1091 1082 1003 1004 1005 1096 1087 1010 1011 1012 1013 1014 1015 1016 1017 PECALEALEAANH 188m Template tor GPIO package GNO tov ton tuu tbe 10c05 iicos 14 lor 1fvon Naor Ais oras ks Xll NXP SEMICONOUCTORS GPIO 16BIT FAMILY fRug13 TITLE Document Number 0 134389 REU Date 12 13 2013 11 08 57 RM 1 06 Sheet 1 2 Jenue y 195 0139 19 91 6872 CSZOLINN S10 onpuooiuleS dXN jenueui 1951 vlog 60 0 2 seuirejosip joefqns si jueuinoop SIY 9130 CI 5540 pamasa syu 102 CNSG 18e 56 17 CNSG 14 4 INT 56 13 lt BESET CNBG 12 50 CNSG 11 203 55 10 lt GNO CN56 9 lt 5 CNEG gB merus CN5G 7 Ze U CN56 6 RESI CNSG 5
4. Jumper Configuration for PCA8575 PCA9535A PCA9535C PCA9535 PCA9555A PCA9555 PCA9675 PCAL9535A PCAL9555A PCF8575 PCA9671 The PCA9671 implements three address pins and RST This configuration ignores the power supply setup but normally only JP4 with a jumper between pins 2 amp 3 need be applied to power the device at 3 3V To configure the function pins apply jumpers between pins 1 amp 2 on JP9 JP10 and JP11 to configure pin 2 and pin 3 as addresses and pin 1 as RST Then apply jumpers to JP1 JP7 and JP8 to configure the desired address Logic high or logic low is labeled on the board but is incorrect for JP7 and JP8 Using the labels a 0 is actually a 1 and a labeled 1 is actually a 0 The schematic is correct and note the square solder pad is pin 1 quisi ur Oo noooo jJ Q PO 7 000 2 4 4 R e jens 4 4 vel Loo ERES 0 on PINA Fig 6 Jumper Configuration for PCA9671 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 2 0 09 January 2014 7 of 16 NXP Semiconductors U M1 0752 OM13489 16 bit GPIO User Manual 4 5 PCA9673 PCAL9539A PCA9539A PCA9539R PCA9539 The PCA9673 and PCA9539 series implement two address pins RST and INT This configuration ignores the powe
5. 2 and SMBus low power I O port with PCA9539R interrupt and reset PCA9539RPW Low voltage 16 bit 2 I O port with interrupt PCA9555A and weak pull up PCA9555APW PCA9555 16 bit l C bus and SMBus port with interrupt PCA9555PW 2 PCA9671 16 bit expander for with PCA9671PW 5 2 PCA9673 Remote 16 bit expander for Fm IC bus with PCA9673PW interrupt and reset 2 A PCA9675 5 expander for Fm I C bus with PCA9675PW Low voltage translating 16 bit PC bus SMBus PCAL6416A expander with interrupt output reset and PCAL6416APW configuration registers Low voltage 16 bit 2 I O port with interrupt PCAL9535A and Agile PCAL9535APW Low voltage 16 bit I C bus and SMBus low power PCAL9539A port with interrupt and reset Low voltage 16 bit I C bus GPIO with Agile I O PCAL9555A interrupt and weak pull up PCAL9555APW PCF8575 Remote 16 bit I O expander for I C bus PCF8575PW All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 2 0 09 January 2014 NXP Semiconductors U M1 0752 OM13489 16 bit GPIO User Manual The pin configuration of these devices varies only a bit and the different pin selections are made via jumpers 2 Features of the OM13489 16 bit GPIO Daughter Card Direct connection to OM13320 Fm Development kit Footprint for a TSSOP24 pa
6. under test is not PCA L 6408A leave this jumper open JP4 selects between 5V and 3 3V for the main power supply on pin 16 of the device under test Add a jumper between pins 2 amp 3 for 3 3V or 1 amp 2 for 5V For external power supply operation do not jumper and JP4 and connect a voltage source to TP2 for the main power supply connected to pin 16 of the device under test Connect another external voltage source to TP1 if the device under test is PCA L 6408A See the schematic section at the end of this document for more details ML OOOOO TESTER ND CN4 00000 noooo e 48 e 21 000 2 4 6 2 oo a TUE EHE 20 ei 2 Pii o PINa o eina o OF AST E Fig 3 Power Jumpers and External Power Test Points SCL and SDA Jumpers The I2C bus signals SDA and SCL supplied to the device under test can be sourced from either the Fm board via CN5 or the tester via CN4 Jumpers JP5 and JP6 select the source Shorting pins 1 to 2 source from the Fm board while shorting pins 2 to source from the tester connector CN4 See the schematic section at the end of this document for more details TESTER ND e 3 Bn4unanpea 2 4 Je ae HE TUE ina oe ad 2 PIN o OF RST E Fig 4 SDAand SCL Jumpers PCA8575 PCA9535A PCA9535C PCA9535 PCA9555
7. 6 bit GPIO portfolio of products Table 1 lists the supported devices The 13489 16 bit GPIO Daughter Card is shipped with no GPIO device soldered to the board The user must purchase the device he is interested in evaluating in a TSSOP24 package the ordering part number suffix should be PW and the package designation should be SOT355 1 These leaded packages should be relatively easy to solder to the board with a low wattage fine tipped soldering iron NOTE pin 1 orientation pointing toward C1 Please note that a fix is needed for correct operation of the A0 jumper JP1 A wire must be soldered between pin 2 of JP1 and the via directly below to make connection to pin 21 on the device under test IC1 See Section 3 2 for additional details Table 1 Devices Supported by OM13489 16 bit GPIO Daughter Card Device Description Orderable Part Number Low voltage translating 16 bit PC bus SMBus PCA6416A expander with interrupt output reset and PCA6416APW configuration registers 2 PCA8575 on expander for I C bus with PCA8575PW PCA9535A Low voltage 16 bit 2 I O port with interrupt PCA9535APW 3 12 PCA9535C nonc and SMBus low power I O port with PCA9535CPW ag 12 PCA9535 E and SMBus low power I O port with PCA9535PW Low voltage 16 bit I C bus port with interrupt PCA9539A andireset PCA9539APW 16 bit I C bus and SMBus low power I O port with PCA9539 interrupt and reset 16 bit
8. A PCA9555 PCA9675 PCAL9535A PCAL9555A PCF8575 The PCA8575 PCA9535 A C PCA9555 A PCA9675 and PCF8575 series implement three address pins and INT This configuration ignores the power supply setup but normally only JP4 with a jumper between pins 2 amp 3 need be applied to power the device at 3 3V All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 2 0 09 January 2014 6 of 16 NXP Semiconductors U M1 0752 UM10752 4 4 OM13489 16 bit GPIO User Manual To configure the function pins apply jumpers between pins 1 amp 2 on JP10 and JP11 to configure device pin 2 and pin 3 as addresses Apply a jumper between pins 2 amp 3 on JP9 to configure device pin 1 as INT Then apply jumpers to JP1 JP7 and JP8 to configure the desired address Logic high or logic low is labeled on the board but is incorrect for JP7 and JP8 Using the labels a 0 is actually a 1 and a labeled 1 is actually a 0 The schematic is correct and note the square solder pad is pin 1 1382 _ P NDi1357 0000 y ef 00000 T 555 1 noooo 5 Jc 2n noooo P 2 4 efie je Sonna 2 406 104 aoi ge 0 5010 9 pana oo unnie RST o ee lO O on 2142 PTS AL A2 gt dii Fig 5
9. NT LED and JP9 pin 3 JP9 pin 1 JP11 pin 3 JP3 pin 1 CN3 pin 3 and JP4 pin 3 CN3 pin 3 and JP4 pin 3 JP3 pin 1 JP9 pin 1 JP11 pin 3 Interrupt to INT LED and JP9 pin 3 SDA Bus 1 to U1 pin 15 SCL Bus 2 not used No connect Table3 CN5 Fm Board Connector CN5 Pin Number Function 1 2 3 SCL 4 SDA2 5 INT 6 RESET 7 5V 8 3 3V 9 GND 10 GND 11 3 3V 12 5V 13 RESET 14 INT 15 SDA 16 SCL2 17 m 18 No connect 5 3 CN4 Tester Connector Generation inspection and logging of l C Bus data is easily achieved with third party development tools from Total Phase www totalphase com There are two tools called Aardvark and Beagle that direct connect to this board through CNA Note Since SDA and SCL are both connected to the device under test the Aardvark and the Fm Development board cannot be used simultaneously The Beagle a bus sniffer does not have any issues Table4 Tester Connector CN4 Pin Number Function SCL Ground SDA 5V 5V 5V Ground Board Connection U1 pin 14 U1 pin 15 JP3 pin 3 JP3 pin 3 JP3 pin 3 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 2 0 09 January 2014 10 of 16 jenuew 1951 vlog 60 0 2 seuirejosip joefqns si jueuinoop SIY uomeuuojul 9110
10. UM10752 OM13489 16 bit GPIO Daughter Card User Manual Rev 2 0 09 January 2014 User manual Document information Info Content Keywords Fm Development Kit OM13320 GPIO OM13303 Abstract Installation guide and User Manual for the OM13489 16 bit GPIO Daughter Card that connects to OM13320 Fm Development Kit This board permits easy and simple evaluation of most of NXP s 16 bit GPIO portfolio of products NXP Semiconductors UM10752 Revision history OM13489 16 bit GPIO User Manual Rev Date 2 0 20140109 1 0 20131011 Description Added AO jumper hardware fix and CN5 schematic changed from 14 pin to 18 pin with 4 pins not connected for correct connector seating on the Fm board Active pins remain the same Labels for JP7 and JP8 A1 and A2 address jumpers are incorrect 1 connects to ground and 0 connects to Initial Release Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com UM10752 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 2 0 09 January 2014 2 of 16 NXP Semiconductors UM10752 OM13489 16 bit GPIO User Manual 1 Introduction UM10752 The OM13489 16 bit IC GPIO Daughter Card connects to the OM13320 Fm Development kit and permits easy evaluation of most of NXP s 1
11. ability in this respect Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities UM10752 All information provided in this document is subject to legal disclaimers OM13489 16 bit GPIO User Manual Evaluation products This product is provided on an as is and with all faults basis for evaluation purposes only NXP Semiconductors its affiliates and their suppliers expressly disclaim all warranties whether express implied or statutory including but not limited to the implied warranties of non infringement merchantability and fitness for a particular purpose The entire risk as to the quality or arising out of the use or performance of this product remains with customer In no event shall NXP Semiconductors its affiliates or their suppliers be liable to customer for any special indirect consequential punitive or incidental damages including without limitation damages for loss of business business interruption loss of use loss of data or information and the like arising out the use of or inability to use the product whether or not based on tort including negligence strict liability breach of contract breach of warranty or any other theory even if advised of the possibility of such damages Notwithstanding any damages that customer might incur for any reason whatsoever includ
12. and external voltage sources connected to TP1 and TP2 See the datasheet for more details on voltage level translation Note that the 10K pull up resistors SDA and SCL R5 and R6 are connected to VDDP which may cause incorrect current readings if two different supplies are used To configure the function pins apply jumpers between pins 2 amp 3 on JP9 J10 and JP11 to configure device pin 2 as a power supply device pin 3 as RST and device pin 1 as INT Then apply a jumper to JP1 to configure the desired address Logic high or logic low are labeled on the board Leave JP7 and JP8 open UM10752 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 2 0 09 January 2014 8 of 16 NXP Semiconductors U M1 0752 OM13489 16 bit GPIO User Manual TESTER GNOD 1349 7 e POND 1357 FM 00000 27 00000 1 2597 22 2 noooo unnpea 2 4 owe wOOAG 2 4 6 oo 104 aos 00 910 OF oo x 2 oo amp w o oo on _ 0413 loo 10 1 0 0129 on 10 420 oloaolaoxo RSTO 4210 2090200 Fig 8 Jumper Configuration for PCA L 6416 5 Connector Pinouts UM10752 5 1 5 2 CN1 GPIO Target Board Connector The OM13303 GPIO Target Board consists of eight LEDs and eig
13. chosen Additionally the PCA L 6416 device implements two power supplies which are separately chosen i e one can be 3 3V and the other 5V for voltage level translation evaluation Both of these power supplies can be supplied externally by using TP1 and TP2 near the tester connector CNA See the schematic section at the end of this document for more details The jumpers for power supply selection are CN3 JP3 and JP4 Reset Interrupt and Address pins selection The Reset Interrupt and Address pins are used in combinations on various devices The selection matrix on the 16 bit GPIO board sends pins 1 2 and 3 to determine if the pins are address or function on JP9 JP10 and JP11 Then if they are determined address pins JP1 JP7 and 8 tie them to logic high or low If they are determined to be function pins the other position of JP9 JP10 and JP11 tie them to the correct connector function pins See the schematic section at the end of this document for more details The logic high level for the address pins is VDDP Please note that a fix is needed for correct operation of the A0 jumper JP1 A wire must be soldered between pin 2 of JP1 and the via directly below to make connection to pin 21 on the device under test IC1 Use 30 AWG wire wrap wire for the easiest connection The solder mask on the board will prevent any short circuits Please note that A1 and A2 jumpers are incorrectly labeled JP7 and program 126 addresses wh
14. ckage user solderable Jumper configuration accommodates most NXP 16 bit GPIO Flexible power supply configuration 3 3V 5V or external supply Direct connection to OM13303 GPIO Target board for I O visualization Jumper configuration of device 2 address LED indicators for power and INT Scope ground connection loop 3 Pin Configuration of 16 bit GPIO Devices The different 16 bit GPIO devices pin configurations differ only slightly between devices See Fig 1 for a description of the different pinouts Fig 1 Pin Configuration 16 bit GPIO Devices PCA L 9535 55 PCA9671 PCA L 9535 55 PCA8575 PCA9675 PCF8575 PCA L 9539 PCA9673 PCA L 6416 PCA L 6416 PCA L 9539 PCA9673 PCA8575 PCA9675 PCF8575 PCA9671 2 RESET vcc P gt VCC I2C bus gt N RESET ADDR 0 Uu UU 0 N Uu o Uu 1 1 UU o gt gt 1 ey Uu nm A 5 v i Uu PO 7 Uu Dan VSS Uu UM10752 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 2 0 09 January 2014 4 of 16 NXP Semiconductors UM10752 3 1 3 2 OM13489 16 bit GPIO User Manual Power Supply Setup Power supply voltages may be selected from the tester connector CN4 or the Fm board CN5 If one selects Fm CN5 either 3 3V or 5V can be
15. en selected The labels show that A1 and A2 pins will be connected to ground when the jumper shorts pin 1 and 2 toward the bottom edge of the board In fact this is a connection to or high The schematic is correct only the labels are incorrect TESTER 135 27 e GNOD 135 2 FM woo mnoooo oo unnpea 2 44 oo oo LI ilo 19 INT o R ST o 0 9 on amp i o 42 0 RIN2 o Glolaodnoxo 2270 aig 929 Fig 2 Fix needed for correct operation of 0 jumper JP1 4 Board Jumper Set Up UM10752 4 1 Power Supply Jumpers The power supply selections for the OM13489 is very flexible and allows for detailed analysis and evaluation of all the NXP 16 bit GPIO devices JP3 labeled PWR selects between 5V supplied from the tester connector CN4 jumper between pin 2 and 3 labeled TSTR and the Fm board connector CN5 jumper between pin 1 and 2 If 3 3V or external power operation is desired no jumper is required All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 2 0 09 January 2014 5 of 16 NXP Semiconductors UM10752 UM10752 4 2 4 3 OM13489 16 bit GPIO User Manual CN3 selects between 5V and 3 3V for a second power supply needed for PCA L 6408A If the device
16. ht switches and connects directly to the 16 bit GPIO board through CN1 The switches and LEDs permit easy exercise of the I O functionality of the device under test The LEDs light red when the voltage on that channel is below VCC x 0 3V and lights green when the voltage is above VCC x 0 7V The LEDs remain off when the voltage is between those two levels Table 2 1 GPIO Target Board Connector Pinout CN1 Pin Number Function Board Connection 1 VDD VDDP 2 Ground GND 3 100 U1 pin 4 4 101 U1 5 5 102 U1 pin 6 6 103 U1 pin 7 7 104 U1 pin 9 8 105 U1 10 9 106 U1 pin 11 10 107 U1 12 CN5 Fm Development Board Connector The OM13489 can connect directly to the OM13320 Fm Development kit via CN5 This connector provides power ge signals and other ancillary signals Note The connector on the Fm board is a male shrouded 14 pin type while the connector on the GPIO board is female 18 pin The reason lies with the shroud around the 14 pin connector To ensure correct mating of the female with the male two pin positions on both of the female sides are unused All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 2 0 09 January 2014 9 of 16 NXP Semiconductors UM10752 UM10752 OM13489 16 bit GPIO User Manual Board Connection No connect No connect SCL Bus 1 to U1 pin 14 SDA Bus 2 not used Interrupt to I
17. ing without limitation all damages referenced above and all direct or general damages the entire liability of NXP Semiconductors its affiliates and their suppliers and customer s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars US 5 00 The foregoing limitations exclusions and disclaimers shall apply to the maximum extent permitted by applicable law even if any remedy fails of its essential purpose NXP B V 2014 All rights reserved User manual Rev 2 0 09 January 2014 13 of 16 NXP Semiconductors U M1 0752 OM13489 16 bit GPIO User Manual 7T List of figures Fig 1 Pin Configuration 16 bit GPIO Devices 4 Fig 2 Fix needed for correct operation of AO jumper JP1 E A 5 Fig 3 Power Jumpers and External Power Test Points6 Fig 4 SDA and SCL 6 Fig 5 Jumper Configuration for PCA8575 PCA9535A PCA9535C PCA9535 PCA9555A PCA9555 PCA9675 PCAL9535A PCAL9555A PCF85757 Fig 6 Jumper Configuration for PCA9671 7 Fig 7 Jumper Configuration for PCA9673 PCAL9539A PCA9539A PCA9539R 9539 8 Fig 8 Jumper Configuration for PCA L 6416 9 UM10752 All information provided in this document is subject to legal di
18. is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any li
19. r consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use
20. r supply setup but normally only JP4 with a jumper between pins 2 amp 3 need be applied to power the device at 3 3V To configure the function pins apply jumpers between pins 2 amp 3 on JP9 and JP11 to configure device pin 3 as RST and device pin 1 as INT Apply a jumper between pins 1 amp 2 on JP10 to configure device pin 2 as an address Then apply jumpers to JP1 and JP7 to configure the desired lC address Logic high or logic low are labeled on the board Leave JP8 open The labels are incorrect for JP7 and JP8 Using the labels a 0 is actually a 1 and a labeled 1 is actually a 0 The schematic is correct and note the square solder pad is pin 1 TESTER qua 1387 e AND 1 35 27 FM 00000 00000 1 2567 noooo d noooo 2 4 owe 2 2 4 be 101 2g de oo Ala 64 oo e e sajojt 97 ell H 4004 on zi loo 7 4001 o _ 929 on di Glolsiolaiolsio Fig 7 Jumper Configuration for PCA9673 9539 PCA9539A PCA9539R PCA9539 4 6 PCAL6416A PCA6416A The PCA L 6416A devices are level translating Agile 1 0 Expanders with two power supplies one address pin RST and INT The two power supplies may operate at different voltages to translate from the I C bus voltage domain to a higher or lower I O voltage CN3 and JP4 may be set to the same or different voltages or left open
21. sclaimers NXP B V 2014 All rights reserved User manual Rev 2 0 09 January 2014 14 of 16 NXP Semiconductors U M1 0752 OM13489 16 bit GPIO User Manual 8 List of tables Table 1 Devices Supported by OM13489 16 bit GPIO Daughter 3 Table 2 1 GPIO Target Board Connector Pinout 9 Table 3 5 Fm Board Connector 10 Table 4 CN4 Tester 10 UM10752 All information provided in this document is subject to legal disclaimers NXP B V 2014 All rights reserved User manual Rev 2 0 09 January 2014 15 of 16 NXP Semiconductors UM10752 OM13489 16 bit GPIO User Manual 9 Contents 1 IntrodUction iere ee 3 2 Features of the OM13489 16 bit GPIO Daughter 4 3 Pin Configuration of 16 bit GPIO Devices 4 3 1 Power Supply 5 3 2 Reset Interrupt and Address pins selection 5 4 Board Jumper Set 5 4 1 Power Supply Jumpers 5 4 2 SCL and SDA 6 4 3 PCA8575 PCA9535A PCA9535C PCA9535 PCA9555A PCA9555 PCA9675 PCAL9535A PCAL9555A PCF8575 6 4 4
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