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1. 423 Behavioral Verilog Modules sess eee e e nennen enn nenne enne nenne ener enne 423 Behavioral Verilog Module Declarattions eem en e e e eren ens 424 Behavioral Verilog Continuous Assiemments e ee e e e ener eres 424 Behavioral Verilog Procedural Assignments ssssssssee eene eene eH eene 425 Behavioral Verilog Combinatorial Always Blocks eee ee ee eeeeeeeneeeeerereeererereee eee 425 Behavioral Verilog If Else Statement ps cossus mesire en ern n ee eI eene 425 Behavioral Verilog Case Statements cccccccccceeesneseeeeeeeeenennse cece cece ene eH eene nennen 426 Behavioral Verilog For and Repeat LoOpsiscicescccscsiscccasssiccesasssssvssassssseasssssevesssasseveseseseuseessbavsecnsaens 426 Behavioral Verilog While LOOpS ws eiecti eerie nni e eoe ie eae E EEN EENS Eed 427 Behavioral Verilog Sequential Always Blocks sssseseessee e 428 Behavioral Verilog Assign and Deassign Statements ee 429 Behavioral Verilog Assign Deassign Statement Performed in Same Always Block 430 Cannot Assign Bit Part Select of Signal Through Assign Deassign Statement ss nssssssese1ee 1e 430 Behavioral Verilog Assignment Extension Past 32 Bits sssssssssss ed 431 Behavioral Verilog Tasks and Functions sssesssssseeee eH eee 431 Behavioral Verilog Recursive Tasks and Puncthons e 432 Behavioral Verilog Constant Functions
2. XST User Guide 366 www xilinx com UG627 v 11 3 September 16 2009 hipter XST VHDL Language Support XILINX Use any of the read functions shown in the following table These read functions are supported by the following packages e standard e std textio e ieee std_logic_textio file type text only standard access type line only standard file_open file name open_kind standard file_close file standard endfile file standard text std textio line std textio width std textio readline text line std textio readline line bit boolean std textio read line bit std textio readline line bit_vector boolean std textio read line bit_vector std textio read line boolean boolean std textio read line boolean std textio read line character boolean std textio read line character std textio read line string boolean std textio read line string std textio write file line std textio write line bit boolean std textio write line bit std textio write line bit_vector boolean std textio write line bit_vector std textio write line boolean boolean std textio write line boolean std textio write line character boolean std textio write line character std textio write line integer boolean std textio write line integer std textio write line string boolean std textio write line string std textio read line std_ulogic boolean ieee std_logic_textio
3. always we or di begin if we 1 dil di 2 DI WIDTH 1 1 DI WIDTH else begin dil RAM addr 2 DI WIDTH 1 1 DI WIDTH dol RAM addr 2 DI WIDTH 1 1 DI WIDTH end if we 0 diO lt di DI WIDTH 1 0 else begin di0 lt RAM addr DI_WIDTH 1 0 do0 lt RAM addr DI_WIDTH 1 0 end end always posedge clk begin RAM addr lt dil di0 do lt dol do0 end endmodule XST can identify RAM descriptions with two or more read ports that access the RAM contents at addresses different from the write address However there can only be one write port XST implements the following descriptions by replicating the RAM contents for each output port as shown in the following figure Multiple Port RAM Descriptions Diagram D pI WE WE wa JA wa a DO1 DO2 RA1 DPRA RA2 DPRA cLK gt cLK gt X8983 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 163 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Multiple Port RAM Descriptions Pin Descriptions ppm Beseription S clk Positive Edge Clock wi Synchronous Write Enable Active High wW Write Address Read Address of the First RAM Read Address of the Second RAM Data Input First RAM Output Port Second RAM Output Port Multiple Port RAM Descriptions VHDL Coding Example Multiple Port RAM Descriptions library ieee use ieee std_logic_1164 all us
4. cee ccc cece e caer ees eee Hee e hene ee ESS 285 FSM EXTRACT Automatic FSM Extraction Architecture Support sss 286 FSM EXTRACT Automatic FSM Extraction Applicable Elements 286 FSM EXTRACT Automatic FSM Extraction Propagation Rules ssssseeeeee 286 ENUM ENCODING Enumerated Encoding e eene 286 ENUM_ENCODING Enumerated Encoding Architecture Support sse 287 ENUM_ENCODING Enumerated Encoding Applicable Elements 287 ENUM_ENCODING Enumerated Encoding Propagation Rules sesssseeee 287 EQUIVALENT REGISTER REMOVAL Equivalent Register Removal eee 287 EQUIVALENT REGISTER REMOVAL Equivalent Register Removal Architecture DUP POLE eege 288 EQUIVALENT_REGISTER_REMOVAL Equivalent Register Removal Applicable E EE 288 EQUIVALENT_REGISTER_REMOVAL Equivalent Register Removal Propagation IRT VE ENADE I EET T E E eege 288 FSM_ENCODING FSM Encoding Aleoritbum ccc cee eee 289 FSM_ENCODING FSM Encoding Algorithm Architecture Support 289 FSM_ENCODING FSM Encoding Algorithm Applicable Hlements eese 289 FSM_ENCODING FSM Encoding Algorithm Propagation Rules sssseeeeeee 289 MUX EXTRACT Mux Extract On ciisciussiccdescsstcvennisstcvesnasaecctseanc cotaaed Coabddsaecdeeuesdeceendesecetuvlssaceeens 290 MUX EXTRACT Mux Extraction Architecture Support cece cere ee eererererererreee es 290 MUX EXTRACT Mux Extracti
5. e WARNING Xst 1426 The value init of the FF Latch reg hinders the constant cleaning in the block block You could achieve better results by setting this init to value Macros in XST Log Files XST log files contain detailed information about the set of macros and associated signals inferred by XST from the VHDL or Verilog source on a block by block basis Macro inference is done in two steps 1 HDL Synthesis XST recognizes as many simple macro blocks as possible such as adders subtractors and registers 2 Advanced HDL Synthesis XST does additional macro processing by improving the macros for example pipelining of multipliers recognized at the HDL synthesis step or by creating the new more complex ones such as dynamic shift registers The Macro Recognition report at the Advanced HDL Synthesis step is formatted the same as the corresponding report at the HDL Synthesis step XST gives overall statistics of recognized macros twice e After the HDL Synthesis step e After the Advanced HDL Synthesis step XST no longer lists statistics of preserved macros in the final report XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 451 XILINX Chapter 11 XST Log File XST Log File Examples This section gives the following XST log file examples e Recognized Macros XST Log File Example e Additional Macro Processing XST Log File Example e XST FPGA Log File Example e XST CPLD Log File Example
6. ssssssseeee HH enne 350 wysiwyg WYSIWYG Applicable Elements sess 350 wysiwyg WYSIWYG Propagation Rules eH eee 350 wysiwyg WYSIWYG Syntax Examples sssseeee eene 350 Pld XP XOR Preserve irissen aE rE EEEE E N EE TNE ee UT IURE ee SER lots 350 XST Timing Constraints sees tssetresie presiese enis nea akna EEn ana sevnbeansacaeactiedeconaanietennadaceces 351 Applying iming EEN 351 Applying Timing Constraints Using Global Optimization Goal 352 Applying Timing Constraints Using the User Constraints File UCF sese 352 Writing Constraints to the NGC File sssssssseeeeee HI een eH e nennen nnns 352 Additional Options Affecting Timing Constraint Drocesetmg e 352 cross clock analysis Cross Clock Analysis sss 352 write timing constraints Write Timing Constratmte Hee 353 write timing constraints Write Timing Constraints Architecture Gupport 353 write timing constraints Write Timing Constraints Applicable Elements 353 write timing constraints Write Timing Constraints Propagation Rules ssesssssssssesetes1e 353 write timing constraints Write Timing Constraints Syntax Examples sess 353 CLOCK SIGNAL Glock Signal soarece een orante kennen pee pue event ek race salta ene uii e uS UR Ve naue 353 CLOCK SIGNAL Clock Signal Architecture Support 353 CLOCK SIGNAL Clock Signal Applicable Elements sss 3
7. Data Output 4 Bit Signed Up Counter With Asynchronous Reset and Modulo Maximum VHDL Coding Example 4 bit Signed Up Counter with Asynchronous Reset and Modulo Maximum library ieee use ieee std logic 1164 al1 use ieee std logic arith all entity counters 8 is generic MAX integer 16 port C CLR in std logic Q out integer range 0 to MAX 1 end counters 8 architecture archi of counters 8 is signal cnt integer range 0 to MAX 1 begin process C CLR begin if CLR 1 then cnt lt 0 elsif rising edge C then cnt lt cnt 1 mod MAX end if end process Q lt cnt end archi XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 47 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques 4 Bit Signed Up Counter With Asynchronous Reset and Modulo Maximum Verilog Coding Example 4 bit Signed Up Counter with Asynchronous Reset and Modulo Maximum module v_counters_8 C CLR Q parameter MAX SQRT 4 MAX MAX SORT MAX SQRT input C CLR output MAX SQRT 1 0 Q reg MAX SQRT 1 0 cnt always 8 posedge C or posedge CLR begin if CLR cnt lt 0 else cnt lt cnt 1 MAX end assign Q cnt endmodule Accumulators Hardware Description Language HDL Coding Techniques An accumulator differs from a counter in the nature of the operands of the add and subtract operation In a counter the destination and
8. States 6 Transitions 15 Inputs 2 Outputs 2 Clock CLK rising_edge Reset RESET positive Reset type asynchronous Reset State 000001 Encoding automatic Implementation automatic Found 1 bit register for signal lt CLKEN gt Found 1 bit register for signal lt RST gt Summary inferred 1 Finite State Machine s inferred 2 D type flip flop s Unit lt statmach gt synthesized Synthesizing Unit lt tenths gt Related source file is tenths v Found 4 bit up counter for signal lt Q gt Summary inferred 1 Counter s Unit lt tenths gt synthesized Synthesizing Unit lt decode gt Related source file is decode v Found 16x10 bit ROM for signal lt ONE_HOT gt XST User Guide 468 www xilinx com UG627 v 11 3 September 16 2009 Chapter ti XST Log File XILINX Summary inferred 1 ROM s Unit decode synthesized Synthesizing Unit lt hex2led gt Related source file is hex2led v Found 16x7 bit ROM for signal LED Summary inferred 1 ROM s Unit lt hex2led gt synthesized Synthesizing Unit lt smallcntr gt Related source file is smallcntr v Found 4 bit up counter for signal lt QOUT gt Summary inferred 1 Counter s Unit lt smallcntr gt synthesized Synthesizing Unit lt cnt60 gt Related source file is cnt60 v Unit lt cnt60 gt synthesized Synthesizing Unit lt stopwatch gt Related so
9. The example uses a Verilog design called watchver These files are found in the ISEexamples watchver directory of the ISE Design Suite installation directory e stopwatch v e statmach v e decode v e cnt60 v smallcntr v e tenths v e hex2led v This design contains seven modules e stopwatch e statmach e tenths a CORE Generator software core e decode e cnt60 e smallcntr e beiled For the example 1 Create a new directory named vlg_m 2 Copy the watchver design files from the ISEexamples watchver directory of the ISE Design Suite installation directory to the newly created v1g_m directory Specify the top level design block with the top command line option To synthesize the design which is now represented by seven Verilog files create a project XST now supports mixed VHDL and Verilog projects Therefore Xilinx recommends that you use the new project format whether it is a real mixed language project or not In this example we use the new project format To create a project file containing only Verilog files place a list of Verilog files preceded by the keyword verilog in a separate file The order of the files is not important XST can recognize the hierarchy and compile Verilog files in the correct order For our example 1 Open a new file called watchver v 2 Enter the names of the Verilog files into this file in any order and save it verilog work decode v verilog work statmach v v
10. case addr endcase end for a ROM with registered output data lt 20 h0200A lt 20 h00300 lt 20 h08101 lt 20 h04000 lt 20 h08601 lt 20 h0233A lt 20 h00300 lt 20 h08602 lt 20 h02310 lt 20 h0203B lt 20 h08300 lt 20 h04002 lt 20 h08201 lt 20 h00500 lt 20 h04001 lt 20 h02500 lt 20 h00340 lt 20 h00241 lt 20 h04002 lt 20 h08300 lt 20 h08201 lt 20 h00500 lt 20 h08101 lt 20 h00602 lt 20 h04003 lt 20 h0241E lt 20 h00301 lt 20 h00102 lt 20 h02122 lt 20 h02021 lt 20 h00301 lt 20 h00102 lock RAM Resources b clk en addr clk en 5 0 addr 19 0 data 19 0 rdata begin 6 5000000 rdata 6 500000 rdata 6 5000010 rdata 6 b000011 rdata 6 5000100 rdata 6 b000101 rdata 6 5000110 rdata 6 b000111 rdata 6 5001000 rdata 6 b001001 rdata 6 5001010 rdata 6 b001011 rdata 6 b001100 rdata 6 b001101 rdata 6 5001110 rdata 6 b001111 rdata 6 5010000 rdata 6 5010001 rdata 6 5010010 rdata 6 5010011 rdata 6 b010100 rdata 6 b010101 rdata 6 5010110 rdata 6 b010111 rdata 6 b011000 rdata 6 5011001 rdata 6 5011010 rdata 6 b011011 rdata 6 b011100 rdata 6 b011101 rdata 6 5011110 rdata 6 b011111 rdata always posedge clk begin if en dat end endmodule ROM With Registered Address Diagram a lt rdata temp
11. Block RAM with Optional Output Registers module v rams 19 clkl clk2 we enl en2 addrl addr2 di resl res2 input elkl input clk2 input we enl en2 input 5 0 addrl input 5 0 addr2 input 5 0 di output 5 0 resl output 5 0 res2 reg 5 0 resl reg 5 0 res2 reg 5 0 RAM 63 0 reg 5 0 dol reg 520 do2 always posedge clk1 begin if we 1 b1 RAM addr1 lt di dol lt RAM addrl end always posedge clk2 begin do2 lt RAM addr2 end always posedge clk1 begin if enl 1 b1 resl dol end always posedge clk2 begin if en2 1 b1 res2 do2 end endmodule Initializing RAM Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip Block and distributed RAM initial contents can be specified by initialization of the signal describing the memory array in your HDL code Do this directly in your HDL code or specify a file containing the initialization data See e Initializing RAM Directly in Hardware Description Language HDL Code e Initializing RAM From an External File XST supports RAM initialization in both VHDL and Verilog Initializing RAM Directly in Hardware Description Language HDL Code The following coding examples show how to initialize RAM directly in Hardware Description Language HDL code For further information see Initia
12. ENUM ENCODING Enumerated Encoding VHDL Syntax Example Specify as a VHDL constraint on the considered enumerated type architecture behavior of example is type statetype is STO ST1 ST2 ST3 attribute enum encoding of statetype type is 001 010 100 111 Signal statel statetype signal state2 statetype begin ENUM ENCODING Enumerated Encoding XST Constraint File XCF Syntax Example BEGIN MODEL entity name NET signal name enum encoding 2 string END EQUIVALENT REGISTER REMOVAL Equivalent Register Removal EQUIVALENT REGISTER REMOVAL Equivalent Register Removal enables or disables removal of equivalent registers described at the RTL Level By default XST does not remove equivalent flip flops if they are instantiated from a Xilinx primitive library Flip flop optimization includes removing e Equivalent flip flops for FPGA and CPLD devices e Flip flops with constant inputs for CPLD devices This processing increases the fitting success as a result of the logic simplification implied by the flip flops elimination Equivalent Register Removal values are e yes default Flip flop optimization is allowed no Flip flop optimization is inhibited The flip flop optimization algorithm is time consuming For fast processing use no e true XCF only e false XCF only XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 287 XILINX nuit t XST Design Constraints EQUIVALENT REGIS
13. XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 387 XILINX Chapter 7 XST VHDL Language Support For Loop Statement VHDL Coding Example library IEEE use IEEE std_logic_1164 all use IEEE std logic unsigned all entity countzeros is port a in std logic vector 7 downto 0 Count out std logic vector 2 downto 0 end mux4 architecture behavior of mux4 is signal Count Aux std logic vector 2 downto 0 begin process a begin Count Aux 000 for i in a range loop if a i 0 then Count Aux lt Count Aux 1 operator defined in std logic unsigned end if end loop Count lt Count Aux end process end behavior VHDL Sequential Circuits Sequential circuits can be described using sequential processes XST allows e VHDL Sequential Process With a Sensitivity List e VHDL Sequential Process Without a Sensitivity List VHDL Sequential Process With a Sensitivity List A process is sequential when it is not a combinatorial process In other words a process is sequential when some assigned signals are not explicitly assigned in all paths of the statements In this case the hardware generated has an internal state or memory flip flops or latches The Sequential Process With Asynchronous Synchronous Parts VHDL Coding Example provides a template for describing sequential circuits For more information see XST Hardware Description Language HDL Coding Techni
14. if oper loadl1 1 b1 acc res0 else acc 0 if oper addsubl 1 b1 res0 lt acc pl else res0 lt acctpl end assign RES res0 endmodule Pipelined Multipliers Hardware Description Language HDL Coding Techniques In order to increase the speed of designs with large multipliers XST can infer pipelined multipliers By interspersing registers between the stages of large multipliers pipelining can significantly increase the overall frequency of your design The effect of pipelining is similar to Flip Flop Retiming To insert pipeline stages 1 Describe the necessary registers in your HDL code 2 Place them after any multipliers 3 Set the Multiplier Style MULT STYLE constraint to pipe_lut XST User Guide 104 www xilinx com UG627 v 11 3 September 16 2009 nuit XST Hardware Description Language HDL Coding Techniques XILINX If the target is a Virtex 4 device or a Virtex 5 device and implementation of a multiplier requires multiple DSP48 blocks XST can pipeline this implementation as well Set Multiplier Style MULT_STYLE for this instance to pipe_block In order to reach the maximum multiplier speed XST uses the maximum number of available registers when e XST detects valid registers for pipelining and e Multiplier Style MULT STYLE is set to pipe_lut or pipe_block In order to obtain the best frequency XST automatically calculates the maximum number of registers for each multiplier
15. 248 Setting Xilinx Specific Options for FPGA Devices eme 248 Setting Xilinx Specific Options for CPLD Dewvices ee 248 Setting Other XST Command Line Optioris eerie nannten ba ieu ts sae u n ense sie nnus da REESEN 249 Custom Compile File List Ier etre n rather pe te dag sau SOARES Costs 249 VADE A tribute cm 249 MIDI Ub dii cT 250 Verilog 2001 Attributes Syntax ires cente niei denne i eee ead Le e sends ER HE IR ER ES EA ERES Cea VERRE 250 KU NEE 251 Verilog 2001 Meta Comments isi ccsscscsiccccnaasiccccanssies Ike FCIRE e EE ERE HE E IRE e SERERE EINE ERR SER e EE RES ES S EEEE 251 REENEN 251 XST Constraint File XCF Syntax and Utilization 0 0 cece eee eee 251 Native and Non Native User Constraint File UCF Constraints Syntax sse 252 Native User Constraints File UCF Constraimnts 0c cceeceece cece cee ee cea e eee e emen 252 Non Native User Constraints File UCF Constraints sseseeeee HH 252 XST Constraint File XCF Syntax Limitations 0 00 0 tin eene nennen 253 Constraints PrOrity ooo e nh e EES E FH ORAE Y Handed ase 253 XST Specific Non Timing Options eee eerte rre te eene ao aeree ea o e E SAANEESEEN ENESE sone 253 AST Command Line Only OpHODS e desseee eet rseten ebbe poire e entes LIRE NERA ARENA ESEE eU IURE S e EENS eE E 259 XST mine Opi Ons E 263 XST Timing Options Process gt Properties or Command Lime 26
16. During the Advanced HDL Synthesis step the XST HDL Advisor advises you to specify the optimum number of register stages if e You have not specified sufficient register stages and e Multiplier Style MULT STYLE is coded directly on a signal XST implements the unused stages as shift registers if e The number of registers placed after the multiplier exceeds the maximum required and e Shift register extraction is activated XST has the following limitations e XST cannot pipeline hardware Multipliers implementation using MULT18X18S resource e XST cannot pipeline Multipliers if registers contain asynch set reset or synch reset signals XST can pipeline if registers contain synch reset signals XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 105 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Pipelined Multipliers Log File Following is a Pipelined Multipliers log file Synthesizing Unit lt multipliers_2 gt Related source file is multipliers_2 vhd Found 36 bit register for signal lt MULT gt Found 18 bit register for signal lt a_in gt Found 18 bit register for signal lt b_in gt Found 18x18 bit multiplier for signal mult res Found 36 bit register for signal pipe 1 Found 36 bit register for signal pipe 2 Found 36 bit register for signal pipe 3 Summary inferred 180 D type flip flop s inferred 1 Multiplier s Unit multipliers 2 synthe
17. PRIORITY EXTRACT Priority Encoder Extraction ISE Design Suite Syntax Example Define this constraint globally in ISE Design Suite in Process Properties HDL Options Priority Encoder Extraction RAM EXTRACT RAM Extraction RAM EXTRACT RAM Extraction enables or disables RAM macro inference RAM EXTRACT values are e yes default no e true XCF only e false XCF only RAM EXTRACT RAM Extraction Architecture Support Applies to all FPGA devices Does not apply to CPLD devices RAM EXTRACT RAM Extraction Applicable Elements Applies to the entire design or to an entity component module or signal RAM EXTRACT Propagation Rules Applies to the entity component module or signal to which it is attached RAM EXTRACT RAM Extraction Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it RAM EXTRACT RAM Extraction VHDL Syntax Example Declare as follows attribute ram extract string Specify as follows attribute ram extract of signal name entity name signal entity is yes no XST User Guide 322 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST Design Constraints XILINX RAM_EXTRACT RAM Extraction Verilog Syntax Example Place immediately before the module declaration or instantiation ram extract yes noJ zi RAM EXTRA
18. This process can dramatically increase input to clock and clock to output timing which is not desirable To prevent this you may use OFFSET_IN_BEFORE and OFFSET_IN_AFTER constraints If The design does not have a strong requirements or e You want to see the first results without touching the first and last flip flop stages You can use two additional constraints e MOVE FIRST STAGE MOVE LAST STAGE Both constraints may have either of two values yes or no e MOVE FIRST STAGE no Prevents the first flip flop stage from moving e MOVE LAST STAGE no Prevents the last flip flop stage from moving Several constraints influence register balancing For more information see Register Balancing REGISTER BALANCING XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 313 XILINX nuit t XST Design Constraints MOVE_FIRST_STAGE Move First Stage Architecture Support Applies to all FPGA devices Does not apply to CPLD devices MOVE_FIRST_STAGE Move First Stage Applicable Elements MOVE_FIRST_STAGE Move First Stage applies to the following only e Entire design e Single modules or entities e Primary clock signal MOVE_FIRST_STAGE Move First Stage Propagation Rules For Move First Stage propagation rules see the figure above MOVE_FIRST_STAGE Move First Stage Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you ca
19. XILINX Chapter i XST Hardware Description Language HDL Coding Techniques In the Tristates Coding Examples comparing to 0 instead of 1 infers a BUFT primitive instead of a BUFE macro The BUFE macro has an inverter on the E pin Tristates Log File The XST log file reports the type and size of recognized tristates during the Macro Recognition step Synthesizing Unit lt three_st gt Related source file is tristates l vhd Found 1 bit tristate buffer for signal o Summary inferred 1 Tristate s Unit lt three_st gt synthesized HDL Synthesis Report Macro Statistics Tristates rd l bit tristate buffer 1 Tristates Related Constraints Convert Tristates to Logic TRISTATE2LOGIC Tristates Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip Tristate Description Using Combinatorial Process and Always Block Diagram BUFT Tristate Description Using Combinatorial Process and Always Block Pin Descriptions Output Enable active Low XST User Guide 34 www xilinx com UG627 v 11 3 September 16 2009 hapter 1 XST Hardware Description Language HDL Coding Techniques XILINX Tristate Description Using Combinatorial Process VHDL Coding Example Tristate Description Using Combinatorial Process library ieee use ieee std_logic_1164 all entity three st 1 is port T in std logic L s i
20. ee 306 POWER Power Reduction Applicable Hlemente en 306 POWER Power Reduction Propagation Rules cece eee rece eeeeeeserererereeereeeees 306 READ CORES Read COLES 2 roster Pert npe te peret eee iE ENEN ET VEEE AEREE EKDE EEEE EEE 307 READ CORES Read Cores Architecture Support ssssssssssseeee nt 307 READ CORES Read Cores Applicable Elements 307 READ CORES Read Cores Propagation Rules ssseessssesee em 308 SHIFT EXTRACT Logical Shifter Extraction seeseeeeee eene 308 SHIFT EXTRACT Logical Shifter Extraction Architecture Support sssssssssesss 309 SHIFT EXTRACT Logical Shifter Extraction Applicable Elements 309 SHIFT EXTRACT Logical Shifter Extraction Propagation Rule 309 LC UT Gronovii M 309 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 9 XILINX LC LUT Combining Architecture Support seeesss eee eene 310 LC LUT Combining Applicable Blements e 310 LC LUT Combining Propagation Rules eee 310 BRAM MAP Map Logic on BRAM eese terr bananas seres esa bove a os ba ead ees sae e ovens sen aUe nues Eae enu REKER 310 BRAM MAP Map Logic on BRAM Architecture Gupport e 310 BRAM MAP Map Logic on BRAM Applicable Elements sss 310 BRAM MAP Map Logic on BRAM Propagation Rule 311 MAX FANOUT Max Fanout e eeeeeeeeeeeeeeeeeeee eene ENNEN hene eene i ubres VE
21. enw oo s T mmayowpamn m E XST User Guide 152 www xilinx com UG627 v 11 3 September 16 2009 lhapter 3 XST Hardware Description Language HDL Coding Techniques XILINX Dual Port Block RAM With Two Write Ports VHDL Coding Example This is the most general example It has different clocks enables and write enables Dual Port Block RAM with Two Write Ports library IEEE use IEEE std logic 1164 a1l1 use IEEE std logic unsigned all entity rams 16 is port clka in std logic clkb in std logic ena in std logic enb in std logic wea in std logic web in std logic addra in std logic vector 5 downto 0 addrb in std logic vector 5 downto 0 dia in std logic vector 15 downto 0 dib in std logic vector 15 downto 0 doa out std logic vector 15 downto 0 dob out std logic vector 15 downto 0 end rams 16 architecture syn of rams 16 is type ram type is array 63 downto 0 of std logic vector 15 downto 0 shared variable RAM ram type begin process CLKA begin if CLKA event and CLKA 1 then if ENA 1 then if WEA 1 then RAM conv integer ADDRA DIA end if DOA lt RAM conv integer ADDRA end if end if end process process CLKB begin if CLKB event and CLKB 1 then if ENB 1 then if WEB 1 then RAM conv integer ADDRB DIB end if DOB RAM conv integer ADDRB end if end if end process end syn Becau
22. process clk variable txtline LINE begin write txtline string ny writeline results txtline write txtline string Base Const write txtline base const writeline results txtline write txtline string New Const write txtline new const writeline results txtline write txtline string nyys writeline results txtline if clk event and clk 1 then if sel 1 then dout new const else dout lt din end if end if end process end Behavioral XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 369 XILINX Chapter 1 XST VHDL Language Support Rules for Debugging Using Write Operation in VHDL Follow these rules for rules for debugging using write operation in VHDL e During a std logic read operation the only allowed characters are 0 and 1 Other values such as X and Z are not allowed XST rejects the design if the file includes characters other than 0 and 1 except that XST ignores a blank space character e Do not use identical names for files placed in different directories e Do not use conditional calls to read procedures as shown in the following coding example if SEL 1 then read MY LINE A 3 downto 0 else read MY LINE A 1 downto 0 end if e When using the endfile function if you use the following description style while not endfile MY FILE l
23. signal RAM ram type signal di0 dil std logic vector DI WIDTH 1 downto 0 signal do0 dol std logic vector DI WIDTH 1 downto 0 begin process we di begin if we 1 1 then dil lt di 2 DI WIDTH 1 downto 1 DI WIDTH else dil lt RAM conv integer addr 2 DI WIDTH 1 downto 1 DI WIDTH dol lt RAM conv integer addr 2 DI WIDTH 1 downto 1 DI WIDTH end if if we 0 1 then di0 lt di DI_WIDTH 1 downto 0 else di0 lt RAM conv_integer addr DI WIDTH 1 downto 0 do0 lt RAM conv_integer addr DI WIDTH 1 downto 0 end if end process process clk begin if clk event and clk 1 then RAM conv_integer addr lt dil amp di0 do lt dol amp do0 end if end process end syn XST User Guide 162 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX No Change Mode Single Port BRAM with Byte Wide Write Enable 2 Bytes in Verilog Coding Example Single Port BRAM with Byte wide Write Enable 2 bytes in No Change Mode module v_rams_26 clk we addr di do parameter SIZE 512 parameter ADDR_WIDTH 9 parameter DI_WIDTH 8 input clk input 1 0 we input ADDR WIDTH 1 0 addr input 2 DI WIDTH 1 0 di output 2 DI WIDTH 1 0 do reg 2 DI WIDTH 1 0 RAM SIZE 1 0 reg 2 DI WIDTH 1 0 do reg DI WIDTH 1 0 dio dil reg DI WIDTH 1 0 do0 dol
24. signal di0 dil std logic vector DI WIDTH 1 downto 0 begin process we di begin if we 1 1 then dil lt di 2 DI WIDTH 1 downto 1 DI WIDTH else dil lt RAM conv integer addr 2 DI WIDTH 1 downto 1 DI WIDTH end if if we 0 1 then di0 lt di DI_WIDTH 1 downto 0 else di0 lt RAM conv_integer addr DI WIDTH 1 downto 0 end if end process process clk begin if clk event and clk 1 then RAM conv_integer addr lt dil amp di0 do lt RAM conv_integer addr end if end process end syn XST User Guide 158 www xilinx com UG627 v 11 3 September 16 2009 nuit XST Hardware Description Language HDL Coding Techniques XILINX Read First Mode Gingle Port BRAM With Byte wide Write Enable 2 Bytes Verilog Coding Example 7 Single Port BRAM with Byte wide Write Enable 2 bytes in Read First Mode module v_rams_24 clk we addr di do parameter SIZE parameter ADDR_WIDTH parameter DI_WIDTH 512 9 8 uo wd og input clk input 1 0 we input ADDR WIDTH 1 0 addr input 2 DI WIDTH 1 0 di output 2 DI WIDTH 1 0 do reg 2 DI WIDTH 1 0 RAM SIZE 1 0 reg 2 DI_WIDTH 1 0 do reg DI WIDTH 1 0 dio dil always Q8 we or di begin if we 1 dil di 2 DI WIDTH 1 1 DI WIDTH else dil RAM addr 2 DI WIDTH 1 1 DI WIDTH if we 0 di0 di DI WIDTH 1 0 else di0 RAM addr DI_WIDTH 1 0 end al
25. sseseseseesssee e eee nennen ener 432 Behavioral Verilog Blocking Versus Non Blocking Procedural Aosaienmente ee 433 Behavioral en EE 434 Behavioral sls M 434 Behavioral Verilog Include Files mes m eee eene nene enne enne 434 Behavioral Verilog C mmmerge 435 XST User Guide 14 www xilinx com UG627 v 11 3 September 16 2009 XILINX Behavioral Verilog Generate Statements sse eee ee n eene nennen e ener en nnns 435 Behavioral Verilog Generate For Dtatements eee 436 Behavioral Verilog Generate If else Statements ssssssssse eene 436 Behavioral Verilog Generate Case Dtatemente eene 436 Chapter 10 XST Mixed Language Support ies cerni eniti eee eere enar anao eR IE e RR E EYE REESE REN EASEUS Ee REP cocesends 439 Mixed Language Project Files 1 esee eere rte ent enn nto sea enne NEE EA ener ena oo sonat einen 439 VHDL and Verilog Boundary Rules in Mixed Language Projects s sssssesetssrsrsrttstssrrerrtnntrrrrereren ene 440 Instantiating a Verilog Module in a VHDL Desten cece cece Hee 440 Instantiating a VHDL Design Unit in a Verilog Design 440 Port Mapping in Mixed Language Projects cc cece ee eee errr ee esas nes e e e eren 441 VIDE mm Verilog Port Mapping nter nte ntt teh sancsssnssabevesssss guesses E ES EE UNER EEES EERE EA 441 Verilog im VHDLE Port Map pin EE 441 VHDL in Mixed Language Port Mappin
26. 1 then if we 1 then RAM conv integer a di end if read a lt a end if end if end process do lt RAM conv integer read a end syn XST User Guide 140 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX Single Port RAM With Enable Verilog Coding Example Single Port RAM with Enable f module v rams 08 clk en we a di do input elk input en input we input 5 0 a input 15 0 di output 15 0 do reg 15 0 ram 63 0 reg 5 0 read a always posedge clk begin if en begin if we ram a lt di read a lt a end end assign do ram read a endmodule The following diagram shows where the two output ports are used It is directly mappable onto Distributed RAM only Dual Port RAM With Asynchronous Read Diagram Distributed SPO RAM DPO Dual Port RAM With Asynchronous Read Pin Descriptions omm bees O eooo o enanada OOOO C E 1 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 141 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Dual Port RAM With Asynchronous Read VHDL Coding Example Dual Port RAM with Asynchronous Read library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity rams 09 is port clk in std logic we in std logic a in std logi
27. DSP slices in the design may come not only from DSP inference processes but also from instantiation Instantiated DSP slices are the primary candidates for available DSP resources The inferred DSPs are placed on the remaining DSP resources If the number of instantiated DSPs exceeds the number of available resources XST does not modify the instantiations and implement them as block DSP slices The same behavior occurs if you force specific macro implementation to be implemented as DSP slices by using the Use DSP48 USE_DSP48 constraint If there are no resources XST respects user constraints even if the number of DSP slices is exceeded If the number of user specified DSP slices exceeds the number of available DSP resources on the target FPGA device XST issues a warning and uses only available DSP resources on the chip for synthesis You can disable automatic DSP resource management for example to see how many DSPs XST can potentially infer for a specific design by specifying 1 or any negative value as a constraint value DSP_UTILIZATION_RATIO DSP Utilization Ratio Architecture Support Applies to the following FPGA devices only Does not apply to any other FPGA devices Does not apply to CPLD devices e Spartan 3A DSP e Virtex 4 e Virtex 5 DSP_UTILIZATION_RATIO DSP Utilization Ratio Applicable Elements Applies to the entire design DSP_UTILIZATION_RATIO DSP Utilization Ratio Propagation Rules Not applicable DS
28. In VHDL a component is represented by a design entity The design entity is a composite consisting of e Entity declaration The entity declaration provides the external view of the component It describes what can be seen from the outside including the component ports e Architecture body The architecture body provides an internal view It describes the behavior or the structure of the component The connections between components are specified within component instantiation statements These statements specify an instance of a component occurring inside an architecture of another component Each component instantiation statement is labeled with an identifier Besides naming a component declared in a local component declaration a component instantiation statement contains an association list the parenthesized list following the reserved word port map The association list specifies which actual signals or ports are associated with which local ports of the component declaration XST supports unconstrained vectors in component declarations XST User Guide 378 www xilinx com UG627 v 11 3 September 16 2009 hipter XST VHDL Language Support XILINX Structural Description of Half Adder VHDL Coding Example The following coding example shows the structural description of a half adder composed of four nand2 components entity NAND2 is port A B in BIT Ys enk BIT j end NAND2 architecture ARCHI of NAND2 is
29. Johnson State Encoding 191 Sequential State Encoding eet ieenieriias eei ed e ENAS AENA R EEEa E E Ear Erri 191 Speed 1 State ENCODING M TEE 191 User State Encoding EE 191 RAM Based Finite State Machine FSM Gantbeste 191 Safe Finite State Machine FSM Implementation eee 192 Finite State Machine FSM Log Pe eteuEEeEESNNEEENEEENEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE SEENEN ENG 192 Finite State Machine FSM Related Constraints sss he Henne nnne 193 Finite State Machine FSM Coding Examples eee 194 Black Boxes Hardware Description Language HDL Coding Techniques sseeee 199 Black Box Log File etre serpere ISIN REL I I ERROR EIE SEE Eos SENSE ERE Woes 200 Black Box Related Constraints ierit c err e ERE NEEN OE Fe FERRE E SPEM Te EARN 200 Black Box Coding Examples P M 200 Chapter 4 XST FPGA Optimization eter terae no SEs seus senssvanssansieuvssevssuvasiecssvassa coscaanccdessenss 203 FPGA Specific Synthesis Options T anaes 204 ETS le EE 204 Arithmetic Functions in Macro Generation 205 Loadable Functions in Macro Generalo en enne nh hen n nnne nennen ene 205 Multipl xers in Macro Generation acts ecece eerte hidden a e eaa oe ie eae E HERE ER SR e EUR ERE ENEE 205 Priority Encoders in Macro Generation eere sesenta aede pa ees ene n nose d a aue oboe un snae euin nee a UN NER EEN 205 Decoders in Macro ee EE 20
30. LOOP_ADD for I in 0 to N generate SUM I lt A I xor B I xor C I C I 1 lt A I and B I or A I and C I or B I and C I end generate end generate end ARCHI VHDL Combinatorial Processes A process assigns values to signals differently than when using concurrent signal assignments The value assignments are made in a sequential mode Later assignments may cancel previous ones See Assignments in a Process VHDL Coding Example First the signal S is assigned to 0 but later on for A and B 1 the value for S is changed to 1 A process is combinatorial when its inferred hardware does not involve any memory elements Said differently when all assigned signals in a process are always explicitly assigned in all paths of the Process statements the process is combinatorial A combinatorial process has a sensitivity list appearing within parentheses after the word process A process is activated if an event value change appears on one of the sensitivity list signals For a combinatorial process this sensitivity list must contain e All signals in conditions for example if and case e All signals on the right hand side of an assignment If one or more signals are missing from the sensitivity list XST issues a warning message for the missing signals and adds them to the sensitivity list In this case the result of the synthesis may be different from the initial design specification A process may contain local var
31. RTL Top Level Output File Name stopwatch ngr Top Level Output File Name stopwatch Output Format NGC Optimization Goal Speed Keep Hierarchy YES Target Technology CoolRunner2 CPLDs Macro Preserve YES XOR Preserve YES Clock Enable YES wysiwyg NO Design Statistics IOs 28 Cell Usage BELS 413 AND2 120 AND3 10 AND4 6 INV 174 OR2 93 OR3 1 XOR2 9 FlipFlops Latches 18 FD 1 FDC 5 FDCE 12 IO Buffers 28 IBUF 4 OBUF 24 Total REAL time to Xst completion 7 00 secs Total CPU time to Xst completion 6 83 secs gt XILINX XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 471 XILINX Total memory usage is 196636 kilobytes Number of errors 0 0 filtered Number of warnings 0 0 filtered Number of infos 0 0 filtered 472 www xilinx com Chapter 11 XST Log File XST User Guide UG627 v 11 3 September 16 2009 XILINX Chapter 12 XST Naming Conventions This chapter describes XST Naming Conventions and includes e XST Net Naming Conventions e XST Instance Naming Conventions e XST Name Generation Control XST Net Naming Conventions The following XST net naming conventions are listed in order of naming priority 1 Maintain external pin names 2 Keep hierarchy in signal names using forward slashes or underscores as hierarchy designators 3 Maintain ou
32. The following coding example describes an 8 bit adder by declaring the bit slice structure 8 bit adder described with a for generate statement entity EXAMPLE is port A B in BIT_VECTOR 0 to 7 GIN zm BIT SUM out BIT VECTOR 0 to 7 COUT i enk BIT end EXAMPLE architecture ARCHI of EXAMPLE is signal C BIT_VECTOR 0 to 8 begin C 0 lt CIN COUT lt C 8 LOOP_ADD for I in 0 to 7 generate SUM I lt A I xor B I xor C I C I 1 lt A I and B I or A I and C I or B I and C I end generate end ARCHI XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 383 XILINX Chapter 7 XST VHDL Language Support The if condition generate statement is supported for static non dynamic conditions The N Bit Adder Described With If Generate and For Generate Statement VHDL Coding Example shows such an example It is a generic N bit adder with a width ranging between 4 and 32 N bit adder described with an if generate and a for generate statement N Bit Adder Described With If Generate and For Generate Statement VHDL Coding Example entity EXAMPLE is generic N INTEGER 8 port A B in BIT_VECTOR N downto 0 CIN in BIT SUM out BIT_VECTOR N downto 0 COUT gt out BIT J3 end EXAMPLE architecture ARCHI of EXAMPLE is signal C BIT_VECTOR N 1 downto 0 begin L1 if N gt 4 and N lt 32 generate C 0 lt CIN COUT lt C N 1
33. V HIDE AL Else Statements eranen vetere Ce Uber e ve E PR De EUER VES segs vu S QE TRE ROO NU X EUR EC QUERER eO dU SENEC GESE 386 VHDL Case Statements cesses eene ese messe e eese sese ese ese sese ese users serere esee 386 VEHIDE For Joop5tatem nts 2 5 2 2 9 Lett ipae tese socer blast il ko depo ev e ere EP EE MERE EE R toad eevee 387 VHDL Sequential Circuits ettet terr eee ern ESE vase dude TREES HERE EE Re IER ERR ee rr SEER 388 VHDL Sequential Process With a Sensitivity List e 388 VHDL Sequential Process Without a Sensitivity List 389 Register and Counter Descriptions VHDL Coding Bxamples sss 389 VHDL Multiple Wait Statements Description 391 VHDL Functions and Procedures eene ee hehehe rete se eese ese ee esee ese se ee eee EEES 392 VHDL Assert Statements eis ene enne memes sese se se ese se e ese ese ese sese esse sese sese sese esee see 393 Using Packages to Define VHDL Models eee eene ene enne nenne 395 Using Standard Packages to Define VHDL Model 395 Using IEEE Packages to Define VHDL Modelen 396 Using Synopsys Packages to Define VHDL Models ssssesssse eH 397 VHDL Constructs Supported in XST sorier iens sese ceret etes tese teda eene ue En dee ERR RS ER NE FUR ER ENEE 397 VHDL Design Entities and Conftoeurationg eH eene ene 398 VADE EX presso Sne EE 399 Va Ile EE 400 ANE BN NS S auro Mere egent dee dee deu deeg dee 401 Chapter 8 XST Verilog Language SUppOrt eere oui pg Ee ee DEENEN
34. XILINX nuit t XST Design Constraints By detecting USE CLOCK ENABLE with a value of no or false XST avoids using CE resources in the final implementation Moreover for some designs putting the Clock Enable function on the data input of the flip flop allows better logic optimization and therefore better QOR In auto mode XST tries to estimate a trade off between using a dedicated clock enable input of a flip flop input and putting clock enable logic on the D input of a flip flop In a case where a flip flop is instantiated by you XST removes the clock enable only if the Optimize Instantiated Primitives option is set to yes Use USE CLOCK ENABLE values are e auto default yes no e true XCF only e false XCF only USE CLOCK ENABLE Use Clock Enable Architecture Support Applies to all FPGA devices Does not apply to CPLD devices USE CLOCK ENABLE Use Clock Enable Applicable Elements Applies to e An entire design through the XST command line e A particular block entity architecture component Asignal representing a flip flop e An instance representing an instantiated flip flop USE CLOCK ENABLE Use Clock Enable Propagation Rules Applies to the entity component module or signal to which it is attached USE CLOCK ENABLE Use Clock Enable Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constrai
35. begin inst LUT2 port map I0 5IO0 I1 511 0 250 end beh Passing an INIT Value Via the INIT Constraint Verilog Coding Example Passing an INIT value via the INIT constraint module v primitive 1 10 11 0 input I0 I1 output O0 INIT 1 LUT2 inst I0 10 I1 I1 0 0 endmodule Passing an INIT Value Via the Generics Mechanism VHDL Coding Example Passing an INIT value via the generics mechanism library ieee use ieee std logic 1164 all library unisim use unisim vcomponents all entity primitive 2 is port IO I1 in std logic Oo out std logic end primitive 2 architecture beh of primitive 2 is begin inst LUT2 generic map INIT gt 1 port map 10 gt 10 11 gt 11 0 gt 0 end beh XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 223 XILINX Chapter 4 XST FPGA Optimization Passing an INIT Value Via the Parameters Mechanism Verilog Coding Example Passing an INIT value via the parameters mechanism Tre module v primitive 2 I0 11 0 input 10 11 output O0 LUTZ 4 h1 inst I0 10 I1 I1 O 0 endmodule Passing an INIT Value Via the Defparam Mechanism Verilog Coding Example Passing an INIT value via the defparam mechanism module v primitive 3 I0 11 0 input 10 11 output O0 LUT2 inst IO IO I1 I1 0 0 defparam inst INIT 4 hl endmodule Using the UniMacro Library In or
36. do2 out std logic vector 15 downto 0 end rams 12 architecture syn of rams 12 is type ram type is array 63 downto 0 of std logic vector 15 downto 0 signal RAM ram type signal read add1 std logic vector 5 downto 0 signal read addi std logic vector 5 downto 0 begin process clkl begin if clkl event and clk1 1 then if we 1 then RAM conv integer addl lt di end if read addl lt addl end if end process dol lt RAM conv integer read addl process clk2 begin if clk2 event and clk2 1 then read add2 lt add2 end if end process do2 lt RAM conv integer read add2 end syn XST User Guide 146 www xilinx com UG627 v 11 3 September 16 2009 nuit XST Hardware Description Language HDL Coding Techniques XILINX Dual Port RAM With Synchronous Read Read Through and Two Clocks Verilog Coding Example Dual Port RAM with Synchronous Read Read Through using More than One Clock module v_rams_12 clkl1 clk2 we addl add2 di dol do2 input clkl input clk2 input we input 5 0 addl input 5 0 add2 input 1520 di output 15 0 dol output 15 0 do2 reg 15 0 ram 63 0 reg 5 0 read add1 reg 5 0 read addi always posedge clk1 begin if we ram addl lt di read addl lt addl end assign dol ram read addl always posedge clk2 begin read_add2 lt add2 end assign d
37. gt tmp inst and two and two port map A gt tmp B gt C REZ gt REZ end beh XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 227 XILINX Chapter 4 XST FPGA Optimization Passing an INIT Value Via the LUT_MAP Constraint Verilog Coding Example Mapping on LUTs via LUT_MAP constraint det LUT_MAP yes module v_and_one A B REZ input A B output REZ and and_inst REZ A B endmodule LUT MAP yes module v and two A B REZ input A B output REZ or or inst REZ A B endmodule module v inits rlocs 1 A B C input A B C output REZ wire tmp v and one inst and one A B tmp v and two inst and two tmp C endmodule Specifying INIT Value for a Flip Flop Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip If a function cannot be mapped on a single LUT XST issues an error message and interrupts synthesis To define an INIT value for a flip flop or a shift register described at RTL level assign its initial value in the signal declaration stage This value is not ignored during synthesis and is propagated to the final netlist as an INIT constraint attached to the flip flop or shift register In the following coding examples a 4 bit register is inferred for signal tmp An INIT value equal 1011 is attached to the in
38. if in2 begin outl 0 1 b0 outl1 1 lt inl end else begin outl 0 in2 outl 1 lt 1 b1 end Errors are checked at the signal level not at the bit level If there is more than one blocking or non blocking error only the first is reported In some cases the line number for the error might be incorrect as there might be multiple lines where the signal has been assigned Verilog Integer Handling XST handles integers differently from other synthesis tools in several instances They must be coded in a particular way Integer Handling in Verilog Case Statements Unsized integers in case item expressions may cause unpredictable results In the following coding example the case item expression 4 is an unsized integer that causes unpredictable results To avoid problems size the 4 to 3 bits as follows reg 2 0 conditionl always 8 conditionl begin case conditionl 4 data out 2 lt will generate bad logic 3 d4 data out 2 lt will work endcase end Integer Handling in Verilog Concatenations Unsized integers in concatenations may cause unpredictable results If you use an expression that results in an unsized integer assign the expression to a temporary signal and use the temporary signal in the concatenation as follows reg 31 0 temp assign temp 4 b1111 2 assign dout 12 3 temp din XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 409 XILINX Ch
39. library ieee use ieee std_logic_1164 all use ieee numeric_std all entity multipliers_2 is generic A_port_size integer 18 B_port_size integer 18 port clk in std logic A in unsigned A port size 1 downto 0 B in unsigned B port size 1 downto 0 MULT out unsigned A port size B port size 1 downto 0 attribute mult style string attribute mult style of multipliers 2 entity is pipe lut end multipliers 2 architecture beh of multipliers 2 is signal a in b in unsigned A port size 1 downto 0 signal mult res unsigned A port size B port size 1 downto 0 signal pipe 1 pipe 2 pipe 3 unsigned IA port size B port size 1 downto 0 begin mult res a in b in process clk begin if clk event and clk 1 then a in lt A b in lt B pipe 1 lt mult res pipe 2 pipe 1 pipe 3 lt pipe 2 MULT pipe 3 end if end process end beh XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 107 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Pipelined Multiplier Outside Single Verilog Coding Example Pipelined multiplier ff The multiplication operation placed outside the iy always block and the pipeline stages represented as single registers mult_style pipe_lut module v_multipliers_2 clk A B MULT input cik input 17 0 A input 17 0 B output 35 0 MUL
40. nuit t XST Design Constraints LC supports three values auto XST tries to make a trade off between area and speed area XST performs maximum LUT combining to provide as small an implementation as possible e off Disables LC LC LUT Combining Architecture Support Applies to Virtex 5 devices only Does not apply to any other FPGA devices Does not apply to CPLD devices LC LUT Combining Applicable Elements Applies to the entire design LC LUT Combining Propagation Rules Not applicable LC LUT Combining Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it LC LUT Combining XST Command Line Syntax Example Define in the XST command line as follows xst run lc auto area off The default is off LC LUT Combining ISE Design Suite Syntax Example Define in ISE Design Suite with Process gt Properties gt Xilinx Specific Options gt LUT Combining BRAM_MAP Map Logic on BRAM BRAM_MAP Map Logic on BRAM is used to map an entire hierarchical block on the block RAM resources available in Virtex devices and later technologies BRAM MAP values are yes e no default BRAM MAP is both a global and a local constraint For more information see Mapping Logic Onto Block RAM BRAM MAP Map Logic on BRAM Architecture Support Applies to all FPGA devices Does not apply to
41. posedge clk begin if reset mult lt 16 b0000000000000000 else mult lt A B end always posedge clk begin if reset accum lt 16 b0000000000000000 else accum lt accum mult end assign RES accum endmodule Multiplier Up Down Accumulate With Register After Multiplication Diagram ADD SUB RESET e X10561 Multiplier Up Down Accumulate With Register After Multiplication Pin Descriptions Description clk Positive Edge Clock reset Synchronous Reset add_sub AddSub Selector A B MAC Operands RES MAC Result XST User Guide 120 www xilinx com UG627 v 11 3 September 16 2009 nuit XST Hardware Description Language HDL Coding Techniques XILINX Multiplier Up Down Accumulate With Register After Multiplication VHDL Coding Example Multiplier Up Down Accumulate with Register After Multiplication library IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD LOGIC UNSIGNED ALL entity multipliers 7b is generic p width integer 8 port clk reset add sub in std logic A B in std logic vector p width 1 downto 0 RES out std logic vector p width 2 1 downto 0 end multipliers 7b architecture beh of multipliers 7b is signal mult accum std logic vector p width 2 1 downto 0 begin process clk begin if clk event and clk 1 then if reset 1 then accum lt others gt 0 mult lt others gt 0 else if ad
42. read line std_ulogic ieee std_logic_textio XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 367 XILINX Chapter 7 XST VHDL Language Support read line std_ulogic_vector boolean read line std_logic_vector boolean write line std_ulogic boolean write line std_ulogic_vector boolean write line std_logic_vector boolean Debugging Using Write Operation in VHDL Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip XST User Guide 368 www xilinx com UG627 v 11 3 September 16 2009 hipter XST VHDL Language Support XILINX Debugging Using Write Operation in VHDL Coding Example Print 2 constants to the output file library IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD LOGIC arith ALL use IEEE STD LOGIC UNSIGNED ALL use STD TEXTIO all use IEEE STD LOGIC TEXTIOC all entity file support 1l is generic data width integer 4 port clk sel in std logic din in std logic vector data width 1 downto 0 dout out std logic vector data width 1 downto 0 end file support 1 architecture Behavioral of file support 1 is file results text is out test dat constant base const std logic vector data width 1 downto 0 conv std logic vector 3 data width constant new const std logic vector data width 1 downto 0 base const 1000 begin
43. write enable ram conv integer addr di end if if rst 1 then optional reset do lt others gt 0 else do lt ram conv integer addr end if end if end if end process end syn XST User Guide 166 www xilinx com UG627 v 11 3 September 16 2009 Chipter XST Hardware Description Language HDL Coding Techniques XILINX Block RAM With Reset Verilog Coding Example Block RAM with Reset module v_rams_18 clk en we rst addr di do input elk input en input we input rst input 5 0 addr input 15 0 di output 15 0 do reg 15 0 ram 63 0 reg 15 0 do always posedge clk begin if en optional enable begin if we write enable ram addr lt di if rst optional reset do lt 16 h0000 else do lt ram addr end end endmodule Block RAM With Optional Output Registers Diagram Block WE RAM EN1 RES1 EN2 D ADDR1 RES2 ADDR2 CLK1 CLK2 x10569 Block RAM With Optional Output Registers Pin Descriptions Description clk1 clk2 Positive Edge Clock we Write Enable en1 en2 Clock Enable Active High addr1 Primary Read Address addr2 Dual Read Address di Data Input Primary Output Port Dual Output Port XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 167 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Block RAM With Op
44. yes no true false END EQUIVALENT REGISTER REMOVAL Equivalent Register Removal XST Command Line Syntax Example Define in the XST command line as follows equivalent register removal yes no The default is yes EQUIVALENT REGISTER REMOVAL Equivalent Register Removal ISE Design Suite Syntax Example Define in ISE Design Suite with Process gt Properties gt Xilinx Specific Options gt Equivalent Register Removal XST User Guide 288 www xilinx com UG627 v 11 3 September 16 2009 taptir t XST Design Constraints XILINX FSM_ENCODING FSM Encoding Algorithm FSM_ENCODING FSM Encoding Algorithm selects the Finite State Machine FSM coding technique In order to select a value for the FSM Encoding Algorithm Automatic FSM Extraction must be enabled FSM Encoding Algorithm values are e Auto e One Hot e Compact e Sequential e Gray e Johnson e Speed1 e User FSM Encoding Algorithm defaults to auto The best coding technique is automatically selected for each individual state machine FSM_ENCODING FSM Encoding Algorithm Architecture Support Architecture independent FSM_ENCODING FSM Encoding Algorithm Applicable Elements Applies to the entire design or to an entity component module or signal FSM_ENCODING FSM Encoding Algorithm Propagation Rules Applies to the entity component module or signal to which it is attached FSM_ENCODING FSM Encoding Algorithm Syntax Exampl
45. B 2 S1 1 S2 ADD A 3 B 3 S2 1 S3 S S3 0 S2 0 SI O SO O COUT S3 1 end endmodule Behavioral Verilog Recursive Tasks and Functions Verilog 2001 adds support for recursive tasks and functions You can use recursion only with the automatic keyword To prevent endless recursive calls the number of recursions is limited by default to 64 Use the recursion iteration limit option to control the number of allowed recursive calls Behavioral Verilog Syntax Using Recursion Coding Example function automatic 31 0 fac input 15 0 n if n 1 fac 1 else fac n fac n 1 recursive function call endfunction Behavioral Verilog Constant Functions Verilog 2001 adds support for constant functions XST supports function calls to calculate constant values XST User Guide 432 www xilinx com UG627 v 11 3 September 16 2009 thipter t XST Behavioral Verilog Language Support XILINX Evaluation of a Constant Function Behavioral Verilog Coding Example module rams_cf clk we a di do parameter DEPTH 1024 input clk input we input 4 0 a input 3 0 di output 3 0 do reg 3 0 ram size DEPTH 0 always posedge clk begin if we ram a lt di end assign do ram a function integer size input depth integer i begin size 1 for i 0 2 i depth i i 1 size itl end endfunction endmodule Behavioral Verilog Blocking Versus Non Blocking Proced
46. Define in the XST command line as follows xst run async to sync yes no The default is no ASYNC TO SYNC Asynchronous to Synchronous ISE Design Suite Syntax Example Define in ISE Design Suite with Process Properties HDL Options Asynchronous to Synchronous AUTO BRAM PACKING Automatic BRAM Packing Automatic BRAM Packing AUTO BRAM PACKING allows you to pack two small BRAMs in a single BRAM primitive as dual port BRAM XST packs BRAMs together only if they are situated in the same hierarchical level AUTO BRAM PACKING Architecture Support Applies to all FPGA devices Does not apply to CPLD devices XST User Guide 298 www xilinx com UG627 v 11 3 September 16 2009 taptir t XST Design Constraints XILINX AUTO_BRAM_PACKING Applicable Elements Applies to the entire design AUTO_BRAM_PACKING Propagation Rules Not applicable AUTO_BRAM_PACKING Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it Automatic BRAM Packing XST Command Line Syntax Example Define in the XST command line as follows auto_bram_packing yes no The default is no Automatic BRAM Packing ISE Design Suite Syntax Example Define in ISE Design Suite with Process gt Properties gt Automatic BRAM Packing BRAM_UTILIZATION_RATIO BRAM Utilization Ratio BRAM_UTILIZATION_RATIO BRAM Utiliza
47. EOUIVALENT REGISTER REMOVAL e FSM Encoding Algorithm FSM_ENCODING e Mux Extraction MUX EXTRACT e Register Power Up REGISTER POWERUD e Resource Sharing RESOURCE SHARING e Safe Recovery State SAFE RECOVERY STATE e Safe Implementation SAFE IMPLEMENTATION e Signal Encoding SIGNAL ENCODING The constraints described in this chapter apply to e FPGA devices e CPLD devices e VHDL code e Verilog code Most of the constraints can be set globally in ISE Design Suite in Process gt Properties gt HDL Options The only constraints that cannot be set in Process gt Properties are e Enumerated Encoding ENUM_ENCODING e Safe Recovery State SAFE RECOVERY STATE e Signal Encoding SIGNAL ENCODING FSM EXTRACT Automatic FSM Extraction FSM EXTRACT Automatic FSM Extraction enables or disables finite state machine extraction and specific synthesis optimizations In order to set values for the FSM Encoding Algorithm and FSM Flip Flop Type Automatic FSM Extraction must be enabled XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 285 XILINX Chapter t XST Design Constraints FSM_EXTRACT Automatic FSM Extraction Architecture Support Architecture independent FSM_EXTRACT Automatic FSM Extraction Applicable Elements Applies to the entire design or to an entity component module or signal FSM_EXTRACT Automatic FSM Extraction Propagation Rules Applies to the entity component module o
48. FSM_STYLE are e Lut default XST maps the FSM using LUTs bram XST maps the FSM onto block RAM XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 191 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Invoke FSM Style FSM_STYLE as follows e ISE Design Suite Select LUT or Block RAM as instructed in the HDL Options topics of the ISE Design Suite Help e Command line Use the sm style command line option e Hardware Description Language HDL code Use FSM Style F5M STYLE If it cannot implement a state machine on block RAM XST e Issues a warning in the Advanced HDL Synthesis step of the log file e Automatically implements the state machine using LUTs For example if FSM has an asynchronous reset it cannot be implemented using block RAM In this case XST informs you WARNING Xst Unable to fit FSM FSM 0 in BRAM reset is asynchronous Selecting encoding for FSM O Optimizing FSM FSM 0 on signal current state with one hot encoding Safe Finite State Machine FSM Implementation XST can add logic to your Finite State Machine FSM implementation that will let your state machine recover from an invalid state If during its execution a state machine enters an invalid state the logic added by XST will bring it back to a known state called a recovery state This is known as Safe Implementation mode To activate Safe FSM implementation e In ISE Design S
49. Follow these general rules Chapter t XST Design Constraints Several constraints can be applied on signals In this case the constraint must be placed in the block where the signal is declared and used If a constraint can be applied on an entity VHDL then it can also be applied on the component declaration The ability to apply constraints on components is not explicitly stated for each individual constraint since it is a general XST rule Some third party synthesis tools allow you to apply constraints on architectures XST allows constraints on architectures only for those third party constraints automatically supported by XST List of XST Design Constraints Following is a list of XST Design Constraints organized by type XST General Constraints XST HDL Constraints XST FPGA Constraints Non Timing XST CPLD Constraints Non Timing XST Timing Constraints XST Implementation Constraints Third Party Constraints 242 www xilinx com XST User Guide UG627 v 11 3 September 16 2009 nuit XST Design Constraints XST General Constraints The following constraints are found in XST General Constraints Add I O Buffers iobuf BoxType BOX_TYPE Bus Delimiter bus_delimiter Case case Case Implementation Style vlgcase Verilog Macros define Duplication Suffix duplication_suffix Full Case FULL_CASE Generate RTL Schematic rtlview Generics generics Hierarchy Separator hierarchy
50. IEEE VHDL Language Reference Manual XST Design Constraints VHDL Attribute Syntax VHDL offers a broad set of constructs for compactly describing complicated logic VHDL allows the description of the structure of a system how it is decomposed into subsystems and how those subsystems are interconnected VHDL allows the specification of the function of a system using familiar programming language forms VHDL allows the design of a system to be simulated before being implemented and manufactured This feature allows you to test for correctness without the delay and expense of hardware prototyping VHDL provides a mechanism for easily producing a detailed device dependent version of a design to be synthesized from a more abstract specification This feature allows you to concentrate on more strategic design decisions and reduce the overall time to market for the design XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 365 XILINX Chapter 1 XST VHDL Language Support VHDL IEEE Support XST supports e VHDL IEEE std 1076 1987 e VHDL IEEE std 1076 1993 e VHDL IEEE std 1076 2006 partially implemented XST allows instantiation for VHDL IEEE std 1076 2006 when e The formal port is a buffer and the associated actual is an out e The formal port is an out and the associated actual is a buffer VHDL IEEE Conflicts VHDL IEEE std 1076 1987 constructs are accepted if they do not conflict with VHDL IEEE std 1076
51. It also supports All overloaded arithmetic operators on these types Conversion and extended functions for these types numeric std Supports the following types based on type std logic Unsigned vectors Signed vectors This package is equivalent to std logic arith math real Supports the following Real number constants as shown in VHDL Real Number Constants Real number functions as shown in VHDL Real Number Constants The procedure uniform which generates successive values between 0 0 and 1 0 VHDL Real Number Constants Bn ee ene EENEG Lenia math rove math roves Let gas EE XST User Guide 396 www xilinx com UG627 v 11 3 September 16 2009 hipter XST VHDL Language Support XILINX VHDL Real Number Functions Fimo e e damned Functions and procedures in the math real packages as well as the real type are for calculations only They are not supported for synthesis in XST Following is an example library ieee use IEEE std logic signed all signal a b c std logic vector 5 downto 0 lt a Di this operator is defined in package std logic signed Operands are converted to signed vectors and function defined in package std logic arith is called with signed operands Using Synopsys Packages to Define VHDL Models The following Synopsys packages are supported in the IEEE library e std logic arith Suppo
52. Offset 1 655ns Levels of Logic 3 Source STRTSTOP PAD Destination MACHINE current state FS5M FFd3 FF Destination Clock CLK rising Data Path STRTSTOP to MACHINE current state F5M FFd3 Gate Net Cell in gt out fanout Delay Delay Logical Name Net Name IBUF I gt O 4 0 754 0 446 STRTSTOP IBUF STRTSTOP IBUF LUT4 I2 gt O 1 0 147 0 000 MACHINE current state F5M FFd3 In F N48 MUXF5 10 gt O 1 0 291 0 000 MACHINEJ current state F5M FFd3 In MACHINE current state FS5M FFd3 In FDC D 0 017 MACHINE current state F5M FFd3 Total 1 655ns 1 209ns logic 0 446ns route 73 0 logic 27 0 route Timing constraint Default OFFSET OUT AFTER for Clock CLK Total number of paths destination ports 96 24 Offset 4 617ns Levels of Logic 2 Source sixty Isbcount OOUT 1 FF Destination ONESOUT lt 6 gt PAD Source Clock CLK rising Data Path sixty lsbcount OOUT 1 to ONESOUT lt 6 gt Gate Net Cell in gt out fanout Delay Delay Logical Name Net Name FDC C gt Q 13 0 272 0 677 sixty lsbcount OOUT 1 sixty Isbcount OOUT 1 LUT4 10 gt O 1 0 147 0 266 Isbled Mrom_LED21 Isbled Mrom LED2 OBUF I gt O 3 255 ONESOUT 2 OBUF ONESOUT lt 2 gt Total 4 617ns 3 674ns logic 0 943ns route 79 676 logic 20 476 route Total REAL time to Xst completion 20 00 secs XST User Guide 464 www xilinx com UG627 v 11 3 September 16 2009 Chapter ti XST Log File XILINX Total CPU time to Xst com
53. Recognized Macros XST Log File Example The following log file example shows the set of recognized macros on a block by block basis as well as the overall macro statistics after this step Synthesizing Unit lt decode gt Related source file is decode vhd Found 16x10 bit ROM for signal lt one_hot gt Summary inferred 1 ROM s Unit lt decode gt synthesized Synthesizing Unit lt statmach gt Related source file is statmach vhd Found finite state machine FSM 0 for signal current state States 6 Transitions 11 Inputs B Outputs 2 Clock CLK rising edge Reset RESET positive Reset type asynchronous Reset State clear Power Up State clear Encoding automatic Implementation LUT Summary inferred 1 Finite State Machine s Unit lt statmach gt synthesized HDL Synthesis Report Macro Statistics ROMs 16x10 bit ROM 16x7 bit ROM Counters 4 bit up counter MNNEF LA 452 www xilinx com XST User Guide UG627 v 11 3 September 16 2009 Chapter ti XST Log File XILINX Additional Macro Processing XST Log File Example The following XST FPGA log file example shows the additional macro processing done during the Advanced HDL Synthesis step and the overall macro statistics after this step Analyzing FSM FSM 0 for best encoding Optimizing FSM MACHINE current state FSM 0 on signal current state 1 3 with gray encoding State Encoding clear 0
54. Verilog modules specified in the Hardware Description Language HDL design and does not concern the macros inferred by the HDL synthesizer Keep Hierarchy values are true Allows the preservation of the design hierarchy as described in the HDL project If this value is applied to synthesis it is also propagated to implementation The default is true for CPLD devices e false Hierarchical blocks are merged in the top level module The default is false for FPGA devices soft Allows the preservation of the design hierarchy in synthesis but KEEP HIERARCHY is not propagated to implementation In general a Hardware Description Language HDL design is a collection of hierarchical blocks Preserving the hierarchy gives the advantage of fast processing because the optimization is done on separate pieces of reduced complexity Nevertheless very often merging the hierarchy blocks improves the fitting results fewer PTerms and device macrocells better frequency because the optimization processes collapsing factorization are applied globally on the entire logic In the following figure if Keep Hierarchy is set to the entity or module D the hierarchy of I2 is in the final netlist but its contents H I5 are flattened inside I2 I1 I3 I6 and I7 are also flattened KEEP HIERARCHY Keep Hierarchy Diagram NGC FILE 1 I0 10 I2 KEEP HIERARCHY YES 12 WM Design View Netlist View KEEP_HIERARCHY Keep Hierarchy Architecture
55. XILINX nuit t XST Design Constraints USE SYNC SET Use Synchronous Set Propagation Rules Applies to the entity component module or signal to which it is attached USE_SYNC_SET Use Synchronous Set Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it USE_SYNC_SET Use Synchronous Set VHDL Syntax Example Declare as follows attribute use_sync_set string Specify as follows attribute use_sync_set of entity name component name signal name instance_name entity component signal label is auto yes no USE SYNC SET Use Synchronous Set Verilog Syntax Example Place immediately before the module or signal declaration use sync set auto yes no zi USE SYNC SET Use Synchronous Set XST Constraint File XCF Syntax Example One MODEL entity name use sync set auto yes no true false USE SYNC SET Use Synchronous Set XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name NET signal name use sync set auto yes no true false END USE SYNC SET Use Synchronous Set XST Constraint File XCF Syntax Example Three BEGIN MODEL entity name INST instance name use sync set auto yes no true false END USE SYNC SET Use Synchronous Set XST Command Line Syntax Example Define in the XST command line as follows xst run
56. architecture syn of rams 22 is type ram type is array 511 downto 0 of std logic vector 3 downto 0 signal RAM ram type signal pipe reg std logic vector 3 downto 0 attribute ram style string attribute ram style of RAM signal is pipe distributed begin process clk begin if clk event and clk 1 then if we 1 then RAM conv integer addr lt di else pipe reg lt RAM conv integer addr end if do lt pipe reg end if end process end syn Pipelined Distributed RAM Verilog Coding Example Pipeline distributed RAMs module v_rams_22 clk we addr di do input clk input we input 8 0 addr input 3 0 di output 3 0 do ram style pipe distributed reg 3 0 RAM 511 0 reg 3 0 do reg 3 0 pipe reg always posedge clk begin if we RAM addr lt di else pipe reg lt RAM addr do lt pipe_reg end endmodule XST User Guide 188 www xilinx com UG627 v 11 3 September 16 2009 nuit XST Hardware Description Language HDL Coding Techniques XILINX Finite State Machine FSM Hardware Description Language HDL Coding Techniques Xilinx Synthesis Technology XST e Includes a large set of templates to describe Finite State Machine FSM components e Can apply several state encoding techniques to obtain better performance or less area e Can re encode your initial encoding e Can handle only synchronous state machines To dis
57. but sets the constraint from the sequential elements to all primary output ports INPAD TO OUTPAD inpad to outpad Sets a maximum combinational path constraint e MAX DELAY Identifies all paths defined by Identifies all paths defined by the following timing constraints ALLCLOCKNETS OFFSET IN BEFORE OFFSET OUT AFTER INPAD TO OUTPAD XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 355 XILINX nuit t XST Design Constraints Offset in Before AllClockNets Period Offset_out_After IPAD D Q D Q gt CLK gt CLK IPAD gt EO Inpad_to_Outpad OPAD IPAD XST Constraint File XCF Timing Constraint Support If you specify timing constraints in the XST Constraint File XCF Xilinx recommends that you use a forward slash as a hierarchy separator instead of an underscore For more information see Hierarchy Separator hierarchy separator If all or part of a specified timing constraint is not supported by XST then XST issues a warning and ignores the unsupported timing constraint or unsupported part of it in the Timing Optimization step If the Write Timing Constraints option is set to yes XST propagates the entire constraint to the final netlist even if it was ignored at the Timing Optimization step The following timing constraints are supported in the XCF e Period PERIOD e Offset OFFSET e From To FROM TO e Timing Name TNM Timing Name on a Ne
58. e Global Optimization Goal glob opt e Keep Hierarchy KEEP HIERARCHY e Logical Shifter Extraction SHIFT EXTRACT e Map Logic on BRAM BRAM MAD e Max Fanout MAX FANOUT e Move First Stage MOVE FIRST STAGE e Move Last Stage MOVE LAST STAGE e Multiplier Style MULT STYLE e Mux Style MUX STYLE e Number of Global Clock Buffers bufg e Optimize Instantiated Primitives OPTIMIZE PRIMITIVES e Pack I O Registers Into IOBs IOB e Priority Encoder Extraction PRIORITY EXTRACT RAM Style RAM STYLE e Register Balancing REGISTER BALANCINC e Register Duplication REGISTER DUPLICATION e Signal Encoding SIGNAL ENCODING e Slice Packing slice packing e Use Carry Chain USE CARRY CHAIN e Write Timing Constraints write timing constraints e XOR Collapsing XOR COLLAPSE Macro Generation The FPGA Device Macro Generator module provides the XST HDL Flow with a catalog of functions These functions are identified by the inference engine from the Hardware Description Language HDL description Their characteristics are handed to the Macro Generator for optimal implementation The set of inferred functions ranges in complexity from simple arithmetic operators such as adders accumulators counters and multiplexers to more complex building blocks such as multipliers shift registers and memories Inferred functions are optimized to deliver the highest levels of performance and efficiency for the selected V
59. end if end process end syn XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 173 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Dual Port RAM Initial Contents Verilog Coding Example Initializing Block RAM Dual Port BRAM module v rams 20b clkl clk2 we addrl addr2 di dol do2 input clk1 clk2 input we input 7 0 addrl addr2 input 15 0 di output 15 0 dol do2 reg 15 0 ram 255 0 reg 15 0 dol do2 integer index initial begin for index 0 index lt 99 index index 1 begin ram index 16 h8282 end for index 100 index lt 255 index index 1 begin ram index 16 hB8B8 end end always posedge clk1 begin if we ram addrl lt di dol lt ram addr1l end always posedge clk2 begin do2 lt ram addr2 end endmodule Initializing RAM From an External File The following coding examples show how to initialize RAM from an external file For further information see Initializing RAM Directly in Hardware Description Language HDL Code above To initialize RAM from values contained in an external file use a read function in the VHDL code For more information see XST VHDL File Type Support Set up the initialization file as follows e Use each line of the initialization file to represent the initial contents of a given row in the RAM e RAM contents can be represented in bin
60. ftp ftp xilinx com pub documentation misc examples_v9 zip Behavioral Verilog Explicit Continuous Assignment Coding Example wire par eq 1 assign par eq ls select b a XST User Guide 424 www xilinx com UG627 v 11 3 September 16 2009 thipter t XST Behavioral Verilog Language Support XILINX Behavioral Verilog Implicit Continuous Assignment Coding Example wire temp_hold a b Continuous assignments are allowed on wire and tri data types only Behavioral Verilog Procedural Assignments Procedural assignments are e Used to assign values to variables declared as regs e Introduced by always blocks tasks and functions e Usually used to model registers and Finite State Machine FSM components XST supports e Combinatorial functions e Combinatorial and sequential tasks e Combinatorial and sequential always blocks Behavioral Verilog Combinatorial Always Blocks Combinatorial logic can be modeled efficiently using two forms of Verilog time control statements e d pound e Q asterisk Since the pound time control statement is ignored for synthesis this discussion describes modeling combinatorial logic with the asterisk time control statement A combinatorial always block has a sensitivity list appearing within parentheses after the word always An always block is activated if an event value change or edge appears on one of the sensitivity list signals This sensitivity list can contain any s
61. v 11 3 September 16 2009 www xilinx com 133 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Single Port RAM In Write First Mode Verilog Coding Example One Write First Mode template 1 module v_rams_02a clk we en addr di do input cik input we input en input 5 0 addr input 15 0 di output 15 0 do reg 15 0 RAM 63 0 reg 15 0 do always posedge clk begin if en begin if we begin RAM addr lt di do lt di end else do lt RAM addr end end endmodule Single Port RAM In Write First Mode Verilog Coding Example Two Write First Mode template 2 module v_rams_02b clk we en addr di do input clk input we input en input 5 0 addr input 15 0 di output 15 0 do reg 15 0 RAM 63 0 reg 5 0 read addr always posedge clk begin if en begin if we RAM addr lt di read_addr lt addr end end assign do RAM read addr endmodule XST User Guide 134 www xilinx com UG627 v 11 3 September 16 2009 hapter 3 XST Hardware Description Language HDL Coding Techniques XILINX Single Port RAM In No Change Mode Diagram X10565 Single Port RAM In No Change Mode Pin Descriptions S s addr Read Write Address C XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 135 XILINX Chapter i XST Hardware Description Langu
62. 1 LUT4_L 4 MUXCY 3 MUXF5 2 VCC 1 XORCY 4 FlipFlops Latches 17 FDC 13 FDCE 4 Clock Buffers 1 BUFG 1 IO Buffers 27 IBUF 2 XILINX XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 461 XILINX Chapter 11 XST Log File IBUFG 1 OBUF 24 DCM ADVs 1 DCM ADV 1 Device utilization summary Selected Device 4vlx15sf363 12 Number of Slices 32 out of 6144 0 Number of Slice Flip Flops 17 out of 12288 0 Number of 4 input LUTs 58 out of 12288 0 Number of IOs 27 Number of bonded IOBs 27 out of 240 1196 Number of GCLKs 1 out of 32 3 Number of DCM_ADVs 1 out of 4 25 TIMING REPORT NOTE THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE and ROUTE Clock Information Clock Signal Clock buffer FF name Load CLK Inst dcem1 DCM INST CLKOI 17 Asynchronous Control Signals Information Control Signal Buffer FF name Load MACHINE RST MACHINE RST Q NONE sixty lsbcount OOUT 1 18 XST User Guide 462 www xilinx com UG627 v 11 3 September 16 2009 Chapter tt XST Log File RESET IBUF 5 sixty msbclr sixty msbclr_f5 O NONE sixty msbcount QOUT_0 4
63. 1 Select Process gt Properties gt Synthesis Options 2 From the Property display level list select Advanced 3 Set the Hierarchy Separator property hierarchy_separator Hierarchy Separator Architecture Support Architecture independent hierarchy_separator Hierarchy Separator Applicable Elements Applies to files hierarchy_separator Hierarchy Separator Propagation Rules Not applicable hierarchy_separator Hierarchy Separator Syntax hierarchy separator _ The default is forward slash for newly created projects hierarchy separator Hierarchy Separator Syntax Example xst run hierarchy separator Ai n Sets the hierarchy separator to underscore IOSTANDARD I O Standard Use I O Standard IOSTANDARD to assign an I O standard to an I O primitive For more information see IOSTANDARD in the Constraints Guide KEEP Keep KEEP Keep is an advanced mapping constraint When a design is mapped some nets may be absorbed into logic blocks When a net is absorbed into a block it can no longer be seen in the physical design database This may happen for example if the components connected to each side of a net are mapped into the same logic block The net may then be absorbed into the block containing the components KEEP prevents this from happening In addition to true and false values supported by the implementation flow XST supports a soft value If this value is specified XST preserves the de
64. 1 0 il 12 13 i14 output 1 0 01 reg 1 0 o1 always sel or il or i2 or i3 or i4 begin case sel 2a bO0 ol 2 bOl ol 2 pi0 ol 2 pii et endcase end endmodule il i2 i3 i4 uU wg dw og Multiplexers Not Full But Parallel Case Statement Coding Example module notfull sel il i2 i3 o1 input 1 0 sel input 1 0 il i2 i3 output 1 0 o1 reg 1 0 o1 always G8 sel or il or i2 or i3 begin case sel 2 b00 ol 2r HOL ol a blO0r ol endcase end endmodule SCT i2 i3 uo dw og XST User Guide 68 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX Multiplexers Neither Full Nor Parallel Case Statement Coding Example module notfull notparallel sell sel2 il i2 o1 input 1 0 sell sel2 input 1 0 il i2 output 1 0 o1 reg 1 0 o1 always 8 sell or sel2 begin case 2 5b00 sell ol il sel2 ol i2 endcase end endmodule XST automatically determines the characteristics of the Case statements and generates logic using multiplexers priority encoders and latches that best implement the exact behavior of the Case statement Multiplexers Verilog Case Implementation Style Parameter This characterization of the Case statements can be guided or modified by using the Case Implementation Style parameter For more information see XST Design Constraints Accepted values
65. 18x18 unsigned multiplier In this case XST implements most of the logic in one DSP48 and the rest in LUTs For Virtex 4 devices Virtex 5 devices and Spartan 3A DSP devices XST can infer pipelined multipliers not only for the LUT implementation but for the DSP48 implementation as well For more information see XST Limitations Macro implementation on DSP48 blocks is controlled by the Use DSP48 USE_DSP48 constraint or command line option with a default value of auto In this mode XST implements multipliers taking into account available DSP48 resources in the device In auto mode use DSP Utilization Ratio DSP_UTILIZATION_RATIO to control DSP48 resources for the synthesis By default XST tries to utilize all DSP48 resources For more information see DSP48 Block Resources XST can automatically recognize the Multiplier Style MULT STYLE constraint with values lut and block and then convert internally to Use DSP48 USE_DSP48 Xilinx recommends using the Use DSP48 USE_DSP48 constraint for Virtex 4 device designs and Virtex 5 device designs to define FPGA resources used for multiplier implementation Xilinx recommends using the Multiplier Style MULT STYLE constraint to define the multiplier implementation method on the selected FPGA resources If Use DSP48 USE DSP48 is set to auto or yes you may usemult style pipe block to pipeline the DSP48 implementation if the multiplier implementation requires multiple DSP48 blocks If Use DS
66. AREA SPEED opt level 1 2 keep hierarchy YES NO vlgincdir verilog2001 YES NO vlgcase Full Parallel Full Parallel Setting Up an XST Script Using the Set Command XST recognizes the Set command The Set command accepts the options shown in the following table For more information see XST Design Constraints Set Command Options tmpdir Location of all temporary files Any valid path to a directory generated by XST during a session xsthdpdir Work Directory location of all Any valid path to a directory files resulting from VHDL or Verilog compilation Setting Up an XST Script Using the Elaborate Command Use the Elaborate command to pre compile VHDL and Verilog files in a specific library or to verify Verilog files without synthesizing the design Since compilation is included in the run the Elaborate command is optional The Elaborate command accepts the options shown in the following table For more information about these options see XST Design Constraints XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 479 XILINX haipter 11 XST Command Line Mode Elaborate Command Options work lib Work Library for Compilation name work library where the top level block was compiled vlgpath Verilog Search Paths Any valid path to directories separated by spaces and enclosed in double quotes vlgincdir Verilog Include Directories Any valid path to directo
67. Cell Usage T M 216 Tristates Cell EE 216 Clock Buthers Cell Usage 216 IO Buffers Cell Usage wm 216 LOGICAL Cell Usa se c 216 OTHER Cell BEEN 217 TIMING Report LRL 217 Pompe Report Example m 218 Timing Report Timing Summary Dechen 219 Timing Report Timing Detail Section 0 cee e eee eene nennen 219 Timing Report Schema serere sosire ann n a r secdossadendagsindis CE e EE E E REE edd eeng 219 Timung Report Paths and Portsea ntl rr e Ye rosae Ana decries ETER 220 Implementation ConstraiiS m 220 FPGA Device Primitive e EE 220 Generating Primitives Through Attributes see ener espina tene ses sa ee un ano ne Uia nen EUR naa Eua 220 Primutives and Black Boxes rette ios ster DEVE EEN SE Cea UP ER e VEU SEN 221 VHDL and Verilog Xilinx Device Primitives Libraries ccccccccccecessseeeeeeeeennsteseeeeeeeneneaeeeees 221 VHDL Xilinx Device Primitives Device Libraries esee mener 221 Verilog Xilinx Device Primitives Device Libraries ssss een eerenererererereee es 221 Primitive Instantiation Guidelines cesses eene e eene ree ren nnne ense nnne 222 Reporting of Instantiated Device Primitives eeeesse eee 222 Primitives Related Constraints eseseseesseseseeeee eene ee een e een e nee ee ee ee re s esee esee en re
68. Chapter i XST Hardware Description Language HDL Coding Techniques 4 Bit Unsigned Up Counter With Synchronous Load With Constant VHDL Coding Example 4 bit Unsigned Up Counter with Synchronous Load with a Constant library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity counters 4 is port C SLOAD in std logic Q out std logic vector 3 downto 0 end counters 4 architecture archi of counters 4 is signal tmp std logic vector 3 downto 0 begin process C begin if C event and C 1 then if SLOAD 1 then tmp 1010 else tmp lt tmp 1 end if end if end process Q lt tmp end archi 4 Bit Unsigned Up Counter With Synchronous Load With Constant Verilog Coding Example 4 bit Unsigned Up Counter with Synchronous Load with a Constant Ve module v_counters_4 C SLOAD Q input C SLOAD output 3 0 Q reg 3 0 tmp always posedge C begin if SLOAD tmp lt 4 D1010 else tmp lt tmp 1 bl end assign Q tmp endmodule 4 Bit Unsigned Up Counter With Asynchronous Reset and Clock Enable Diagram CE Cc p CLR XST User Guide 42 www xilinx com UG627 v 11 3 September 16 2009 hapter 1 XST Hardware Description Language HDL Coding Techniques XILINX 4 Bit Unsigned Up Counter With Asynchronous Reset and Clock Enable Pin Descriptions gp Beseription S Positive Edge Clock Asynchronous Reset Active High
69. Clock Serial In and Serial Out Verilog Coding Example 16 bit dynamic shift register module v dynamic shift registers 1 Q CE CLK D A input CLK D CE input 3 0 A output OQ reg 15 0 data assign Q data A always posedge CLK begin if CE 1 b1 data lt data 14 0 D end endmodule XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 67 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Multiplexers Hardware Description Language HDL Coding Techniques XST supports different description styles for multiplexers MUXs such as I Then Else or Case If you describe a MUX using a Case statement and you do not specify all values of the selector the result may be latches instead of a multiplexer When writing MUXs you can use don t care to describe selector values XST decides whether to infer the MUXs during the Macro Inference step If the MUX has several inputs that are the same XST can decide not to infer it You can use the MUX_EXTRACT constraint to force XST to infer the MUX Verilog Case statements can be fullornot full e parallel ornot parallel A Verilog Case statement is e full if all possible branches are specified e parallel if it does not contain branches that can be executed simultaneously Multiplexers Full and Parallel Case Statement Coding Example module full sel il i2 i3 i4 o1 input 1 0 sel input
70. Clock Enable Data Output 4 Bit Unsigned Up Counter With Asynchronous Reset and Clock Enable VHDL Coding Example 4 bit Unsigned Up Counter with Asynchronous Reset and Clock Enable library ieee use ieee std_logic_1164 all use ieee std logic unsigned all entity counters 5 is port C CLR CE in std logic Q out std logic vector 3 downto 0 end counters 5 architecture archi of counters 5 is signal tmp std logic vector 3 downto 0 begin process C CLR begin if CLR 1 then tmp 0000 elsif C event and C 1 then if CE 1 then tmp lt tmp 1 end if end if end process Q lt tmp end archi 4 Bit Unsigned Up Counter With Asynchronous Reset and Clock Enable Verilog Coding Example 4 bit Unsigned Up Counter with Asynchronous Reset and Clock Enable module v_counters_5 C CLR CE Q input C CLR CE output 3 0 Q reg 3 0 tmp always posedge C or posedge CLR begin if CLR tmp lt 4 b0000 else if CE tmp lt tmp 1 bl end assign Q tmp endmodule XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 43 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques 4 Bit Unsigned Up Down Counter With Asynchronous Reset Diagram 4 Bit Unsigned Up Down Counter With Asynchronous Reset Pin Descriptions C Positive Edge Clock CLR Asynchronous Reset Active High UP DOWN Up Down Count Mode Selector 4
71. Constraint Command Command Name Value Target Verilog Target XCF Target Line Value yes no default no Safe Recovery string signal signal net in model N A N A State yes Logical Shifter Extraction Shift Register Extraction Signal Encoding Slice Utilization Ratio Slice Utilization Ratio Delta Translate Off Translate On Convert Tristates to Logic Use Carry Chain auto one hot user integer range 1 to 100 integer range 1 to 100 integer integer range 0 to 100 integer range 0 to 100 integer yes no yes no shift extract entity module model signal signal net in model entity module model signal signal net in model entity module model signal signal net in model local local N A entity modulesignal entity shreg extract signal _encoding slice _utilization _ratio slice _utilization _ratio _maxmargin module signal signal net in model no default yes yes no default yes auto one hot user default auto integer range 1 to 100 integer range 1 to 100 integer default 100 integer range 0 to 100 integer range 0 to 100 integer default 0 yes no default yes yes no default yes 258 www xilinx com XST User Guide UG627 v 11 3 September 16 2009 nuit XST Design Constraints XILINX g Constraint VHDL Constraint Command Command Name Value Target
72. Dep UTILIZATION RATIO e Keep KEEP Adders Subtractors and Adders Subtractors Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip Unsigned 8 Bit Adder Diagram Unsigned 8 Bit Adder Pin Descriptions IO Pins Dome Been OOOO SUM Add Result XST User Guide 88 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX Unsigned 8 Bit Adder VHDL Coding Example Unsigned 8 bit Adder library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity adders 1 is port A B in std logic vector 7 downto 0 SUM out std logic vector 7 downto 0 end adders 1 architecture archi of adders 1 is begin SUM lt A B end archi Unsigned 8 Bit Adder Verilog Coding Example Unsigned 8 bit Adder module v_adders_1 A B SUM input 7 0 A input 7 0 B output 7 0 SUM assign SUM A B endmodule Unsigned 8 Bit Adder With Carry In Diagram SUM x10550 Unsigned 8 Bit Adder With Carry In Pin Descriptions IO Pins EC XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 89 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Unsigned 8 Bit Adder With Carry In VHDL Coding Example Unsigned 8 bit Adder with Carry In library ieee use i
73. Description Language HDL Coding Techniques XILINX Shift Registers Log File XST recognizes shift registers in the Low Level Optimization step The XST log file reports the size of recognized shift registers Synthesizing Unit lt shift_registers_1 gt Related source file is shift registers l vhd Found 8 bit register for signal tmp Summary inferred 8 D type flip flop s Unit shift registers 1 synthesized Advanced HDL Synthesis Report Macro Statistics Registers 8 Flip Flops 8 Processing Unit shift registers 1 Found 8 bit shift register for signal tmp 7 Unit shift registers 1 processed Final Register Report Macro Statistics Shift Registers 1 8 bit shift register 1 Shift Registers Related Constraints Shift Register Extraction SHREG EXTRACT Shift Registers Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip 8 Bit Shift Left Register With Positive Edge Clock Serial In and Serial Out Diagram SI SAL SO XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 53 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques 8 Bit Shift Left Register With Positive Edge Clock Serial In and Serial Out Pin Descriptions gp Desripon Positive Edge Clock Serial In Serial Output 8 Bit Shift Left Register With Positive
74. EEN 403 Behavioral e 404 Variable Part Selects Joe een dius Neger ee Lea cete se oce vos Fe gov esee do DEENEN DESEN Heel 404 otr ctural Verilog TEE 404 Verilog icut cM 406 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 13 XILINX Verilog Parameter and Attribute Conflicts 0 cee cee ienten Eent i E E EE EEEE EEEE ENEE 407 Verilog Parameter and Attribute Conflicts Precedence sssssseses eee 407 Verilog Limitations in EE 408 KEE EE 408 XST Support for Verilog Case Sensitivity ecce et rero ete eno ss ines nee ELE ERES eR a ERR 408 Verilog Restrictions Within XT 408 Verilog Blocking and Nonblocking Assignments sess 409 Verilog Integer Handling ert ore tenere terne eere ritos eo suvdaeceatsesdsonsstunacadeedandinnbesnoeton 409 Integer Handling in Verilog Case Statements eee 409 Integer Handling in Verilog Concatenations eene 409 Verilog Attributes and Meta Comments 410 RE el EE 410 Verilog Meta Comments 0 0 004sdtiacseescerssenneceacnsnnsdepilcnebsvenseens aie ENEE EES AEN M 410 Verilog Constructs Supported in XT 411 Verilog Constants Supported in SET ccses cess cones sscg cvs isses serae nna t eee ead ee e sends Ee HE IRSE EE eeng 411 Verilog Data Types Supported in XST scscictssscvcvescsencsens ae nha EES anoo nee ene EEN one ENEE NEEN 411 Verilog Continuous Assignments Supported in
75. Edge Clock Serial In and Serial Out VHDL Coding Example 8 bit Shift Left Register with Positive Edge Clock Serial In and Serial Out library ieee use ieee std logic 1164 a11 entity shift registers 1 is port C SI in std logic SO out std logic end shift registers 1 architecture archi of shift registers 1 is signal tmp std logic vector 7 downto 0 begin process C begin if C event and C 1 then for i in 0 to 6 loop tmp i 1 lt tmp i end loop tmp 0 lt SI end if end process SO lt tmp 7 end archi 8 Bit Shift Left Register With Positive Edge Clock Serial In and Serial Out Verilog Coding Example 8 bit Shift Left Register with Positive Edge Clock Serial In and Serial Out module v shift registers 1 C SI SO input C SI output SO reg 7 0 tmp always posedge C begin tmp tmp 6 0 SI end assign SO tmp 7 endmodule XST User Guide 54 www xilinx com UG627 v 11 3 September 16 2009 nuit XST Hardware Description Language HDL Coding Techniques XILINX 8 Bit Shift Left Register With Negative Edge Clock Clock Enable Serial In and Serial Out Diagram SI SAI so CE c O gt 8 Bit Shift Left Register With Negative Edge Clock Clock Enable Serial In and Serial Out Pin Descriptions Negative Edge Clock Clock Enable Active High Serial Output 8 Bit Shift Left Register With Negative Edge Clock Clock Enable Seria
76. Example Declare as follows attribute rom extract string Specify as follows attribute rom extract of signal name entity name signal entity is yes no ROM EXTRACT ROM Extraction Verilog Syntax Example Place immediately before the module or signal declaration rom extract yes no zi ROM EXTRACT ROM Extraction XST Constraint File XCF Syntax Example One MODEL entity name rom extract yes no true false ROM EXTRACT ROM Extraction XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name NET signal name rom extract yes no true false END ROM EXTRACT ROM Extraction XST Command Line Syntax Example Define in the XST command line as follows xst run rom extract yes no The default is yes XST User Guide 330 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST Design Constraints XILINX ROM_EXTRACT ROM Extraction ISE Design Suite Syntax Example Define in ISE Design Suite with Process gt Properties gt HDL Options gt ROM Extraction ROM_STYLE ROM Style ROM STYLE ROM Style controls the way the macrogenerator implements the inferred ROM macros ROM Extraction ROM EXTRACT must be set to yes in order to use ROM STYLE ROM STYLE values are e auto default e block The default is auto XST looks for the best implementation for each inferred ROM The implementation style can be manually forced to use block ROM or distrib
77. Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip 4 Bit Unsigned Up Accumulator With Asynchronous Reset Diagram XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 49 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques 4 Bit Unsigned Up Accumulator With Asynchronous Reset Pin Descriptions gp Beseription S Positive Edge Clock Asynchronous Reset Active High Data Input Data Output 4 Bit Unsigned Up Accumulator With Asynchronous Reset VHDL Coding Example 4 bit Unsigned Up Accumulator with Asynchronous Reset library ieee use ieee std_logic_1164 all use ieee std logic unsigned all entity accumulators l is port C CLR in std logic D in std logic vector 3 downto 0 Q out std logic vector 3 downto 0 end accumulators 1 architecture archi of accumulators 1 is signal tmp std logic vector 3 downto 0 begin process C CLR begin if CLR 1 then tmp 0000 elsif C event and C 1 then tmp lt tmp D end if end process Q lt tmp end archi 4 Bit Unsigned Up Accumulator With Asynchronous Reset Verilog Coding Example 4 bit Unsigned Up Accumulator with Asynchronous Reset module v accumulators 1 C CLR D Q input C CLR input 3 0 B output 3 0 Q reg 3 0 tmp always 8 posedge C or posedge CL
78. FPGA Optimization XILINX Using PCI Flow With XST To satisfy placement constraints and meet timing requirements when using PCI flow with XST e For VHDL ensure that the names in the generated netlist are all in UPPER case The default case is lower Specify the case in ISE Design Suite in Process gt Properties gt Synthesis Options gt Case For Verilog ensure that Case is set to maintain The default case is maintain Specify the case in ISE Design Suite in Process Properties Synthesis Options Case e Preserve the hierarchy of the design Specify the Keep Hierarchy KEEP_HIERARCHY setting in ISE Design Suite in Process gt Properties gt Synthesis Options gt Keep Hierarchy e Preserve equivalent flip flops XST removes equivalent flip flops by default Specify the Equivalent Register Removal EQUIVALENT_REGISTER_REMOVAL setting in ISE Design Suite in Process gt Properties gt Xilinx Specific Options gt Equivalent Register Removal Preventing Logic and Flip Flop Replication To prevent logic and flip flop replication caused by a high fanout flip flop set reset signal e Seta high maximum fanout value for the entire design in ISE Design Suite in Process gt Properties gt Synthesis Options gt Max Fanout or e Use Max Fanout MAX_FANOUT to set a high maximum fanout value for the initialization signal connected to the RST port of PCI core for example max_fanout 2048 Disabling Re
79. FPGA devices Does not apply to CPLD devices USE CARRY CHAIN Use Carry Chain Applicable Elements Applies to the entire design or to signals USE CARRY CHAIN Use Carry Chain Propagation Rules Applies to the signal to which it is attached USE CARRY CHAIN Use Carry Chain Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it USE CARRY CHAIN Use Carry Chain Schematic Syntax Example e Attach to a valid instance e Attribute Name USE CARRY CHAIN e Attribute Values yes 22 no USE CARRY CHAIN Use Carry Chain VHDL Syntax Example Declare as follows attribute use carry chain string XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 339 XILINX nuit t XST Design Constraints Specify as follows attribute use_carry_chain of signal_name signal is yes no USE_CARRY_CHAIN Use Carry Chain Verilog Syntax Example Place immediately before the signal declaration use carry chain yes no zi USE CARRY CHAIN Use Carry Chain XST Constraint File XCF Syntax Example One MODEL entity name use carry chain yes no true falseJX USE CARRY CHAIN Use Carry Chain XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name NET signal name use carry chain yes no true false END USE CARRY CHAIN Use Carry Chain XST Command Line Syntax
80. For more information see Multipliers Hardware Description Language HDL Coding Techniques and Accumulators Hardware Description Language HDL Coding Techniques Macro implementation on DSP48 blocks is controlled by the Use DSP48 USE DSP48 constraint or command line option with default value of auto In auto mode XST implements multiply accumulate taking into account available DSP48 resources in the device In auto mode use DSP Utilization Ratio DS5P UTILIZATION RATIO to control DSP48 resources XST tries to utilize as many DSP48 resources as possible For more information see DSP48 Block Resources XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 117 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques To deliver the best performance XST by default tries to infer and implement the maximum macro configuration including as many registers in the DSP48 as possible To shape a macro in a specific way use the Keep KEEP constraint For example to exclude the first register stage from the DSP48 place Keep KEEP constraints on the outputs of these registers In the log file XST reports the details of inferred multipliers accumulators and registers at the HDL Synthesis step The composition of multiply accumulate macros happens at Advanced HDL Synthesis step Multiply Accumulate Log File In the log file XST reports the details of inferred multipliers accumulators and registers at
81. ISE Design Suite the name of the project is the name of the top level block In creating a default LSO file ISE Design Suite places the DEFAULT SEARCH ORDER keyword in the first line of the file XST User Guide 442 www xilinx com UG627 v 11 3 September 16 2009 iii ti XST Mixed Language Support XILINX Specifying the Library Search Order LSO File in the Command Line Library Search Order LSO 1so specifies the Library Search Order LSO file when using XST from the command line If the 1so option is omitted XST automatically uses the default library search order without using an LSO file Library Search Order LSO Rules When processing a mixed language project XST obeys the following search order rules depending on the contents of the Library Search Order LSO file e Library Search Order LSO Empty es DEFAULT SEARCH ORDER Keyword Only e DEFAULT SEARCH ORDER Keyword and List of Libraries e List of Libraries Only e DEFAULT SEARCH ORDER Keyword and Non Existent Library Name Library Search Order LSO Empty When the Library Search Order LSO file is empty XST Issues a warning stating that the LSO file is empty e Searches the files specified in the project file using the default library search order e Updates the LSO file by adding the list of libraries in the order that they appear in the project file DEFAULT SEARCH ORDER Keyword Only When the Library Search Order LSO file contains only the DEFA
82. In this case the result is assigned to the signal on the left side Simple Signal Assignment VHDL Coding Example T A and B XST User Guide 382 www xilinx com UG627 v 11 3 September 16 2009 hipter XST VHDL Language Support XILINX MUX Description Using Selected Signal Assignment VHDL Coding Example library IEEE use IEEE std_logic_1164 all entity select_bhv is generic width integer 8 port a b c d in std logic vector width 1 downto 0 selector in std logic vector 1 downto 0 T out std logic vector width 1 downto 0 end select bhv architecture bhv of select bhv is begin with selector select T lt a when 00 b when 01 c when 10 d when others end bhv MUX Description Using Conditional Signal Assignment VHDL Coding Example entity when ent is generic width integer 8 port a b c d in std logic vector width 1 downto 0 selector in std logic vector 1 downto 0 T out std logic vector width 1 downto 0 end when ent architecture bhv of when ent is begin T lt a when selector 00 else b when selector 01 else c when selector 10 else d end bhv VHDL Generate Statements Repetitive structures are declared with the generate VHDL statement For this purpose for I in 1 to N generate means that the bit slice description is repeated N times 8 Bit Adder Described With For Generate Statement VHDL Coding Example
83. Indexed vector part selects Multi dimensional arrays Arrays of net and real data types Array bit and part selects Signed reg net and port declarations Signed based integer numbers Signed arithmetic expressions Arithmetic shift operators Automatic width extension past 32 bits Power operator N sized parameters Explicit in line parameter passing Fixed local parameters Enhanced conditional compilation File and line compiler directives Variable part selects Recursive Tasks and Functions Constant Functions XST Verilog Language Support 416 www xilinx com XST User Guide UG627 v 11 3 September 16 2009 XILINX Chapter 9 XST Behavioral Verilog Language Support This chapter describes XST support for Behavioral Verilog and includes e Behavioral Verilog Variable Declarations Behavioral Verilog Initial Values e Behavioral Verilog Local Reset e Behavioral Verilog Arrays e Behavioral Verilog Multi Dimensional Arrays e Behavioral Verilog Data Types e Behavioral Verilog Legal Statements e Behavioral Verilog Expressions e Behavioral Verilog Blocks e Behavioral Verilog Modules e Behavioral Verilog Module Declarations e Behavioral Verilog Continuous Assignments e Behavioral Verilog Procedural Assignments e Behavioral Verilog Constants e Behavioral Verilog Macros e Behavioral Verilog Include Files e Behavioral Verilog Comments e Behavioral Verilog Generate Statements Behavioral Verilog Vari
84. LOGICAL Cell Usage OTHER Cell Usage BELS Cell Usage The BELS group in the Cell Usage section of the Final Report contains all the logical cells that are basic elements of the targeted FPGA device family for example e LUTs e MUXCY e MUXF5 e MUXF6 e MUXF7 e MUXF8 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 215 XILINX Chapter 4 XST FPGA Optimization Flip Flops and Latches Cell Usage The Flip Flops and Latches group in the Cell Usage section of the Final Report contains all the flip flops and latches that are primitives of the targeted FPGA device family for example e FDR e FDRE e LD RAMS Cell Usage The RAMS group in the Cell Usage section of the Final Report contains all the RAMs SHIFTERS Cell Usage The SHIFTERS group in the Cell Usage section of the Final Report contains all the shift registers that use the Virtex device primitive e TSRL16 e SRL16 1 e SRLI6E SRLI6E 1 e SRLC Tristates Cell Usage The Tristates group in the Cell Usage section of the Final Report contains all the tristate primitives BUFT Clock Buffers Cell Usage The Clock Buffers group in the Cell Usage section of the Final Report contains all the clock buffers e BUFG e BUFGP es BUFGDIL IO Buffers Cell Usage The IO Buffers group in the Cell Usage section of the Final Report contains all the standard I O buffers except the clock buffer s IBUF e OBUF e IOBUF e OBUFT e BUF GI
85. Macro Statistics RAMs 1 64x4 bit registered single port distributed RAM E Pipelined Distributed RAM Related Constraints e RAM Extraction RAM EXTRACT e RAM Style RAM STYLE e ROM Extraction ROM EXTRACT e ROM Style ROM STYLE e BRAM Utilization Ratio BRAM UTILIZATION RATIO e Automatic BRAM Packing AUTO BRAM PACKING XST User Guide 186 www xilinx com UG627 v 11 3 September 16 2009 lhapter 1 XST Hardware Description Language HDL Coding Techniques XILINX Pipelined Distributed RAM Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip Pipelined Distributed RAM Diagram 2o 3 WE DO Block ADDR RAM YV CLK vA Pipelined Distributed RAM Pin Descriptions Positive Edge Clock Synchronous Write Enable Active High Read Write Address Data Input Data Output XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 187 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Pipelined Distributed RAM VHDL Coding Example Pipeline distributed RAMs library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity rams 22 is port clk in std logic we in std logic addr in std logic vector 8 downto 0 di in std logic vector 3 downto 0 do out std logic vector 3 downto 0 end rams 22
86. Multipliers Related Constraints None Sequential Complex Multipliers Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip Signed 18x18 bit Sequential Complex Multiplier Pin Descriptions CES Oper Load Oper_AddSub Control Signals controlling Load and AddSub Operations Signed 18x18 bit Sequential Complex Multiplier VHDL Coding Example Sequential Complex Multiplier library ieee use ieee std logic 1164 al1 use ieee numeric std all entity multipliers 8 is generic A WIDTH positive 18 B WIDTH positive 18 RES WIDTH positive 48 port CLK in std logic A in signed A WIDTH 1 downto 0 B in signed B WIDTH 1 downto 0 Oper Load in std logic Oper AddSub in std logic Oper Load Oper AddSub Operation e 0 0 R A B p ale R A B XST User Guide 102 www xilinx com UG627 v 11 3 September 16 2009 nuit XST Hardware Description Language HDL Coding Techniques XILINX 4 0 R R A B L R R A B RES out signed RES_WIDTH 1 downto 0 i end multipliers_8 architecture beh of multipliers_8 is constant P_WIDTH integer A_WIDTH B_WIDTH signal oper load0 std logic 0 signal oper addsub0 std logic 0 signal pl signed P WIDTH 1 downto 0 others gt 0 signal oper loadl std logic 0 signal oper addsubl std logic 0 signal res0 signed RES
87. Perform anormal Verilog instantiation XST User Guide 440 www xilinx com UG627 v 11 3 September 16 2009 iii ti XST Mixed Language Support XILINX The only VHDL construct that can be instantiated in a Verilog design is a VHDL entity No other VHDL constructs are visible to Verilog code When you do this XST uses the entity architecture pair as the Verilog VHDL boundary XST performs the binding during elaboration During binding XST searches for a Verilog module name using the name of the instantiated module in the user specified list of unified logical libraries in the user specified order XST ignores any architecture name specified in the module instantiation For more information see Library Search Order LSO Files in Mixed Language Projects If found XST binds the name If XST cannot find a Verilog module it treats the name of the instantiated module as a VHDL entity and searches for it using a case sensitive search for a VHDL entity XST searches for the VHDL entity in the user specified list of unified logical libraries in the user specified order assuming that a VHDL design unit was stored with extended identifier For more information see Library Search Order LSO Files in Mixed Language Projects If found XST binds the name XST selects the first VHDL entity matching the name and binds it XST has the following limitations when instantiating a VHDL design unit from a Verilog module e Use explicit port associati
88. Regional Clock Buffers Syntax Example xst run bufr 6 Sets the number or regional clock buffers to 6 OPTIMIZE PRIMITIVES Optimize Instantiated Primitives By default XST does not optimize instantiated primitives in Hardware Description Languages HDLs Use OPTIMIZE PRIMITIVES Optimize Instantiated Primitives to deactivate the default OPTIMIZE PRIMITIVES allows XST to optimize Xilinx library primitives that have been instantiated in an HDL XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 319 XILINX nuit d XST Design Constraints Optimization of instantiated primitives is limited by the following factors e If an instantiated primitive has specific constraints such as RLOC attached XST preserves it as is e Not all primitives are considered by XST for optimization Such hardware elements as MULT18x18 BRAMs and DSP48 are not optimized modified even if optimization of instantiated primitives is enabled OPTIMIZE PRIMITIVES Optimize Instantiated Primitives Architecture Support Applies to all FPGA devices Does not apply to CPLD devices OPTIMIZE PRIMITIVES Optimize Instantiated Primitives Applicable Elements Applies to hierarchical blocks components and instances OPTIMIZE PRIMITIVES Optimize Instantiated Primitives Propagation Rules Applies to the component or instance to which it is attached OPTIMIZE PRIMITIVES Optimize Instantiated Primitives Syntax Examples The following examples
89. Related source file is bram map 1 vhd Found 4 bit register for signal RES Found 4 bit adder for signal n0001 created at line 29 Summary inferred 4 D type flip flop s inferred 1 Adder Subtractor s Unit logic bram 1 synthesized HDL Synthesis Report Macro Statistics Block RAMs 4 256x4 bit single port block RAM L INFO Xst 1789 Unable to map block lt no_logic_bram gt on BRAM Output FF lt RES gt must have a synchronous reset Mapping Logic Onto Block RAM Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip XST User Guide 210 www xilinx com UG627 v 11 3 September 16 2009 Chapter 4 XST FPGA Optimization XILINX 8 Bit Adders With Constant in a Single Block Ram Primitive VHDL Coding Example The following example places 8 bit adders with constant in a single block RAM primitive library ieee use ieee std logic 1164 all use ieee numeric std all entity logic bram 1 is port clk rst in std logic A B in unsigned 3 downto 0 RES out unsigned 3 downto 0 attribute bram map string attribute bram map of logic bram 1 entity is yes end logic bram 1 architecture beh of logic bram 1 is begin process clk begin if clk event and clk 1 then if rst 1 then RES lt 0000 else RES lt A B 0001 end if end if end proces
90. Signal Encoding Architecture Support sss 296 SIGNAL ENCODING Signal Encoding Applicable Elements 296 SIGNAL ENCODING Signal Encoding Propagation Rules sss 296 XST FPGA Constraints Non Timiang i iie er coeno aries an reitera rb eere P ee dede abe d e ERR EE EddEEE ee de duds 296 ASYNC TO SYNC Asynchronous to Gvpnchronous een 298 ASYNC TO SYNC Asynchronous to Synchronous Architecture Support ssssss 298 ASYNC TO SYNC Asynchronous to Synchronous Applicable Elements 298 ASYNC TO SYNC Asynchronous to Synchronous Propagation Rules cccccccceeeeeeeertees 298 AUTO BRAM PACKING Automatic BRAM Dacks 298 AUTO BRAM PACKING Architecture Support 298 AUTO BRAM PACKING Applicable Elements cece erste tere eeeeeererererererneee es 299 AUTO BRAM PACKING Propagation Rules een 299 BRAM UTILIZATION RATIO BRAM Utilization Ratio seseeeeeesseee mee 299 BRAM UTILIZATION RATIO BRAM Utilization Ratio Architecture Support 299 BRAM UTILIZATION RATIO BRAM Utilization Ratio Applicable Elements 299 BRAM UTILIZATION RATIO BRAM Utilization Ratio Propagation Rules 299 B FBEBR TYPE Buffer Type EE 300 BUFFER TYPE Buffer Type Architecture Support sssssss He 300 BUFFER TYPE Buffer Type Applicable Elements 300 BUFFER TYPE Buffer Type Propagation Rules eee eenerere
91. Support Architecture independent KEEP_HIERARCHY Keep Hierarchy Applicable Elements Applies to logical blocks including blocks of hierarchy or symbols KEEP_HIERARCHY Keep Hierarchy Propagation Rules Applies to the entity or module to which it is attached XST User Guide 274 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST Design Constraints XILINX KEEP_HIERARCHY Keep Hierarchy Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it KEEP_HIERARCHY Keep Hierarchy Schematic Syntax Example e Attach to the entity or module symbol e Attribute Name KEEP HIERARCHY e Attribute Values YES NO KEEP HIERARCHY Keep Hierarchy VHDL Syntax Example Declare as follows attribute keep hierarchy string Specify as follows attribute keep hierarchy of architecture name architecture is yes no truel false soft The default is no for FPGA devices The default is yes for CPLD devices KEEP HIERARCHY Keep Hierarchy Verilog Syntax Example Place immediately before the module declaration or instantiation keep hierarchy yes no true false soft KEEP HIERARCHY Keep Hierarchy XST Constraint File XCF Syntax Example MODEL entity name keep hierarchy yes no true false soft KEEP HIERARCHY Keep Hierarchy XST Command Line Syntax Example Define in the XST command line
92. Techniques 8 b00000001 8 b00000010 8 b00000100 8 b00001000 uo n wg tua XST can recognize a priority encoder but in most cases XST does not infer it To force priority encoder inference use Priority Encoder Extraction PRIORITY EXTRACT with the value force Xilinx recommends that you use Priority Encoder Extraction PRIORITY EXTRACT on a signal by signal basis Otherwise Priority Encoder Extraction PRIORITY EXTRACT may give sub optimal results Priority Encoders Log File The XST log file reports the type and size of recognized priority encoders during the Macro Recognition step Synthesizing Unit priority Related source file is priority encoders l vhd Found 3 bit 1 of 9 priority encoder for signal lt code gt Summary inferred 3 Priority encoder s Unit lt priority gt synthesized HDL Synthesis Report Macro Statistics Priority Encoders el 3 bit 1 of 9 priority encoder 1 Priority Encoders Related Constraints Priority Encoder Extraction PRIORITY_EXTRACT Priority Encoders Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 79 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques 3 Bit 1 of 9 Priority Encoder Coding Examples For this example XST may infer a priority encoder Use Prio
93. The ROM lt Mrom__varindex0000 gt will be implemented as a read only BLOCK RAM absorbing the register data ram type Block Port A aspect ratio 64 word x 20 bit 6 9 mode write first ClkA connected to signal lt clk gt rise enA connected to signal en high weA connected to internal node high addrA connected to signal lt addr gt diA connected to internal node doA connected to signal data Advanced HDL Synthesis Report Macro Statistics RAMs SZ 64x20 bit single port block RAM zd ROMs Using Block RAM Resources Related Constraints ROM Style ROM STYLE ROMs Using Block RAM Resources Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip ROM With Registered Output Diagram EN DATA Block ADDR ROM CLK gt x10570 XST User Guide 178 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX ROM With Registered Output Pin Descriptions ppm Desripion S clk Positive Edge Clock en Synchronous Enable Active High Read Address Data Output ROM With Registered Output VHDL Coding Example One ROMs Using Block RAM Resources VHDL code for a ROM with registered output template 1 library ieee use ieee std logic 1164 a11 use ieee std logic unsigned all entity rams 21a is port clk in std l
94. VHDL consists of two parts e The interface defining the I O ports e The body In VHDL e The entity corresponds to the interface e The architecture describes the behavior XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 377 XILINX Chapter 1 XST VHDL Language Support VHDL Entity Declarations The I O ports of the circuit are declared in the entity Each port has A name e A mode in out inout or buffer e lt A type ports A B C D Ein the Entity and Architecture Declaration VHDL Coding Example Types of ports must be constrained Not more than one dimensional array types are accepted as ports VHDL Architecture Declarations Internal signals may be declared in the architecture Each internal signal has A name e A type signal T in the Entity and Architecture Declaration VHDL Coding Example Entity and Architecture Declaration VHDL Coding Example Library IEEE use IEEE std logic 1164 all entity EXAMPLE is port A B C t in std logic D E out std logic end EXAMPLE architecture ARCHI of EXAMPLE is signal T std logic begin ead ARCHI VHDL Component Instantiation Structural descriptions assemble several blocks and allow the introduction of hierarchy in a design The basic concepts of hardware structure are e Component The component is the building or basic block e Port A port is a component I O connector Signal A signal corresponds to a wire between components
95. Verilog Target XCF Target Line Value BoxType primitive entity module model N black_box inst inst inst in model user_black_box A Map Logicon yes entity module model N A BRAM ns Buffer Type bufgdll signal signal net in model N A N A ibufg bufg bufgp ibuf bufr none XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 253 XILINX Chapte XST Design Constraints Constraint VHDL Constraint Command Command Name Value Target Verilog Target XCF Target Line Value Clock Signal primary clock signal Clock Signal Decoder Extraction Enumerated Encoding Equivalent Register Removal FSM Encoding Algorithm Automatic FSM Extraction FSM Style Pack I O Registers Into IOBs primary clock signal clock signal entity signal string containing space separated binary codes auto one hot compact sequential gray johnson speed1 user module signal module signal signal instance instance net in model clock signal net in model model net in model net in model model net in model model net in model model net in model model net in model net in model inst in model decoder _extract equivalent _tegister _removal fsm _encoding fsm extract fsm _style mo no default no yes no default yes yes no default yes auto one hot compact sequential g
96. WIDTH if we 0 diO di DI WIDTH 1 0 else diO RAM addr DI_WIDTH 1 0 end always posedge clk begin RAM addr lt dil di0 do lt RAM addr end To simplify the understanding of byte wide write enable templates the following coding examples use single port block RAMs XST supports dual port Block RAM as well as byte wide write enable XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 157 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Read First Mode Single Port BRAM with Byte wide Write Enable 2 Bytes Pin Descriptions ppm Desripon clk Positive Edge Clock e Write Enable Write Read Address Data Input RAM Output Port Read First Mode Single Port BRAM With Byte Wide Write Enable 2 Bytes VHDL Coding Example Single Port BRAM with Byte wide Write Enable 2 bytes in Read First Mode library ieee use ieee std_logic_1164 all use ieee std logic unsigned all entity rams 24 is generic SIZE integer 512 ADDR WIDTH integer 9 DI WIDTH integer 8 port clk in std logic we in std logic vector 1 downto 0 addr in std logic vector ADDR WIDTH 1 downto 0 di in std logic vector 2 DI WIDTH 1 downto 0 do out std logic vector 2 DI WIDTH 1 downto 0 end rams 24 architecture syn of rams 24 is type ram type is array SIZE 1 downto 0 of std logic vector 2 DI WIDTH 1 downto 0 Signal RAM ram type
97. WIDTH 1 downto 0 begin process clk variable acc signed RES WIDTH 1 downto 0 begin if rising edge clk then oper loadO lt Oper Load oper addsub0 lt Oper AddSub pl lt A B oper_loadl lt oper load0 oper addsubl lt oper addsub0 if oper loadl 1 then acc res0 else acc others 0 end if if oper addsubl 1 then res0 lt acc pl else resQ lt acctpl end if end if end process RES lt Test end architecture XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 103 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Signed 18x18 bit Sequential Complex Multiplier Verilog Coding Example module v multipliers 8 CLK A B Oper Load Oper AddSub RES parameter A WIDTH 18 parameter B WIDTH 18 parameter RES WIDTH 48 parameter P WIDTH A WIDTH B WIDTH input CLK input signed A WIDTH 1 0 A B input Oper Load Oper AddSub Oper Load Oper AddSub Operation 0 0 R A B 0 1 R A B 1 0 R R A B Hf 2 1 R R A B output RES WIDTH 1 0 RES reg oper loadO0 reg oper addsubO0 0 0 reg signed P WIDTH 1 0 pl 0 reg oper loadl 0 reg oper_addsubl 0 reg signed RES WIDTH 1 0 res0 0 reg signed RES WIDTH 1 0 acc always posedge CLK begin oper load0 lt Oper Load oper addsub0 lt Oper AddSub pl lt A B oper loadl lt oper load0 oper addsubl lt oper addsub0
98. Work Directory Example User Two Mapping file schlib z sharedlibs shlib 1lib12 z userlibs lib12 xsthdpdir Work Directory Example User Three Mapping file schlib z sharedlibs shlib User Three will also set XSTHDPDIR c temp xsthdpdir Work Directory Architecture Support Architecture independent xsthdpdir Work Directory Applicable Elements Applies to directories XST User Guide 284 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST Design Constraints XILINX xsthdpdir Work Directory Propagation Rules Not applicable xsthdpdir Work Directory Syntax Examples xsthdpdir Work Directory XST Command Line Syntax Example Define Work Directory globally with the set xsthdpdir command line option before running the run command set xsthdpdir directory Work Directory can accept a single path only You must specify the directory There is no default xsthdpdir Work Directory ISE Design Suite Syntax Example Define in ISE Design Suite with Process Properties Synthesis Options VHDL Work Directory To view Work Directory select Edit Preferences Processes Property Display Level Advanced XST Hardware Description Language HDL Constraints This section describes Hardware Description Language HDL design constraints that can be used with XST e Automatic FSM Extraction F5M EXTRACT e Enumerated Encoding ENUM_ENCODING e Equivalent Register Removal
99. XST Equivalent Recognition Available For Synplicity rom_extract and VHDL Verilog rom_style Synplicity VHDL Verilog Synplicity Automatic FSM VHDL Verilog Extraction syn_romstyle syn_sharing syn_state_machine syn_tco lt n gt Synplicity syn_tpd lt n gt Synplicity syn_tristate Synplicity syn_tristatetomux Synplicity syn_tsu lt n gt Synplicity Ni A A A A A A A A A A syn_useenables syn_useioff synthesis translate_off Synplicity Synopsys Translate Off VHDL Verilog synthesis translate_on Synplicity i I O Registers Into S xc alias xc clockbuftype xc fast xc fast auto xc global buffers xc ioff i VHDL Verilog VHDL Verilog VHDL Verilog VHDL Verilog xc isgsr xc loc LOC Synplicity Synplicity i I O Registers Into S xc map Synplicity LUT MAP Yes XST supports VHDL Verilog only the value lut for automatic recognition xc nodelay xc padtype xc props xc pullup xc rloc A A A A A A A A A A xc_fast A xc_slow xc_uset XST User Guide 362 www xilinx com UG627 v 11 3 September 16 2009 nuit XST Design Constraints Third Party Constraints Syntax Examples This section contains the following third party constraints syntax examples e Third Party Constraints Verilog Syntax Example e Third Party Constraints XST Constraint File XCF Syntax Example Third Party Constraints Verilog Syntax Exampl
100. additional comments in the script file run option_1 value option_2 value option_3 value XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 477 XILINX int 13 XST Command Line Mode Observe the following rules e The first line contains only the run command without any options There are no blank lines in the middle of the command e Each option name begins with dash For example ifn ifmt ofn e Bach option has one value There are no options without a value The value for a given option can be one of the following Predefined by XST for instance yes or no Any string for instance a file name or a name of the top level entity Options such as v1gincdir accept several directories as values Separate the directories by spaces and enclose them in braces vlgincdir c Nvlgl c vlg2 For more information see Names With Spaces in Command Line Mode An integer XST Specific Non Timing Options and XST Specific Non Timing Options XST Command Line Only summarize XST specific non timing related options including run command options and their values XST provides online Help from the UNIX command line The following information is available by typing help at the command line The XST help function provides a list of supported families available commands options and their values for each supported device family To see a detailed explanation of an XST command use the followin
101. as follows keep hierarchy yes no soft The default is no for FPGA devices The default is yes for CPLD devices For more information see XST Command Line Mode KEEP HIERARCHY Keep Hierarchy ISE Design Suite Syntax Example Define in ISE Design Suite with Process Properties Synthesis Options Keep Hierarchy Iso Library Search Order 1so Library Search Order specifies the location of the library search order file For more information about the LSO file see Library Search Order LSO Files in Mixed Language Projects To specify the library search order file in ISE Design Suite 1 Select Process gt Properties gt Synthesis Options 2 From the Property display level list select Advanced 3 Set the Library Search Order property Iso Library Search Order Architecture Support Architecture independent XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 275 XILINX nuit t XST Design Constraints Iso Library Search Order Applicable Elements Applies to files lso Library Search Order Propagation Rules Not applicable Iso Library Search Order Syntax lso file name lso There is no default file name If not specified XST uses the default search order Iso Library Search Order Syntax Example xst elaborate lso c data my libraries my lso Specifies c data my libraries my 1so as the file that sets your library search order LOC The LOC constraint defines whe
102. bit mode write first ClkB connected to signal clkb enB connected to signal enb weB connected to internal web addrB connected to signal addrb diB connected to internal dib doB connected to signal dob optimization speed Unit rams 16 synthesized advanced Advanced HDL Synthesis Report Macro Statistics RAMs 1 64x16 bit dual port block RAM 1 128 www xilinx com XST User Guide UG627 v 11 3 September 16 2009 lhapter 3 XST Hardware Description Language HDL Coding Techniques XILINX RAMs and ROMs Related Constraints e BRAM Utilization Ratio BRAM_UTILIZATION_RATIO e Automatic BRAM Packing AUTO_BRAM_PACKING e RAM Extraction RAM EXTRACT e RAM Style RAM STYLE e ROM Extraction ROM EXTRACT e ROM Style ROM STYLE XST accepts LOC and RLOC constraints on inferred RAMs that can be implemented in a single block RAM primitive The LOC and RLOC constraints are propagated to the NGC netlist RAMs and ROMs Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip Block RAM resources in the following devices offer different read write synchronization modes e Virtex amp 4 e Virtex 5 e Spartan 3 e Spartan 3E e Spartan 3A The following coding examples describe a single port block RAM You can deduce descriptions of dual port block RAMs from th
103. blocks the statements are executed in the order listed Block statements are designated by begin and end keywords XST does not support parallel blocks Behavioral Verilog Modules In Verilog a design component is represented by a module The connections between components are specified within module instantiation statements Such a statement specifies an instance of a module Each module instantiation statement has a name instance name In addition to the name a module instantiation statement contains an association list that specifies which actual nets or ports are associated with which local ports formals of the module declaration All procedural statements occur in blocks that are defined inside modules The two kinds of procedural blocks are e Initial block e Always block XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 423 XILINX Chapter 1 XST Behavioral Verilog Language Support Within each block Verilog uses a begin and end to enclose the statements Since initial blocks are ignored during synthesis only always blocks are discussed Always blocks usually take the following format always begin statement end Each statement is a procedural assignment line terminated by a semicolon Behavioral Verilog Module Declarations The I O ports of the circuit are declared in the module declaration Each port has A name A mode in out inout The input and output ports defined in th
104. can include a synchronously controlled initialization of the RAM data outputs Block RAM with the following synchronization modes can have re settable data ports e Read First Block RAM with Reset e Write First Block RAM with Reset e No Change Block RAM with Reset e Registered ROM with Reset e Supported Dual Port Templates Because XST does not support block RAMs with dual write in a dual read block RAM description both data outputs may be reset but the various read write synchronizations are allowed for the primary data output only The dual output may be used in Read First Mode only Block RAM With Reset Pin Descriptions Dom Beim B m9Mow XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 165 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Block RAM With Reset VHDL Coding Example Block RAM with Reset library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity rams 18 is port clk in std logic en in std logic we in std logic rst 1 in Std logic addr in std logic vector 5 downto 0 di in std logic vector 15 downto 0 do out std logic vector 15 downto 0 end rams 18 architecture syn of rams 18 is type ram type is array 63 downto 0 of std logic vector 15 downto 0 signal ram ram type begin process clk begin if clk event and clk 1 then if en 1 then optional enable if we 1 then
105. can make large Finite State Machine FSM components more compact and faster by implementing them in the block RAM resources provided in Virtex devices and later technologies Use FSM_STYLE to direct XST to use block RAM resources rather than LUTs default to implement FSMs FSM_STYLE is both a global and a local constraint FSM_STYLE FSM Style Architecture Support Applies to all FPGA devices Does not apply to CPLD devices FSM_STYLE FSM Style Applicable Elements Applies to the entire design or to an entity component module or signal FSM_STYLE FSM Style Propagation Rules Applies to the entity component module or signal to which it is attached FSM_STYLE FSM Style Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it FSM_STYLE FSM Style VHDL Syntax Example Declare as follows attribute fsm_style string Declare as follows attribute fsm_style of entity_name signal_name entity signal is lut bram The default is Lut FSM_STYLE FSM Style Verilog Syntax Example Place immediately before the module or signal declaration fsm style lut bram FSM_STYLE FSM Style XST Constraint File XCF Syntax Example One MODEL entity name fsm style lut bram FSM STYLE FSM Style XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name NET signal n
106. component SINGLE SRL is generic SRL WIDTH integer 16 port elk in std logico inp in std logic outp out std logic end component begin inst1l SINGLE SRL generic map SRL WIDTH gt 13 port map clk gt clk inp gt inpl outp gt outpl inst2 SINGLE_SRL generic map SRL_WIDTH gt 18 port map cik gt clk inp gt inp2 outp gt outp2 end beh XST User Guide 394 www xilinx com UG627 v 11 3 September 16 2009 hipter XST VHDL Language Support XILINX SINGLE_SRL Describing a Shift Register VHDL Error Message If you run the SINGLE_SRL Describing a Shift Register VHDL Coding Example XST issues the following error message Analyzing Entity lt top gt Architecture lt beh gt Entity lt top gt analyzed Unit lt top gt generated Analyzing generic Entity single srl Architecture lt beh gt SRL WIDTH 13 Entity single srl analyzed Unit single srl generated Analyzing generic Entity single srl Architecture lt beh gt SRL WIDTH 18 ERROR Xst assert l vhd line 15 FAILURE The size of Shift Register exceeds the size of a single SRL Using Packages to Define VHDL Models VHDL models may be defined using packages Packages contain e Type and subtype declarations e Constant definitions e Function and procedure definitions e Component declarations Using packages to define VHDL models provides the ability to change parameters an
107. conv integer read a end syn Single Port RAM With Synchronous Read Read Through Verilog Coding Example Single Port RAM with Synchronous Read Read Through ff module v rams 07 clk we a di do input clk input we input 5 0 a input 15 0 di output 15 0 do reg 15 20 ram 6320 reg 5 0 read a always posedge clk begin if we ram a lt di read a lt a end assign do ram read a endmodule XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 139 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Single Port RAM With Enable Diagram A DO EN WE Block RAM D CLK p Single Port RAM With Enable Pin Descriptions 10 Pins J JjBesrpio Cd clk Positive Edge Clock Deier SSC Single Port RAM With Enable VHDL Coding Example Single Port RAM with Enable library ieee use ieee std_logic_1164 all use ieee std logic unsigned all entity rams 08 is port clk in std logic en in std logic we in std logic a in std logic vector 5 downto 0 di in std logic vector 15 downto 0 do out std logic vector 15 downto 0 end rams 08 architecture syn of rams 08 is type ram type is array 63 downto 0 of std logic vector 15 downto 0 signal RAM ram type signal read a std logic vector 5 downto 0 begin process clk begin if clk event and clk 1 then if en
108. cores yes no true false optimize READ CORES Read Cores XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name END INST instance name read cores yes no true false optimize END The default is yes READ CORES Read Cores XST Command Line Syntax Example Define in the XST command line as follows read cores yes no optimize READ CORES Read Cores ISE Design Suite Syntax Example Define in ISE Design Suite with Process Properties Synthesis Options Read Cores The optimize option is not available in ISE Design Suite SHIFT EXTRACT Logical Shifter Extraction SHIFT EXTRACT Logical Shifter Extraction enables or disables logical shifter macro inference SHIFT EXTRACT values are e yes default no e true XCF only e false XCF only XST User Guide 308 www xilinx com UG627 v 11 3 September 16 2009 Chapter t XST Design Constraints XILINX SHIFT_EXTRACT Logical Shifter Extraction Architecture Support Applies to all FPGA devices Does not apply to CPLD devices SHIFT_EXTRACT Logical Shifter Extraction Applicable Elements Applies to the entire design or to design elements and nets SHIFT_EXTRACT Logical Shifter Extraction Propagation Rules Applies to the entity component module or signal to which it is attached SHIFT_EXTRACT Logical Shifter Extraction Syntax Examples The following examples show how to use this constraint with part
109. does not correspond to the data type defined in the VHDL or Verilog code then XST tries to detect the situation and issues a warning ignoring the command line definition In some situations XST may fail to detect a type mismatch In that case XST attempts to apply this value by adopting it to the type defined in the VHDL or Verilog file without any warning Be sure that the value you specified corresponds to the type defined in the VHDL or Verilog code If a defined generic or parameter name does not exist in the design no message is given and the definition is ignored XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 271 XILINX nuit t XST Design Constraints You can also set this value in ISE Design Suite in Process gt Properties gt Synthesis Options gt Generics Parameters generics Generics Architecture Support Architecture independent generics Generics Applicable Elements Applies to the entire design generics Generics Propagation Rules Not applicable generics Generics Syntax xst run generics name value name value name is the name of a generic or parameter of the top level design block value is the value of a generic or parameter of the top level design block The default is an empty definition generics Follow these rules e Place the values inside curly braces e Separate the values with spaces e XST can accept as values only constants of scala
110. e Describes the FPGA primitive support This chapter includes e FPGA Specific Synthesis Options e Macro Generation e DSP48 Block Resources e Mapping Logic Onto Block RAM e Flip Flop Retiming e Partitions e Speed Optimization Under Area Constraint e FPGA Optimization Report e Implementation Constraints e FPGA Primitive Support e Cores Processing e Specifying INIT and RLOC e Using PCI Flow With XST XST performs the following steps during FPGA synthesis and optimization e Mapping and optimization on an entity by entity or module by module basis e Global optimization on the complete design The output is an NGC file This section describes e The constraints that can be applied to fine tune synthesis and optimization e Macro generation The log file e The timing models used during synthesis and optimization e The constraints available for timing driven synthesis e The generated NGC file e Support for primitives XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 203 XILINX Chapter 4 XST FPGA Optimization FPGA Specific Synthesis Options XST supports options to fine tune synthesis in accordance with user constraints For information about each option see XST FPGA Constraints Non Timing The following options relate to the FPGA specific optimization of synthesis e Extract BUFGCE BUFGCE e Cores Search Directories sd e Decoder Extraction DECODER EXTRACT e FSM Style F5M STYLE
111. e Drive strength and delay Ignored e Arrays of primitives Unsupported XST User Guide 414 www xilinx com UG627 v 11 3 September 16 2009 tapter t XST Verilog Language Support XILINX XST does not support Verilog Switch Level primitives such as cmos nmos pmos rcmos rnmos rpmos e rtran rtranifO rtranif1 tran tranifO tranif1 XST does not support Verilog user defined primitives Verilog Reserved Keywords Keywords marked with an asterisk are reserved by Verilog but are not supported by XST always begin case cmos defparam else endfunction endspecify for function highz1 include instance liblist medium nmos notif0 parameter pullo pulsestyle ondetect realtime rnmos rtranif1 small strong1 task tranif1 triand vectored weak1 xnor mee e XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 415 XILINX Verilog 2001 Support in XST XST supports the following Verilog 2001 features For more information see Verilog 2001 A Guide to the New Features by Stuart Sutherland or IEEE Standard Verilog Hardware Description Language manual IEEE Standard 1364 2001 Generate statements Combined port data type declarations ANSI style port lists Module parameter port lists ANSI C style task function declarations Comma separated sensitivity list Combinatorial logic sensitivity Default nets with continuous assigns Disable default net declarations
112. e Obtaining Better Frequency Try 4 The CPU time increases from Try 1 to Try 4 Obtaining Better Frequency Try 1 Select only optimization effort 2 and speed optimization The other options have default values e Optimization effort 2 or High e Optimization Goal Speed Obtaining Better Frequency Try 2 Flatten the user hierarchy In this case optimization has a global view of the design and the depth reduction may be better e Optimization effort 1 Normal or 2 High e Optimization Goal Speed e Keep Hierarchy no Obtaining Better Frequency Try 3 Merge the macros with surrounded logic The design flattening is increased e Optimization effort 1 or Normal e Optimization Goal Speed e Keep Hierarchy no e Macro Preserve no Obtaining Better Frequency Try 4 Apply the equation shaping algorithm Options to be selected e Optimization effort 2 or High e Macro Preserve no e Keep Hierarchy no XST User Guide 238 www xilinx com UG627 v 11 3 September 16 2009 taptir i XST CPLD Optimization XILINX Fitting a Large Design If a design does not fit in the selected device exceeding the number of device macrocells or device P Term capacity you must select an area optimization for XST Statistically the best area results are obtained with the following options e Optimization effort 1 Normal or 2 High e Optimization Goal Area e Default values for other options Another option is wysiwyg yes This optio
113. edge C then Flip Flop With Positive Edge Clock Verilog Coding Example Flip Flop with Positive Edge Clock module v registers 1 C D Q input OC D output OQ reg Q always posedge C begin Q lt Di end endmodule XST User Guide 24 www xilinx com UG627 v 11 3 September 16 2009 nuit XST Hardware Description Language HDL Coding Techniques XILINX Flip Flop With Positive Edge Clock with INITSTATE of the Flop Set Verilog coding example module test d C q input d input C output q reg qtemp bl always posedge C begin qtemp d end assign q qtemp endmodule VHDL coding example library ieee use ieee std_logic_1164 all entity registers 1 is port C D in std logic Q out std logico end registers 1 architecture archi of registers 1 is Signal qtemp std logic 1 begin process C begin if C event and C 1 then qtemp lt D end if Q Qtemp end process end archi Flip Flop With Negative Edge Clock and Asynchronous Reset Diagram Flip Flop With Negative Edge Clock and Asynchronous Reset Pin Descriptions XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 25 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Flip Flop With Negative Edge Clock and Asynchronous Reset VHDL Coding Example Flip Flop with Negative Edge Clock and Asynchronous Reset library ieee us
114. eeu on EE ssh ASER e Pene ehe See 475 XST File Types in Command Line Mode ess ie ennt eet ee eio roni ee ER ERE REI KE e eI EFE Re EE ERE cesesends 475 Temporary Files in Command Line Mode 475 Names With Spaces in Command Line Mode 476 Launching XST in Command Line Mode eee erret eee nte ihnen nie enu NEE EEN ne eue be need ane 476 Launching XST in Command Line Mode Using the XST Shell sssssseeR 476 Launching XST in Command Line Mode Using a Script Pie 476 Setting Up an XST SCPI sespe hiscosndisys co ipeo petes aee adeb der er bome dasa AENEA Eege ese Ei 477 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 15 XILINX Setting Up an XST Script Using the Run Commande 477 Setting Up an XST Script Using the Set Commande 479 Setting Up an XST Script Using the Elaborate Commande 479 Synthesizing VHDL Designs Using Command Line Mode 480 Running XST in Script Mode VHDDL eese eet rer eio ra nn EENS cbvesbavecevevadie cacenasd NEEN 482 Synthesizing Verilog Designs Using Command Line Mode 482 Running XST in Script Mode Verilog cece ee a e eee e ene enne nennen nnns 484 Synthesizing Mixed Designs Using Command Line Mode 484 Running XST in Script Mode Mixed Language sssseessesee ee eene 485 16 XST User Guide www xilinx com UG627 v 11 3 September 16 2009 XILINX Chapter 1 About the XST User Guide The XST User Guide e Describes Xilinx Synthesis
115. either of the following e ise Formats messages for ISE Design Suite e xflow Formats messages for XFLOW Normally XST prints the entire log to stdout In Quiet Mode XST does not print the following portions of the log to stdout e Copyright Message e Table of Contents e Synthesis Options Summary The following portions of the Final Report Final Results header for CPLD devices Final Results section for FPGA devices A note in the Timing Report stating that the timing numbers are only a synthesis estimate Timing Detail CPU XST run time Memory usage The following sections are still available for FPGA devices e Device Utilization Summary e Clock Information e Timing Summary Use Silent Mode Silent Mode prevents any messages from being sent to the computer screen stdout although XST continues to generate the entire log file To invoke Silent Mode set the intstyle command line option to silent Hide Specific Messages To hide specific messages at the HDL or Low Level Synthesis steps set the XIL XST HIDEMESSAGES environment variable to one of the values shown in the following table XIL XST HIDEMESSAGES Environment Variable Values C none default Maximum verbosity All messages are printed out hdl_level Reduce verbosity during VHDL or Verilog Analysis and HDL Basic and Advanced Synthesis hdl_and_low_levels Reduce verbosity at all stages XST User Guide 450 www xilinx com UG627 v 11
116. endmodule Verilog Parameters Verilog modules allow you to define constants known as parameters Parameters can be passed to module instances to define circuits of arbitrary widths Parameters form the basis of creating and using parameterized blocks in a design to achieve hierarchy and stimulate modular design techniques XST User Guide 406 www xilinx com UG627 v 11 3 September 16 2009 tapter t XST Verilog Language Support XILINX Verilog Parameters Coding Example The following Verilog coding example shows the use of parameters Null string parameters are not supported module lpm reg out in en reset clk parameter SIZE 1 input in en reset clk output out wire SIZE 0 in reg SIZE i O0 out always posedge clk or negedge reset begin if reset out lt 1 b0 else if en out lt in else out lt out redundant assignment end endmodule module top portlist left blank intentionally wire 7 0 sys_in sys_out wire sys_en sys_reset sysclk lpm_reg 8 buf_373 sys_out sys_in sys_en sys_reset sysclk endmodule Instantiation of the module Ipm reg with a instantiation width of 8 causes the instance bu 373 to be 8 bits wide The Generics generics command line option allows you to redefine parameters Verilog values defined in the top level design block This allows you to easily modify the design configuration without any Hardware Description Language HDL
117. first operand is a signal or variable and the other operand is a constant equal to 1 A lt A 1 In an accumulator the destination and first operand is a signal or variable and the second operand is either e A signal or variable A A B e A constant not equal to 1 A lt A Constant An inferred accumulator can be up down or updown For an updown accumulator the accumulated data may differ between the up and down mode if updown 1 then a lt a Di else a lt a c XST can infer an accumulator with the same set of control signals available for counters For more information see Counters Hardware Description Language HDL Coding Techniques Accumulators in Virtex 4 Devices and Virtex 5 Devices Virtex 4 devices and Virtex 5 devices enable accumulators to be implemented on DSP48 resources XST can push up to two levels of input registers into DSP48 blocks XST User Guide 48 www xilinx com UG627 v 11 3 September 16 2009 nuit XST Hardware Description Language HDL Coding Techniques XILINX XST can implement an accumulator in a DSP48 block if its implementation requires only a single DSP48 resource If an accumulator macro does not fit in a single DSP48 XST implements the entire macro using slice logic Macro implementation on DSP48 resources is controlled by the Use DSP48 USE_DSP48 constraint or command line option with a default value of auto In this mode XST implements accumulators takin
118. flip flop names e Whether it is a forward or backward retiming Limitations of Flip Flop Retiming Flip flop retiming has the following limitations e Flip flop retiming is not applied to flip flops that have the IOB TRUE property e Flip flops are not moved forward if the flip flop or the output signal has the Keep KEEP property e Flip flops are not moved backward if the input signal has the Keep KEEP property e nstantiated flip flops are moved only if the Optimize Instantiated Primitives constraint or command line option is set to yes e Flip Flops are moved across instantiated primitives only if the Optimize Instantiated Primitives command line option or constraint is set to yes e Flip flops with both a set and a reset are not moved Controlling Flip Flop Retiming Use the following constraints to control flip flop retiming Register Balancing REGISTER BALANCING e Move First Stage MOVE FIRST STAGE e Move Last Stage MOVE LAST STAGE Partitions XST now supports Partitions in place of Incremental Synthesis Incremental Synthesis is no longer supported The incremental synthesis and resynthesize constraints are no longer supported For more information on Partitions see the ISE Design Suite Help Speed Optimization Under Area Constraint XST performs timing optimization under the area constraint This option is named e LUT FF Pairs Utilization Ratio Virtex 5 devices e Slice LUT FF Pairs Utilization Ra
119. following warning WARNING You have requested that asynchronous control signals of sequential elements be treated as if they were synchronous If you haven t done so yet please carefully review the related documentation material If you have opted to asynchronously control flip flop initialization this feature allows you to better explore the possibilities offered by the Xilinx solution without having to go through a painful rewriting effort However be well aware that the synthesis result while providing you with a good way to assess final device usage and design performance is not functionally equivalent to your HDL description As a result you will not be able to validate your design by comparison of pre synthesis and post synthesis simulation results Please also note that in general we strongly recommend synchronous flip flop initialization ASYNC_TO_SYNC Asynchronous to Synchronous Architecture Support Applies to all FPGA devices Does not apply to CPLD devices ASYNC_TO_SYNC Asynchronous to Synchronous Applicable Elements Applies to the entire design ASYNC_TO_SYNC Asynchronous to Synchronous Propagation Rules Not applicable ASYNC_TO_SYNC Asynchronous to Synchronous Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it ASYNC_TO_SYNC Asynchronous to Synchronous XST Command Line Syntax Example
120. logic end latches 1 architecture archi of latches 1l is begin process G D begin if G 2 1 then Q lt D end if end process end archi Latch With Positive Gate Verilog Coding Example hf Latch with Positive Gate module v latches 1 G D Q input G D output QO reg Q always G or D begin if G Q D end endmodule Latch With Positive Gate and Asynchronous Reset Diagram XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 31 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Latch With Positive Gate and Asynchronous Reset Pin Descriptions es Bein RSR E CLR Asynchronous Reset Active High aq wow Latch With Positive Gate and Asynchronous Reset VHDL Coding Example Latch with Positive Gate and Asynchronous Reset library ieee use ieee std logic 1164 al1 entity latches 2 is port G D CLR in std logic Q out std logic end latches 2 architecture archi of latches 2 is begin process CLR D G begin if CLR 1 then Q lt 0 elsif G 2 1 then Q lt D end if end process end archi Latch With Positive Gate and Asynchronous Reset Verilog Coding Example Latch with Positive Gate and Asynchronous Reset module v_latches_2 G D CLR Q input G D CLR output OQ reg Q always BIG or D or CLR begin if CLR Q 1 b0 else if G Q D end en
121. lt 4 b1111 else if CE Q lt D end endmodule Latches Hardware Description Language HDL Coding Techniques XST can recognize latches with asynchronous set reset control signals Latches can be described using e Process VHDL e Always block Verilog e Concurrent state assignment XST does not support Wait statements VHDL for latch descriptions Latches Log File The XST log file reports the type and size of recognized latches during the Macro Recognition step Synthesizing Unit lt latch gt Related source file is latch 1l vhd WARNING Xst 737 Found 1 bit latch for signal lt q gt Summary inferred 1 Latch s Unit lt latch gt synthesized HDL Synthesis Report Macro Statistics Latches td 1 bit latch iol Latches Related Constraints Pack I O Registers Into IOBs IOB Latches Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip XST User Guide 30 www xilinx com UG627 v 11 3 September 16 2009 hapter 3 XST Hardware Description Language HDL Coding Techniques XILINX Latch With Positive Gate Diagram LD D Q o Latch With Positive Gate Pin Descriptions Positive Gate Data Output Latch With Positive Gate VHDL Coding Example Latch with Positive Gate library ieee use ieee std logic 1164 al1 entity latches 1l is port G D in std logic Q out std
122. lt Cc else outmux lt d end if end if end process end behavior VHDL Case Statements Case statements perform a comparison to an expression to evaluate one of a number of parallel branches The Case statement evaluates the branches in the order they are written The first branch that evaluates to true is executed If none of the branches match the default branch is executed XST User Guide 386 www xilinx com UG627 v 11 3 September 16 2009 Chapter T XST VHDL Language Support XILINX Case Statement VHDL Coding Example library IEEE use IEEE std_logic_1164 all entity mux4 is port a b c d in std logic vector 7 downto 0 sel in std logic vector 1 downto 0 outmux out std logic vector 7 downto 0 end mux4 architecture behavior of mux4 is begin process a b c d sel begin case sel is when 00 gt outmux lt a when 01 gt outmux lt b when 10 gt outmux lt c when others gt outmux lt d case statement must be complete end case end process end behavior VHDL For Loop Statements The or statement is supported for e Constant bounds Stop test condition using any of the following operators lt gt e Next step computation falling within one of the following specifications var var step var var step where var is the loop variable and step is a constant value e Next and exit statements are supported
123. machine REGISTER_POWERUP Register Power Up is attached to the signal and its value is one of the symbolic states defined Actual power up code differs depending on how the state machine is encoded type state_type is sl s2 s3 s4 s5 signal statel state_type REGISTER_POWERUP Register Power Up VHDL Syntax Example Three REGISTER_POWERUP Register Power Up is attached to an enumerated type All registers defined with that type inherit the constraint type state type is sl s2 s3 s4 s5 attribute register powerup of state type type is s1 signal statel state2 state type REGISTER POWERUP Register Power Up VHDL Syntax Example Four For enumerated type objects the power up value may also be defined as a binary code However if automatic encoding is enabled and leads to a different encoding scheme in particular a different code width the power up value is ignored type state type is sl s2 s3 s4 s5 attribute enum encoding of state type type is 001 011 010 100 111 attribute register powerup of state type type is 100 signal statel state type REGISTER POWERUP Register Power Up Verilog Syntax Example Place REGISTER POWERUP Register Power Up immediately before the signal declaration register powerup value REGISTER POWERUP Register Power Up XST Constraint File XCF Syntax Example BEGIN MODEL entity name NET signal name register powerup string END RESOURCE
124. module decode in library work Analyzing hierarchy for module lt cnt60 gt in library lt work gt Analyzing hierarchy for module lt hex2led gt in library work Analyzing hierarchy for module lt smallcntr gt in library lt work gt HDL Analysis Analyzing top module lt stopwatch gt Module lt stopwatch gt is correct for synthesis Analyzing module lt statmach gt in library work clear 6 b000001 counting 6 b001000 start 66000100 stop 66010000 stopped 6 b100000 zero 6 b000010 Module lt statmach gt is correct for synthesis Analyzing module lt tenths gt in library lt work gt Module lt tenths gt is correct for synthesis Analyzing module lt decode gt in library lt work gt Module lt decode gt is correct for synthesis Analyzing module lt cnt60 gt in library lt work gt Module lt cnt60 gt is correct for synthesis XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 467 XILINX Chapter 11 XST Log File Analyzing module lt smallcntr gt in library work Module lt smallcntr gt is correct for synthesis Analyzing module lt hex2led gt in library lt work gt Module lt hex2led gt is correct for synthesis HDL Synthesis Performing bidirectional port resolution Synthesizing Unit lt statmach gt Related source file is statmach v Found finite state machine FSM 0 for signal current state
125. module declaration or instantiation opt level 1 2 OPT LEVEL Optimization Effort XST Constraint File XCF Syntax Example MODEL entity name opt level 1 2 OPT LEVEL Optimization Effort XST Command Line Syntax Example Define globally with the Copt level command line option opt level 1 2 The default is 1 OPT LEVEL Optimization Effort ISE Design Suite Syntax Example Define in ISE Design Suite with Process Properties Synthesis Options Optimization Effort OPT MODE Optimization Goal OPT MODE Optimization Goal defines the synthesis optimization strategy XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 277 XILINX nuit t XST Design Constraints Available Optimization Goal values are speed The priority of speed is to reduce the number of logic levels and therefore to increase frequency speed is the default area The priority of area is to reduce the total amount of logic used for design implementation and therefore improve design fitting OPT_MODE Optimization Goal Architecture Support Architecture independent OPT_MODE Optimization Goal Applicable Elements Applies to the entire design or to an entity or module OPT_MODE Optimization Goal Propagation Rules Applies to the entity or module to which it is attached OPT_MODE Optimization Goal Syntax Examples The following examples show how to use this constraint with particular tool
126. ne ener eda reor ERKENNEN EEEE 273 KEEP HIERARCHY Keep Hierarchy Architecture Support 274 KEEP HIERARCHY Keep Hierarchy Applicable Elements ssssssssee 274 KEEP HIERARCHY Keep Hierarchy Propagation Rules eee eee eeeeeeeeneeeeereeees 274 Iso Library Search Order terrere teen videa Eed E EXE EXE SEENEN a ten 275 jean 276 netlist hierarchy Netlist Hierarchy eee HH ener nennen 276 OPT EEVEL Optimization Effort 15er ete stenna EAEE ave n nos sdeveass set unen one ease dE 276 OPT LEVEL Optimization Effort Architecture Support sssssssssssee ree 277 OPT LEVEL Optimization Effort Applicable Elements 277 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 7 XILINX OPT LEVEL Optimization Effort Propagation Rules cece eeeeeeeeeerereeerenereeeees 277 OPT MODE Optimization Goal 277 OPT MODE Optimization Goal Architecture Support eee cere rererererererereeees 278 OPT MODE Optimization Goal Applicable Elements 278 OPT MODE Optimization Goal Propagation Rules eee rr ee rererererererees 278 PARALLEL CASE Parallel Case eese eene eene hehehe eese nen nennen nene eere nenne 279 PARALLEL CASE Parallel Case Architecture Dupport cece cece cece eerereeereeerreeees 279 PARALLEL CASE Parallel Case Applicable Elements sss 279 PARALLEL CASE Parallel Case Propagation Rule 279 ROC ROC P scans icecsa nesta ged ausstssdat
127. not accepted VHDL Integer Types INTEGER VHDL Predefined Types e BIT e BOOLEAN e BIT VECTOR INTEGER e REAL VHDL STD_LOGIC_1164 IEEE Types The following types are declared in the STD_LOGIC_1164 IEEE package STD LOGIC STD LOGIC VECTOR This package is compiled in the IEEE library To use one of these types add the following two lines to the VHDL specification library IEEE use IEEE STD LOGIC 1164 all XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 371 XILINX Chapter 7 XST VHDL Language Support VHDL Overloaded Data Types The following data types can be overloaded e VHDL Overloaded Enumerated Types e VHDL Overloaded Bit Vector Types e VHDL Overloaded Integer Types e VHDL Overloaded STD LOGIC 1164 IEEE Types e VHDL Overloaded STD_LOGIC_ARITH IEEE Types VHDL Overloaded Enumerated Types STD ULOGIC Contains the same nine values as the STD LOGIC type but does not contain predefined resolution functions e X01 Subtype of STD ULOGIC containing the X 0 and 1 values e X01Z Subtype of STD ULOGIC containing the X 0 1 and Z values e UX01 Subtype of STD ULOGIC containing the U X 0 and 1 values e UX01Z Subtype of STD ULOGIC containing the U X 0 and Z values VHDL Overloaded Bit Vector Types STD ULOGIC VECTOR e UNSIGNED e SIGNED Unconstrained types types whose length is not defined are not accepted VHDL Overloaded Integer Types NATURAL e POSITIVE Any inte
128. of a single DSP48 XST processes it as two separate Multiplier and Adder Subtractor macros making independent decisions on each macro For more information see Multipliers Hardware Description Language HDL Coding Techniques and Adders Subtractors and Adders Subtractors Hardware Description Language HDL Coding Techniques XST User Guide 112 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX Macro implementation on DSP48 blocks is controlled by the Use DSP48 USE_DSP48 constraint or command line option with default value of auto In this mode XST implements multiply adder subtractors taking into account DSP48 resources in the device In auto mode use the DSP Utilization Ratio DSP_UTILIZATION_RATIO constraint to control DSP48 resources for the synthesis By default XST tries to utilize all available DSP48 resources For more information see DSP48 Block Resources To deliver the best performance XST by default tries to infer and implement the maximum macro configuration including as many registers in the DSP48 as possible To shape a macro in a specific way use the Keep KEEP constraint For example to exclude the first register stage from the DSP48 place Keep KEEP constraints on the outputs of these registers In the log file XST reports the details of inferred multipliers adders subtractors and registers at the HDL Synthesis step XST re
129. or method is not listed you cannot use this constraint with it TRISTATE2LOGIC Convert Tristates to Logic VHDL Syntax Example Declare as follows attribute tristate2logic string Specify as follows attribute tristate2logic of entity_name component_name signal_name entity component signal is yes no TRISTATE2LOGIC Convert Tristates to Logic Verilog Syntax Example Place immediately before the module or signal declaration tristate21ogic yes no zi TRISTATE2LOGIC Convert Tristates to Logic XST Constraint File XCF Syntax Example One MODEL entity name tristate2logic yes no true false TRISTATE2LOGIC Convert Tristates to Logic XST Constraint File XCF Example Two BEGIN MODEL entity name NET signal name tristate2logic yes no true false END TRISTATE2LOGIC Convert Tristates to Logic XST Command Line Syntax Example Define in the XST command line as follows run tristate21ogic yes no The default is yes TRISTATE2LOGIC Convert Tristates to Logic ISE Design Suite Syntax Example Define in ISE Design Suite with Process Properties Xilinx9 Specific Options Convert Tristates to Logic USE CLOCK ENABLE Use Clock Enable USE CLOCK ENABLE Use Clock Enable enables or disables the clock enable function in flip flops The disabling of the clock enable function is typically used for ASIC prototyping on FPGA devices XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 341
130. order vhlibil rtfllib vhlib2 After processing the contents of my proj 1so is rtfllib vhlib2 vhlibl DEFAULT_SEARCH_ORDER List of Libraries Only When the Library Search Order LSO file contains a list of the libraries without the DEFAULT_SEARCH_ORDER keyword XST e Searches the library files in the order in which they appear in the LSO file e Leaves the LSO file unchanged For a project file my proj prj with the following contents vhdl vhlibl f1 vhd verilog rtfllib fl v vhdl vhlib2 f3 vhd and an LSO file my proj 1so created with the following contents rtfllib vhlib2 vhlib1 XST uses the following search order rtfllib vhlib2 vhlib1 After processing the contents of my_proj 1so is rtfllib vhlib2 vhlibl DEFAULT_SEARCH_ORDER Keyword and Non Existent Library Name When the Library Search Order LSO file contains a library name that does not exist in the project or INI file and the LSO file does not contain the DEFAULT_SEARCH_ORDER keyword XST ignores the library XST User Guide 444 www xilinx com UG627 v 11 3 September 16 2009 Chapter 11 XST Mixed Language Support For a project file my proj prj with the following contents vhdl vhlibl fl vhd verilog rtfllib fl v vhdl vhlib2 f3 vhd and an LSO file my proj 1so created with the following contents personal lib rtfllib vhlib2 vhlibl XST uses the following search order rtfllib vhlib2 vhlibl After proces
131. preferred syntax but the meta comment style is still supported Use the following syntax synthesis attribute AttributeName of ObjectName is AttributeValue Verilog 2001 Meta Comments Examples synthesis attribute RLOC of u123 is R11C1 S0 synthesis attribute HU SET ul MY SET synthesis attribute bufg of my clock is clk The following constraints use a different syntax e Parallel Case PARALLEL CASE e Full Case FULL CASE e Translate Off TRANSLATE OFT and Translate On TRANSLATE ON For more information see Verilog Attributes and Meta Comments XST Constraint File XCF XST constraints can be specified in the XST Constraint File XCF The XCF has an extension of xcf For information on specifying the XCF in ISE Design Suite see the ISE Design Suite Help To specify the XCF in command line mode use Synthesis Constraint File uc with the run command For more information about the run command and running XST from the command line see XST Command Line Mode XST Constraint File XCF Syntax and Utilization The XST Constraint File XCF syntax enables you to specify a specific constraint for e The entire device globally or Specific modules The XCF syntax is basically the same as the User Constraints File UCF syntax for applying constraints to nets or instances but with an extension to the syntax to allow constraints to be applied to specific levels of hierarchy Use the keyword MODEL to define the enti
132. process CLKA begin if CLKA event and CLKA 1 then if WEA 1 then RAM conv integer ADDRA DIA end if DOA lt RAM conv integer ADDRA The read statement must come AFTER the write statement end if end process XST User Guide 154 www xilinx com UG627 v 11 3 September 16 2009 nuit XST Hardware Description Language HDL Coding Techniques XILINX Although they may look the same except for the signal variable difference it is also important to understand the functional difference between this template and the following well known template which describes a read first synchronization in a single write RAM signal RAM RAMtype process CLKA begin if CLKA event and CLKA 1 then if WEA 1 then RAM conv integer ADDRA lt DIA end if DOA lt RAM conv integer ADDRA end if end process Read First Synchronization Coding Example A read first synchronization is described as follows where the read statement must come BEFORE the write statement process CLKA begin if CLKA event and CLKA 1 then DOA lt RAM conv integer ADDRA The read statement must come BEFORE the write statement if WEA 1 then RAM conv integer ADDRA DIA end if end if end process No Change Synchronization Coding Example process CLKA begin if CLKA event and CLKA 1 then if WEA 1 then RAM conv integer ADDRA DIA else DOA lt RAM co
133. show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it OPTIMIZE PRIMITIVES Optimize Instantiated Primitives Schematic Syntax Examples e Attach to a valid instance e Attribute Name OPTIMIZE_PRIMITIVES e Attribute Values yes no default OPTIMIZE PRIMITIVES Optimize Instantiated Primitives VHDL Syntax Example Declare as follows attribute optimize primitives string Specify as follows attribute optimize primitives of component name entity name label name component entity label is yes no Optimize Instantiated Primitives Verilog Syntax Example Place immediately before the module or signal declaration optimize primitives yes no OPTIMIZE_PRIMITIVES Optimize Instantiated Primitives XST Constraint File XCF Syntax Example MODEL entity name optimize primitives yes no true false OPTIMIZE_PRIMITIVES Optimize Instantiated Primitives ISE Design Suite Syntax Example Define in ISE Design Suite with Process gt Properties gt Xilinx Specific Options gt Optimize Instantiated Primitives IOB Pack I O Registers Into IOBs IOB Pack I O Registers Into IOBs packs flip flops in the I Os to improve input output path timing XST User Guide 320 www xilinx com UG627 v 11 3 September 16 2009 taptir i XST Design Constraints XILINX When IOB is set to auto the action XST takes depen
134. the HDL Synthesis step The composition of multiply accumulate macros happens at the Advanced HDL Synthesis step Synthesizing Unit multipliers 7a Related source file is multipliers 7a vhd Found 8x8 bit multiplier for signal n0002 created at line 28 Found 16 bit up accumulator for signal accum Found 16 bit register for signal mult Summary inferred 1 Accumulator s inferred 16 D type flip flop s inferred 1 Multiplier s Unit lt multipliers_7a gt synthesized Synthesizing advanced Unit lt Mmult__n0002 gt Multiplier Mmult n0002 in block lt multipliers_7a gt and accumulator lt accum gt in block lt multipliers_7a gt are combined into a MAC lt Mmac_accum gt The following registers are also absorbed by the MAC lt mult gt in block multipliers 7a Unit lt Mmult__n0002 gt synthesized advanced HDL Synthesis Report Macro Statistics MACs S 2 8x8 to 16 bit MAC 1 Multiply Accumulate Related Constraints e Use DSP48 USE DSP48 e DSP Utilization Ratio DSP UTILIZATION RATIO e Keep KEEP Multiply Accumulate Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip XST User Guide 118 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX Multiplier Up Accumulate With Register After Multipl
135. the set relative to other elements in the set regardless of eventual placement in the overall design For more information see RLOC in the Constraints Guide XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 279 XILINX nuit t XST Design Constraints S Save S Save is an advanced mapping constraint When the design is mapped some nets may be absorbed into logic blocks and some elements such as LUTs can be optimized away When a net is absorbed into a block or a block is optimized away it can no longer be seen in the physical design database S SAVE prevents this from happening Several optimization techniques such as nets or blocks replication and register balancing are also disabled by the S SAVE constraint If S SAVE is applied to a net XST preserves the net with all elements directly connected to it in the final netlist This includes nets connected to these elements If S SAVE is applied to a block such as a LUT XST preserves the LUT with all signals connected to it For more information see the Constraints Guide uc Synthesis Constraint File uc Synthesis Constraint File specifies a synthesis constraint file for XST to use The XST Constraint File XCF has an extension of xcf If the extension is not xc XST errors out and stops processing For more information see XST Constraint File XCF You can also set this value in ISE Design Suite in Process gt Properties gt Synthe
136. tool to enable or disable portions of code TRANSLATE_OFF Translate Off Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it TRANSLATE_OFF Translate Off VHDL Syntax Example In VHDL write TRANSLATE_OFF Translate Off as follows synthesis translate off code not synthesized synthesis translate on TRANSLATE OFF Translate Off Verilog Syntax Example TRANSLATE OFF Translate Off is available as VHDL or Verilog meta comments The Verilog syntax differs from the standard meta comment syntax presented earlier as shown in the following coding example synthesis translate off code not synthesized synthesis translate_on iuc Use Synthesis Constraints File iuc Use Synthesis Constraints File allows you to ignore the constraints file during synthesis iuc Use Synthesis Constraints File Architecture Support Architecture independent iuc Use Synthesis Constraints File Applicable Elements Applies to files iuc Use Synthesis Constraints File Propagation Rules Not applicable E this value in ISE Design Suite with Process gt Properties gt Synthesis Options gt Use Synthesis Constraints ile iuc Use Synthesis Constraints File Syntax xst run iuc yes no The default is no iuc Use Synthesis Constraints File Syntax Example xst run iuc yes Tells XS
137. use sync set auto yes no The default is auto USE SYNC SET Use Synchronous Set ISE Design Suite Syntax Example Define in ISE Design Suite with Process gt Properties gt Xilinx Specific Options gt Use Synchronous Set USE SYNC RESET Use Synchronous Reset USE SYNC RESET Use Synchronous Reset enables or disables the usage of synchronous reset function of flip flops The disabling of the Synchronous Reset function could be used for ASIC prototyping flow on FPGA devices Detecting USE SYNC RESET with a value of no or false XST avoids using synchronous reset resources in the final implementation Moreover for some designs putting synchronous reset function on data input of the flip flop allows better logic optimization and therefore better QOR XST User Guide 344 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST Design Constraints XILINX In auto mode XST tries to estimate a trade off between using a dedicated Synchronous Reset input on a flip flop input and putting Synchronous Reset logic on the D input of a flip flop In a case where a flip flop is instantiated by you XST removes the synchronous reset only if the Optimize Instantiated Primitives option is set to yes USE_SYNC_RESET Use Synchronous Reset values are e auto default yes no e true XCF only e false XCF only USE SYNC RESET Use Synchronous Reset Architecture Support Applies to all FPGA devices Does not apply t
138. warning Apply Attribute Security attributes on the module definition always have higher precedence than any other attribute or parameter XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 407 XILINX Chapter d XST Verilog Language Support Verilog Limitations in XST This section describes Verilog Limitations in XST Verilog Case Sensitivity Since Verilog is case sensitive module and instance names can be made unique by changing capitalization However for compatibility with file names mixed language support and other tools Xilinx recommends that you do not rely on capitalization only to make instance names unique XST does not allow module names to differ by capitalization only It renames instances and signal names to ensure that lack of case sensitivity support in other tools in your flow does not adversely impact your design XST Support for Verilog Case Sensitivity XST supports Verilog case sensitivity as follows e Designs can use case equivalent names for I O ports nets regs and memories e Equivalent names are renamed using a postfix rnm Index e A rename construct is generated in the NGC file e Designs can use Verilog identifiers that differ in case only XST renames them using a postfix as with equivalent names For instance module upperlower4 inputl INPUT1 outputl output2 input inputl input INPUT1 For this example INPUT1 is renamed to INPUT1_rnm0 Verilog Res
139. with T flip flops Compact State Encoding Compact State Encoding consists of minimizing the number of bits in the state variables and flip flops This technique is based on hypercube immersion Compact State Encoding is appropriate when trying to optimize area Johnson State Encoding Like Gray State Encoding Johnson State Encoding shows benefits with state machines containing long paths with no branching Sequential State Encoding Sequential State Encoding consists of identifying long paths and applying successive radix two codes to the states on these paths Next state equations are minimized Speed1 State Encoding Speed1 State Encoding is oriented for speed optimization The number of bits for a state register depends on the particular FSM but generally it is greater than the number of FSM states User State Encoding In User State Encoding XST uses the original encoding specified in the HDL file For example if you use enumerated types for a state register use the Enumerated Encoding ENUM_ENCODING constraint to assign a specific binary value to each state For more information see XST Design Constraints RAM Based Finite State Machine FSM Synthesis Large Finite State Machine FSM components can be made more compact and faster by implementing them in the block RAM resources provided in Virtex devices and later technologies FSM Style FSM_STYLE directs XST to use block RAM resources for FSMs Values for FSM Style
140. work gt Analyzing hierarchy for module lt hex2led gt in library work Analyzing hierarchy for module lt smallcntr gt in library lt work gt HDL Analysis Analyzing top module lt stopwatch gt Module lt stopwatch gt is correct for synthesis Analyzing Entity lt dcm1 gt in library work Architecture lt BEHAVIORAL gt Set user defined property CAPACITANCE DONT CARE for instance CLKIN IBUFG INST in unit lt dcm1 gt Set user defined property IBUF DELAY VALUE 0 for instance CLKIN IBUFG INST in unit lt dcm1 gt XST User Guide 456 www xilinx com UG627 v 11 3 September 16 2009 Chapter ti XST Log File XILINX Set user defined property IOSTANDARD DEFAULT for instance lt CLKIN_IBUFG_INST gt in unit lt dcm1 gt Set user defined property CLKDV_DIVIDE 2 0000000000000000 for instance lt DCM_INST gt in unit lt dcm1 gt Set user defined property CLKFX_DIVIDE 1 for instance lt DCM_INST gt in unit lt dcm1 gt Set user defined property CLKFX MULTIPLY 4 for instance lt DCM_INST gt in unit lt dcem1 gt Set user defined property CLKIN_DIVIDE_BY_2 FALSE for instance lt DCM_INST gt in unit lt dem1 gt Set user defined property CLKIN PERIOD 20 0000000000000000 for instance lt DCM_INST gt in unit lt dem1 gt Set user defined property CLKOUT PHASE SHIFT NONE for instance lt DCM_INST gt in unit lt dcm1 gt Set user defined property CLK FEEDB
141. 0 do0 lt di DI_WIDTH 1 0 end else begin di0 lt RAM addr DI_WIDTH 1 0 do0 lt RAM addr DI_WIDTH 1 0 end end always posedge clk begin RAM addr lt dil di0 do lt dol do0 end endmodule No Change Mode Single Port BRAM with Byte Wide Write Enable 2 Bytes Pin Descriptions 10 Pins Desripon S Clk Positive Edge Clock e Write Enable Addr Write Read Address Data Input RAM Output Port XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 161 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques XST infers latches for dol and doO signals during the basic HDL Synthesis These latches are absorbed by BRAM during the Advanced HDL Synthesis step No Change Mode Single Port BRAM with Byte Wide Write Enable 2 Bytes VHDL Coding Example Single Port BRAM with Byte wide Write Enable 2 bytes in No Change Mode library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity rams 26 is generic SIZE integer 512 ADDR WIDTH integer 9 DI WIDTH integer 8 port clk in std logic we in std logic vector 1 downto 0 addr in std logic vector ADDR WIDTH 1 downto 0 di in std logic vector 2 DI WIDTH 1 downto 0 do out std logic vector 2 DI WIDTH 1 downto 0 end rams 26 architecture syn of rams 26 is type ram type is array SIZE 1 downto 0 of std logic vector 2 DI WIDTH 1 downto 0
142. 0 h0233A 55 20 n02310 52 20 h04002 49 20 h04001 46 20 h00241 43 20 n08201 40 20 h00602 37 20 n00301 34 20 h02021 31 20 h02222 28 20 n0232B 25 20 h00102 22 20 n08201 19 20 h02433 16 20 n00301 13 20 n02036 10 20 h02237 20 h04040 20 h02500 20 h08201 end endmodule XST User Guide 172 www xilinx com UG627 v 11 3 September 16 2009 Chipter1 XST Hardware Description Language HDL Coding Techniques XILINX Dual Port RAM Initial Contents VHDL Coding Example Initializing Block RAM Dual Port BRAM library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity rams 20b is port elki in std logic Clk2 lt in std logic we in std logic addrl in std logic vector 7 downto 0 addr2 in std logic vector 7 downto 0 di in std logic vector 15 downto 0 dol out std logic vector 15 downto 0 do2 out std logic vector 15 downto 0 end rams 20b architecture syn of rams 20b is type ram type is array 255 downto 0 of std logic vector 15 downto 0 signal RAM ram type 255 downto 100 gt X B8B8 99 downto 0 gt X 8282 begin process clk1l begin if rising edge clk1 then if we 1 then RAM conv integer addrl lt di end if dol lt RAM conv integer addrl end if end process process clk2 begin if rising edge clk2 then do2 lt RAM conv integer addr2
143. 00 zero 001 start 011 counting 010 stop 110 stopped 111 Advanced HDL Synthesis Report Macro Statistics FSMs 1 ROMs 3 16x10 bit ROM 1 16x7 bit ROM s Counters 2 4 bit up counter 2 2 Registers 3 Flip Flops Latches 3 XST FPGA Log File Example The following is an example of an XST log file for FPGA synthesis Release 10 1 xst K 31 nt64 Copyright c 1995 2008 Xilinx Inc All rights reserved TABLE OF CONTENTS 1 Synthesis Options Summary 2 HDL Compilation 3 Design Hierarchy Analysis 4 HDL Analysis 5 HDL Synthesis 5 1 HDL Synthesis Report 6 Advanced HDL Synthesis 6 1 Advanced HDL Synthesis Report 7 Low Level Synthesis 8 Partition Report 9 Final Report 9 1 Device utilization summary 9 2 Partition Resource Summary 9 3 TIMING REPORT XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 453 XILINX Synthesis Options Summary Source Parameters Input File Name stopwatch prj Input Format mixed Ignore Synthesis Constraint File NO Target Parameters Output File Name stopwatch Output Format NGC Target Device xc4vlx15 12 sf363 Source Options Top Module Name stopwatch Automatic FSM Extraction YES FSM Encoding Algorithm Auto Safe Implementation No FSM Style lut RAM Extraction Yes RAM Style Auto ROM Extraction Yes Mux Style Auto Decoder Extraction YES Priority Encode
144. 000 3 b110 res 8 b01000000 default res 8 b10000000 endcase end endmodule unused decoder output No Decoder Inference Some Selector Values Unused VHDL Coding Example No Decoder Inference library ieee use ieee std logic 1164 all entity decoders 4 is port sel in std logic vector some selector values are unused 2 downto 0 res out std logic vector 7 downto 0 end decoders 4 architecture archi of decoders 4 is begin res lt 00000001 when sel 000 else 00000010 when sel 001 else 00000100 when sel 010 else 00001000 when sel 011 else 00010000 when sel 100 else 00100000 when sel 101 else 110 and 111 selector values are unused XXXXXXXX end archi 78 www xilinx com XST User Guide UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX No Decoder Inference Some Selector Values Unused Verilog Coding Example No Decoder Inference some selector values are unused module v_decoders_4 sel res input 2 0 sel output 7 0 res reg 7 0 res always sel or res begin case sel 3 b000 res 3 b001 res 3 b010 res 3 b011 res 3 b100 res 8 500010000 3 b101 res 8 b00100000 110 and 111 selector values are unused default res 8 bxxxxxxxx endcase end endmodule Priority Encoders Hardware Description Language HDL Coding
145. 01 6 5001110 data lt 20 n04001 6 b101110 data lt 20 h04004 6 b001111 data lt 20 n02500 6 b101111 data lt 20 h00301 6 5010000 data lt 20 h00340 6 5110000 data lt 20 h00102 6 b010001 data lt 20 h00241 6 b110001 data lt 20 h02137 6 5010010 data lt 20 h04002 6 5110010 data lt 20 h02036 6 b010011 data lt 20 h08300 6 b110011 data lt 20 h00301 6 5010100 data lt 20 h08201 6 b110100 data lt 20 h00102 6 5010101 data lt 20 h00500 6 b110101 data lt 20 h02237 6 5010110 data lt 20 h08101 6 b110110 data lt 20 h04004 6 b010111 data lt 20 h00602 6 b110111 data lt 20 h00304 6 b011000 data lt 20 h04003 6 b111000 data lt 20 h04040 6 5011001 data lt 20 h0241E 6 b111001 data lt 20 h02500 6 5011010 data lt 20 h00301 6 b111010 data lt 20 h02500 6 b011011 data lt 20 n00102 6 b111011 data lt 20 h02500 6 b011100 data lt 20 h02122 6 b111100 data lt 20 h0030D 6 5011101 data lt 20 h02021 6 b111101 data lt 20 h02341 6 5011110 data lt 20 h00301 6 b111110 data lt 20 h08201 6 b011111 data lt 20 h00102 6 b111111 data lt 20 h0400D endcase end endmodule Pipelined Distributed RAM Hardware Description Language HDL Coding Techniques In order to increase the speed of designs XST can infer pipelined distributed RAM By interspersing re
146. 08300 h04002 h08201 h00500 h04001 h02500 h00340 h00241 h04002 h08300 h08201 h00500 h08 01 h00602 h04003 h024 lE h00301 hoo h02 025 221 h02021 h00301 h00 02 00000 00001 00010 00011 00100 00101 OV OV OV OO OO OD OD OV OD OD OV OV OD OD OV OV OD OD OO OO OV OV DD OV OV OO On DD DG D DD DG DG DG DD DD DD pp DD OOOO oO DD pp D 1 data data data data data data data data data data data data data data data data data data data data data data data data data data data data data data data data 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 h02222 h04001 h00342 h0232B h00900 h00302 h00102 h04002 h00900 h08201 h02023 h00303 h02433 h00301 h04004 h00301 h00102 h02137 h02036 h00301 h00102 h02237 h04004 h00304 h04040 h02500 h02500 h02500 h0030D h02341 h08201 h0400D XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 181 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques ROM With Registered Output Verilog Coding Example Two ROMs Using B Verilog code Lf module v rams 2 input input input output reg reg always addr
147. 1 3 September 16 2009 www xilinx com 345 XILINX nuit t XST Design Constraints USE SYNC RESET Use Synchronous Reset XST Constraint File XCF Syntax Example Three BEGIN MODEL entity_name INST instance_name use_sync_reset auto yes no true false END USE_SYNC_RESET Use Synchronous Reset XST Command Line Syntax Example Define in the XST command line as follows xst run use_sync_reset auto yes no The default is auto USE_SYNC_RESET Use Synchronous Reset ISE Design Suite Syntax Example Define in ISE Design Suite with Process gt Properties gt Xilinx Specific Options gt Use Synchronous Reset USE_DSP48 Use DSP48 This constraint is called e Use DSP48 Virtex 4 devices e Use DSP Block Virtex 5 devices and Spartan 3A DSP devices XST enables you to use the resources of the DSP48 blocks introduced in Virtex 4 devices The default is auto In auto mode XST automatically implements such macros as MAC and accumulates on DSP48 but some of them as adders are implemented on slices You have to force their implementation on DSP48 using a value of yes or true For more information on supported macros and their implementation control see XST Hardware Description Language HDL Coding Techniques Several macros for example MAC that can be placed on DSP48 are in fact a composition of simpler macros such as multipliers accumulators and registers To achieve the best performance XST by def
148. 11111 default res 8 b01111111 endcase end endmodule 8 b11111110 8 b11111101 8 b11111011 8 b11110111 8 b11101111 Decoder With Unselected Outputs Pin Descriptions 10 Pins Desrpion res Data Output No Decoder Inference Unused Decoder Output VHDL Coding Example No Decoder Inference unused decoder output library ieee use ieee std logic 1164 al1 entity decoders 3 is port sel in std logic vector 2 downto 0 res out std logic vector 7 downto 0 end decoders 3 architecture archi of decoders 3 is begin res lt 00000001 when sel 000 else unused decoder output XXXXXXXX when sel 001 else 00000100 when sel 010 else 00001000 when sel 011 else 00010000 when sel 100 else 00100000 when sel 101 else 01000000 when sel 110 else 10000000 end archi XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 77 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques No Decoder Inference Unused Decoder Output Verilog Coding Example No Decoder Inference module v_decoders_3 sel res input 2 0 sel output 7 0 res reg 7 0 res always sel begin case sel 3 b000 res 8 b00000001 unused decoder output 3 b001 res 8 bxxxxxxxx 3 b010 res 8 500000100 3 b011 res 8 b00001000 3 b100 res 8 b00010000 3 b101 res 8 b00100
149. 16 and SRLC16 Both SRL16 and SRLC16 are available with or without a clock enable Synchronous and asynchronous control signals are not available in the SLRC16x primitives However XST takes advantage of dedicated SRL resources if a shift register description has only a single asynchronous or synchronous set or reset signal Such implementation reduces area significantly XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 51 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques SRL16 and SRLC16 support only LEFT shift operation for a limited number of IO signals e clock e clock enable e serial data in e serial data out If your shift register does have for instance a synchronous parallel load or multiple set or reset signals no SRL16 is implemented XST uses specific internal processing which enables it to produce the best final results The XST log file reports recognized shift registers when they can be implemented using SRL16 or SRLC16 resources As a result some of the coding examples shown below in particular those with parallel load or parallel out functionality do not result in any specific shift register reporting For more information see Specifying INIT and RLOC Pin Layout of SRL16E Diagram SRL16E Q Pin Layout of SRLC16 Diagram Q CLK AO SRLC16 Q15 A1 A2 A3 XST User Guide 52 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware
150. 16 downto 0 begin Ul addern generic map n gt 13 port map X Y C1 C2 lt Cl amp A C3 lt Z amp B U2 addern generic map n gt 17 port map C2 C3 S end bhv The GENERICS command line option allows you to redefine generics VHDL values defined in the top level design block This allows you to easily modify the design configuration without any Hardware Description Language HDL source modifications such as for IP core generation and testing flows For more information see Generics generics VHDL Generic and Attribute Conflicts Since generics and attributes can be applied to both instances and components in the VHDL code and attributes can also be specified in a constraints file from time to time conflicts may arise To resolve these conflicts XST uses the following rules of precedence 1 Whatever is specified on an instance lower level takes precedence over what is specified on a component higher level 2 Ifa generic and an attribute are specified on either the same instance or the same component the generic takes precedence and XST issues a message warning of the conflict 3 An attribute specified in the XST Constraint File XCF always takes precedence over attributes or generics specified in the VHDL code XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 381 XILINX Chapter 7 XST VHDL Language Support When an attribute specified on an instance overrides a generic specifi
151. 1993 In case of a conflict Std 1076 1993 behavior overrides std 1076 1987 In cases where e Std 1076 1993 requires a construct to be an erroneous case but e Std 1076 1987 accepts it XST issues a warning instead of an error An error would stop analysis VHDL IEEE Conflict Example Following is an example of a VHDL IEEE conflict e Std 1076 1993 requires an impure function to use the impure keyword while declaring a function e Std 1076 1987 has no such requirement In this case XST e Accepts the VHDL code written for Std 1076 1987 e Issues a warning stating Std 1076 1993 behavior Non LRM Compliant Constructs in VHDL XST supports some non LRM compliant constructs XST supports a specific non LRM compliant construct when e The construct is supported by majority of synthesis or simulation third party tools and e Itisa real language limitation for design coding and has no impact on quality of results or problem detection in the design For example the LRM does not allow instantiation when the formal port is a buffer and the effective one is an out and vice versa XST VHDL File Type Support XST supports a limited File Read and File Write capability for VHDL e Use File Read capability for example to initialize RAMs from an external file e Use File Write capability for debugging processes or to write a specific constant or generic value to an external file For more information see Initializing RAM Coding Examples
152. 3 September 16 2009 Chapter ti XST Log File XILINX Messages Hidden When Value is Set to hdl level and hdl and low levels The following messages are hidden when the value of the XIL XST HIDEMESSAGES environment variable is set to bal level and hdl and low levels e WARNING HDLCompilers 38 design v line 5 Macro my macro redefined Note This message is issued by the Verilog compiler only e WARNING Xst 916 design vhd line 5 Delay is ignored for synthesis e WARNING Xst 766 design vhd line 5 Generating a Black Box for component comp e Instantiating component comp from Library lib e Set user defined property LOC X1Y1 for instance inst in unit block e Set user defined property RLOC X1Y1 for instance inst in unit block e Set user defined property INIT 1 for instance inst in unit block prop y Register regl equivalent to reg2 has been removed Messages Hidden When Value is Set to low level or hdl and low levels The following messages are hidden when the value of the ZIL XST HIDEMESSAGES environment variable is set to Low levelorhdl and low levels e WARNING Xst 382 Register regl is equivalent to reg2 Register regl equivalent has been removed Xst 1710 FF Latch reg without init value is constant in block block 2 G e WARNING Xst 1293 FF Latch reg is constant in block block G Xst 1291 FF Latch reg is unconnected in block block
153. 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX Finite State Machine FSM With Three Always Blocks Verilog Coding Example State Machine with three always blocks module v_fsm_3 clk reset xl outp input clk reset xl output outp reg outp reg 1 0 state reg 1 0 next_state parameter sl parameter s3 2 b00 parameter s2 2 b10 parameter s4 2 501 2 b11 initial begin state 2 b00 end always posedge clk or posedge reset begin if reset state lt sl else state lt next_state end always state or x1 begin case state sl if xl 1 bl next state s2 else next state s3 S2 next state s4 S3 next state s4 S4 next state sl endcase end always G state begin case state sl outp 1 b1 S2 outp 1 b1 S3 outp 1 b5b0 S4 outp 1 b0 endcase end endmodule Black Boxes Hardware Description Language HDL Coding Techniques Your design may contain Electronic Data Interchange Format EDIF or NGC files generated by e Synthesis tools Schematic text editors e Any other design entry mechanism These modules must be instantiated in your code in order to be connected to the rest of your design To do so in XST use Black Box instantiation in the VHDL or Verilog code The netlist is propagated to the final top level netlist without being processed by XST Moreover XST enables you to a
154. 3 XST Timing Options XST Constraint File OGCH emen 263 XST General Constraints 6 35 ee EE 264 iobut Add O Buffers 5 meer tert emer evectus eee epe es eee es eee ve ko Re ere E Nee vr ERE re canons 264 BOX 21 YPEABOXTY E 265 BOX TYPE BoxType Architecture Support 265 BOX TYPE BoxType Applicable Elements e 266 BOX TYPE BoxType Propagation Rules enero tese pek EES sinnn 266 bus delimiter Bus Delimiter eei iter eret eter ete eorr ere EEE eet PY eS HUE REP Ye Feb Fe FREUE 266 ECASE CASE M 267 vlgcase Case Implementation Style sss HH eene 267 define Verilog Macr0s i hierie pri east aio ee eer ERE a saat 268 duplication suffix Duplication Suffix i eese ersten aea opns hne nue oae auo cast un anon e uie ne a EIER sates 269 PULL CASE Pull Case tette rere ree hen ee E EN eR sess ERRARE E CERE PN EENEG HERMES 270 FULL CASE Full Case Architecture Dupport eee 270 FULL CASE Full Case Applicable Elements sse 270 FULL CASE Full Case Propagation Rules eee 270 rilview Generate RTL Schematic XH 271 SARL EE 271 hierarchy_separator Hierarchy Separator ue EE NENNEN NENNEN 272 IOSTANDARD I O Standard riii siirron ettet etae eee te Eee ea tee ne en ere run ec taba ee rues eee Rep tette nura 273 qudm 273 KBEP HIERARCHY Keep Hierarchy eee eee ntt nete
155. 54 CLOCK SIGNAL Clock Signal Propagation Rules e 354 glob opt Global Optimization Goal EEN ENNEN NENNEN 354 Global Optimization Goal Domain Definitions essen 355 XST Constraint File XCF Timing Constraint Support 356 PERIOD Terno eege ee dree eege 356 RISIKEN 356 EROM IO BLOM e ET 357 TNM Timing Name EE 357 INM NET Timing Name on a Net 357 TIMEGRP IMME STOUP sene musson stata dens rete oto rte Eee Eure eere d ee vk rasa avit dinetsseatansvensssed des 357 TIG Clisme lonor EE 357 XST Implementation Constraints ete etcrenes cette eere rhe aee E dea eae cen e a Ya Ee SEENEN ENEE 358 Implementation Constraints Syntax Examples sss 358 Implementation Constraints XST Constraint File XCF Syntax Examples 358 Implementation Constraints VHDL Syntax Examples sss 358 Implementation Constraints Verilog Syntax Bxamples sss 358 RLOC CERTE 358 NOREDUGE LEHRER 359 PWR MODE Power Mode ceti reise terr npe kho nete a ERO LI REOR ECCE SEU SEEN E NEU ERR AE LEER A ERE re ERA 359 PWR MODE Power Mode Architecture Support ssssssssssee es 359 XST Supported Third Party Constraints eeeeeseseseeeeeee eese enne EEEE nennen eren nene 360 XST Equivalents to Third Party Constraints eene 360 Third Party Constraints Syntax Baxamples eee eee 363 Chapter 7 XST VHDL Language Support eren sesssesssevsscsessvndicacsvavssecsieuvsscessuedscessba
156. 6 Shift Registers in Macro Generation 206 RAMS m Macro Generation c esce eue Eege EA 206 Primitives Used by XST ict tmetttt eet pese e SHEER ES ERE PU NEESS NEEN EEN 206 Controlling Implementation of Inferred RAM sse 207 ROMs in Macro Generation 4 2 rote e pet eb REENEN NEESS EENS 207 DSP48 Block RESOULCES n 208 Mapping Logic Onto Block RAM eerie etre dree EEN en SEENEN 209 Mapping Logic Onto Block RAM Log Files sssessssssee eH een 209 Mapping Logic Onto Block RAM Coding Examples ssesssssee He 210 Fhp Elop Retiming ier ta E eee ehe ones eet ee oe coeds dee gedet 212 Limitations of Flip Flop Retiming eerte ttr tratan en beta boves bae Sues EES E RARE E 213 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 5 XILINX Controlling Flip Flop Reimp e decevsantencevttvetecsocaeetactecdeoseesens vate eta dn tiq ono endure un aeree naga 213 BN EE 213 Speed Optimization Under Area Constraimt cee cece creer eeereeeeesereeeeeee nese e e e e eene 213 EPGA Optimization Report SeChOMiscissscscstdsnsnstasssnsccdncntiscs ni insp E EE E ESS EEI ESEE ESEESE E 215 Cell Usage e 215 BELS Coll Usage sviscus ccessous eve eeneg dcissieie enectevs ge deeg dee Eed ONEA EEEE EAEE ETETEN 215 Flip Flops and Latches Cell Usage s ccccccecssssesnccesccecnssnseneeeconensnseseeeecceseosssneascecsesenneneees 216 RAMS Cell USa ee E ia 216 SHIFTERS
157. 8 memory register parameter statel 3 b001 3 bit constant parameter component TMS380C16 string Behavioral Verilog Legal Statements The following statements are legal in Behavioral Verilog Variable and signal assignment e Variable expression e if condition statement e if condition statement else statement case expression expression statement default statement endcase e for variable expression condition variable variable expression statement e while condition statement e forever statement e functions and tasks XST User Guide 420 www xilinx com UG627 v 11 3 September 16 2009 thipter t XST Behavioral Verilog Language Support XILINX All variables are declared as integer or reg A variable cannot be declared as a wire Behavioral Verilog Expressions An expression involves constants and variables with arithmetic logical relational and conditional operators as shown in Operators Supported in Behavioral Verilog The logical operators are further divided as bit wise versus logical depending on whether it is applied to an expression involving several bits or a single bit Operators Supported in Behavioral Verilog Expressions Supported in Behavioral Verilog in Supper ka Supported Arithmetic Supported only if second operand is a power of 2 Modulus Supported only if second operand is a power of 2 XST User Guide UG627 v 11 3 September 16 2009
158. 8 www xilinx com UG627 v 11 3 September 16 2009 thipter t XST Behavioral Verilog Language Support XILINX This sets the set reset value on the register output at initial power up but since this is dependent upon a local reset the value changes whenever the local set reset is activated Behavioral Verilog Arrays Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip Verilog allows arrays of reg and wires to be defined as shown in the following coding examples Behavioral Verilog Arrays Coding Example The following coding example describes an array of 32 elements each 4 bits wide which can be assigned in behavioral Verilog code reg 3 0 mem_array 31 0 Structural Verilog Arrays Coding Example The following coding example describes an array of 64 elements each 8 bits wide which can be assigned only in structural Verilog code wire 7 0 mem_array 63 0 Behavioral Verilog Multi Dimensional Arrays XST supports multi dimensional array types of up to two dimensions Multi dimensional arrays can be any net or any variable data type You can code assignments and arithmetic operations with arrays but you cannot select more than one element of an array at one time You cannot pass multi dimensional arrays to system tasks or functions or to regular tasks or functions Behavioral Verilog Multi Dimensional Arrays Coding Ex
159. 83 XILINX nuit d XST Design Constraints xsthdpini HDL Library Mapping File Syntax Example xst set xsthdpini c data my_libraries my ini file_name Specifies c data my_libraries my ini as the file that will point to all of your libraries You must run this set command before any run commands MY INI Example Text work1 H Users conf my_lib work1l work2 C mylib work2 xsthdpdir Work Directory xsthdpdir Work Directory defines the location in which VHDL compiled files must be placed if the location is not defined by library mapping files To access Work Directory e In ISE Design Suite select Process gt Properties gt Synthesis Options gt VHDL Working Directory or e Use the following command in stand alone mode set xsthdpdir directory xsthdpdir Work Directory Example Assume the following for purposes of this example Three different users are working on the same project e They share one standard pre compiled library shlib This library contains specific macro blocks for their project e Each user also maintains a local work library e User places her local work library outside the project directory for example in c temp e Users 1 and 2 share another library lib12 between them but not with User 3 The settings required for the three users are as follows xsthdpdir Work Directory Example User One Mapping file schlib z sharedlibs shlib libl22z NuserlibsMlib12 xsthdpdir
160. 995 2008 Xilinx Inc All rights reserved Writing module to tenths ngo Reading core lt tenths_c_counter_binary_v8_0_xst_l ngc gt Loading core tenths c counter binary v8 0 xst 1 for timing and area information for instance lt BU2 gt Loading core lt tenths gt for timing and area information for instance lt xcounter gt Advanced HDL Synthesis Report Macro Statistics ROMs 3 16x10 bit ROM 1 16x7 bit ROM 2 Counters 2 4 bit up counter 2 Registers 5 Flip Flops 5 Low Level Synthesis Optimizing unit lt stopwatch gt Mapping all equations Building and optimizing final netlist Found area constraint ratio of 100 5 on block stopwatch actual ratio is 0 Number of LUT replicated for flop pair packing 0 Final Macro Processing Final Register Report Macro Statistics Registers 13 Flip Flops 13 Partition Report Partition Implementation Status XST User Guide 460 www xilinx com UG627 v 11 3 September 16 2009 Chapter tt XST Log File Final Report Final Results RTL Top Level Output File Name stopwatch ngr Top Level Output File Name stopwatch Output Format NGC Optimization Goal Speed Keep Hierarchy NO Design Statistics IOs 27 Cell Usage BELS 70 GND 2 INV 1 LUT1 3 LUT2 1 LUT2_L 1 LUT3 8 LUT3 D 1 LUT3_L 1 LUT4 37 LUT4_D
161. A devices Does not apply to CPLD devices READ_CORES Read Cores Applicable Elements Since this constraint can be used with BoxType BOX_TYPE the set of objects on which the both constraints can be applied must be the same Apply READ_CORES to e A component or entity VHDL e A model or label instance Verilog e A model or INST in model XCF e The entire design XST command line If READ_CORES is applied to at least a single instance of a block then READ_CORES is applied to all other instances of this block for the entire design XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 307 XILINX nuit t XST Design Constraints READ_CORES Read Cores Propagation Rules Not applicable READ_CORES Read Cores Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it READ_CORES Read Cores VHDL Syntax Example Declare as follows attribute read_cores string Specify as follows attribute read_cores of component_name entity_name component entity is yes no optimize The default is yes READ CORES Read Cores Verilog Syntax Example Place immediately before the module declaration or instantiation read_cores yes no optimize The default is yes READ_CORES Read Cores XST Constraint File XCF Syntax Example One MODEL entity name read
162. A port size B port size 1 downto 0 begin process clk begin if clk event and clk 1 then a in lt A b in lt B mult res a in b in pipe 2 lt mult res pipe 3 lt pipe 2 MULT lt pipe 3 end if end process end beh XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 109 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Pipelined Multiplier Inside Single Verilog Coding Example Pipelined multiplier ry The multiplication operation placed inside the process block and the pipeline stages are represented as single registers mult_style pipe_lut module v_multipliers_3 clk A B MULT input clk input 17 0 A input 17 0 B output 35 0 MULT reg 35 0 MULT reg 17 0 a in b in reg 35 0 mult res reg 35 0 pipe 2 pipe 3 always posedge clk begin a in lt A b in lt B mult res a in b in pipe 2 mult res pipe 3 pipe 2 MULT pipe 3 end endmodule Pipelined Multiplier Outside Shift Pin Descriptions 10 Pins Description Cd clk Positive Edge Clock MULT MULT Result XST User Guide 110 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX Pipelined Multiplier Outside Shift VHDL Coding Example Pipelined multiplier The multiplication operation placed out
163. AB D 0 4 2 downto 0 lt CNST A 5 downto 3 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 373 XILINX Chapter 7 XST VHDL Language Support Multi Dimensional Array VHDL Coding Example Two Add the following declaration subtype MATRIX15 is array 4 downto 0 2 downto 0 of STD_LOGIC_VECTOR 7 downto 0 signal MATRIX_A MATRIX15 The following can now be specified e A multi dimensional array signal or variable MATRIXA lt CNST A e An index of one row of the array MATRIXA 5 lt TAB A e Indexes of the maximum number of dimensions MATRIXA 5 0 0 lt 1 Indices may be variable VHDL Record Types XST supports record types as shown in the following coding example type REC1 is record fieldl std_logic field2 std_logic_vector 3 downto 0 end record e Record types can contain other record types e Constants can be record types e Record types cannot contain attributes e XST supports aggregate assignments to record signals VHDL Initial Values In VHDL you can initialize registers when you declare them The value e Isa constant e Cannot depend on earlier initial values e Cannot be a function or task call e Can be a parameter value propagated to a register When you give a register an initial value in a declaration XST sets this value on the output of the register at global reset or at power up The assigned value is carried in the NGC file as an INIT attribute
164. ACK 1X for instance lt DCM_INST gt in unit lt dcem1 gt Set user defined property DESKEW_ADJUST SYSTEM_SYNCHRONOUS for instance lt DCM_INST gt in unit lt dcm1 gt Set user defined property DFS_FREQUENCY_MODE LOW for instance lt DCM_INST gt in unit lt dem1 gt Set user defined property DLL FREQUENCY MODE LOW for instance lt DCM_INST gt in unit lt dem1 gt Set user defined property DSS_MODE NONE for instance lt DCM_INST gt in unit lt dcm1 gt Set user defined property DUTY CYCLE CORRECTION TRUE for instance lt DCM_INST gt in unit lt dcm1 gt Set user defined property FACTORY JF C080 for instance lt DCM_INST gt in unit lt dcem1 gt Set user defined property PHASE SHIFT 0 for instance lt DCM_INST gt in unit lt dcm1 gt Set user defined property SIM MODE SAFE for instance lt DCM_INST gt in unit lt dcm1 gt Set user defined property STARTUP_WAIT TRUE for instance lt DCM_INST gt in unit lt dcem1 gt Entity dcm1 analyzed Unit dcm1 generated Analyzing module lt statmach gt in library work clear 6 b000001 counting 6 b001000 start 66000100 stop 6 b010000 stopped 6 b100000 zero 66000010 Module lt statmach gt is correct for synthesis Analyzing module decode in library lt work gt Module lt decode gt is correct for synthesis Analyzing module lt cnt60 gt in library lt work gt Module lt cnt60 gt is correct for syn
165. AM conv integer read addrb end syn XST User Guide 148 www xilinx com UG627 v 11 3 September 16 2009 Chapter 3 XST Hardware Description Language HDL Coding Techniques XILINX Dual Port RAM With One Enable Controlling Both Ports Verilog Coding Example Dual Port RAM with One Enable Controlling Both Ports eh module v_rams_13 input elk input en input we clk en we addra input 5 0 addra input 5 0 addrb input 15 0 di output 15 0 doa output 15 0 dob reg 15 0 ram 63 0 reg 5 0 read addra reg 5 0 read addrb always posedge clk begin if en begin if we ram addra di read addra lt addra read addrb lt addrb end end assign doa assign dob endmodule The following descriptions are directly mappable onto block RAM as shown in the diagram Dual Port RAM With Enable on Each Port Diagram ADDRA ADDRB ENA Block WEA DIA CLK WV ram read_addra ram read_addrb DOA DOB addrb di doa dob XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 149 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Dual Port RAM With Enable on Each Port Pin Descriptions Lom bee O O SSC ESCH l t N NN Dual Port RAM With Enable on Each Port VHDL Coding Example Dual Port RAM with Enable on Each Port library ieee use ieee std logic 1164 all use ieee std l
166. Bit Unsigned Up Down Counter With Asynchronous Reset VHDL Coding Example 4 bit Unsigned Up Down counter with Asynchronous Reset library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity counters_6 is port C CLR UP DOWN in std logic Q out std logic vector 3 downto 0 end counters 6 architecture archi of counters 6 is signal tmp std logic vector 3 downto 0 begin process C CLR begin if CLR 1 then tmp 0000 elsif C event and C 1 then if UP DOWN 1 then tmp lt tmp 1 else tmp lt tmp 1 end if end if end process Q lt tmp end archi XST User Guide 44 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX 4 Bit Unsigned Up Down Counter With Asynchronous Reset Verilog Coding Example 4 bit Unsigned Up Down counter with Asynchronous Reset ee module v counters 6 C CLR UP DOWN Q input C CLR UP DOWN output 3 0 Q reg 3 0 tmp always 8 posedge C or posedge CLR begin if CLR tmp lt 4 b0000 else if UP_DOWN tmp lt tmp 1 bl else tmp lt tmp 1 b1 end assign Q tmp endmodule 4 Bit Signed Up Counter With Asynchronous Reset Diagram COUNT 4 CLR ven 4 Bit Signed Up Counter With Asynchronous Reset Pin Descriptions Positive Edge Clock Asynchronous Reset Active High XST User Guide UG627 v 11 3 Sep
167. CIN C COUT amp S end ADD end PKG use work PKG all entity EXAMPLE is port A B in BIT_VECTOR 3 downto 0 CIN in BIT S out BIT VECTOR 3 downto 0 COUT out BIT end EXAMPLE architecture ARCHI of EXAMPLE is begin process A B CIN variable S50 S1 S2 S3 BIT VECTOR 1 downto 0 begin ADD A 0 B 0 CIN S0 ADD A 1 B 1 SO 1 S1 ADD A 2 B 2 S1 1 S2 ADD A 3 B 3 S2 1 S3 S lt S3 0 amp S2 0 amp S1 0 amp SO 0 COUT lt S3 1 4 end process end ARCHI Recursive Function VHDL Coding Example XST supports recursive functions The following coding example represents n function function my_func x integer return integer is begin if x 1 then return x else return x my func x 1 end if end function my func VHDL Assert Statements XST supports Assert statements Assert statements enable you to detect undesirable conditions in VHDL designs such as bad values for generics constants and generate conditions or bad values for parameters in called functions For any failed condition in an Assert statement XST according to the severity level issues a warning message or rejects the design and issues an error message XST supports the Assert statement only with static condition The following coding example contains a block SINGLE SRL which describes a shift register The size of the shift register depends on the SRL WIDTH generic value The Asse
168. CPLD devices BRAM MAP Map Logic on BRAM Applicable Elements Applies to BRAMs XST User Guide 310 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST Design Constraints XILINX BRAM_MAP Map Logic on BRAM Propagation Rules Isolate the logic including output register to be mapped on RAM in a separate hierarchical level Logic that does not fit on a single block RAM is not mapped Ensure that the whole entity fits not just part of it The attribute BRAM MAP is set on the instance or entity If no block RAM can be inferred the logic is passed to Global Optimization where it is optimized The macros are not inferred Be sure that XST has mapped the logic BRAM MAP Map Logic on BRAM Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it BRAM MAP Map Logic on BRAM VHDL Syntax Example Declare as follows attribute bram map string Specify as follows attribute bram map of component name component is yes no BRAM MAP Map Logic on BRAM Verilog Syntax Example Place immediately before the module declaration or instantiation bram_map yes no zi BRAM MAP Map Logic on BRAM XST Constraint File XCF Syntax Example One MODEL entity name bram map yes no true false BRAM MAP Map Logic on BRAM XST Constraint File XCF Syntax Example Two BEGIN MODEL entity
169. CT RAM Extraction XST Constraint File XCF Syntax Example One MODEL entity name ram extract yes no true false RAM EXTRACT RAM Extraction XST Constraint File XCF Example Two BEGIN MODEL entity name NET signal name ram extract yes no true false END RAM EXTRACT RAM Extraction XST Command Line Syntax Example Define in the XST command line as follows xst run ram extract yes no The default is yes RAM EXTRACT RAM Extraction ISE Design Suite Syntax Example Define in ISE Design Suite with Process Properties HDL Options RAM Extraction RAM STYLE RAM Style RAM STYLE RAM Style controls the way the macrogenerator implements the inferred RAM macros RAM STYLE values are e auto default e block e distributed pipe distributed e block powerl block power2 The default is auto XST looks for the best implementation for each inferred RAM You must use block powerl and block power2 in order to achieve power oriented BRAM optimization For more information see Power Reduction POWER The implementation style can be manually forced to use block RAM or distributed RAM resources You can specify p pe distributed block powerl and block power2 only through VHDL or Verilog or XCF constraints RAM STYLE RAM Style Architecture Support Applies to all FPGA devices Does not apply to CPLD devices Block powerl and block power2 are supported for Virtex 4 devices and Vi
170. Chapter i XST CPLD Optimization The XST log file contains e Tracing of progressive unit optimizations Optimizing unit unit_name e Information warnings or fatal messages related to unit optimization When equation shaping is applied XC9500 devices only Collapsing Removing equivalent flip flops Register ff1 equivalent to ff2 has been removed User constraints fulfilled by XST implementation constraint constraint name value signal name e Final results statistics Final Results Top Level Output file name file name Output format ngc Optimization goal area speed Target Technology 9500 9500xl 9500xv xpla3 xbr cr2s Keep Hierarchy yes soft no Macro Preserve yes no XOR Preserve yes no Design Statistics NGC Instances nb of instances I Os nb of io ports Macro Statistics 4 FSMs nb of FSMs Registers nb of registers Tristates nb of tristates Comparators nb of comparators n bit comparator equal not equal greater less greatequal lessequal nb of n bit comparators Multiplexers nb_of_multiplexers n bit m to 1 multiplexer nb of n bit m to 1 multiplexers Adders Subtractors nb of adds subs n bit adder nb of n bit adds n bit subtractor nb of n bit subs Multipliers nb of multipliers Logic Shifters nb of logic shifters Counters nb of counters n bit up down updown counter nb of n bit counters 4 XORs nb of xors Cell Usage BEL
171. Code 169 Initializing RAM From an External Pie 174 Initializing Block RAM External Data File csereinorseinrrs seisseen asns rs 175 ROMs Using Block RAM Resources Hardware Description Language HDL Coding Techniques 177 ROMs Using Block RAM Resources Log Pe 178 ROMs Using Block RAM Resources Related Constramnts eee 178 ROMs Using Block RAM Resources Coding Examples sss 178 Pipelined Distributed RAM Hardware Description Language HDL Coding Techniques 184 Pipelined Distributed RAM Log Pie 186 Pipelined Distributed RAM Related Constratmts eee 186 Pipelined Distributed RAM Coding Bvamples eee 187 Finite State Machine FSM Hardware Description Language HDL Coding Techniques 189 Describing a Finite State Machine FSM Component eee 189 State REPISELS M EESE aN 190 Next State EE 190 Unreachable Statessa Em 190 Finite State Machine FSM OutpUuls eerte reato pos e saepe ho peso a enge bo sdssevesesdbensassdsnadeesseey 190 Finite State Machine FSM Iriputs etes terrier eer nod EES E de HEIN SES RR EY eer 190 State Encodirig I chniqUes eoeeeeciesocecen ek ena aede Reb Ra I GEES ASAE se snuuasdsadedeasssnsialensdsedse 190 Auto State Encoding EE 191 One HOt State EnCodiNg sisses egene EE 191 Gray State Bereet ege EE E E e eege eg 191 Compact EE 191
172. DAMAGES INCLUDING ANY LOSS OF DATA OR LOST PROFITS ARISING FROM YOUR USE OF THE DOCUMENTATION Copyright 2002 2009 Xilinx Inc All Rights Reserved XILINX the Xilinx logo the Brand Window and other designated brands included herein are trademarks of Xilinx Inc All other trademarks are the property of their respective owners The PowerPC name and logo are registered trademarks of IBM Corp and used under license All other trademarks are the property of their respective owners XST User Guide 2 www xilinx com UG627 v 11 3 September 16 2009 XILINX Table of Contents Xilinx Trademarks and Copyright Information 2 Chapter J About the XST User Guide ifsc Segen rn meer hne n EEN 17 XST User Guide Contents 17 Additional Resources EE 17 CONVENTIONS M eege geed EEN geed ech 18 Typographical M 18 Online Domenica 18 Chapter 2 Introduction to Xilinx Synthesis Technology CT 19 Pep P eer 19 What s New tn Release e HH 19 RE EE 19 Chapter 3 XST Hardware Description Language HDL Coding Techniques ccccccccesssseeeeeeeenesteeeeeeees 21 Signed and Unsigned Support 1n X9T terrere teret pensent e na eese EES EES ENEE Oak Kun 22 Registers Hardware Description Language HDL Coding Techniques ssssseee 22 Registers Log Piles sive EEEL 23 Registers Relat
173. DI WIDTH dol lt RAM conv_integer addr 2 DI WIDTH 1 downto 1 DI WIDTH end if if we 0 1 then di0 lt di DI_WIDTH 1 downto 0 do0 lt di DI_WIDTH 1 downto 0 else di0 lt RAM conv_integer addr DI WIDTH 1 downto 0 do0 lt RAM conv_integer addr DI WIDTH 1 downto 0 end if end process process clk begin if clk event and clk 1 then RAM conv integer addr lt dil amp di0 do lt dol amp do0 end if end process end syn XST User Guide 160 www xilinx com UG627 v 11 3 September 16 2009 nuit XST Hardware Description Language HDL Coding Techniques XILINX Write First Mode Single Port BRAM with Byte Wide Write Enable 2 Bytes Verilog Coding Example Single Port BRAM with Byte wide Write Enable 2 bytes in Write First Mode module v_rams_25 clk we addr di do parameter SIZE 512 parameter ADDR_WIDTH 9 parameter DI_WIDTH 8 input clk input 1 0 we input ADDR_WIDTH 1 0 addr input 2 DI_WIDTH 1 0 di output 2 DI_WIDTH 1 0 do reg 2 DI_WIDTH 1 0 RAM SIZE 1 0 reg 2 DI_WIDTH 1 0 do reg DI_WIDTH 1 0 dio dil reg DI_WIDTH 1 0 do0 dol always we or di begin if we 1 begin dil di 2 DI WIDTH 1 1 DI WIDTH dol di 2 DI WIDTH 1 1 DI WIDTH end else begin dil RAM addr 2 DI WIDTH 1 1 DI WIDTH dol RAM addr 2 DI WIDTH 1 1 DI WIDTH end if we 0 begin diO lt di DI_WIDTH 1
174. Description Language HDL Coding Techmioues ssssssesstistssrserrttsssssrerrresnseet 74 pressure 74 Decoders Related Constraints ssssssssssseeeeeee eene ee e enne eH eren enne E iS 75 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 3 XILINX Decoders Coding Examples s sicccseoacdossous 75 Priority Encoders Hardware Description Language HDL Coding Techniques seeeeee 79 Priority Encoders Log Pile cic scsicecscassiectenesstccccesdties cosedsces i ee ssevedscssstovssecsseresscdssvesstecsvebbcbesennsee 79 Priority Encoders Related Constraints c ccccccccssscccscesesissascecsacssisuesessesevesssseseveosautswvassdannessssdendaeasndense 79 Priority Encoders Coding Examples eiecit eee vno SCENE eS HERE ER ENEE EENS 79 3 Bit 1 of 9 Priority Encoder Coding Examples 80 Logical Shifters Hardware Description Language HDL Coding Techniques ssssessssssssrsttstsssrrerresssee 81 Logical Shifters LOS le p M ER Logical Shifters Related Comsttaints cccscissciccscestscevsedaccteesedoeiaesessdseveatuadvtasotsesstannace bao ani e enean 82 Logical Shifters Coding Examples 5 rer eret rer een FO RE e sra Iba e e aea EE 82 Arithmetic Operators Hardware Description Language HDL Coding Techniques esses 86 Arithmetic Operators Log File eie eerte irent tato ne abeo sosbons e rh e ea ede E otia 87 Arithmetic O
175. Drive strengths All drive strengths are ignored e Registers Real and realtime registers are unsupported e Named events All named events are unsupported Verilog Continuous Assignments Supported in XST XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 411 XILINX Chapter t XST Verilog Language Support Verilog Procedural Assignments Supported in XST Verilog Procedural Assignments are supported in XST except as noted below e assign Supported with limitations See Behavioral Verilog Assign and Deassign Statements e deassign Supported with limitations See Behavioral Verilog Assign and Deassign Statements e force Unsupported e release Unsupported e forever statements Unsupported e repeat statements Supported but repeat value must be constant e for statements Supported but bounds must be static e delay Ignored e event Unsupported e wait Unsupported Named Events Unsupported Parallel Blocks Unsupported e Specify Blocks Ignored Disable Supported except in For and Repeat Loop statements Verilog Design Hierarchies Supported in XST Design Hierarchy Supported Unsupported module definition Supported macromodule definition Unsupported hierarchical names Unsupported defparam Supported array of instances Supported XST User Guide 412 www xilinx com UG627 v 11 3 September 16 2009 tapter t XST Verilog Language Support XILINX Verilog Compiler Directives Support
176. E UTILIZATION RATIO MAXMARGIN Applicable Elements 5 ivit ter eb aedes te etra ce Pedir e e ER eI RT 337 Slice LUT FF Pairs Utilization Ratio Delta SLICE UTILIZATION RATIO MAXMARGIN Propagation Rules cit eet RP e ved esee peste I bs ree tiene 337 LUT MAP Map Entity on a Single LUT eee nee nnn nnno nnne EES 338 LUT MAP Map Entity on a Single LUT Architecture Support 338 LUT MAP Map Entity on a Single LUT Applicable Blements esre rrsrrssrrrsrsssrse 338 LUT MAP Map Entity on a Single LUT Propagation Rules sss 338 USE CARRY CHAIN Use Carry Chairn eee eren nant nennen CERS eiie bna ENNEN 339 USE CARRY CHAIN Use Carry Chain Architecture Support sss 339 USE CARRY CHAIN Use Carry Chain Applicable Demenz 339 USE CARRY CHAIN Use Carry Chain Propagation Rule 339 TRISTATE2LOGIC Convert Tristates to Logic eesesee eene 340 TRISTATE2LOGIC Convert Tristates to Logic Architecture Gupport 341 TRISTATE2LOGIC Convert Tristates to Logic Applicable Elements sese 341 TRISTATE2LOGIC Convert Tristates to Logic Propagation Rules sese 341 USE CLOCK ENABLE Use Clock Enable eeesssssssesee e Henne 341 USE CLOCK ENABLE Use Clock Enable Architecture Support 342 USE CLOCK ENABLE Use Clock Enable Applicable Elements sse 342 USE CLOCK ENABLE Use Clock Enable Propagation Rules sss 342 USE SYNC SET Use Synch
177. ER TYPE e Extract BUFGCE BUFGCE e Cores Search Directories sd Decoder Extraction DECODER EXTRACT e DSP Utilization Ratio D5P UTILIZATION RATIO e FSM Style F5M STYLE Power Reduction POWER e Read Cores READ CORES e Logical Shifter Extraction SHIFT EXTRACT e LUT Combining LC e Map Logic on BRAM BRAM MAD e Max Fanout MAX FANOUT e Move First Stage MOVE FIRST STAGE e Move Last Stage MOVE LAST STAGE e Multiplier Style MULT STYLE e Mux Style MUX STYLE e Number of Global Clock Buffers bufg e Number of Regional Clock Buffers bufr Optimize Instantiated Primitives OPTIMIZE PRIMITIVES e Pack I O Registers Into IOBs IOB e Priority Encoder Extraction PRIORITY EXTRACT e RAM Extraction RAM EXTRACT RAM Style RAM STYLE e Reduce Control Sets REDUCE CONTROL SETS e Register Balancing REGISTER BALANCING XST User Guide 244 www xilinx com UG627 v 11 3 September 16 2009 nuit XST Design Constraints Register Duplication REGISTER_DUPLICATION ROM Extraction ROM_EXTRACT ROM Style ROM_STYLE Shift Register Extraction SHREG EXTRACT Slice Packing slice packing XOR Collapsing XOR COLLAPSE Slice LUT FF Pairs Utilization Ratio SLICE UTILIZATION RATIO Slice LUT FF Pairs Utilization Ratio Delta SLICE UTILIZATION RATIO MAXMARGIN Map Entity on a Single LUT LUT MAP Use Carry Chain USE CARRY CHAIN Convert Tristates to Logic TRISTATE2LOGIC Use Cloc
178. ES input clk rst input 3 0 A B output 3 0 RES reg 3 0 RES always posedge clk or posedge rst begin if rst RES lt 4 b0000 else RES lt A B 8 b0001 end endmodule Flip Flop Retiming Flip flop retiming consists of moving flip flops and latches across logic for the purpose of improving timing thus increasing clock frequency Flip flop retiming can be either forward or backward e Forward retiming moves a set of flip flops that are the input of a LUT to a single flip flop at its output e Backward retiming moves a flip flop that is at the output of a LUT to a set of flip flops at its input XST User Guide 212 www xilinx com UG627 v 11 3 September 16 2009 Chapter XST FPGA Optimization XILINX Flip flop retiming can e Significantly increase the number of flip flops e Remove some flip flops Nevertheless the behavior of the designs remains the same Only timing delays are modified Flip flop retiming is part of global optimization It respects the same constraints as all other optimization techniques Since retiming is iterative a flip flop that is the result of a retiming can be moved again in the same direction forward or backward if it results in better timing The only limit for the retiming occurs when the timing constraints are satisfied or if no more improvements in timing can be obtained For each flip flop moved a message is printed specifying e The original and new
179. Example Define in the XST command line as follows xst run use carry chain yes no The default is yes TRISTATE2LOGIC Convert Tristates to Logic Since some devices do not support internal tristates XST automatically replaces tristates with equivalent logic Because the logic generated from tristates can be combined and optimized with surrounding logic the replacement of internal tristates by logic for other devices can lead to better speed and in some cases better area optimization But in general tristate to logic replacement may lead to area increase If the optimization goal is Area you should apply TRISTATE2LOGIC Convert Tristates to Logic set to no TRISTATE2LOGIC values are e yes default no e true XCF only e false XCF only There are some limitations to the TRISTATE2LOGIC constraint Only internal tristates are replaced by logic The tristates of the top module connected to output pads are preserved e TRISTATE2LOGIC does not apply to technologies that do not have internal tristates such as Spartan 3 devices or Virtex 4 devices In this case the conversion of tristates to logic is performed automatically In some situations XST is unable to make the replacement automatically due to the fact that this may lead to wrong design behavior or multi source This may happen when the hierarchy is preserved or XST does not have full design visibility for example design is synthesized on a block by block basi
180. HDL Options Safe Implementation e Hardware Description Language HDL Apply SAFE_IMPLEMENTATION to the hierarchical block or signal that represents the state register in the FSM SAFE_IMPLEMENTATION Safe Implementation Architecture Support Architecture independent SAFE_IMPLEMENTATION Safe Implementation Applicable Elements Applies to an entire design through the XST command line to a particular block entity architecture component or to a signal XST User Guide 294 www xilinx com UG627 v 11 3 September 16 2009 Chapter t XST Design Constraints XILINX SAFE_IMPLEMENTATION Safe Implementation Propagation Rules Applies to the entity component module or signal to which it is attached SAFE_IMPLEMENTATION Safe Implementation Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it SAFE_IMPLEMENTATION Safe Implementation VHDL Syntax Example Declare as follows attribute safe_implementation string Specify as follows attribute safe implementation of entity name component name signal name entity component signal is yes no SAFE IMPLEMENTATION Safe Implementation Verilog Syntax Example Place immediately before the module or signal declaration safe implementation yes noj zi SAFE IMPLEMENTATION Safe Implementation XST Constraint File XCF Synta
181. Hierarchy as_optimized RTL Output Yes Hierarchy Separator Bus Delimiter lt gt Case Specifier maintain Verilog 2001 YES Other Options Clock Enable YES wysiwyg NO Chapter 11 XST Log File HDL Compilation Compiling verilog file smallcntr v in library work Compiling verilog file tenths v in library work Module lt smallcntr gt compiled Compiling verilog file statmach v in library work Module tenths compiled Compiling verilog file hex2led v in library work Module lt statmach gt compiled Compiling verilog file decode v in library work Module lt hex2led gt compiled Compiling verilog file cnt60 v in library work Module decode compiled Compiling verilog file stopwatch v in library work Module lt cnt60 gt compiled 466 www xilinx com XST User Guide UG627 v 11 3 September 16 2009 Chapter ti XST Log File XILINX Module lt stopwatch gt compiled No errors in compilation Analysis of file lt stopwatch prj gt succeeded Design Hierarchy Analysis Analyzing hierarchy for module lt stopwatch gt in library lt work gt Analyzing hierarchy for module lt statmach gt in library lt work gt with parameters clear 000001 counting 001000 start 000100 stop 010000 stopped 100000 zero 000010 Analyzing hierarchy for module lt tenths gt in library lt work gt Analyzing hierarchy for
182. ILINX nuit t XST Design Constraints XST Supported Third Party Constraints This section describes constraints of third party synthesis vendors that are supported by XST XST Equivalents to Third Party Constraints This section shows the XST equivalent for each of the third party constraints For specific information on these constraints see the vendor documentation Several third party constraints are automatically supported by XST as shown in the table below Constraints marked yes are fully supported If a constraint is only partially supported the support conditions are shown in the Automatic Recognition column The following rules apply e VHDL uses standard attribute syntax No changes are needed to the Hardware Description Language HDL code For Verilog with third party metacomment syntax the metacomment syntax must be changed to conform to XST conventions The constraint name and its value can be used as shown in the third party tool e For Verilog 2001 attributes no changes are needed to the HDL code The constraint is automatically translated as in the case of VHDL attribute syntax XST Equivalents to Third Party Constraints Jean E Jeer Vendor XST Equivalent Recognition Available For NAA retum port name retum port name name Synopsys resource sharing Synopsys Resource mo m mo directives ee a XST User Guide 360 www xilinx com UG627 v 11 3 September 16 2009 h
183. ILINX Chapter 1 XST FPGA Optimization Timing Report Example These timing numbers are only a synthesis estimate For accurate timing information see the TRACE report generated after place and route Clock Information 4 4 Clock Signal Clock buffer FF name Load 4 4 CLK BUFGP ARE 4 4 Asynchronous Control Signals Information 4 4 Control Signal Buffer FF name Load 2 2 2 2 4p 2 4 4 rstint MACHINE current state Out01 0 NONE sixty lsbcount qoutsig 3 4 RESET IBUF 3 sixty msbclr sixty msbclr 0O NONE sixty msbcount qoutsig 3 4 4 4 V Speed Grade 12 Minimum period 2 644ns Maximum Frequency 378 165MHz Minimum input arrival time before clock 2 148ns Maximum output required time after clock 4 803ns Maximum combinational path delay 4 473ns Timing Detail All values displayed in nanoseconds ns Timing constraint Default period analysis for Clock CLK Clock period 2 644ns frequency 378 165MHz Total number of paths destination ports 77 11 Delay 2 644ns Levels
184. IMEGRP group name FROM TO From To From To FROM TO defines a timing constraint between two groups A group can be user defined or predefined FFS PADS RAMS For more information see FROM TO in the Constraints Guide From To XST Constraint File XCF Syntax Example TIMESPEC TSname FROM groupl TO group2 value TNM Timing Name TNM Timing Name is a basic grouping constraint Use TNM to identify the elements that make up a group which you can then use in a timing specification TNM tags specific FFS RAMs LATCHES PADS BRAMS_PORTA BRAMS_PORTB CPUS HSIOS and MULTS as members of a group to simplify the application of timing specifications to the group The RISING and FALLING keywords may also be used with TNM constraints For more information see TNM in the Constraints Guide TNM Timing Name Syntax Examples INST NET PIN inst_net_or_pin_name TNM predefined_group identifier TNM NET Timing Name on a Net TNM NET Timing Name on a Net is essentially equivalent to TNM on a net except for input pad nets Special rules apply when using TNM NET with the PERIOD constraint for DLL DCMs For more information see PERIOD Specifications on CLKDLLs and DCMs in the Constraints Guide A INM NET is a property that you normally use in conjunction with a Hardware Description Language HDL design to tag a specific net All downstream synchronous elements and pads tagged with the TNM NET identifier are considered a grou
185. INX cross_clock_analysis Cross Clock Analysis Syntax xst run cross_clock_analysis yes no cross_clock_analysis Cross Clock Analysis Syntax Example xst run cross_clock_analysis yes Tells XST to perform inter clock domain analysis during timing optimization write_timing_constraints Write Timing Constraints Timing constraints are written to the NGC file only when Write Timing Constraints is checked yes in ISE Design Suite inProcess gt Properties or The write_timing_constraints option is specified when using the command line Timing constraints are not written to the NGC file by default Wwrite timing constraints Write Timing Constraints Architecture Support Architecture independent Wwrite timing constraints Write Timing Constraints Applicable Elements Applies to an entire design through the XST command line Wwrite timing constraints Write Timing Constraints Propagation Rules Not applicable write timing constraints Write Timing Constraints Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it write timing constraints Write Timing Constraints XST Command Line Syntax Example Define in the XST command line as follows xst run write timing constraints yes no The default is yes write timing constraints Write Timing Constraints ISE Design Suite Syntax Examp
186. ISTER_DUPLICATION Register Duplication REGISTER_DUPLICATION Register Duplication enables or disables register replication REGISTER_DUPLICATION values are e yes default no e true XCF only e false XCF only The default is yes Register replication is enabled and is performed during timing optimization and fanout control REGISTER DUPLICATION Register Duplication Architecture Support Applies to all FPGA devices Does not apply to CPLD devices REGISTER DUPLICATION Register Duplication Applicable Elements Applies to the entire design or to an entity component module or signal REGISTER DUPLICATION Register Duplication Propagation Rules Applies to the entity or module to which it is attached REGISTER DUPLICATION Register Duplication Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it REGISTER DUPLICATION Register Duplication VHDL Syntax Example Declare as follows attribute register duplication string Specify as follows attribute register duplication of entity name entity is yes no REGISTER DUPLICATION Register Duplication Verilog Syntax Example Place immediately before the module declaration or instantiation register duplication yes no zi REGISTER DUPLICATION Register Duplication XST Constraint File XCF Syntax Example One MODEL entity name r
187. IVES YES Keep KEEP If applied to the output flip flop signal the flip flop is not moved forward Applied to the Input Flip Flop Signal SE H LUT OH LUT FF p 7 x95065 If applied to the input flip flop signal the flip flop is not moved backward bh b ra i o Lei xo562 If applied to both the input and output of the flip flop it is equivalent to REGISTER BALANCING no REGISTER BALANCING Register Balancing Architecture Support Applies to all FPGA devices Does not apply to CPLD devices XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 327 XILINX nuit t XST Design Constraints REGISTER_BALANCING Register Balancing Applicable Elements Applies to e The entire design using the command line or ISE Design Suite e Anentity or module e A signal corresponding to the flip flop description RTL e A flip flop instance e The Primary Clock Signal In this case the register balancing is performed only for flip flops synchronized by this clock REGISTER_BALANCING Register Balancing Propagation Rules Applies to the entity component module or signal to which it is attached REGISTER_BALANCING Register Balancing Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it REGISTER_BALANCING Register Balancing VHDL Syntax Example Declare as follows at
188. L LOGICAL Cell Usage The LOGICAL group in the Cell Usage section of the Final Report contains all the logical cells primitives that are not basic elements e AND2 e OR2 XST User Guide 216 www xilinx com UG627 v 11 3 September 16 2009 Chapter t XST FPGA Optimization XILINX OTHER Cell Usage The OTHER group in the Cell Usage section of the Final Report contains all the cells that have not been classified in the previous groups Cell Usage Report Example Cell Usage BELS 70 LUT2 34 d LUT3 E3 d LUT4 34 FlipFlops Latches GK FDC 8 d FDP 1 Clock Buffers gt 1 BUFGP zs I IO Buffers 24 d IBUF 16 OBUF 8 Where XST estimates the number of slices and gives for example the number of flip flops IOBs and BRAMS This report is very close to the one produced by MAP A short table gives information about the number of clocks in the design how each clock is buffered and how many loads it has A short table gives information about the number of asynchronous set reset signals in the design how each signal is buffered and how many loads it has Timing Report At the end of synthesis XST reports the timing information for the design The Timing Report shows the information for all four possible domains of a netlist register to register e input to register register to outpad e inpad to outpad XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 217 X
189. LE Timing Summary Speed Grade 12 Minimum period 2 282ns Maximum Frequency 438 212MHz Minimum input arrival time before clock 1 655ns Maximum output required time after clock 4 617ns Maximum combinational path delay No path found Timing Detail All values displayed in nanoseconds ns Timing constraint Default period analysis for Clock CLK Clock period 2 282ns frequency 438 212MHz Total number of paths destination ports 134 21 Delay 2 282ns Levels of Logic 4 Source xcounter BU2 U0 q_i_1 FF Destination sixty msbcount QOUT_1 FF Source Clock CLK rising Destination Clock CLK rising Data Path xcounter BU2 U0 q_i_1 to sixty msbcount QOUT_1 Gate Net Cell in gt out fanout Delay Delay Logical Name Net Name FDCE C gt Q 12 0 272 0 672 U0 q i 1 q 1 LUT4 10 gt O 11 0 147 0 492 U0 thresh0 i cmp eq00001 thresh0 end scope BU2 end scope xcounter LUT4_D 13 gt 0 1 0 147 0 388 sixty msbce sixty msbce LUT3 12 gt 0 1 0 147 0 000 sixty msbcount OOUT 1 rstpot sixty msbcount OOUT 1 rstpot FDC D 0 017 sixty msbcount OOUT 1 Total 2 282ns 0 730ns logic 1 552ns route 32 0 logic 68 0 route XILINX XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 463 XILINX Chapter 11 XST Log File Timing constraint Default OFFSET IN BEFORE for Clock CLK Total number of paths destination ports 4 3
190. Libraries In Verilog the UNISIM library is precompiled XST automatically links it with your design XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 221 XILINX Chapter 4 XST FPGA Optimization Primitive Instantiation Guidelines Use UPPERCASE for generic VHDL and parameter Verilog values when instantiating primitives For example the ODDR element has the following component declaration in the UNISIM library component ODDR generic DDR CLK EDGE string OPPOSITE EDGE INIT bit 0 SRTYPE string SYNC port Q out std ulogic Cos in std ulogic CE in std ulogic D1 in std ulogic D2 in std ulogic R in std ulogic S in std ulogic end component When you instantiate this primitive in your code the values of DDR CLK EDGE and SRTYPE generics must be in uppercase If not XST issues a warning stating that unknown values are used Some primitives such as LUT1 enable you to use an INIT during instantiation The two ways to pass an INIT to the final netlist are e Attach an INIT attribute to the instantiated primitive e Pass the INIT with the generics mechanism VHDL or the parameters mechanism Verilog Xilinx recommends this method since it allows you to use the same code for synthesis and simulation Reporting of Instantiated Device Primitives XST does not issue any message concerning instantiation of instantiated device primitives during HDL synthesis beca
191. MODEL entity name mux_style auto muxf muxcy MUX STYLE Mux Style XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name NET signal name mus style auto muxf muxcy END MUX STYLE Mux Style XST Command Line Syntax Example Define in the XST command line as follows xst run mux style auto muxf muxcy DOCTYPE command auto MUX STYLE Mux Style ISE Design Suite Syntax Example Define in ISE Design Suite with Process Properties HDL Options Mux Style bufg Number of Global Clock Buffers bufg Number of Global Clock Buffers controls the maximum number of BUFGs created by XST The value is an integer The default value depends on the target device and is equal to the maximum number of available BUFGs bufg Number of Global Clock Buffers Architecture Support Applies to all FPGA devices Does not apply to CPLD devices bufg Number of Global Clock Buffers Applicable Elements Applies to the entire design bufg Number of Global Clock Buffers Propagation Rules Not applicable To set the number of global clock buffers in ISE Design Suite 1 Select Process gt Properties gt Xilinx Specific Options 2 From the Property display level list select Advanced 3 Set the Number of Clock Buffers property bufg Number of Global Clock Buffers Syntax The value is an integer and cannot exceed the maximum number of BUFGs available in the target device The default values
192. Mmult_mult gt synthesized advanced HDL Synthesis Report Macro Statistics MACs tx 8x8 to 16 bit MAC e Z XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 113 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Multiply Adder Subtractors Related Constraints Use DSP48 USE_DSP48 e DSP Utilization Ratio DSP_UTILIZATION_RATIO e Keep KEEP Multiply Adder Subtractors Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip Multiplier Adder With 2 Register Levels on Multiplier Inputs Diagram 8 ji TTL Re CLK ADD_SUB Multiplier Adder With 2 Register Levels on Multiplier Inputs Pin Descriptions Positive Edge Clock MULT Add Operands MULT Add Result XST User Guide 114 www xilinx com UG627 v 11 3 September 16 2009 Chipter1 XST Hardware Description Language HDL Coding Techniques XILINX Multiplier Adder With 2 Register Levels on Multiplier Inputs VHDL Coding Example Multiplier Adder with 2 Register Levels on Multiplier Inputs library IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD LOGIC UNSIGNED ALL entity multipliers 5 is generic p width integer 8 port clk in std logic A B C in std logic vector p width 1 downto 0 RES out std logic vector p width 2 1 downto 0 end multipliers 5 architecture beh o
193. OPTIMIZE PRIMITIVES Optimize Instantiated Primitives sss 319 OPTIMIZE PRIMITIVES Optimize Instantiated Primitives Architecture Support 320 OPTIMIZE PRIMITIVES Optimize Instantiated Primitives Applicable Elements 320 OPTIMIZE PRIMITIVES Optimize Instantiated Primitives Propagation Rules 320 TOB Pack I O Registers Into IOBSs eet so ce ario eo deno eene ENNEA ee ERASE SERERE 320 PRIORITY EXTRACT Priority Encoder Extraction eee 321 PRIORITY EXTRACT Priority Encoder Extraction Architecture Support sss 321 PRIORITY EXTRACT Priority Encoder Extraction Applicable Elements sess 321 PRIORITY EXTRACT Priority Encoder Extraction Propagation Rules sess 321 RAM EXIRACT RAM BXtrattlOD ccu tero either rh eere rae Har de ER RENE EYRE ENEE 322 RAM EXTRACT RAM Extraction Architecture Support ssssssssssseeee 322 RAM EXTRACT RAM Extraction Applicable Elements 322 RAM EXTRACT Propagation Rules eeeeeeee eee nennen nennen 322 RAM STYLE RAM Style ness correr EU Pebe tee ha OE ERE Cen EAE ee Eege 323 RAM STYLE RAM Style Architecture Support 323 RAM STYLE RAM Style Applicable Elements sssse eH 323 RAM STYLE RAM Style Propagation Rules e 324 REDUCE CONTROL SETS Reduce Control Sete ene nennen 324 REDUCE CONTROL SETS Reduce Control Sets A
194. P48 USE DSPA48 is set to no use mult style pipe lut KCM CSD to define the multiplier implementation method on LUTs To deliver the best performance XST by default tries to infer and implement the maximum macro configuration including as many registers in the DSP48 as possible To shape a macro in a specific way use the Keep KEEP constraint For example to exclude the first register stage from the DSP48 place Keep KEEP constraints on the outputs of these registers XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 99 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Multiplication with Constant When one of the arguments is a constant XST can create efficient dedicated implementations of a multiplier with a constant using two methods e Constant Coefficient Multiplier KCM e Canonical Signed Digit CSD Dedicated implementations do not always provide the best results for multiplication with constants XST can automatically choose between KCM or standard multiplier implementation The CSD method cannot be automatically chosen Use the Mux Style MUX_STYLE constraint to force CSD implementation XST does not support KCM or CSD implementation for signed numbers If the either of the arguments is larger than 32 bits XST does not use KCM or CSD implementation even if it is specified with the Multiplier Style MULT_STYLE constraint Multipliers Log File The XST log file r
195. P_UTILIZATION_RATIO DSP Utilization Ratio Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it DSP_UTILIZATION_RATIO DSP Utilization Ratio XST Command Line Syntax Example Define in the XST command line as follows dsp utilization ratio integer where integer is 1 to 100 when is used or both and are omitted To specify a percent of total slices use To specify an absolute number of slices use The default is For example e To specify 50 of DSP blocks of the target device enter the following dsp utilization ratio 50 e To specify 50 of DSP blocks of the target device enter the following dsp utilization ratio 50 e To specify 50 DSP blocks enter the following dsp utilization ratio 50i Note There must be no space between the integer value and the percent or pound characters DSP UTILIZATION RATIO DSP Ultilization Ratio ISE Design Suite Syntax Example Define in ISE Design Suite with XST User Guide 304 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST Design Constraints XILINX Process gt Properties gt Synthesis Options gt DSP Utilization Ratio In ISE Design Suite you can define the value of DSP Utilization Ratio only as a percentage You can not define the value as an absolute number of slices FSM_STYLE FSM Style FSM_STYLE FSM Style
196. Propagation Rules Not applicable FULL CASE Full Case Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it FULL CASE Full Case Verilog Syntax Example The syntax is full case Since PULL CASE does not contain a target reference the attribute immediately precedes the selector full case casex select 4 blxxx res datal 4 bx1xx res data2 4 bxxlx res data3 4 pxxxl res data4 endcase FULL CASE is also available as a meta comment in the Verilog code The syntax differs from the standard meta comment syntax as shown in the following synthesis full_case Since FULL_CASE does not contain a target reference the meta comment immediately follows the selector casex select 4 b1xxx res synthesis full_case datal uo dg dg dg s 4 bxlxx res data2 4 bxxlx res data3 4 pxxxl res data4 endcase XST User Guide 270 www xilinx com UG627 v 11 3 September 16 2009 taptir i XST Design Constraints XILINX FULL_CASE Full Case XST Command Line Syntax Example Define in the XST command line as follows vlgcase full parallel full parallel FULL_CASE Full Case ISE Design Suite Syntax Example Note For Verilog files only Define in ISE Design Suite with Process gt Properties gt Synthesis Options gt Full Case For Case Implementation Styl
197. R begin if CLR tmp 4 p0000 else tmp tmp D end assign Q tmp endmodule XST User Guide 50 www xilinx com UG627 v 11 3 September 16 2009 Chipter XST Hardware Description Language HDL Coding Techniques XILINX Shift Registers Hardware Description Language HDL Coding Techniques In general a shift register is characterized by the following control and data signals which are fully recognized by XST e Clock Serial input e Asynchronous set reset e Synchronous set reset e Synchronous asynchronous parallel load e Clock enable e Serial or parallel output The shift register output mode may be Serial Only the contents of the last flip flop are accessed by the rest of the circuit Parallel The contents of one or several flip flops other than the last one are accessed e Shift modes for example left right Describing Shift Registers Ways to describe shift registers in VHDL include e Concatenation operator shreg lt shreg 6 downto 0 amp SI e For loop construct for i in 0 to 6 loop shreg it l lt shreg i end loop shreg 0 lt SI e Predefined shift operators for example SLL or SRL For more information see your VHDL and Verilog language reference manuals Implementing Shift Registers Hardware Resources to Implement Shift Registers SRL16 SRL16E SRLC16 SRLC16E SRLC32E Spartan 3 Spartan 3E asia 3A wos e he Mer e c he 348 509 118 3 SRL
198. R Preserve pld xp pld ce Clock Enable pld ce Clock Enable specifies how sequential logic should be implemented when it contains a clock enable either using the specific device resources available for that or generating equivalent logic Clock Enable values are yes The synthesizer implements the clock enable signal of the device no The clock enable function is implemented through equivalent logic Keeping or not keeping the clock enable signal depends on the design logic Sometimes when the clock enable is the result of a Boolean expression setting Clock Enable to no may improve the fitting result The input data of the flip flop is simplified when it is merged with the clock enable expression pld ce Clock Enable Architecture Support Applies to all CPLD devices Does not apply to FPGA devices pld ce Clock Enable Applicable Elements Applies to an entire design through the XST command line pld ce Clock Enable Propagation Rules Not applicable Set this value in ISE Design Suite in Process gt Properties gt Xilinx Specific Options gt Clock Enable pld ce Clock Enable Syntax xst run pld ce yes no The default is yes pld ce Clock Enable Syntax Example xst run pld ce yes Defines Clock Enable globally to yes so that the clock enable function is implemented through equivalent logic DATA GATE Data Gate Data Gate DATA GATE provides direct means of reducing power consumption in yo
199. RAM Style RAM_STYLE attribute can also be global If the RAM resources are limited XST can generate additional RAMs using registers To generate additional RAMs using registers use RAM Extraction RAM_EXTRACT with the value set to no ROMs in Macro Generation A ROM can be inferred when all assigned contexts in a Case or If else statement are constants Macro inference considers only ROMs of at least 16 words with no width restriction For example the following Hardware Description Language HDL equation can be implemented with a ROM of 16 words of 4 bits 0000 then 0010 0001 then 1100 0010 then 1011 data if address if address if address uon og if address 1111 then 0001 A ROM can also be inferred from an array composed entirely of constants as shown in the following coding example type ROM TYPE is array 15 downto 0 of std logic vector 3 downto 0 constant ROM rom type 0010 1100 1011 0001 data lt ROM conv integer address ROM Extraction ROM EXTRACT can be used to disable the inference of ROMs Set the value to yes to enable ROM inference Set the value to no to disable ROM inference The default is yes XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 207 XILINX Chapter 4 XST FPGA Optimization Two types of ROM are available during inference and generation e Distributed ROM Distributed ROMs are generated by using the optimal tree structure of LU
200. ROR Xst 719 filel vhd Line 172 Operator is not supported yet DIVIDE Dividers Related Constraints None Dividers Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip XST User Guide 122 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX Division by Constant 2 Divider Diagram Division by Constant 2 Divider Pin Descriptions n Desrpton 9 T Division by Constant 2 Divider VHDL Coding Example Division By Constant 2 library ieee use ieee std logic 1164 all use ieee numeric std all entity divider 1 is port DI in unsigned 7 downto 0 DO out unsigned 7 downto 0 end divider 1 architecture archi of divider 1 is begin DO lt DI 2 end archi Division by Constant 2 Divider Verilog Coding Example ere Division By Constant 2 module v divider 1 DI DO input 7 0 DI output 7 0 DO assign DO DI 2 endmodule Resource Sharing Hardware Description Language HDL Coding Techniques The goal of resource sharing also known as folding is to minimize the number of operators and the subsequent logic in the synthesized design This optimization is based on the principle that two similar arithmetic resources may be implemented as one single arithmetic operator if they are never used a
201. R_COLLAPSE XOR Collapsing XST Command Line Syntax Example Define in the XST command line as follows xst run xor_collapse yes no The default is yes XOR_COLLAPSE XOR Collapsing ISE Design Suite Syntax Example Define in ISE Design Suite with Process gt Properties gt HDL Options gt XOR Collapsing Slice LUT FF Pairs Utilization Ratio SLICE_UTILIZATION_RATIO Slice LUT FF Pairs Utilization Ratio SLICE_UTILIZATION_RATIO defines the area size in absolute numbers or percent of total numbers of e LUT FF pairs Virtex 5 devices e slices all other devices that XST must not exceed during timing optimization If the area constraint cannot be satisfied XST will make timing optimization regardless of the area constraint To disable automatic resource management specify 1 as a constraint value For more information see Speed Optimization Under Area Constraint Slice LUT FF Pairs Utilization Ratio SLICE_UTILIZATION_RATIO Architecture Support Applies to all FPGA devices Does not apply to CPLD devices Slice LUT FF Pairs Utilization Ratio SLICE_UTILIZATION_RATIO Applicable Elements Applies to the entire design or to an entity component module or signal Slice LUT FF Pairs Utilization Ratio SLICE_UTILIZATION_RATIO Propagation Rules Applies to the entity or module to which it is attached Slice LUT FF Pairs Utilization Ratio SLICE_UTILIZATION_RATIO Syntax Examples The following example
202. Register Balancing moves a flip flop at the output of a LUT to a set of flip flops at its inputs u 5 X566 As a consequence the number of flip flops in the design can be increased or decreased The new flip flop has the same name as the original flip flop with an indexed suffix as shown in the following OriginalFFName BRBId XST User Guide 326 www xilinx com UG627 v 11 3 September 16 2009 taptir i XST Design Constraints XILINX Register Balancing values are yes Both forward and backward retiming are allowed no default Neither forward nor backward retiming is allowed forward Only forward retiming is allowed backward Only backward retiming is allowed e true XCF only e false XCF only Two additional constraints control register balancing e Move First Stage MOVE FIRST STAGE e Move Last Stage MOVE LAST STAGE Several other constraints also influence register balancing e Keep Hierarchy KEEP HIERARCHY If the hierarchy is preserved flip flops are moved only inside the block boundaries If the hierarchy is flattened flip flops may leave the block boundaries e Pack I O Registers Into IOBs IOB If IOB TRUE register balancing is not applied to the flip flops having this property Optimize Instantiated Primitives OPTIMIZE PRIMITIVES Instantiated flip flops are moved only if OPTIMIZE PRIMITIVES YES e Flip flops are moved across instantiated primitives only if OPTIMIZE PRIMIT
203. Rules Applies to the entity component module or signal to which it is attached SHREG EXTRACT Shift Register Extraction Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it XST User Guide 332 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST Design Constraints XILINX SHREG_EXTRACT Shift Register Extraction VHDL Syntax Example Declare as follows attribute shreg_extract string Specify as follows attribute shreg_extract of signal_name entity_name signal entity is yes no SHREG_EXTRACT Shift Register Extraction Verilog Syntax Example Place immediately before the module or signal declaration shreg extract yes no zi SHREG_EXTRACT Shift Register Extraction XST Constraint File XCF Syntax Example One MODEL entity name shreg_extract yes no true false SHREG EXTRACT Shift Register Extraction XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name NET signal name shreg_extract yes no true false END SHREG EXTRACT Shift Register Extraction XST Command Line Syntax Example Define in the XST command line as follows xst run shreg extract yes no The default is yes SHREG EXTRACT Shift Register Extraction ISE Design Suite Syntax Example Define in ISE Design Suite with Process Properties HDL Op
204. S nb of bels AND nb of and OR a EE OF ee INV nb_of_inv XOR2 nb_of_xor2 GND nb_of_gnd VCC nb of vcc FlipFlops Latches nb of ff latch ED nb of fdiis LD nb of ld Tri States nb of tristates BUFE nb of bufe BUFT nb of buft IO Buffers nb of iobuffers IBUF nb of ibuf OBUF nb of obuf IOBUF nb of iobuf OBUFE nb of obufe OBUFT nb of obuft Others nb of others XST User Guide 236 www xilinx com UG627 v 11 3 September 16 2009 taptir i XST CPLD Optimization XILINX CPLD Synthesis Constraints The constraints attributes specified in the Hardware Description Language HDL design or in the constraint files are written by XST into the NGC file as signal properties Improving Results in CPLD Synthesis XST produces optimized netlists for the CPLD fitter which e Fits them in specified devices e Creates the download programmable files The CPLD low level optimization of XST consists of e Logic minimization e Subfunction collapsing e Logic factorization e Logic decomposition Optimization results in an NGC netlist corresponding to Boolean equations The CPLD fitter reassembles these equations to fit the best of the macrocell capacities A special XST optimization process known as equation shaping is applied for XC9500 and XC9500XL devices when the following options are selected e Keep Hierarchy No e Optimization Effort 2 or High e Macro Preserve No T
205. SHARING Resource Sharing RESOURCE SHARING Resource Sharing enables or disables resource sharing of arithmetic operators RESOURCE SHARING values are e yes default no force e true XCF only e false XCF only RESOURCE SHARING Resource Sharing Architecture Support Architecture independent RESOURCE SHARING Resource Sharing Applicable Elements Applies to the entire design or to design elements XST User Guide 292 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST Design Constraints XILINX RESOURCE_SHARING Resource Sharing Propagation Rules Applies to the entity component module or signal to which it is attached RESOURCE_SHARING Resource Sharing Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it RESOURCE_SHARING Resource Sharing VHDL Syntax Example Declare as follows attribute resource_sharing string Specify as follows attribute resource sharing of entity_name entity is yes no RESOURCE SHARING Resource Sharing Verilog Syntax Example Place immediately before the module declaration or instantiation resource sharing yes no zi RESOURCE SHARING Resource Sharing XST Constraint File XCF Syntax Example One MODEL entity name resource sharing yes no true false RESOURCE SHARING Resource Sharing XST Constraint Fi
206. SP48 USE_DSP48 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 247 XILINX nuit t XST Design Constraints Setting Hardware Description Language HDL Options for CPLD Devices To set Hardware Description Language HDL options for CPLD devices in ISE Design Suite select Process gt Properties gt Synthesize XST gt Options The following HDL Options can be set for CPLD devices e FSM Encoding Algorithm FSM_ENCODING e Safe Implementation SAFE IMPLEMENTATION e Case Implementation Style vlgcase e Mux Extraction MUX EXTRACT e Resource Sharing RESOURCE SHARING Setting Xilinx Specific Options You can set Xilinx specific options for e FPGA devices e CPLD devices Setting Xilinx Specific Options for FPGA Devices To set Xilinx specific options for FPGA devices in ISE Design Suite select Process gt Properties gt Synthesis Options gt Xilinx Specific Options The following Xilinx specific options can be set for FPGA devices e Add I O Buffers iobuf e LUT Combining LC e Max Fanout MAX FANOUT e Register Duplication REGISTER DUPLICATION e Reduce Control Sets REDUCE CONTROL SETS e Equivalent Register Removal EOUIVALENT REGISTER REMOVAL e Register Balancing REGISTER BALANCINC e Move First Stage MOVE FIRST STAGE e Move Last Stage MOVE LAST STAGE e Convert Tristates to Logic TRISTATE2LOGIC Convert Tristate to Logic appears only when working with devices with internal
207. ST 411 Verilog Procedural Assignments Supported in XST sssssssssssseee eee 412 Verilog Design Hierarchies Supported in AT 412 Verilog Compiler Directives Supported in AT 413 Verilog System Tasks and Functions Supported in SD 413 Verilog Tt nm 414 Verilog Reserved Keywords vii cates 415 Venlog 2001 Support in XSI ee 416 Chapter 9 XST Behavioral Verilog Language Support eene 417 Behavioral Verilog Variable Declarations em en e n e n eene 417 Behavioral Verilog Initial Values rtc eere acusscavescusienvicee souvnsacessnassa dessanasceessenss 418 Behavioral Verilog Local Reset ettet tatiecsssssocpusasssivesasssascgessssatevesersscersswsdeiensssbeedeatecdsneseaestees 418 Behavioral Verilog Arrays Coding Examples ssssssssssseeeeeeee e ee e ener 419 Behavioral Verilog Multi Dimensional Arrays e e e ne ee nennen 419 Behavioral Verilog Data s 419 Behavioral Verilog Legal Statements sss eee eee ee eren eee eren enne 420 Behavioral Verilog EXpressiOns ceno eres sisisi snas aea es bae anao eo on aoi e eee S RE KE RENE EE n aeria ege a Pee ae EE ES 421 Operators Supported in Behavioral Verilog eeesessss eee 421 Expressions Supported in Behavioral Verilog sse en 421 Results of Evaluating Expressions in Behavioral Verilog ssssssss 423 Behavioral sullo c
208. ST Hardware Description Language HDL Coding Techniques Initializing Block RAM External Data File VHDL Coding Example In the following coding example the loop that generates the initial value is controlled by testing that we are in the RAM address range The following coding examples show initializing Block RAM from an external data file Initializing Block RAM from external data file library ieee use ieee std logic 1164 all use ieee std logic unsigned all use std textio all entity rams 20c is port clk in std logic we in std logic addr in std logic vector 5 downto 0 din in std logic vector 31 downto 0 dout out std logic vector 31 downto 0 end rams 20c architecture syn of rams 20c is type RamType is array 0 to 63 of bit vector 31 downto 0 impure function InitRamFromFile RamFileName in string return RamType is FILE RamFile text is in RamFileName variable RamFileLine line variable RAM RamType begin for I in RamType range loop readline RamFile RamFileLine read RamFileLine RAM I end loop return RAM end function signal RAM RamType InitRamFromFile rams 20c data begin process clk begin if clk event and clk 1 then if we 1 then RAM conv integer addr lt to bitvector din end if dout lt to stdlogicvector RAM conv integer addr end if end process end syn If there are not enough lines in the external data file XST iss
209. ST supports wildcards and hierarchical names with these constraints Writing Constraints to the NGC File Timing constraints are not written to the NGC file by default Timing constraints are written to the NGC file only when Write Timing Constraints is checked yes in ISE Design Suite in Process Properties or e The write timing constraints option is specified when using the command line Additional Options Affecting Timing Constraint Processing Three additional options affect timing constraint processing regardless of how the timing constraints are specified e Cross Clock Analysis cross clock analysis e Write Timing Constraints write timing constraints e Clock Signal CLOCK SIGNAL cross clock analysis Cross Clock Analysis cross clock analysis Cross Clock Analysis tells XST to perform inter clock domain analysis during timing optimization By default no XST does not perform this analysis cross clock analysis Cross Clock Analysis Architecture Support Applies to all FPGA devices Does not apply to CPLD devices cross clock analysis Cross Clock Analysis Applicable Elements Applies to the entire design cross clock analysis Cross Clock Analysis Propagation Rules Not applicable Set this value in ISE Design Suite in Process gt Properties gt Synthesis Options gt Cross Clock Analysis XST User Guide 352 www xilinx com UG627 v 11 3 September 16 2009 taptir i XST Design Constraints XIL
210. Setting XST Options About XST Xilinx Synthesis Technology XST is a Xilinx application that synthesizes Hardware Description Language HDL designs to create Xilinx specific netlist files called NGC files The NGC file is a netlist that contains both logical design data and constraints The NGC file takes the place of both Electronic Data Interchange Format EDIF and Netlist Constraints File NCF files For more information about XST see Xilinx Synthesis Technology XST Frequently Asked Questions FAQ Search for keyword XST FAQ What s New in Release 11 1 Following are the major changes to XST for Release 11 1 e Added new value soft for the KEEP constraint While this value instructs XST to preserve a designated net the KEEP constraint is not propagated to the synthesized netlist e Support for the Synplicity syn keep constraint has been better aligned with the way it is treated by Synplify A syn keep constraint still prevents XST from removing a designated signal However XST no longer propagates the constraint to the synthesized netlist allowing placement and routing to optimize away this net if needed e XST now supports Partitions in place of Incremental Synthesis Incremental Synthesis is no longer supported The incremental synthesis and resynthesize constraints are no longer supported For more information on Partitions see the ISE Design Suite Help Setting XST Options Before synthesizing your design you
211. T reg 35 0 MULT reg 17 0 a_in b_in wire 35 0 mult_res reg 35 0 pipe_l pipe_2 pipe_3 assign mult_res a_in b_in always posedge clk begin a in lt A b in lt B pipe 1 lt mult res pipe 2 pipe 1 pipe 3 pipe 2 MULT pipe 3 end endmodule Pipelined Multiplier Inside Single Pin Descriptions 10 Pins jBesrpio Cd clk Positive Edge Clock MULT MULT Result XST User Guide 108 www xilinx com UG627 v 11 3 September 16 2009 Chapter 3 XST Hardware Description Language HDL Coding Techniques XILINX Pipelined Multiplier Inside Single VHDL Coding Example Pipelined multiplier The multiplication operation placed inside the process block and the pipeline stages represented SES as single registers library ieee use ieee std logic 1164 all use ieee numeric std all entity multipliers 3 is generic A port size integer 18 B port size integer 18 port clk in std logic A in unsigned A port size 1 downto 0 B in unsigned B port size 1 downto 0 MULT out unsigned A port size B port size 1 downto 0 attribute mult style string attribute mult style of multipliers 3 entity is pipe lut end multipliers 3 architecture beh of multipliers 3 is signal a in b in unsigned A port size 1 downto 0 signal mult res unsigned A port size B port size 1 downto 0 signal pipe 2 pipe 3 unsigned
212. T MUXF5 MUXF6 MUXF7 and MUXES primitives which allows compact implementation of large inferred ROMs e Block ROM Block ROMs are generated by using block RAM resources When a synchronous ROM is identified it can be inferred either as a distributed ROM plus a register or it can be inferred using block RAM resources ROM Style ROM STYLE specifies which type of synchronous ROM XST infers e If set to block and the ROM fits entirely on a single block of RAM XST infers the ROM using block RAM resources e Ifset to distributed XST infers a distributed ROM plus register e If setto auto XST determines the most efficient method to use and infers the ROM accordingly Auto is the default You can apply RAM Style RAM STYLE as a VHDL attribute or a Verilog meta comment to an individual signal or to the entity or module of the ROM RAM Style RAM STYLE can also be applied globally from ISE Design Suite in Process Properties or from the command line DSP48 Block Resources XST can automatically implement the following macros on a DSP48 block e Adders subtractors e Accumulators e Multipliers e Multiply adder subtractors e Multiply accumulate MAC XST also supports the registered versions of these macros Macro implementation on DSP48 blocks is controlled by the Use DSP48 USE DSP48 constraint or command line option with a default value of auto In auto mode XST attempts to implement accumulators multipliers
213. T instance name box type primitive black box user black box END bus delimiter Bus Delimiter bus delimiter Bus Delimiter vectors in the result netlist You can also set this value in ISE Design Suite by setting Process gt Properties gt Synthesis Options gt Bus Delimiter bus delimiter Bus Delimiter Architecture Support Architecture independent bus delimiter Bus Delimiter Applicable Elements Applies to syntax XST User Guide 266 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST Design Constraints XILINX bus_delimiter Bus Delimiter Propagation Rules Not applicable bus delimiter Bus Delimiter Syntax bus delimiter lt gt The default delimiter is lt gt bus_delimiter Bus Delimiter Syntax Example xst run bus delimiter This example defines bus delimiters globally as square braces case Case case Case determines if instance and net names are written in the final netlist using all lower or upper case letters or if the case is maintained from the source The case can be maintained for either Verilog or VHDL synthesis flow You can also set this value in ISE Design Suite with Process gt Properties gt Synthesis Options gt Case case Case Architecture Support Architecture independent case Case Applicable Elements Applies to syntax case Case Propagation Rules Not applicable case Case Syntax case u
214. T Command Line Syntax Example Define in the XST command line as follows xst run power yes no The default is no POWER Power Reduction ISE Design Suite Syntax Example Define in ISE Design Suite with Process gt Properties gt Synthesis Options gt Power Reduction READ_CORES Read Cores Use READ_CORES Read Cores to enable or disable the ability of XST to read Electronic Data Interchange Format EDIF or NGC core files for timing estimation and device utilization control By reading a specific core XST is better able to optimize logic around the core since it sees how the logic is connected However in some cases the READ_CORES operation must be disabled in XST in order to obtain the desired results For example the PCI core must not be visible to XST since the logic directly connected to the PCI core must be optimized differently as compared to other cores READ_CORES allows you to enable or disable read operations on a core by core basis For more information see Cores Processing READ_CORES has three possible values e no false Disables cores processing e yes true Enables cores processing but maintains the core as a black box and does not further incorporate the core into the design e optimize Enables cores processing and merges the cores netlist into the overall design This value is available through the XST command line mode only READ_CORES Read Cores Architecture Support Applies to all FPG
215. T gt Summary inferred 1 Counter s Chapter 11 XST Log File 458 www xilinx com XST User Guide UG627 v 11 3 September 16 2009 Chapter ti XST Log File XILINX Unit lt smallcntr gt synthesized Synthesizing Unit lt dcm1 gt Related source file is C xst watchver dcem1 vhd Unit lt dcm1 gt synthesized Synthesizing Unit lt cnt60 gt Related source file is cnt60 v Unit lt cnt60 gt synthesized Synthesizing Unit lt stopwatch gt Related source file is stopwatch v Unit lt stopwatch gt synthesized HDL Synthesis Report Macro Statistics ROMs 3 16x10 bit ROM 1 16x7 bit ROM 2 Counters 2 4 bit up counter 2 Registers 2 1 bit register 2 Advanced HDL Synthesis Analyzing FSM lt FSM_0 gt for best encoding Optimizing FSM lt MACHINE current_state FSM gt on signal lt current_state 1 3 gt with sequential encoding 000001 000 000010 001 000100 010 001000 011 010000 100 100000 101 Loading device for application Rf Device from file 4vlx15 nph in environment C xilinx Executing edif2ngd noa tenths edn tenths ngo XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 459 XILINX Chapter 11 XST Log File Release 10 1 edif2ngd K 31 nt64 Copyright c 1995 2008 Xilinx Inc All rights reserved INFO NgdBuild Release 10 1 edif2ngd K 31 nt64 INFO NgdBuild Copyright c 1
216. T to use the constraints file during synthesis XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 281 XILINX nuit t XST Design Constraints vigincdir Verilog Include Directories vlgincdir Verilog Include Directories is used to help the parser find files referenced by include statements When an include statement references a file XST looks in different areas in this order e Relative to the current directory Relative to the inc directories Relative to the current file Note vlgincdir should be used with include vlgincdir Verilog Include Directories Architecture Support Architecture independent vlgincdir Verilog Include Directories Applicable Elements Applies to directories vlgincdir Verilog Include Directories Propagation Rules Not applicable To specify the Verilog include directories in ISE Design Suite 1 Select Process Properties Synthesis Options 2 From the Property display level list select Advanced 3 Setthe Verilog Include Directories property vigincdir Verilog Include Directories Syntax vlgincdir directory path directory_path directory_path is the name of a directory For more information see Names With Spaces in Command Line Mode vigincdir Verilog Include Directories Syntax Example xst elaborate vlgincdir c my_verilog Adds c my verilog to the list of directories in which XST looks for a file verilog2001 Verilog 2001 v
217. TER REMOVAL Equivalent Register Removal Architecture Support Architecture independent EQUIVALENT REGISTER REMOVAL Equivalent Register Removal Applicable Elements Applies to the entire design or to an entity component module or signal EQUIVALENT REGISTER REMOVAL Equivalent Register Removal Propagation Rules Removes equivalent flip flops and flip flops with constant inputs EQUIVALENT REGISTER REMOVAL Equivalent Register Removal Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it EQUIVALENT REGISTER REMOVAL Equivalent Register Removal VHDL Syntax Example Declare as follows attribute equivalent register removal string Specify as follows attribute equivalent register removal of entity name signal name signal entity is yes no EQUIVALENT REGISTER REMOVAL Equivalent Register Removal Verilog Syntax Example Place immediately before the module or signal declaration equivalent register removal yes no zi EQUIVALENT REGISTER REMOVAL Equivalent Register Removal XST Constraint File XCF Syntax Example One MODEL entity name equivalent register removal yes no true false EQUIVALENT REGISTER REMOVAL Equivalent Register Removal XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name NET signal name equivalent register removal
218. TIO MAXMARGIN Propagation Rules Applies to the entity or module to which it is attached Slice LUT FF Pairs Utilization Ratio Delta SLICE UTILIZATION RATIO MAXMARGIN Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it Slice LUT FF Pairs Utilization Ratio Delta VHDL Syntax Examples Declare as follows attribute slice utilization ratio maxmargin string Specify as follows attribute slice utilization ratio maxmargin of entity name entity is integer attribute slice utilization ratio maxmargin of entity name entity is integer attribute slice utilization ratio maxmargin of entity name entity is integer XST interprets the integer values in the first two examples above as a percentage and in the last example as an absolute number of slices or FF LUT pairs The integer value range is 0 to 100 when percent is used or both percent and pound are omitted Slice LUT FF Pairs Utilization Ratio Delta Verilog Syntax Examples Place immediately before the module declaration or instantiation slice utilization ratio maxmargin integer zi slice utilization ratio maxmargin integer slice utilization ratio maxmargin integeri XST interprets the integer values in the first two examples above as a percentage and in the last example as an absolute number of slices o
219. T_STAGE Move Last Stage Architecture Support Applies to all FPGA devices Does not apply to CPLD devices MOVE_LAST_STAGE Move Last Stage Applicable Elements Applies to the following Entire design e Single modules or entities e Primary clock signal MOVE_LAST_STAGE Move Last Stage Propagation Rules MOVE_LAST_STAGE Move Last Stage propagation rules see Move First Stage MOVE_FIRST_STAGE MOVE_LAST_STAGE Move Last Stage Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it MOVE_LAST_STAGE Move Last Stage Syntax Example Declare as follows attribute move_last_stage string Specify as follows attribute move last stage of entity name signal name signal entity is yes no Move Last Stage Verilog Syntax Example Place immediately before the module or signal declaration move last stage yes no zi Move Last Stage XST Constraint File XCF Syntax Example One MODEL entity name move last stage yes no true false Move Last Stage XST Constraint File XCF Syntax Example Two BEGIN MODEL entity_name NET primary clock signal move last stage yes no true false END Move Last Stage XST Command Line Syntax Example Define in the XST command line as follows xst run move last stage yes no The default is yes Move Last Stage ISE Design Suite Synta
220. Technology XST support for Hardware Description Language HDL Xilinx devices and design constraints for the Xilinx ISE Design Suite software e Discusses FPGA and CPLD optimization and coding techniques when creating designs for use with XST e Explains how to run XST from the ISE Design Suite Process window and from the command line XST User Guide Contents The XST User Guide includes e Chapter 1 About This Guide provides an overview of the XST User Guide Chapter 2 Introduction to Xilinx Synthesis Technology XST provides general information about Xilinx Synthesis Technology XST and describes the changes to XST in this release e Chapter 3 XST Hardware Description Language HDL Coding Techniques gives Hardware Description Language HDL coding examples for digital logic circuits e Chapter 4 XST FPGA Optimization explains how constraints can be used to optimize FPGA devices explains macro generation and describes the FPGA device primitive support e Chapter 5 XST CPLD Optimization discusses CPLD synthesis options and the implementation details for macro generation e Chapter 6 XST Design Constraints provides general information about XST design constraints as well as information about specific constraints e Chapter 7 XST VHDL Language Support explains how XST supports the VHSIC Hardware Description Language VHDL and provides details on VHDL supported constructs and synthesis options e Chapter 8 XST
221. Type Black Box Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip Black Box VHDL Coding Example Black Box library ieee use ieee std logic 1164 al1 entity black box 1 is port DI 1 DI 2 in std logic DOUT out std logic end black box 1 architecture archi of black box 1 is component my block port I1 in std logic I2 in std logic O out std logic end component begin inst my block port map 1I1 gt DI_1 12 gt DI_2 0 gt DOUT end archi XST User Guide 200 www xilinx com UG627 v 11 3 September 16 2009 Chipter1 XST Hardware Description Language HDL Coding Techniques Black Box Verilog Coding Example Black Box module v_my_block inl in2 dout input inl in2 output dout endmodule module v black box 1 DI 1 DI 2 DOUT input DI 1 DI 2 output DOUT v my block inst inl DI 1 in2 DI 2 dout DOUT endmodule XILINX For more information on component instantiation see your VHDL and Verilog language reference manuals XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 201 XST User Guide 202 www xilinx com UG627 v 11 3 September 16 2009 XILINX Chapter 4 XST FPGA Optimization This chapter e Explains how constraints can be used to optimize FPGA devices e Explains macro generation
222. ULT SEARCH ORDER keyword XST e Searches the specified library files in the order in which they appear in the project file e Updates the LSO file by Removing the DEFAULT SEARCH ORDER keyword Adding the list of libraries to the LSO file in the order in which they appear in the project file For a project file my proj prj with the following contents vhdl vhlibl fl vhd verilog rtfllib fl v vhdl vhlib2 3 vhd LSO file Created by ProjNav and an LSO file my proj 1so created by ISE Design Suite with the following contents DEFAULT SEARCH ORDER XST uses the following search order vhlibl rtfllib vhlib2 After processing the contents of my proj 1so is vhlibl TtEllrb vhlib2 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 443 XILINX Chapter 11 XST Mixed Language Support DEFAULT_SEARCH_ORDER Keyword and List of Libraries When the Library Search Order LSO file contains the DEFAULT_SEARCH_ORDER keyword and a list of the libraries XST e Searches the specified library files in the order in which they appear in the project file e Ignores the list of library files in the LSO file e Leaves the LSO file unchanged For a project file my proj prj with the following contents vhdl vhlibl fl vhd verilog rtfllib fl v vhdl vhlib2 3 whd and an LSO file my proj 1so created with the following contents rtfllib vhlib2 vhlibl DEFAULT SEARCH ORDER XST uses the following search
223. Verilog Language Support describes XST support for Verilog constructs and meta comments e Chapter 9 XST Behavioral Verilog Language Support describes XST support for Behavioral Verilog e Chapter 10 XST Mixed Language Support describes how to run an XST project that mixes Verilog and VHDL designs e Chapter 11 XST Log File describes the XST log file e Chapter 12 XST Naming Conventions describes XST naming conventions e Chapter 13 XST Command Line Mode describes how to run XST using the command line Additional Resources To find additional documentation see the Xilinx website at http www xilinx com literature To search the Answer Database of silicon software and IP questions and answers or to create a technical support WebCase see the Xilinx website at XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 17 XILINX Chapter 1 About the XST User Guide http www xilinx com support Conventions This document uses the following conventions An example illustrates each convention Typographical The following typographical conventions are used in this document Convention Meaning or Use Messages prompts and program files that the system displays Courier bold Helvetica bold pem Square brackets Literal commands that you enter in a syntactical statement Commands that you select from a menu Keyboard shortcuts Variables in a syntax statement for which you m
224. Verilog Target XCF Target Line Value Use Clock entity Enable signal FF instance name Use DSP48 Use entity Synchronous Reset signal Use entity Synchronous Set signal FF instance name XOR Collapsing XST Command Line Only Options module signal FF instance name module signal module signal FF instance name module signal FF instance name module signal model net in model inst in model model net in model model net in model inst in model model net in model inst in model model net in model use clock enable XOr collapse XST Specific Non Timing Options XST Command Line Only ee Asynchronous to Synchronous Automatic BRAM Packing async to sync no auto bram packing architecture name default N A yes default no yes no default no auto yes no default auto auto yes no default auto yes no default auto auto yes no default auto yes no default XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 259 XILINX nuit t XST Design Constraints BRAM Utilization Ratio bram_utilization_ integer range 1 to 100 BRAM_UTILIZATION_RATIO ratio integer range 1 to 100 integer default 100 Maximum Global Clock Buffers Integer default max number of buffers in target device Maximum Regional Clock Buffers Integer default ma
225. XST User Guide UG627 v 11 3 September 16 2009 XILINX Xilinx Trademarks and Copyright Information XILINX Xilinx is disclosing this user guide manual release note and or specification the Documentation to you solely for use in the development of designs to operate with Xilinx hardware devices You may not reproduce distribute republish download display post or transmit the Documentation in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Xilinx expressly disclaims any liability arising out of your use of the Documentation Xilinx reserves the right at its sole discretion to change the Documentation without notice at any time Xilinx assumes no obligation to correct any errors contained in the Documentation or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DOCUMENTATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL
226. YLE values are e auto default muxf e muxcy DOCTYPE command auto XST looks for the best implementation for each considered macro Available MUX STYLE Mux Style Implementation Styles Devices Devices Resources Spartan 3 Spartan 3E Spartan 3A Spartan 3A DSP Virtex 4 Virtex 5 MUX_STYLE Mux Style Architecture Support Applies to all FPGA devices Does not apply to CPLD devices MUX_STYLE Mux Style Applicable Elements Applies to the entire design or to an entity component module or signal MUX_STYLE Mux Style Propagation Rules Applies to the entity component module or signal to which it is attached MUX_STYLE Mux Style Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it MUX_STYLE Mux Style VHDL Syntax Example Declare as follows attribute mux_style string XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 317 XILINX nuit t XST Design Constraints Specify as follows attribute mux_style of signal_name entity_name signal entity is auto muxf muxcy The default is auto MUX_STYLE Mux Style Verilog Syntax Example Place immediately before the module or signal declaration mux_style auto muxf muxcy The default is auto MUX_STYLE Mux Style XST Constraint File XCF Syntax Example One
227. _IN input RST input SELECT input CLOCK input 0 3 DATA_IN output 0 3 STATE reg 0 3 STATE always RST if RST begin assign STATE 4 b0 end else begin deassign STATE end always posedge CLOCK begin STATE lt DATA_IN end endmodule The main limitations on support of the assign deassign statement in XST are Fora given signal there is only one assign deassign statement e The assign deassign statement is performed in the same always block through an if else statement You cannot assign a bit part select of a signal through an assign deassign statement Behavioral Verilog Assign Deassign Statement Coding Example For a given signal there is only one assign deassign statement For example XST rejects the following design module dflop RST SET STATE CLOCK DATA IN input RST input SET input CLOCK input DATA IN output STATE reg STATE always RST block bl if RST assign STATE 1 b0 else deassign STATE always SET block bl if SET assign STATE 1 bl else deassign STATE always posedge CLOCK block b2 begin STATE lt DATA_IN end endmodule XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 429 XILINX Chapter 1 XST Behavioral Verilog Language Support Behavioral Verilog Assign Deassign Statement Performed in Same Always Block The assign deassign statement is performed in the same always block thr
228. _separator I O Standard IOSTANDARD Keep KEEP Keep Hierarchy KEEP HIERARCHY Library Search Order 1so LOC Netlist Hierarchy netlist hierarchy Optimization Effort OPT LEVEL Optimization Goal OPT MODE Parallel Case PARALLEL CASE RLOC Save S SAVE Synthesis Constraint File uc Translate Off TRANSLATE OFF and Translate On TRANSLATE ON Use Synthesis Constraints File iuc Verilog Include Directories vlgincdir Verilog 2001 verilog2001 HDL Library Mapping File xsthdpini Work Directory xsthdpdir XST User Guide UG627 v 11 3 September 16 2009 www xilinx com XILINX 243 XILINX nuit t XST Design Constraints XST Hardware Description Language HDL Constraints The following constraints are found in XST HDL Constraints e Automatic FSM Extraction FSM_EXTRACT e Enumerated Encoding ENUM_ENCODING e Equivalent Register Removal EQUIVALENT_REGISTER_REMOVAL e FSM Encoding Algorithm FSM_ENCODING e Mux Extraction MUX_EXTRACT e Register Power Up REGISTER POWERUD e Resource Sharing RESOURCE SHARING e Safe Recovery State SAFE RECOVERY STATE e Safe Implementation SAFE IMPLEMENTATION e Signal Encoding SIGNAL ENCODING XST FPGA Constraints Non Timing The following are XST FPGA Constraints Non Timing e Asynchronous to Synchronous ASYNC TO SYNC e Automatic BRAM Packing AUTO_BRAM_PACKING e BRAM Utilization Ratio BRAM_UTILIZATION_RATIO e Buffer Type BUFF
229. a Single LUT Applicable Elements Applies to a VHDL entity or Verilog module LUT MAP Map Entity on a Single LUT Propagation Rules Applies to the entity or module to which it is attached LUT MAP Map Entity on a Single LUT Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it XST User Guide 338 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST Design Constraints XILINX LUT_MAP Map Entity on a Single LUT VHDL Syntax Example Declare as follows attribute lut_map string Specify as follows attribute lut_map of entity_name entity is yes no LUT_MAP Map Entity on a Single LUT Verilog Syntax Example Place immediately before the module declaration or instantiation lut_map yes no LUT_MAP Map Entity on a Single LUT XST Constraint File XCF Syntax Example MODEL entity name lut_map yes no true false USE CARRY CHAIN Use Carry Chain XST uses carry chain resources to implement certain macros but there are situations where you can obtain better results by not using carry chain USE CARRY CHAIN Use Carry Chain can deactivate carry chain use for macro generation USE CARRY CHAIN is both a global and a local constraint USE CARRY CHAIN values are e yes default no USE CARRY CHAIN Use Carry Chain Architecture Support Applies to all
230. able Declarations Variables in Verilog may be declared as integers or real These declarations are intended for use in test code only Verilog provides data types such as reg and wire for actual hardware description The difference between reg and wire is whether the variable is given its value in a procedural block reg or ina continuous assignment wire Verilog code Both reg and wire have a default width being one bit wide scalar To specify an N bit width vectors for a declared reg or wire the left and right bit positions are defined in square brackets separated by a colon In Verilog 2001 both reg and wire data types can be signed or unsigned Behavioral Verilog Variable Declarations Coding Example reg 3 0 arb_priority wire 31 0 arb_request wire signed 8 0 arb_signed XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 417 XILINX Chapter 1 XST Behavioral Verilog Language Support where e arb_request 31 is the MSB e arb request 0 is the LSB Behavioral Verilog Initial Values In Verilog 2001 you can initialize registers when you declare them The value e Isa constant e Cannot depend on earlier initial values e Cannot be a function or task call e Can be a parameter value propagated to the register e Specifies all bits of a vector Behavioral Verilog Initial Values Coding Example When you give a register an initial value in a declaration XST sets this value on the output of the r
231. able FSM extraction use Automatic FSM Extraction FSM_EXTRACT Describing a Finite State Machine FSM Component There are many ways to describe a Finite State Machine FSM component A traditional FSM representation incorporates Mealy and Moore machines as shown in the following diagram XST supports both models Finite State Machine FSM Representation Incorporating Mealy and Moore Machines Diagram Output State Outputs Register Function Inputs Function 9 Only for Mealy Machine xaosa For HDL process VHDL and always blocks Verilog are the best ways to describe FSM components Xilinx uses process to refer to both VHDL processes and Verilog always blocks You may have several processes 1 2 or 3 in your description depending upon how you consider and decompose the different parts of the preceding model Following is an example of the Moore Machine with Asynchronous Reset RESET e 4 states s1 s2 s3 ad e 5 transitions e input x1 e 1 output outp This model is represented by the following bubble diagram Bubble Diagram RESET XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 189 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques State Registers State registers must be initialized with an asynchronous or synchronous signal or have the power up value defined by Register Power Up REGISTER_POWERUP Otherwise XST does not reco
232. ad Cores Disabling Read Cores prevents XST from automatically reading PCI cores for timing and area estimation In reading PCI cores XST may perform logic optimization that does not allow the design to meet timing requirements or which might lead to errors during MAP To disable Read Cores uncheck it in ISE Design Suite inProcess gt Properties gt Synthesis Options gt Read Cores By default XST reads cores for timing and area estimation XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 231 XST User Guide 232 www xilinx com UG627 v 11 3 September 16 2009 XILINX Chapter 5 XST CPLD Optimization This chapter discusses CPLD synthesis options and the implementation details for macro generation This chapter includes e CPLD Synthesis Options e Implementation Details for Macro Generation e CPLD Synthesis Log File Analysis e CPLD Synthesis Constraints e Improving Results in CPLD Synthesis CPLD Synthesis Options XST generates an NGC file ready for the CPLD fitter The general flow of XST for CPLD synthesis is 1 Hardware Description Language HDL synthesis of VHDL or Verilog designs 2 Macro inference 3 Module optimization 4 NGC file generation This section describes supported CPLD families It lists the XST options related only to CPLD synthesis that can be set ISE Design Suite in Process gt Properties CPLD Synthesis Supported Devices XST supports CPLD synthesis for
233. adder use the arithmetic packages and types that operate on unsigned values shown in the following table Unsigned Adder PACKAGE TYPE To create a signed adder use the arithmetic packages and types that operate on signed values shown in the following table Signed Adder PACKAGE TYPE For more information about available types see the IEEE VHDL Manual Registers Hardware Description Language HDL Coding Techniques XST recognizes flip flops with the following control signals e Asynchronous Set Reset e Synchronous Set Reset e Clock Enable For more information see Specifying INIT and RLOC XST User Guide 22 www xilinx com UG627 v 11 3 September 16 2009 nuit XST Hardware Description Language HDL Coding Techniques XILINX Registers Log File The XST log file reports the type and size of recognized flip flops during the Macro Recognition step Synthesizing Unit lt registers_5 gt Related source file is registers_5 vhd Found 4 bit register for signal lt Q gt Summary inferred 4 D type flip flop s Unit lt registers_5 gt synthesized HDL Synthesis Report Macro Statistics Registers ks 4 bit register si Advanced HDL Synthesis Report Macro Statistics Registers 4 Flip Flops Latches 4 With the introduction of new device families such as the Virtex 4 device family XST may optimize different slices of the same register in different ways For example XST may push a part of a
234. addra reg 5 0 read addrb always posedge clk begin if ena begin if wea ram addra dia read addra addra end if enb read addrb addrb end assign doa assign dob ram read addra ram read addrb pog endmodule Dual Port Block RAM With Different Clocks Diagram DIA BLOCK RAM WEA ADDRA DOA ADDRB DOB CLKA CLKB Dual Port Block RAM With Different Clock Pin Descriptions opm Bein XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 151 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques XST supports dual port block RAMs with two write ports for VHDL and Verilog The concept of dual write ports implies not only distinct data ports but the possibility of distinct write clocks and write enables as well Distinct write clocks also mean distinct read clocks since the dual port block RAM offers two clocks one shared by the primary read and write port the other shared by the secondary read and write port In VHDL the description of this type of block RAM is based on the usage of shared variables The XST VHDL analyzer accepts shared variables but errors out in the HDL Synthesis step if a shared variable does not describe a valid RAM macro Dual Port Block RAM With Two Write Ports Diagram WEA WEB ENA DOA ENB DOB DIA Block DIB RAM ADDRA ADDRB CLKA gt CLKB gt Dual Port Block RAM With Two Write Ports Pin Descriptions oms lee
235. age HDL Coding Techniques Single Port RAM In No Change Mode VHDL Coding Example Two No Change Mode template 1 library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity rams 03 is port clk in std logic we in std logic en in std logic addr in std logic vector 5 downto 0 di in std logic vector 15 downto 0 do out std logic vector 15 downto 0 end rams 03 architecture syn of rams 03 is type ram type is array 63 downto 0 of std logic vector 15 downto 0 signal RAM ram type begin process clk begin if clk event and clk 1 then if en 1 then if we 1 then RAM conv integer addr lt di else do lt RAM conv integer addr end if end if end if end process end syn Single Port RAM In No Change Mode Verilog Coding Example Two No Change Mode template 1 module v_rams_03 clk we en addr di do input elk input we input en input 5 0 addr input 15 0 di output 15 0 do reg 15 0 RAM 63 0 reg 15 0 do always posedge clk begin if en begin if we RAM addr lt di else do lt RAM addr end end endmodule The following descriptions are directly mappable onto distributed RAM only XST User Guide 136 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX Single Port RAM With Asynchronous R
236. alf adder composed of four 2 input nand modules module halfadd X Y C S input X Y output DC S wire S1 S2 S3 nand NANDA S3 X Y nand NANDB S1 X S3 nand NANDC S2 S3 Y nand NANDD S S1 S2 assign C S3 endmodule XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 405 XILINX Chapter d XST Verilog Language Support Synthesized Top Level Netlist xO YO Lc The structural features of Verilog also allow you to design circuits by instantiating pre defined primitives such as gates registers and Xilinx specific primitives such as CLKDLL and BUFGs These primitives are other than those included in Verilog These pre defined primitives are supplied with the XST Verilog libraries unisim comp v Structural Instantiation of REGISTER and BUFG Structural Verilog Coding Example module foo sysclk in reset out input sysclk in reset output out reg out wire sysclk out FDC register out sysclk out reset in position based referencing BUFG clk O sysclk out I sysclk name based referencing endmodule The unisim comp v library file supplied with XST includes the definitions for FDC and BUFG BOX TYPE PRIMITIVE Verilog 2001 module FDC Q C CLR D parameter INIT 1 b0 output O input C input CLR input D endmodule BOX TYPE PRIMITIVE Verilog 2001 module BUFG O I output O input I
237. am addr lt din dout lt ram addr end endmodule ROMs Using Block RAM Resources Hardware Description Language HDL Coding Techniques XST can use block RAM resources to implement ROMs with synchronous outputs or address inputs These ROMs are implemented as single port or dual port block RAMs depending on the HDL description XST can infer block ROM across hierarchies if Keep Hierarchy KEEP_HIERARCHY is set to no In this case ROM and the data output or address register can be described in separate hierarchy blocks This inference is performed during Advanced HDL Synthesis Using block RAM resources to implement ROMs is controlled by the ROM Style ROM_STYLE constraint For more information about ROM Style ROM_STYLE see XST Design Constraints For more information about ROM implementation see XST FPGA Optimization XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 177 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques ROMs Using Block RAM Resources Log File Synthesizing Unit rams 21a Related source file is rams 21a vhd Found 64x20 bit ROM for signal varindex0000 created at line 38 Found 20 bit register for signal data Summary inferred 1 ROM s inferred 20 D type flip flop s Unit lt rams_2la gt synthesized HDL Synthesis Report Macro Statistics ROMs 64x20 bit ROM Registers 20 bit register PRPRPR INFO Xst Unit rams 21a
238. ame fsm style luxt bram END FSM STYLE FSM Style XST Constraint File XCF Syntax Example Three BEGIN MODEL entity name INST instance name fsm style lut bram END FSM STYLE FSM Style ISE Design Suite Syntax Example Define in ISE Design Suite with Process Properties Synthesis Options FSM Style XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 305 XILINX nuit t XST Design Constraints POWER Power Reduction POWER Power Reduction instructs XST to optimize the design to consume as little power as possible Macro processing decisions are made to implement functions in a manner than uses minimal power Although POWER is allowed in both AREA and SPEED modes it may negatively impact the final overall area and speed of the design In the current release power optimization done by XST is dedicated to DSP48 and BRAM blocks XST supports two BRAM optimization methods e Method One does not significantly impact area and speed Method One is used by default when power optimization is enabled e Method Two saves more power but may significantly impact area and speed Both methods can be controlled by using the RAM Style RAM STYLE constraint with block powerl for Method One and block power2 for Method Two In some situations XST may issue an HDL Advisor message giving you tips on how to improve your design For example if XST detects that Read First mode is used for BRAM XST recomme
239. ameters Target Parameters e Source Options Target Options e General Options e Other Options XST FPGA Log File Hardware Description Language HDL Compilation For information on Hardware Description Language HDL Compilation see XST FPGA Log File Hardware Description Language HDL Analysis XST FPGA Log File Design Hierarchy Analyzer For information on Design Hierarchy Analyzer see XST FPGA Log File HDL Analysis XST FPGA Log File Hardware Description Language HDL Analysis During Hardware Description Language HDL Compilation Design Hierarchy Analyzer and HDL Analysis XST e Parses and analyzes VHDL and Verilog files e Recognizes the design hierarchy e Gives the names of the libraries into which they are compiled During this step XST may report potential mismatches between synthesis and simulation results potential multi sources and other issues XST FPGA Log File Hardware Description Language HDL Synthesis Report During Hardware Description Language HDL Synthesis XST tries to recognize as many basic macros as possible to create a technology specific implementation This is done on a block by block basis At the end of this step XST issues the HDL Synthesis Report For more information about the processing of each macro and the corresponding messages issued during synthesis see XST Hardware Description Language HDL Coding Techniques XST FPGA Log File Advanced HDL Synthesis Report XST performs adv
240. ample subtype WORD8 is STD LOGIC VECTOR 7 downto 0 type TAB12 is array 11 downto 0 of WORDS type TABO3 is array 2 downto 0 of TAB12 You can also declare an array as a matrix as shown in the following coding example subtype TAB13 is array 7 downto 0 4 downto 0 of STD LOGIC VECTOR 8 downto 0 The following coding examples demonstrate the uses of multi dimensional array signals and variables in assignments Multi Dimensional Array VHDL Coding Example One Consider the declarations subtype WORD8 is STD LOGIC VECTOR 7 downto 0 type TABO5 is array 4 downto 0 of WORD8 type TABO3 is array 2 downto 0 of TABO5 signal WORD_A WORD8 signal TAB_A TAB_B TABO5 signal TAB C TAB D TABO3 constant CNST A TABO3 00000000 01000001 01000010 10000011 00001100 00100000 00100001 00101010 10100011 00101100 01000010 01000010 01000100 01000111 01000100 The following can now be specified e A multi dimensional array signal or variable TAB A lt TAB B TAB C lt TAB D TAB C lt CNST A e Anindex of one array TAB A 5 lt WORD A TAB C 1 lt TAB A e Indexes of the maximum number of dimensions TAB A 5 0 lt 1 TAB C 2 5 0 lt KE 0 e A slice of the first array TAB A 4 downto 1 lt TAB B 3 downto 0 e Anindex of a higher level array and a slice of a lower level array TAB C 2 5 3 downto 0 lt TAB B 3 4 downto 1 T
241. ample if you use the following timing constraints TIMESPEC TSidentifier FROM source group TO dest group value units then the number of ports corresponds to the number of elements in the destination group For a given timing constraint XST may report that the number of failed paths is 100 but that the number of failed destination ports is only two flip flops In that case it is sufficient to analyze the design description for these two flip flops only in order to detect the changes necessary to meet timing Implementation Constraints XST writes all implementation constraints generated from Hardware Description Language HDL or constraint file attributes LOC into the output NGC file Keep KEEP properties are generated during buffer insertion for maximum fanout control or for optimization FPGA Device Primitive Support XST enables you to instantiate device primitives directly in your VHDL or Verilog code Primitives such as the following can be manually inserted in your HDL design through instantiation e MUXCYL e LUT4_L CLKDLL e RAMBA SI S16 e BUFG PCI33 5 e NAND3b2 These primitives e Are compiled in the UNISIM library e Are not optimized by XST by default e Are available in the final NGC file Use the Optimize Instantiated Primitives synthesis option to optimize instantiated primitives and obtain better results Timing information is available for most of the primitives allowing XST to per
242. ample One The following Verilog coding example describes an array of 256 x 16 wire elements each 8 bits wide which can be assigned only in structural Verilog code wire 7 0 array2 0 255 0 15 Behavioral Verilog Multi Dimensional Arrays Coding Example Two The following Verilog coding example describes an array of 256 x 8 register elements each 64 bits wide which can be assigned in behavioral Verilog code reg 63 0 regarray2 255 0 7 0 Behavioral Verilog Data Types The Verilog representation of the bit data type contains the following values e 0 logic zero e 1 logic one kb x unknown logic value Zz high impedance XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 419 XILINX Chapter 1 XST Behavioral Verilog Language Support XST supports the following Verilog data types e Net wire tri triand wand trior wor e Registers reg integer e Supply nets supplyO Ssupplyl e Constants parameter e Multi Dimensional Arrays Memories Net and registers can be either Single bit scalar Multiple bit vectors Behavioral Verilog Data Types Coding Example The following Behavioral Verilog coding example shows sample Verilog data types found in the declaration section of a Verilog module wire netl single bit net reg rl single bit register tri 7 0 busl 8 bit tristate bus reg 15 0 bus1 15 bit register reg 7 0 mem 0 127 8x12
243. an e Eo EE E ASO EEE E EAP EAEN ET O ENE EKDE EEEE E 279 5S SAVE 280 uc Syrithesis Constraint Pile csrssicccusscsvetvasevscetsaceicecsotecesecpvacgaessbossgdessvovss lt evsbuse IERI E ee ee 280 TRANSLATE OFF Iranslate Off sinsero iniiis enni a eia eana Tais 280 TRANSLATE OFF Translate Off Architecture Support 281 TRANSLATE OFF Translate Off Applicable Hlements eee ee ee eerererererereneeees 281 TRANSLATE OFF Translate Off Propagation Rules ssssssse eerererererennees 281 iuc Use Synthesis Constraints File iei eeeeeecsesee eee ena ce a n ta aee drini PEES ENN Ee ee SENEE ESFERAS 281 vlgincdir Verilog Include Directories eee 282 sveriloe2001 Verilog 200 1 EE 282 xsthdpini HDL Library Mapping Eile ee ettet terrea tp nono Er dene eo oin Eee nn eR nna 283 cieolosidia od dBiivwutus M 284 xsthdpdir Work Directory Example eeeeeseeeeeeeeee nennen AEn E ra ne tenen nene 284 xsthdpdir Work Directory Architecture Dupport eee nererererererrees 284 xsthdpdir Work Directory Applicable Hlemente 284 xsthdpdir Work Directory Propagation Rules eee rete ee eeeeeerererererereee es 285 xsthdpdir Work Directory Syntax Examples cree eee teeeeeeeseseeeeereeerege es 285 XST Hardware Description Language HDL Constraints sss 285 FSM_EXTRACT Automatic FSM Extraction
244. an take two values yes macro generation is allowed no macro generation is inhibited The general macro generation flow is 1 Hardware Description Language HDL infers macros and submits them to the low level synthesizer 2 Low level synthesizer accepts or rejects the macros depending on the resources required for the macro implementations An accepted macro is generated by an internal macro generator A rejected macro is replaced by equivalent logic generated by the HDL synthesizer A rejected macro may be decomposed by the HDL synthesizer into component blocks so that one component may be a new macro requiring fewer resources than the initial one and another smaller macro may be accepted by XST For instance a flip flop macro with clock enable CE cannot be accepted when mapping onto the XC9500 In this case the HDL synthesizer submits two new macros e A flip flop macro without clock enable signal e A MUX macro implementing the clock enable function A generated macro is optimized separately and then merged with surrounded logic because optimization gives better results for larger components XST User Guide 234 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST CPLD Optimization XILINX CPLD Synthesis Log File Analysis XST messages related to CPLD synthesis are located after the following message Low Level Synthesis XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 235 XILINX
245. anced macro recognition and inference In this step XST e Recognizes for example dynamic shift registers e Implements pipelined multipliers e Codes state machines The Advanced HDL Synthesis Report contains a summary of recognized macros in the overall design sorted by macro type XST FPGA Log File Low Level Synthesis XST reports the potential removal of for example equivalent flip flops and register replication For more information see FPGA Optimization Report Section XST User Guide 448 www xilinx com UG627 v 11 3 September 16 2009 Chapter ti XST Log File XILINX XST FPGA Log File Partition Report If the design is partitioned the XST FPGA log file Partition Report contains information detailing the design partitions XST FPGA Log File Final Report The XST FPGA log file Final Report includes e Final Results including RTL Top Level Output File Name for example stopwatch ngr Top Level Output File Name for example stopwatch Output Format for example NGC Optimization Goal for example Speed Whether the Keep Hierarchy constraint is used for example No e Cell usage Cell usage reports on for example the number and type of BELS Clock Buffers and IO Buffers e Device Utilization Summary The Device Utilization Summary estimates the number of slices and gives for example the number of flip flops IOBs and BRAMS The Device Utilization Summary closely approximates the report produced
246. and Synchronous Set Verilog Coding Example Flip Flop with Positive Edge Clock and Synchronous Set module v registers 3 C D S Q input C D S output QO reg Q always posedge C begin if S Q lt 1 bl else Q lt D end endmodule Flip Flop With Positive Edge Clock and Clock Enable Diagram X8363 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 27 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Flip Flop With Positive Edge Clock and Clock Enable Pin Descriptions gp Beseription S Data Input Positive Edge Clock Clock Enable Active High Data Output Flip Flop With Positive Edge Clock and Clock Enable VHDL Coding Example Flip Flop with Positive Edge Clock and Clock Enable library ieee use ieee std logic 1164 a1l1 entity registers 4 is port C D CE in std logic Q out std logic end registers 4 architecture archi of registers 4 is begin process C begin if C event and C 1 then if CE 1 then Q lt D end if end if end process end archi Flip Flop With Positive Edge Clock and Clock Enable Verilog Coding Example Flip Flop with Positive Edge Clock and Clock Enable module v registers 4 C D CE Q input C D CE output OQ reg Q always posedge C begin if CE Q lt D end endmodule XST User Guide 28 www xilinx com UG627 v 11 3 September 16 2009 Ch
247. and in the last example as an absolute number of slices or FF LUT pairs The integer value range is 0 to 100 when percent is used or both percent and pound are omitted LUT MAP Map Entity on a Single LUT LUT MAP Map Entity on a Single LUT forces XST to map a single block into a single LUT If a described function on an RTL level description does not fit in a single LUT XST issues an error message Use the UNISIM library to directly instantiate LUT components in your Hardware Description Language HDL code To specify a function that a particular LUT must execute apply an INIT constraint to the instance of the LUT To place an instantiated LUT or register in a particular slice attach an RLOC constraint to the same instance Itis not always convenient to calculate INIT functions and different methods can be used to achieve this Instead you can describe the function that you want to map onto a single LUT in your VHDL or Verilog code in a separate block Attaching a LUT MAP constraint to this block indicates to XST that this block must be mapped on a single LUT XST automatically calculates the INIT value for the LUT and preserves this LUT during optimization For more information see Specifying INIT and RLOC XST automatically recognizes the XC MAP constraint supported by Synplicity LUT MAP Map Entity on a Single LUT Architecture Support Applies to all FPGA devices Does not apply to CPLD devices LUT MAP Map Entity on
248. apter XST Design Constraints XILINX FSM mo Algorithm Yes Mo value safe is not supported for automatic recognition Use Automatic Vendor XST e Geer a E For Safe Implementation syn_edif_scalar_format syn_edif_scalar_format scalar _format Synplicity Synplicity syn_encoding Synplicity VHDL r in XST to activate this mode syn hier in automatic syn hier Synplicity Keep Hierarchy Yes VHDL Verilog See Yes XST preserves the VHDL Verilog designated net in the final netlist but does not attach any KEEP constraint to it syn_hier hardrecognized askeep_hierarchy soft syn_hier removerecognized askeep_hierarchy no XST supports only the values hard and remove for synisdock isclock u syn netlist hierarchy Synplicity Netlist Hierarchy VHDL Verilog Synplicity hb syn_noclockbuf Synplicity Buffer Type Ys Ss VHDL VHDL Verilog Synplicity Optimize Instantiated VHDL Verilog Primitives syn_pipeline Synplicity Register Balancing eee Removal T Removal i syn_reference_clock Synplicity ram_extract and ram_style Yes VHDL Verilog VHDL Verilog VHDL Verilog XST implements RAMs in no_rw_check mode regardless if no_rw_check is specified or not the area value is ignored VHDL Verilog XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 361 XILINX hipter t XST Design Constraints Automatic Vendor
249. apter d XST Verilog Language Support Verilog Attributes and Meta Comments XST supports both Verilog 2001 style attributes and meta comments in Verilog Xilinx recommends Verilog 2001 attributes since they are more generally accepted Meta comments are comments that are understood by the Verilog parser Verilog 2001 Attributes XST supports Verilog 2001 attribute statements Attributes are comments that pass specific information to software tools such as synthesis tools Verilog 2001 attributes can be specified anywhere for operators or signals within module declarations and instantiations Other attribute declarations may be supported by the compiler but are ignored by XST Use attributes to e Set constraints on individual objects for example module instance net e Set the following synthesis constraints Full Case FULL CASE Parallel Case PARALLEL CASE Verilog Meta Comments Use Verilog meta comments to e Set constraints on individual objects such as module instance net e Set directives on synthesis parallel case and full case directives translate onand translate off directives all tool specific directives for example syn sharing For more information see XST Design Constraints Meta comments can be written using the C style or the Verilog style for comments C style comments can be multiple line Verilog style comments end at the end of the line XST supp
250. ar tools or methods If a tool or method is not listed you cannot use this constraint with it USE DSP48 Use DSP48 VHDL Syntax Example Declare as follows attribute use dsp48 string Specify as follows attribute use dsp48 of entity name component name signal name entity component signal is auto yes no USE DSP48 Use DSP48 Verilog Syntax Example Place immediately before the module or signal declaration use dsp48 auto yes no zi USE DSP48 Use DSP48 XST Constraint File XCF Syntax Example One MODEL entity name use dsp48 auto yes no true false USE DSP48 Use DSP48 XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name NET signal name use dsp48 auto yes no true false END USE DSP48 Use DSP48 XST Command Line Syntax Example Define in the XST command line as follows use dsp48 auto yes no The default is auto USE DSP48 Use DSP48 ISE Design Suite Syntax Example Define in ISE Design Suite with Process gt Properties gt HDL Options gt Use DSP48 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 347 XILINX nuit t XST Design Constraints XST CPLD Constraints Non Timing The following XST CPLD constraints non timing apply to CPLD devices only They do not apply to FPGA devices e Clock Enable Cold ce e Data Gate DATA GATE e Macro Preserve pld mp e No Reduce NOREDUCE e WYSIWYG wysiwyg e XO
251. ardware Description Language HDL Coding Techniques XILINX Macro Statistics Decoders s l 1 of 8 decoder M Decoders Related Constraints Decoder Extraction DECODER EXTRACT Decoders Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip 1 of 8 Decoder One Hot Diagram RES 7 RES 6 sta RES 5 RES 4 RES 3 RES 2 RES 1 RES 0 S 1 sto X10547 1 of 8 Decoders One Hot Pin Descriptions gp Desrpion S res Data Output 1 of 8 Decoder One Hot VHDL Coding Example l of 8 decoder One Hot library ieee use ieee std logic 1164 a11 entity decoders 1 is port sel in std logic vector 2 downto 0 res out std logic vector 7 downto 0 end decoders 1 architecture archi of decoders 1 is begin res lt 00000001 when sel 000 else 00000010 when sel 001 else 00000100 when sel 010 else 00001000 when sel 011 else 00010000 when sel 100 else 00100000 when sel 101 else 01000000 when sel 110 else 10000000 end archi XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 75 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques 1 of 8 decoder One Hot Verilog Coding Example 1 of 8 decoder One Hot module v_decoders_1 sel res input 2 0 sel output 7 0 res
252. are Description Language HDL Coding Techniques Latches Hardware Description Language HDL Coding Techniques Tristates Hardware Description Language HDL Coding Techniques Counters Hardware Description Language HDL Coding Techniques Accumulators Hardware Description Language HDL Coding Techniques Shift Registers Hardware Description Language HDL Coding Techniques Dynamic Shift Registers Hardware Description Language HDL Coding Techniques Multiplexers Hardware Description Language HDL Coding Techniques Decoders Hardware Description Language HDL Coding Techniques Priority Encoders Hardware Description Language HDL Coding Techniques Logical Shifters Hardware Description Language HDL Coding Techniques Arithmetic Operators Hardware Description Language HDL Coding Techniques Adders Subtractors and Adders Subtractors Hardware Description Language HDL Coding Techniques Comparators Hardware Description Language HDL Coding Techniques Multipliers Hardware Description Language HDL Coding Techniques Sequential Complex Multipliers Hardware Description Language HDL Coding Techniques Pipelined Multipliers Hardware Description Language HDL Coding Techniques Multiply Adder Subtractors Hardware Description Language HDL Coding Techniques Multiply Accumulate Hardware Description Language HDL Coding Techniques Dividers Hardware Description Language HDL Coding Techniques Resource Sharing Hardware Description Language HDL Codi
253. are different for different architectures Defaults for selected architectures are shown below XST User Guide 318 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST Design Constraints XILINX Devices Default Value Virtex 4 32 Spartan 3E 24 Spartan 3A Spartan 3A DSP bufg Number of Global Clock Buffers Syntax Example xst run bufg 8 Sets the number of global clock buffers to 8 bufr Number of Regional Clock Buffers bufr Number of Regional Clock Buffers controls the maximum number of BUFRs created by XST The value is an integer The default value depends on the target device and is equal to the maximum number of available BUFRs bufr Number of Regional Clock Buffers Architecture Support e May be used with Virtex 4 devices only e May NOT be used with Virtex 5 devices e Does not apply to CPLD devices bufr Number of Regional Clock Buffers Applicable Elements Applies to the entire design bufr Number of Regional Clock Buffers Propagation Rules Not applicable To set the number of regional clock buffers in ISE Design Suite 1 Select Process gt Properties gt Xilinx Specific Options 2 From the Property display level list select Advanced 3 Setthe Number of Regional Clock Buffers property bufr Number of Regional Clock Buffers Syntax xst run bufr integer The value is an integer and cannot exceed the maximum number of BUFRs for the target device bufr Number of
254. ary or hexadecimal e There should be as many lines in the file as there are rows in the RAM array e Following is an example of the contents of a file initializing an 8 x 32 bit RAM with binary values 00001111000011110000111100001111 01001010001000001100000010000100 0000000001111100000000001000001 1111101010000011100010000100100 0001111000011110000111100001111 1001010001000001100000010000100 0000000001111100000000001000001 1111101010000011100010000100100 0 1 0 0 0 1 XST User Guide 174 www xilinx com UG627 v 11 3 September 16 2009 hapter 3 XST Hardware Description Language HDL Coding Techniques XILINX Initializing Block RAM External Data File RAM initial values may be stored in an external data file that is accessed from within the HDL code The data file must be pure binary or hexadecimal content with no comments or other information Following is an example of the contents of a file initializing an 8 x 32 bit RAM with binary values For both examples the data file referenced is called rams_20c data 00001111000011110000111100001111 01001010001000001100000010000100 00000000001111100000000001000001 11111101010000011100010000100100 00001111000011110000111100001111 01001010001000001100000010000100 00000000001111100000000001000001 11111101010000011100010000100100 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 175 XILINX Chapter i X
255. as ERROR Xst 1363 Option verilog2002 is not available for command run Custom Compile File List Use the Custom Compile File List property to change the order in which source files are processed by XST With this property you select a user defined compile list file that XST uses to determine the order in which it processes libraries and design files Otherwise XST uses an automatically generated list List all design files and their libraries in the order in which they are to be compiled from top to bottom Type each file and library pair on its own line with a semicolon separating the library from the file as follows library name file name library name file name Following is an example work stopwatch vhd work statmach vhd Since this property is not connected to Simulation Properties Custom Compile File List a different compile list file is used for synthesis than for simulation VHDL Attribute Syntax You can describe constraints with VHDL attributes in the VHDL code Before it can be used an attribute must be declared with the following syntax attribute AttributeName Type VHDL Attribute Syntax Example One attribute RLOC string The attribute type defines the type of the attribute value The only allowed type for XST is string An attribute can be declared in an entity or architecture If declared in the entity it is visible both in the entity and the architecture body If the attribute is declared in
256. ase Implementation Style Syntax vlgcase full parallel full parallel By default there is no value vigcase Case Implementation Style Syntax Example xst run vlgcase full Defines Case Implementation Style globally to parallel define Verilog Macros define Verilog Macros allows you to define or redefine Verilog macros This allows you to easily modify the design configuration without any Hardware Description Language HDL source modifications such as for IP core generation and testing flows If the defined macro is not used in the design no message is given define is valid for Verilog designs only To define Verilog macros in ISE Design Suite 1 Select Process Properties Synthesis Options 2 From the Property display level list select Advanced 3 Setthe Verilog Macros property Do not use curly braces when specifying macros define Verilog Macros Architecture Support Architecture independent define Verilog Macros Applicable Elements Applies to the entire design define Verilog Macros Propagation Rules Not applicable define Verilog Macros Syntax define name value name value e name is a macro name e v lue is the macro text The default is an empty definition define XST User Guide 268 www xilinx com UG627 v 11 3 September 16 2009 taptir i XST Design Constraints XILINX Note e Values for macros are not mandatory e Place the
257. ated and made available to the implementation tools The object to which an implementation constraint is attached is preserved A binary equivalent of the implementation constraint is written to the NGC file Since the file is binary you cannot edit an implementation constraint in the NGC file You can code an implementation constraint in the XST Constraint File XCF as illustrated in Implementation Constraints Syntax Examples For more information see the Constraints Guide Implementation Constraints Syntax Examples This section gives the following Implementation Constraints syntax examples e Implementation Constraints XST Constraint File XCF Syntax Examples e Implementation Constraints VHDL Syntax Examples e Implementation Constraints Verilog Syntax Examples Implementation Constraints XST Constraint File XCF Syntax Examples To apply an implementation constraint to an entire entity use either of the following XST Constraint File XCF syntaxes MODEL EntityName PropertyName MODEL EntityName PropertyName PropertyValue To apply an implementation constraint to specific instances nets or pins within an entity use either of the following syntaxes BEGIN MODEL EntityName NET INST PIN NetName InstName SigName PropertyName END BEGIN MODEL EntityName NET INST PIN NetName InstName SigName PropertyName Propertyvalue END Implementation Constraints VHDL Syntax Examples Specify implementation const
258. ators Unsupported Static Expressions Supported XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 399 XILINX Chapter 7 XST VHDL Language Support VHDL Statements XST supports all VHDL statements except as noted below e VHDL Wait Statements e VHDL Loop Statements e VHDL Concurrent Statements VHDL Wait Statements Wait Statement Supported Unsupported Wait on sensitivity_list until Boolean_expression For more Supported with one signal in the sensitivity list and in the information see VHDL Sequential Circuits Boolean expression In case of multiple Wait statements the sensitivity list and the Boolean expression must be the same for each Wait statement Note XST does not support Wait statements for latch descriptions Wait for time expression For more information see VHDL Unsupported Sequential Circuits Assertion Statement Supported only for static conditions Signal Assignment Supported delay is ignored Statement VHDL Loop Statements for loop end loop Supported for constant bounds only Disable statements are not supported loop end loop Only supported in the particular case of multiple Wait statements VHDL Concurrent Statements Concurrent Statement Supported Unsupported Concurrent Signal Supported no after clause no transport or guarded options no waveforms UNAFFECTED is supported Assignment Statement F If Generate Statement supported for
259. ault tries to infer and implement the maximum macro configuration To shape a macro in a specific way use the Keep KEEP constraint For example DSP48 allows you to implement a multiple with two input registers To leave the first register stage outside of the DSP48 place the Keep KEEP constraint in their outputs Use DSP48 values are e auto default yes no e true XCF only e false XCF only In auto mode you can control the number of available DSP48 resources for synthesis using DSP Utilization Ratio DSP UTILIZATION RATIO By default XST tries to utilize as much as possible all available DSP48 resources For more information see DSP48 Block Resources USE DSPA8 Use DSP48 Architecture Support Applies to the following FPGA devices only Does not apply to any other FPGA devices Does not apply to CPLD devices e Spartan 3A DSP e Virtex 4 e Virtex 5 XST User Guide 346 www xilinx com UG627 v 11 3 September 16 2009 taptir i XST Design Constraints XILINX USE _DSP48 Use DSP48 Applicable Elements Applies to e Anentire design through the XST command line e A particular block entity architecture component e A signal representing a macro described at the RTL level USE DSPA8 Use DSP48 Propagation Rules Applies to the entity component module or signal to which it is attached USE DSP48 Use DSP48 Syntax Examples The following examples show how to use this constraint with particul
260. avioral Verilog Function Declared Within a Module Coding Example described with a task is shown in the following coding example Behavioral Verilog Function Declared Within a Module Coding Example module comb15 A B CIN S COUT input 3 0 A B input CIN output 3 0 S output COUT wire 1 0 S0 S1 S2 S3 function signed 1 0 ADD input A B CIN reg S COUT begin S A B CIN COUT A amp B A amp CIN B amp CIN ADD COUT S end endfunction assign SO ADD A 0 B 0 CIN S1 ADD A 1 B 1 SO 1 S2 ADD A 2 B 2 S1 11 S3 ADD A 3 B 3 S2 1 2 S S S3 0 S2 0 S1 0 SO 0 COUT S3 1 endmodule XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 431 XILINX Chapter 1 XST Behavioral Verilog Language Support Behavioral Verilog Task Declaration and Task Enable Coding Example The following coding example shows the Behavioral Verilog Function Declared Within a Module Coding Example described with a task module EXAMPLE A B CIN S COUT input 3 0 A B input CIN output 3 0 S output COUT reg 3 0 S reg COUT reg 1 0 SO S1 S2 S3 task ADD input A B CIN output 1 0 C reg 1 0 C reg S COUT begin S A B CIN COUT A amp B A amp CIN B amp CIN C COUT S end endtask always A or B or CIN begin ADD A 0 B 0 CIN S0 ADD A 1 B 1 SO 1 S1 ADD A 2
261. b101 else if sel 6 code 3 b110 else if sel 7 code 3 b111 else code 3 bxxx end endmodule Logical Shifters Hardware Description Language HDL Coding Techniques Xilinx defines a logical shifter as a combinatorial circuit with 2 inputs and 1 output e The first input is a data input that is shifted e The second input is a selector whose binary value defines the shift distance e The output is the result of the shift operation All of these I Os are mandatory Otherwise XST does not infer a logical shifter When writing your Hardware Description Language HDL code e Use only logical arithmetic and rotate shift operators Shift operations that fill vacated positions with values from another signal are not recognized e For VHDL you can use predefined shift for example SLL SRL ROL or concatenation operations only For more information on predefined shift operations see the IEEE VHDL reference manual e Use only one type of shift operation Then value in the shift operation must be incremented or decremented only by 1 for each consequent binary value of the selector Then value can be positive only e All values of the selector must be presented XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 81 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Logical Shifters Log File The XST log file reports the type and size of a recognized logical shifter du
262. begin Y lt A nand B end ARCHI entity HALFADDER is port X Y v in BIT Cra out BIT end HALFADDER architecture ARCHI of HALFADDER is component NAND2 port A B in BIT Y out BIT end component for all NAND2 use entity work NAND2 ARCHI signal S1 S2 S3 BIT begin NANDA NAND2 port map X Y S3 NANDB NAND2 port map X S3 S1 NANDC NAND2 port map S3 Y S2 NANDD NAND2 port map S1 S2 S C lt S3 end ARCHI Synthesized Top Level Netlist Diagram VHDL Recursive Component Instantiation XST supports recursive component instantiation Direct instantiation is not supported for recursion To prevent endless recursive calls the number of recursions is limited by default to 64 Use the recursion iteration limit option to control the number of allowed recursive calls XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 379 XILINX Chapter 7 XST VHDL Language Support 4 Bit Shift Register With Recursive Component Instantiation VHDL Coding Example library ieee use ieee std_logic_1164 all library unisim use unisim vcomponents all entity single_stage is generic sh_st integer 4 port CLK in std_logic DI i in std logic DO out std logic iz end entity single stage architecture recursive of single stage is component single stage generic sh st integer port CLK in std logic DI in std logic DO ou
263. begin case s is when 00 gt o lt a when 01 gt o lt b when 10 gt o lt c when others gt o lt d end case end process end archi 4 to 1 1 Bit MUX Using Case Statement Verilog Coding Example 4 to 1 1 bit MUX using a Case statement L module v_multiplexers_2 a b c d s 0 input a b c d input 1 0 s output 0 reg o always a or b or c or d or s begin case s 2 b00 o a 2 b01 o b 2 b10 0 default o d endcase end endmodule 4 to 1 1 Bit MUX Using Tristate Buffers Diagram Oo S 3 S 2 S 1 S 0 um p ob o gt x10544 XST User Guide 72 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX 4 to 1 1 Bit MUX Using Tristate Buffers Pin Descriptions 10 Pins Beseription S Data Inputs MUX Selector Data Output 4 to 1 1 Bit MUX Using Tristate Buffers VHDL Coding Example 4 to 1 1 bit MUX using tristate buffers library ieee use ieee std logic 1164 all entity multiplexers 3 is port a b c d in std logic S in std logic vector 3 downto 0 o out std logic end multiplexers 3 architecture archi of multiplexers 3 is begin o lt a when s 0 0 else i o lt b when s 1 2 0 else zi o lt c when s 2 0 else Z o lt d when s 3 0 else Z end archi 4 to 1 1 Bit MUX Using Tris
264. bind this component to a particular design unit from a particular library Such binding is not supported Only default Verilog module binding is supported The only Verilog construct that can be instantiated in a VHDL design is a Verilog module No other Verilog constructs are visible to VHDL code During elaboration all components subject to default binding are regarded as design units with the same name as the corresponding component name During binding XST treats a component name as a VHDL design unit name and searches for it in the logical library work If XST finds a VHDL design unit XST binds it If XST cannot find a VHDL design unit it treats the component name as a Verilog module name and searches for it using a case sensitive search XST searches for the Verilog module in the user specified list of unified logical libraries in the user specified search order For more information see Library Search Order LSO Files in Mixed Language Projects XST selects the first Verilog module matching the name and binds it Since libraries are unified a Verilog cell by the same name as that of a VHDL design unit cannot co exist in the same logical library A newly compiled cell unit overrides a previously compiled one Instantiating a VHDL Design Unit in a Verilog Design To instantiate a VHDL entity 1 Declare a module name with the same as name as the VHDL entity optionally followed by an architecture name that you want to instantiate 2
265. ble pld_ce yes no Macro Preserve pld_mp yes no default yes XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 261 XILINX nuit t XST Design Constraints XOR Preserve pld_xp yes no default yes Reduce Control Sets reduce_control_sets no default no Generate RTL Schematic rtlview yes no only default no Cores Search Directories directories default N A Slice Packing slice_packing no default yes Top Level Block top block_name pee Synthesis Constraints File uc file name xcf deme Verilog 2001 verilog2001 yes no default yes Case Implementation Style vlgcase full parallel full parallel default N A Verilog Include Directories vlgincdir directories m RA Work Library work lib directory e eee wysiwyg wysiwyg yes no default no Work Directory xsthdpdir Directory BRENNEN fo HDL Library Mapping File xsthdpini file name ini mom dex XST User Guide 262 www xilinx com UG627 v 11 3 September 16 2009 hapter t XST Design Constraints XILINX XST Timing Options You can invoke XST timing options from e ISE Design Suite Process gt Properties e The command line e The XST Constraint File XCF XST Timing Options Process gt Properties or Command Line The following table shows the XST timing constraints that you can invoke only from ISE Design Suite Process gt Properties or from the command line XST Timing Constraints Supported Only
266. buted block powerl block power2 END RAM STYLE RAM Style XST Command Line Syntax Example Define in the XST command line as follows xst run ram style auto block distributed The default is auto The pipe distributed value is not accessible through the command line RAM STYLE RAM Style ISE Design Suite Syntax Example Define in ISE Design Suite with Process Properties HDL Options RAM Style REDUCE CONTROL SETS Reduce Control Sets REDUCE CONTROL SETS Reduce Control Sets allows you to reduce the number of control sets and as a consequence reduce the design area Reducing the control set number should improve the packing process in map and therefore reduce the number of used slices even if the number of LUTs is increased XST User Guide 324 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST Design Constraints XILINX REDUCE CONTROL SETS supports two values auto XST optimizes automatically and reduces the existing control sets in the design no XST performs no control set optimization REDUCE CONTROL SETS Reduce Control Sets Architecture Support Applies to Virtex 5 devices only Does not apply to any other FPGA devices Does not apply to CPLD devices REDUCE CONTROL SETS Reduce Control Sets Applicable Elements Applies to the entire design REDUCE CONTROL SETS Reduce Control Sets Propagation Rules Not applicable REDUCE CONTROL SETS Reduce Control Sets S
267. by MAP e Partition Resource Summary The Partition Resource Summary estimates the number of slices and gives for example the number of flip flops IOBs and BRAMS for each partition The Partition Resource Summary closely resembles the report produced by MAP e Timing Report At the end of synthesis XST reports the timing information for the design The Timing Report shows the information for all four possible domains of a netlist register to register input to register register to outpad inpad to outpad For an example see the Timing Report section in XST FPGA Log File Example For more information see FPGA Optimization Report Section e Encrypted Modules If a design contains encrypted modules XST hides the information about these modules Reducing the Size of the XST Log File To reduce the size of the XST log file e Use Message Filtering e Use Quiet Mode e Use Silent Mode e Hide Specific Messages Use Message Filtering When running XST from ISE Design Suite use the Message Filtering wizard to select specific messages to filter out of the log file For more information see Using the Message Filters in the ISE Design Suite Help XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 449 XILINX Chapter 11 XST Log File Use Quiet Mode Quiet Mode limits the number of messages printed to the computer screen stdout To invoke Quiet Mode set the intstyle command line option to
268. c vector 5 downto 0 dpra in std logic vector 5 downto 0 di in std logic vector 15 downto 0 Spo out std logic vector 15 downto 0 dpo out std logic vector 15 downto 0 end rams 09 architecture syn of rams 09 is type ram type is array 63 downto 0 of std logic vector 15 downto 0 signal RAM ram type begin process clk begin if clk event and clk 1 then if we 1 then RAM conv integer a di end if end if end process spo lt RAM conv integer a dpo lt RAM conv integer dpra end syn Dual Port RAM With Asynchronous Read Verilog Coding Example Dual Port RAM with Asynchronous Read module v_rams_09 clk we a dpra di spo dpo input elk input we input 5 0 a input 5 0 dpra input 15 0 di output 15 0 spo output 15 0 dpo reg 15 0 ram 63 0 always posedge clk begin if we ram a lt di end assign spo ram a assign dpo ram dpra endmodule The following descriptions are directly mappable onto block RAM as shown in the diagram below They may also be implemented with Distributed RAM XST User Guide 142 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX Dual Port RAM With Synchronous Read Read Through Diagram DPRA WE DI A CLK Block SPO RAM DPO Dual Port RAM With Synchronous Read Read Through Pin Description
269. can set a variety of options for XST For more information on setting XST options see ISE Design Suite Help e XST Design Constraints e XST Command Line Mode XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 19 XILINX Chapter 2 Introduction to Xilinx Synthesis Technology XST Designs are usually made up of combinatorial logic and macros such as flip flops adders subtractors counters FSMs and RAMs The macros greatly improve performance of the synthesized designs It is important to use coding techniques to model the macros so they are optimally processed by XST XST first tries to recognize infer as many macros as possible These macros are then passed to the Low Level Optimization step In order to obtain better optimization results the macros are either preserved as separate blocks or merged with surrounded logic This filtering depends on the type and size of a macro For example by default 2 to 1 multiplexers are not preserved by the optimization engine Synthesis constraints control the processing of inferred macros For more information see XST Design Constraints XST User Guide 20 www xilinx com UG627 v 11 3 September 16 2009 XILINX Chapter 3 XST Hardware Description Language HDL Coding Techniques This chapter gives Hardware Description Language HDL coding examples for digital logic circuits This chapter includes Signed and Unsigned Support in XST Registers Hardw
270. ce XST was unable to satisfy the target area constraint XST issues the following warning Found area constraint ratio of 70 5 on block fpga_hm actual ratio is 64 Optimizing block lt fpga_hm gt to meet ratio 70 5 of 1536 slices WARNING Xst Area constraint could not be met for block lt tge gt final ratio is 94 Note 5 stands for the max margin of the area constraint If the area constraint is not met but the difference between the requested area and obtained area during area optimization is less or equal then 5 then XST runs timing optimization taking into account the achieved area not exceeding it Speed Optimization Under Area Constraint Example Three 55 In the following example the area was specified as 5576 XST achieved only 6076 But taking into account that the difference between requested and achieved area is not more than 5 XST considers that the area constraint was met Found area constraint ratio of 55 5 on block fpga hm actual ratio is 64 Optimizing block fpga hm to meet ratio 55 5 of 1536 slices Area constraint is met for block fpga hm final ratio is 60 In some situations it is important to disable automatic resource management To do so specify 1 as the value for SLICE UTILIZATION RATIO Slice LUT FF Pairs Utilization Ratio SLICE UTILIZATION RATIO can be attached to a specific block of a design You can specify an absolute number of slices or FF LUT pairs as a percentag
271. ch xst file especially if you use many options to run synthesis place each option with its value on a separate line Observe the following rules e The first line contains only the run command without any options There are no blank lines in the middle of the command e Each line except the first one begins with a dash For the previous command example the stopwatch xst file should look like run ifn watchver prj ifmt mixed ofn watchver ngc ofmt NGC p xc5vfx30t 2 rff324 opt mode Speed opt level 1 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 485
272. chi Logical Shifter Two Verilog Coding Example XST does not infer a logical shifter for this example as not all of the selector values are presented module v logical shifters 2 DI SEL SO input 7 0 DI input 1 0 SEL output 7 0 SO reg 7 0 SO always DI or SEL begin case SEL 2 b00 SO DI 2 b01 SO DI lt lt 1 default SO DI lt lt 2 endcase end endmodule Logical Shifter Three Pin Descriptions CR EE SEL Shift Distance Selector XST User Guide 84 www xilinx com UG627 v 11 3 September 16 2009 hapter 3 XST Hardware Description Language HDL Coding Techniques XILINX Logical Shifter Three VHDL Coding Example XST does not infer a logical shifter for this example as the value is not incremented by 1 for each consequent binary value of the selector XST does not infer a logical shifter for this example as the value is not incremented by 1 for each consequent binary value of the selector library ieee use ieee std logic 1164 all use ieee numeric std all entity logical shifters 3 is port DI in unsigned 7 downto 0 SEL in unsigned 1 downto 0 SO out unsigned 7 downto 0 end logical shifters 3 architecture archi of logical shifters 3 is begin with SEL select SO lt DI when 00 DI sll 1 when 01 DI sll 3 when 10 DI sll 2 when others end archi Logical Shifter Three Verilog Coding Example XST does n
273. cific Options Use Clock Enable USE SYNC SET Use Synchronous Set USE SYNC SET Use Synchronous Set enables or disables the synchronous set function in flip flops The disabling of the synchronous set function is typically used for ASIC prototyping on FPGA devices Detecting Use Synchronous Set with a value of no or false XST avoids using synchronous reset resources in the final implementation Moreover for some designs putting synchronous reset function on data input of the flip flop allows better logic optimization and therefore better QOR In auto mode XST tries to estimate a trade off between using dedicated Synchronous Set input of a flip flop input and putting Synchronous Set logic on the D input of a flip flop In a case where a flip flop is instantiated by you XST removes the synchronous reset only if the Optimize Instantiated Primitives option is set to yes USE SYNC SET Use Synchronous Set values are e auto default yes no e true XCF only e false XCF only USE SYNC SET Use Synchronous Set Architecture Support Applies to all FPGA devices Does not apply to CPLD devices USE SYNC SET Use Synchronous Set Applicable Elements Applies to e An entire design through the XST command line e A particular block entity architecture component Asignal representing a flip flop e An instance representing an instantiated flip flop XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 343
274. citly specify them if needed using REGISTER POWERUP Register Power Up This XST synthesis constraint can be assigned to a VHDL enumerated type or it may be directly attached to a VHDL signal or a Verilog register node through a VHDL attribute or Verilog meta comment The value may be a binary string or a symbolic code value REGISTER POWERUP Register Power Up Architecture Support Applies to the following devices only Does not apply to any other devices e All CPLD devices e Spartan 3A devices REGISTER POWERUP Register Power Up Applicable Elements Applies to signals or types REGISTER POWERUP Register Power Up Propagation Rules Applies to the signal or type to which it is attached REGISTER POWERUP Register Power Up Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 291 XILINX nuit t XST Design Constraints REGISTER_POWERUP Register Power Up VHDL Syntax Example One The register is defined with a predefined VHDL type such as std_logic_vector The REGISTER_POWERUP value is necessarily a binary code signal myreg std_logic_vector 3 downto 0 attribute register_powerup of myreg signal is 0001 REGISTER_POWERUP Register Power Up VHDL Syntax Example Two The register is defined with an enumerated type symbolic state
275. ck signal signal net in model distributed pipe_distributed block_power1 block_power2 XST Design Constraints distributed default auto block Read Cores Register Balancing Register Duplication Ee Power Resource Sharing ROM Extraction ROM Style XST User Guide yes no optimize yes no forward backward entity component entity signal FF instance name entity signal module label module signal FF instance name primary clock signal model inst in model modelnet in model inst in model model net in model register _balancing register _duplication yes no optimize default yes yes no forward backward default no yes no default yes auto block distributed entity signal entity signal entity signal signal inst of primitive UG627 v 11 3 September 16 2009 module signal module signal module signal signal inst of primitive www xilinx com d net in model model net in model model net in model net in model inst of primitive in model resource _sharing rom extract rom _style no default yes yes no default yes auto block distributed default auto XILINX Gate Implementation Chapter b safe yes entity module model no signal signal net in model _implementation XST Design Constraints g Constraint VHDL
276. cks There must be no space between the integer value and the percent or pound characters In some situations you can disable automatic BRAM resource management for example to see how many BRAMs XST can potentially infer for a specific design To disable automatic resource management specify 1 or any negative value as a constraint value BRAM UTILIZATION RATIO BRAM Utilization Ratio ISE Design Suite Syntax Example Define in ISE Design Suite with Process Properties Synthesis Options BRAM Utilization Ratio In ISE Design Suite you can define the value of BRAM Utilization Ratio only as a percentage The definition of the value in the form of absolute number of BlockRAMs is not supported BUFFER TYPE Buffer Type Buffer Type BUFFER TYPE is a new name for CLOCK BUFFER Since CLOCK BUFFER will become obsolete in future releases Xilinx recommends that you use this new name BUFFER TYPE selects the type of buffer to be inserted on the input port or internal net The bufr value is supported for Virtex 4 devices and Virtex 5 devices only BUFFER TYPE Buffer Type Architecture Support Applies to all FPGA devices Does not apply to CPLD devices BUFFER TYPE Buffer Type Applicable Elements Applies to signals XST User Guide 300 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST Design Constraints XILINX BUFFER_TYPE Buffer Type Propagation Rules Applies to the signal to which it is attac
277. clock signals BUFGCE Extract BUFGCE Propagation Rules Applies to the signal to which it is attached BUFGCE Extract BUFGCE Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 301 XILINX nuit t XST Design Constraints BUFGCE Extract BUFGCE VHDL Syntax Example Declare as follows attribute bufgce string Specify as follows attribute bufgce of signal_name signal is yes no BUFGCE Extract BUFGCE Verilog Syntax Example Place immediately before the signal declaration bufgce yes no BUFGCE Extract BUFGCE XST Constraint File XCF Syntax Example BEGIN MODEL entity_name NET primary_clock_signal bufgce yes no true false END sd Cores Search Directories sd Cores Search Directories tells XST to look for cores in directories other than the default By default XST searches for cores in the directory specified in the ifn option sd Cores Search Directories Architecture Support Applies to all FPGA devices Does not apply to CPLD devices sd Cores Search Directories Applicable Elements Applies to the entire design sd Cores Search Directories Propagation Rules Not applicable Set this value in ISE Design Suite in Process gt Properties gt Synthesis Options gt Cores Sea
278. ctive High XST User Guide 56 www xilinx com UG627 v 11 3 September 16 2009 nuit XST Hardware Description Language HDL Coding Techniques XILINX 8 Bit Shift Left Register With Positive Edge Clock Asynchronous Reset Serial In and Serial Out VHDL Coding Example 8 bit Shift Left Register with Positive Edge Clock Asynchronous Reset Serial In and Serial Out library ieee use ieee std logic 1164 all entity shift registers 3 is port C SI CLR in std logic SO out std logic end shift registers 3 architecture archi of shift registers 3 is signal tmp std logic vector 7 downto 0 begin process C CLR begin if CLR 1 then tmp lt others gt 0 elsif C event and C 1 then tmp lt tmp 6 downto 0 amp SI end if end process SO lt tmp 7 end archi 8 Bit Shift Left Register With Positive Edge Clock Asynchronous Reset Serial In and Serial Out Verilog Coding Example 8 bit Shift Left Register with Positive Edge Clock Asynchronous Reset Serial In and Serial Out module v_shift_registers_3 C CLR SI SO input C SI CLR output SO reg 7 0 tmp always 8 posedge C or posedge CLR begin if CLR tmp lt 8 b00000000 else tmp lt tmp 6 0 SI end assign SO tmp 7 endmodule XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 57 XILINX Chapter i XST Hardware Description Language HDL Coding Techni
279. cture to create a 4 bit adder The same example using a procedure is shown in Procedure Declaration and Procedure Call VHDL Coding Example package PKG is function ADD A B CIN BIT return BIT VECTOR end PKG package body PKG is function ADD A B CIN BIT return BIT VECTOR is variable S COUT BIT variable RESULT BIT VECTOR 1 downto 0 begin S A xor B xor CIN COUT A and B or A and CIN or B and CIN RESULT COUT amp S return RESULT end ADD end PKG use work PKG all entity EXAMPLE is port A B in BIT_VECTOR 3 downto 0 CIN in BIT S out BIT VECTOR 3 downto 0 COUT out BIT end EXAMPLE architecture ARCHI of EXAMPLE is signal S0 S1 S2 S3 BIT VECTOR 1 downto 0 begin SO lt ADD A 0 B 0 CIN S1 lt ADD A 1 B 1 S0 1 S2 lt ADD A 2 B 2 S1 1 S3 lt ADD A 3 B 3 S2 1 S lt 83 0 amp S2 0 amp S1 0 amp SO 0 COUT lt S3 1 end ARCHI XST User Guide 392 www xilinx com UG627 v 11 3 September 16 2009 hipter XST VHDL Language Support XILINX Procedure Declaration and Procedure Call VHDL Coding Example package PKG is procedure ADD A B CIN in BIT C out BIT VECTOR 1 downto 0 end PKG package body PKG is procedure ADD A B CIN in BIT C out BIT VECTOR 1 downto 0 is variable S COUT BIT begin S A xor B xor CIN COUT A and B or A and CIN or B and
280. d vhdl work decode vhd vhdl work stopwatch vhd vhdl work cnt60 vhd vhdl work smallcntr vhd vhdl work tenths vhd vhdl my lib hex2led vhd If XST does not recognize the order it issues the following warning WARNING XST 3204 The sort of the vhdl files failed they will be compiled in the order of the project fil In this case you must e Put all VHDL files in the correct order e Add the hdl compilation order option with value user to the XST run command run ifn watchvhd prj ifmt mixed top stopwatch ofn watchvhd ngc ofmt NGC p XC5vfx30t 2 ff324 opt mode Speed opt level 1 top hex2led hdl compilation order user XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 481 XILINX Ctapter 13 XST Command Line Mode Running XST in Script Mode VHDL It can be tedious to enter XST commands directly in the XST shell especially when you have to specify several options and execute the same command several times To run XST in script mode 1 Opena new file named stopwatch xst in the current directory Put the previously executed XST shell command into this file and save it run ifn watchvhd prj ifmt mixed top stopwatch ofn watchvhd ngc ofmt NGC p xc5vfx30t 2 ff324 opt mode Speed opt level 1 2 From the tesh or other shell enter the following command to begin synthesis xst ifn stopwatch xst During this run XST creates the following files e watchvhd ngc An NGC file ready for the imple
281. d constants of the design such as constant values and function definitions Packages may contain two declarative parts e Body declaration e Package declaration The body declaration includes the description of function bodies declared in the package declaration XST provides full support for packages To use a given package include the following lines at the beginning of the VHDL design library lib_pack lib pack is the name of the library specified where the package has been compiled work by default use lib pack pack name all pack name is the name of the defined package XST also supports predefined packages These packages are pre compiled and can be included in VHDL designs These packages are intended for use during synthesis but may also be used for simulation Using Standard Packages to Define VHDL Models The Standard package contains basic types bit bit vector e integer The Standard package is included by default XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 395 XILINX Chapter 2 XST VHDL Language Support Using IEEE Packages to Define VHDL Models XST supports the following IEEE packages e std_logic_1164 Supports the following types std logic std ulogic std logic vector std ulogic vector It also supports conversion functions based on these types numeric bit Supports the following types based on type bit Unsigned vectors Signed vectors
282. d sub 1 then accum lt accum mult else accum lt accum mult end if mult lt A B end if end if end process RES lt accum end beh XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 121 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Multiplier Up Down Accumulate With Register After Multiplication Verilog Coding Example Multiplier Up Down Accumulate with Register After Multiplication ek module v multipliers 7b clk reset add sub A B RES input clk reset add sub input 7 0 A input 7 0 B output 15 0 RES reg 15 0 mult accum always posedge clk begin if reset mult lt 16 b0000000000000000 else mult lt A B end always posedge clk begin if reset accum lt 16 b0000000000000000 else if add sub accum lt accum mult else accum lt accum mult end assign RES accum endmodule Dividers Hardware Description Language HDL Coding Techniques Dividers are supported only when the divisor is a constant and is a power of 2 In that case the operator is implemented as a shifter Otherwise XST issues an error message Dividers Log File When you implement a divider with a constant with the power of 2 XST does not issue any message during the Macro Recognition step If the divider does not correspond to the case supported by XST then XST issues the following error message ER
283. d using internal signals which are assigned in the sequential process State Encoding Techniques XST supports the following state encoding techniques e Auto State Encoding e One Hot State Encoding e Gray State Encoding e Compact State Encoding Johnson State Encoding e Sequential State Encoding e Speed1 State Encoding e User State Encoding XST User Guide 190 www xilinx com UG627 v 11 3 September 16 2009 Chipter XST Hardware Description Language HDL Coding Techniques XILINX Auto State Encoding In Auto State Encoding XST tries to select the best suited encoding algorithm for each FSM One Hot State Encoding One Hot State Encoding is the default encoding scheme Its principle is to associate one code bit and also one flip flop to each state At a given clock cycle during operation one and only one bit of the state variable is asserted Only two bits toggle during a transition between two states One Hot State Encoding is appropriate with most FPGA targets where a large number of flip flops are available It is also a good alternative when trying to optimize speed or to reduce power dissipation Gray State Encoding Gray State Encoding guarantees that only one bit switches between two consecutive states It is appropriate for controllers exhibiting long paths without branching In addition this coding technique minimizes hazards and glitches Very good results can be obtained when implementing the state register
284. dd I O Buffers Applicable Elements XST User Guide 264 www xilinx com UG627 v 11 3 September 16 2009 taptir i XST Design Constraints XILINX Applies to the entire design iobuf Add I O Buffers Propagation Rules Applies to design primary IOs iobuf Add I O Buffers Syntax iobuf yes no true false soft Allowed values are e yes the default tells XST to generate IBUF and OBUF primitives and connected them to I O ports of the top level module e no tells XST not to generate IBUF and OBUF primitives and must be used when XST is called to synthesize an internal module that is instantiated later in a larger design If I O buffers are added to a design this design cannot be used as a submodule of another design true false soft iobuf Add UO Buffers Syntax Example xst run iobuf yes This command line example adds I O buffers to the top level module of the design BOX TYPE BoxType BOX TYPE BoxType is a synthesis constraint BOX TYDE values are e primitive black box user black box These values instruct XST not to synthesize the behavior of a module The black box value is equivalent to primitive It will eventually become obsolete If user black box is specified XST reports inference of a black box in the log file It does not do so if primitive is specified If BOX TYPE is applied to at least a single instance of a block of a design BOX TYPE is propagated to all other instances
285. de UG627 v 11 3 September 16 2009 www xilinx com 183 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques ROM With Registered Address Verilog Coding Example ROMs Using Block RAM Resources Verilog code for a ROM with registered address module v rams 21c clk en addr data input clk input en input 5 0 addr output reg 19 0 data reg 5 0 raddr always posedge clk begin if en raddr lt addr end always raddr begin case raddr 6 b000000 data lt 20 h0200A 6 b100000 data lt 20 h02222 6 b000001 data lt 20 h00300 6 b100001 data lt 20 h04001 6 5000010 data lt 20 h08101 6 5100010 data lt 20 h00342 6 b000011 data lt 20 h04000 6 b100011 data lt 20 h0232B 6 5000100 data lt 20 h08601 6 b100100 data lt 20 h00900 6 b000101 data lt 20 h0233A 6 5100101 data lt 20 h00302 6 5000110 data lt 20 h00300 6 5100110 data lt 20 h00102 6 b000111 data lt 20 h08602 6 b100111 data lt 20 h04002 6 b001000 data lt 20 h02310 6 b101000 data lt 20 h00900 6 b001001 data lt 20 h0203B 6 b101001 data lt 20 h08201 6 5001010 data lt 20 h08300 6 5101010 data lt 20 h02023 6 5001011 data lt 20 h04002 6 b101011 data lt 20 h00303 6 b001100 data lt 20 h08201 6 5101100 data lt 20 h02433 6 b001101 data lt 20 h00500 6 b101101 data lt 20 h003
286. de is padded to the left according to the following rules e If the right hand expression is signed the left hand expression is padded with the sign bit 0 for positive 1 for negative z for high impedance x for unknown e If the right hand expression is unsigned the left hand expression is padded with Os zeroes e For unsized x or z constants only the following rule applies If the value of the right hand expression s left most bit is z high impedance or x unknown regardless of whether the right hand expression is signed or unsigned the left hand expression is padded with that value z or x respectively The above rules follow the Verilog 2001 standard They are not backward compatible with Verilog 1995 Behavioral Verilog Tasks and Functions The declaration of a function or task is intended for handling blocks used multiple times in a design They must be declared and used in a module The heading part contains the parameters input parameters only for functions and input output inout parameters for tasks The return value of a function can be declared either signed or unsigned The content is similar to the combinatorial always block content The Behavioral Verilog Function Declared Within a Module Coding Example shows a function declared within a module The ADD function declared is a single bit adder This function is called four times with the proper parameters in the architecture to create a 4 bit adder The Beh
287. der to simplify instantiation of such complex primitives as RAMs XST supports an additional library called UniMacro UniMacro libraries are supported for Virtex 4 devices Virtex 5 devices and newer devices For more information see the Libraries Guides In VHDL declare library unimacro with its package vcomponents in your source code library unimacro use unimacro vcomponents all The source code of this package can be found in the vhdlNsrcN unisims unisims_vcomp vhd file in the XST installation In Verilog the UniMacro library is precompiled XST automatically links it with your design Cores Processing If a design contains cores represented by an Electronic Data Interchange Format EDIF or an NGC file XST can automatically read them for timing estimation and area utilization control Use ISE Design Suite Process gt Properties Synthesis Options Read Cores to enable or disable this feature Using the read cores option of the run command from the command line you can also specify optimize This enables cores processing and allows XST to integrate the core netlist into the overall design XST reads cores by default XST User Guide 224 www xilinx com UG627 v 11 3 September 16 2009 Chapter t XST FPGA Optimization XILINX Cores Processing VHDL Coding Example In the following VHDL coding example the block my_add is an adder which is represented as a black box in the design whose netlist was generated b
288. ding to a Latch Inference gt 3 to 1 1 bit MUX with a 1 bit latch library ieee use ieee std logic 1164 a11 entity multiplexers 4 is port a b c in std logic S in std logic vector 1 downto 0 o out std logic end multiplexers 4 architecture archi of multiplexers 4 is begin process a b C S begin if s 00 then o lt a elsif s 01 then o lt b elsif s 10 then o lt c end if end process end archi Verilog Coding Example of a Missing Else Statement Leading to a Latch Inference 3 to 1 1 bit MUX with a 1 bit latch module v multiplexers 4 a b C S o input a b c input 1 0 s output oi reg o always Q8 a or b or c or s begin if s 2 p00 o a else if s 2 b01 o b else if s 2 b10 o c end endmodule Decoders Hardware Description Language HDL Coding Techniques A decoder is a multiplexer whose inputs are all constant with distinct one hot or one cold coded values For more information see Multiplexers HDL Coding Techniques Decoders Log File The XST log file reports the type and size of recognized decoders during the Macro Recognition step Synthesizing Unit dec Related source file is decoders 1 vhd Found 1 of 8 decoder for signal res Summary inferred 1 Decoder s Unit dec synthesized HDL Synthesis Report XST User Guide 74 www xilinx com UG627 v 11 3 September 16 2009 nuit XST H
289. dmodule 4 Bit Latch With Inverted Gate and Asynchronous Set Diagram PRE XST User Guide 32 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX 4 Bit Latch With Inverted Gate and Asynchronous Set Pin Descriptions C i mma PRE Asynchronous Preset Active High ag T 7 4 Bit Latch With Inverted Gate and Asynchronous Set VHDL Coding Example 4 bit Latch with Inverted Gate and Asynchronous Set library ieee use ieee std logic 1164 all entity latches 3 is port D in std logic vector 3 downto 0 G PRE in std logic Q out std logic vector 3 downto 0 end latches_3 architecture archi of latches 3 is begin process PRE G D begin if PRE 1 then Q 1111 elsif G 0 then Q lt D end if end process end archi 4 Bit Latch With Inverted Gate and Asynchronous Set Verilog Coding Example 4 bit Latch with Inverted Gate and Asynchronous Set module v_latches_3 G D PRE Q input G PRE input 3 0 D output 3 0 Q reg 3 0 Q always G or D or PRE begin if PRE Q 4 b1111 else if G Q D end endmodule Tristates Hardware Description Language HDL Coding Techniques Tristate elements can be described using e Combinatorial process VHDL e Always block Verilog e Concurrent assignment XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 33
290. ds on the Optimization setting e If Optimization is set to area XST packs registers as tightly as possible to the IOBs in order to reduce the number of slices occupied by the design e If Optimization is set to speed XST packs registers to the IOBs provided they are not covered by timing constraints in other words they are not taken into account by timing optimization For example if you specify a period constraint XST packs a register to the IOB if it is not covered by the period constraint If a register is covered by timing optimization but you do want to pack it to an IOB you must apply the IOB constraint locally to the register For more information see IOB in the Constraints Guide PRIORITY EXTRACT Priority Encoder Extraction PRIORITY EXTRACT Priority Encoder Extraction enables or disables priority encoder macro inference PRIORITY EXTRACT values are e yes default e no e true XCF only e force XCF only For each identified priority encoder description based on some internal decision rules XST actually creates a macro or optimize it with the rest of the logic The force value allows you to override those decision rules and force XST to extract the macro PRIORITY_EXTRACT Priority Encoder Extraction Architecture Support Applies to all FPGA devices Does not apply to CPLD devices PRIORITY_EXTRACT Priority Encoder Extraction Applicable Elements Applies to the entire design or to an entity component
291. e module testkeep inl in2 out1 input inl input in2 output outil keep yes wire auxl keep yes wire aux2 assign auxl inl assign aux2 in2 assign outl auxl amp aux2 endmodule Third Party Constraints XST Constraint File XCF Syntax Example The Keep KEEP constraint can also be applied through the separate synthesis constraint file BEGIN MODEL testkeep NET auxl KEEP true END XILINX These are the only two ways of preserving a signal net in a Hardware Description Language HDL design and preventing optimization on the signal or net during synthesis XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 363 XST User Guide 364 www xilinx com UG627 v 11 3 September 16 2009 XILINX Chapter 7 XST VHDL Language Support This chapter explains how XST supports the VHSIC Hardware Description Language VHDL and provides details on VHDL supported constructs and synthesis options This chapter includes VHDL IEEE Support XST VHDL File Type Support Debugging Using Write Operation in VHDL VHDL Data Types VHDL Record Types VHDL Initial Values VHDL Objects VHDL Operators Entity and Architecture Descriptions in VHDL VHDL Combinatorial Circuits VHDL Sequential Circuits VHDL Functions and Procedures VHDL Assert Statements Using Packages to Define VHDL Models VHDL Constructs Supported in XST VHDL Reserved Words For more information see
292. e case e Case Implementation Style vlgcase e Verilog Macros define Duplication Suffix duplication suffix e Full Case FULL CASE e Generate RTL Schematic rtlview e Generics generics e Hierarchy Separator hierarchy separator e HO Standard IOSTANDARD e Keep KEEP e Keep Hierarchy KEEP_HIERARCHY e Library Search Order lso e LOC e Netlist Hierarchy netlist hierarchy Optimization Effort OPT LEVEL e Optimization Goal OPT MODE e Parallel Case PARALLEL CASE e RLOC e Save S SAVE e Synthesis Constraint File uc e Translate Off TRANSLATE_OFF and Translate On TRANSLATE_ON e Use Synthesis Constraints File iuc e Verilog Include Directories vlgincdir e Verilog 2001 verilog2001 e HDL Library Mapping File xsthdpini e Work Directory xsthdpdir iobuf Add UO Buffers iobuf Add I O Buffers enables or disables I O buffer insertion XST automatically inserts Input Output Buffers into the design If you manually instantiate I O Buffers for some or all the I Os XST inserts I O Buffers only for the remaining I Os If you do not want XST to insert I O Buffers set iobuf to no Add I O Buffers is useful to synthesize a part of a design to be instantiated later on You can set this value in ISE Design Suite by setting Process Properties Xilinx8 Specific Options Add I O Buffers iobuf Add I O Buffers Architecture Support Architecture independent iobuf A
293. e END glob_opt Global Optimization Goal Depending on the Global Optimization Goal XST can optimize the following design regions e Register to register e Inpad to register e Register to outpad e Inpad to outpad glob opt Global Optimization Goal selects the global optimization goal For a detailed description of supported timing constraints see Partitions You cannot specify a value for Global Optimization Goal XST optimizes the entire design for the best performance XST User Guide 354 www xilinx com UG627 v 11 3 September 16 2009 hapter XST Design Constraints XILINX Apply the following constraints with Global Optimization Goal e ALLCLOCKNETS register to register optimizes the period of the entire design XST will identify by default all paths from register to register on the same clock for all clocks in a design To take inter clock domain delays into account set Cross Clock Analysis cross_clock_analysis to yes OFFSET IN BEFORE inpad to register optimizes the maximum delay from input pad to clock either for a specific clock or for an entire design XST will identify all paths from either all sequential elements or the sequential elements driven by the given clock signal name to all primary output ports OFFSET OUT AFTER register to outpad optimizes the maximum delay from clock to output pad either for a specific clock or for an entire design XST will identify all paths from all pri
294. e select Full as a Value rtlview Generate RTL Schematic rtlview Generate RTL Schematic tells XST to generate a netlist file representing a Register Transfer Level RTL structure of the design This netlist can be viewed by the RTL and Technology Viewers rtlview has three possible values e yes tells XST to generate an RTL view e no tells XST not to generate the RTL view only tells XST to stop the synthesis once the RTL view is generated The file containing the RTL view has an NGR file extension You can also set this value in ISE Design Suite in Process gt Properties gt Synthesis Options gt Generate RTL Schematic rtlview Generate RTL Schematic Architecture Support Architecture independent rtlview Generate RTL Schematic Applicable Elements Applies to files rtlview Generate RTL Schematic Propagation Rules Not applicable rtlview Generate RTL Schematic Syntax rtlview yes no only The default is no rtlview Generate RTL Schematic Syntax Example rtlview yes Tells XST to generate a netlist file representing the RTL structure of the design generics Generics generics Generics allows you to redefine generics VHDL or parameters Verilog values defined in the top level design block This allows you to easily modify the design configuration without any Hardware Description Language HDL source modifications such as for IP core generation and testing flows If the defined value
295. e C begin if S tmp lt 8 b11111111 else tmp lt tmp 6 0 SI end assign SO tmp 7 endmodule 8 Bit Shift Left Register with Positive Edge Clock Serial In and Parallel Out Diagram 8 HIFT SI REG j PO 8 Bit Shift Left Register With Positive Edge Clock Serial In and Parallel Out Pin Descriptions Positive Edge Clock Parallel Output XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 59 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques 8 Bit Shift Left Register With Positive Edge Clock Serial In and Parallel Out VHDL Coding Example 8 bit Shift Left Register with Positive Edge Clock Serial In and Parallel Out library ieee use ieee std logic 1164 all entity shift registers 5 is port C SI in std logic PO out std logic vector 7 downto 0 end shift registers 5 architecture archi of shift registers 5 is signal tmp std logic vector 7 downto 0 begin process C begin if C event and C 1 then tmp lt tmp 6 downto 0 amp SI end if end process PO tmp end archi 8 Bit Shift Left Register With Positive Edge Clock Serial In and Parallel Out Verilog Coding Example 8 bit Shift Left Register with Positive Edge Clock Serial In and Parallel Out e module v_shift_registers_5 C SI PO input C SI output 7 0 PO reg 7 0 tmp always posedge C tmp lt tmp 6 0 SI assign PO t
296. e High Read Address Data Output Positive Edge Clock ROM With Registered Address VHDL Coding Example ROMs Using Block RAM Resources VHDL code for a ROM with registered address library ieee use ieee std logic 1164 a1l1 use ieee std logic unsigned all entity rams 21c is port clk in std logic en in std logic addr in std logic vector 5 downto 0 data out std logic vector 19 downto 0 end rams 210 architecture syn of rams 21c is type rom type is array 63 downto 0 of std logic vector 19 downto 0 H signal ROM rom_type X 0200A X 00300 X 08101 X 04000 X 08601 X 0233A X 00300 X 08602 X 02310 X 0203B X 08300 X 04002 X 08201 X 00500 X 04001 X 02500 X 00340 X 00241 X 04002 X 08300 X 08201 X 00500 X 08101 X 00602 X 04003 X 0241E X 00301 X 00102 X 02122 X 02021 X 00301 X 00102 X 02222 X 04001 X 00342 X 0232B X 00900 X 00302 X 00102 X 04002 X 00900 X 08201 X 02023 X 00303 X 02433 X 00301 X 04004 X 00301 X 00102 X 02137 X 02036 X 00301 X 00102 X 02237 X 04004 X 00304 X 04040 X 02500 X 02500 X 02500 X 0030D X 02341 X 08201 X 0400D signal raddr std logic vector 5 downto 0 begin process clk begin if clk event and clk 1 then if en 1 then raddr addr end if end if end process data lt ROM conv integer raddr end syn XST User Gui
297. e Packing slice packing e XOR Collapsing XOR COLLAPSE e Slice LUT FF Pairs Utilization Ratio SLICE UTILIZATION RATIO e Slice LUT FF Pairs Utilization Ratio Delta SLICE UTILIZATION RATIO MAXMARGIN e Map Entity on a Single LUT LUT MAD e Use Carry Chain USE CARRY CHAIN e Convert Tristates to Logic TRISTATE2LOGIC e Use Clock Enable USE CLOCK ENABLE e Use Synchronous Set USE SYNC SET e Use Synchronous Reset USE SYNC RESET e Use DSP48 USE DSP48 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 297 XILINX nuit t XST Design Constraints ASYNC_TO_SYNC Asynchronous to Synchronous ASYNC_TO_SYNC Asynchronous to Synchronous allows you to replace Asynchronous Set Reset signals with Synchronous signals throughout the entire design This allows absorption of registers by DSP48 and BRAMs thereby improving quality of results In addition this feature may have a positive impact on power optimization Although XST can place FSMs on BRAMs in most cases an FSM has an Asynchronous Set Reset signal which does not allow FSM implementation on BRAMs ASYNC_TO_SYNC allows you to more easily place FSMs on BRAMs by eliminating the need to manually change the design Replacing Asynchronous Set Reset signals by Synchronous signals makes the generated NGC netlist NOT equivalent to the initial RTL description You must ensure that the synthesized design satisfies the initial specification XST issues the
298. e connections are N bit wires such as e Register e Adder e Counter e Multiplexer e Glue logic e Finite State Machine FSM A Hardware Description Language HDL such as Verilog allows the expression of notations such as ASM charts and circuit diagrams in a computer language XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 403 XILINX Chapter d XST Verilog Language Support Verilog provides both behavioral and structural language structures These structures allow expressing design objects at high and low levels of abstraction Designing hardware with a language such as Verilog allows using software concepts such as parallel processing and object oriented programming Verilog has a syntax similar to C and Pascal and is supported by XST as IEEE 1364 The Verilog support in XST provides an efficient way to describe both the global circuit and each block according to the most efficient style Synthesis is then performed with the best synthesis flow for each block Synthesis in this context is the compilation of high level behavioral and structural Verilog Hardware Description Language HDL statements into a flattened gate level netlist which can then be used to custom program a programmable logic device such as a Virtex device Different synthesis methods are used for arithmetic blocks glue logic and Finite State Machine FSM components The XST User Guide assumes that you are familiar with basic Verilog co
299. e ieee std logic 1164 all entity registers 2 is port C D CLR in std logic Q out std logic end registers 2 architecture archi of registers 2 is begin process C CLR begin if CLR 1 then Q lt 0 elsif C event and C 0 then Q lt D end if end process end archi Flip Flop With Negative Edge Clock and Asynchronous Reset Verilog Coding Example Flip Flop with Negative Edge Clock and Asynchronous Reset module v registers 2 C D CLR Q input C D CLR output OQ reg 9 always 8 negedge C or posedge CLR begin if CLR Q lt 1 b0 else Q lt D end endmodule Flip Flop With Positive Edge Clock and Synchronous Set Diagram S x3722 XST User Guide 26 www xilinx com UG627 v 11 3 September 16 2009 Chipter XST Hardware Description Language HDL Coding Techniques XILINX Flip Flop With Positive Edge Clock and Synchronous Set Pin Descriptions CECR leier SSCS ES Flip Flop With Positive Edge Clock and Synchronous Set VHDL Coding Example Flip Flop with Positive Edge Clock and Synchronous Set library ieee use ieee std_logic_1164 all entity registers_3 is port C D S in std logic Q i out std logic end registers 3 architecture archi of registers 3 is begin process C begin if C event and C 1 then if S 1 then Q x 1r else Q lt D end if end if end process end archi Flip Flop With Positive Edge Clock
300. e ieee std logic unsigned all entity rams 17 is port clk in std logic we in std logic wa in std logic vector 5 downto 0 ral in std logic vector 5 downto 0 ra2 in std logic vector 5 downto 0 di in std logic vector 15 downto 0 dol out std logic vector 15 downto 0 do2 out std logic vector 15 downto 0 end rams 17 architecture syn of rams 17 is type ram type is array 63 downto 0 of std logic vector 15 downto 0 signal RAM ram type begin process clk begin if clk event and clk 1 then if we 1 then RAM conv integer wa lt di end if end if end process dol lt RAM conv integer ral do2 lt RAM conv integer ra2 end syn XST User Guide 164 www xilinx com UG627 v 11 3 September 16 2009 Chipter XST Hardware Description Language HDL Coding Techniques XILINX Multiple Port RAM Descriptions Verilog Coding Example Multiple Port RAM Descriptions module v_rams_17 clk we wa ral ra2 di dol do2 input elk input we input 5 0 wa input 5 0 ral input 5 0 ra2 input 15 0 di output 15 0 dol output 15 0 do2 reg 15 0 ram 63 0 always posedge clk begin if we ram wa lt di end assign dol ram ral assign do2 ram ra2 endmodule XST supports block RAM with reset on the data outputs as offered with Virtex 4 device Virtex 5 device and related block RAM resources Optionally you
301. e implementation uses the MUXF5 or MUXCY primitive depending on the size of the decoder Use the Decoder Extraction DECODER EXTRACT constraint to enable or disable decoder inference Shift Registers in Macro Generation XST builds two types of shift registers e Serial shift register with single output e Parallel shift register with multiple outputs The length of the shift register can vary from 1 bit to 16 bits as determined from the following formula Width 8 A3 4 A2 2 A1 A0 1 If A3 A2 Al and AO are all zeros 0000 the shift register is one bit long If they are all ones 1111 it is 16 bits long For serial shift register SRL16 flip flops are chained to the appropriate width For a parallel shift register each output provides a width of a given shift register For each width a serial shift register is built it drives one output and the input of the next shift register Use the Shift Register Extraction SHREG EXTRACT constraint to enable and disable shift register inference RAMs in Macro Generation Two types of RAM are available during inference and generation e Distributed RAM If the RAM is asynchronous READ Distributed RAM is inferred and generated e Block RAM If the RAM is synchronous READ block RAM is inferred In this case XST can implement block RAM or distributed RAM The default is block RAM Primitives Used by XST This section applies to the following devices e Virtex 4 e Sparta
302. e is enabled yes XST e Preserves all user internal signals nodes e Creates SOURCE NODE constraints in the NGC file for all these nodes e Skips design optimization collapse factorization Only boolean equation minimization is performed wysiwyg WYSIWYG Architecture Support Applies to all CPLD devices Does not apply to FPGA devices wysiwyg WYSIWYG Applicable Elements Applies to an entire design through the XST command line wysiwyg WYSIWYG Propagation Rules Not applicable wysiwyg WYSIWYG Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it wysiwyg WYSIWYG XST Command Line Syntax Example Define in the XST command line as follows xst run wysiwyg yes no The default is no wysiwyg WYSIWYG ISE Design Suite Syntax Example Define in ISE Design Suite with Process gt Properties gt Xilinx Specific Options gt WYSIWYG pld xp XOR Preserve pld xp XOR Preserve enables or disables hierarchical flattening of XOR macros The XORs inferred by Hardware Description Language HDL synthesis are also considered as macro blocks in the CPLD flow They are processed separately to give more flexibility for using device macrocells XOR gates Therefore you can decide to flatten its design Flatten Hierarchy yes Macro Preserve no but you want to preserve the XORs Preserving XOR
303. e module declaration called EXAMPLE are the basic input and output I O signals for the design The in out port in Verilog is analogous to a bi directional I O pin on the device with the data flow for output versus input being controlled by the enable signal to the tristate buffer The Behavioral Verilog Module Declaration Coding Example describes E as a tristate buffer with a high true output enable signal e Ifoe 1 the value of signal A is output on the pin represented by E e Ifoe 0 the buffer is in high impedance zZ and any input value driven on the pin E from the external logic is brought into the device and fed to the signal represented by D Behavioral Verilog Module Declaration Coding Example module EXAMPLE A B C D E input A B C output D inout E wire D E assign E p A l1 bz assign D B amp E endmodule Behavioral Verilog Continuous Assignments Continuous assignments are used to model combinatorial logic in a concise way Both explicit and implicit continuous assignments are supported Explicit continuous assignments are introduced by the assign keyword after the net has been separately declared Implicit continuous assignments combine declaration and assignment Delays and strengths given to a continuous assignment are ignored by XST Continuous assignments are allowed on wire and tri data types only Coding examples are accurate as of the date of publication Download updates from
304. e nene 222 Primitives Coding Examples seste iieri tertie lene re eee sa eret rrt baee ie Pra esie Pent raa og 222 Using the UniMaecto Library erectae eren tenere a noa nina nane net ANNEKE esee dea een 224 Kreeser Eeer 224 Cores Processing VHDL Coding sample 225 Read Cores Enabled or Disabled ssesesssesessee IR m mI e mI Henne ee ne nne se e eren r ene 225 Specifying INIT and REOG S EE 225 Passing an INIT Value Via the LUT MAP Constraint Coding Bxamples ee 226 Specifying INIT Value for a Flip Flop Coding Bxamples sse 228 Specifying INIT and RLOC Values for a Flip Flop Coding Examples sese 229 Using PCT Flow With XS RE 231 Preventing Logic and Flip Flop Replicatton cc eee 231 Disabling Read Cores uenire sidesse X sess 231 Chapter XST CPLD ODpEImuzatlon eene eere teo ote erret rE ENN E NEEN E EE AVEN EE EEE 233 CPLD Synthesis OPHOMS M 233 CPLD Synthesis Supported D eVICeS atn tte eo bo ned rernm the te esI pane pb Annee sa eb E EEA Ena 233 Setting CPLD Synthesis Options ene eene I e nenne nene ener en ener enne 234 Implementation Details for Macro Generation e e n e e e ener 234 CPLD Synthesis Log File Analysis eee tette netter tenete rtt nno ven nie re de aera Re Sepe rore nene 235 CPLD Synthesis Constraints P 237 Improving Results in CPLD Synthesis icis ase a Ee r nE I eee eH enne enne nee enne ener 237 Obtaining Bett
305. e of recognized adder subtractor and adder subtractor during the Macro Recognition step Synthesizing Unit lt adder gt Related source file is arithmetic operations l vhd Found 8 bit adder for signal sum Summary inferred 1 Adder Subtracter s Unit lt adder gt synthesized HDL Synthesis Report Macro Statistics Adders Subtractors a 8 bit adder Sr Arithmetic Operators Related Constraints e Use DSP48 USE_DSP48 e DSP Utilization Ratio DSP_UTILIZATION_RATIO e Keep KEEP Adders Subtractors and Adders Subtractors Hardware Description Language HDL Coding Techniques The following device families allow adders and subtractors to be implemented on DSP48 resources e Virtex amp 4 e Virtex 5 e Spartan 3A DSP XST supports the one level of output registers into DSP48 blocks If the Carry In or Add Sub operation selectors are registered XST pushes these registers into the DSP48 as well XST can implement an adder subtractor in a DSP48 block if its implementation requires only a single DSP48 resource If an adder subtractor macro does not fit in a single DSP48 XST implements the entire macro using slice logic Macro implementation on DSP48 blocks is controlled by DSP Utilization Ratio DSP_UTILIZATION_RATIO with a default value of auto In auto mode if an adder subtractor is a part of a more complex macro such as a filter XST automatically places it on the DSP block Otherwise XST implements adders subtractor
306. e of the total number XST User Guide 214 www xilinx com UG627 v 11 3 September 16 2009 Chapter t XST FPGA Optimization XILINX FPGA Optimization Report Section During design optimization XST reports e Potential removal of equivalent flip flops Two flip flops latches are equivalent when they have the same data and control pins e Register replication Register replication is performed either for timing performance improvement or for satisfying MAX_FANOUT constraints Register replication can be turned off using the Register Duplication REGISTER_DUPLICATION constraint Design Optimization Report Example Starting low level synthesis Optimizing unit lt down4cnt gt Optimizing unit doc readwrite Optimizing unit doc Building and optimizing final netlist The FF Latch doc readwrite state D2 in Unit doc is equivalent to the following 2 FFs Latches which will be removed doc readwrite state P2 doc readwrite state M2 5Register doc reset I reset out has been replicated 2 time s Register wr JL has been replicated 2 time s Cell Usage Report The Cell Usage section of the Final Report gives the count of all the primitives used in the design The primitives are classified in the following groups e BELS Cell Usage e Flip Flops and Latches Cell Usage e RAMS Cell Usage e SHIFTERS Cell Usage e Tristates Cell Usage e Clock Buffers Cell Usage e IO Buffers Cell Usage e
307. e process library IEEE use IEEE std logic 1164 al1 entity fsm 1 is port clk reset xL IN std logic outp OUT std logic end entity architecture behl of fsm 1 is type state type is s1 s2 s3 s4 signal state state type begin process clk reset begin if reset 1 then state s1 outp lt 1 elsif clk 1 and clk event then case state is when sl gt if x1 1 then state lt s2 outp lt 1 else state lt s3 outp lt 0 end if when s2 gt state lt s4 outp lt 0 when s3 gt state lt s4 outp lt 0 when s4 gt state lt sl outp lt 1 end case end if end process end behl XST User Guide 194 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX Finite State Machine FSM With Single Always Block Verilog Coding Example State Machine with a single always block Ve module v fsm 1 clk reset xl outp input clk reset x1 output outp reg outp reg 1 0 state parameter sl parameter s3 2 500 parameter s2 2 b10 parameter s4 2 501 2 b11 initial begin state 2 b00 end always posedge clk or posedge reset begin if reset begin state lt sl outp lt 1 b1 end else begin case state sl begin if xl 1 b1 begin state lt s2 outp lt 1 b1 end else begin state lt s3 outp lt 1 b0 end end s2 be
308. e referenced by a relative or absolute path The file need not be added to the project Be aware that conflicts can occur For example at the top of a Verilog file you might see the following timescale 1 ns 1 ps include modules vi If the specified file modules v has been added to an ISE Design Suite project directory and is specified with include conflicts may occur In that case XST issues an error message ERROR Xst 1068 fifo v line 2 Duplicate declarations of module RAMB4 S8 S8 Behavioral Verilog Comments Behavioral Verilog supports two forms of comments as shown in the following table Behavioral Verilog comments are similar to the comments used in a language such as C Behavioral Verilog Comment oe Double forward slash One line comments Define a one line comment as illustrated by this sentence Slash asterisk Multi line comments Define a multi line comment by enclosing it as illustrated by this sentence Behavioral Verilog Generate Statements A generate statement allows you to dynamically create Verilog code from conditional statements This allows you to create repetitive structures or structures that are appropriate only under certain conditions Structures likely to be created using a generate statement are Primitive or module instances Initial or always procedural blocks e Continuous assignments e Net and variable declarations e Parameter redefinitions e Task or function def
309. e same time Xilinx recommends that you use a script file Launching XST in Command Line Mode Using a Script File Store your commands in a separate script file and run them all at once To execute your script file run the following workstation or PC command xst ifn in file name ofn out file name intstyle silent ise xflow The ofn option is not mandatory If you omit it XST automatically generates a log file with the file extension srp and all messages display on the screen Use the following to limit the number of messages printed to the screen e The intstyle silent option The XIL XST HIDEMESSAGES environment variable e The message filter feature in ISE Design Suite For more information see Reducing the Size of the XST Log File For example assume that the following text is contained in a file oo scr run ifn til ee top ttl ifmt MIXED opt mode SPEED opt level 1 ofn ttl ngc p lt parttype gt XST User Guide 476 www xilinx com UG627 v 11 3 September 16 2009 Cbipttr i1 XST Command Line Mode XILINX This script file can be executed under XST using the following command xst ifn foo scr You can also generate a log file with the following command xst ifn foo scr ofn foo log A script file can be run either using xst ifn script name or executed under the XST prompt by using the script script name command script foo scr If you make a mistake in an XST command option or its
310. e watchvhd ngc An NGC file ready for the implementation tools e design srp The xst script log file To save XST messages in a different log file for example wat chver 1log run xst ifn design xst ofn watchver log To improve the readability of the design xst file especially if you use many options to run synthesis place each option with its value on a separate line Observe the following rules e The first line contains only the run command without any options e There are no blank lines in the middle of the command e Each line except the first one begins with a dash For the previous command example the design xst file should look like the following run ifn watchver prj ifmt mixed top stopwatch ofn watchver ngc ofmt NGC p xc5vfx30t 2 ff324 opt mode Speed opt level 1 Synthesizing Mixed Designs Using Command Line Mode This example shows the synthesis of a hierarchical mixed VHDL and Verilog design for a Virtex device using command line mode 1 Create a new directory named vhdl verilog 2 Copy the following files from the ISEexamples watchvhd directory of the ISE Design Suite installation directory to the newly created vhdl verilog directory e stopwatch vhd e statmach vhd e decode vhd e cnt60 vhd e smallcntr vhd e tenths vhd 3 Copy the hex21ed v file from the ISEexamples watchver directory of the ISE Design Suite installation directory to the newly created vhdl veril
311. ead Diagram Distributed RAM Single Port RAM With Asynchronous Read Pin Descriptions nn Deseription clk Positive Edge Clock od tpt Single Port RAM With Asynchronous Read VHDL Coding Example Single Port RAM with Asynchronous Read library ieee use ieee std_logic_1164 all use ieee std logic unsigned all entity rams 04 is port clk in std logic we in std logic a in std logic vector 5 downto 0 di in std logic vector 15 downto 0 do out std logic vector 15 downto 0 end rams 04 architecture syn of rams 04 is type ram type is array 63 downto 0 of std logic vector 15 downto 0 signal RAM ram type begin process clk begin if clk event and clk 1 then if we 1 then RAM conv integer a di end if end if end process do lt RAM conv integer a end syn XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 137 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Single Port RAM With Asynchronous Read Verilog Coding Example Single Port RAM with Asynchronous Read f module v rams 04 clk we a di do input elk input we input 520 az input 15 0 di output 15 0 do reg 15 0 ram 63 0 always posedge clk begin if we ram a lt di end assign do ram a endmodule The following description implements a true synchronous read A true synchronous r
312. ead is the synchronization mechanism in Virtex device block RAMs where the read address is registered on the RAM clock edge Such descriptions are directly mappable onto block RAM as shown in the diagram below The same descriptions can also be mapped onto Distributed RAM Single Port RAM With Synchronous Read Read Through Diagram WE Di Block DO A RAM CLK Single Port RAM With Synchronous Read Read Through Pin Descriptions Positive Edge Clock Synchronous Write Enable Active High Read Write Address XST User Guide 138 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX Single Port RAM With Synchronous Read Read Through VHDL Coding Example Single Port RAM with Synchronous Read Read Through library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity rams 07 is port clk in std logic we in std logic a in std logic vector 5 downto 0 di in std logic vector 15 downto 0 do out std logic vector 15 downto 0 end rams 07 architecture syn of rams 07 is type ram type is array 63 downto 0 of std logic vector 15 downto 0 signal RAM ram type signal read a std logic vector 5 downto 0 begin process clk begin if clk event and clk 1 then if we 1 then RAM conv integer a di end if read a lt a end if end process do lt RAM
313. ead to sub optimal performance The Asynchronous to Synchronous ASYNC TO SYNC constraint allows you to replace Asynchronous Set Reset signals with Synchronous signals throughout the entire design This allows absorption of registers by DSP48 thereby improving quality of results XST User Guide 208 www xilinx com UG627 v 11 3 September 16 2009 Chapter XST FPGA Optimization XILINX Replacing Asynchronous Set Reset signals by Synchronous signals makes the generated NGC netlist NOT equivalent to the initial RTL description You must ensure that the synthesized design satisfies the initial specification For more information see Asynchronous to Synchronous ASYNC_TO_SYNC For more information on individual macro processing see XST Hardware Description Language HDL Coding Techniques If your design contains several interconnected macros where each macro can be implemented on DSP48 XST attempts to interconnect DSP48 blocks using fast BCIN BCOUT and PCIN PCOUT connections Such situations are typical in filter and complex multiplier descriptions XST can build complex DSP macros and DSP48 chains across the hierarchy when the Keep Hierarchy KEEP_HIERARCHY command line option is set to no This is the default in ISE Design Suite Mapping Logic Onto Block RAM If your design does not fit into the target device you can place some of the design logic into unused block RAM 1 Put the part of the RTL description to be placed in
314. ecoder_extract string Specify as follows attribute decoder_extract of entity_name signal_name entity signal is yes no Decoder Extraction DECODER_EXTRACT Verilog Syntax Example Place Decoder Extraction immediately before the module or signal declaration decoder extract yes no Decoder Extraction DECODER EXTRACT XST Constraint File XCF Syntax Example One MODEL entity name decoder extract yes no true false Decoder Extraction DECODER EXTRACT XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name NET signal name decoder extract yes no true false END Decoder Extraction DECODER EXTRACT XST Command Line Syntax ISE Design Suite Example Define in the XST command line as follows xst run decoder extract yes no The default is yes Decoder Extraction DECODER EXTRACT ISE Design Suite Syntax Example Define in ISE Design Suite with Process Properties HDL Options Decoder Extraction Decoder Extraction values are e yes default e no check box in not checked DSP UTILIZATION RATIO DSP Utilization Ratio DSP UTILIZATION RATIO DSP Utilization Ratio defines the number of DSP slices in absolute number or percent of slices that XST must not exceed during synthesis optimization The default is 10076 of the target device XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 303 XILINX nuit t XST Design Constraints
315. ectory xsthdpdir e HDL Library Mapping File xsthdpini e Verilog Include Directories vlgincdir e Slice LUT FF Pairs Utilization Ratio SLICE_UTILIZATION_RATIO Setting Hardware Description Language HDL Options You can set Hardware Description Language HDL options for FPGA devices and CPLD devices Setting Hardware Description Language HDL Options for FPGA Devices To set Hardware Description Language HDL options for FPGA devices in ISE Design Suite select Process gt Properties gt Synthesize XST gt HDL Options The following HDL Options can be set for FPGA devices e FSM Encoding Algorithm FSM_ENCODING e Safe Implementation SAFE IMPLEMENTATION e Case Implementation Style vlgcase e FSM Style F5M STYLE To view FSM Style select Edit Preferences Processes Property Display Level Advanced e RAM Extraction RAM EXTRACT e RAM Style RAM STYLE e ROM Extraction ROM EXTRACT e ROM Style ROM STYLE e Mux Extraction MUX EXTRACT e Mux Style MUX STYLE e Decoder Extraction DECODER_EXTRACT e Priority Encoder Extraction PRIORITY EXTRACT e Shift Register Extraction SHREG EXTRACT e Logical Shifter Extraction SHIFT EXTRACT e XOR Collapsing XOR COLLAPSE e Resource Sharing RESOURCE SHARING e Multiplier Style MULT STYLE For later devices Multiplier Style is renamed as follows Use DSP48 Virtex 4 devices Use DSP Block Virtex 5 devices and Spartan 3A DSP devices e Use D
316. ed Constraints eee eee E ERE ee eene e e ene eH e enne nee ener rennen 23 Registers Coding Examples iiti eene sess end eer ePi e EES e ERR ee EEAS 23 Latches Hardware Description Language HDL Coding Techntogues 30 Latches Log Files EE 30 Latches Related Constraints sse eee e ene eene e enne nennen eren nne 30 Latches Coding Examples 5 ee ER eo Yece tiere E e Ere HERE EX RR ER Yr URS EE PUES Ux ENS ere ERES 30 Latch With Positive Gate VHDL Coding Example sss 31 Tristates Hardware Description Language HDL Coding Techniques sss 33 jorcgReds cmt 34 Tristates Related Constraints 34 Tristates Coding Examples i e eret saves eei eb esee ree es ee AREE E E SEEEN 34 Counters Hardware Description Language HDL Coding Techniques ss nsssssssssttstrsrserrtestrssrerrrensseet 36 ieuaciEdu WE 37 Counters Related Constraints eicere hia een o d thee eo E Ee HEP RES QE EE EROR EE dE eoa E ERE FERE oA 37 Counters Coding Examples sisstin 37 Accumulators Hardware Description Language HDL Coding Techniques ccccceceessseeeeeeeeeneeeeees 48 Accumulators in Virtex 4 Devices and Virtex 5 Devices ssssssseeee eH 48 Accumulators Log File 455i sse teet rentrer ee EUER Hr IR EE CEREREM dee LE c rupe oe ERREUR deeg 49 Accumulators Related Constraimts eene e een HH enne enne 49 Accumulators Coding Examples esit ttr toten terree sq ES Ens
317. ed in XST Compiler Directive celldefine endcelldefine default nettype define ifdef else endif undef ifndef elsif include resetall timescale unconnected drive nounconnected drive uselib file line Supported Unsupported Supported Verilog System Tasks and Functions Supported in XST System Task or Function display fclose fdisplay fgets finish fopen fscanf fwrite monitor random readmemb readmemh signed stop strobe time unsigned write all others XST User Guide UG627 v 11 3 September 16 2009 Supported Escape sequences are limited to d b Yh o Yor and s Supported Supported Supported Supported finish is supported for statically never active conditional branches only Supported Supported Escape sequences are limited to b and Zod Supported Escape sequences are limited to d ob Yh 0 Yc and 76s Dez REN RN www xilinx com 413 XILINX Chapter t XST Verilog Language Support The XST Verilog compiler ignores unsupported system tasks The signed and unsigned system tasks can be called on any expression using the following syntax signed expr or unsigned expr The return value from these calls is the same size as the input value Its sign is forced regardless of any previous sign The readmemb and readmemh system tasks can be used to initialize block memories For
318. ed multiplier implementation Loadable Functions in Macro Generation For Loadable functions XST provides the following elements e Loadable Up Down and Up Down Binary Counters e Loadable Up Down and Up Down Accumulators XST can provide synchronously loadable cascadable binary counters and accumulators inferred in the HDL flow Fast carry logic is used to cascade the different stages of the macros Synchronous loading and count functions are packed in the same LUT primitive for optimal implementation For Up Down counters and accumulators XST uses dedicated carry ANDs to improve performance Multiplexers in Macro Generation For multiplexers the Macro Generator provides the following two architectures e MUXFx based multiplexers e Dedicated Carry MUXs based multiplexers For Virtex 4 devices XST can implement a 16 1 multiplexer in a single CLB using a MUXF7 primitive and it can implement a 32 1 multiplexer across two CLBs using a MUXF8 To have better control of the implementation of the inferred multiplexer XST offers a way to select the generation of either the MUXF5 MUXF6 or Dedicated Carry MUxXs architectures The attribute MUX_STYLE specifies that an inferred multiplexer be implemented on a MUXFx based architecture if the value is MUXF or a Dedicated Carry MUxXs based architecture if the value is MUXCY You can apply this attribute to either a signal that defines the multiplexer or the instance name of the multiplexer Th
319. ed on a component in XST it is possible that your simulation tool may nevertheless use the generic This may cause the simulation results to not match the synthesis results Use the following as a guide in determining precedence in VHDL Precedence in VHDL E Generic on an Instance Generic on a Component Attribute on an Instance Apply Generic XST issues warning Apply Attribute possible simulation mismatch Attribute on a Component Apply Generic Apply Generic XST issues warning Attribute in XCF Apply Attribute XST issues warning Apply Attribute Security attributes on the block definition always have higher precedence than any other attribute or generic VHDL Combinatorial Circuits XST supports the following VHDL combinatorial circuits e Concurrent Signal Assignments e Generate Statements e Combinatorial Processes e f Else Statements e Case Statements For Loop Statements VHDL Concurrent Signal Assignments Combinatorial logic in VHDL may be described using concurrent signal assignments These can be defined within the body of the architecture VHDL offers three types of concurrent signal assignments e Simple e Selected e Conditional You can describe as many concurrent statements as needed The order of concurrent signal definition in the architecture is irrelevant A concurrent assignment consists of two sides e Lett hand e Right hand The assignment changes when any signal in the right side changes
320. eee std logic 1164 all use ieee std logic unsigned all entity adders 2 is port A B in std logic vector 7 downto 0 CI in std logic SUM out std logic vector 7 downto 0 end adders 2 architecture archi of adders 2 is begin SUM lt A B CI end archi Unsigned 8 Bit Adder With Carry In Verilog Coding Example Unsigned 8 bit Adder with Carry In module v_adders_2 A B CI SUM input 7 0 A input 7 0 B input CI output 7 0 SUM assign SUM A B CI endmodule Unsigned 8 Bit Adder With Carry Out Before writing a plus operation with carry out in VHDL read the arithmetic package you plan to use For example std_logic_unsigned does not allow you to write plus in the following form to obtain Carry Out Res 9 bit A 8 bit B 8 bit The reason is that the size of the result for plus in this package is equal to the size of the longest argument 8 bits One solution for the example is to adjust the size of operands A and B to 9 bits using concatenation Res lt 0 amp A O amp B In this case XST recognizes that this 9 bit adder can be implemented as an 8 bit adder with carry out Another solution is e Convert A and B to integers e Convert the result back to the std_logic vector e Specify the size of the vector equal to 9 XST User Guide 90 www xilinx com UG627 v 11 3 September 16 2009 Chipter XST Hardware Description Language HDL Coding Techni
321. egin A_regl lt A A_reg2 lt A_regl B_regl lt B B_reg2 lt B_regl end assign mult A_reg2 B_reg2 assign multaddsub add sub C mult C mult assign RES multaddsub endmodule Multiply Accumulate Hardware Description Language HDL Coding Techniques The Multiply Accumulate macro is a complex macro consisting of several basic macros such as e Multipliers e Accumulators e Registers The recognition of this complex macro enables XST to implement it on dedicated DSP48 resources in the following devices e Virtex8 4 e Virtex 5 Multiply Accumulate in Virtex 4 Devices and Virtex 5 Devices The Multiply Accumulate macro is a complex macro consisting of several basic macros as multipliers accumulators and registers The recognition of this complex macro enables XST to implement it on dedicated DSP48 resources in Virtex 4 devices and Virtex 5 devices XST supports the registered version of this macro and can push up to 2 levels of input registers into the DSP48 block If Adder Subtractor operation selectors are registered XST pushes these registers into the DSP48 In addition the multiplication operation could be registered as well XST can implement a multiply accumulate in a DSP48 block if its implementation requires only a single DSP48 resource If the macro exceeds the limits of a single DSP48 XST processes it as two separate Multiplier and Accumulate macros making independent decisions on each macro
322. egister at global reset or at power up A value assigned this way is carried in the NGC file as an INIT attribute on the register and is independent of any local reset reg arb onebit 1 b0 reg 3 0 arb priority 4 b1011 You can also assign a set reset initial value to a register in your behavioral Verilog code Assign value to a register when the register reset line goes to the appropriate value as shown in the following coding example always posedge clk begin if rst arb_onebit lt 1 b0 end end When you set the initial value of a variable in the behavioral code it is implemented in the design as a flip flop whose output can be controlled by a local reset As such it is carried in the NGC file as an FDP or FDC flip flop Behavioral Verilog Local Reset Local reset is independent of global reset Registers controlled by a local reset may be set to a different value than ones whose value is only reset at global reset power up In the Behavioral Verilog Local Reset Coding Example the register arb_onebit is set to 0 at global reset but a pulse on the local reset rst can change its value to 1 Behavioral Verilog Local Reset Coding Example module mult clk rst A_IN B_OUT input clk rst A_IN output B_OUT reg arb_onebit 1 b0 always posedge clk or posedge rst begin LE rst arb onebit lt 1 b1 else arb onebit lt A IN end end B OUT arb onebit endmodule XST User Guide 41
323. egister duplication yes no true false REGISTER DUPLICATION Register Duplication XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name NET signal name register duplication yes no true false END REGISTER DUPLICATION Register Duplication ISE Design Suite Syntax Example Define in ISE Design Suite with Process Properties Xilinx Specific Options Register Duplication XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 329 XILINX nuit t XST Design Constraints ROM_EXTRACT ROM Extraction ROM_EXTRACT ROM Extraction enables or disables ROM macro inference ROM_EXTRACT values are e yes default no e true XCF only e false XCF only The default is yes Typically a ROM can be inferred from a case statement where all assigned contexts are constant values ROM EXTRACT ROM Extraction Architecture Support Applies to all FPGA devices Does not apply to CPLD devices ROM EXTRACT ROM Extraction Applicable Elements Applies to the entire design or to a design element or signal ROM EXTRACT ROM Extraction Propagation Rules Applies to the entity component module or signal to which it is attached ROM EXTRACT ROM Extraction Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it ROM EXTRACT ROM Extraction VHDL Syntax
324. el e Be left or right e Have a synchronous or asynchronous reset e Have a depth up to 16 bits 16 Bit Dynamic Shift Register With Positive Edge Clock Serial In and Serial Out Pin Descriptions XST User Guide 66 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX 16 Bit Dynamic Shift Register With Positive Edge Clock Serial In and Serial Out VHDL Coding Example 16 bit dynamic shift register library IEEE use IEEE std logic 1164 al1 use IEEE std logic unsigned all entity dynamic shift registers 1l is port CLK in std logic DATA in std logic CE in std logic A in std logic vector 3 downto 0 Q out std logic end dynamic shift registers 1 architecture rtl of dynamic shift registers 1 is constant DEPTH WIDTH integer 16 type SRL ARRAY is array 0 to DEPTH WIDTH 1 of std logic The type SRL ARRAY can be array 0 to DEPTH WIDTH 1 of std logic vector BUS WIDTH downto 0 or array DEPTH WIDTH 1 downto 0 of std logic vector BUS WIDTH downto 0 the subtype is forward see below signal SRL SIG SRL ARRAY begin PROC SRL16 process CLK begin if CLK event and CLK 1 then if CE 1 then SRL SIG lt DATA amp SRL SIG 0 to DEPTH WIDTH 2 end if end if end process Q SRL SIG conv integer A end rtl 16 Bit Dynamic Shift Register With Positive Edge
325. en if we 1 then RAM conv integer addr lt di end if do lt RAM conv integer addr end if end if end process end syn XST User Guide 130 www xilinx com UG627 v 11 3 September 16 2009 lhapter 3 XST Hardware Description Language HDL Coding Techniques XILINX Single Port RAM in Read First Mode Verilog Coding Example One Read First Mode module v rams 01 clk en we addr di do input clk input we input en input 5 0 addr input 15 0 di output 15 0 do reg 15 0 RAM 63 0 reg 15 0 do always posedge clk begin if en begin if we RAM addr lt di do lt RAM addr end end endmodule Single Port RAM in Write First Mode Diagram WE EN DO DI Lech CE ADDR S CLK a x10564 Single Port RAM in Write First Mode Pin Descriptions Description Positive Edge Clock we Synchronous Write Enable Active High en Clock Enable addr Read Write Address C E XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 131 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Single Port RAM in Write First Mode VHDL Coding Example One Write First Mode template 1 library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity rams 02a is port clk in std logic we in std logic en in std logic addr in std logic vector 5 downto 0 di in std logic vecto
326. en EE eee eo E One e ERR ESNE REEE 49 Shift Registers Hardware Description Language HDL Coding Techntoues 51 Describing Shift Registers M V 51 Implementing Shift Registers dicireni nn n et tines eee Rea EE SEENEN ee 51 SREI E D e m n X 51 Shift Registers Log Files in hesitate ENEE RUE late a tit Gere Ce eur P Ee VEREOR EL RYE 53 Shift Registers Related Constraints iet eee edo pea SEEI de ERENS de ean nee E Re ea RR e NENNEN 53 Shift Registers Coding Exam ples cetera tite oae thee Peces tb inre nnne aE Eh boue giten ces Pies oves epis iste sheets 53 Dynamic Shift Registers Hardware Description Language HDL Coding Techniques 65 Dynamic Shift Registers Log File essit eere eterne rie eorr en eni be shear e ea Yours revue aso een 65 Dynamic Shift Registers Related Constant 66 Dynamic Shift Registers Coding Examples eee 66 Multiplexers Hardware Description Language HDL Coding Techniques ssssseessssrsersttssrssrerrt estese 68 Multiplexers Verilog Case Implementation Style Parameter 69 Multiplexers Verilog Case Statement Resourceg eee 69 Mult plexers Log File i ere tete eor Pe PIER e ERE HEIC D reb ERREUR GI E LE VERDE TI CARERE Cea a E 70 Multiplexers Related Constraints ue eene ee erre tette neenon enacted cosessvetenssessedenssunesssoesons 70 Multiplexers Coding Examples ite I be eee ter ient ere EES NEESS 70 Decoders Hardware
327. en s3 gt state lt s4 when s4 gt state lt sl end case end if end process processl process2 process state begin case state is when sl gt outp lt 1 when s2 gt outp lt 1 when s3 gt outp lt 0 when s4 gt outp lt 0 end case end process process2 end behl XST User Guide 196 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX Finite State Machine FSM With Two Always Blocks Verilog Coding Example State Machine with two always blocks module v_fsm_2 clk reset xl outp input clk reset xl output outp reg outp reg 1 0 state parameter sl 2 b00 parameter s2 2 b01 parameter s3 2 b10 parameter s4 2 b11 initial begin state 2 Db00 end always posedge clk or posedge reset begin if reset state lt sl else begin case state sl if xl 1 b1 state s2 else state lt s3 S2 state lt s4 S3 state lt s4 s4 state lt sl endcase end end always state begin case state sl outp 1 b1 S2 outp 1 bl S3 outp 1 b0 s4 outp 1 b0 endcase end endmodule You can also separate the NEXT State function from the state register Finite State Machine FSM With Three Processes Diagram E Next State State Output R Outputs Register Function Inputs ie Function Only for Meal
328. ential circuits can be described in VHDL with multiple Wait statements in a process Follow these rules when using multiple Wait statements e The process contains only one Loop statement The first statement in the loop is a Wait statement e After each Wait statement a Next or Exit statement is defined The condition in the Wait statements is the same for each Wait statement e This condition use only one signal the clock signal e This condition has the following form wait on clock signal until clock signal EVENT not clock signal STABLE and clock signal 0 1 j Sequential Circuit Using Multiple Wait Statements VHDL Coding Example The following VHDL coding example uses multiple Wait statements This example describes a sequential circuit performing four different operations in sequence The design cycle is delimited by two successive rising edges of the clock signal A synchronous reset is defined providing a way to restart the sequence of operations at the beginning The sequence of operations consists of assigning each of the following four inputs to the output RESULT e DATA1 e DATA2 e DATA e DATA4 library IEEE use IEEE STD_LOGIC_1164 all entity EXAMPLE is port DATA1 DATA2 DATA3 DATA4 in STD LOGIC VECTOR 3 downto 0 RESULT out STD LOGIC VECTOR 3 downto 0 CLK in STD LOGIC RST in STD LOGIC end EXAMPLE architecture ARCH of EXAMPLE is begin process begin SEQ LOOP l
329. ents are specified within component instantiation statements These statements specify an instance of a component occurring within another component or the circuit Each component instantiation statement is labeled with an identifier XST User Guide 404 www xilinx com UG627 v 11 3 September 16 2009 Chipter t XST Verilog Language Support XILINX Besides naming a component declared in a local component declaration a component instantiation statement contains an association list the parenthesized list that specifies which actual signals or ports are associated with which local ports of the component declaration Verilog provides a large set of built in logic gates which can be instantiated to build larger logic circuits The set of logical functions described by the built in gates includes AND e OR e XOR s NAND s NOR NOT Building a Basic XOR Function Structural Verilog Coding Example Following is an example of building a basic XOR function of two single bit inputs a and b module build xor a b c input a b output c wire c a not b not not a inv a not a not b inv b not b and al x a not b and a2 y b not a or out c X y endmodule Each instance of the built in modules has a unique instantiation name such as e a inv e b inv out Structural Description of a Half Adder Structural Verilog Coding Example The following coding example shows the structural description of a h
330. eports the type and size of recognized multipliers during the Macro Recognition step Synthesizing Unit lt mult gt Related source file is multipliers l vhd Found 8x4 bit multiplier for signal res Summary inferred 1 Multiplier s Unit lt mult gt synthesized HDL Synthesis Report Macro Statistics Multipliers ST 8x4 bit multiplier Se E Multipliers Related Constraints e Multiplier Style MULT STYLE e Use DSP48 USE DSPA8 e DSP Utilization Ratio DSP UTILIZATION RATIO e Keep KEEP Multipliers Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip Unsigned 8x4 Bit Multiplier Diagram XST User Guide 100 www xilinx com UG627 v 11 3 September 16 2009 hapter 1 XST Hardware Description Language HDL Coding Techniques XILINX Unsigned 8x4 Bit Multiplier Pin Descriptions Hoping Description S Unsigned 8x4 Bit Multiplier VHDL Coding Example Unsigned 8x4 bit Multiplier library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity multipliers 1 is port A in std logic vector 7 downto 0 B in std logic vector 3 downto 0 RES out std logic vector 11 downto 0 end multipliers 1 architecture beh of multipliers 1 is begin RES lt A B end beh Unsigned 8x4 Bit Multiplier Verilog Coding Example Unsigned 8x4 bit Multiplier module v_
331. er Frequency 2 eerte ettet e HI Lk e ENEN ERN NS SNR E IU SEENEN REEERERR 237 Fitting a Large Desle nassssasssasngindens cncstiensce En EA EE ENE NE NEE geess Ans 239 Chapter 6 XST Design Constraints 3ii 2ccssc ccnceenss ccvesessi cass sass cena NEE NEE REFERRE EEEE E KE SEATO erue cede seas 241 List of XST Design Constraints coercet sone cease pee i ta aoa ee Ee RS toa SENSE ERR See e eeu sete aos gena sane cel 242 XST General Constraints ie ter varese eger ase named oan eeh E Febr wee sa UE Pa Ee Cava Ter PERDE e re PE 243 XST Hardware Description Language HDL Constraints sssssseeee eH 244 XST FPGA Constraints None l iming eeng coc doses dede tkt eus ee po ES ha ando eege Eege d annee e ber nu Ea Fade a ead qa 244 XST CPLD Constraints Non Timing 245 XST Timing EE EE 245 XST User Guide 6 www xilinx com UG627 v 11 3 September 16 2009 XILINX XST Implementation EE EE 246 Third Party Constraints doeet tree Re Sues satsiscossssGescgposieeccspnsdguce EEN 246 Setting Global Constraints and COpttons cece etree eee er nner rene nnn nn ene e n e n e e nnns 246 Settings Synthesis OPHONS E 246 Setting Hardware Description Language HDL Options ssssssee 247 Setting Hardware Description Language HDL Options for FPGA Devices eese 247 Setting Hardware Description Language HDL Options for CPLD Devices sees 248 Setting Xilinx Specific OPUONS M
332. er Inputs VHDL Coding Example Multiplier Adder Subtractor with 2 Register Levels on Multiplier Inputs library IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD LOGIC UNSIGNED ALL entity multipliers 6 is generic p width integer 8 port clk add sub in std logic A B C in std logic vector p width 1 downto 0 RES out std logic vector p width 2 1 downto 0 end multipliers 6 architecture beh of multipliers 6 is signal A regl A reg2 B regl B reg2 std logic vector p width 1 downto 0 Signal mult multaddsub std logic vector p width 2 1 downto 0 begin mult lt A reg2 B reg2 multaddsub lt C mult when add sub 1 else C mult process clk begin if clk event and clk 1 then A regl lt A A reg2 lt A regl B regl lt B B reg2 lt B regl end if end process RES lt multaddsub end beh XST User Guide 116 www xilinx com UG627 v 11 3 September 16 2009 lhapter 3 XST Hardware Description Language HDL Coding Techniques XILINX Multiplier Adder Subtractor With 2 Register Levels On Multiplier Inputs Verilog Coding Example Multiplier Adder Subtractor with 2 Register Levels on Multiplier Inputs module v_multipliers_6 clk add_sub A B C RES input clk add sub input 7 0 A input 7 0 B input 7 0 output 15 0 RES reg 7 0 A regl A reg2 B regl B reg2 wire 15 0 mult multaddsub always posedge clk b
333. erilog work stopwatch v verilog work cnt60 v verilog work smallcntr v verilog work hex2led v 3 To synthesize the design execute the following command from the XST shell or a script file run ifn watchver v ifmt mixed top stopwatch ofn watchver ngc ofmt NGC p xc5bvfx30t 2 ff324 opt mode Speed opt level 1 To synthesize just HEX2LED and check its performance independently of the other blocks specify the top level module to synthesize in the command line using the top option For more information see XST Specific Non Timing Options run ifn watchver v ifmt Verilog ofn watchver ngc ofmt NGC p xc5vfx30t 2 ff324 opt mode Speed opt level 1 top HEX2LED XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 483 XILINX Ctapter 13 XST Command Line Mode Running XST in Script Mode Verilog It can be tedious to enter XST commands directly into the XST shell especially when you have to specify several options and execute the same command several times To run XST in script mode 1 Open a new file called design xst in the current directory Put the previously executed XST shell command into this file and save it run ifn watchver prj ifmt mixed ofn watchver ngc ofmt NGC p xc5vfx30t 2 ff324 opt mode Speed opt level 1 2 From the tesh or other shell enter the following command to begin synthesis xst ifn design xst During this run XST creates the following files
334. erilog2001 Verilog 2001 enables or disables interpreted Verilog source code as the Verilog 2001 standard By default Verilog source code is interpreted as the Verilog 2001 standard You can also set this value in ISE Design Suite with Process gt Properties gt Synthesis Options gt Verilog 2001 verilog2001 Verilog 2001 Architecture Support Architecture independent verilog2001 Verilog 2001 Applicable Elements Applies to syntax verilog2001 Verilog 2001 Propagation Rules Not applicable verilog2001 Verilog 2001 Syntax xst run verilog2001 yes no The default is yes XST User Guide 282 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST Design Constraints XILINX verilog2001 Verilog 2001 Syntax Example xst elaborate verilog2001 no XST will not interpret Verilog code according to the Verilog 2001 standard xsthdpini HDL Library Mapping File Use xsthdpini HDL Library Mapping File to define the library mapping XST maintains two library mapping files e The pre installed file which is installed during the Xilinx software installation e The user file which you may define for your own projects The pre installed default INI file is named xhdp ini and is located in SXILINX vhd1 xst This file contains information about the locations of the standard VHDL and UNISIM libraries This file should not be modified but you can copy the syntax for your own library mapping file To s
335. es The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it FSM_ENCODING FSM Encoding Algorithm Algorithm VHDL Syntax Example Declare as follows attribute fsm encoding string Specify as follows attribute fsm_encoding of entity_name signal_name entity signal is auto one hot compact sequential gray johnson speedl user The default is auto FSM ENCODING FSM Encoding Algorithm Verilog Syntax Example Place FSM Encoding Algorithm immediately before the module or signal declaration Place immediately before the module or signal declaration fsm encoding auto one hot compact sequential gray johnson speedl user The default is auto FSM_ENCODING FSM Encoding Algorithm XST Constraint File XCF Syntax Example One MODEL entity name fsm_encoding auto one hot compact sequential gray johnson speedl user XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 289 XILINX nuit t XST Design Constraints FSM_ENCODING FSM Encoding Algorithm XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name NET signal name fsm_encoding auto one hot compact sequential gray johnson speedl user END FSM ENCODING FSM Encoding Algorithm XST Command Line Syntax Example Define in the XST command line as follows fsm enc
336. es Applies to the signal to which it is attached SAFE RECOVERY STATE Safe Recovery State Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it SAFE RECOVERY STATE Safe Recovery State VHDL Syntax Example Declare as follows attribute safe recovery state string Specify as follows attribute safe recovery state of signal name signal is lt value gt SAFE RECOVERY STATE Safe Recovery State Verilog Syntax Example Place immediately before the signal declaration safe recovery state value SAFE RECOVERY STATE Safe Recovery State XST Constraint File XCF Syntax Example BEGIN MODEL entity name NET signal name safe recovery state value END SAFE IMPLEMENTATION Safe Implementation SAFE IMPLEMENTATION Safe Implementation implements Finite State Machine FSM components in Safe Implementation mode In Safe Implementation mode XST generates additional logic that forces an FSM to a valid state recovery state if the FSM enters an invalid state By default XST automatically selects reset as the recovery state If the FSM does not have an initialization signal XST selects power up as the recovery state Define the recovery state manually with Safe Recovery State SAFE RECOVERY STATE To activate SAFE IMPLEMENTATION in ISE Design Suite Select Process Properties
337. ese examples Dual port block RAMs can be configured with a different read write mode on each port Inference supports this capability Support For Read Write Modes summarizes support for read write modes according to the targeted devices and how XST handles it Support For Read Write Modes Spartan 3 write first Macro inference and generation Spartan 3E read first Attach adequate WRITE_MODE WRITE_MODE_A WRITE_MODE_B Spartan 3A no change constraints to generated block RAMs Virtex 4 in NCF Virtex 5 CPLD TEETE Single Port RAM in Read First Mode Diagram EN D ADDR CLK X10563 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 129 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Single Port RAM in Read First Mode Pin Descriptions Iesse ES jemkEwe 0000000 mmm mou Single Port RAM in Read First Mode VHDL Coding Example One Read First Mode library ieee use ieee std logic 1164 al1 use ieee std logic unsigned all entity rams 01 is port clk in std logic we t Xn Stdlogic en in std logic addr in std logic vector 5 downto 0 di in std logic vector 15 downto 0 do out std logic vector 15 downto 0 end rams 01 architecture syn of rams 01 is type ram type is array 63 downto 0 of std logic vector 15 downto 0 signal RAM ram type begin process clk begin if clk event and clk 1 then if en 1 th
338. esses eese enne thee teretes eee i 311 MAX FANOUT Max Fanout Architecture Gupport eee rere ererererer reins 312 MAX FANOUT Max Fanout Applicable Elements sssss ee eerenerererererees 312 MAX FANOUT Max Fanout Propagation Rules He 312 MOVE FIRST STAGE Move First Stage ccccccssccscssssscssccescssscecscsseeesscssececsessensssusssnsenesssersneeennea 313 MOVE FIRST STAGE Move First Stage Architecture Support sssssseeeeeee 314 MOVE FIRST STAGE Move First Stage Applicable Elements sse 314 MOVE FIRST STAGE Move First Stage Propagation Rules sss 314 MOVE LAST STAGE Move Last Stage eee tenter oae enne one eene shoe unun ne ENEE NEEN 314 MOVE LAST STAGE Move Last Stage Architecture Support sssssssssssseeeee 315 MOVE LAST STAGE Move Last Stage Applicable Elements 315 MOVE LAST STAGE Move Last Stage Propagation Rules sse 315 MULT STYLE Ee EE 315 MULT STYLE Multiplier Style Architecture Support 316 MULT STYLE Multiplier Style Applicable Elements sss 316 MULT STYLE Multiplier Style Propagation Rules sss 316 MUX STXEE Mux Style EE 317 MUX STYLE Mux Style Architecture Dupport ee 317 MUX STYLE Mux Style Applicable Elements 317 MUX STYLE Mux Style Propagation Rule 317 bufg Number of Global Clock Butffers eerte brennen eet honeste genes EES EEN 318 bufr Number of Regional Clock Buttere eene 319
339. et the library mapping file location in ISE Design Suite 1 InISE Design Suite select Process Properties Synthesis Options 2 From the Property display level list select Advanced 3 Set the HDL INI File property A library mapping file looks like the following Default lib mapping for XST std XILINX vhdl xst std ieee S XILINX vhdl xst unisim unisim XILINX vhdl xst unisim aim XILINX vhdl xst aim pls XILINX vhdl xst pls Use this file format to define where each of your own libraries must be placed By default all compiled VHDL flies are stored in the xst sub directory of the ISE Design Suite project directory The library mapping file contains a list of libraries one per line with the following information The library name e The directory in which the library is compiled You can give this library mapping file any name you wish but it is best to keep the ini classification The format for each line is library name path to compiled directory Use double dash to start a comment line xsthdpini HDL Library Mapping File Architecture Support Architecture independent xsthdpini HDL Library Mapping File Applicable Elements Applies to files xsthdpini HDL Library Mapping File Propagation Rules Not applicable xsthdpini HDL Library Mapping File Syntax xsthdpini file name You can specify only one library mapping file XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 2
340. f XST synthesis constraints see XST Specific Non Timing Options Native and Non Native User Constraint File UCF Constraints Syntax All constraints supported by XST can be divided into two groups e Native User Constraints File UCF Constraints e Non Native User Constraints File UCF Constraints Native User Constraints File UCF Constraints Only Timing and Area Group constraints use native User Constraints File UCF syntax Use native UCF syntax including wildcards and hierarchical names for native UCF constraints such as e Period PERIOD e Offset OFFSET e Timing Name on a Net TNM NET e Timegroup TIMEGRP e Timing Ignore TIG e From To FROM TO Do not use these constraints inside the BEGIN MODEL END construct If you do XST issues an error Non Native User Constraints File UCF Constraints For all non native User Constraints File UCF constraints use the MODEL or BEGIN MODEL END constructs This includes e Pure XST constraints such as Automatic FSM Extraction F5M EXTRACT RAM Style RAM STYLE e Implementation non timing constraints such as RLOC Keep KEEP If you specify timing constraints in the XST Constraint File XCF Xilinx recommends that you use a forward slash as a hierarchy separator instead of an underscore For more information see Hierarchy Separator hierarchy separator XST User Guide 252 www xilinx com UG627 v 11 3 September 16 2009 tapt
341. f multipliers 5 is signal A regl A reg2 B real B reg2 std logic vector p width 1 downto 0 signal multaddsub std logic vector p width 2 1 downto 0 begin multaddsub lt A reg2 B reg2 C process clk begin if clk event and clk 1 then A regl lt A A reg2 lt A regl B regl lt B B reg2 lt B regl end if end process RES lt multaddsub end beh Multiplier Adder With 2 Register Levels on Multiplier Inputs Verilog Coding Example Multiplier Adder with 2 Register Levels on Multiplier Inputs module v_multipliers_5 clk A B C RES input clk input 7 0 A input 7 0 B input T20 C output 15 0 RES reg 7 0 A regl A reg2 B regl B reg2 wire 15 0 multaddsub always posedge clk begin A_regl lt A A reg2 lt A regl B regl B B reg2 B regl end assign multaddsub A reg2 B reg2 C assign RES multaddsub endmodule XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 115 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Multiplier Adder Subtractor With 2 Register Levels On Multiplier Inputs Diagram 8 LH Te ll ADD SUB CLK Multiplier Adder Subtractor With 2 Register Levels On Multiplier Inputs Pin Descriptions Positive Edge Clock AddSub Selector MULT AddSub Operands MULT AddSub Result Multiplier Adder Subtractor With 2 Register Levels On Multipli
342. ferred register and propagated to the final netlist 228 XST User Guide www xilinx com UG627 v 11 3 September 16 2009 Chapter t XST FPGA Optimization XILINX Specifying INIT Value for a Flip Flop VHDL Coding Example Specification on an INIT value for a flip flop described at RTL level library ieee use ieee std logic 1164 all entity inits rlocs 2 is port CLK in std logic DI in std logic vector 3 downto 0 DO out std logic vector 3 downto 0 end inits rlocs 2 architecture beh of inits rlocs 2 is signal tmp std logic vector 3 downto 0 1011 begin process CLK begin if clk event and clk 1 then tmp DI end if end process DO tmp end beh Specifying INIT Value for a Flip Flop Verilog Coding Example Specification on an INIT value for a flip flop described at RTL level module v_inits_rlocs_2 clk di do input clk input 3 0 di output 3 0 do reg 3 0 tmp initial begin tmp 4 b1011 end always posedge clk begin tmp lt di end assign do tmp endmodule Specifying INIT and RLOC Values for a Flip Flop Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip To infer a register and place it in a specific location of a chip attach an RLOC constraint to the tmp signal as shown in the following coding example
343. for compilation xsthdpdir previously available only for VHDL is now available for Verilog e The xhdp ini mechanism for mapping a logical library name to a physical directory name on the host file system previously available only for VHDL is now available for Verilog Mixed language projects accept a search order used for searching unified logical libraries in design units cells During Elaboration XST follows this search order for picking and binding a VHDL entity or a Verilog module to the mixed language project Mixed Language Project Files XST uses dedicated mixed language project files to support mixed VHDL and Verilog designs You can use this mixed language format not only for mixed projects but also for purely VHDL or Verilog projects e If you run XST from ISE Design Suite it creates the project file It is always a mixed language project file e If you run XST from the command line you must create the mixed language project file yourself XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 439 XILINX Chapter 11 XST Mixed Language Support To create a mixed language project file at the command line use the ifmt command line option set to mixed or with its value is omitted You can still use the VHDL and Verilog formats for existing designs To use the VHDL format set ifmt to vhdl and to use the Verilog format set i fmt to verilog The syntax for invoking a library or any external file in a
344. for this parameter are none full parallel and full parallel If none default is used XST implements the exact behavior of the Case statements e If full is used XST considers that Case statements are complete and avoids latch creation e If parallel is used XST considers that the branches cannot occur in parallel and does not use a priority encoder e ffull parallel is used XST considers that Case statements are complete and that the branches cannot occur in parallel therefore saving latches and priority encoders Verilog Case Statement Resources indicates the resources used to synthesize the Multiplexers Case Statement Examples using the four Case Implementation Styles The term resources means the functionality For example if you code the Case statement neither full nor parallel with Case Implementation Style set to none from the functionality point of view XST implements a priority encoder latch But it does not inevitably mean that XST infers the priority encoder during the Macro Recognition step Multiplexers Verilog Case Statement Resources Parameter Value Case Implementation Specifying full parallel or full parallel may result in an implementation with a behavior that may differ from the behavior of the initial model XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 69 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Multiplexers Log File The XST log file
345. form efficient timing driven optimization In order to simplify instantiation of complex primitives as RAMs XST supports an additional library called UniMacro For more information see the Libraries Guides Generating Primitives Through Attributes Some primitives can be generated through attributes e Buffer Type BUFFER TYPE can be assigned to the primary input or internal signal to force the use of BUFGDLL IBUFG BUFR or BUFGP The same constraints can be used to disable buffer insertion e LO Standard IOSTANDARD can be used to assign an I O standard to an I O primitive For example the following assigns PCI33 5 I O standard to the I O port synthesis attribute IOSTANDARD of inl is PCI33 5 XST User Guide 220 www xilinx com UG627 v 11 3 September 16 2009 Chapter t XST FPGA Optimization XILINX Primitives and Black Boxes The primitive support is based on the concept of the black box For information on the basics of black box support see Safe FSM Implementation There is a significant difference between black box and primitive support Assume you have a design with a submodule called MUXF5 In general the MUXF5 can be your own functional block or a Xilinx device primitive To avoid confusion about how XST interprets this module attach BoxType BOX_TYPE to the component declaration of MUXF5 If BoxType BOX_TYPE is attached to the MUXF5 with a value of e primitive or black_box XST tries to interpre
346. from generate statements are used in composition of instance names For example for the following VHDL generate statement il loop for i in 1 to 10 generate inst lut LUT2 generic map INIT gt 00 XST generates the following instance names for LUT2 il loop 1 inst lut il loop 2 inst lut il loop 9 inst lut hee 10 inst lut Name register instances including state bits for the output signal Name clock buffer instances clockbuffertype such as BUFGP or IBUFG after the output signal Maintain instantiation instance names of black boxes Maintain instantiation instance names of library primitives Name input and output buffers using the form _IBUF or OBUF after the pad name Name Output instance names of IBUFs using the form instance name IBUF Name input instance names to OBUFs using the form instance name OBUF XST Name Generation Control Use the following properties to control aspects of the manner in which names are written Apply these properties in ISE Design Suite with Synthesis Properties or the appropriate command line options For more information see XST Design Constraints Hierarchy Separator hierarchy separator Bus Delimiter bus delimiter Case case Duplication Suffix duplication suffix 474 XST User Guide www xilinx com UG627 v 11 3 September 16 2009 XILINX Chapter 13 XST Command Line Mode This chapter describes how to run XST using the command li
347. g cccccccc eee eene emen nennen 442 Verilog in Mixed Language Port Mapping emen 442 Generics Support in Mixed Language Projects ssssssssesssseeeee e ee HH eren 442 Library Search Order LSO Files in Mixed Language Drolects e 442 Specifying the Library Search Order LSO File in ISE Design Suite sssssssssseeee 442 Specifying the Library Search Order LSO File in the Command Line sese 443 Library Search Order LSO Rules ssssssssseee eI e eee enne enn ener 443 Library Search Order ESO BEqmply ceu eeceeceee eren roten tore aee pep eoo o ed dene ge oue RE n eee RR e 443 DEFAULT SEARCH ORDER Keyword Only 443 DEFAULT SEARCH ORDER Keyword and List of Libraries sss 444 List of Libraries OMIY s 444 DEFAULT_SEARCH_ORDER Keyword and Non Existent Library Name 444 Chapter LE keelen eebe 447 XSTFEPGA Lop Fille Contents seis Emm 447 XST FPGA Log File Copyright Gtatement esee eene nnne 447 XST FPGA Log File Table of Contents erret rtt satcossnssatserssssseuessstsaveeasssnsnceassdsnnsssssdens 447 XST FPGA Log File Synthesis Options Gummar eene 448 XST FPGA Log File Hardware Description Language HDL Compilation sse 448 XST FPGA Log File Design Hierarchy Analyzer Hee 448 XST FPGA Log File Hardware Description Language HDL Analysis se 448 XST FPGA Log File Hardware Description Language HDL Sy
348. g The preceding Case statement evaluates the values of the input sel in priority order To avoid priority processing Xilinx recommends that you use a parallel case Verilog attribute to ensure parallel evaluation of the sel inputs as shown in the following parallel case case sel Behavioral Verilog For and Repeat Loops When using always blocks repetitive or bit slice structures can also be described using the or statement or the repeat statement XST User Guide 426 www xilinx com UG627 v 11 3 September 16 2009 thipter t XST Behavioral Verilog Language Support XILINX The for statement is supported for e Constant bounds e Stop test condition using operators lt lt gt or gt e Next step computation falling in one of the following specifications U r var step var var step where var is the loop variable and step is a constant value The repeat statement is supported for constant values only Disable statements are not supported Behavioral Verilog For Loop Coding Example module countzeros a Count input 7 0 a output 2 0 Count reg 2 0 Count reg 2 0 Count Aux integer i always a begin Count Aux 3 b0 for i 0 i lt 8 i itl begin if la il Count Aux Count Aux l end Count Count Aux end endmodule Behavioral Verilog While Loops When using always blocks use the while statement to execute repetitive procedures A whi
349. g into account DSP48 resources on the device In auto mode to control DSP48 resources for the synthesis use the DSP Utilization Ratio DSP_UTILIZATION_RATIO constraint By default XST tries to utilize all DSP48 resources For more information see DSP48 Block Resources To deliver the best performance XST by default tries to infer and implement the maximum macro configuration including as many registers as possible in the DSP48 To shape a macro in a specific way use the Keep KEEP constraint For example to exclude the first register stage from the DSP48 place Keep KEEP constraints on the outputs of these registers As with other families for Virtex 4 devices and Virtex 5 devices XST reports the details of inferred accumulators at the HDL Synthesis step Because accumulators are implemented within the MAC implementation mechanism they are no longer visible in the Final Synthesis Report Accumulators Log File The XST log file reports the type and size of recognized accumulators during the Macro Recognition step Synthesizing Unit lt accum gt Related source file is accumulators_1 vhd Found 4 bit up accumulator for signal tmp Summary inferred 1 Accumulator s Unit lt accum gt synthesized HDL Synthesis Report Macro Statistics Accumulators b 4 bit up accumulator g Accumulators Related Constraints e Use DSP48 USE_DSP48 e DSP Utilization Ratio DSP_UTILIZATION_RATIO e Keep KEEP Accumulators Coding
350. g syntax help arch family name command command name where e family name is a list of supported Xilinx families in the current version of XST e command name is one of the following XST commands run set elaborate time To see a list of supported families type help at the command line prompt with no argument XST issues the following message help ERROR Xst 1356 Help Missing arch family Please specify what family you want to target available families acr2 aspartan3 aspartan3a aspartan3adsp aspartan3e avirtex4 fpgacore qrvirtex4 qvirtex4 spartan3 spartan3a spartan3adsp spartan3e virtex4 virtex5 xa9500xl xbr xc9500 xc9500xl xpla3 To see a list of commands for a specific device type the following at the command line prompt with no argument help arch family name For example help arch virtex Use the following command to see a list of options and values for the run command for Virtex 5 devices XST User Guide 478 www xilinx com UG627 v 11 3 September 16 2009 Cbipttr i1 XST Command Line Mode XILINX gt help arch virtex5 command run This command gives the following output mult style Multiplier Style block lut auto pipe lut bufg Maximum Global Buffers bufgce BUFGCE Extraction YES NO decoder extract Decoder Extraction YES NO sifm ck ifmt Mixed VHDL Verilog O8 ms ofmt NGC NCD p ent top opt mode
351. g to a case sensitive port in a Verilog module By default XST assumes Verilog ports are in all lower case VHDL in Mixed Language Port Mapping XST supports the following VHDL data types for mixed language designs e bit bit vector e std logic e std ulogic std logic vector std ulogic vector Verilog in Mixed Language Port Mapping XST supports the following Verilog data types for mixed language designs e wire reg Generics Support in Mixed Language Projects XST supports the following VHDL generic types and their Verilog equivalents for mixed language designs e integer real string boolean Library Search Order LSO Files in Mixed Language Projects The Library Search Order LSO file specifies the search order that XST uses to link the libraries used in VHDL and Verilog mixed language designs By default XST searches the files specified in the project file in the order in which they appear in that file XST uses the default search order when e The DEFAULT SEARCH ORDER keyword is used in the LSO file or e The LSO file is not specified Specifying the Library Search Order LSO File in ISE Design Suite In ISE Design Suite the default name for the Library Search Order LSO file is project name Lso Ifa project name 1so file does not already exist ISE Design Suite automatically creates one If ISE Design Suite detects an existing project name 1so file this file is preserved and used as is In
352. ger type within a user defined range For example type MSB is range 8 to 15 means any integer greater than 7 or less than 16 The types NATURAL and POSITIVE are VHDL predefined types VHDL Overloaded STD LOGIC 1164 IEEE Types The following types are declared in the STD LOGIC 1164 IEEE package e STD ULOCGIC and subtypes X01 X01Z UX01 UX01Z e STD LOGIC STD ULOGIC VECTOR STD LOGIC VECTOR This package is compiled in the library IEEE To use one of these types add the following two lines to the VHDL specification library IEEE use IEEE STD LOGIC 1164 al1 XST User Guide 372 www xilinx com UG627 v 11 3 September 16 2009 hipter XST VHDL Language Support XILINX VHDL Overloaded STD_LOGIC_ARITH IEEE Types The types UNSIGNED and SIGNED defined as an array of STD_LOGIC are declared in the STD_LOGIC_ARITH IEEE package This package is compiled in the library IEEE To use these types add the following two lines to the VHDL specification library IEEE use IEEE STD LOGIC ARITH all VHDL Multi Dimensional Array Types XST supports multi dimensional array types of up to three dimensions BRAMs are not inferred Arrays can be e Signals e Constants e VHDL variables You can do assignments and arithmetic operations with arrays You can also pass multi dimensional arrays to functions and use them in instantiations The array must be fully constrained in all dimensions as shown in the following coding ex
353. gin state lt s4 outp lt 1 bl end s3 begin state lt s4 outp lt 1 Db0 end s4 begin state lt sl outp lt 1 b0 end endcase end end endmodule Finite State Machine FSM With Two Processes To eliminate a register from the outputs remove all assignments outp lt section This can be done by introducing two processes as shown below from the Clock synchronization XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 195 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Finite State Machine FSM With Two Processes Diagram Output e Outputs Register Function Only for Mealy Machine PROCESS 1 PROCESS 2 Finite State Machine FSM With Two Processes Pin Descriptions 10 Pins Description S clk Positive Edge Clock reset Asynchronous Reset Active High Finite State Machine FSM With Two Processes VHDL Coding Example State Machine with two processes library IEEE use IEEE std logic 1164 all entity fsm 2 is port clk reset x1 IN std logic outp OUT std logic end entity architecture behl of fsm 2 is type state type is s1 s2 s3 s4 signal state state type begin processi process clk reset begin if reset 1 then state lt s1 elsif clk 1 and clk Event then case state is when sl gt if x1 1 then state lt s2 else state lt s3 end if when s2 gt state lt s4 wh
354. gisters between the stages of distributed RAM pipelining can significantly increase the overall frequency of your design The effect of pipelining is similar to Flip Flop Retiming XST User Guide 184 www xilinx com UG627 v 11 3 September 16 2009 nuit XST Hardware Description Language HDL Coding Techniques XILINX To insert pipeline stages 1 Describe the necessary registers in your Hardware Description Language HDL code 2 Place them after any distributed RAM 3 Set the RAM Style RAM STYLE constraint to pipe_distributed In order to reach the maximum distributed RAM speed XST uses the maximum number of available registers when e It detects valid registers for pipelining and e RAM _STYLE is set to pipe_distributed In order to obtain the best frequency XST automatically calculates the maximum number of registers for each RAM During the Advanced HDL Synthesis step the XST HDL Advisor advises you to specify the optimum number of register stages if e You have not specified sufficient register stages and e RAM STYLE is coded directly on a signal XST implements the unused stages as shift registers if e The number of registers placed after the multiplier exceeds the maximum required and e Shift register extraction is activated XST cannot pipeline RAM if registers contain asynchronous set reset signals XST can pipeline RAM if registers contain synchronous reset signals XST User Guide UG627 v 11 3 Se
355. gnize FSM See Registers HDL Coding Techniques for coding examples on how to write Asynchronous and Synchronous initialization signals In VHDL the type of a state register can be a different type such as e integer bit vector std logic vector But it is common and convenient to define an enumerated type containing all possible state values and to declare your state register with that type In Verilog the type of state register can be an integer or a set of defined parameters In the following Verilog examples the state assignments could have been made as follows parameter 3 0 sl 4 p0001 s2 4 p0010 s3 4 p0100 s4 4 p1000 reg 3 0 state These parameters can be modified to represent different state encoding schemes Next State Equations Next state equations can be described directly in the sequential process or in a distinct combinational process The simplest coding example is based on a Case statement If using a separate combinational process its sensitivity list should contain the state signal and all FSM inputs Unreachable States XST can detect unreachable states in an FSM It lists them in the log file in the HDL Synthesis step Finite State Machine FSM Outputs Non registered outputs are described either in the combinational process or in concurrent assignments Registered outputs must be assigned within the sequential process Finite State Machine FSM Inputs Registered inputs are describe
356. he equation shaping processing also includes a critical path optimization algorithm This algorithm tries to reduce the number of levels of critical paths Xilinx recommends CPLD fitter multi level optimization because of the special optimizations done by the fitter DoT flip flop conversion e De Morgan Boolean expression selection Obtaining Better Frequency The frequency depends on the number of logic levels logic depth To reduce the number of levels Xilinx recommends the following options e Optimization Effort Set Optimization Effort to 2 or High This value implies the calling of the collapsing algorithm which tries to reduce the number of levels without increasing the complexity beyond certain limits e Optimization Goal Set Optimization Goal to Speed The priority is the reduction of number of levels Obtaining the best frequency depends on the CPLD fitter optimization Xilinx recommends running the multi level optimization of the CPLD fitter with different values for the pterms options beginning with 20 and finishing with 50 with a step of 5 Statistically the value 30 gives the best results for frequency XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 237 XILINX Chapter i XST CPLD Optimization The following tries in this order may give successively better results for frequency e Obtaining Better Frequency Try 1 e Obtaining Better Frequency Try 2 e Obtaining Better Frequency Try 3
357. hed BUFFER_TYPE Buffer Type Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it BUFFER_TYPE Buffer Type VHDL Syntax Example Declare as follows attribute buffer_type string Specify as follows attribute buffer type of signal name signal is bufgdll ibufg bufgp ibuf bufr none BUFFER_TYPE Buffer Type Verilog Syntax Example Place immediately before the signal declaration buffer type bufgdll ibufg bufgp ibuf bufr none zi BUFFER_TYPE Buffer Type XST Constraint File XCF Syntax Example BEGIN MODEL entity_name NET signal_name buffer type bufgdll ibufg bufgp ibuf bufr none END BUFGCE Extract BUFGCE BUFGCE Extract BUFGCE implements BUFGMUX functionality by inferring a BUFGMUX primitive This operation reduces the wiring Clock and clock enable signals are driven to n sequential components by a single wire BUFGCE must be attached to the primary clock signal BUFGCE values are yes no BUFGCE is accessible through Hardware Description Language HDL code If bufgce yes XST implements BUFGMUX functionality if possible AII flip flops must have the same clock enable signal BUFGCE Extract BUFGCE Architecture Support Applies to all FPGA devices Does not apply to CPLD devices BUFGCE Extract BUFGCE Applicable Elements Applies to
358. i XST Hardware Description Language HDL Coding Techniques Unsigned 8 Bit Greater or Equal Comparator Diagram CMP X10555 Unsigned 8 Bit Greater or Equal Comparator Pin Descriptions Comparison Operands Comparison Result Unsigned 8 Bit Greater or Equal Comparator VHDL Coding Example Unsigned 8 bit Greater or Equal Comparator library ieee use ieee std logic 1164 a11 use ieee std logic unsigned all entity comparator 1 is port A B in std logic vector 7 downto 0 CMP out Std logic end comparator 1 architecture archi of comparator 1 is begin CMP 1 when A B else 0 end archi Unsigned 8 Bit Greater or Equal Comparator Verilog Coding Example Unsigned 8 bit Greater or Equal Comparator module v comparator 1 A B CMP input 7 0 A input 750 B output CMP assign CMP A gt B 1 bl 1 b0 endmodule Multipliers Hardware Description Language HDL Coding Techniques When implementing a multiplier the size of the resulting signal is equal to the sum of two operand lengths For example if you multiply A 8 bit signal by B 4 bit signal the size of the result must be declared as a 12 bit signal XST User Guide 98 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX Registered Multipliers In instances where a multiplier would have a registered output XST infers a unique
359. iables The variables are handled in a similar manner as signals but are not of course outputs to the design In Combinatorial Process VHDL Coding Example One a variable named AUX is declared in the declarative part of the process and is assigned to a value with in the statement part of the process In combinatorial processes if a signal is not explicitly assigned in all branches of if or case statements XST generates a latch to hold the last value To avoid latch creation ensure that all assigned signals in a combinatorial process are always explicitly assigned in all paths of the Process statements XST User Guide 384 www xilinx com UG627 v 11 3 September 16 2009 Chapter T XST VHDL Language Support XILINX Different statements can be used in a process e Variable and signal assignment e If statement Case statement e For Loop statement e Function and procedure call Following are examples of each of these statements Assignments in a Process VHDL Coding Example entity EXAMPLE is port A B in BIT S 2 out BIT end EXAMPLE architecture ARCHI of EXAMPLE is begin process A B begin S lt Q if A and B 1 then S lt III end if end process end ARCHI Combinatorial Process VHDL Coding Example One library ASYL use ASYL ARITH all entity ADDSUB is port A B in BIT_VECTOR 3 downto 0 ADD_SUB in BIT S out BIT VECTOR 3 downto 0 end ADDSUB a
360. iagram Unsigned 8 Bit Adder With Carry In and Carry Out Pin Descriptions IO Pins Dom Deep XST User Guide 92 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX Unsigned 8 Bit Adder With Carry In and Carry Out VHDL Coding Example Unsigned 8 bit Adder with Carry In and Carry Out library ieee use ieee std_logic_1164 all use ieee std_logic_arith all use ieee std logic unsigned all entity adders 4 is port A B in std logic vector 7 downto 0 CI in std logic SUM out std logic vector 7 downto 0 CO out std logic end adders 4 architecture archi of adders 4 is signal tmp std logic vector 8 downto 0 begin tmp lt conv std logic vector conv integer A conv integer B conv integer CI 9 SUM lt tmp 7 downto 0 CO lt tmp 8 end archi Unsigned 8 Bit Adder With Carry In and Carry Out Verilog Coding Example Unsigned 8 bit Adder with Carry In and Carry Out module v_adders_4 A B CI SUM CO input CI input 7 0 A input 7 0 B output 7 0 SUM output CO wire 8 0 tmp assign tmp A B CI assign SUM tmp 7 0 assign CO tmp 8 endmodule Signed 8 Bit Adder Diagram Add Operands Add Result XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 93 XILINX Chapter i XST Hardware Description Language HDL Coding Techni
361. ication Diagram RESET x10560 Multiplier Up Accumulate With Register After Multiplication Pin Descriptions Positive Edge Clock Synchronous Reset MAC Operands MAC Result Multiplier Up Accumulate With Register After Multiplication VHDL Coding Example Multiplier Up Accumulate with Register After Multiplication library IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD LOGIC UNSIGNED ALL entity multipliers 7a is generic p width integer 8 port clk reset in std logic A B in std logic vector p width 1 downto 0 RES out std logic vector p width 2 1 downto 0 end multipliers 7a architecture beh of multipliers 7a is Signal mult accum std logic vector p width 2 1 downto 0 begin process clk begin if clk event and clk 1 then if reset 1 then accum lt others gt 0 mult lt others gt 0 else accum lt accum mult mult lt A B end if end if end process RES lt accum end beh XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 119 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Multiplier Up Accumulate With Register After Multiplication Verilog Coding Example Multiplier Up Accumulate with Register After Multiplication fd module v multipliers 7a clk reset A B RES input clk reset input 7 0 A input 7 0 B output 15 0 RES reg 15 0 mult accum always
362. icular tools or methods If a tool or method is not listed you cannot use this constraint with it SHIFT_EXTRACT Logical Shifter Extraction VHDL Syntax Example Declare as follows attribute shift_extract string Specify as follows attribute shift_extract of entity_name signal_name signal entity is yes no SHIFT_EXTRACT Logical Shifter Extraction Verilog Syntax Example Place immediately before the module declaration or instantiation shift extract yes no SHIFT EXTRACT Logical Shifter Extraction XST Constraint File XCF Syntax Example One MODEL entity name shift extract yes no true false SHIFT EXTRACT Logical Shifter Extraction XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name NET signal name shift extract yes no true false END SHIFT EXTRACT Logical Shifter Extraction XST Command Line Syntax Example Define in the XST command line as follows shift extract yes no The default is yes SHIFT EXTRACT Logical Shifter Extraction ISE Design Suite Syntax Example Define in ISE Design Suite with Process Properties HDL Options Logical Shifter Extraction LC LUT Combining LC LUT Combining enables the merging of LUT pairs with common inputs into single dual output LUT6s in order to improve design area This optimization process may reduce design speed XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 309 XILINX
363. ignal that appears in conditions If or Case for example and any signal appearing on the right hand side of an assignment By substituting an asterisk without parentheses for a list of signals the always block is activated for an event in any of the always block s signals as described above In combinatorial processes if a signal is not explicitly assigned in all branches of If or Case statements XST generates a latch to hold the last value To avoid latch creation be sure that all assigned signals in a combinatorial process are always explicitly assigned in all paths of the process statements Various statements can be used in a process e Variable and signal assignment e If else statement e Case statement e For and while loop statement e Function and task call Behavioral Verilog If Else Statement If else statements use true false conditions to execute statements e If the expression evaluates to true the first statement is executed e If the expression evaluates to false or x or z the else statement is executed A block of multiple statements may be executed using begin and end keywords If else statements may be nested XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 425 XILINX Chapter 1 XST Behavioral Verilog Language Support Behavioral Verilog If Else Statement Coding Example The following coding example shows how a MUX can be described using an If else statement
364. il Section The Timing Detail section of the Timing Report describes the most critical path in detail for each region e Start point of the path e End point of the path e Maximum delay of the path e Slack The start and end points can be e Clock with the phase rising falling or e Port Path from Clock sysclk rising to Clock sysclk rising 7 523ns Slack 7 523ns The detailed path shows e Cell type e Input and output of this gate e Fanout at the output e Gate delay e Net delay estimate e Name of the instance When entering a hierarchical block begin scope is printed When exiting a hierarchical block end scope is printed Timing Report Schematic The preceding report corresponds to the following schematic gt C 1 372ns 2 970ns 0 738ns D 0 440ns state FFD1 LUT 54 next state 2 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 219 XILINX Chapter 4 XST FPGA Optimization Timing Report Paths and Ports The Timing Report section shows the number of analyzed paths and ports If XST is run with timing constraints it also shows the number of failed paths and ports The number of analyzed and failed paths shows how many timing problems there are in the design The number of analyzed and failed ports may show how they are spread in the design The number of ports in a timing report represent the number of destination elements for a timing constraint For ex
365. in Process gt Properties or Command Line Process Property ISE Design Suite Values glob_opt Global Optimization Goal allclocknetsinpad _to_outpadoffset _in_beforeoffset out aftermax delay default allclocknets cross clock analysis Cross Clock Analysis yes no default no write timing constraints Write Timing Constraints yes no default no XST Timing Options XST Constraint File XCF The following XST timing constraints can be applied for synthesis only through the XST Constraint File XCF e Period PERIOD e Offset OFFSET e From To FROM TO e Timing Name TNM e Timing Name on a Net TNM_NET e Timegroup TIMEGRP e Timing Ignore TIG e Timing Specifications TIMESPEC e Timing Specification Identifier TSidentifier These timing constraints influence synthesis optimization and can be passed on to place and route by selecting the Write Timing Constraints command line option For more information as to the Value and Target of each constraint see the Constraints Guide XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 263 XILINX nuit t XST Design Constraints XST General Constraints The following general constraints apply to FPGA devices CPLD devices VHDL and Verilog You can set some of these options in ISE Design Suite in Process gt Properties gt Synthesis Options e Add I O Buffers iobuf e BoxType BOX_TYPE e Bus Delimiter bus delimiter e Cas
366. in std logic PO out std logic vector 7 downto 0 end shift registers 8 architecture archi of shift registers 8 is signal tmp std logic vector 7 downto 0 begin process C begin if C event and C 1 then if LEFT RIGHT 0 then tmp lt tmp 6 downto 0 amp SI else tmp lt SI amp tmp 7 downto 1 end if end if end process PO tmp end archi XST User Guide 64 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX 8 Bit Shift Left Shift Right Register With Positive Edge Clock Serial In and Parallel Out Verilog Coding Example if 8 bit Shift Left Shift Right Register with Positive Edge Clock Serial In and Parallel Out module v_shift_registers_8 C SI LEFT_RIGHT PO input C SI LEFT RIGHT output 7 0 PO reg 7 0 tmp always posedge C begin if LEFT RIGHT 1 b0 tmp lt tmp 6 0 SI else tmp lt SI tmp 7 1 end assign PO tmp endmodule Dynamic Shift Registers Hardware Description Language HDL Coding Techniques XST can infer Dynamic Shift Registers Once a Dynamic Shift Register has been identified its characteristics are handed to the XST macro generator for optimal implementation using the primitives shown in the following table E NER SRL16 SRL16E SRLC16 SRLC16E SRLC32E Spartan 3 Spartan 3E Spartan 3A Virtex 4 Virtex 4 EE Dynamic Shif
367. ing Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip For the following VHDL and Verilog examples XST gives the following solution Resource Sharing Diagram B OPER OPER XST User Guide 124 www xilinx com UG627 v 11 3 September 16 2009 hapter 1 XST Hardware Description Language HDL Coding Techniques XILINX Resource Sharing Pin Descriptions gp Beseription S A B C Operands OPER Operation Selector RES Data Output Resource Sharing VHDL Coding Example Resource Sharing library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity resource sharing 1 is port A B C in std logic vector 7 downto 0 OPER in std logic RES out std logic vector 7 downto 0 end resource sharing 1 architecture archi of resource sharing 1l is begin RES lt A B when OPER 0 else A C end archi Resource Sharing Verilog Coding Example Resource Sharing module v resource sharing 1 A B C OPER RES input 7 0 A B C input OPER output 7 0 RES wire 7 0 RES assign RES OPER A B A C endmodule XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 125 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques RAMs and ROMs Hardware Description Language HDL Coding Techniques If you do no
368. initions XST supports the following generate statements e Behavioral Verilog Generate For Statements e Behavioral Verilog Generate If else Statements e Behavioral Verilog Generate Case Statements XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 435 XILINX Chapter 1 XST Behavioral Verilog Language Support Behavioral Verilog Generate For Statements Use a generate for loop to create one or more instances that can be placed inside a module Use the generate for loop the same way you would a normal Verilog for loop with the following limitations e The index fora generate for loop has a genvar variable e The assignments in the for loop control refers to the genvar variable The contents of the for loop are enclosed by begin and end statements The begin statement is named with a unique qualifier 8 Bit Adder Using a Generate For Loop Behavioral Verilog Coding Example generate genvar i for i 0 i lt 7 i i 1 begin for_name adder add a 8 it7 8 i b 8 i 7 8 i cili sum_for 8 it 7 8 i cO or i 1 end endgenerate Behavioral Verilog Generate If else Statements Useagenerate if elsestatement inside a generate block to conditionally control which objects are generated Generate If else Statement Behavioral Verilog Coding Example In the following coding example of a generate if else statement generate controls the type of multiplier that is instantiated e The co
369. ion Supported except for deferred constant Signal Declaration Supported except for register and bus type signals Attribute Declaration Supported for some attributes otherwise skipped see XST Design Constraints VHDL Specifications Attribute Supported for some predefined attributes only HIGHLOW LEFT RIGHT RANGE REVERSE_RANGE LENGTH POS ASCENDING EVENT LAST_VALUE Configuration Supported only with the a11 clause for instances list If no clause is added XST looks for the entity or architecture compiled in the default library Disconnection Unsupported XST does not allow underscores as the first character of signal names for example DATA 1 398 XST User Guide www xilinx com UG627 v 11 3 September 16 2009 hipter XST VHDL Language Support XILINX VHDL Expressions XST supports the following expressions e VHDL Operators e VHDL Operands VHDL Operators Logical Operators Supported and or nand nor xor xnor not Relational Operators Supported Shift Operators Supported VHDL Operands Operand Supported Unsupported Abstract Literals Only integer literals are supported Physical Literals Ignored Enumeration Literals Supported String Literals Supported Bit String Literals Supported Record Aggregates Supported Array Aggregates Supported Function Call Supported Qualified Expressions Supported for accepted predefined attributes Types Conversions Supported Alloc
370. ion Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it MUX EXTRACT Mux Extraction VHDL Syntax Example Declare as follows attribute mux extract string XST User Guide 290 www xilinx com UG627 v 11 3 September 16 2009 taptir i XST Design Constraints XILINX Specify as follows attribute mux_extract of signal_name entity_name entity signal is yes no force The default is yes MUX_EXTRACT Mux Extraction Verilog Syntax Example Place immediately before the module or signal declaration mux extract yes no force zi The default is yes MUX_EXTRACT Mux Extraction XST Constraint File XCF Syntax Example One MODEL entity name mux_extract yes no true false force MUX EXTRACT Mux Extraction XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name NET signal name mux_extract yes no true false force END MUX EXTRACT Mux Extraction XST Command Line Syntax Example Define in the XST command line as follows mux extract yes no force The default is yes MUX EXTRACT Mux Extraction ISE Design Suite Syntax Example Define in ISE Design Suite with Process Properties HDL Options REGISTER POWERUP Register Power Up XST does not automatically calculate and enforce register power up values You must expli
371. ious aspects of synthesis as well as placement and routing Synthesis algorithms and heuristics automatically provide optimal results in most situations If synthesis fails to initially achieve optimal results use available constraints to try other synthesis alternatives The following mechanisms are available to specify constraints Options provide global control on most synthesis aspects They can be set either in ISE Design Suite in Process Properties Synthesis Options or by the run command from the command line e VHDL attributes can be directly inserted into the VHDL code and attached to individual elements of the design to control both synthesis and placement and routing e Constraints can be added as Verilog attributes preferred or Verilog meta comments e Constraints can be specified in a separate constraint file Global synthesis settings are typically defined in ISE Design Suite in Process Properties Synthesis Options or from the command line VHDL and Verilog attributes and Verilog meta comments can be inserted in your source code to specify different choices for individual parts of the design The local specification of a constraint overrides its global setting Similarly if a constraint is set both on a node or an instance and on the enclosing design unit the former takes precedence for the considered node or instance XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 241 XILINX
372. ipter 1 XST Hardware Description Language HDL Coding Techniques XILINX 4 Bit Register With Positive Edge Clock Asynchronous Set and Clock Enable Diagram PRE D FDPE Q CE c p 4 Bit Register With Positive Edge Clock Asynchronous Set and Clock Enable Pin Descriptions Positive Edge Clock Asynchronous Set Active High Clock Enable Active High 4 Bit Register With Positive Edge Clock Asynchronous Set and Clock Enable VHDL Coding Example 4 bit Register with Positive Edge Clock Asynchronous Set and Clock Enable library ieee use ieee std logic 1164 al1 entity registers 5 is port C CE PRE in std logic D in std logic vector 3 downto 0 Q out std logic vector 3 downto 0 end registers 5 architecture archi of registers 5 is begin process C PRE begin if PRE 1 then Q lt 1111 elsif C event and C 1 then if CE 1 then Q lt D end if end if end process end archi XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 29 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques 4 Bit Register With Positive Edge Clock Asynchronous Set and Clock Enable Verilog Coding Example 4 bit Register with Positive Edge Clock Asynchronous Set and Clock Enable module v_registers_5 C D CE PRE Q input C CE PRE input 3 0 D output 3 0 Oo reg 3 0 Oo always 8 posedge C or posedge PRE begin if PRE Q
373. iques XST recognizes counters with the following control signals e Asynchronous Set Reset e Synchronous Set Reset e Asynchronous Synchronous Load signal or constant or both e Clock Enable e Modes Up Down Up Down e Mixture of all of the above Hardware Description Language HDL coding styles for the following control signals are equivalent to those described in Registers Hardware Description Language HDL Coding Techniques e Clock e Asynchronous Set Reset e Synchronous Set Reset XST supports both unsigned and signed counters XST User Guide 36 www xilinx com UG627 v 11 3 September 16 2009 lhapter 1 XST Hardware Description Language HDL Coding Techniques XILINX Counters Log File The XST log file reports the type and size of recognized counters during the Macro Recognition step Synthesizing Unit lt counter gt Related source file is counters l vhd Found 4 bit up counter for signal tmp Summary inferred 1 Counter s Unit lt counter gt synthesized HDL Synthesis Report Macro Statistics Counters ae 4 bit up counter SS Counters Related Constraints e Use DSP48 USE_DSP48 e DSP Utilization Ratio DSP UTILIZATION RATIO e Keep KEEP Counters Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip 4 Bit Unsigned Up Counter With Asynchronous Reset Diagram 4 Bit Unsigned U
374. ir i XST Design Constraints XILINX XST Constraint File XCF Syntax Limitations XST Constraint File XCF syntax has the following limitations e Nested model statements are not supported e Instance or signal names listed between the BEGIN MODEL statement and the END statement are only the ones visible inside the entity Hierarchical instance or signal names are not supported e Wildcards in instance and signal names are not supported except in timing constraints e Not all native User Constraints File UCF constraints are supported For more information see the Constraints Guide Constraints Priority Constraints priority depends on the file in which the constraint appears A constraint in a file accessed later in the design flow overrides a constraint in a file accessed earlier in the design flow Priority is as follows from highest to lowest 1 Synthesis Constraint File 2 Hardware Description Language HDL file 3 ISE Design Suite Process gt Properties or the command line XST Specific Non Timing Options The following table shows e Allowed values for each constraint e Type of objects to which they can be applied Usage restrictions In many cases a particular constraint can be applied globally to an entire entity or model or alternatively it can be applied locally to individual signals nets or instances XST Specific Non Timing Options Constraint VHDL Constraint Command Command Name Value Target
375. irtex architecture or Spartan architecture and then integrated into the rest of the design In addition the generated functions are optimized through their borders depending on the design context This discussion categorizes by function all available macros and briefly describes technology resources used in the building and optimization phase Macro Generation can be controlled through attributes These attributes are listed in each subsection For general information on attributes see XST Design Constraints XST User Guide 204 www xilinx com UG627 v 11 3 September 16 2009 Chapter XST FPGA Optimization XILINX XST uses dedicated carry chain logic to implement many macros In some situations carry chain logic may lead to sub optimal optimization results Use the Use Carry Chain USE CARRY CHAIN constraint to deactivate this feature Arithmetic Functions in Macro Generation For Arithmetic Functions XST provides the following elements e Adders Subtractors and Adder Subtractors e Cascadable Binary Counters e Accumulators ncrementers Decrementers and Incrementer Decrementers e Signed and Unsigned Multipliers XST uses fast carry logic MUXCY to provide fast arithmetic carry capability for high speed arithmetic functions The sum logic formed from two XOR gates is implemented using LUTs and the dedicated carry XORs XORCY In addition XST benefits from a dedicated carry ANDs MULTAND resource for high spe
376. is integer MAX FANOUT Max Fanout Verilog Syntax Example Place immediately before the signal declaration max fanout integer zi MAX FANOUT Max Fanout XST Constraint File XCF Syntax Example One MODEL entity name max fanout integer MAX FANOUT Max Fanout XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name NET signal name max fanout integer END MAX FANOUT Max Fanout XST Command Line Syntax Example Define in the XST command line as follows max fanout integer XST User Guide 312 www xilinx com UG627 v 11 3 September 16 2009 hapter i XST Design Constraints XILINX MAX_FANOUT Max Fanout ISE Design Suite Syntax Example Define in ISE Design Suite with Process gt Properties gt Xilinx Specific Options gt Max Fanout MOVE_FIRST_STAGE Move First Stage MOVE_FIRST_STAGE Move First Stage controls the retiming of registers with paths coming from primary inputs Both MOVE_FIRST_STAGE and MOVE_LAST_STAGE Move Last Stage relate to Register Balancing Note e A flip flop FF in the diagram belongs to the First Stage if it is on the paths coming from primary inputs e A flip flop belongs to the Last Stage if it is on the paths going to primary outputs MOVE_FIRST_STAGE Move First Stage Diagram Copies Ken Loge v Ev First FF Last FF Stage Stage During register balancing First Stage flip flops are moved forward e Last Stage flip flops are moved backward
377. is attribute can also be global The attribute MUX_EXTRACT with respectively the value no or force can be used to disable or force the inference of the multiplexer You still may have MUXFx elements in the final netlist even if multiplexer inference is disabled using the MUX EXTRACT constraint These elements come from the general mapping procedure of Boolean equations Priority Encoders in Macro Generation The if elsif structure described in Priority Encoders Hardware Description Language HDL Coding Techniques is implemented with a 1 of n priority encoder XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 205 XILINX Chapter 4 XST FPGA Optimization XST uses the MUXCY primitive to chain the conditions of the priority encoder which results in its high speed implementation Use the Priority Encoder Extraction PRIORITY_EXTRACT constraint to enable or disable priority encoder inference XST does not generally infer and so does not generate a large number of priority encoders To enable priority encoders use the Priority Encoder Extraction PRIORITY_EXTRACT constraint with the force option Decoders in Macro Generation A decoder is a demultiplexer whose inputs are all constant with distinct one hot or one cold coded values An n bit or 1 of m decoder is mainly characterized by an m bit data output and an n bit selection input such that n 2 1 lt m lt n 2 Once XST has inferred the decoder th
378. ith Synchronous Read Read Through Lf module v rams 11 clk we a dpra di spo dpo input elk input we input 5 0 a input 5 0 dpra input 15 0 di output 15 0 spo output 15 0 dpo reg 15 0 ram 63 0 reg 5 0 read a reg 5 0 read dpra always posedge clk begin if we ram a lt di read_a lt a read_dpra lt dpra end assign spo assign dpo ram read_a ram read_dpra oil endmodule Dual Port RAM With Synchronous Read Read Through and Two Clocks Diagram WE DI DO1 Block ADD1 DO2 ADD2 PAM CLK1 p CLK2 gt Dual Port RAM With Synchronous Read Read Through and Two Clocks Pin Descriptions clk1 Positive Edge Write Primary Read Clock clk2 Positive Edge Dual Read Clock we Synchronous Write Enable Active High XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 145 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Dual Port RAM With Synchronous Read Read Through and Two Clocks VHDL Coding Example Dual Port RAM with Synchronous Read Read Through using More than One Clock library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity rams 12 i port clk1 in std logic Clk2 in std logic we in std logic addl in std logic vector 5 downto 0 add2 in std logic vector 5 downto 0 di in std logic vector 15 downto 0 dol out std logic vector 15 downto 0
379. itial Contents Verilog Coding Example Initializing Block RAM hf module v rams 20a clk we a input clk input we input 5 0 addr input 19 0 di output 19 0 do reg 19 0 ram 63 0 reg 19 0 do initial begin ram 63 20 h0200A ram 62 ram 60 20 h04000 ram 59 ram 57 20 h00300 ram 56 ram 54 20 h0203B ram 53 ram 51 20 h08201 ram 50 ram 48 20 h02500 ram 47 ram 45 20 h04002 ram 44 ram 42 20 h00500 ram 41 ram 39 20 h04003 ram 38 ram 36 20 h00102 ram 35 ram 33 20 h00301 ram 32 ram 30 20 h04001 ram 29 ram 27 20 h00900 ram 26 ram 24 20 h04002 ram 23 ram 21 20 h02023 ram 20 ram 18 20 h00301 ram 17 ram 15 20 h00102 ram 14 ram 12 20 h00301 ram 11 ram 9 20 h04004 ram 8 ram 6 20 h02500 ram 5 ram 3 20 h0030D ram 2 ram 0 20 h0400D end always posedge clk begin if we ram addr do lt ram addr lt di ddr 20 Single Port BRAM di do 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 h00300 ram h08601 ram h08602 ram h08300 ram h00500 ram h00340 ram h08300 ram h08101 ram h0241E ram h02122 ram h00102 ram h00342 ram h00302 ram h00900 ram h00303 ram h04004 ram h02137 ram h00102 ram h00304 ram 7 20 h02500 ram 4 20 h02341 ram 1 61 20 h08101 58 2
380. ity rams 21b is port clk in std logic en in std logic addr in std logic vector 5 downto 0 data out std logic vector 19 downto 0 end rams 21b architecture syn of rams 21b is type rom type is array 63 downto 0 of std logic vector 19 downto 0 signal ROM rom type X 0200A X 00300 X 08101 X 04000 X 08601 X 0233A X 00300 X 08602 X 02310 X 0203B X 08300 x 04002 X 08201 X 00500 X 04001 X 02500 X 00340 x 00241 X 04002 X 08300 X 08201 X 00500 X 08101 X 00602 X 04003 X 0241E X 00301 X 00102 X 02122 X 02021 X 00301 X 00102 X 02222 X 04001 X 00342 X 0232B X 00900 X 00302 X 00102 X 04002 X 00900 X 08201 X 02023 X 00303 X 02433 X 00301 X 04004 X 00301 X 00102 X 02137 X 02036 X 00301 X 00102 X 02237 X 04004 X 00304 X 04040 X 02500 X 02500 x 02500 X 0030D X 02341 X 08201 X 0400D signal rdata std logic vector 19 downto 0 begin rdata lt ROM conv integer addr process clk begin if clk event and clk 1 then if en 1 then data lt rdata end if end if end process end syn XST User Guide 180 www xilinx com UG627 v 11 3 September 16 2009 Chipter1 XST Hardware Description Language HDL Coding Techniques XILINX ROM With Registered Output Verilog Coding Example One ROMs Using Block RAM Resources Verilog code for a ROM with registered o
381. k Enable USE CLOCK ENABLE Use Synchronous Set USE SYNC SET Use Synchronous Reset USE SYNC RESET Use DSP48 USE DSP48 XST CPLD Constraints Non Timing The following constraints are found in XST CPLD Constraints Non Timing Clock Enable pld ce Data Gate DATA GATE Macro Preserve pld mp No Reduce NOREDUCE WYSIWYG wysiwyg XOR Preserve pld xp XST Timing Constraints The following constraints are found in XST Timing Constraints Cross Clock Analysis cross clock analysis Write Timing Constraints write timing constraints Clock Signal CLOCK SIGNAL Global Optimization Goal glob opt XCF Timing Constraint Support Period PERIOD Offset OFFSET From To FROM TO Timing Name TNM Timing Name on a Net TNM NET Timegroup TIMEGRP Timing Ignore TIG XST User Guide UG627 v 11 3 September 16 2009 www xilinx com XILINX 245 XILINX nuit t XST Design Constraints XST Implementation Constraints The following constraints are found in XST Implementation Constraints e RLOC e NOREDUCE e PWR MODE Third Party Constraints For a discussion of Third Party Constraints and their XST equivalents see XST Supported Third Party Constraints Setting Global Constraints and Options This section explains how to set global constraints and options in ISE Design Suite in Process gt Properties For a description of each constraint that applies generally that is to FPGA device
382. l In and Serial Out VHDL Coding Example 8 bit Shift Left Register with Negative Edge Clock Clock Enable Serial In and Serial Out library ieee use ieee std logic 1164 al1 entity shift registers 2 is port C SI CE in std logic SO out std logic end shift registers 2 architecture archi of shift registers 2 is signal tmp std logic vector 7 downto 0 begin process C begin if C event and C 0 then if CE 1 then for i in 0 to 6 loop tmp i 1 lt tmp i end loop tmp 0 lt SI end if end if end process SO lt tmp 7 end archi XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 55 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques 8 Bit Shift Left Register With Negative Edge Clock Clock Enable Serial In and Serial Out Verilog Coding Example 8 bit Shift Left Register with Negative Edge Clock Clock Enable Serial In and Serial Out module v_shift_registers_2 C CE SI SO input C SI CE output SO reg 7 0 tmp always 8 negedge C begin if CE begin tmp tmp 6 0 SI end end assign SO tmp 7 endmodule 8 Bit Shift Left Register With Positive Edge Clock Asynchronous Reset Serial In and Serial Out Diagram si SHIFT so C D CLR x10538 8 Bit Shift Left Register With Positive Edge Clock Asynchronous Reset Serial In and Serial Out Pin Descriptions Asynchronous Reset A
383. late 2 6 b100000 rdata 6 b100001 rdata 6 b100010 rdata 6 b100011 rdata 6 b100100 rdata 6 b100101 rdata 6 b100110 rdata 6 b100111 rdata 6 b101000 rdata 6 b101001 rdata 6 b101010 rdata 6 b101011 rdata 6 b101100 rdata 6 b101101 rdata 6 b101110 rdata 6 b101111 rdata 6 b110000 rdata 6 b110001 rdata 6 b110010 rdata 6 b110011 rdata 6 b110100 rdata 6 b110101 rdata 6 5110110 rdata 6 b110111 rdata 6 b111000 rdata 6 b111001 rdata b blll010 rdata 6 b111011 rdata 6 b111100 rdata 6 b111101 rdata 6 b111110 rdata 6 b111111 rdata 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 h02222 h04001 h00342 h0232B h00900 h00302 h00102 h04002 h00900 h08201 h02023 h00303 h02433 h00301 h04004 h00301 h00102 h02137 h02036 h00301 h00102 h02237 h04004 h00304 h04040 h02500 h02500 h02500 h0030D h02341 h08201 h0400D EN DATA Block ADDR ROM CLK XST User Guide 182 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX ROM With Registered Address Pin Descriptions ppm Beseription S clk Positive Edge Clock en Synchronous Enable Activ
384. le Define in ISE Design Suite with Process Properties Synthesis Options Write Timing Constraints CLOCK SIGNAL Clock Signal If a clock signal goes through combinatorial logic before being connected to the clock input of a flip flop XST cannot identify what input pin or internal signal is the real clock signal CLOCK SIGNAL Clock Signal allows you to define the clock signal CLOCK SIGNAL Clock Signal Architecture Support Applies to all FPGA devices Does not apply to CPLD devices XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 353 XILINX nuit t XST Design Constraints CLOCK_SIGNAL Clock Signal Applicable Elements Applies to signals CLOCK_SIGNAL Clock Signal Propagation Rules Applies to clock signals CLOCK_SIGNAL Clock Signal Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it CLOCK_SIGNAL Clock Signal VHDL Syntax Example Declare as follows attribute clock_signal string Specify as follows attribute clock_signal of signal_name signal is yes no CLOCK_SIGNAL Clock Signal Verilog Syntax Example Place immediately before the signal declaration clock_signal yes no CLOCK SIGNAL Clock Signal XST Constraint File XCF Syntax Example BEGIN MODEL entity_name NET primary_clock_signal clock_signal yes no true fals
385. le XCF Syntax Example Two BEGIN MODEL entity name NET signal name resource sharing yes no true false END RESOURCE SHARING Resource Sharing XST Command Line Syntax Example Define in the XST command line as follows resource sharing yes no The default is yes RESOURCE SHARING Resource Sharing ISE Design Suite Syntax Example Define in ISE Design Suite with HDL Options Resource Sharing SAFE RECOVERY STATE Safe Recovery State SAFE RECOVERY STATE Safe Recovery State defines a recovery state for use when a Finite State Machine FSM is implemented in Safe Implementation mode If the FSM enters an invalid state XST uses additional logic to force the FSM to a valid recovery state By implementing FSM in safe mode XST collects all code not participating in the normal FSM behavior and treats it as illegal XST uses logic that returns the FSM synchronously to the e Known state e Reset state e Power up state e State you specified using SAFE RECOVERY STATE For more information see Safe Implementation SAFE IMPLEMENTATION XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 293 XILINX nuit t XST Design Constraints SAFE_RECOVERY_ STATE Safe Recovery State Architecture Support Architecture independent SAFE_RECOVERY_ STATE Safe Recovery State Applicable Elements Applies to a signal representing a state register SAFE_RECOVERY_ STATE Safe Recovery State Propagation Rul
386. le loop executes other statements until its test expression becomes false It is not executed if the test expression is initially false e The test expression is any valid Verilog expression e To prevent endless loops use the loop_iteration_limit option While loops can have disable statements The disable statement is used inside a labeled block since the syntax is disable blockname Behavioral Verilog While Loop Coding Example parameter P 4 always Q8 ID complete begin UNIDENTIFIED integer i reg found unidentified 0 i 0 found 0 while found amp amp i lt P begin found ID complete i unidentified i ID complete i i i 4 1 end end XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 427 XILINX Chapter 1 XST Behavioral Verilog Language Support Behavioral Verilog Sequential Always Blocks Sequential circuit description is based on always blocks with a sensitivity list The sensitivity list contains a maximum of three edge triggered events e A clock signal event mandatory e A reset signal event possibly e A set signal event One and only one if else statement is accepted in such an always block An asynchronous part may appear before the synchronous part in the first and the second branch of the if else statement Signals assigned in the asynchronous part are assigned to the following constant values e 0 e 1 e X e Z e Any vector composed
387. lexity when all non fittable BRAMs are converted to distributed RAMs BRAM UTILIZATION RATIO BRAM Utilization Ratio Architecture Support Applies to all FPGA devices Does not apply to CPLD devices BRAM UTILIZATION RATIO BRAM Utilization Ratio Applicable Elements Applies to the entire design BRAM UTILIZATION RATIO BRAM Utilization Ratio Propagation Rules Not applicable XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 299 XILINX nuit t XST Design Constraints BRAM_UTILIZATION_RATIO BRAM Utilization Ratio Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it BRAM_UTILIZATION_RATIO BRAM Utilization Ratio XST Command Line Syntax Examples Define in the XST command line as follows bram utilization ratio integer 4 where integer range is 1 to 100 when is used or both and are omitted The default is 100 BRAM UTILIZATION RATIO BRAM Utilization Ratio XST Command Line Syntax Example One bram utilization ratio 50 means 50 of BRAMs blocks in the target device BRAM UTILIZATION RATIO BRAM Utilization Ratio XST Command Line Syntax Example Two bram utilization ratio 50 means 50 of BRAMs blocks in the target device BRAM UTILIZATION RATIO BRAM Utilization Ratio XST Command Line Syntax Example Three bram utilization ratio 504 means 50 BRAMs blo
388. linx com UG627 v 11 3 September 16 2009 XILINX Chapter 10 XST Mixed Language Support This chapter describes how to run an XST project that mixes Verilog and VHDL designs and includes e Mixed Language Project Files e VHDL and Verilog Boundary Rules in Mixed Language Projects e Port Mapping in Mixed Language Projects e Generics Support in Mixed Language Projects e Library Search Order LSO Files in Mixed Language Projects XST supports mixed VHDL and Verilog projects e Mixing VHDL and Verilog is restricted to design unit cell instantiation only A VHDL design can instantiate a Verilog module A Verilog design can instantiate a VHDL entity No other mixing between VHDL and Verilog is not supported e Ina VHDL design a restricted subset of VHDL types generics and ports is allowed on the boundary to a Verilog module Ina Verilog design a restricted subset of Verilog types parameters and ports is allowed on the boundary to a VHDL entity or configuration e XST binds VHDL design units to a Verilog module during Elaboration e Component instantiation based on default binding is used for binding Verilog modules to a VHDL design unit e Configuration specification direct instantiation and component configurations are not supported for a Verilog module instantiation in VHDL e VHDL and Verilog project files are unified e VHDL and Verilog libraries are logically unified e Specification of the work directory
389. lizing RAM from an External File below XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 169 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques RAM Initial Contents VHDL Coding Example Hexadecimal To specify RAM initial contents initialize the signal describing the memory array in the VHDL code as shown in the following coding example type ram_type is array 0 to 63 of std_logic_vector 19 downto 0 signal RAM ram_type X 0200A X 00300 X 08101 X 04000 X 08601 X 0233A X 00300 X 08602 X 02310 X 0203B X 08300 X 04002 X 08201 X 00500 X 04001 X 02500 X 00340 X 00241 X 04002 X 08300 X 08201 X 00500 X 08101 X 00602 X 04003 X O241E X 00301 X 00102 X 02122 X 02021 X 00301 X 00102 X 02222 X 04001 X 00342 X 0232B X 00900 X 00302 X 00102 X 04002 X 00900 X 08201 X 02023 X Q0S03 X 02433 X00301 x 04004 X OOSOI X 00102 X 02137 X 02036 X 00301 X D0102 X 02237 X 04004 X 00304 X 04040 X 02500 X 02500 X 02500 X 0030D X 02341 X 08201 X 0400D process clk begin if rising edge clk then if we 1 then RAM conv integer a di end if ra lt a end if end process do lt RAM conv_integer ra Initializing Block RAM Verilog Coding Example Hexadecimal To specify RAM initial contents initialize the signal describing the memory array in your Ve
390. lt style string Specify as follows attribute mult style of signal name entity name signal entity is auto block pipe block kcm csd lut pipe lut MULT STYLE Multiplier Style Verilog Syntax Example Place immediately before the module or signal declaration mult_style auto block pipe_block kcm csd lut pipe_lut MULT STYLE Multiplier Style XST Constraint File XCF Syntax Example One MODEL entity name mult_style auto block pipe block kom csd lut pipe lut MULT STYLE Multiplier Style XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name NET signal name mult style auto block pipe block kcm csd lut pipe lut END XST User Guide 316 www xilinx com UG627 v 11 3 September 16 2009 Chapter t XST Design Constraints XILINX MULT_STYLE Multiplier Style XST Command Line Syntax Example Define in the XST command line as follows xst run mult style auto block pipe block kem csd lut pipe lut The mult style command line option is not supported for Virtex 4 devices Virtex 5 devices or Spartan 3A DSP devices For those devices use use dsp48 MULT STYLE Multiplier Style ISE Design Suite Syntax Example Define in ISE Design Suite with Process Properties HDL Options Multiplier Style MUX STYLE Mux Style MUX STYLE Mux Style controls the way the macrogenerator implements the multiplexer macros MUX ST
391. lut module v_multipliers_4 clk A B MULT input clk input 17 0 A input 17 0 B output 35 0 MULT reg 35 0 MULT reg 17 0 a_in b_in wire 35 0 mult_res reg 35 0 pipe_regs 2 0 integer i assign mult_res a_in b_in always posedge clk begin a in lt A b in lt B pipe regs 2 lt mult res for i20 i 1 i i 1 pipe regs i lt pipe regs i 1 MULT lt pipe regs 0 end endmodule Multiply Adder Subtractors Hardware Description Language HDL Coding Techniques The Multiply Adder Subtractor macro is a complex macro consisting of several basic macros such as e Multipliers e Adder subtractors e Registers The recognition of this complex macro enables XST to implement it on dedicated DSP48 resources in the following devices e Virtex amp 4 e Virtex 5 Multiply Adder Subtractors in Virtex8 4 Devices and Virtex 5 Devices XST supports the registered version of this macro and can push up to 2 levels of input registers on multiplier inputs 1 register level on the Adder Subtractor input and 1 level of output register into the DSP48 block If the Carry In or Add Sub operation selectors are registered XST pushes these registers into the DSP48 In addition the multiplication operation could be registered as well XST can implement a multiply adder subtractor in a DSP48 block if its implementation requires only a single DSP48 resource If the macro exceeds the limits
392. m 433 XILINX Chapter 1 XST Behavioral Verilog Language Support Behavioral Verilog Constants By default constants in Verilog are assumed to be decimal integers They can be specified explicitly in binary octal decimal or hexadecimal by prefacing them with the appropriate syntax For example the following all represent the same value e 4 b1010 e 4012 e 4 d10 e Aha Behavioral Verilog Macros Verilog provides a way to define macros as shown in the following coding example define TESTEQ1 4 b1101 Later in the design code a reference to the defined macro is made as follows if request TESTEQ1 This is shown in the following coding example define myzero 0 assign mysig myzero The Verilog ifdef and endif constructs determine whether or not a macro is defined These constructs are used to define conditional compilation If the macro called out by the ifdef command has been defined that code is compiled If not the code following the else command is compiled The else is not required but endif must complete the conditional statement The ifdef and endif constructs are shown in the following coding example ifdef MYVAR module if_MYVAR_is_declared endmodule else module if_MYVAR_is_not_declared endmodule endif The Verilog Macros define command line option allows you to define or redefine Verilog macros This allows you to easily modify the design configu
393. mary input ports to either all sequential elements or the sequential elements driven by the given clock signal name e INPAD TO OUTPAD inpad to outpad optimizes the maximum delay from input pad to output pad throughout an entire design e MAX DELAY incorporates all previously mentioned constraints These constraints affect the entire design They apply only if no timing constraints are specified in the constraint file Set this value in ISE Design Suite in Process gt Properties gt Synthesis Options gt Global Optimization Goal glob opt Global Optimization Goal Syntax glob opt allclocknets offset in beforel loffset out afterlinpad to outpad max delay glob opt Global Optimization Goal Syntax Example xst run glob opt OFFSET OUT AFTER Optimizes the maximum delay from clock to output pad for the entire design Global Optimization Goal Domain Definitions The possible domains are shown in the following schematic e ALLCLOCKNETS register to register Identifies by default all paths from register to register on the same clock for all clocks in a design To take inter clock domain delays into account set Cross Clock Analysis cross clock analysis to yes e OFFSET IN BEFORE inpad to register Identifies all paths from all primary input ports to either all sequential elements or the sequential elements driven by the given clock signal name e OFFSET OUT AFTER register to outpad Similar to the previous constraint
394. mentation tools e xst srp The xst log file To save XST messages in a different log file for example wat chvhd 1og run the following command xst ifn stopwatch xst ofn watchvhd log To improve the readability of the stopwatch xst file especially if you use many options to run synthesis place each option with its value on a separate line Observe these rules e The first line contains only the run command without any options There are no blank lines in the middle of the command e Each line except the first one begins with a dash An error occurs if a leading space is inadvertently entered in the value field From 8 1i Service Pack 1 forward ISE Design Suite automatically strips leading spaces from a process value Accordingly the xst file written by ISE Design Suite is not affected by leading spaces If you hand edit the xst file and run XST from the command line manually delete any leading spaces For the previous command example stopwatch xst should look like the following run ifn watchvhd prj ifmt mixed top stopwatch ofn watchvhd ngc ofmt NGC p xc5vfx30t 2 ff324 opt mode Speed opt level 1 Synthesizing Verilog Designs Using Command Line Mode The following coding example shows the synthesis of a hierarchical Verilog design for a Virtex device using command line mode XST User Guide 482 www xilinx com UG627 v 11 3 September 16 2009 Cbipttr i1 XST Command Line Mode XILINX
395. mixed language project is language library file_name ext The following example shows how to invoke libraries in a mixed language project vhdl work my vhdll vhd verilog work my vlgl v vhdl my vhdl lib my vhdl2 vhd verilog my vlg lib my vlg2 v Each line specifies a single Hardware Description Language HDL design file e The first column specifies whether the HDL file is VHDL or Verilog e The second column specifies the logic library where the HDL is compiled The default logic library is work e The third column specifies the name of the HDL file VHDL and Verilog Boundary Rules in Mixed Language Projects The boundary between VHDL and Verilog is enforced at the design unit level A VHDL design can instantiate a Verilog module A Verilog design can instantiate a VHDL entity Instantiating a Verilog Module in a VHDL Design To instantiate a Verilog module in your VHDL design 1 Declare a VHDL component with the same name respecting case sensitivity as the Verilog module you want to instantiate If the Verilog module name is not all lower case use the case property to preserve the case of your Verilog module a In ISE Design Suite select Process gt Properties gt Synthesis Options gt Case gt Maintain or b Set the case command line option to maintain at the command line 2 Instantiate your Verilog component as if you were instantiating a VHDL component Using a VHDL configuration declaration you could attempt to
396. module or signal PRIORITY_EXTRACT Priority Encoder Extraction Propagation Rules Applies to the entity component module or signal to which it is attached PRIORITY_EXTRACT Priority Encoder Extraction Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it PRIORITY_EXTRACT Priority Encoder Extraction VHDL Syntax Example Declare as follows attribute priority_extract string Specify as follows attribute priority_extract of signal_name entity_name signal entity is yes no force The default is yes PRIORITY_EXTRACT Priority Encoder Extraction Verilog Syntax Example Place immediately before the module or signal declaration XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 321 XILINX nuit t XST Design Constraints PRIORITY_EXTRACT Priority Encoder Extraction XST Constraint File XCF Syntax Example One MODEL entity name priority_extract yes no true false force PRIORITY_EXTRACT Priority Encoder Extraction XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name NET signal name priority_extract yes no true false force END PRIORITY EXTRACT Priority Encoder Extraction XST Command Line Syntax Example Define in the XST command line as follows xst run priority extract yes no force The default is yes
397. module mux4 sel a b c d outmux input 1 0 sel input 1 0 a b c d output 1 0 outmux reg 1 0 outmux always sel or a or b or c or d begin if sel 1 if sel 0 outmux d else outmux C else if sel 0 outmux b else outmux a end endmodule Behavioral Verilog Case Statements Case statements perform a comparison to an expression to evaluate one of a number of parallel branches The Case statement evaluates the branches in the order they are written The first branch that evaluates to t rue is executed If none of the branches match the default branch is executed Do not use unsized integers in case statements Always size integers to a specific number of bits or results can be unpredictable Casez treats all z values in any bit position of the branch alternative as a don t care Casex treats all x and z values in any bit position of the branch alternative as a don t care The question mark can be used asa don t care in either the casez or casex case statements Behavioral Verilog Case Statement Coding Example The following coding example shows how a MUX can be described using a Case statement module mux4 sel a b c d outmux input 1 0 sel input 1 0 b cy d output 1 0 outmux reg 1 0 outmux always sel or a or b or c or d begin case sel 2 500 outmux 2 b01 outmux b 2 b10 outmux cr default outmux d endcase end endmodule a uo dw d
398. more information see Initializing RAM From an External File Use readmemb for binary and readmemh for hexadecimal representation To avoid the possible difference between XST and simulator behavior Xilinx recommends that you use index parameters in these system tasks See the following coding example readmemb rams 20c data ram 0 7 The remainder of the system tasks can be used to display information to your computer screen and log file during processing or to open and use a file during synthesis You must call these tasks from within initial blocks XST supports a subset of escape sequences specifically e Sh e sd So e b e Se e s Verilog display Syntax Example The following example shows the syntax for display that reports the value of a binary constant in decimal format parameter c 8 b00101010 initial begin Sdisplay The value of c is d c end The following information is written to the log file during the HDL Analysis phase Analyzing top module example c 8 500101010 foo v line 9 display The value of c is 42 Verilog Primitives XST supports certain gate level primitives The supported syntax is gate type instance name output inputs Following is a gate level primitive instantiations coding example and Ul out inl in2 bufifl U2 triout data trienable XST supports the following Verilog Gate Level primitives except for the following e Pulldown and pullup Unsupported
399. mp endmodule 8 Bit Shift Left Register With Positive Edge Clock Asynchronous Parallel Load Serial In and Serial Out Diagram SHIFT SI REG so 8 D ALOAD x10538 XST User Guide 60 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX 8 Bit Shift Left Register With Positive Edge Clock Asynchronous Parallel Load Serial In and Serial Out Pin Descriptions oms bee O ALOAD Asynchronous Parallel Load Active High Serial Output 8 Bit Shift Left Register With Positive Edge Clock Asynchronous Parallel Load Serial In and Serial Out VHDL Coding Example 8 bit Shift Left Register with Positive Edge Clock Asynchronous Parallel Load Serial In and Serial Out library ieee use ieee std logic 1164 a11 entity shift registers 6 is port C SI ALOAD in std logic D in std logic vector 7 downto 0 SO out std logic end shift registers 6 architecture archi of shift registers 6 is signal tmp std logic vector 7 downto 0 begin process C ALOAD D begin if ALOAD 1 then tmp lt D elsif C event and C 1 then tmp lt tmp 6 downto 0 amp SI end if end process SO lt tmp 7 end archi XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 61 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques 8 Bit Shift Left Register With Positive Edge Clock Asynchrono
400. mple In these examples the top block contains the instantiation of two AND gates described in and_one and and_two blocks XST generates two LUT2s and does not merge them For more information see Map Entity on a Single LUT LUT_MAP XST User Guide 226 www xilinx com UG627 v 11 3 September 16 2009 Chapter XST FPGA Optimization XILINX Passing an INIT Value Via the LUT_MAP Constraint VHDL Coding Example Mapping on LUTs via LUT MAP constraint library ieee use ieee std logic 1164 al1 entity and one is port A B in std logic REZ out std logic attribute LUT MAP string attribute LUT MAP of and one entity is yes end and one architecture beh of and one is begin REZ lt A and B end beh library ieee use ieee std logic 1164 all entity and two is port A B in std logic REZ out std logic attribute LUT MAP string attribute LUT MAP of and two entity is yes end and two architecture beh of and two is begin REZ lt A or B end beh library ieee use ieee std logic 1164 al1 entity inits rlocs 1 is port A B C in std logic REZ out std logic end inits rlocs 1 architecture beh of inits rlocs 1 is component and one port A B in std logic REA out std logic end component component and two port A B in std logic REZ out std logic end component signal tmp std logic begin inst and one and one port map A gt A B gt B REZ
401. multipliers_1 A B RES input 7 0 A input 3 0 B output 11 0 RES assign RES A B endmodule Sequential Complex Multipliers Hardware Description Language HDL Coding Techniques A sequential complex multiplier is a complex multiplier that requires four cycles to make a complete multiplication by accumulating intermediate results It requires one DSP block for implementation Multiplying two complex numbers A and B requires four cycles The first two first cycles compute Res_real A_real B_real A_imag B_imag The second two cycles compute Res_imag A_real B_imag A_imag B_real XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 101 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques While several templates could be used to describe the above functionality XST does not support using enum or integer types to describe the different DSP modes and store the enum values Instead Xilinx recommends a very regular template to ease XST inferencing This general accumulator template allows XST to inference a single DSP to perform the following operations e Load P lt Value Load P lt Value e Accumulate P lt P Value e Accumulate P lt P Value This template works with the following two control signals that perform the above four operations when combined e load e addsub Sequential Complex Multipliers Log File None Sequential Complex
402. multiply adder subtractors and MACs on DSP48 resources XST does not implement adders subtractors on DSP48 resources in auto mode To push adder subtractors into a DSP48 set the Use DSP48 USE DSP48 constraint or command line option value to yes XST performs automatic resource control in auto mode for all macros Use the DSP Utilization Ratio DSP UTILIZATION RATIO constraint in this mode to control available DSP48 resources for the synthesis By default XST tries to utilize all available DSP48 resources as much as possible If the number of user specified DSP slices exceeds the number of available DSP resources on the target FPGA device XST issues a warning and uses only available DSP resources on the chip for synthesis Disable automatic DSP resource management to see the number of DSPs that XST can potentially infer for a specific design To disable automatic DSP resource management set value 1 To deliver the best performance XST by default tries to infer and implement the maximum macro configuration including as many registers in the DSP48 as possible Use Keep KEEP to shape a macro in a specific way For example if your design has a multiplier with two register levels on each input place Keep KEEP constraints on the outputs of these registers to exclude the first register stage from the DSP48 DSP48 blocks do not support registers with Asynchronous Set Reset signals Since such registers cannot be absorbed by DSP48 this may l
403. n eee emen eene 332 SHREG EXTRACT Shift Register Extraction Architecture Support cece ee eeeeeeeeeeeeeee es 332 SHREG EXTRACT Shift Register Extraction Applicable Elements cccceeeeeseseeeeeeeeees 332 SHREG EXTRACT Shift Register Extraction Propagation Rules ssssseeeee 332 slice packing Slice Packing esee nennen I ATENE AESA P entente eret ee ent neon 333 USELOWSKEWLINES Use Low Skew Lines 334 XOR COLLAPSE XOR Collapsing ut cette tior rh Lei tonta vs eese ge isse es oo e tex ON Ree RE ERR UE 334 XOR COLLAPSE XOR Collapsing Architecture Support ssssssssssssee 334 XOR COLLAPSE XOR Collapsing Applicable Elements 334 XOR COLLAPSE XOR Collapsing Propagation Rule 334 Slice LUT FF Pairs Utilization Ratio SLICE UTILIZATION RATIO esee 335 Slice LUT FF Pairs Utilization Ratio SLICE UTILIZATION RATIO Architecture DUP POLE d HH 335 Slice LUT FF Pairs Utilization Ratio SLICE UTILIZATION RATIO Applicable isa EE 335 Slice LUT FF Pairs Utilization Ratio SLICE UTILIZATION RATIO Propagation oi HELD 335 Slice LUT FF Pairs Utilization Ratio Delta SLICE UTILIZATION RATIO MAXMARGIN 337 Slice LUT FF Pairs Utilization Ratio Delta SLICE UTILIZATION RATIO MAXMARGIN Architecture prport sz bt eetee teet RHET HC E FH SRS EES 337 Slice LUT FF Pairs Utilization Ratio Delta SLIC
404. n 3 For these devices XST uses the primitives shown in the following table XST User Guide 206 www xilinx com UG627 v 11 3 September 16 2009 Chapter XST FPGA Optimization XILINX Primitives Used by XST Single Port Synchronous Distributed Distributed Single Port RAM with M16X1S RAM16X2S RAM16XAS RAM positive clock edge M16X8S RAM32XIS RAM32X2S M32X4S RAM32X8S RAMO6AXIS M64X2S RAMI28X1S M16XI1S 1 RAM32XIS 1 M64XI1S 1 RAMI28XIS 1 Dual Port Synchronous Distributed Distributed Dual Port RAM with M16X1D RAM32X1D RAM64X1D RAM positive clock edge Dual Port Synchronous Distributed Distributed Dual Port RAM with M16X1D 1 RAM32XID 1 EE clock edge M64X1D_1 Single Port Synchronous Block RAM Port Synchronous Block RAM B4_Sn Dual Port Synchronous Block RAM MB4_Sm_Sn SESS w gt Single Port Synchronous Distributed Distributed Single Port RAM with RAM negative clock edge S lt Controlling Implementation of Inferred RAM To better control the implementation of the inferred RAM XST offers a way to control RAM inference and to select the generation of distributed RAM or block RAMs if possible The RAM Style RAM_STYLE attribute specifies that an inferred RAM be generated using e Block RAM if the value is block e Distributed RAM if the value is distributed Apply the RAM Style RAM_STYLE attribute to e A signal that defines the RAM or e The instance name of the RAM The
405. n etd Togi O out std logic end three st 1 architecture archi of three st 1l is begin process I T begin if T2 0 then O lt I else O lt Z end if end process end archi Tristate Description Using Combinatorial Always Block Verilog Coding Example Tristate Description Using Combinatorial Always Block module v three st 1 T I 0 input T I output O0 reg O always T or I begin if T O else O 1 bZ2 end endmodule Tristate Description Using Concurrent Assignment Diagram T Tristate Description Using Concurrent Assignment Pin Descriptions Output Enable active Low XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 35 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Tristate Description Using Concurrent Assignment VHDL Coding Example Tristate Description Using Concurrent Assignment library ieee use ieee std logic 1164 a1l1 entity three st 2 is port T in std logic L s in Std logic O out std logic end three st 2 architecture archi of three st 2 is begin O lt I when T 2 0 else i end archi Tristate Description Using Concurrent Assignment Verilog Coding Example Tristate Description Using Concurrent Assignment module v three st 2 T I 0 input T I output O0 assign O T I 1 bZ endmodule Counters Hardware Description Language HDL Coding Techn
406. n if SLOAD 1 then tmp lt D else tmp lt tmp 6 downto 0 amp SI end if end if end process SO lt tmp 7 end archi 8 Bit Shift Left Register With Positive Edge Clock Synchronous Parallel Load Serial In and Serial Out Verilog Coding Example Serial Out 8 bit Shift Left Register with Positive Edge Clock Synchronous Parallel Load Serial In and module v_shift_registers_7 C SLOAD SI D input C SI SLOAD input 7 0 D output SO reg 7 0 tmp always posedge C begin if SLOAD tmp lt D else tmp lt tmp 6 0 SI end assign SO tmp 7 endmodule Serial Out SO XILINX XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 63 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques 8 Bit Shift Left Shift Right Register With Positive Edge Clock Serial In and Parallel Out Diagram SI LEFT RIGHT C X10541 8 Bit Shift Left Shift Right Register With Positive Edge Clock Serial In and Parallel Out Pin Descriptions LEFT RIGHT Left right shift mode selector PO Parallel Output 8 Bit Shift Left Shift Right Register With Positive Edge Clock Serial In and Parallel Out VHDL Coding Example 8 bit Shift Left Shift Right Register with Positive Edge Clock Serial In and Parallel Out library ieee use ieee std logic 1164 a11 entity shift registers 8 is port C SI LEFT RIGHT
407. n may be useful when the design cannot be simplified by optimization and the complexity in number of P Terms is near the device capacity It may be that optimization trying to reduce the number of levels creates larger equations therefore increasing the number of P Terms and so preventing the design from fitting By validating this option the number of P Terms is not increased and the design fitting may be successful XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 239 XST User Guide 240 www xilinx com UG627 v 11 3 September 16 2009 XILINX Chapter 6 XST Design Constraints This chapter provides general information about XST design constraints as well as information about specific constraints For general information about XST design constraints see e List of XST Design Constraints e Setting Global Constraints and Options e VHDL Attribute Syntax e Verilog 2001 Attributes e XST Constraint File XCF Constraints Priority e XST Specific Non Timing Options e XST Command Line Only Options For information about specific XST design constraints see e XST General Constraints e XST HDL Constraints e XST FPGA Constraints Non Timing e XST CPLD Constraints Non Timing e XST Timing Constraints e XST Implementation Constraints e XST Supported Third Party Constraints Constraints help you meet your design goals and obtain the best implementation of your circuit Constraints control var
408. n the entity declaration part XST supports all types for generics including for example Integer e Boolean e String e Real e Std_logic_vector XST User Guide 380 www xilinx com UG627 v 11 3 September 16 2009 hipter XST VHDL Language Support XILINX An example of using generic parameters is setting the width of the design In VHDL describing circuits with generic ports has the advantage that the same component can be repeatedly instantiated with different values of generic ports as shown in the following coding example Describing Circuits With Generic Ports VHDL Coding Example Library IEEE use IEEE std logic 1164 all use IEEE std logic unsigned all entity addern is generic width integer 8 port A B in std logic vector width 1 downto 0 Y out std logic vector width 1 downto 0 end addern architecture bhv of addern is begin Y lt A B end bhv Library IEEE use IEEE std_logic_1164 all entity top is port X Y Z in std logic vector 12 downto 0 A B in std logic vector 4 downto 0 S out std logic vector 16 downto 0 end top architecture bhv of top is component addern generic width integer 8 port A B in std logic vector width 1 downto 0 Y out std logic vector width 1 downto 0 end component for all addern use entity work addern bhv signal Cl std logic vector 12 downto 0 signal C2 C3 std logic vector
409. name INST instance name bram map yes no true false END MAX FANOUT Max Fanout MAX FANOUT Max Fanout limits the fanout of nets or signals The value is an integer The default value varies depending on the targeted device family as shown in the following table MAX FANOUT is both a global and a local constraint MAX FANOUT Max Fanout Default Value Spartan 3 500 Spartan 3E Spartan 3A Spartan 3A DSP Virtex 4 500 Virtex 5 100000 One Hundred Thousand Large fanouts can cause routability problems XST tries to limit fanout by duplicating gates or by inserting buffers This limit is not a technology limit but a guide to XST It may happen that this limit is not exactly respected especially when this limit is small less than 30 In most cases fanout control is performed by duplicating the gate driving the net with a large fanout If the duplication cannot be performed buffers are inserted These buffers are protected against logic trimming at the implementation level by defining a Keep KEEP attribute in the NGC file XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 311 XILINX nuit t XST Design Constraints If the register replication option is set to no only buffers are used to control fanout of flip flops and latches MAX_FANOUT is global for the design but you can control maximum fanout independently for each entity or module or for given individual signals by using co
410. ncepts For more information see the IEEE Verilog HDL Reference Manual Behavioral Verilog For information about Behavioral Verilog see XST Behavioral Verilog Language Support Variable Part Selects Verilog 2001 adds the capability of using variables to select a group of bits from a vector A variable part select is defined by the starting point of its range and the width of the vector instead of being bounded by two explicit values The starting point of the part select can vary but the width of the part select remains constant Variable Part Select Symbols Symbol Meaning 0 plus The part select increases from the starting point Variable Part Select Verilog Coding Example reg 3 0 data reg 3 0 select a value from 0 to 7 wire 7 0 byte data select 8 Structural Verilog Features Structural Verilog descriptions assemble several blocks of code and allow the introduction of hierarchy in a design The basic concepts of hardware structure are e Component The building or basic block e Port A component I O connector e Signal Corresponds to a wire between components In Verilog a component is represented by a design module The module declaration provides the external view of the component It describes what can be seen from the outside including the component ports The module body provides an internal view It describes the behavior or the structure of the component The connections between compon
411. nds that you use Write First or No Change modes POWER Power Reduction Architecture Support Applies to Virtex 4 devices and Virtex 5 devices only Does not apply to any other FPGA devices Does not apply to CPLD devices POWER Power Reduction Applicable Elements Applies to e A component or entity VHDL e A model or label instance Verilog e A model or INST in model XCF e The entire design XST command line POWER Power Reduction Propagation Rules Applies to the entity component module or signal to which it is attached POWER Power Reduction Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it POWER Power Reduction VHDL Syntax Example Declare as follows attribute power string Specify as follows attribute power of component name entity name component entity is yes no The default is no POWER Power Reduction Verilog Syntax Example Place this constraint immediately before the module declaration or instantiation power yes no zi The default is no XST User Guide 306 www xilinx com UG627 v 11 3 September 16 2009 hapter i XST Design Constraints XILINX POWER Power Reduction XST Constraint File XCF Syntax Example MODEL entity name power yes no true false The default is false POWER Power Reduction XS
412. ne including the XST run and set commands and their options This chapter includes e Running XST in Command Line Mode e XST File Types in Command Line Mode e Temporary Files in Command Line Mode e Names With Spaces in Command Line Mode e Launching XST in Command Line Mode e Setting Up an XST Script e Synthesizing VHDL Designs Using Command Line Mode e Synthesizing Verilog Designs Using Command Line Mode e Synthesizing Mixed Designs Using Command Line Mode Running XST in Command Line Mode To run XST in command line mode e Ona workstation run xst e Ona PC run xst exe XST File Types in Command Line Mode XST generates the following files types in command line mode e Design output file NGC ngc This file is generated in the current output directory see the ofn option e Register Transfer Level RTL netlist for RTL and Technology Viewers ngr e Synthesis log file srp e Temporary files Temporary Files in Command Line Mode Temporary files are generated in the XST temp directory in command line mode By default the XST temp directory is e Workstations tmp e Windows The directory specified by either the TEMP or TMP environment variable Use set tmpdir directory to change the XST temp directory XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 475 XILINX int 13 XST Command Line Mode VHDL or Verilog compilation files are generated in the temp directory The default temp direct
413. ng Examples sissien osei edin ra eH eere 118 Dividers Hardware Description Language HDL Coding Techniques ccccccssceeeeeeeeenseeeeeeeeeeneanees 122 Dividers Eaa 122 Dividers Related Constraints ssssssssssessseeenee e eene ee I ene eee ener enne nennen enne 122 Dividers Coding Examples iier rhetor etre tho euet ede EEN endo EXPERS ER EUR Oen Eva keen doa gn 122 Resource Sharing Hardware Description Language HDL Coding Techniques ssesess 123 Resource Sharing Log dui m M 124 Resource Sharing Related Constraints iei eese eese esses vanessa eve nodo ae Nana sae un anon e unn neon aur aaa aan 124 Resource Sharing Coding Examples cciccscissiccccenssiescceasicissseessecessevssecsssensscesstevsscnsvenssscnsstessecsssunes 124 RAMs and ROMs Hardware Description Language HDL Coding Techmioues 126 XST User Guide 4 www xilinx com UG627 v 11 3 September 16 2009 XILINX RAMS atid ROMs E 127 RAMs and ROMs Related Constraints c cece cece cece ce ceceseeeeeeeee cesses e Henne eene n heh hen een ese eren 129 RAMS and ROMS Coding Examples ic ciccscssssiccccenssies eset eee erede epo ee etd aee da no e EKE AES e ERR EE Rae EERS 129 Initializing RAM Coding Pxamples ieeseesteeeses tees sae kv sas ssa ese ase ba euge as see ane usse nain neos Ease eu uE E EKxa 169 Initializing RAM Directly in Hardware Description Language HDL
414. ng Techniques RAMs and ROMs Hardware Description Language HDL Coding Techniques Pipelined Distributed RAM Hardware Description Language HDL Coding Techniques Finite State Machines FSMs Hardware Description Language HDL Coding Techniques Black Boxes Hardware Description Language HDL Coding Techniques XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 21 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Most sections include e A general description of the macro A sample log file e Constraints you can use to control the macro processing in XST e VHDL and Verilog coding examples including a schematic diagram and pin descriptions For more information see XST FPGA Optimization and XST CPLD Optimization For information on accessing the synthesis templates from ISE Design Suite see the ISE Design Suite Help Signed and Unsigned Support in XST When using Verilog or VHDL in XST some macros such as adders or counters can be implemented for signed and unsigned values To enable support for signed and unsigned values in Verilog enable Verilog 2001 as follows e In ISE Design Suite select Verilog 2001 as instructed in the Synthesis Options topic of ISE Design Suite Help or e Set the verilog2001 command line option to yes For VHDL depending on the operation and type of the operands you must include additional packages in your code For example to create an unsigned
415. nitial Values If the output port has an initial condition XST ties the unconnected output port to the explicitly defined initial condition According to the IEEE VHDL specification input ports cannot be left unconnected As a result XST issues an error message if an input port is not connected Even the open keyword is not sufficient for an unconnected input port VHDL Objects VHDL objects include e Signals e Variables e Constants Signals in VHDL Signals in VHDL can be declared in an architecture declarative part and used anywhere within the architecture Signals can also be declared in a block and used within that block Signals can be assigned by the assignment operator lt signal sigl std_logic sigl lt 1 Variables in VHDL Variables in VHDL are declared in a process or a subprogram and used within that process or that subprogram Variables can be assigned by the assignment operator variable varl std logic vector 7 downto 0 varl 01010011 Constants in VHDL Constants in VHDL can be declared in any declarative region and can be used within that region Their values cannot be changed once declared signal sigl std_logic_vector 5 downto 0 constant initO std logic vector 5 downto 0 010111 sigl lt init0 VHDL Operators Supported operators are listed in VHDL Operators This section provides examples of how to use each shift operator Operators VHDL Coding Example One
416. nnot use this constraint with it MOVE_FIRST_STAGE Move First Stage VHDL Syntax Example Declare as follows attribute move_first_stage string Specify as follows attribute move_first_stage of entity name signal name signal entity is yes no MOVE_FIRST_STAGE Move First Stage Verilog Syntax Example Place immediately before the module or signal declaration move_first_stage yes no MOVE FIRST STAGE Move First Stage XST Constraint File XCF Syntax Example One MODEL entity name move_first_stage yes no true false MOVE FIRST STAGE Move First Stage XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name NET primary clock signal move first stage yes no true false END MOVE FIRST STAGE Move First Stage XST Command Line Syntax Define in the XST command line as follows xst run move first stage yes no The default is yes MOVE FIRST STAGE Move First Stage ISE Design Suite Syntax Define in ISE Design Suite with Process gt Properties gt Xilinx Specific Options gt Move First Flip Flop Stage MOVE LAST STAGE Move Last Stage MOVE LAST STAGE Move Last Stage controls the retiming of registers with paths going to primary outputs Both Move Last Stage and Move First Stage MOVE FIRST STAGE relate to Register Balancing XST User Guide 314 www xilinx com UG627 v 11 3 September 16 2009 hapter t XST Design Constraints XILINX MOVE_LAS
417. nstraint File XCF Syntax Example Two ROM Extraction ROM EXTRACT must be set to yes in order to use ROM STYLE ROM Style BEGIN MODEL entity name NET signal name rom style auto block distributed END ROM STYLE ROM Style XST Command Line Syntax Example ROM Extraction ROM EXTRACT must be set to yes in order to use ROM STYLE ROM Style Define in the XST command line as follows xst run rom style auto block distributed The default is auto ROM STYLE ROM Style ISE Design Suite Syntax Example ROM Extraction ROM EXTRACT must be set to yes in order to use ROM STYLE ROM Style Define in ISE Design Suite with Process Properties HDL Options ROM Style SHREG EXTRACT Shift Register Extraction SHREG EXTRACT Shift Register Extraction enables or disables shift register macro inference SHREG EXTRACT values are e yes default no e true XCF only e false XCF only Enabling SHREG EXTRACT for FPGA devices results in the usage of dedicated hardware resources such as SRL16 and SRLC16 For more information see Shift Registers Hardware Description Language HDL Coding Techniques SHREG EXTRACT Shift Register Extraction Architecture Support Applies to all FPGA devices Does not apply to CPLD devices SHREG EXTRACT Shift Register Extraction Applicable Elements Applies to the entire design or to a design element or signal SHREG EXTRACT Shift Register Extraction Propagation
418. nstraint File XCF Syntax Examples MODEL entity name slice utilization ratio integer MODEL entity name slice utilization ratio integer MODEL entity name slice utilization ratio integerd XST interprets the integer values in the first two examples above as a percentage and in the last example as an absolute number of slices or FF LUT pairs The integer value range is 1 to 100 when percent is used or both percent and pound 4 are omitted There must be no space between the integer value and the percent or pound 4 characters You must surround the integer value and the percent and pound characters with double quotes because the percent and pound characters are special characters in the XST Constraint File XCF Slice LUT FF Pairs Utilization Ratio XST Command Line Syntax Examples Define in the XST command line as follows xst run slice utilization ratio integer xst run slice utilization ratio integer xst run slice utilization ratio integers XST interprets the integer values in the first two examples above as a percentage and in the last example as an absolute number of slices or FF LUT pairs The integer value range is 1 to 100 when percent is used or both percent and pound 4 are omitted Slice LUT FF Pairs Utilization Ratio ISE Design Suite Syntax Example Define in ISE Design Suite with Process Properties Synthesis Options Slice Utilization Ratio or Proces
419. nstraints If the actual net fanout is less than the MAX_FANOUT value XST behavior depends on how MAX_FANOUT is specified e If the value of MAX FANOUT is set in ISE Design Suite in the command line or is attached to a specific hierarchical block XST interprets its value as a guidance e If MAX FANOUT is attached to a specific net XST does not perform logic replication Putting MAX FANOUT on the net may prevent XST from having better timing optimization For example suppose that the critical path goes through the net which actual fanout is 80 and set Max Fanout value to 100 If MAX FANOUT is specified in ISE Design Suite XST may replicate it trying to improve timing If MAX FANOUT is attached to the net itself XST does not perform logic replication MAX FANOUT Max Fanout Architecture Support Applies to all FPGA devices Does not apply to CPLD devices MAX FANOUT Max Fanout Applicable Elements Applies to the entire design MAX FANOUT Max Fanout Propagation Rules Applies to the entity component module or signal to which it is attached MAX FANOUT Max Fanout Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it MAX FANOUT Max Fanout VHDL Syntax Example Declare as follows attribute max fanout string Specify as follows attribute max fanout of signal name entity name signal entity
420. nt with it USE CLOCK ENABLE Use Clock Enable VHDL Syntax Example Declare as follows attribute use clock enable string Specify as follows attribute use clock enable of entity name component name signal name instance_name entity component signal label is auto yes no USE CLOCK ENABLE Use Clock Enable Verilog Syntax Example Place Use Clock Enable immediately before the instance module or signal declaration use clock enable auto yes no zi USE CLOCK ENABLE Use Clock Enable XST Constraint File XCF Syntax Example One MODEL entity name use clock enable auto yes no true false XST User Guide 342 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST Design Constraints XILINX USE CLOCK ENABLE Use Clock Enable XST Constraint File XCF Syntax Example Two BEGIN MODEL entity_name NET signal_name use_clock_enable auto yes no true false END USE CLOCK ENABLE Use Clock Enable XST Constraint File XCF Syntax Example Three BEGIN MODEL entity name INST instance name use clock enable auto yes no true false END USE CLOCK ENABLE Use Clock Enable XST Command Line Syntax Example Define in the XST command line as follows xst run use clock enable auto yes no The default is auto USE CLOCK ENABLE Use Clock Enable ISE Design Suite Syntax Example Define in ISE Design Suite with Process Properties Xilinx Spe
421. ntax xst run pld xp yes no The default is yes pld xp XOR Preserve Syntax Example xst run pld xp no XOR macros are merged with surrounded logic XST Timing Constraints This section discusses how to apply XST timing constraints and gives information on specific constraints Applying Timing Constraints Apply XST supported timing constraints with e Global Optimization Goal glob opt e ISE Design SuiteProcess gt Properties gt Synthesis Options gt Global Optimization Goal e User Constraints File UCF XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 351 XILINX nuit t XST Design Constraints Applying Timing Constraints Using Global Optimization Goal Global Optimization Goal glob_opt allows you to apply the five global timing constraints e ALLCLOCKNETS e OFFSET_IN_BEFORE e OFFSET_OUT_AFTER INPAD TO OUTPAD MAX DELAY These constraints are applied globally to the entire design You cannot specify a value for these constraints since XST optimizes them for the best performance These constraints are overridden by constraints specified in the User Constraints File UCF Applying Timing Constraints Using the User Constraints File UCF The User Constraints File UCF allows you to specify timing constraints using native UCF syntax XST supports constraints such as e Timing Name TNM e Timegroup TIMEGRP e Period PERIOD e Timing Ignore TIG e From To FROM TO X
422. ntents of each branch of the if else statement are enclosed by begin and end statements e The begin statement is named with a unique qualifier generate if IF WIDTH lt 10 begin if name adder 4 IF WIDTH ul a b sum if end else begin else name subtractor IF WIDTH u2 a b sum if end endgenerate Behavioral Verilog Generate Case Statements Use a generate case statement inside a generate block to conditionally control which objects are generated Use a generate case statement when there are several conditions to be tested to determine what the generated code would be e Each test statement in a generate case is enclosed by begin and end statements The begin statement is named with a unique qualifier XST User Guide 436 www xilinx com UG627 v 11 3 September 16 2009 Chapter XST Behavioral Verilog Language Support XILINX Behavioral Verilog Generate Case Statement Coding Example In the following coding example of a generate case statement generate controls the type of adder that is instantiated generate case WIDTH dae begin casel_name adder WIDTH 8 x1 a b ci sum case CD case end 2 begin case2 name adder WIDTH 4 x2 a b ci sum case cO case end default begin d case name adder x3 a b ci sum case cO case end endcase endgenerate XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 437 XST User Guide 438 www xi
423. nthesis Report 448 XST FPGA Log File Advanced HDL Synthesis Report 448 XST FPGA Log File Low Level Synthesis atteintes eo etes esae na peu eine no euo ERR EERE 448 XST FPGA Log File Partition Report ex erret tet rte npe tanen tree ne Parere ESEE dente EA Rp EN 449 XSFFPGA L g Blende Geesse EE eege 449 Reducing the Size of the XST Log Pie 449 Use Message EE 449 IB erras 450 Use Silent MOC ERE g EAR SEENEN SEENEN m 450 FUG Specife Messages 450 Messages Hidden When Value is Set to hdl level and hdl and low Jewvels 451 Messages Hidden When Value is Set to low level or hdl and low levels 451 Macros in COMPETIT 451 XST Log File Examples eei erret rrr rta i8 ee er eS I Ha EE EEN 452 Chapter 12 XST Naming Conventions wcccsicssccccsiccsacsatsccsansticecsesssscevesssoadevadesasenvusdearedvessdecestasssceiedducdisessadcates 473 XOT Net Naming Conventions use pedea EE e ees toti CH eH ER eege ae 473 XST Instance Naming Conventions en etr deee terrena eene e a annu oa kn aa pane or aue EKETE audere aa eed aen a reen 473 XST Name Generation Contfol eee tree reto ho teer e a een re dos ne ee epe VU Tee Pha e Rd ee eua U ape Cu GENS 474 Chapter 13 XST Command Line Mode eec rented eee id tnit das IE ena eSI EN ERE See SKANSE ENEE Re eee HERREN Ee FREUE 475 Running XST in Command Line Mod sisi iiri eene orent state deese oe borea it
424. ntity top is Port clk rst in std_logic a in in std logic dout out std logic end top architecture Behavioral of top is signal arb onebit std logic 1 begin process clk rst begin if rst 1 then arb onebit 0 elsif clk event and clk 1 then arb onebit lt a in end if end process dout arb onebit end Behavioral Default Initial Values on Memory Elements in VHDL Because every memory element in a Xilinx FPGA device must come up in a known state in certain cases XST does not use IEEE standards for initial values In the Local Reset Global Reset VHDL Coding Example if signal arb onebit were not initialized to 1 one XST would assign it a default of 0 zero as its initial state In this case XST does not follow the IEEE standard where U is the default for std_logic This process of initialization is the same for both registers and RAMs Where possible XST adheres to the IEEE VHDL standard when initializing signal values If no initial values are supplied in the VHDL code XST uses the default values where possible as shown in the XST column in the following table bit 0 0 std_logic U 0 bit_vector 3 downto 0 0000 0000 std_logic_vector 3 downto 0 0000 0000 Boca XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 375 XILINX Chapter 7 XST VHDL Language Support Unconnected output ports default to the values shown in the XST column of VHDL I
425. nv integer ADDRA end if end if end process XST supports single and dual port block RAM with Byte wide Write Enable for VHDL and Verilog The RAM can be seen as a collection of equal size columns During a write cycle you separately control writing into each of these columns In the Multiple Write Statement method there is one separate write access statement including the description of the related write enable for each column The Single Write Statement method allows you to describe only one write access statement The write enables are described separately outside the main sequential process The two methods for describing column based RAM writes are shown in the following coding examples XST currently supports the second solution only Single Write Statement XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 155 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Multiple Write Statement VHDL Coding Example type ram_type is array SIZE 1 downto 0 of std_logic_vector 2 WIDTH 1 downto 0 signal RAM ram_type Cu process clk begin if posedge clk then if we 1 1 then RAM conv integer addr 2 WIDTH 1 downto WIDTH lt di 2 WIDTH 1 downto WIDTH end if if we 0 1 then RAM conv integer addr WIDTH 1 downto 0 lt di WIDTH 1 downto 0 end if do lt RAM conv integer addr end if end process Multiple Write Statement Verilog C
426. o CPLD devices USE SYNC RESET Use Synchronous Reset Applicable Elements Applies to e An entire design through the XST command line e A particular block entity architecture component Asignal representing a flip flop e An instance representing an instantiated flip flop USE SYNC RESET Use Synchronous Reset Propagation Rules Applies to the entity component module or signal to which it is attached USE SYNC RESET Use Synchronous Reset Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it USE SYNC RESET Use Synchronous Reset VHDL Syntax Example Declare as follows attribute use sync reset string Specify as follows attribute use sync reset of entity name component name signal name instance name entity component signal label is auto yes no USE SYNC RESET Use Synchronous Reset Verilog Syntax Example Place immediately before the module or signal declaration use sync reset auto yes no USE SYNC RESET Use Synchronous Reset XST Constraint File XCF Syntax Example One MODEL entity name use sync reset auto yes no true false USE SYNC RESET Use Synchronous Reset XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name NET signal name use sync reset auto yes no true false END XST User Guide UG627 v 1
427. o2 ram read add2 endmodule Dual Port RAM With One Enable Controlling Both Ports Diagram ADDRA ADDRB DOA EN Block WE n DOB D CLK 0581 Dual Port RAM With One Enable Controlling Both Ports Pin Descriptions Lom Been O aaa aoe EE EST XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 147 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Dual Port RAM With One Enable Controlling Both Ports VHDL Coding Example Dual Port RAM with One Enable Controlling Both Ports library ieee use ieee std logic 1164 all1 use ieee std logic unsigned all entity rams 13 is port clk in std logic en in std logic we in std logic addra in std logic vector 5 downto 0 addrb in std logic vector 5 downto 0 di in std logic vector 15 downto 0 doa out std logic vector 15 downto 0 dob out std logic vector 15 downto 0 end rams 13 architecture syn of rams 13 is type ram type is array 63 downto 0 of std logic vector 15 downto 0 signal RAM ram type signal read addra std logic vector 5 downto 0 signal read addrb std logic vector 5 downto 0 begin process clk begin if clk event and clk 1 then if en 1 then if we 1 then RAM conv integer addra lt di end if read addra addra read addrb lt addrb end if end if end process doa lt RAM conv integer read addra dob lt R
428. oding auto one hot compact sequential gray johnson speedl user The default is auto FSM ENCODING FSM Encoding Algorithm ISE Design Suite Syntax Example Define in ISE Design Suite with Process gt Properties gt HDL Options gt FSM Encoding Algorithm These options are e Ifthe FSM Encoding Algorithm menu is set to None and sm extract is set to no sm encoding has no influence on the synthesis e Inall other cases f sm extract is set to yes and sm encoding is set to the value selected in the menu For more information see Automatic FSM Extraction F5M EXTRACT MUX EXTRACT Mux Extraction MUX EXTRACT Mux Extraction enables or disables multiplexer macro inference MUX EXTRACT values are yes no force e true XCF only e false XCF only By default multiplexer inference is enabled yes For each identified multiplexer description based on some internal decision rules XST actually creates a macro or optimizes it with the rest of the logic The force value overrides those decision rules and forces XST to create the MUX macro MUX EXTRACT Mux Extraction Architecture Support Architecture independent MUX EXTRACT Mux Extraction Applicable Elements Applies to the entire design or to an entity component module or signal MUX EXTRACT Mux Extraction Propagation Rules Applies to the entity component module or signal to which it is attached MUX EXTRACT Mux Extract
429. oding Example reg 2 DI WIDTH 1 0 RAM SIZE 1 0 always posedge clk begin if we 1 then RAM addr 2 WIDTH 1 WIDTH lt di 2 WIDTH 1 WIDTH end if if we 0 then RAM addr WIDTH 1 0 lt di WIDTH 1 0 end if do lt RAM addr end XST User Guide 156 www xilinx com UG627 v 11 3 September 16 2009 Chipter1 XST Hardware Description Language HDL Coding Techniques XILINX Single Write Statement VHDL Coding Example type ram_type is array SIZE 1 downto 0 of std_logic_vector 2 WIDTH 1 downto 0 signal RAM ram_type signal di0 dil std logic vector WIDTH 1 downto 0 Ces Write enables described outside main sequential process process we di addr begin if we 1 1 then dil lt di 2 WIDTH 1 downto WIDTH else dil lt RAM conv integer addr 2 WIDTH 1 downto WIDTH end if if we 0 1 then di0 lt di WIDTH 1 downto 0 else di0 lt RAM conv_integer addr WIDTH 1 downto 0 end if end process process clk begin if posedge clk then if en 1 then RAM conv integer addr lt dil amp di0 single write access statement do lt RAM conv integer addr end if end if end process Single Write Statement Verilog Coding Example reg 2 DI WIDTH 1 0 RAM SIZE 1 0 reg DI WIDTH 1 0 aid dil always 8 we or di or addr begin if we 1 dil di 2 DI WIDTH 1 1 DI WIDTH else dil RAM addr 2 DI WIDTH 1 1 DI
430. of Logic 3 Source MACHINE current state FFd3 FF Destination sixty msbcount qoutsig 3 FF Source Clock CLK rising Destination Clock CLK rising Data Path MACHINE current state FFd3 to sixty msbcount qoutsig 3 Gate Net Cell in out fanout Delay Delay Logical Name Net Name FDC C Q 8 0 272 0 642 MACHINE current_state_FFd3 MACHINE current_state_FFd3 LUT3 10 gt 0 3 0 147 0 541 Ker81 clkenable LUT4_D I1 gt 0 1 0 147 0 451 sixty msbce sixty msbce LUT3 12 50 1 0 147 0 000 sixty msbcount qoutsig_3_rstpot FDC D 0 297 sixty msbcount qoutsig 3 Total 2 644ns 1 010ns logic 1 634ns route 38 2 logic 61 8 route XST User Guide 218 www xilinx com UG627 v 11 3 September 16 2009 Chapter t XST FPGA Optimization XILINX Timing Report Timing Summary Section The Timing Summary section of the Timing Report summarizes the timing paths for all four domains e The path from any clock to any clock in the design inimum period 7 523ns Maximum Frequency 132 926MHz e The maximum path from all primary inputs to the sequential elements inimum input arrival time before clock 8 945ns e The maximum path from the sequential elements to all primary outputs aximum output required time before clock 14 220ns e The maximum path from inputs to outputs aximum combinational path delay 10 899ns If there is no path in the domain No path found is printed instead of the value Timing Report Timing Deta
431. of the entire design This feature was implemented for Verilog and XST Constraint File XCF in order to have a VHDL like support where BOX TYPE can be applied to a component BOX TYPE BoxType Architecture Support Architecture independent XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 265 XILINX nuit t XST Design Constraints BOX_TYPE BoxType Applicable Elements Applies to the following design elements e VHDL component entity e Verilog module instance e XST Constraint File XCF model instance BOX_TYPE BoxType Propagation Rules Applies to the design element to which it is attached BOX_TYPE BoxType Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it BOX_TYPE BoxType VHDL Syntax Example Declare as follows attribute box_type string Specify as follows attribute box_type of component_name entity_name component entity is primitive black_box user_black_box BOX_TYPE BoxType Verilog Syntax Example Place immediately before the instantiation box_type primitive black_box user_black_box BOX TYPE BoxType XST Constraint File XCF Syntax Example One MODEL entity name box_type primitive block box user_black_box BOX TYPE BoxType XST Constraint File XCF Syntax Example Two BEGIN MODEL entity_name INS
432. of these values These same signals are also assigned in the synchronous part that is the last branch of the if else statement The clock signal condition is the condition of the last branch of the if else statement 8 Bit Register Using an Always Block Behavioral Verilog Coding Example module seql DI CLK DO input 7 0 DI input CLK output 7 0 DO reg 7 0 DO always posedge CLK DO lt DI 8 Bit Register with Asynchronous Reset High True Using an Always Block Behavioral Verilog Coding Example module EXAMPLE DI CLK RST DO input 7 0 DI input CLK RST output 7 0 DO reg 7 0 DO always posedge CLK or posedge RST if RST 1 bl DO lt 8 b00000000 else DO lt DI endmodule 8 Bit Counter with Asynchronous Reset Low True Using an Always Block Behavioral Verilog Coding Example module seq2 CLK RST DO input CLK RST output 7 0 DO reg 7 0 DO always 8 posedge CLK or posedge RST if RST 1 b1 DO lt 8 b00000000 else DO lt DO 8 b00000001 endmodule XST User Guide 428 www xilinx com UG627 v 11 3 September 16 2009 thipter t XST Behavioral Verilog Language Support XILINX Behavioral Verilog Assign and Deassign Statements Assign and deassign statements are supported within simple templates Behavioral Verilog Assign and Deassign Statements General Template Coding Example module assig RST SELECT STATE CLOCK DATA
433. og directory XST User Guide 484 www xilinx com UG627 v 11 3 September 16 2009 Cbipttr i1 XST Command Line Mode XILINX To synthesize the design which is now represented by six VHDL files and one Verilog file create a project To create a project file place a list of VHDL files preceded by keyword vhd1 and a list of Verilog files preceded by keyword verilog ina separate file The order of the files is not important XST recognizes the hierarchy and compiles Hardware Description Language HDL files in the correct order Running XST in Script Mode Mixed Language It can be tedious to enter XST commands directly into the XST shell especially when you have to specify several options and execute the same command several times To run XST in script mode 1 Opena new file called stopwatch xst in the current directory Put the previously executed XST shell command into this file and save it run ifn watchver prj ifmt mixed top stopwatch ofn watchver ngc ofmt NGC p xc5vfx30t 2 ff324 opt mode Speed opt level 1 2 From the tcsh or other shell enter the following command to begin synthesis xst ifn stopwatch xst During this run XST creates the following files e watchver ngc an NGC file ready for the implementation tools e xst srp the xst script log file To save XST messages to a different log file for example wat chver 109 run xst ifn stopwatch xst ofn watchver log To improve the readability of the stopwat
434. ogic en in std logic addr in std logic vector 5 downto 0 data out std logic vector 19 downto 0 end rams 21a architecture syn of rams 21a is type rom type is array 63 downto 0 of std logic vector 19 downto 0 signal ROM rom type X 0200A X 00300 X 08101 X 04000 X 08601 X 0233A X 00300 X 08602 X 02310 X 0203B X 08300 X 04002 X 08201 X O00500 X 04001 X 02500 X 00340 X 00241 X 04002 X 08300 X 08201 X 00500 X O08101 X 00602 X 04003 X 0241E X 00301 X 00102 X 02122 x 02021 X 00301 X D0O102 X 02222 X 04001 X 00342 X 0232B X 00900 X 00302 X 00102 X 04002 X 00900 X 08201 X 02023 X O00303 X 02433 X 00301 X 04004 X O0301 X 00102 X 02137 X 02036 X 00301 X 00102 X 02237 x 04004 X 00304 X 04040 X 02500 X 02500 X 02500 X DOS3 0D X 02341 X D8201 X 0400D begin process clk begin if clk event and clk 1 then if en 1 then data lt ROM conv integer addr end if end if end process end syn XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 179 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques ROM With Registered Output VHDL Coding Example Two ROMs Using Block RAM Resources VHDL code for a ROM with registered output template 2 library ieee use ieee std logic 1164 all use ieee std logic unsigned all ent
435. ogic unsigned all entity rams 14 is port clk in std logic ena in std_logic enb in std_logic wea t in std logico addra in std logic vector 5 downto 0 addrb in std logic vector 5 downto 0 dia in std logic vector 15 downto 0 doa out std logic vector 15 downto 0 dob out std logic vector 15 downto 0 end rams 14 architecture syn of rams 14 is type ram type is array 63 downto 0 of std logic vector 15 downto 0 signal RAM ram type signal read addra std logic vector 5 downto 0 signal read addrb std logic vector 5 downto 0 begin process clk begin if clk event and clk 1 then if ena 1 then if wea 1 then RAM conv integer addra dia end if read addra addra end if if enb 1 then read addrb addrb end if end if end process doa lt RAM conv integer read addra dob lt RAM conv integer read addrb end syn XST User Guide 150 www xilinx com UG627 v 11 3 September 16 2009 hapter 1 XST Hardware Description Language HDL Coding Techniques XILINX Dual Port RAM With Enable on Each Port Verilog Coding Example Dual Port RAM with Enable on Each Port ii module v rams 14 clk ena enb wea addra addrb dia doa dob input elk input ena input enb input wea input 5 0 addra input 5 0 addrb input 15 0 dia output 15 0 doa output 15 0 dob reg 15 0 ram 63 0 reg 5 0 read_
436. ollowing examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it SIGNAL_ENCODING Signal Encoding VHDL Syntax Example Declare as follows attribute signal_encoding string Specify as follows attribute signal_encoding of component_name signal_name entity_name label_name component signal entity label is auto one hot user The default is auto SIGNAL_ENCODING Signal Encoding Verilog Syntax Example Place immediately before the signal declaration signal_encoding auto one hot user The default is auto SIGNAL_ENCODING Signal Encoding XST Constraint File XCF Syntax Example One MODEL entity name signal encoding auto one hot user SIGNAL ENCODING Signal Encoding XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name NET signal name signal encoding auto one hot user END SIGNAL ENCODING Signal Encoding XST Command Line Syntax Example Define in the XST command line as follows signal encoding auto one hot user The default is auto XST FPGA Constraints Non Timing In many cases a particular constraint can be applied globally to an entire entity or model or alternatively it can be applied locally to individual signals nets or instances See XST Specific Non Timing Options and XST Specific Non Timing Options XST Command Line Only for valid con
437. omes a hierarchical block as shown below yes Merged in the design logic Very small macros such as 2 bit adders and 4 bit multiplexers are always merged independent of the Macro Preserve or Flatten Hierarchy options pld mp Macro Preserve Architecture Support Applies to all CPLD devices Does not apply to FPGA devices pld mp Macro Preserve Applicable Elements Applies to the entire design pld mp Macro Preserve Propagation Rules Not applicable Set this value in ISE Design Suite in Process gt Properties gt Xilinx Specific Options gt Macro Preserve pld_mp Macro Preserve Syntax xst run pld mp yes no The default is yes pld_mp Macro Preserve Syntax Example xst run pld mp no Macros are rejected and generated by HDL synthesizer XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 349 XILINX nuit t XST Design Constraints NOREDUCE No Reduce NOREDUCE No Reduce e Prevents minimization of redundant logic terms that are typically included in a design to avoid logic hazards or race conditions e Identifies the output node of a combinatorial feedback loop to ensure correct mapping For more information see NOREDUCE in the Constraints Guide wysiwyg WYSIWYG wysiwyg WYSIWYG makes a netlist reflect the user specification as closely as possible That is all the nodes declared in the Hardware Description Language HDL design are preserved If WYSIWYG mod
438. on Applicable Elements 290 MUX EXTRACT Mux Extraction Propagation Rules ssssssssssseee ees 290 REGISTER POWERUP Register Power Up 291 REGISTER POWERUP Register Power Up Architecture Support 291 REGISTER POWERUP Register Power Up Applicable Hlemente 291 REGISTER POWERUP Register Power Up Propagation Rules sssseeee 291 RESOURCE SHARING Resource Sharing eene 292 RESOURCE SHARING Resource Sharing Architecture Support ssssseeee 292 RESOURCE SHARING Resource Sharing Applicable Elements 292 RESOURCE SHARING Resource Sharing Propagation Rules sss 293 SAFE RECOVERY STATE Safe Recovery State enero b eese saeva notes iie a eat EEE EEN 293 XST User Guide 8 www xilinx com UG627 v 11 3 September 16 2009 XILINX SAFE RECOVERY STATE Safe Recovery State Architecture Support ssssesstrrsssssessreses 294 SAFE RECOVERY STATE Safe Recovery State Applicable Elements nssssesetietrsreeert este 294 SAFE RECOVERY STATE Safe Recovery State Propagation Rules sese 294 SAFE IMPLEMENTATION Safe Implementatton eee 294 SAFE IMPLEMENTATION Safe Implementation Architecture Support 294 SAFE IMPLEMENTATION Safe Implementation Applicable Elements esses 294 SAFE IMPLEMENTATION Safe Implementation Propagation Rules sees 295 SIGNAL ENCODING Sigrial Bricoding eeccee eroe Ft een ne nonet eid anoo ond noi nu n un du eina geed 295 SIGNAL ENCODING
439. on Specify formal and effective port names in the port map e All parameters are passed at instantiation even if they are unchanged e The parameter override is named and not ordered The parameter override occurs through instantiation and not through defparams Correct Use of Parameter Override Coding Example ff init 2 b01 ul sel sel din din dout dout Correct Use of Parameter Override Coding Example The following example is not accepted by XST ff ul sel sel din din dout dout defparam ul init 2 b01 Port Mapping in Mixed Language Projects Port Mapping in mixed language projects includes e VHDL in Verilog Port Mapping e Verilog in VHDL Port Mapping e VHDL in Mixed Language Port Mapping e Verilog in Mixed Language Port Mapping VHDL in Verilog Port Mapping For VHDL entities instantiated in Verilog designs XST supports the following port types in out e inout XST does not support VHDL buffer and linkage ports Verilog in VHDL Port Mapping For Verilog modules instantiated in VHDL designs XST supports the following port types e input e output e inout XST does not support connection to bi directional pass options in Verilog XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 441 XILINX Chapter tl XST Mixed Language Support XST does not support unnamed Verilog ports for mixed language boundaries Use an equivalent component declaration for connectin
440. on individual objects for example module instance net e Set the following synthesis constraints Full Case FULL CASE Parallel Case PARALLEL CASE Verilog 2001 Attributes Syntax Verilog 2001 attributes are bounded by the asterisk character and use the following syntax attribute name attribute value where The attribute precedes the signal module or instance declaration to which it refers The attribute value is a string No integer or scalar values are allowed e The attribute value is between quotes e The default is 1 e attribute name isthesameas attribute name 1 Si Verilog 2001 Attributes Syntax Example One clock buffer IBUFG input CLK Verilog 2001 Attributes Syntax Example Two INIT 0000 reg 3 0 d out Verilog 2001 Attributes Syntax Example Three always current state or reset begin parallel case full case case current state Verilog 2001 Attributes Syntax Example Four mult style pipe lut MULT my mult a b c XST User Guide 250 www xilinx com UG627 v 11 3 September 16 2009 Chapter t XST Design Constraints XILINX Verilog 2001 Limitations Verilog 2001 attributes are not supported for e Signal declarations e Statements e Port connections e Expression operators Verilog 2001 Meta Comments Constraints can also be specified in Verilog code using meta comments The Verilog 2001 format is the
441. on the register and is independent of any local reset signal arb onebit std logic 0 signal arb priority std logic vector 3 downto 0 1011 You can also assign a set reset value to a register in behavioral VHDL code Assign a value to a register when the register reset line goes to the appropriate value See the following coding example process clk rst begin if rst 1 then arb onebit lt 0 end if end process When you set the initial value of a variable in the behavioral code it is implemented in the design as a flip flop whose output can be controlled by a local reset As such it is carried in the NGC file as an FDP or FDC flip flop XST User Guide 374 www xilinx com UG627 v 11 3 September 16 2009 hipter XST VHDL Language Support XILINX VHDL Local Reset Global Reset Local reset is independent of global reset Registers controlled by a local reset may be set to a different value from registers whose value is only reset at global reset power up In the Local Reset Global Reset VHDL Coding Example the register arb_onebit is set to 1 at global reset but a pulse on the local reset rst can change its value to 0 Local Reset Global Reset VHDL Coding Example The following coding example sets the initial value on the register output to 1 one at initial power up but since this is dependent upon a local reset the value changes to 0 zero whenever the local set reset is activated e
442. oop readline MY FILE MY LINE read MY LINE MY DATA end loop XST rejects the design and issues the following error message Line MY LINE has not enough elements for target MY DATA To fix the problem add exit when endfile MY FILE to the while loop as shown in the following coding example while not endfile MY FILE loop readline MY FILE MY LINE exit when endfile MY FILE read MY LINE MY DATA end loop VHDL Data Types This section discusses VHDL Data Types including e Accepted VHDL Data Types e VHDL Overloaded Data Types e VHDL Multi Dimensional Array Types Accepted VHDL Data Types XST accepts the following VHDL data types e VHDL Enumerated Types e VHDL User Defined Enumerated Types e VHDL Bit Vector Types e VHDL Integer Types e VHDL Predefined Types e VHDL STD LOGIC 1164 IEEE Types XST User Guide 370 www xilinx com UG627 v 11 3 September 16 2009 hipter XST VHDL Language Support XILINX VHDL Enumerated Types nearing o o Fo o ooa feee E ew jene EE Dee meweseweaysr ws mewesewenyer Treated identically to 0 weak high Treated identically to 1 Po high impedance Treated as high impedance K VHDL User Defined Enumerated Types type COLOR is RED GREEN YELLOW VHDL Bit Vector Types e BIT VECTOR STD LOGIC VECTOR Unconstrained types types whose length is not defined are
443. oop wait until CLK EVENT and CLK 1 exit SEQ LOOP when RST 1 RESULT lt DATA wait until CLK EVENT and CLK 1 exit SEQ LOOP when RST 1 RESULT DATA2 wait until CLK EVENT and CLK 1 exit SEQ LOOP when RST 1 RESULT lt DATA3 wait until CLK EVENT and CLK 1 exit SEQ LOOP when RST 1 RESULT lt DATA4 end loop end process end ARCH XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 391 XILINX Chapter 7 XST VHDL Language Support VHDL Functions and Procedures The declaration of a function or a procedure in VHDL provides a mechanism for handling blocks used multiple times in a design Functions and procedures can be declared in the declarative part of an entity in an architecture or in packages The heading part contains Input parameters for functions and input e Output and inout parameters for procedures These parameters can be unconstrained They are not constrained to a given bound The content is similar to the combinatorial process content Resolution functions are not supported except the one defined in the IEEE std 1ogic 1164 package Function Declaration and Function Call VHDL Coding Example The following VHDL coding example shows a function declared within a package The ADD function declared here is a single bit adder This function is called four times with the proper parameters in the archite
444. orts e Both C style and Verilog style meta comments Translate Off TRANSLATE OFF and Translate On TRANSLATE ON constraints synthesis translate on synthesis translate off e Parallel Case PARALLEL CASE constraints synthesis parallel case full case synthesis parallel case synthesis full case e Constraints on individual objects The general syntax is synthesis attribute of ObjectName is AttributeValue XST User Guide 410 www xilinx com UG627 v 11 3 September 16 2009 Chipter t XST Verilog Language Support XILINX Verilog Meta Comments Coding Example synthesis attribute BLOC of u123 is R11C1 S0 synthesis attribute HUSET ul MY_SET synthesis attribute fsm_extract of State2 is yes synthesis attribute fsm_encoding of State2 is gray Verilog Constructs Supported in XST This section discusses Verilog Constructs Supported in XST including e Constants e Data Types e Continuous Assignments e Procedural Assignments Design Hierarchies Compiler Directives Note XST does not allow underscores as the first character of signal names for example _DATA_1 Verilog Constants Supported in XST Constant Supported Unsupported Integer Constants Supported Real Constants Supported Strings Constants Unsupported Verilog Data Types Supported in XST All Verilog data types are supported in XST except as noted below e Net types triO0 tril and trireg are unsupported e
445. ory is the xst subdirectory of the current directory Xilinx recommends that you clean the XST temp directory regularly The temp directory contains the files resulting from the compilation of all VHDL and Verilog files during all XST sessions Eventually the number of files stored in the temp directory may severely impact CPU performance XST does not automatically clean the temp directory Names With Spaces in Command Line Mode XST supports file and directory names with spaces in command line mode Enclose file or directory names containing spaces in double quotes C my project The command line syntax for options supporting multiple directories sd vlgincdir has changed Enclose multiple directories in braces vlgincdir C my project C temp In previous releases multiple directories were included in double quotes XST still supports this convention provided directory names do not contain spaces Xilinx recommends that you change existing scripts to the new syntax Launching XST in Command Line Mode You can launch XST in command line mode using e The XST shell e A script file Launching XST in Command Line Mode Using the XST Shell Type xst to enter directly into an XST shell Enter your commands and execute them To run synthesis specify a complete command with all required options XST does not accept a mode where you can first enter set option_1 then set option_2 and then enter run Since all options are set at th
446. ositive Reset type asynchronous Reset State sl Power Up State sl Encoding automatic Implementation LUT Found 1 bit register for signal lt outp gt Summary inferred 1 Finite State Machine s inferred 1 D type flip flop s Unit fsm 1 synthesized HDL Synthesis Report Macro Statistics Registers td 1 bit register ed Advanced Registered AddSub inference Analyzing FSM FSM 0 for best encoding Optimizing FSM state FSM 0 on signal state 1 2 with gray encoding sl 00 s2 01 s3 x s4 10 HDL Synthesis Report Macro Statistics FSMs 1 Finite State Machine FSM Related Constraints e Automatic Finite State Machine FSM Extraction FSM_EXTRACT e Finite State Machine FSM Style FSM_STYLE e Finite State Machine FSM Encoding Algorithm FSM_ENCODING e Enumerated Encoding ENUM_ENCODING e Safe Implementation SAFE IMPLEMENTATION e Safe Recovery State SAFE RECOVERY STATE XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 193 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Finite State Machine FSM Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip Finite State Machine FSM With One Process Pin Descriptions homm lee Finite State Machine FSM With One Process VHDL Coding Example State Machine with a singl
447. ot infer a logical shifter for this example as the value is not incremented by 1 for each consequent binary value of the selector module v logical shifters 3 DI SEL SO input 7 0 DI input 1 0 SEL output 7 0 SO reg 7 0 SO always DI or SEL begin case SEL 2 b00 SO DI 2 b01 SO DI lt lt 1 2 bl0 SO DI lt lt 3 default SO DI lt lt 2 endcase end endmodule XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 85 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Arithmetic Operators Hardware Description Language HDL Coding Techniques XST supports the following arithmetic operators e Adders with Carry In Carry Out Carry In Out e Subtractors e Adders Subtractors e Comparators f lt amp gt gt e Multipliers e Dividers XST supports the following for signed and unsigned operators e Adders e Subtractors e Comparators e Multipliers For more information on signed and unsigned operators support in VHDL see Registers Hardware Description Language HDL Coding Techniques XST performs resource sharing for e Adders e Subtractors e Adders subtractors e Multipliers XST User Guide 86 www xilinx com UG627 v 11 3 September 16 2009 lhapter 3 XST Hardware Description Language HDL Coding Techniques XILINX Arithmetic Operators Log File The XST log file reports the type and siz
448. ough an if else statement For example XST rejects the following design module dflop RST SET input RST input SET input CLOCK input DATA_IN output STATE reg STATE always RST or SET case RST SET 2 b00 assign STATE 2 b01 assign STATE 2 b10 assign STATE block bl 1 b0 1 b0 1 bl 2 b11 deassign STATE endcase always posedge CLOCK begin block b2 STATE lt DATA IN end endmodule STATE CLOCK DATA_IN Cannot Assign Bit Part Select of Signal Through Assign Deassign Statement You cannot assign a bit part select of a signal through an assign deassign statement For example XST rejects the following design module assig RST SELECT STATE CLOCK DATA_IN input RST input SELECT input CLOCK input 0 7 DATA_IN output 0 7 STATE reg 0 7 STATE always RST if RST begin block bl assign STATE 0 7 8 b0 end else begin deassign STATE 0 7 end always posedge CLOCK block b2 lt DATA_IN 0 3 lt DATA_IN 4 7 begin if SELECT STATE 0 3 else STATE 4 7 end 430 www xilinx com XST User Guide UG627 v 11 3 September 16 2009 thipter t XST Behavioral Verilog Language Support XILINX Behavioral Verilog Assignment Extension Past 32 Bits If the expression on the left hand side of an assignment is wider than the expression on the right hand side the left hand si
449. p For more information see TNM NET in the Constraints Guide TNM NET Timing Name on a Net Syntax Examples NET netname TNM NET predefined group identifier TIMEGRP Timegroup TIMEGRP Timegroup is a basic grouping constraint In addition to naming groups using the TNM identifier you can also define groups in terms of other groups You can create a group that is a combination of existing groups by defining a TIMEGRP constraint Place TIMEGRP constraints in an XST Constraint File XCF or a Netlist Constraints File NCF Use TIMEGRP attributes to create groups using the following methods e Combining multiple groups into one e Defining flip flop subgroups by clock sense For more information see TIMEGRP in the Constraints Guide TIMEGRP Timegroup Syntax Examples TIMEGRP newgroup existing_grpl existing grp2 existing_grp3 TIG Timing Ignore TIG Timing Ignore causes all paths going through a specific net to be ignored for timing analyses and optimization purposes TIG can be applied to the name of the signal affected For more information see TIG in the Constraints Guide XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 357 XILINX nuit t XST Design Constraints TIG Timing Ignore XST Constraint File XCF Syntax Example NET net name TIG XST Implementation Constraints Implementation constraints control placement and routing They are not directly used by XST but are propag
450. p Counter With Asynchronous Reset Pin Descriptions Positive Edge Clock Asynchronous Reset Active High XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 37 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques 4 Bit Unsigned Up Counter With Asynchronous Reset VHDL Coding Example 4 bit unsigned up counter with an asynchronous reset library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity counters 1 is port C CLR in std logic Q out std logic vector 3 downto 0 end counters 1 architecture archi of counters 1l is signal tmp std logic vector 3 downto 0 begin process C CLR begin if CLR 1 then tmp 0000 elsif C event and C 1 then tmp tmp 1 end if end process Q lt tmp end archi 4 Bit Unsigned Up Counter With Asynchronous Reset Verilog Coding Example 4 bit unsigned up counter with an asynchronous reset module v counters 1 C CLR Q input C CLR output 3 0 Q reg 3 0 tmp always 8 posedge C or posedge CLR begin if CLR tmp lt 4 b0000 else tmp lt tmp 1 bl end assign Q tmp endmodule 4 Bit Unsigned Down Counter With Synchronous Set Diagram S COUNT 4 X10527 XST User Guide 38 www xilinx com UG627 v 11 3 September 16 2009 Chipter XST Hardware Description Language HDL Coding Techniques XILINX 4 Bit Unsigned Down Co
451. perators Related Constant 87 Adders Subtractors and Adders Subtractors Hardware Description Language HDL Coding Techniques m EE 87 Adders Subtractors and Adders Subtractors Log Pe 88 Adders Subtractors and Adders Subtractors Related Constraints e 88 Adders Subtractors and Adders Subtractors Coding Examples sss 88 Unsigned 8 Bit Adder With Carry Out eene Ei Er aen nnne 90 Comparators Hardware Description Language HDL Coding Techniques s sssssrssssssserrttstrsrsrrrresseee 97 Comparators Log le 97 Comparators Related Constraints cceeasdtscesesatocecsersssceseeaniscssoveassecsveesecddieassstediensscccsenasse 97 Comparators Coding Examples iecsisiccincenscsscessse catecsisss sas cona eoe nsi EERE dsotevess soa een nne EESE EEEE SNEER 97 Multipliers Hardware Description Language HDL Coding Techniques sse 98 Registered Multipliers erer dEeee d en 99 Multipliets 2 5 Aint aad REI PRIX uct etecstesetveeseosvis sesso vate ege aere 99 Multiplication with Constant itte tere rtr Hk nho de a a pa e EEEN o e E ERE E EENE RES ERR EE SEE ones 100 Multipliers Log Be D 100 Multipliers Related Constraints eiecit cs irrite sennie Errn rna i ee e aa E HERE ENER ENEE 100 Multipliers Coding Examples nier er phe rey oe nente aset ee Peso rone enata gs 100 Se
452. piling verilog file statmach v in library work Module lt smallcntr gt compiled Compiling verilog file hex2led v in library work Module statmach compiled Compiling verilog file decode v in library work XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 455 XILINX Chapter 11 XST Log File Module hex2led compiled Compiling verilog file cnt60 v in library work Module decode compiled Compiling verilog file stopwatch v in library work Module lt cnt60 gt compiled Module lt stopwatch gt compiled No errors in compilation Analysis of file lt stopwatch prj gt succeeded Compiling vhdl file C xst watchver tenths vhd in Library work Entity tenths compiled Entity lt tenths gt Architecture tenths a compiled Compiling vhdl file C xst watchver dcm1 vhd in Library work Entity dcm1 compiled Entity dcm1 Architecture BEHAVIORAL compiled Design Hierarchy Analysis Analyzing hierarchy for module lt stopwatch gt in library work Analyzing hierarchy for entity lt dcm1 gt in library work architecture BEHAVIORAL Analyzing hierarchy for module lt statmach gt in library work with parameters clear 000001 counting 001000 start 000100 stop 010000 stopped 100000 zero 000010 Analyzing hierarchy for module decode in library work Analyzing hierarchy for module lt cnt60 gt in library lt
453. pletion 19 53 secs gt Total memory usage is 333688 kilobytes Number of errors 0 0 filtered Number of warnings 0 0 filtered Number of infos 1 0 filtered XST CPLD Log File Example The following is an example of an XST log file for CPLD synthesis Release 10 1 xst K 31 nt64 Copyright c 1995 2008 Xilinx Inc All rights reserved TABLE OF CONTENTS 1 Synthesis Options Summary 2 HDL Compilation 3 Design Hierarchy Analysis 4 HDL Analysis 5 HDL Synthesis 5 1 HDL Synthesis Report 6 Advanced HDL Synthesis 6 1 Advanced HDL Synthesis Report 7 Low Level Synthesis 8 Partition Report 9 Final Report Synthesis Options Summary Source Parameters Input File Name stopwatch prj Input Format mixed Ignore Synthesis Constraint File NO Target Parameters Output File Name stopwatch Output Format NGC Target Device CoolRunner2 CPLDs Source Options Top Module Name stopwatch Automatic FSM Extraction YES FSM Encoding Algorithm Auto Safe Implementation No XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 465 XILINX Mux Extraction YES Resource Sharing YES Target Options Add IO Buffers YES MACRO Preserve YES XOR Preserve YES Equivalent register Removal YES General Options Optimization Goal Speed Optimization Effort 1 Library Search Order stopwatch lso Keep Hierarchy YES Netlist
454. ports about inferred MACs during the Advanced HDL Synthesis Step where the MAC implementation mechanism takes place Multiply Adder Subtractors Log File In the log file XST reports the details of inferred multipliers adder subtractors and registers at the HDL Synthesis step The composition of multiply adder subtractor macros happens at the Advanced HDL Synthesis step XST reports information about inferred MACs because they are implemented within the MAC implementation mechanism Synthesizing Unit multipliers 6 Related source file is multipliers 6 vhd Found 8 bit register for signal A regl Found 8 bit register for signal A reg2 Found 8 bit register for signal B regl Found 8 bit register for signal B reg2 Found 8x8 bit multiplier for signal mult Found 16 bit addsub for signal lt multaddsub gt Summary inferred 32 D type flip flop s inferred 1 Adder Subtractor s inferred 1 Multiplier s Unit multipliers 6 synthesized Synthesizing advanced Unit Mmult mult Multiplier Mmult mult in block multipliers 6 and adder subtractor Maddsub multaddsub in block lt multipliers_6 gt are combined into a MAC lt Mmac_Maddsub_multaddsub gt The following registers are also absorbed by the MAC lt A_reg2 gt in block lt multipliers_6 gt lt A_regl gt in block lt multipliers_6 gt lt B_reg2 gt in block lt multipliers_6 gt lt B_regl gt in block lt multipliers_6 gt Unit lt
455. pper lower maintain The default value is maintain case Case Syntax Example xst run case upper Defines case globally to upper case vigcase Case Implementation Style vlgcase Case Implementation Style is valid for Verilog designs only vlgcase instructs XST how to interpret Verilog Case statements It has three possible values full XST assumes that the case statements are complete and avoids latch creation parallel XST assumes that the branches cannot occur in parallel and does not use a priority encoder e full parallel XST assumes that the case statements are complete and that the branches cannot occur in parallel therefore saving latches and priority encoders e If the option is not specified XST implements the exact behavior of the case statements vlgcase Case Implementation Style Architecture Support XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 267 XILINX nuit d XST Design Constraints Architecture independent vlgcase Case Implementation Style Applicable Elements Applies to the entire design vlgcase Case Implementation Style Propagation Rules Not applicable For more information see e Multiplexers Hardware Description Language HDL Coding Techniques e FULL_CASE Full Case e PARALLEL CASE Parallel Case You can also set this value in ISE Design Suite with Process gt Properties gt HDL Options gt Case Implementation Style vigcase C
456. preceded by keyword VHDL in a separate file The order of the files is not important XST can recognize the hierarchy and compile VHDL files in the correct order For the example perform the following steps 1 Opena new file called watchvhd prj 2 Enter the names of the VHDL files in any order into this file and save the file vhdl work statmach vhd vhdl work decode vhd vhdl work stopwatch vhd vhdl work cnt60 vhd vhdl work smallcntr vhd vhdl work tenths vhd vhdl work hex2led vhd 3 To synthesize the design execute the following command from the XST shell or the script file run ifn watchvhd prj ifmt mixed top stopwatch ofn watchvhd ngc ofmt NGC p xc5bvfx30t 2 ff324 opt mode Speed opt level 1 You must specify a top level design block with the top command line option To synthesize just hex21ed and check its performance independently of the other blocks you can specify the top level entity to synthesize on the command line using the top option For more information see XST Specific Non Timing Options run ifn watchvhd prj ifmt mixed ofn watchvhd ngc ofmt NGC p xc5vfx30t 2 ff324 opt mode Speed opt level 1 top hex2led During VHDL compilation XST uses the library work as the default If some VHDL files are to be compiled to different libraries add the library name before the file name For example to compile hex121ed into the library my lib write the project file as follows vhdl work statmach vh
457. ptember 16 2009 www xilinx com 185 XILINX Chapter XST Hardware Description Language HDL Coding Techniques Pipelined Distributed RAM Log File Following is the log file for Pipelined Distributed RAM Synthesizing Unit lt rams_22 gt Related source file is rams 22 vhd Found 64x4 bit single port RAM for signal RAM Found 4 bit register for signal do Summary inferred 1 RAM s inferred 4 D type flip flop s Unit lt rams_22 gt synthesized HDL Synthesis Report Macro Statistics RAMs 64x4 bit single port RAM Registers 4 bit register PRPRR Advanced HDL Synthesis SS INFO Xst Unit lt rams_22 gt The RAM Mram RAM will be implemented as a distributed RAM absorbing the following register s do aspect ratio 64 word x 4 bit clock connected to signal lt clk gt write enable connected to signal we address connected to signal lt addr gt data in connected to signal di data out connected to internal node ram style distributed Synthesizing advanced Unit rams 22 Found pipelined ram on signal varindex0000 1 pipeline level s found in a register on signal lt _varindex0000 gt Pushing register s into the ram macro INFO Xst 2390 HDL ADVISOR You can improve the performance of the ram Mram RAM by adding 1 register level s on output signal varindex0000 Unit rams 22 synthesized advanced Advanced HDL Synthesis Report
458. quential Complex Multipliers Hardware Description Language HDL Coding Techniques 101 Sequential Complex Multipliers Log File sssesssssssee Hee 102 Sequential Complex Multipliers Related Constraints sssssseeseee eee 102 Sequential Complex Multipliers Coding Examples sssssssseeee ee 102 Pipelined Multipliers Hardware Description Language HDL Coding Techniques ssesssssssssseret1e 1e 104 Pipelined Multipliers Log EE 106 Pipelined Multipliers Related Constratmte ee en 106 Pipelined Multipliers Coding Examples sss Hee 106 Pipelined Multiplier Outside Single VHDL Coding sample 107 Pipelined Multiplier Outside Single Verilog Coding Example sese 108 Multiply Adder Subtractors Hardware Description Language HDL Coding Techniques 112 Multiply Adder Subtractors in Virtex 4 Devices and Virtex 5 Devices sssssssssseeeeee 112 Multiply Adder Subtractors Log File eene emen nennen 113 Multiply Adder Subtractors Related Constramnts ee 114 Multiply Adder Subtractors Coding Examples eee 114 Multiply Accumulate Hardware Description Language HDL Coding Techniques sssssessssssserstes1s 117 Multiply Accumulate in Virtex 4 Devices and Virtex 5 Devices sssssssseseee tn 117 Multiply Aecumulate Log File eoe tert etel EE EN 118 Multiply Accumulate Related Constraimts ee eene 118 Multiply Accumulate Codi
459. ques 8 Bit Shift Left Register With Positive Edge Clock Synchronous Set Serial In and Serial Out Diagram S SHIFT REG so S Cc gt 8 Bit Shift Left Register With Positive Edge Clock Synchronous Set Serial In and Serial Out Pin Descriptions Synchronous Set Active High Serial Output 8 Bit Shift Left Register With Positive Edge Clock Synchronous Set Serial In and Serial Out VHDL Coding Example 8 bit Shift Left Register with Positive Edge Clock Synchronous Set Serial In and Serial Out library ieee use ieee std logic 1164 a11 entity shift registers 4 is port C SI S in std logic SO out std logic end shift registers 4 architecture archi of shift registers 4 is signal tmp std logic vector 7 downto 0 begin process C S begin if C event and C 1 then if S 1 then tmp lt others gt 1 else tmp lt tmp 6 downto 0 amp SI end if end if end process SO lt tmp 7 end archi XST User Guide 58 www xilinx com UG627 v 11 3 September 16 2009 nuit XST Hardware Description Language HDL Coding Techniques XILINX 8 Bit Shift Left Register With Positive Edge Clock Synchronous Set Serial In and Serial Out Verilog Coding Example 8 bit Shift Left Register with Positive Edge Clock Synchronous Set Serial In and Serial Out module v shift registers 4 C S SI SO input C SI S output SO reg 7 0 tmp always posedg
460. ques Signed 8 Bit Adder VHDL Coding Example Signed 8 bit Adder library ieee use ieee std_logic_1164 all use ieee std logic signed all entity adders 5 is port A B in std logic vector 7 downto 0 SUM out std logic vector 7 downto 0 end adders 5 architecture archi of adders 5 is begin SUM lt A B end archi Signed 8 Bit Adder Verilog Coding Example Signed 8 bit Adder module v adders 5 A B SUM input signed 7 0 A input signed 7 0 B output signed 7 0 SUM wire signed 7 0 SUM assign SUM A B endmodule Unsigned 8 Bit Subtractor Diagram Unsigned 8 Bit Subtractor Pin Descriptions IO Pins s Despton S RES Sub Result XST User Guide 94 www xilinx com UG627 v 11 3 September 16 2009 hapter 1 XST Hardware Description Language HDL Coding Techniques XILINX Unsigned 8 Bit Subtractor VHDL Coding Example Unsigned 8 bit Subtractor library ieee use ieee std logic 1164 all1 use ieee std logic unsigned all entity adders 6 is port A B in std logic vector 7 downto 0 RES out std logic vector 7 downto 0 end adders 6 architecture archi of adders 6 is begin RES lt A B end archi Unsigned 8 Bit Subtractor Verilog Coding Example Unsigned 8 bit Subtractor module v_adders_6 A B RES input 7 0 A input 7 0 B output 7 0 RES assign RES A B endmodule Unsigned 8 Bit Subtractor With Bor
461. ques XILINX Unsigned 8 Bit Adder With Carry Out Diagram SUM Unsigned 8 Bit Adder With Carry Out Pin Descriptions IO Pins Dome eem SUM Add Result Unsigned 8 Bit Adder With Carry Out VHDL Coding Example Unsigned 8 bit Adder with Carry Out library ieee use ieee std logic 1164 a11 use ieee std logic arith all use ieee std logic unsigned all entity adders 3 is port A B in std logic vector 7 downto 0 SUM out std logic vector 7 downto 0 CO out std logic end adders 3 architecture archi of adders 3 is signal tmp std logic vector 8 downto 0 begin tmp lt conv std logic vector conv integer A conv integer B 9 SUM lt tmp 7 downto 0 CO lt tmp 8 end archi The preceding example uses two arithmetic packages e std logic arith Contains the integer to std_logic conversion function conv std logic vector e std logic unsigned Contains the unsigned plus operation XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 91 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Unsigned 8 Bit Adder With Carry Out Verilog Coding Example Unsigned 8 bit Adder with Carry Out hf module v adders 3 A B SUM CO input 7 0 A input 7 0 B output 7 0 SUM output CO wire 8 0 tmp assign tmp A B assign SUM tmp 7 0 assign CO tmp 8 endmodule Unsigned 8 Bit Adder With Carry In and Carry Out D
462. ques describing macro inference for example registers and counters Sequential Process With Asynchronous Synchronous Parts VHDL Coding Example Declare asynchronous signals in the sensitivity list Otherwise XST issues a warning and adds them to the sensitivity list In this case the behavior of the synthesis result may be different from the initial specification process CLK RST begin if RST lt 0 1 then an asynchronous part may appear here optional part elsif CLK EVENT not CLK STABLE gt and CLK lt 0 1 then synchronous part sequential statements may appear here end if end process XST User Guide 388 www xilinx com UG627 v 11 3 September 16 2009 hipter XST VHDL Language Support XILINX VHDL Sequential Process Without a Sensitivity List Sequential processes without a sensitivity list must contain a Wait statement The Wait statement must be the first statement of the process The condition in the Wait statement must be a condition on the clock signal Several Wait statements in the same process are accepted but a set of specific conditions must be respected For more information see VHDL Multiple Wait Statements Descriptions An asynchronous part cannot be specified within processes without a sensitivity list Sequential Process Without a Sensitivity List VHDL Coding Example The following VHDL coding example shows the skeleton of the process described in this sec
463. r 15 downto 0 do out std logic vector 15 downto 0 end rams 02a architecture syn of rams 02a is type ram type is array 63 downto 0 of std logic vector 15 downto 0 signal RAM ram type begin process clk begin if clk event and clk 1 then if en 1 then if we 1 then RAM conv integer addr lt di do lt di else do lt RAM conv integer addr end if end if end if end process end syn XST User Guide 132 www xilinx com UG627 v 11 3 September 16 2009 Chipter1 XST Hardware Description Language HDL Coding Techniques XILINX Single Port RAM in Write First Mode VHDL Coding Example Two Write First Mode template 2 library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity rams 02b is port clk in St logic we xn Std logro en in std logic addr in std logic vector 5 downto 0 di in std logic vector 15 downto 0 do out std logic vector 15 downto 0 end rams 02b architecture syn of rams 02b is type ram type is array 63 downto 0 of std logic vector 15 downto 0 signal RAM ram type signal read addr std logic vector 5 downto 0 begin process clk begin if clk event and clk 1 then if en 1 then if we 1 then ram conv integer addr di end if read addr lt addr end if end if end process do lt ram conv integer read addr end syn XST User Guide UG627
464. r Description Using a Process Without a Sensitivity List Containing a Wait Statement VHDL Coding Example entity EXAMPLE is port DI in BIT VECTOR 7 downto 0 CLK in BIT DO out BIT VECTOR 7 downto 0 end EXAMPLE architecture ARCHI of EXAMPLE is begin process begin wait until CLK EVENT and CLK 1 DO DI end process end ARCHI 8 Bit Register With Clock Signal and Asynchronous Reset Signal VHDL Coding Example entity EXAMPLE is port DI in BIT VECTOR 7 downto 0 CLK in BIT RST in BIT DO out BIT VECTOR 7 downto 0 end EXAMPLE architecture ARCHI of EXAMPLE is begin process CLK RST begin if RST 1 then DO lt 00000000 elsif CLK EVENT and CLK 1 then DO lt DI end if end process end ARCHI 8 Bit Counter Description Using a Process With a Sensitivity List VHDL Coding Example library ASYL use ASYL PKG ARITH all entity EXAMPLE is port CLK 2n BIT RST in BIT DO out BIT VECTOR 7 downto 0 end EXAMPLE architecture ARCHI of EXAMPLE is begin process CLK RST variable COUNT BIT VECTOR 7 downto 0 begin if RST 1 then COUNT 00000000 elsif CLK EVENT and CLK 1 then COUNT COUNT 00000001 end if DO lt COUNT end process end ARCHI XST User Guide 390 www xilinx com UG627 v 11 3 September 16 2009 hipter XST VHDL Language Support XILINX VHDL Multiple Wait Statements Descriptions Sequ
465. r Extraction YES Shift Register Extraction YES Logical Shifter Extraction YES XOR Collapsing YES ROM Style Auto Mux Extraction YES Resource Sharing YES Asynchronous To Synchronous NO Use DSP Block auto Automatic Register Balancing No Target Options Add IO Buffers YES Global Maximum Fanout 500 Add Generic Clock Buffer BUFG 32 Number of Regional Clock Buffers 16 Register Duplication YES Chapter 11 XST Log File 454 www xilinx com XST User Guide UG627 v 11 3 September 16 2009 Chapter ti XST Log File XILINX Slice Packing YES Optimize Instantiated Primitives NO Use Clock Enable Auto Use Synchronous Set Auto Use Synchronous Reset Auto Pack IO Registers into IOBs auto Equivalent register Removal YES General Options Optimization Goal Speed Optimization Effort 1 Power Reduction NO Library Search Order stopwatch lso Keep Hierarchy NO Netlist Hierarchy as_optimized RTL Output Yes Global Optimization AllClockNets Read Cores YES Write Timing Constraints NO Cross Clock Analysis NO Hierarchy Separator Bus Delimiter lt gt Case Specifier maintain Slice Utilization Ratio 100 BRAM Utilization Ratio 100 DSP48 Utilization Ratio 100 Verilog 2001 YES Auto BRAM Packing NO Slice Utilization Ratio Delta 5 HDL Compilation Compiling verilog file smallcntr v in library work Com
466. r FF LUT pairs The integer value range is 0 to 100 when percent is used or both percent and pound are omitted XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 337 XILINX nuit t XST Design Constraints Slice LUT FF Pairs Utilization Ratio Delta XST Constraint File XCF Syntax Example One MODEL entity name slice utilization ratio maxmargin integer MODEL entity name slice utilization ratio maxmargin integer MODEL entity name slice utilization ratio maxmargin integertf XST interprets the integer values in the first two examples above as a percentage and in the last example as an absolute number of slices or FF LUT pairs The integer value range is 0 to 100 when percent is used or both percent and pound are omitted There must be no space between the integer value and the percent or pound characters You must surround the integer value and the percent and pound characters with double quotes because the percent and pound characters are special characters in the XST Constraint File XCF Slice LUT FF Pairs Utilization Ratio Delta XST Command Line Syntax Examples Define in the XST command line as follows xst run slice utilization ratio maxmargin integer xst run slice utilization ratio maxmargin integer xst run slice utilization ratio maxmargin integer XST interprets the integer values in the first two examples above as a percentage
467. r signal to which it is attached FSM_EXTRACT Automatic FSM Extraction Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it FSM_EXTRACT Automatic FSM Extraction VHDL Syntax Example Declare as follows attribute fsm extract string Specify as follows attribute Cam extract of entity name signal name entity signal is yes no FSM EXTRACT Automatic FSM Extraction Verilog Syntax Example Place immediately before the module or signal declaration fsm extract yes no si FSM EXTRACT Automatic FSM Extraction XST Constraint File XCF Syntax Example One MODEL entity name fsm_extract yes no true false FSM EXTRACT Automatic FSM Extraction XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name NET signal name fsm_extract yes no true false END FSM EXTRACT Automatic FSM Extraction XST Command Line Syntax Example Define in the XST command line as follows fsm extract yes no The default is yes FSM EXTRACT Automatic FSM Extraction ISE Design Suite Syntax Example Define in ISE Design Suite with Process gt Properties gt HDL Options gt FSM Encoding Algorithm These options are e If FSM Encoding Algorithm is set to None and sm extract is set to no sm encoding does not influence synthesis e nall other cases sm ex
468. r types Composite data types arrays or records are supported only in the following situations string std logic vector std ulogic vector signed unsigned bit vector There are no spaces between the prefix and the corresponding value generics Generics syntax Example generics company Xilinx width 5 init vector b100101 This command sets company to Xilinx width to 5 and init vector to b100101 hierarchy separator Hierarchy Separator hierarchy separator Hierarchy Separator defines the hierarchy separator character that is used in name generation when the design hierarchy is flattened The two supported characters are e _ underscore e forward slash The default is forward slash for newly created projects If a design contains a sub block with instance INSTI and this sub block contains a net called TMP_NET then the hierarchy is flattened and the hierarchy separator character is forward slash The name TMP_NET becomes INST1_TMP_NET If the hierarchy separator character is forward slash the net name is INST1 TMP_NET Using forward slash as a hierarchy separator is useful in design debugging because the forward slash separator makes it much easier to identify a name if it is hierarchical XST User Guide 272 www xilinx com UG627 v 11 3 September 16 2009 hapter XST Design Constraints XILINX To specify the hierarchy separator in ISE Design Suite
469. raints in VHDL as follows attribute PropertyName of NetName InstName PinName signal label is PropertyValue Implementation Constraints Verilog Syntax Examples Specify implementation constraints in Verilog as follows synthesis attribute PropertyName of NetName InstName PinName is PropertyValue In Verilog 2001 where descriptions precede the signal module or instance to which they refer specify implementation constraints as follows PropertyName PropertyValue RLOC Applies to all FPGA devices Does not apply to CPLD devices Use RLCC to indicate the placement of a design element on the FPGA die relative to other elements Assuming an SRL16 instance of name srl1 to be placed at location R9C0 50 you may specify the following in the Verilog code synthesis attribute RLOC of srll R9CO SO XST User Guide 358 www xilinx com UG627 v 11 3 September 16 2009 hapter i XST Design Constraints XILINX You may specify the same attribute in the XST Constraint File XCF as follows BEGIN MODEL ENTNAME INST sr11 RLOC R9CO S0 END The binary equivalent of the following line is written to the output NGC file INST srll RLOC R9CO S0 For more information see RLOC in the Constraints Guide NOREDUCE Applies to all CPLD devices Does not apply to FPGA devices NOREDUCE prevents the optimization of the boolean equation generating a given signal Assuming a local signal is assigned the arbitra
470. ration without any Hardware Description Language HDL source modifications such as for IP core generation and testing flows Behavioral Verilog Include Files Verilog allows you to separate source code into more than one file To reference the code contained in another file use the following syntax in the current file include path file to be included The path can be relative or absolute Multiple include statements are allowed in a single Verilog file This feature makes your code modular and more manageable in a team design environment where different files describe different modules of the design XST User Guide 434 www xilinx com UG627 v 11 3 September 16 2009 thipter t XST Behavioral Verilog Language Support XILINX To enable the file in your include statement to be recognized identify the directory where it resides either to ISE Design Suite or to XST e Since ISE Design Suite searches the ISE Design Suite project directory by default adding the file to your project directory identifies the file to ISE Design Suite e To direct ISE Design Suite to a different directory include a path relative or absolute in the include statement in your source code To point XST directly to your include file directory use Verilog Include Directories vlgincdir e If the include file is required for ISE Design Suite to construct the design hierarchy this file must either reside in the project directory or b
471. ray johnson speed1 user default auto yes no default yes lut bram EH lut A false auto default auto 254 www xilinx com XST User Guide UG627 v 11 3 September 16 2009 Chapter t XST Design Constraints XILINX i Constraint VHDL Constraint Command Command Name Value Target Verilog Target XCF Target Line Value T O Standard string signal signal net in model N A N A For more instance instance inst in model information see the Constraints Guide B dud Keep entity module model keep Hierarchy hierarchy no soft soft default FPGA no default CPLD yes LOC string signal primary signal primary net in model N A N A IO IO inst in model instance instance Map Entity on yes entity module model N A N A a Single LUT architecture Max Fanout integer entity module model max integer _fanout signal signal net in model default see detailed description Move First entity module model yes Stage primary primary primary clock no clock clock signal default yes signal signal net in model Move Last entity module model yes Stage primary primary primary clock TIO clock clock signal default yes signal signal net in model XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 255 XILINX Multiplier Style Mux Extraction yes No sadi Effort Optimization Goal Optimize Instantiated Primitive
472. rch Directory sd Cores Search Directories Syntax sd directory_path directory_path There is no default sd Cores Search Directories Syntax Example xst run sd c data cores c ise cores Tells XST to search for cores in c data cores and c ise cores in addition to the default directory For more information see Names With Spaces in Command Line Mode Decoder Extraction DECODER EXTRACT Decoder Extraction DECODER EXTRACT enables or disables decoder macro inference Decoder Extraction DECODER EXTRACT Architecture Support Applies to all FPGA devices Does not apply to CPLD devices Decoder Extraction DECODER EXTRACT Applicable Elements Applies to the entire design or to an entity component module or signal Decoder Extraction DECODER EXTRACT Propagation Rules When attached to a net or signal Decoder Extraction applies to the attached signal XST User Guide 302 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST Design Constraints XILINX When attached to an entity or module Decoder Extraction is propagated to all applicable elements in the hierarchy within the entity or module Decoder Extraction DECODER_EXTRACT Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it Decoder Extraction DECODER_EXTRACT VHDL Syntax Example Declare as follows attribute d
473. rchitecture ARCHI of ADDSUB is begin process A B ADD SUB variable AUX BIT VECTOR 3 downto 0 begin if ADD SUB 1 then AUX A B else AUX A end if S lt AUX end process end ARCHI B XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 385 XILINX Chapter 7 XST VHDL Language Support Combinatorial Process VHDL Coding Example Two entity EXAMPLE is port A B in BIT Ss out BIT J3 end EXAMPLE architecture ARCHI of EXAMPLE is begin process A B variable X Y BIT begin xs and B Y and A Y then S REC S end if end process end ARCHI VHDL H Eise Statements If else statements use true false conditions to execute statements If the expression evaluates to true the first statement is executed If the expression evaluates to false or x or z the Else statement is executed A block of multiple statements may be executed using begin and end keywords If else statements may be nested 2n ll lw m if If Else Statement VHDL Coding Example library IEEE use IEEE std logic 1164 all entity mux4 is port a b c d in std logic vector 7 downto 0 sell sel2 in std logic outmux out std logic vector 7 downto 0 end mux4 architecture behavior of mux4 is begin process a b c d sell sel2 begin if sell 1 then if sel2 1 then outmux lt a else outmux lt b end if else if sel2 1 then outmux
474. rchitecture Support sss 325 REDUCE CONTROL SETS Reduce Control Sets Applicable Elements sess 325 REDUCE CONTROL SETS Reduce Control Sets Propagation Rules sse 325 REGISTER BALANCING Register Balancing eene 325 REGISTER BALANCING Register Balancing Architecture Support 327 REGISTER BALANCING Register Balancing Applicable Elements sse 328 REGISTER BALANCING Register Balancing Propagation Rules sse 328 REGISTER DUPLICATION Register Duplication eeee e 329 REGISTER DUPLICATION Register Duplication Architecture Support sess 329 REGISTER DUPLICATION Register Duplication Applicable Elements sess 329 REGISTER DUPLICATION Register Duplication Propagation Rules sees 329 ROM EXTRACT ROM Extraction eso taut eoo to sean nere SERE o cero oa Spe SENEU e Sob ENEE RR en SENNENG 330 XST User Guide 10 www xilinx com UG627 v 11 3 September 16 2009 XILINX ROM_EXTRACT ROM Extraction Architecture Support sssssssssseee 330 ROM_EXTRACT ROM Extraction Applicable Hlements ee 330 ROM_EXTRACT ROM Extraction Propagation Rules sss 330 Ie vapeur u 331 ROM STYLE ROM Style Architecture Support i errr nererererererrees 331 ROM STYLE ROM Style Applicable Elements 331 ROM STYLE ROM Style Propagation Rules e 331 SHREG EXTRACT Shift Register Extractio
475. re a design element can be placed within an FPGA or CPLD device For more information see LOC in the in the netlist hierarchy Netlist Hierarchy Use netlist hierarchy Netlist Hierarchy to control the form in which the final NGC netlist is generated Netlist Hierarchy allows you to write the hierarchical netlist even if the optimization was done on a partially or fully flattened design If the value of Netlist Hierarchy is e as optimized XST takes into account the Keep Hierarchy KEEP HIERARCHY constraint and generates the NGC netlist in the form in which it was optimized In this mode some hierarchical blocks can be flattened and some can maintain hierarchy boundaries rebuilt XST writes a hierarchical NGC netlist regardless of the Keep Hierarchy KEEP HIERARCHY constraint To set this option in ISE Design Suite 1 Select Process gt Properties gt Synthesis Options 2 From the Property display level list select Advanced 3 Set the Netlist Hierarchy property netlist_hierarchy Netlist Hierarchy Syntax netlist hierarchy as_optimized rebuilt The default is as_optimized netlist_hierarchy Netlist Hierarchy Syntax Example netlist hierarchy rebuilt XST writes a hierarchical NGC netlist regardless of the KEEP HIERARCHY constraint OPT LEVEL Optimization Effort OPT LEVEL Optimization Effort defines the synthesis optimization effort level XST User Guide 276 www xilinx com UG627 v 11 3 Sep
476. reg 7 0 res always sel or res begin case sel 3 b000 res 8 b00000001 3 b001 res 8 500000010 3 b010 res 8 b00000100 3 b011 res 8 b00001000 3 b100 res 8 500010000 3 b101 res 8 b00100000 3 b110 res 8 b01000000 default res 8 b10000000 endcase end endmodule 1 of 8 Decoder One Cold Pin Descriptions gp Beseription S res Data Output 1 of 8 decoder One Cold VHDL Coding Example l of 8 decoder One Cold library ieee use ieee std logic 1164 all1 entity decoders 2 is port sel in std logic vector 2 downto 0 res out std logic vector 7 downto 0 end decoders 2 architecture archi of decoders 2 is begin res lt 11111110 when sel 000 else 11111101 when sel 001 else 11111011 when sel 010 else 11110111 when sel 011 else 11101111 when sel 100 else 11011111 when sel 101 else 10111111 when sel 110 else OITIITIITS end archi XST User Guide 76 www xilinx com UG627 v 11 3 September 16 2009 nuit XST Hardware Description Language HDL Coding Techniques XILINX 1 of 8 Decoder One Cold Verilog Coding Example 1 of 8 decoder One Cold module v_decoders_2 sel res input 2 0 sel output 7 0 res reg 7 0 res always sel begin case sel 3 b000 res 3 b001 res 3 b010 res 3 b011 res 3 b100 res 3 b101 res 8 b11011111 3 b110 res 8 b101
477. register into a DSP48 block while another part may be implemented on slices or even become a part of a shift register XST reports the total number of FF bits in the design in the HDL Synthesis Report after the Advanced HDL Synthesis step Registers Related Constraints e Pack I O Registers Into IOBs IOB e Register Duplication REGISTER DUPLICATION e Equivalent Register Removal EQUIVALENT REGISTER REMOVAL e Register Balancing REGISTER BALANCING Registers Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip Flip Flop With Positive Edge Clock Diagram XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 23 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Flip Flop With Positive Edge Clock Pin Descriptions gp Beseription S Data Input Positive Edge Clock Data Output Flip Flop With Positive Edge Clock VHDL Coding Example Flip Flop with Positive Edge Clock library ieee use ieee std logic 1164 a1l1 entity registers 1 is port C D in std logic Q out std logic end registers 1 architecture archi of registers 1 is begin process C begin if C event and C 1 then Q lt D end if end process end archi When using VHDL for a positive edge clock instead of using if C event and C 1 then you can also use if rising
478. registered multiplier for the following devices e Virtex 4 devices e Virtex 5 devices This registered multiplier is 18x18 bits Under the following conditions a registered multiplier is not used and a multiplier register is used instead e Output from the multiplier goes to any component other than the register e The Multiplier Style MULT STYLE constraint is set to lut e The multiplier is asynchronous e The multiplier has control signals other than synchronous reset or clock enable e The multiplier does not fit in a single 18x18 bit block multiplier The following pins are optional for a registered multiplier e Clock enable port e Synchronous and asynchronous reset and load ports Multipliers Note This section applies only to Virtex 4 devices Virtex 5 devices and Spartan 3A DSP devices Virtex 4 devices Virtex 5 devices and Spartan 3A DSP devices allow multipliers to be implemented on DSP48 resources XST supports the registered version of these macros and can push up to 2 levels of input registers and 2 levels of output registers into DSP48 blocks If a multiplier implementation requires multiple DSP48 resources XST automatically decomposes it onto multiple DSP48 blocks Depending on the operand size and to obtain the best performance XST may implement most of a multiplier using DSP48 blocks and use slice logic for the rest of the macro For example it is not sufficient to use a single DSP48 to implement an
479. reports the type and size of recognized MUXs during the Macro Recognition step Synthesizing Unit lt mux gt Related source file is multiplexers l vhd Found 1 bit 4 to 1 multiplexer for signal o Summary inferred 1 Multiplexer s Unit lt mux gt synthesized HDL Synthesis Report Macro Statistics Multiplexers E l bit 4 to 1 multiplexer SO Explicit inference and reporting of multiplexers may vary depending on the targeted device families The following coding examples are limited to 4 to 1 multiplexers They are reported as shown above only if the target is a LUT4 based device family For Virtex 5 devices multiplexers are explicitly inferred only for sizes of 8 to 1 and above Multiplexers Related Constraints e Mux Extraction MUX EXTRACT e Mux Style MUX STYLE e Enumerated Encoding ENUM_ENCODING Multiplexers Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip 4 to 1 1 Bit MUX Using IF Statement Diagram A B o c D 2 S X10543 4 to 1 1 Bit MUX Using IF Statement Pin Descriptions gp Desrpion S fii Outpt XST User Guide 70 www xilinx com UG627 v 11 3 September 16 2009 Chapter 3 XST Hardware Description Language HDL Coding Techniques XILINX 4 to 1 1 Bit MUX Using IF Statement VHDL Coding Example 4 to 1 1 bit MUX using an If statement library ieee use ieee
480. rererernrees 301 BUFGCE Extract BUEGCB eege ee HEN ERE ER ER MARY CORRER TECH EEA FEE EAR ERE Cr hd Bee dene 301 BUFGCE Extract BUFGCE Architecture Support s eseseressesrerererererererreeresersrererersrsesssrsrsssssese 301 BUFGCE Extract BUFGCE Applicable Elements cece rete teeeeeeeeerererererereneees 301 BUFGCE Extract BUFGCE Propagation Rules ssse tt 301 5d Cores Search Re ET 302 Decoder Extraction DECODER ESTRACT he Henne nennen nhe hene nee ess eene 302 Decoder Extraction DECODER EXTRACT Architecture Support ssssssssseeee 302 Decoder Extraction DECODER EXTRACT Applicable Elements 302 Decoder Extraction DECODER EXTRACT Propagation Rules sssssssseee 302 Decoder Extraction DECODER EXTRACT Syntax Examples sss 303 DSP UTILIZATION RATIO DSP Utilization Raat 303 DSP UTILIZATION RATIO DSP Utilization Ratio Architecture Support 304 DSP UTILIZATION RATIO DSP Utilization Ratio Applicable Elements sss 304 DSP UTILIZATION RATIO DSP Utilization Ratio Propagation Rules sess 304 FSM STYEE ESM Style rrie eege deeg ee ote Ice rhone so Deest denota s enden ee ess 305 FSM STYLE FSM Style Architecture Gupport viesim eiieeii ae 305 FSM STYLE FSM Style Applicable Elements 305 FSM STYLE FSM Style Propagation Rule 305 POWER dio dues V 306 POWER Power Reduction Architecture Support
481. ries separated by spaces and enclosed in braces C Synthesizing VHDL Designs Using Command Line Mode The following coding example shows how to synthesize a hierarchical VHDL design for a Virtex device using command line mode The example uses a VHDL design called watchvhd The files for wat chvhd can be found in the ISEexamples watchvhd directory of the ISE Design Suite installation directory This design contains seven entities e stopwatch e statmach e tenths a CORE Generator software core e decode e smallcntr e cnt60 e hex2led Following is an example of how to synthesize a VHDL design using command line mode 1 Create a new directory named vhd1 m 2 Copy the following files from the ISEexamples watchvhd directory of the ISE Design Suite installation directory to the newly created vhdl m directory e stopwatch vhd e statmach vhd e decode vhd e cnt60 vhd e smallcntr vhd e tenths vhd e hex2led vhd To synthesize the design which is now represented by seven VHDL files create a project XST User Guide 480 www xilinx com UG627 v 11 3 September 16 2009 Cbipttr i1 XST Command Line Mode XILINX XST supports mixed VHDL and Verilog projects Xilinx recommends that you use the new project format whether or not it is a real mixed language project In this example we use the new project format To create a project file containing only VHDL files place a list of VHDL files
482. rilog code using initial statements as shown in the following coding example reg 19 0 ram 63 0 initial begin ram 63 20 h0200A ram 62 20 h00300 ram 61 20 h08101 ram 60 20 h04000 ram 59 20 h08601 ram 58 20 h0233A ram 2 20 h02341 ram 1 20 h08201 ram 0 20 h0400D end always posedge clk begin if we ram addr lt di do lt ram addr end RAM Initial Contents VHDL Coding Example Binary RAM initial contents can be specified in hexadecimal as shown in RAM Initial Contents VHDL Coding Example Hexadecimal or in binary as shown in the following coding example type ram type is array 0 to SIZE 1 of std logic vector 15 downto 0 Signal RAM ram type 0111100100000101 0000010110111101 1100001101010000 0000100101110011 XST User Guide 170 www xilinx com UG627 v 11 3 September 16 2009 Chipter XST Hardware Description Language HDL Coding Techniques XILINX Initializing Block RAM Verilog Coding Example Binary RAM initial contents can be specified in hexadecimal as shown in Initializing Block RAM Verilog Coding Example Hexadecimal or in binary as shown in the following coding example reg 15 0 ram 63 0 initial begin ram 63 16 b0111100100000101 ram 62 16 b0000010110111101 ram 61 16 b1100001101010000 ram 0 16 b0000100101110011 end Single Port BRAM Initial Contents VHDL Coding Example Initiali
483. ring the Macro Recognition step Synthesizing Unit lt lshift gt Related source file is Logical Shifters l vhd Found 8 bit shifter logical left for signal so Summary inferred 1 Combinational logic shifter s Unit lt lshift gt synthesized HDL Synthesis Report Macro Statistics Logic shifters 2 aL 8 bit shifter logical left ae Logical Shifters Related Constraints Logical Shifter Extraction SHIFT EXTRACT Logical Shifters Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip The minimal size for XST to explicitly infer logical shifter macros may vary depending on the targeted device family The following coding examples have been validated on LUT4 based device families such as Virtex 4 devices For Virtex 5 devices logical shifters are explicitly inferred only when the selector size is at least 3 Logical Shifter One Diagram X10548 Logical Shifter One Pin Descriptions Shift Distance Selector XST User Guide 82 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX Logical Shifter One VHDL Coding Example Following is the VHDL code for a logical shifter library ieee use ieee std_logic_1164 all use ieee numeric std all entity logical shifters 1l is port DI in unsigned 7 downto 0 SEL in unsigned 1 do
484. rity Encoder Extraction PRIORITY_EXTRACT with a value force to force its inference 3 Bit 1 of 9 Priority Encoder Pin Descriptions n Despton S 3 Bit 1 of 9 Priority Encoder VHDL Coding Example 3 Bit l of 9 Priority Encoder library ieee use ieee std logic 1164 a11 entity priority encoder 1 is port sel in std logic vector 7 downto 0 code out std logic vector 2 downto 0 attribute priority extract string attribute priority extract of priority encoder 1 entity is force end priority encoder 1 architecture archi of priority encoder 1l is begin code lt 000 when sel 0 1 else 001 when sel 1 1 else 010 when sel 2 1 else 011 when sel 3 1 else 100 when sel 4 1 else 101 when sel 5 1 else 110 when sel 6 1 else 111 when sel 7 1 else end archi XST User Guide 80 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX 3 Bit 1 of 9 Priority Encoder Verilog Coding Example 3 Bit 1 of 9 Priority Encoder ere priority_extract force module v priority encoder 1 sel code input 7 0 sel output 2 0 code reg 2 0 code always G sel begin if sel 0 code 3 b000 else if sel 1 code 3 b001 else if sel 2 code 3 b010 else if sel 3 code 3 b011 else if sel 4 code 3 b100 else if sel 5 code 3
485. ronous Set eege etre ere tetra EEN 343 USE SYNC SET Use Synchronous Set Architecture Gupport 343 USE SYNC SET Use Synchronous Set Applicable Elements sssseeee 343 USE SYNC SET Use Synchronous Set Propagation Rules sse 344 USE SYNC RESET Use Synchronous Reset erre sterne bat gne betonen sheep eaa soap EaEER ENN 344 USE SYNC RESET Use Synchronous Reset Architecture Dupport 345 USE SYNC RESET Use Synchronous Reset Applicable Elements 345 USE SYNC RESET Use Synchronous Reset Propagation Rules see 345 WISER SPAS ER WEE 346 USE_DSP48 Use DSP48 Architecture Support ssssseessseee eee 346 USE DSP48 Use DSP48 Applicable Elements HH 347 USE DSPA48 Use DSP48 Propagation Rules em 347 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 11 XILINX XST CPLD Constraints NNon Drpogeet ee eu iise tenen eene nEn nona ko EE eisi EREKE ENK TEREKE Nee 348 spld ce Clock En ble erc ote eet i E E C E E E E E de 348 DATA GATE D ta Gafe EE 348 DATA GATE Architecture SUpPpOTLt ccsccinsccscsinessnssstenssacsascussnssssgusssssesdvensssesevessseneneeassdennsenssiene 349 pld mip Macro Preserve eee ecrit eere ccsessned cosvaad ccsverads EEEE ENE PEPEKA TENER ERR RE TATAE ERES 349 NOREDUCE No Reduce eese reseo anena nna e eiea ESE A terret EAE EE EAA EE S nenne 350 Wysiwye WYSIWYG DEE 350 wysiwyg WYSIWYG Architecture Support
486. row In Pin Descriptions IO Pins C RES Sub Result Unsigned 8 Bit Subtractor With Borrow In VHDL Coding Example Unsigned 8 bit Subtractor with Borrow In library IEEE use IEEE STD_LOGIC_1164 ALL use IEEE STD_LOGIC_UNSIGNED ALL entity adders_8 is port A B in std_logic_vector 7 downto 0 BI in std logic RES out std logic vector 7 downto 0 end adders 8 architecture archi of adders 8 is begin RES lt A B BI end archi XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 95 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Unsigned 8 Bit Subtractor With Borrow In Verilog Coding Example Unsigned 8 bit Subtractor with Borrow In hf module v adders 8 A B BI RES input 7 0 A input 7 0 B input BI output 7 0 RES assign RES A B BI endmodule Unsigned 8 Bit Adder Subtractor Diagram SUM OPER Unsigned 8 Bit Adder Subtractor Pin Descriptions IO Pins oms Bein O OPER Add Sub Select Unsigned 8 Bit Adder Subtractor VHDL Coding Example Unsigned 8 bit Adder Subtractor library ieee use ieee std_logic_1164 all use ieee std logic unsigned all entity adders 7 is port A B in std logic vector 7 downto 0 OPER in std logic RES out std logic vector 7 downto 0 end adders 7 architecture archi of adders 7 is begin RES lt A B when OPER O else A B end archi XST User Guide 96 w
487. rt statement ensures that the implementation of a single shift register does not exceed the size of a single Shift Register LUT SRL XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 393 XILINX Chapter 1 XST VHDL Language Support Since the size of the SRL is 16 bit and XST implements the last stage of the shift register using a flip flop ina slice then the maximum size of the shift register cannot exceed 17 bits The SINGLE_SRL block is instantiated twice in the entity named TOP the first time with SRL_WIDTH equal to 13 and the second time with SRL_WIDTH equal to 18 SINGLE_SRL Describing a Shift Register VHDL Coding Example library ieee use ieee std logic 1164 all entity SINGLE SRL is generic SRL WIDTH integer 16 port elk s in std logic inp in std logic outp out std logic end SINGLE SRL architecture beh of SINGLE SRL is signal shift reg std logic vector SRL WIDTH 1 downto 0 begin assert SRL WIDTH 17 report The size of Shift Register exceeds the size of a single SRL severity FAILURE process clk begin if clk event and clk 1 then shift reg lt shift reg SRL WIDTH 1 downto 1 amp inp end if end process outp lt shift reg SRL WIDTH 1 end beh library ieee use ieee std logic 1164 all entity TOP is port Glk i in std logic inpl inp2 in std logic outpl outp2 out std logic end TOP architecture beh of TOP is
488. rtex 5 devices only RAM STYLE RAM Style Applicable Elements Applies to the entire design or to an entity component module or signal XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 323 XILINX nuit d XST Design Constraints RAM_STYLE RAM Style Propagation Rules Applies to the entity component module or signal to which it is attached RAM_STYLE RAM Style Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it RAM_STYLE RAM Style VHDL Syntax Example Declare as follows attribute ram_style string Specify as follows attribute ram_style of signal_name entity_name signal entity is auto block distributed pipe_distributed block_powerl block_power2 The default is auto RAM_STYLE RAM Style Verilog Syntax Example Place this constraint immediately before the module or signal declaration ram_style auto block distributed pipe_distributed block_powerl block_power2 The default is auto RAM_STYLE RAM Style XST Constraint File XCF Syntax Example One MODEL entity name ram_style auto block distributed pipe distributed block powerl block power2 RAM STYLE RAM Style XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name NET signal name ram style auto block distributed pipe distri
489. rts types unsigned signed vectors and all overloaded arithmetic operators on these types It also defines conversion and extended functions for these types std logic unsigned Defines arithmetic operators on std ulogic vector and considers them as unsigned operators e std logic signed Defines arithmetic operators on std logic vector and considers them as signed operators e std logic misc Defines supplemental types subtypes constants and functions for the std 1ogic 1164 package such as and reduce or reduce VHDL Constructs Supported in XST XST supports the following VHDL Constructs e Design Entities and Configurations Expressions e Statements XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 397 XILINX Chapter 7 XST VHDL Language Support VHDL Design Entities and Configurations XST supports VHDL design entities and configurations except as noted below VHDL Entity Headers Generics Supported but integer type only Ports Supported but unconstrained ports are not allowed Entity Statement Part Unsupported VHDL Packages STANDARD Type TIME is not supported VHDL Physical Types TIME Ignored REAL Supported but only in functions for constant calculations VHDL Modes Linkage Unsupported VHDL Declarations Type Supported for enumerated types types with positive range having constant bounds bit vector types and multi dimensional arrays VHDL Objects Constant Declarat
490. ry function below and NOREDUCE attached to the signal s signal s std logic attribute NOREDUCE boolean attribute NOREDUCE of s signal is true S lt a or a and b Specify NOREDUCE in the XST Constraint File XCF as follows BEGIN MODEL ENTNAME NET s NOREDUCE NET s KEEP END XST writes the following statements to the NGC file NET s NOREDUCE NET s KEEP For more information see NOREDUCE in the or more information see NOREDUCE in the PWR MODE Power Mode PWR MODE Power Mode controls the power consumption characteristics of macrocells The following VHDL statement specifies that the function generating signal s should be optimized for low power consumption attribute PWR MODE string attribute PWR MODE of s signal is LOW Specify PWR MODE in the XST Constraint File XCF as follows MODEL ENTNAME NET s PWR MODE LOW NET s KEEP END XST writes the following statement to the NGC file NET s PWR MODE LOW NET s KEEP The Hardware Description Language HDL attribute can be applied to the signal on which XST infers the instance if e The attribute applies to an instance for example Pack I O Registers Into IOBs IOB DRIVE IOSTANDARD and e The instance is not available not instantiated in the HDL source PWR_MODE Power Mode Architecture Support Applies to all CPLD devices Does not apply to FPGA devices XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 359 X
491. s Parallel Case Case Power Reduction Priority Encoder Extraction auto block pipe block kcm csd lut pipe_lut HA module signal module signal module signal T i E EN Cl apler 6 g Constraint VHDL Constraint Command Command Name Value Target Verilog Target XCF Target Line Value entity signal entity signal entity signal XST Design Constraints auto block model net in model pipe_block kom csd lut pipe_lut default auto mux _extract mux _style model yes net in model no force default yes model auto net in model muxf muxcy default auto p Lom module model E level default 1 speed entity module model opt mode area yes entity no instance INA PPP a D entity no signal force module instance case statement case statement module signal speed area default speed model optimize yes i _primitives instance in no model NC no INA E fa no default no model priority yes _extract no net in model force default yes 256 www xilinx com XST User Guide UG627 v 11 3 September 16 2009 Chapter d XILINX Constraint VHDL Constraint Command Command Name Value Target Verilog Target XCF Target Line Value RAM yes entity module model ram _extract signal signal net in model no default yes Extraction RAM Style auto entity module model auto blo
492. s XST propagates it to the final netlist This feature is supported for registers and also for inferred block RAM if it can be implemented on a single block RAM primitive XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 229 XILINX Chapter 1 XST FPGA Optimization Specifying INIT and RLOC Values for a Flip Flop VHDL Coding Example Specification on an INIT and RLOC values for a flip flop described at RTL level library ieee use ieee std logic 1164 all entity inits rlocs 3 is port CLK in std logic DI in std logic vector 3 downto 0 DO out std logic vector 3 downto 0 end inits rlocs 3 architecture beh of inits rlocs 3 is signal tmp std logic vector 3 downto 0 1011 attribute RLOC string attribute RLOC of tmp signal is X3YO X2YO X1Y0 XO0YO begin process CLK begin if clk event and clk 1 then tmp DI end if end process DO tmp end beh Specifying INIT and RLOC Values for a Flip Flop Verilog Coding Example Specification on an INIT and RLOC values for a flip flop described at RTL level module v_inits_rlocs_3 clk di do input elk input 3 0 di output 3 0 do RLOC X3YO X2YO X1YO XOYO reg 3 0 tmp initial begin tmp 4 b1011 end always posedge clk begin tmp lt di end assign do tmp endmodule XST User Guide 230 www xilinx com UG627 v 11 3 September 16 2009 Chapter XST
493. s end beh 8 Bit Adders With Constant in a Single Block Ram Primitive Verilog Coding Example ff The following example places 8 bit adders with constant in a single block RAM primitive bram_map yes module v logic bram 1 clk rst A B RES input clk rst input 3 0 A B output 3 0 RES reg 3 0 RES always posedge clk begin if rst RES lt 4 p0000 else RES lt A B 8 b0001 end endmodule XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 211 XILINX Chapter 1 XST FPGA Optimization Asynchronous Reset VHDL Coding Example In the following example an asynchronous reset is used and so the logic is not mapped onto block RAM library ieee use ieee std logic 1164 all use ieee numeric std all entity logic bram 2 is port clk rst in std logic A B in unsigned 3 downto 0 RES out unsigned 3 downto 0 attribute bram map string attribute bram map of logic bram 2 entity is yes end logic bram 2 architecture beh of logic bram 2 is begin process clk rst begin if rst 1 then RES 0000 elsif clk event and clk 1 then RES lt A B 0001 end if end process end beh Asynchronous Reset Verilog Coding Example In the following example an asynchronous reset is used and so the logic is not mapped onto block RAM bram_map yes module v_logic_bram_2 clk rst A B R
494. s Dope Beim E wueAdeesmmayRed Adm gs wowptrat XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 143 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Dual Port RAM With Synchronous Read Read Through VHDL Coding Example Dual Port RAM with Synchronous Read Read Through library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity rams 11 is port clk in std logic we in std logic a in std logic vector 5 downto 0 dpra in std logic vector 5 downto 0 di in std logic vector 15 downto 0 Spo out std logic vector 15 downto 0 dpo out std logic vector 15 downto 0 end rams 11 architecture syn of rams 11 is type ram type is array 63 downto 0 of std logic vector 15 downto 0 signal RAM ram type signal read a std logic vector 5 downto 0 signal read dpra std logic vector 5 downto 0 begin process clk begin if clk event and clk 1 then if we 1 then RAM conv integer a di end if read a lt a read dpra lt dpra end if end process spo lt RAM conv integer read a dpo lt RAM conv integer read dpra end syn XST User Guide 144 www xilinx com UG627 v 11 3 September 16 2009 nuit XST Hardware Description Language HDL Coding Techniques XILINX Dual Port RAM With Synchronous Read Read Through Verilog Coding Example Dual Port RAM w
495. s Properties Synthesis Options LUT FF Pairs Utilization Ratio In ISE Design Suite you can define the value of Slice LUT FF Pairs Utilization Ratio only as a percentage You can not define the value as an absolute number of slices XST User Guide 336 www xilinx com UG627 v 11 3 September 16 2009 Chapter t XST Design Constraints XILINX Slice LUT FF Pairs Utilization Ratio Delta SLICE UTILIZATION RATIO MAXMARGIN Slice LUT FF Pairs Utilization Ratio Delta SLICE UTILIZATION RATIO MAXMARCGIN is closely related to Slice LUT FF Pairs Utilization Ratio SLICE UTILIZATION RATIO Slice LUT FF Pairs Utilization Ratio Delta defines the tolerance margin for Slice LUT FF Pairs Utilization Ratio SLICE UTILIZATION RATIO The value of the parameter can be defined in the form of percentage as well as an absolute number of slices or LUT FF pairs If the ratio is within the margin set the constraint is met and timing optimization can continue For more information see Speed Optimization Under Area Constraint Slice LUT FF Pairs Utilization Ratio Delta SLICE UTILIZATION RATIO MAXMARGIN Architecture Support Applies to all FPGA devices Does not apply to CPLD devices Slice LUT FF Pairs Utilization Ratio Delta SLICE UTILIZATION RATIO MAXMARGIN Applicable Elements Applies to the entire design or to an entity component module or signal Slice LUT FF Pairs Utilization Ratio Delta SLICE UTILIZATION RA
496. s In these cases XST issues a warning at the low level optimization step Depending on the particular design situation you may continue the design flow and the replacement could be done by MAP or you can force the replacement by applying Convert Tristates to Logic set to yes on a particular block or signal e The situations in which XST is unable to replace a tristate by logic are The tristate is connected to a black box Thetristate is connected to the output of a block and the hierarchy of the block is preserved The tristate is connected to a top level output Convert Tristates to Logic is set to no on the block where tristates are placed or on the signals to which tristates are connected XST User Guide 340 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST Design Constraints XILINX TRISTATE2LOGIC Convert Tristates to Logic Architecture Support Applies to all FPGA devices Does not apply to CPLD devices TRISTATE2LOGIC Convert Tristates to Logic Applicable Elements Applies to e Anentire design through the XST command line e A particular block entity architecture component e A signal TRISTATE2LOGIC Convert Tristates to Logic Propagation Rules Applies to the entity component module or signal to which it is attached TRISTATE2LOGIC Convert Tristates to Logic Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool
497. s Number of Reserved BRAMs In this formula Total Number of Available BRAMs is the number of BRAMs specified by the BRAM Utilization Ratio BRAM UTILIZATION RATIO constraint By default it is 100 The Number of Reserved BRAMs encapsulates The number of instantiated BRAMs in the Hardware Description Language HDL code from the UNISIM library e The number of RAM which were forced to be implemented as BRAMs by the RAM Style RAM STYLE and ROM Style ROM STYLE constraints e The number of BRAMs generated using BRAM mapping optimizations BRAM MAP Where there are available BRAM resources XST implements the largest inferred RAMs and ROMs using BRAM and the smallest on distributed resources If the Number of Reserved BRAMs exceeds available resources XST implements them as block RAMs and all inferred RAMs are implemented on distributed memory As soon as this process is completed XST can automatically pack two small single port BRAMs in a single BRAM primitive This optimization is controlled by the Automatic BRAM Packing AUTO BRAM PACKING constraint It is disabled by default For more information see BRAM Utilization Ratio BRAM UTILIZATION RATIO and Automatic BRAM Packing AUTO BRAM PACKING RAMs and ROMs Log File The XST log file reports the type and size of recognized RAM as well as complete information on its I O ports RAM recognition consists of two steps e During the HDL Synthesis step XST recognize
498. s sd Specifying INIT and RLOC Use the UNISIM library to directly instantiate LUT components in your Hardware Description Language HDL code To specify a function that a particular LUT must execute apply an INIT constraint to the instance of the LUT To place an instantiated LUT or register in a particular slice of the chip attach an RLOC constraint to the same instance XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 225 XILINX Chapter XST FPGA Optimization It is not always convenient to calculate INIT functions and different methods that can be used to achieve this Instead you can describe the function that you want to map onto a single LUT in your VHDL or Verilog code in a separate block Attaching a LUT_MAP constraint to this block indicates to XST that this block must be mapped on a single LUT XST automatically calculates the INIT value for the LUT and preserves this LUT during optimization XST automatically recognizes the XC_MAP constraint supported by Synplicity Passing an INIT Value Via the LUT_MAP Constraint Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip The following coding examples show how to pass an INIT value using the LUT_MAP constraint e Passing an INIT Value Via the LUT MAP Constraint VHDL Coding Example e Passing an INIT Value Via the LUT MAP Constraint Verilog Coding Exa
499. s CPLD devices VHDL and Verilog see the Constraints Guide Except for Value fields with check boxes there is a pulldown arrow or browse button in each Value field The arrow is not visible until you click in the Value field Setting Synthesis Options To set Hardware Description Language HDL synthesis options from ISE Design Suite Select a source file from the Source File window Right click Synthesize XST in the Process window Select Properties Select Synthesis Options Depending on the device type you have selected FPGA or CPLD devices one of two dialog boxes opens gi Um DOS uu ES Select any of the following synthesis options Optimization Goal OPT MODE e Optimization Effort OPT LEVEL e Use Synthesis Constraints File iuc e Synthesis Constraint File uc e Library Search Order lso e Global Optimization Goal glob_opt e Generate RTL Schematic rtlview e Write Timing Constraints write timing constraints e Verilog 2001 verilog2001 XST User Guide 246 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST Design Constraints XILINX To view the following options select Edit gt Preferences gt Processes gt Property Display Level gt Advanced e Keep Hierarchy KEEP_HIERARCHY e Cores Search Directories sd e Cross Clock Analysis cross clock analysis e Hierarchy Separator hierarchy_separator e Bus Delimiter bus_delimiter e Case case e Work Dir
500. s Load From Primary Input VHDL Coding Example 4 bit Unsigned Up Counter with Asynchronous Load from Primary Input library ieee use ieee std_logic_1164 all use ieee std logic unsigned all entity counters 3 is port C ALOAD in std logic D in std logic vector 3 downto 0 Q out std logic vector 3 downto 0 end counters 3 architecture archi of counters 3 is signal tmp std logic vector 3 downto 0 begin process C ALOAD D begin if ALOAD 1 then tmp lt D elsif C event and C 1 then tmp tmp 1 end if end process Q lt tmp end archi XST User Guide 40 www xilinx com UG627 v 11 3 September 16 2009 nuit XST Hardware Description Language HDL Coding Techniques XILINX 4 Bit Unsigned Up Counter With Asynchronous Load From Primary Input Verilog Coding Example 4 bit Unsigned Up Counter with Asynchronous Load from Primary Input module v_counters_3 C ALOAD D Q input C ALOAD input 3 0 D output 3 0 0 reg 3 0 tmp always 8 posedge C or posedge ALOAD begin if ALOAD tmp lt D else tmp lt tmp 1 bl end assign Q tmp endmodule 4 Bit Unsigned Up Counter With Synchronous Load With Constant Diagram 4 Bit Unsigned Up Counter With Synchronous Load With Constant Pin Descriptions Positive Edge Clock Synchronous Load Active High XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 41 XILINX
501. s has a great impact on reducing design complexity XST User Guide 350 www xilinx com UG627 v 11 3 September 16 2009 taptir i XST Design Constraints XILINX XOR Preserve values are e yes default XOR macros are preserved no XOR macros are merged with surrounded logic Preserving XORs generally gives better results That is the number of PTerms is lower Use the no value to obtain completely flat netlists Applying global optimization on a completely flat design sometimes improves design fitting To obtain a completely flattened design select the following options e Flatten Hierarchy yes e Macro Preserve no e XOR Preserve no The no value does not guarantee the elimination of the XOR operator from the Electronic Data Interchange Format EDIF netlist During the netlist generation the netlist mapper tries to recognize and infer XOR gates in order to decrease the logic complexity This process is independent of the XOR preservation done by Hardware Description Language HDL synthesis and is guided only by the goal of complexity reduction pld xp XOR Preserve Architecture Support Applies to all CPLD devices Does not apply to FPGA devices pld xp XOR Preserve Applicable Elements Applies to the entire design pld xp XOR Preserve Propagation Rules Not applicable Set this value in ISE Design Suite with Process gt Properties gt Xilinx Specific Options gt XOR Preserve pld xp XOR Preserve Sy
502. s or methods If a tool or method is not listed you cannot use this constraint with it OPT_MODE Optimization Goal VHDL Syntax Example Declare as follows attribute opt_mode string Specify as follows attribute opt_mode of entity_name entity is speed area OPT_MODE Optimization Goal Verilog Syntax Example Place immediately before the module declaration or instantiation opt_mode speed area OPT_MODE Optimization Goal XST Constraint File XCF Syntax Example MODEL entity_name opt_mode speed area OPT_MODE Optimization Goal XST Command Line Syntax Example Define in the XST command line as follows xst run opt_mode area speed The default is speed OPT_MODE Optimization Goal ISE Design Suite Syntax Example Define in ISE Design Suite with Process gt Properties gt Synthesis Options gt Optimization Goal XST User Guide 278 www xilinx com UG627 v 11 3 September 16 2009 hapter i XST Design Constraints XILINX PARALLEL_CASE Parallel Case PARALLEL_CASE Parallel Case is valid for Verilog designs only PARALLEL_CASE forces a case statement to be synthesized as a parallel multiplexer and prevents the case statement from being transformed into a prioritized if elsif cascade For more information see Multiplexers Hardware Description Language HDL Coding Techniques PARALLEL CASE Parallel Case Architecture Support Architecture independent PARALLEL CASE Parallel Ca
503. s show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it Slice LUT FF Pairs Utilization Ratio VHDL Syntax Examples Declare as follows attribute slice_utilization_ratio string XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 335 XILINX nuit t XST Design Constraints Specify as follows attribute slice_utilization_ratio of entity_name entity is integer attribute slice_utilization_ratio of entity_name entity is integer attribute slice utilization ratio of entity name entity is integer XST interprets the integer values in the first two examples above as a percentage and in the last example as an absolute number of slices or FF LUT pairs The integer value range is 1 to 100 when percent is used or both percent and pound 4 are omitted Slice LUT FF Pairs Utilization Ratio Verilog Syntax Examples Place immediately before the module declaration or instantiation slice utilization ratio integer slice utilization ratio integer slice utilization ratio integer XST interprets the integer values in the first two examples above as a percentage and in the last example as an absolute number of slices or FF LUT pairs The integer value range is 1 to 100 when percent is used or both percent and pound are omitted Slice LUT FF Pairs Utilization Ratio XST Co
504. s the presence of the memory structure in the Hardware Description Language HDL code e During the Advanced HDL Synthesis step XST decides how to implement a specific memory that is whether to use Block or Distributed memory resources Synthesizing Unit rams 16 Related source file is rams 16 vhd Found 64x16 bit dual port RAM Mram RAM for signal RAM Found 16 bit register for signal doa Found 16 bit register for signal dob Summary inferred 1 RAM s inferred32 D type flip flop s Unit rams 16 synthesized XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 127 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques HDL Synthesis Report Macro Statistics RAMs 1 64x16 bit dual port RAM Registers 2 16 bit register 2 1 Synthesizing advanced Unit lt rams_16 gt INFO Xst The RAM lt Mram_RAM gt will be implemented as a BLOCK RAM absorbing the following register s lt doa gt lt dob gt rise high high rise high high ram_type Block Port A aspect ratio 64 word x 16 bit mode write first ClkA connected to signal clka enA connected to signal ena weA connected to internal lt wea gt addrA connected to signal lt addra gt diA connected to internal dia doA connected to signal doa optimization speed ram_type Block Port B aspect ratio 64 word x 16
505. s using LUTs Set the value of Use DSP48 USE_DSP48 to yes in order to force XST to push these macros into a DSP48 When placing an Adder Subtractor on a DSP block XST checks to see if it is connected to other DSP chains If so XST tries to take advantage of fast DSP connections and connects this adder subtractor to the DSP chain using these fast connections When implementing adders subtractors on DSP48 blocks XST performs automatic DSP48 resource control To deliver the best performance XST by default tries to infer and implement the maximum macro configuration including as many registers in the DSP48 as possible Use the Keep KEEP constraint to shape a macro in a specific way For example to exclude the first register stage from the DSP48 place Keep KEEP constraints on the outputs of these registers XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 87 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Adders Subtractors and Adders Subtractors Log File Synthesizing Unit lt v_adders_4 gt Related source file is v_adders_4 v Found 8 bit adder carry in out for signal lt Saddsub0000 gt Summary inferred 1 Adder Subtractor s Unit lt v_adders_4 gt synthesized HDL Synthesis Report Macro Statistics Adders Subtractors 1 8 bit adder carry in out tod Adders Subtractors and Adders Subtractors Related Constraints e Use DSP48 USE DSP48 e DSP Utilization Ratio
506. se Applicable Elements Applies to case statements in Verilog meta comments only PARALLEL CASE Parallel Case Propagation Rules Not applicable PARALLEL CASE Parallel Case Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it PARALLEL CASE Parallel Case Verilog Syntax Examples The syntax is parallel case Since PARALLEL CASE does not contain a target reference the attribute immediately precedes the selector parallel case casex select 4 plxxx res datal 4 bxlxx res data2 4 pxxlx res data3 4 pxxxl res data4 endcase PARALLEL CASE is also available as a meta comment in the Verilog code The syntax differs from the standard meta comment syntax as shown in the following synthesis parallel case Since PARALLEL CASE does not contain a target reference the meta comment immediately follows the selector casex select synthesis parallel case 4 plxxx res datal 4 bxlxx res data2 4 bxxlx res data3 4 pxxxl res data4 endcase PARALLEL CASE Parallel Case XST Command Line Syntax Example Define in the XST command line as follows xst run vlgcase full parallel full parallel RLOC RLOC RLOC RLOC is a basic mapping and placement constraint RLOC groups logic elements into discrete sets and allows you to define the location of any element within
507. se of the shared variable the description of the different read write synchronizations may be different from coding examples recommended for single write RAMs The order of appearance of the different lines of code is significant XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 153 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Dual Port Block RAM With Two Write Ports Verilog Coding Example This is the most general example It has different clocks enables and write enables Dual Port Block RAM with Two Write Ports module v rams 16 clka clkb ena enb wea web addra addrb dia dib doa dob input clka clkb ena enb wea web input 5 0 addra addrb input 15 0 dia dib output 15 0 doa dob reg 15 0 ram 63 0 reg 15 0 doa dob always posedge clka begin if ena begin if wea ram addra lt dia doa lt ram addra end end always posedge clkb begin if enb begin if web ram addrb lt dib dob lt ram addrb end end endmodule Write First Synchronization Coding Example One process CLKA begin if CLKA event and CLKA 1 then if WEA 1 then RAM conv integer ADDRA DIA DOA DIA else DOA lt RAM conv integer ADDRA end if end if end process Write First Synchronization Coding Example Two In this example the read statement necessarily comes after the write statement
508. sescasstussecsssens 365 VEIDIGTEBE SUpPOrt LEE 366 VHIDE IBBE Ee GE 366 Non LRM Compliant Constructs in VHDL eeeeeeeeee eee nennen 366 XST VADE bile Type Supporter eeen e a e E E EER A E 366 Debugging Using Write Operation in VHDL Coding Examples e 368 Rules for Debugging Using Write Operation in VDL 370 VADE Data EE 370 Accepted VADE MB Mus M 370 XST User Guide 12 www xilinx com UG627 v 11 3 September 16 2009 XILINX VHDL Enumerated Types i24 ice tice stages ree rte reme ai etn aeter ean ener e edo er renun 371 VHDL User Defined Enumerated Types sssi esrin eH eene 371 VADL Bit Vector T pesS ER 371 VADE Integer Type EE 371 VHDL Predefined Ty pes ses terrre errem eerie teen ade EE Aa E eua ER TENER ERR KE IEPENE YR E 371 VHDL STD FOGIC 1164 TEBE Typeset eerte nnn ten nue antt reno EES 371 VADE Overloaded Data Types ict rettet dened va geed 372 VHDL Overloaded Enumerated Tvpes eH eene 372 VHDL Overloaded Bit Vector Iypes eee teeesessseese eade soe ndo tena na saos EE EES ENEE EN 372 VHDL Overloaded Integer Types i eee et rne ers Ernis Ses Erni NEE EN SEE ERES EES Raa 372 VHDL Overloaded STD LOGIC 1164 IEEE Tvpes Hmm 372 VHDL Overloaded STD LOGIC ARITH IEEE Types 373 VHDL Multi Dimensional Array Typess eserse nienie HI ee HH enne nne nenne 373 VADE Record Tee TE 374 VHD Ib Initials Vales ci odes ccdcees ccc de weitesiedevetiass aE A TELE 374 VHDL Local Rese
509. side the process block and the pipeline stages represented SES as shift registers library ieee use ieee std logic 1164 all use ieee numeric std all entity multipliers 4 is generic A port size integer 18 B port size integer 18 port clk in std logic A in unsigned A port size 1 downto 0 B in unsigned B port size 1 downto 0 MULT out unsigned A port size B port size 1 downto 0 attribute mult style string attribute mult style of multipliers 4 entity is pipe lut end multipliers 4 architecture beh of multipliers 4 is signal a in b in unsigned A port size 1 downto 0 signal mult res unsigned A port size B port size 1 downto 0 type pipe reg type is array 2 downto 0 of unsigned IA port size B port size 1 downto 0 Signal pipe regs pipe reg type begin mult res lt a in b in process clk begin if clk event and clk 1 then a in lt A b in lt B pipe regs mult res amp pipe regs 2 downto 1 MULT lt pipe regs 0 end if end process end beh XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 111 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Pipelined Multiplier Outside Shift Verilog Coding Example Pipelined multiplier iy The multiplication operation placed outside the always block and the pipeline stages represented as shift registers mult_style pipe_
510. signated net as in the case of the true value but does not attach the KEEP constraint in the final netlist to this net KEEP preserves the existence of the signal in the final netlist but not its structure For example if your design has a 2 bit multiplexer selector and you attach KEEP to it this signal is preserved in the final netlist But the multiplexer could be automatically re encoded by XST using one hot encoding As a consequence this signal in the final netlist is four bits wide instead of the original two To preserve the structure of the signal in addition to KEEP you must also use Enumerated Encoding ENUM ENCODING For more information see KEEP in the Constraints Guide KEEP_HIERARCHY Keep Hierarchy KEEP_HIERARCHY Keep Hierarchy is a synthesis and implementation constraint If hierarchy is maintained during synthesis the implementation tools use Keep Hierarchy to preserve the hierarchy throughout implementation and allow a simulation netlist to be created with the desired hierarchy XST can flatten the design to obtain better results by optimizing entity or module boundaries You can set Keep Hierarchy to true so that the generated netlist is hierarchical and respects the hierarchy and interface of any entity or module in your design XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 273 XILINX nuit t XST Design Constraints Keep Hierarchy is related to the hierarchical blocks VHDL entities
511. sing the contents of my proj 1so is rtfllib vhlib2 vhlibl XILINX XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 445 XST User Guide 446 www xilinx com UG627 v 11 3 September 16 2009 XILINX Chapter 11 XST Log File This chapter describes the XST log file and includes e XST FPGA Log File Contents e Reducing the Size of the XST Log File e Macros in XST Log Files e XST Log File Examples XST FPGA Log File Contents The XST FPGA log file contains the following e Copyright Statement e Table of Contents e Synthesis Options Summary e HDL Compilation e Design Hierarchy Analyzer e HDL Analysis e HDL Synthesis Report e Advanced HDL Synthesis Report e Low Level Synthesis e Partition Report e Final Report XST FPGA Log File Copyright Statement The XST FPGA log file copyright statement contains e ISE Design Suite release number e Xilinx notice of copyright XST FPGA Log File Table of Contents The XST FPGA log file table of contents lists the major sections in the log file Use the table of contents to navigate to different log file sections These headings are not linked Use the Find function in your text editor XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 447 XILINX Chapter 11 XST Log File XST FPGA Log File Synthesis Options Summary The XST FPGA log file Synthesis Options Summary contains information relating to e Source Par
512. sis Options gt Synthesis Constraint File uc Synthesis Constraint File Architecture Support Architecture independent uc Synthesis Constraint File Applicable Elements Applies to files uc Synthesis Constraint File Propagation Rules Not applicable uc Synthesis Constraint File Syntax The command line syntax is xst run uc filename uc Synthesis Constraint File Syntax Example uc my constraints xcf Specifies mu constraints xcf as the constraint file for this project TRANSLATE OFF Translate Off TRANSLATE OFF Translate Off and TRANSLATE ON Translate On instruct XST to ignore portions of VHDL or Verilog code that are not relevant for synthesis such as simulation code e TRANSLATE OFF marks the beginning of the section to be ignored e TRANSLATE ON instructs XST to resume synthesis from that point TRANSLATE OFF and TRANSLATE ON are also Synplicity and Synopsys directives that XST supports in Verilog Automatic conversion is also available in VHDL and Verilog TRANSLATE OFF and TRANSLATE ON can be used with the following words e synthesis e Synopsys A pragma XST User Guide 280 www xilinx com UG627 v 11 3 September 16 2009 Chapter t XST Design Constraints XILINX TRANSLATE_OFF Translate Off Architecture Support Architecture independent TRANSLATE_OFF Translate Off Applicable Elements Applies locally TRANSLATE_OFF Translate Off Propagation Rules Instructs the synthesis
513. sized Synthesizing advanced Unit multipliers 2 Found pipelined multiplier on signal mult res 4 pipeline level s found in a register connected to the multiplier macro output Pushing register s into the multiplier macro INFO Xst HDL ADVISOR You can improve the performance of the multiplier Mmult mult res by adding 1 register level s Unit multipliers 2 synthesized advanced HDL Synthesis Report Macro Statistics Multipliers 2 18x18 bit registered multiplier Ss Pipelined Multipliers Related Constraints e Use DSP48 USE_DSP48 e DSP Utilization Ratio DSP_UTILIZATION_RATIO e Keep KEEP e Multiplier Style MULT STYLE Pipelined Multipliers Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip Pipelined Multiplier Outside Single Diagram A MULT CLK X10557 XST User Guide 106 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX Pipelined Multiplier Outside Single Pin Descriptions ppm Beseription S clk Positive Edge Clock A B MULT Operands MULT Result Pipelined Multiplier Outside Single VHDL Coding Example Pipelined multiplier The multiplication operation placed outside the process block and the pipeline stages represented gt as single registers
514. sll Shift Left Logical sigl lt A 4 downto 0 sll 2 logically equivalent to sigl lt A 2 downto 0 amp 00 Operators VHDL Coding Example Two srl Shift Right Logical sigl lt A 4 downto 0 srl 2 logically equivalent to sigl lt 00 amp A 4 downto 2 XST User Guide 376 www xilinx com UG627 v 11 3 September 16 2009 hipter XST VHDL Language Support XILINX Operators VHDL Coding Example Three sla Shift Left Arithmetic sigl lt A 4 downto 0 sla 2 logically equivalent to sigl lt A 2 downto 0 amp A 0 amp A 0 Operators VHDL Coding Example Four sra Shift Right Arithmetic sigl lt A 4 downto 0 sra 2 logically equivalent to sigl lt lt A 4 amp A 4 amp A 4 downto 2 Operators VHDL Coding Example Five rol Rotate Left sigl lt A 4 downto 0 rol 2 logically equivalent to sigl lt A 2 downto 0 amp A 4 downto 3 Operators VHDL Coding Example Six ror Rotate Right A 4 downto 0 ror 2 logically equivalent to sigl lt A 1 downto 0 amp A 4 downto 2 Entity and Architecture Descriptions in VHDL Entity and architecture descriptions in VHDL include e Circuit Descriptions e Entity Declarations e Architecture Declarations e Component Instantiation e Recursive Component Instantiation e Component Configuration e Generic Parameter Declarations e Generic and Attribute Conflict VHDL Circuit Descriptions A circuit description in
515. source modifications such as for IP core generation and testing flows Verilog Parameter and Attribute Conflicts Since parameters and attributes can be applied to both instances and modules in your Verilog code and attributes can also be specified in a constraints file conflicts will occasionally arise To resolve these conflicts XST uses the following rules of precedence 1 Specifications on an instance lower level takes precedence over specifications on a module higher level 2 Ifa parameter and an attribute are specified on either the same instance or the same module the parameter takes precedence XST issues a warning message 3 An attribute specified in the XST Constraint File XCF takes precedence over attributes or parameters specified in the Verilog code When an attribute specified on an instance overrides a parameter specified on a module in XST the simulation tool may use the parameter any way If that happens the simulation results may not match the synthesis results Verilog Parameter and Attribute Conflicts Precedence Use the following table as a guide in determining precedence Verilog Parameter and Attribute Conflicts Precedence EE Parameter on an Instance Parameter on a Module Attribute on an Instance Apply Parameter XST issues warning Apply Attribute possible simulation mismatch Attribute on a Module Apply Parameter Apply Parameter XST issues warning Attribute in XCF Apply Attribute XST issues
516. static condition only XST User Guide 400 www xilinx com UG627 v 11 3 September 16 2009 hipter XST VHDL Language Support XILINX VHDL Reserved Words shared sla sll sra XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 401 XST User Guide 402 www xilinx com UG627 v 11 3 September 16 2009 XILINX Chapter 8 XST Verilog Language Support This chapter describes XST support for Verilog constructs and meta comments and includes e Behavioral Verilog e Variable Part Selects e Structural Verilog Features e Verilog Parameters e Verilog Parameter and Attribute Conflicts e Verilog Limitations in XST e Verilog Attributes and Meta Comments e Verilog Constructs Supported in XST e Verilog System Tasks and Functions Supported in XST e Verilog Primitives e Verilog Reserved Keywords e Verilog 2001 Support in XST For more information see e Verilog design constraints and options XST Design Constraints e Verilog attribute syntax Verilog 2001 Attributes e Setting Verilog options in the Process window of ISE Design Suite XST General Constraints Complex circuits are commonly designed using a top down methodology Various specification levels are required at each stage of the design process For example at the architectural level a specification may correspond to a block diagram or an Algorithmic State Machine ASM chart A block or ASM stage corresponds to a register transfer block where th
517. std logic 1164 all entity multiplexers 1l is port a b c d in std logic S in std logic vector 1 downto 0 o out std logic end multiplexers 1 architecture archi of multiplexers 1 is begin process a b C d S begin if s 00 then o lt a elsif s 01 then o lt b elsif s 10 then o lt c else o lt d end if end process end archi 4 to 1 1 Bit MUX Using IF Statement Verilog Coding Example 4 to 1 1 bit MUX using an If statement module v multiplexers 1 a b c d s o input a b c d input 1 0 s output oi reg o always a or b or c or d or s begin if s 2 b00 o a else if s 2 b01 o b else if s 2 b10 o c else o d end endmodule 4 to 1 1 Bit MUX Using Case Statement Diagram X10543 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 71 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques 4 to 1 1 Bit MUX Using Case Statement Pin Descriptions 10 Pins Beseription Data Inputs MUX Selector Data Output 4 to 1 1 Bit MUX Using Case Statement VHDL Coding Example 4 to 1 1 bit MUX using a Case statement library ieee use ieee std logic 1164 al1 entity multiplexers 2 is port a b c d in std logic S in std logic vector 1 downto 0 o out std logic end multiplexers 2 architecture archi of multiplexers 2 is begin process a b C d S
518. straint targets The following XST FPGA constraints non timing apply only to FPGA devices These constraints do not apply to CPLD devices e Asynchronous to Synchronous ASYNC TO SYNC XST User Guide 296 www xilinx com UG627 v 11 3 September 16 2009 Chapter t XST Design Constraints XILINX e Automatic BRAM Packing AUTO BRAM PACKING e BRAM Utilization Ratio BRAM UTILIZATION RATIO e Buffer Type BUFFER TYPE e Extract BUFGCE BUFGCE e Cores Search Directories sd e Decoder Extraction DECODER EXTRACT e DSP Utilization Ratio DSP_UTILIZATION_RATIO e FSM Style FSM_STYLE e Power Reduction POWER e Read Cores READ_CORES e Logical Shifter Extraction SHIFT EXTRACT e LUT Combining LC e Map Logic on BRAM BRAM_MAP e Max Fanout MAX FANOUT e Move First Stage MOVE FIRST STAGE e Move Last Stage MOVE LAST STAGE e Multiplier Style MULT STYLE e Mux Style MUX STYLE e Number of Global Clock Buffers bufg e Number of Regional Clock Buffers bufr e Optimize Instantiated Primitives OPTIMIZE_PRIMITIVES e Pack I O Registers Into IOBs IOB e Priority Encoder Extraction PRIORITY EXTRACT e RAM Extraction RAM EXTRACT RAM Style RAM STYLE e Reduce Control Sets REDUCE CONTROL SETS e Register Balancing REGISTER BALANCINCG e Register Duplication REGISTER DUPLICATION e ROM Extraction ROM EXTRACT e ROM Style ROM STYLE e Shift Register Extraction SHREG EXTRACT e Slic
519. t TNM NET e Timegroup TIMEGRD Timing Ignore TIG PERIOD Period Period PERIOD is a basic timing constraint and synthesis constraint A clock period specification checks timing between all synchronous elements within the clock domain as defined in the destination element group The group may contain paths that pass between clock domains if the clocks are defined as a function of one or the other For more information see PERIOD in the Constraints Guide Period XST Constraint File XCF Syntax Example NET netname PERIOD value HIGH LOW value OFFSET Offset OFFSET Offset is a basic timing constraint It specifies the timing relationship between an external clock and its associated data in or data out pin OFFSET is used only for pad related signals and cannot be used to extend the arrival time specification method to the internal signals in a design OFFSET allows you to e Calculate whether a setup time is being violated at a flip flop whose data and clock inputs are derived from external nets e Specify the delay of an external output net derived from the Q output of an internal flip flop being clocked from an external device pin For more information see OFFSET in the Constraints Guide XST User Guide 356 www xilinx com UG627 v 11 3 September 16 2009 taptir t XST Design Constraints XILINX OFFSET Offset Syntax Examples OFFSET IN OUT offset_time units BEFORE AFTER clk name T
520. t Global Reser 375 Default Initial Values on Memory Elements in VHDL sssseee eee 375 VADE ODJECIS M EE eaa 376 Signalin VADE EE 376 Vanables Im VNR steers ccc steers EE EAE EA E E EEE E N e AA P 376 Gonstants in WEIEN 376 MEHLEN 376 Entity and Architecture Descriptions in VHDL sii ceccscssscsssssascesssesovesscsssacuevasdsabeesessssecstaessseveasucsacesancsates 377 VHDL Circuit Descriptions kee eee tree eter sevice n ooo vs be donor Ure vv n SEENEN SEENEN 377 VHDL Entity IBI durior 378 VHDL Architecture Declarattons eese ikr nes sonr E e nemi esee esse eese TEREKE SES 378 VHDL Component Instantiation sitsers eisenii e He e e e he eene een n nne enne enne nennen 378 VHDL Recursive Component Instantiation eese HH e e e eene ener 379 VHDL Component Configuration rrt hte th hear h tane rat ee e raa EES EE HEU n SES RR IER MEA RE ERROR 380 VHDL Generic Parameter Declaratons eee hehe eerie ese ense esee ense ee oa 380 VHDL Generic and Attribute Conflicts eeesseeeeesese ee eene he hehehe eere se eese esee ense res 381 VADE Combinatorial Circuits EE 382 VHDL Concurrent Signal Aealemments sss e eem eH ene enne 382 VHDL Generate Statements isssssssesesesee ehe e e e ennemi sese se ese ese esse ese e eres esee sees 383 VHDL Combinatorial Processes eseseesesee e mI e e he tr irtete teter ee esi esee esse e se esee ere ee in 384
521. t Registers Log File The recognition of dynamic shift registers happens in the Advanced HDL Synthesis step The XST log file reports the size of recognized dynamic shift registers during the Macro Recognition step Synthesizing Unit lt dynamic_shift_registers_1 gt Related source file is dynamic shift registers l vhd Found 1 bit 16 to 1 multiplexer for signal lt Q gt Found 16 bit register for signal SRL SIG Summary inferred 16 D type flip flop s inferred 1 Multiplexer s Unit dynamic shift registers 1 synthesized Synthesizing advanced Unit dynamic shift registers 1 Found 16 bit dynamic shift register for signal Q XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 65 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Unit dynamic shift registers 1 synthesized advanced HDL Synthesis Report Macro Statistics Shift Registers 2 1 16 bit dynamic shift register 1 Dynamic Shift Registers Related Constraints Shift Register Extraction SHREG EXTRACT Dynamic Shift Registers Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip 16 Bit Dynamic Shift Register With Positive Edge Clock Serial In and Serial Out DYNAMIC SRL The following table shows pin descriptions for a dynamic register The register can e Be either serial or parall
522. t std logic end component signal tmp std logic begin GEN FD LAST if sh st 1 generate inst fd FD port map D gt DI C gt CLK Q DO end generate GEN FD INTERM if sh st 1 generate inst fd FD port map D gt DI C gt CLK Q gt tmp inst sstage single stage generic map sh st sh st 1 port map DI gt tmp CLK gt CLK DO gt DO end generate end recursive VHDL Component Configuration Associating an entity and architecture pair to a component instance provides the means of linking components with the appropriate model entity and architecture pair XST supports component configuration in the declarative part of the architecture for instantiation list component name use LibName entity Name Architecture Name The Structural Description of Half Adder VHDL Coding Example shows how to use a configuration clause for component instantiation The example contains the following for all statement for all NAND2 use entity work NAND2 ARCHI This statement indicates that all NAND2 components use the entity NAND2 and Architecture ARCHI When the configuration clause is missing for a component instantiation XST links the component to the entity with the same name and same interface and the selected architecture to the most recently compiled architecture If no entity or architecture is found a black box is generated during synthesis VHDL Generic Parameter Declarations Generic parameters may be declared i
523. t the same time XST performs both resource sharing and if required reduces the number of multiplexers XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 123 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques XST supports resource sharing for e Adders e Subtractors e Adders subtractors e Multipliers If the optimization goal is speed disabling resource sharing may give better results To improve clock frequency XST recommends deactivating resource sharing at the Advanced HDL Synthesis step Resource Sharing Log File The XST log file reports the type and size of recognized arithmetic blocks and multiplexers during the Macro Recognition step Synthesizing Unit lt addsub gt Related source file is resource sharing l vhd Found 8 bit addsub for signal res Found 8 1 bit 2 to 1 multiplexers Summary inferred 1 Adder Subtracter s inferred 8 Multiplexer s Unit lt addsub gt synthesized HDL Synthesis Report Macro Statistics Multiplexers x 2 to 1 multiplexer zf Adders Subtractors ed 8 bit addsub SC Advanced HDL Synthesis INFO Xst HDL ADVISOR Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization For improved clock frequency you may try to disable resource sharing Resource Sharing Related Constraints Resource Sharing RESOURCE SHARING Resource Shar
524. t this module as a Xilinx device primitive and use its parameters for instance in critical path estimation user black box XST processes it as a regular user black box If the name of the user black box is the same as that of a Xilinx device primitive XST renames it to a unique name and issues a warning For example MUX5 could be renamed to MUX51 as shown in the following log file example WARNING Xst 79 Model muxf5 has different characteristics in destination library WARNING Xst 80 Model name has been changed to muxf51 If BoxType BOX TYPE is not attached to the MUXF5 XST processes this block as a user hierarchical block If the name of the user black box is the same as that of a Xilinx device primitive XST renames it to a unique name and issues a warning VHDL and Verilog Xilinx Device Primitives Libraries XST provides dedicated libraries both in VHDL and Verilog simplifying instantiation of Xilinx device primitives in your HDL source code These libraries contain the complete set of Xilinx device primitives declarations with a BoxIype BOX TYPE constraint attached to each component VHDL Xilinx Device Primitives Device Libraries In VHDL declare library UNISIM with its package vcomponents in your source code library unisim use unisim vcomponents all The source code of this package can be found in the vhndl src unisims unisims_vcomp vhd file of the XST installation Verilog Xilinx Device Primitives Device
525. t want to instantiate RAM primitives to keep your Hardware Description Language HDL code architecture independent use XST automatic RAM recognition XST can infer distributed as well as block RAM It covers the following characteristics offered by these RAM types e Synchronous write Write enable e RAM enable e Asynchronous or synchronous read e Reset of the data output latches e Data output reset Single dual or multiple port read e Single port and dual port write e Parity bits e Block Ram with Byte Wide Write Enable e Simple dual port BRAM XST does not support RAMs and ROMs with negative addresses The type of inferred RAM depends on its description e RAM descriptions with an asynchronous read generate a distributed RAM macro e RAM descriptions with a synchronous read generate a block RAM macro In some cases a block RAM macro can actually be implemented with distributed RAM The decision on the actual RAM implementation is done by the macro generator If a given template can be implemented using Block and Distributed RAM XST implements BLOCK ones Use the RAM Style RAM STYLE constraint to control RAM implementation and select a desirable RAM type For more information see XST Design Constraints The following block RAM features are not supported e Parity bits Different aspect ratios on each port e Simple dual port distributed RAMs e Quad port distributed RAMs XST uses speed oriented implementation
526. tate Buffers Verilog Coding Example 4 to 1 1 bit MUX using tristate buffers module v_multiplexers_3 a b c d s 0 input a b c d input 3 0 s output assign o s 3 a 1 bz assign o s 2 b 1 bz assign o S 1 e 1 bz assign o s 0 d 1 bz endmodule The following coding examples illustrate how XST infers a latch when no else statement is described at the end of an if elsif construct Since the else statement is missing XST assumes that for the s 11 case o retains its old value and that a memory element is needed XST issues the following warning message WARNING Xst 737 Found 1 bit latch for signal lt ol gt INFO Xst HDL ADVISOR Logic functions respectively driving the data and gate enable inputs of this latch share common terms This situation will potentially lead to setup hold violations and as a result to Simulation problems This situation may come from an incomplete case statement all selector values are not covered You should carefully review if it was in your intentions to describe such a latch Unless you actually intended to describe such a latch add the missing else statement Caution Leaving out an else statement may result in errors during simulation XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 73 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques VHDL Coding Example of a Missing Else Statement Lea
527. tember 16 2009 Chapter i XST Design Constraints XILINX Allowed OPT_LEVEL values are e 1 normal optimization Use 1 normal optimization for very fast processing especially for hierarchical designs In speed optimization mode Xilinx recommends using 1 normal optimization for the majority of designs 1 normal optimization is the default e 2 higher optimization While 2 higher optimization is more time consuming it sometimes gives better results in the number of slices macrocells or maximum frequency Selecting 2 higher optimization usually results in increased synthesis run times and does not always bring optimization gain OPT_LEVEL Optimization Effort Architecture Support Architecture independent OPT_LEVEL Optimization Effort Applicable Elements Applies to the entire design or to an entity or module OPT_LEVEL Optimization Effort Propagation Rules Applies to the entity component module or signal to which it is attached OPT_LEVEL Optimization Effort Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it OPT_LEVEL Optimization Effort VHDL Syntax Example Declare as follows attribute opt_level string Specify as follows attribute opt level of entity name entity is 1 2 OPT LEVEL Optimization Effort Verilog Syntax Example Place immediately before the
528. tember 16 2009 www xilinx com 45 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques 4 Bit Signed Up Counter With Asynchronous Reset VHDL Coding Example 4 bit Signed Up Counter with Asynchronous Reset library ieee use ieee std logic 1164 all use ieee std logic signed all entity counters 7 is port C CLR in std logic Q out std logic vector 3 downto 0 end counters 7 architecture archi of counters 7 is signal tmp std logic vector 3 downto 0 begin process C CLR begin if CLR 1 then tmp 0000 elsif C event and C 1 then tmp tmp 1 end if end process Q lt tmp end archi 4 Bit Signed Up Counter With Asynchronous Reset Verilog Coding Example 4 bit Signed Up Counter with Asynchronous Reset module v counters 7 C CLR Q input C CLR output signed 3 0 Q reg signed 3 0 tmp always 8 posedge C or posedge CLR begin if CLR tmp lt 4 b0000 else tmp lt tmp 1 bl1 end assign Q tmp endmodule 4 Bit Signed Up Counter With Asynchronous Reset and Modulo Maximum Diagram 4 COUNT o CLR aen XST User Guide 46 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX 4 Bit Signed Up Counter With Asynchronous Reset and Modulo Maximum Pin Descriptions gp Beseription S Positive Edge Clock Asynchronous Reset Active High
529. the architecture it cannot be used in the entity declaration Once declared a VHDL attribute can be specified as follows attribute AttributeName of ObjectList ObjectType is AttributeValue VHDL Attribute Syntax Example Two attribute RLOC of u123 label is R11C1 S0 attribute bufg of my signal signal is sr XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 249 XILINX nuit t XST Design Constraints The object list is a comma separated list of identifiers Accepted object types are entity component label signal variable and type Follow these general rules e Ifa constraint can be applied on an entity VHDL then it can also be applied on the component declaration The ability to apply constraints on components is not explicitly stated for each individual constraint since it is a general XST rule e Some third party synthesis tools allow you to apply constraints on architectures XST allows constraints on architectures only for those third party constraints automatically supported by XST Verilog 2001 Attributes XST supports Verilog 2001 attribute statements Attributes are comments that pass specific information to software tools such as synthesis tools Verilog 2001 attributes can be specified anywhere for operators or signals within module declarations and instantiations Other attribute declarations may be supported by the compiler but are ignored by XST Use attributes to e Set constraints
530. the following devices e CoolRunner XPLA3 e CoolRunner II e XC9500 e XC9500XL The synthesis for CoolRunner XPLA3 device families and XC9500XL device families includes clock enable processing You can allow or invalidate the clock enable signal When invalidated it is replaced by equivalent logic The selection of the macros that use the clock enable counters for instance depends on the device type A counter with clock enable is accepted for the CoolRunner XPLAS3 device families and XC9500XL device families but rejected replaced by equivalent logic for XC9500 devices XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 233 XILINX hapter i XST CPLD Optimization Setting CPLD Synthesis Options Set the following CPLD synthesis options in ISE Design Suite in Process gt Properties gt Synthesis Options For more information see XST CPLD Constraints Non Timing e Keep Hierarchy KEEP_HIERARCHY e Macro Preserve pld mp e XOR Preserve pld xp Equivalent Register Removal EQUIVALENT REGISTER REMOVAL e Clock Enable Cold ce e WYSIWYG wysiwyg No Reduce NOREDUCE Implementation Details for Macro Generation XST processes the following macros e Adders e Subtractors e Add sub e Multipliers e Comparators e Multiplexers e Counters Logical shifters e Registers flip flops and latches e XORs The macro generation is decided by the Macro Preserve command line option which c
531. ther cascaded XORs should be collapsed into a single XOR XOR_COLLAPSE values are e yes default no e true XCF only e false XCF only XOR COLLAPSE XOR Collapsing Architecture Support Applies to all FPGA devices Does not apply to CPLD devices XOR COLLAPSE XOR Collapsing Applicable Elements Applies to cascaded XORs XOR_COLLAPSE XOR Collapsing Propagation Rules Not applicable XOR_COLLAPSE XOR Collapsing Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it XOR_COLLAPSE XOR Collapsing VHDL Syntax Example Declare as follows attribute xor_collapse string Specify as follows attribute xor_collapse signal_name entity_name signal entity is yes no The default is yes XOR_COLLAPSE XOR Collapsing Verilog Syntax Example Place immediately before the module or signal declaration xor_collapse yes no The default is yes XOR COLLAPSE XOR Collapsing XST Constraint File XCF Syntax Example One MODEL entity name xor_collapse yes no true false XST User Guide 334 www xilinx com UG627 v 11 3 September 16 2009 taptir t XST Design Constraints XILINX XOR_COLLAPSE XOR Collapsing XST Constraint File XCF Syntax Example Two BEGIN MODEL entity_name NET signal_name xor_collapse yes no true false XOR Collapsing END XO
532. thesis Analyzing module lt smallcntr gt in library lt work gt Module lt smallcntr gt is correct for synthesis Analyzing module lt hex2led gt in library lt work gt Module lt hex2led gt is correct for synthesis HDL Synthesis Performing bidirectional port resolution XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 457 XILINX Synthesizing Unit lt statmach gt Related source file is statmach v Found finite state machine lt FSM_0 gt for signal current state States 6 Transitions 15 Inputs 2 Outputs 2 Clock CLK rising_edge Reset RESET positive Reset type asynchronous Reset State 000001 Encoding automatic Implementation LUT Found 1 bit register for signal lt CLKEN gt Found 1 bit register for signal lt RST gt Summary inferred 1 Finite State Machine s inferred 2 D type flip flop s Unit lt statmach gt synthesized Synthesizing Unit decode Related source file is decode v Found 16x10 bit ROM for signal ONE HOT Summary inferred 1 ROM s Unit decode synthesized Synthesizing Unit lt hex2led gt Related source file is hex2led v Found 16x7 bit ROM for signal LED Summary inferred 1 ROM s Unit lt hex2led gt synthesized Synthesizing Unit lt smallcntr gt Related source file is smallcntr v Found 4 bit up counter for signal lt QOU
533. tio SLICE UTILIZATION RATIO all other FPGA devices Define in ISE Design Suite with Process Properties XST Synthesis Options By default this constraint is set to 100 of the selected device size This constraint has influence at low level synthesis only It does not control inference XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 213 XILINX Chapter 1 XST FPGA Optimization If this constraint is specified XST makes an area estimation If the specified constraint is met XST continues timing optimization trying not to exceed the constraint If the design is larger than requested XST tries to reduce the area first If the area constraint is met XST begins timing optimization Speed Optimization Under Area Constraint Example One 100 In the following example the area constraint was specified as 100 and initial estimation shows that in fact it occupies 102 of the selected device XST begins optimization and reaches 95 Found area constraint ratio of 100 5 on block tge actual ratio is 102 Optimizing block lt tge gt to meet ratio 100 5 of 1536 slices Area constraint is met for block lt tge gt final ratio is 95 Speed Optimization Under Area Constraint Example Two 70 If the area constraint cannot be met XST ignores it during timing optimization and runs low level synthesis to achieve the best frequency In the following example the target area constraint is set to 70 Sin
534. tion The clock condition may be a falling or a rising edge process begin wait until CLK EVENT not CLK STABLE and CLK lt 0 1 a synchronous part may be specified here end process XST does not support clock and clock enable descriptions within the same Wait statement Instead code these descriptions as shown in Clock and Clock Enable Not Supported VHDL Coding Example XST does not support Wait statements for latch descriptions Clock and Clock Enable Not Supported VHDL Coding Example wait until CLOCK event and CLOCK 0 and ENABLE II Clock and Clock Enable Supported VHDL Coding Example 8 Bit Counter Description Using a Process with a Sensitivity List if ENABLE 1 then Register and Counter Descriptions VHDL Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip 8 Bit Register Description Using a Process With a Sensitivity List Example VHDL Coding Example entity EXAMPLE is port DI in BIT_VECTOR 7 downto 0 CLK in BIT DO out BIT VECTOR 7 downto 0 end EXAMPLE architecture ARCHI of EXAMPLE is begin process CLK begin if CLK EVENT and CLK 1 then DO lt DI end if end process end ARCHI XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 389 XILINX Chapter 1 XST VHDL Language Support 8 Bit Registe
535. tion Ratio defines the number of BRAM blocks that XST must not exceed during synthesis BRAMs in the design may come not only from BRAM inference processes but from instantiation and BRAM mapping optimizations You may isolate an RTL description of logic in a separate block and then ask XST to map this logic to BRAM For more information see Mapping Logic Onto Block RAM Instantiated BRAMs are the primary candidates for available BRAM resources The inferred RAMs are placed on the remaining BRAM resources However if the number of instantiated BRAMs exceeds the number of available resources XST does not modify the instantiations and implement them as block RAMs The same behavior occurs if you force specific RAMs to be implemented as BRAMs If there are no resources XST respects user constraints even if the number of BRAM resources is exceeded If the number of user specified BRAMs exceeds the number of available BRAM resources on the target FPGA device XST issues a warning and uses only available BRAM resources on the chip for synthesis However you may disable automatic BRAM resource management by using value 1 This can be used to see the number of BRAMs XST can potentially infer for a specific design You may experience significant synthesis time if the number of BRAMs in the design significantly exceeds the number of available BRAMs on the target FPGA device hundreds of BRAMs This may happen due to a significant increase in design comp
536. tion Rules Not applicable duplication_suffix Duplication Suffix Architecture Syntax duplication suffix string dstring The default is d duplication suffix Duplication Suffix Architecture Syntax Example One xst run duplication suffix dupreg d If the flip flop named my is duplicated three times this command tells XST to generate the following names my ff dupreg 1 e my ff dupreg 2 my ff dupreg 3 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 269 XILINX nuit t XST Design Constraints duplication_suffix Duplication Suffix Architecture Syntax Example Two xst run duplication suffix dup d reg The d escape character can be placed anywhere in the suffix definition If the flip flop named my is duplicated three times this command tells XST to generate the following names my ff dup 1 reg my ff dup 2 reg my ff dup 3 reg FULL CASE Full Case FULL CASE Full Case is valid for Verilog designs only FULL CASE indicates that all possible selector values have been expressed in a case casex or casez statement The FULL CASE directive prevents XST from creating additional hardware for those conditions not expressed For more information see Multiplexers HDL Coding Techniques FULL CASE Full Case Architecture Support Architecture independent FULL CASE Full Case Applicable Elements Applies to case statements in Verilog meta comments FULL CASE Full Case
537. tional Output Registers VHDL Coding Example Block RAM with Optional Output Registers library IEEE library IEEE use use IEEE STD LOGIC 1164 ALL IEEE STD LOGIC UNSIGNED ALL entity rams 19 is end port clk1 clk2 in std logic we enl en2 in std logic addrl in std_logic_vector 5 downto 0 addr2 in std_logic_vector 5 downto 0 di in std_logic_vector 15 downto 0 resl out std_logic_vector 15 downto 0 res2 out std_logic_vector 15 downto 0 rams_19 architecture beh of rams_19 is type ram_type is array 63 downto 0 of std_logic_vector signal ram ram_type signal dol std_logic_vector 15 downto 0 signal do2 std_logic_vector 15 downto 0 begin process clkl begin if rising edge clkl then if we 1 then ram conv integer addrl lt di end if dol lt ram conv integer addrl end if end process process clk2 begin if rising edge clk2 then end do2 lt ram conv integer addr2 end if end process process clk1 begin if rising edge clkl then if enl 1 then resl lt dol end if end if end process process clk2 begin if rising edge clk2 then if en2 1 then res2 do2 end if end if end process beh 15 downto 0 168 www xilinx com XST User Guide UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX Block RAM With Optional Output Registers Verilog Coding Example
538. tions Shift Register Extraction slice packing Slice Packing slice packing Slice Packing enables the XST internal packer The packer attempts to pack critical LUT to LUT connections within a slice or a CLB This exploits the fast feedback connections among the LUTs in a CLB slice packing Slice Packing Architecture Support Applies to all FPGA devices Does not apply to CPLD devices slice packing Slice Packing Applicable Elements Applies to the entire design slice packing Slice Packing Propagation Rules Not applicable Set this value in ISE Design Suite in Process gt Properties gt Xilinx Specific Options gt Slice Packing slice packing Slice Packing Syntax slice packing yes no slice packing Slice Packing Syntax Example xst run slice packing no Disables the XST internal slice packer XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 333 XILINX nuit t XST Design Constraints USELOWSKEWLINES Use Low Skew Lines Use Low Skew Lines USELOWSKEWLINES is a basic routing constraint During synthesis Use Low Skew Lines prevents XST from using dedicated clock resources and logic replication based on the value of the Max Fanout MAX_FANOUT constraint Use Low Skew Lines specifies the use of low skew routing resources for any net For more information see USELOWSKEWLINES in the Constraints Guide XOR COLLAPSE XOR Collapsing XOR COLLAPSE XOR Collapsing controls whe
539. to block RAM in a separate hierarchical block 2 Attach a BRAM MAP Map Logic on BRAM constraint to the separate hierarchical block either directly in Hardware Description Language HDL code or in the XST Constraint File XCF XST cannot automatically decide which logic can be placed in block RAM Logic placed into a separate block must satisfy the following criteria e All outputs are registered e The block contains only one level of registers which are output registers e All output registers have the same control signals e The output registers have a Synchronous Reset signal e The block does not contain multisources or tristate busses The Keep KEEP constraint is not allowed on intermediate signals XST attempts to map the logic onto block RAM during the Advanced Synthesis step If any of the listed requirements are not satisfied XST does not map the logic onto block RAM and issues a warning If the logic cannot be placed in a single block RAM primitive XST spreads it over several block RAMs Mapping Logic Onto Block RAM Log Files This section contains examples of Mapping Logic Onto Block RAM Log Files e Mapping Logic Onto Block RAM Log File Example One e Mapping Logic Onto Block RAM Log File Example Two XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 209 XILINX Chapter 1 XST FPGA Optimization Mapping Logic Onto Block RAM Log File Example One Synthesizing Unit logic bram 1
540. to implement RAMs on BRAM resources This gives good results for speed but may require more BRAM resources than area oriented implementation XST does not support area oriented BRAM implementation Xilinx recommends the CORE Generator software for area oriented implementation For more information on RAM implementation see XST FPGA Optimization XST can e Implement Finite State Machine FSM components For more information see Finite State Machine FSM Hardware Description Language HDL Coding Techniques e Map general logic onto block RAMs For more information see Mapping Logic Onto Block RAM XST automatically controls BRAM resources on the target device BRAM Utilization Ratio BRAM_UTILIZATION_RATIO allows you to specify the number of BRAM blocks that XST must not exceed during synthesis To achieve better design speed XST implements small RAMs and ROMs using distributed resources RAMs and ROMs are considered small if their sizes follow the rules shown in the following table XST User Guide 126 www xilinx com UG627 v 11 3 September 16 2009 nuit XST Hardware Description Language HDL Coding Techniques XILINX Rules for Small RAMs and ROMs meum Sue its Wim os Use RAM Style RAM STYLE and ROM Style ROM STYLE to force implementation of small RAMs and ROMs on BRAM resources XST calculates the available BRAM resources for inference using the following formula Total Number of Available BRAM
541. tput signal names of registers including state bits Use the hierarchical name from the level where the register was inferred 4 Ensure that output signals of clock buffers get clockbuffertype such as BUFGP or IBUFG follow the clock signal name Maintain input nets to registers and tristates names Maintain names of signals connected to primitives and black boxes Name output net names of IBUFs using the form net name IBUF For example for an IBUF with an output net name of DIN the output IBUF net name is DIN IBUF 8 Name input net names to OBUFs using the form net name OBUF For example for an OBUF with an input net name of DOUT the input OBUF net name is DOUT_OBUF 9 Base names for internal combinatorial nets on user HDL signal names where possible XST Instance Naming Conventions Xilinx highly recommends that you use the following instance naming conventions To use instance naming conventions from previous releases of ISE Design Suite insert the following command line option in the XST command line old instance names 1 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 473 t XILINX Chapter 12 XST Naming Conventions The following rules are listed in order of naming priority 1 9o N og Bm Keep hierarchy in instance names using forward slashes or underscores as hierarchy designators When instance names are generated from VHDL or Verilog generate statements labels
542. tract is set to yes and f sm encoding is set to the selected value For more information about sm encoding see FSM Encoding Algorithm FSM_ENCODING ENUM ENCODING Enumerated Encoding ENUM ENCODING Enumerated Encoding applies a specific encoding to a VHDL enumerated type The value is a string containing space separated binary codes You can specify ENUM ENCODING only as a VHDL constraint on the considered enumerated type XST User Guide 286 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST Design Constraints XILINX When describing a Finite State Machine FSM using an enumerated type for the state register you may specify a particular encoding scheme with ENUM ENCODING In order for this encoding to be used by XST set FSM Encoding Algorithm FSM_ENCODING to user for the considered state register ENUM ENCODING Enumerated Encoding Architecture Support Architecture independent ENUM ENCODING Enumerated Encoding Applicable Elements Applies to signals or types Because ENUM_ENCODING must preserve the external design interface XST ignores ENUM_ENCODING when it is used on a port ENUM ENCODING Enumerated Encoding Propagation Rules Applies to the signal or type to which it is attached ENUM ENCODING Enumerated Encoding Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it
543. tribute register_balancing string Specify as follows attribute register_balancing of signal_name entity_name signal entity is yes no forward backward REGISTER_BALANCING Register Balancing Verilog Syntax Example Place immediately before the module or signal declaration register_balancing yes no forward backward The default is no REGISTER BALANCING Register Balancing XST Constraint File XCF Syntax Example One MODEL entity name register_balancing yes no true false forward backward REGISTER BALANCING Register Balancing XST Constraint File XCF Syntax Example Two BEGIN MODEL entity nameNET primary clock signal register balancing yes no true false forward backward END REGISTER BALANCING Register Balancing XST Constraint File XCF Example Three BEGIN MODEL entity name INST instance name register balancing yes no true false forward backward END REGISTER BALANCING Register Balancing XST Command Line Syntax Example Define in the XST command line as follows xst run register balancing yes no forward backward The default is no REGISTER BALANCING Register Balancing ISE Design Suite Syntax Example Define in ISE Design Suite with Process Properties Xilinx Specific Options Register Balancing XST User Guide 328 www xilinx com UG627 v 11 3 September 16 2009 Chapter t XST Design Constraints XILINX REG
544. trictions Within XST Code using equivalent names named blocks tasks and functions such as the following is rejected always clk begin fir_maind reg 4 0 fir mainb5 w1 reg 4 0 fir mainb5 WI XST issues the following error message ERROR Xst 863 design v line 6 Name conflict fir main5 fir main5 wl and fir main5 fir mainb5 W1 Code using case equivalent module names such as the following is rejected module UPPERLOWER10 module upperlowerl0 XST issues the following error message ERROR Xst 909 Module name conflict UPPERLOWER10 and upperlowerl10 XST User Guide 408 www xilinx com UG627 v 11 3 September 16 2009 tapter t XST Verilog Language Support XILINX Verilog Blocking and Nonblocking Assignments XST rejects Verilog designs if a given signal is assigned through both blocking and nonblocking assignments as shown in the following coding example always inl begin if in2 outl inl else outi lt in2 end If a variable is assigned in both a blocking and nonblocking assignment XST issues the following error message ERROR Xst 880 design v line n Cannot mix blocking and non blocking assignments on signal outl There are also restrictions when mixing blocking and nonblocking assignments on bits and slices The following coding example is rejected even if there is no real mixing of blocking and non blocking assignments
545. tristate resources e Use Clock Enable USE CLOCK ENABLE e Use Synchronous Set USE SYNC SET e Use Synchronous Reset USE SYNC RESET To display the following options select Edit Preferences Processes Property Display Level Advanced e Number of Global Clock Buffers bufg e Number of Regional Clock Buffers bufr Setting Xilinx Specific Options for CPLD Devices To set Xilinx specific options for CPLD devices in ISE Design Suite select Process gt Properties gt Synthesis Options gt Xilinx Specific Options XST User Guide 248 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST Design Constraints XILINX The following Xilinx specific options can be set for CPLD devices e Add I O Buffers iobuf e Equivalent Register Removal EQUIVALENT_REGISTER_REMOVAL e Clock Enable pld ce e Macro Preserve pld mp e XOR Preserve pld xp e WYSIWYG wysiwyg Setting Other XST Command Line Options Set other XST command line options in ISE Design Suite in Process gt Properties gt Other XST Command Line Options This is an advanced property Use the syntax described in XST Command Line Mode Separate multiple options with a space While Other XST Command Line Options is intended for XST options not listed in Process Properties if an option already listed is entered precedence is given to that option Illegal or unrecognized options cause XST to stop processing and generate a message such
546. ttach specific constraints to these Black Box instantiations which are passed to the NGC file XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 199 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques In addition you may have a design block for which you have an Register Transfer Level RTL model as well as your own implementation of this block in the form of an EDIF netlist The RTL model is valid for simulation purposes only Use the BoxType BOX_TYPE constraint to direct XST to skip synthesis of this RTL code and create a Black Box The EDIF netlist is linked to the synthesized design during NGDBuild For more information see XST General Constraints and the Constraints Guide Once you make a design a Black Box each instance of that design is a Black Box While you can attach constraints to the instance XST ignores any constraint attached to the original design Black Box Log File Since XST recognizes Black Boxes before macro inference the Black Box log file differs from the log files generated for other macros Analyzing Entity lt black_b gt Architecture lt archi gt WARNING Xst 766 black_box_l vhd Line 15 Generating a Black Box for component my block Entity black b analyzed Unit black b generated Black Box Related Constraints BoxType BOX TYPE BoxType was introduced for device primitive instantiation in XST See Device Primitive Support before using Box
547. ty or module to which the constraint is applied If a constraint is applied to an entity or module the constraint is applied to each instance of the entity or module Define constraints in ISE Design Suite in Process gt Properties or the XST run script if running on the command line Specify exceptions in the XCF file The constraints specified in the XCF file are applied only to the module listed and not to any submodules below it To apply a constraint to the entire entity or module use the following syntax MODEL entityname constraintname constraintvalue XST Constraint File XCF Example One MODEL top mux extract false MODEL my design max fanout 256 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 251 XILINX nuit t XST Design Constraints If the entity my_design is instantiated several times in the design the max_fanout 256 constraint is applied to each instance of my_design To apply constraints to specific instances or signals within an entity or module use the INST or NET keywords XST does not support constraints that are applied to VHDL variables BEGIN MODEL entityname INST instancename constraintname constraintvalue NET signalname constraintname constraintvalue END XST Constraint File XCF Example Two BEGIN MODEL crc32 INST stopwatch opt mode area INST U2 ram style block NET myclock clock buffer true NET data in iob true END For a complete list o
548. ues the following message for target lt RAM lt 63 gt gt ERROR Xst raminitfilel vhd line 40 Line RamFileLine has not enough elements XST User Guide 176 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX Initializing Block RAM External Data File Verilog Coding Example To initialize RAM from values contained in an external file use a readmemb or readmemh system task in your Verilog code For more information see XST Behavioral Verilog Language Support Set up the initialization file as follows e Arrange each line of the initialization file to represent the initial contents of a given row in the RAM e RAM contents can be represented in binary or hexadecimal e Use readmemb for binary and readmemh for hexadecimal representation To avoid the possible difference between XST and simulator behavior Xilinx recommends that you use index parameters in these system tasks See the following coding example readmemb rams 20c data ram 0 7 Create as many lines in the file as there are rows in the RAM array Initializing Block RAM from external data file module v_rams_20c clk we addr din dout input clk input we input 5 0 addr input 31 0 din output 31 0 dout reg 31 0 ram 0 63 reg 31 0 dout initial begin Sreadmemb rams_20c data ram 0 63 end always posedge clk begin if we r
549. uite select Safe Implementation as instructed in the HDL Options topic of ISE Design Suite Help or e Apply the Safe Implementation SAFE IMPLEMENTATION constraint to the hierarchical block or signal that represents the state register By default XST automatically selects a reset state as the recovery state If the FSM does not have an initialization signal XST selects a power up state as the recovery state To manually define the recovery state apply the Safe Recovery State SAFE RECOVERY STATE constraint Finite State Machine FSM Log File The XST log file reports the full information of recognized Finite State Machine FSM components during the Macro Recognition step Moreover if you allow XST to choose the best encoding algorithm for your FSMs it reports the one it chose for each FSM XST User Guide 192 www xilinx com UG627 v 11 3 September 16 2009 Chipter 1 XST Hardware Description Language HDL Coding Techniques XILINX As soon as encoding is selected XST reports the original and final FSM encoding If the target is an FPGA device XST reports this encoding at the HDL Synthesis step If the target is a CPLD device then XST reports this encoding at the Low Level Optimization step Synthesizing Unit fsm 1 Related source file is state machines l vhd Found finite state machine FSM 0 for signal state States 4 Transitions 5 Inputs T Outputs 4 Clock clk rising edge Reset reset p
550. unter With Synchronous Set Pin Descriptions gp Beseription S Positive Edge Clock Synchronous Set Active High Data Output 4 Bit Unsigned Down Counter With Synchronous Set VHDL Coding Example 4 bit unsigned down counter with a synchronous set library ieee use ieee std logic 1164 a1l1 use ieee std logic unsigned all entity counters 2 is port C S in std logic Q out std logic vector 3 downto 0 end counters 2 architecture archi of counters 2 is signal tmp std logic vector 3 downto 0 begin process C begin if C event and C 1 then if S 1 then tmp lt 1111 else tmp lt tmp 1 end if end if end process Q lt tmp end archi 4 Bit Unsigned Down Counter With Synchronous Set Verilog Coding Example 4 bit unsigned down counter with a synchronous set module v_counters_2 C S Q input C S output 3 0 Q reg 3 0 tmp always posedge C begin if S tmp lt 4 Db1111 else tmp lt tmp 1 bl end assign Q tmp endmodule XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 39 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques 4 Bit Unsigned Up Counter With Asynchronous Load From Primary Input Diagram 4 Bit Unsigned Up Counter With Asynchronous Load From Primary Input Pin Descriptions Positive Edge Clock Asynchronous Load Active High 4 Bit Unsigned Up Counter With Asynchronou
551. ur design Each I O pin input signal passes through a latch that can block the propagation of incident transitions during periods when such transitions are not of interest to your CPLD design XST User Guide 348 www xilinx com UG627 v 11 3 September 16 2009 hapter i XST Design Constraints XILINX Input transitions that do not affect the CPLD design function still consume power if not latched as they are routed among the CPLD s Function Blocks By asserting the Data Gate control I O pin on the device selected I O pin inputs become latched thereby eliminating the power dissipation associated with external transitions on those pins For more information see DATA_GATE in the Constraints Guide DATA_GATE Architecture Support Data Gate applies to CoolRunner II devices only pld_mp Macro Preserve pld mp Macro Preserve makes macro handling independent of design hierarchy processing This allows you to merge all hierarchical blocks in the top module while still keeping the macros as hierarchical modules You can also keep the design hierarchy except for the macros which are merged with the surrounding logic Merging the macros sometimes gives better results for design fitting Macro Preserve values are yes Macros are preserved and generated by Macrot no Macros are rejected and generated by HDL synthesizer Depending on the Flatten Hierarchy value a rejected macro is either merged in the design logic or bec
552. ural Assignments The pound and asterisk time control statements delay execution of the statement following them until the specified event is evaluated as true Blocking and non blocking procedural assignments have time control built into their respective assignment statement The pound delay is ignored for synthesis Behavioral Verilog Blocking Procedural Assignment Syntax Example The syntax for a blocking procedural assignment is shown in the following coding example reg a a 10 b c or if inl out 1 b0 else out in2 As the name implies these types of assignments block the current process from continuing to execute additional statements at the same time These should mainly be used in simulation Non blocking assignments on the other hand evaluate the expression when the statement executes but allow other statements in the same process to execute as well at the same time The variable change occurs only after the specified delay Behavioral Verilog Non Blocking Procedural Assignment Syntax Example The syntax for a non blocking procedural assignment is shown in the following coding example variable lt posedge_or_negedge_bit expression Behavioral Verilog Non Blocking Procedural Assignment Example The following shows an example of how to use a non blocking procedural assignment if inl out lt 1 bl else out lt in2 XST User Guide UG627 v 11 3 September 16 2009 www xilinx co
553. urce file is stopwatch v Found 1 bit register for signal lt strtstopinv gt Summary inferred 1 D type flip flop s Unit lt stopwatch gt synthesized HDL Synthesis Report Macro Statistics ROMs 3 16x10 bit ROM 1 16x7 bit ROM 2 Counters 3 4 bit up counter 3 Registers 3 1 bit register 3 Advanced HDL Synthesis XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 469 XILINX Chapter 11 XST Log File Analyzing FSM FSM 0 for best encoding Optimizing FSM lt MACHINE current_state FSM gt on signal current state 1 3 with sequential encoding 000001 000 000010 001 000100 010 001000 011 010000 100 100000 101 Advanced HDL Synthesis Report Macro Statistics ROMs 3 16x10 bit ROM 1 16x7 bit ROM 2 Counters 3 4 bit up counter 3 Registers 6 Flip Flops 6 Low Level Synthesis Optimizing unit lt stopwatch gt Optimizing unit lt statmach gt Optimizing unit decode Optimizing unit lt hex2led gt Optimizing unit lt tenths gt Optimizing unit lt smallcntr gt Optimizing unit lt cnt60 gt Partition Report Partition Implementation Status XST User Guide 470 www xilinx com UG627 v 11 3 September 16 2009 Chapter tt XST Log File No Partitions were found in this design Final Report Final Results
554. us Parallel Load Serial In and Serial Out Verilog Coding Example 8 bit Shift Left Register with Positive Edge Clock Asynchronous Parallel Load Serial In and Serial Out module v_shift_registers_6 C ALOAD SI D SO input C SI ALOAD input 7 0 D output SO reg 7 0 tmp always 8 posedge C or posedge ALOAD begin if ALOAD tmp lt D else tmp lt tmp 6 0 SI end assign SO tmp 7 endmodule 8 Bit Shift Left Register With Positive Edge Clock Synchronous Parallel Load Serial In and Serial Out Diagram X10540 8 Bit Shift Left Register With Positive Edge Clock Synchronous Parallel Load Serial In and Serial Out Pin Descriptions Synchronous Parallel Load Active High Serial Output XST User Guide 62 www xilinx com UG627 v 11 3 September 16 2009 Chipter1 XST Hardware Description Language HDL Coding Techniques 8 Bit Shift Left Register With Positive Edge Clock Synchronous Parallel Load Serial In and Serial Out VHDL Coding Example 8 bit Shift Left Register with Positive Edge Clock Synchronous Parallel Load Serial In and library ieee use ieee std logic 1164 all entity shift registers 7 is port C SI SLOAD in std logic D in std logic vector 7 downto 0 SO out std logic end shift registers 7 architecture archi of shift registers 7 is signal tmp std logic vector 7 downto 0 begin process C begin if C event and C 1 the
555. use the BoxType BOX_TYPE attribute with its value primitive is attached to each primitive in the UNISIM library If you instantiate a block non primitive in your design and the block has no contents no logic description or the block has a logic description but you attach a BoxType BOX_TYPE constraint to it with a value of user_black_box XST issues a warning as shown in the following log file example Analyzing Entity lt black_b gt Architecture lt archi gt WARNING VHDL 0103 c jm des vhd Line 23 Generating a Black Box for component my block Entity black b analyzed Unit black b generated Primitives Related Constraints e BoxType BOX TYPE e The PAR constraints that can be passed from HDL to NGC without processing Primitives Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip XST User Guide 222 www xilinx com UG627 v 11 3 September 16 2009 Chapter XST FPGA Optimization XILINX Passing an INIT Value Via the INIT Constraint VHDL Coding Example Passing an INIT value via the INIT constraint library ieee use ieee std logic 1164 all library unisim use unisim vcomponents all entity primitive 1 is port IO I1 in std logic O out std_logic end primitive 1 architecture beh of primitive 1 is attribute INIT string attribute INIT of inst label is 1
556. ust supply values References to other manuals Emphasis in text An optional entry or parameter However in bus specifications such as bus 7 0 they are required Braces A list of items from which you must choose one or more Vertical bar Separates items in a list of choices Vertical ellipsis Repetitive material that has been omitted Horizontal ellipsis Repetitive material that has been omitted Online Document The following conventions are used in this document speed grade 100 ngdbuild design_name File gt Open ngdbuild design_name See the Command Line Tools User Guide for more information If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected ngdbuild option_name design_name lowpwr on off lowpwr on off IOB 1 QOUT IOB 2 Name Name CLKIN allow block block name loc1 loc2 locn Blue text Cross reference link 18 www xilinx com See the section Additional Resources for details Refer to Title Formats in Chapter 1 for details See Figure 2 5 in the Virtex 6 Handbook XST User Guide UG627 v 11 3 September 16 2009 XILINX Chapter 2 Introduction to Xilinx Synthesis Technology XST This chapter provides general information about Xilinx Synthesis Technology XST and describes the changes to XST in this release This chapter includes e About XST e Whats New in Release 11 1 e
557. uted ROM resources ROM STYLE ROM Style Architecture Support Applies to all FPGA devices Does not apply to CPLD devices ROM STYLE ROM Style Applicable Elements Applies to the entire design or to an entity component module or signal ROM STYLE ROM Style Propagation Rules Applies to the entity component module or signal to which it is attached ROM STYLE ROM Style Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it ROM STYLE ROM Style VHDL Syntax Example ROM Extraction ROM EXTRACT must be set to yes in order to use ROM STYLE Declare as follows attribute rom style string Specify as follows attribute rom style of signal name entity name signal entity is auto block distributed The default is auto ROM STYLE ROM Style Verilog Syntax Example ROM Extraction ROM EXTRACT must be set to yes in order to use ROM STYLE Declare as follows rom style auto block distributed The default is auto XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 331 XILINX nuit t XST Design Constraints ROM_STYLE ROM Style XST Constraint File XCF Syntax Example One ROM Extraction ROM_EXTRACT must be set to yes in order to use ROM_STYLE MODEL entity name rom_style auto block distributed ROM STYLE ROM Style XST Co
558. utput template module v rams 21a clk en input clk input en input 5 0 addr output reg 19 0 data addr always posedge clk begin if en case addr 6 b000000 6 500000 6 5000010 6 50000 6 5000100 6 b00010 6 5000110 6 b0001 6 b001000 6 b00100 6 b001010 6 50010 6 5001100 6 500110 6 5001110 6 b0011 6 b010000 6 b01000 6 b010010 6 50100 6 5010100 6 501010 6 b010110 6 b0101 6 5011000 6 b01100 6 b011010 6 50110 6 b011100 6 501110 6 b011110 6 b0111 endcase end endmodule a a a a a a a a a a a a ata data data ata ata data ata ata data data ata ata data data ata ata data data ata ata data data ata data data ata ata data data ata ata data lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 data h0200A h00300 h08101 h04000 h08601 h0233A h00300 h08602 h02310 h0203B h
559. value XST issues an error message and stops execution For example if in the previous script example VHDL is incorrectly spelled VHDLL XST gives the following error message ERROR Xst 1361 Syntax error in command run for option ifmt parameter VHDLL is not allowed If you created your project using ISE Design Suite and have run XST at least once from ISE Design Suite you can switch to XST command line mode and use the script and project files that were created by ISE Design Suite To run XST from the command line run the following command from project directory xst ifn top level block xst ofn top level block syr Setting Up an XST Script An XST script is a set of commands each command having various options You can set up an XST script using any of the following commands e Run e Set e Elaborate Setting Up an XST Script Using the Run Command The run command is the main synthesis command It allows you to run synthesis in its entirety beginning with the parsing of the Hardware Description Language HDL files and ending with the generation of the final netlist The run keyword can be used only once per script file The run command begins with a keyword run which is followed by a set of options and its values run option_1 value option_2 value To improve the readability of your script file place each option value pair on a separate line Use the pound character to comment out options or place
560. values inside curly braces e Separate the values with spaces e Macro text can be specified between quotation marks or without them If the macro text contains spaces you must use quotation marks define macro1 Xilinx macro2 Xilinx Virtex4 define Verilog Macros Syntax Example xst run define macrol Xilinx macro2 Xilinx Virtex4 Defines two macros named macro1 and macro2 duplication suffix Duplication Suffix duplication suffix Duplication Suffix controls how XST names replicated flip flops By default when XST replicates a flip flop it creates a name for the new flip flop by taking the name of the original flip flop and adding _n to the end of it where n is an index number For instance if the original flip flop name is my and this flip flop was replicated three times XST generates flip flops with the following names e my f 1 e my EE 2 my ff 3 duplication suffix lets you change the string that is added to the original name To set this value in ISE Design Suite 1 Select Process gt Properties gt Synthesis Options 2 From the Property display level list select Advanced 3 Set the Other XST Command Line Options property duplication_suffix Duplication Suffix Architecture Support Architecture independent duplication_suffix Duplication Suffix Architecture Applicable Elements Applies to files duplication_suffix Duplication Suffix Architecture Propaga
561. ways posedge clk begin RAM addr lt dil di0 do lt RAM addr end endmodule Write First Mode Single Port BRAM with Byte wide Write Enable 2 Bytes Pin Descriptions ome E 00000 E mem E CC RAM np XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 159 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Write First Mode Single Port BRAM with Byte Wide Write Enable 2 Bytes VHDL Coding Example Single Port BRAM with Byte wide Write Enable 2 bytes in Write First Mode library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity rams 25 is generic SIZE integer 512 ADDR WIDTH integer 9 DI WIDTH integer 8 port clk in std logic we in std logic vector 1 downto 0 addr in std logic vector ADDR WIDTH 1 downto 0 di in std logic vector 2 DI WIDTH 1 downto 0 do out std logic vector 2 DI WIDTH 1 downto 0 end rams 25 architecture syn of rams 25 is type ram type is array SIZE 1 downto 0 of std logic vector 2 DI WIDTH 1 downto 0 signal RAM ram type Signal di0 dil std logic vector DI WIDTH 1 downto 0 signal do0 dol std logic vector DI WIDTH 1 downto 0 begin process we di begin if we 1 1 then dil lt di 2 DI WIDTH 1 downto 1 DI WIDTH dol lt di 2 DI WIDTH 1 downto 1 DI WIDTH else dil lt RAM conv integer addr 2 DI WIDTH 1 downto 1
562. wnto 0 SO out unsigned 7 downto 0 end logical shifters 1 architecture archi of logical shifters 1l is begin with SEL select SO lt DI when 00 DI sll 1 when O1 DI sll 2 when 10 DI sll 3 when others end archi Logical Shifter One Verilog Coding Example Following is the Verilog code for a logical shifter module v logical shifters 1 DI SEL SO input 7 0 DI input 1 0 SEL output 7 0 SO reg 7 0 SO always DI or SEL begin case SEL 2 b00 SO DI 2 b01 SO DI lt lt 1 2 b10 SO DI lt lt 2 default SO DI lt lt 3 endcase end endmodule Logical Shifter Two Pin Descriptions CSR EE XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 83 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Logical Shifter Two VHDL Coding Example XST does not infer a logical shifter for Logical Shifter Two since not all selector values are presented XST does not infer a logical shifter for this example as not all of the selector values are presented library ieee use ieee std logic 1164 all use ieee numeric std all entity logical shifters 2 is port DI in unsigned 7 downto 0 SEL in unsigned 1 downto 0 SO out unsigned 7 downto 0 end logical shifters 2 architecture archi of logical shifters 2 is begin with SEL select SO lt DI when 00 DI sll 1 when 01 DI sll 2 when others end ar
563. ww xilinx com UG627 v 11 3 September 16 2009 Chipter XST Hardware Description Language HDL Coding Techniques XILINX Unsigned 8 Bit Adder Subtractor Verilog Coding Example Unsigned 8 bit Adder Subtractor hf module v adders 7 A B OPER RES input OPER input 7 0 A input 7 0 B output 7 0 RES reg 7 0 RES always A or B or OPER begin if OPER 1 b0 RES A B else RES A B end endmodule Comparators Hardware Description Language HDL Coding Techniques This section discusses Comparators Hardware Description Language HDL Coding Techniques and includes e Comparators Log File e Comparators Related Constraints e Comparators Coding Examples Comparators Log File The XST log file reports the type and size of recognized comparators during the Macro Recognition step Synthesizing Unit lt compar gt Related source file is comparators l vhd Found 8 bit comparator greatequal for signal n0000 created at line 10 Summary inferred 1 Comparator s Unit lt compar gt synthesized HDL Synthesis Report Macro Statistics Comparators UC 8 bit comparator greatequal f Comparators Related Constraints None Comparators Coding Examples Coding examples are accurate as of the date of publication Download updates from ftp ftp xilinx com pub documentation misc examples_v9 zip XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 97 XILINX Chapter
564. www xilinx com 421 XILINX Chapter 1 XST Behavioral Verilog Language Support Power e Supported e Both operands are constants with the second operand being non negative If the first operand is a 2 then the second operand may be a variable XST does not support the real data type Any combination of operands that results in a real type causes an error The values X unknown and Z high impedance are not allowed Division Supported XST generates incorrect logic for the division operator between signed and unsigned constants Example 1235 3 b111 DER RE Lentz Heed i a eeng DEER EE EE sese 1 Iwemepay i sees Pevwise Negation Eesen id weemawweog leed PeeducionOR E leed PRedusionNOR 4 Sweet XST User Guide 422 www xilinx com UG627 v 11 3 September 16 2009 thipter t XST Behavioral Verilog Language Support XILINX Results of Evaluating Expressions in Behavioral Verilog The following table lists the results of evaluating expressions using the more frequently used operators supported by XST The and operators are special comparison operators useful in simulations to check if a variable is assigned a value of x or z They are treated as or in synthesis Results of Evaluating Expressions in Behavioral Verilog Behavioral Verilog Blocks Block statements are used to group statements together XST supports sequential blocks only Within these
565. x Example Define in ISE Design Suite with Process gt Properties gt Xilinx Specific Options gt Move Last Stage MULT STYLE Multiplier Style MULT STYLE Multiplier Style controls the way the macrogenerator implements the multiplier macros XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 315 XILINX nuit t XST Design Constraints MULT_STYLE values are e auto The default is auto The default instructs XST to look for the best implementation for each considered macro e block pipe block The pipe block option is used to pipeline DSP48 based multipliers It is available for Virtex 4 devices Virtex 5 devices and Spartan 3A DSP devices only e kcm csd e lut pipe lut The pipe lut option is for pipeline slice based multipliers MULT STYLE Multiplier Style Architecture Support Applies to all FPGA devices Does not apply to CPLD devices MULT STYLE Multiplier Style Applicable Elements Applies to the entire design or to an entity component module or signal MULT STYLE Multiplier Style Propagation Rules Applies to the entity component module or signal to which it is attached MULT STYLE Multiplier Style Syntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it MULT STYLE Multiplier Style VHDL Syntax Example Declare as follows attribute mu
566. x Example One MODEL entity name safe implementation yes no true false SAFE IMPLEMENTATION Safe Implementation XST Constraint File XCF Syntax Example Two BEGIN MODEL entity name NET signal name safe implementation yes no true false END SAFE IMPLEMENTATION Safe Implementation XST Command Line Syntax Example Define in the XST command line as follows safe implementation yes no The default is no SAFE IMPLEMENTATION Safe Implementation ISE Design Suite Syntax Example Define in ISE Design Suite with HDL Options Safe Implementation SIGNAL ENCODING Signal Encoding SIGNAL ENCODING Signal Encoding selects the coding technique to use for internal signals SIGNAL ENCODING values are e auto The default The best coding technique is automatically selected for each individual signal e one hot Forces the encoding to a one hot encoding user Forces XST to keep your encoding XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 295 XILINX nuit d XST Design Constraints SIGNAL_ENCODING Signal Encoding Architecture Support Architecture independent SIGNAL_ENCODING Signal Encoding Applicable Elements Applies to the entire design or to an entity component module or signal SIGNAL_ENCODING Signal Encoding Propagation Rules Applies to the entity component module or signal to which it is attached SIGNAL_ENCODING Signal Encoding Syntax Examples The f
567. x number of buffers in target device Bus Delimiter bus_delimiter default upper lower maintain default maintain Verilog Macros define name value default N A DSP Utilization Ratio dsp_utilization_ratio integer range 1 to 100 DSP_UTILIZATION_RATIO integer 6 range 1 to 100 integer default 100 Duplication suffix duplication suffix string odstring default 96d VHDL Top Level block entity name Valid only when old VHDL project default N A format is used ifmt VHDL Use project format ifmt mixed and top option to specify which top level block to synthesize Generics generics name value default N A HDL File Compilation Order hdl_compilation_order auto user default auto XST User Guide 260 www xilinx com UG627 v 11 3 September 16 2009 Chapter i XST Design Constraints XILINX Hierarchy Separator hierarchy_separator default Input Format ifmt mixed vhdl verilog default mixed Input Project File Name ifn file name default N A yes Add I O Buffers no default yes Ignore User Constraints yes no default no Library Search Order lso file name leo default N A LUT Combining lc auto area off default off Netlist Hierarchy netlist_hierarchy as_optimized rebuilt default as_optimized default ngc Output File Name ofn file_name ee a Foe Target Device part package speed For example xc5vfx30t ff324 2 Clock Ena
568. y Machine PROCESS 1 PROCESS 2 PROCESS 3 XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 197 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Finite State Machine FSM With Three Processes Pin Descriptions 10 Pins Beseription S clk Positive Edge Clock reset Asynchronous Reset Active High x1 FSM Input outp FSM Output Finite State Machine FSM With Three Processes VHDL Coding Example State Machine with three processes library IEEE use IEEE std logic 1164 all1 entity fsm 3 is port clk reset xl IN std logic outp OUT std logic end entity architecture behl of fsm 3 is type state type is s1 s2 s3 s4 signal state next state state type begin processl process clk reset begin if reset 1 then state s1 elsif clk 1 and clk Event then State next state end if end process processl process2 process state x1 begin case state is when sl gt if x1 1 then next state s2 else next state s3 end if when s2 gt next state lt s4 when s3 gt next state lt s4 when s4 gt next state lt sl end case end process process2 process3 process state begin case state is when sl gt outp lt 1 when s2 gt outp lt 1 when s3 gt outp lt 0 when s4 gt outp lt 0 end case end process process3 end behl XST User Guide 198 www xilinx com UG627 v 11
569. y the CORE Generator software library ieee use ieee std logic 1164 all use ieee std logic signed all entity read cores is port A B in std logic vector 7 downto 0 al DL os inm std logic SUM out std logic vector 7 downto 0 res out std logic end read cores architecture beh of read cores is component my add port A B in std logic vector 7 downto 0 S out std logic vector 7 downto 0 end component begin res lt al and bl inst my add port map A gt A B gt B S gt SUM end beh Read Cores Enabled or Disabled If Read Cores is disabled XST estimates Maximum Combinational Path Delay as 6 639ns critical path goes through a simple AND function and an area of one slice If Read Cores is enabled XST issues the following messages during Low Level Synthesis Launcher Executing edif2ngd noa my add edn my add ngo INFO NgdBuild Release 6 1i edif2ngd G 21 INFO NgdBuild Copyright c 1995 2003 Xilinx Inc All rights reserved Writing the design to my add ngo Loading core my add for timing and area information for instance inst Estimation of Maximum Combinational Path Delay is 8 281ns with an area of five slices By default XST reads Electronic Data Interchange Format EDIF and NGC cores from the current project directory If the cores are not in the project directory specify the directory in which the cores are located with Cores Search Directorie
570. yntax Examples The following examples show how to use this constraint with particular tools or methods If a tool or method is not listed you cannot use this constraint with it REDUCE CONTROL SETS Reduce Control Sets XST Command Line Syntax Example Define in the XST command line as follows xst run reduce control sets auto no The default is no REDUCE CONTROL SETS Reduce Control Sets ISE Design Suite Syntax Example Define in ISE Design Suite with Process Properties Xilinx Specific Options Reduce Control Sets REGISTER BALANCING Register Balancing REGISTER BALANCING Register Balancing enables flip flop retiming The main goal of register balancing is to move flip flops and latches across logic to increase clock frequency The two categories of REGISTER BALANCING are e Forward Register Balancing e Backward Register Balancing XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 325 XILINX nuit t XST Design Constraints Forward Register Balancing LP LUT1 LUT2 FF LUT1 LUT2 a Forward Register Balancing moves a set of flip flops at the inputs of a LUT to a single flip flop at its output When replacing several flip flops with one select the name based on the name of the LUT across which the flip flops are moving as shown in the following LutName FRBId Backward Register Balancing LUTI LUT2 DFF i H LUTI LUT2 FF Backward
571. zing Block RAM Single Port BRAM library ieee use ieee std logic 1164 all use ieee std logic unsigned all entity rams 20a is port clk in std logic we in std logic addr in std logic vector 5 downto 0 di in std logic vector 19 downto 0 do out std logic vector 19 downto 0 end rams 20a architecture syn of rams 20a is type ram type is array 63 downto 0 of std logic vector 19 downto 0 signal RAM ram type X 0200A X 00300 X 08101 X 04000 X 08601 X 0233A X 00300 X 08602 X 02310 X 0203B X 08300 X 04002 X 08201 X 00500 X 04001 X 02500 X 00340 X 00241 X 04002 X 08300 X 08201 X 00500 X 08101 X 00602 X 04003 X O241E X DO3OI X 00102 X 02122 X 02021 X 00301 X 00102 X 02222 X 04001 X 00342 X 0232B X 00900 X 00302 X 00102 X 04002 X 00900 X 08201 X 02023 X 00303 X 02433 X 00301 X 04004 X 00301 X O0102 X 02137 X 02036 X 00301 X OO0IO2 X 02237 x 04004 X 00304 X 04040 X 02500 X 02500 X 02500 X 0030D X 02341 X 08201 X 0400D begin process clk begin if rising edge clk then if we 1 then RAM conv integer addr lt di end if do lt RAM conv integer addr end if end process end syn XST User Guide UG627 v 11 3 September 16 2009 www xilinx com 171 XILINX Chapter i XST Hardware Description Language HDL Coding Techniques Single Port BRAM In

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