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1. 3 5 Efficient Program Sequencing In addition to zero overhead loops the ADSP 210xx supports single cycle setup and exit for loops Loops are nestable six levels in hardware and interruptable The processor also supports delayed and non delayed branches Introduction 14 ADSP 21000 FAMILY ARCHITECTURE OVERVIEW The following sections summarize the basic features of the ADSP 21020 architecture These features are also common to the ADSP 21060 SHARC processor SHARC specific enhancements to the base architecture are discussed in the next section 1 4 1 ADSP 21000 Family Base Architecture All members of the ADSP 21000 Family have the same base architecture The ADSP 21060 has advanced features built on to this base but retains code compatibility with the ADSP 21020 processor The key features of the base architecture are Independent Parallel Computation Units The arithmetic logic unit ALU multiplier and shifter perform single cycle instructions The three units are arranged in parallel maximizing computational throughput Single multifunction instructions execute parallel ALU and multiplier operations These computation units support IEEE 32 bit single precision floating point extended precision 40 bit floating point and 32 bit fixed point data formats Data Register File A general purpose data register file transfers data between the computation units and the data buses and for storing intermediate results This 10 por2. to the target processor through the processor s JTAG test access port Your software runs on your hardware at full speed in real time which simplifies hardware and software debugging 123 Third Party Support Several third party companies also provide products that support ADSP 21000 family development contact Analog Devices for a complete list Here are a few of the products available as of this writing Spectron SPOX Real time Operating System Comdisco Signal Processing Worksystem Loughborough Sound Images Spectrum Processing PC Plug in Board Momentum Data Systems Filter Design Software FDAS Hyperceptions Hypersignal Workstation Introduction 1 2 4 DSPatch DSPatch is Analog Devices award winning DSP product support newsletter Each quarterly issue includes applications feature articles stories about customers using ADI DSPs in consumer industrial and military products new product announcements product upgrade announcements and features as regular columns e Q 6 and tips from the Application Engineering staff e Programming a popular series of articles about programming DSPs with the C language 1 2 5 Applications Engineering Support Analog Devices expert staff of Applications Engineers are available to answer your technical questions e To speak to an Applications Engineer Monday to Friday 9am to 5pm EST call 617 461 3672 e You can send email to dsp_applications analog com e Fa
3. AM WE MEMORY MEMORY ADDR DATA pup ADSP 21020 PMTS PMPAGE ack PERIPHERALS ADDR DATA TIMEXP FLAG3 0 Figure 1 2 ADSP 21020 System Diagram 10 Introduction 143 ADSP 21060 SHARC The ADSP 21060 SHARC Super Harvard Architecture Computer is a single chip 32 bit computer optimized for signal computing applications The ADSP 21060 SHARC has the following key features Four Megabit Configurable On Chip SRAM Dual Ported for Independent Access by Base Processor and DMA Configurable as Maximum 128K Words Data Memory 32 Bit 80K Words Program Memory 48 Bit or Combinations of Both Up To 4 Mbits Off Chip Memory Interfacing e 4Gigawords Addressable 32 bit Address Programmable Wait State Generation Page Mode DRAM Support DMA Controller
4. Introducton TJ 1 This applications handbook is intended to help you get a quick start in developing DSP applications with ADSP 21000 Family digital signal processors This chapter includes a summary of available resources and an introduction to the ADSP 21000 Family architecture Complete architecture and programming details are found in each processor s data sheet the ADSP 21060 SHARC User s Manual and the ADSP 21020 User s Manual The next eight chapters describe commonly used DSP algorithms and their implementations on ADSP 21000 family DSPs The last chapter shows you how to build a bootstrap program downloader using the ADSP 21020 built in JTAG port 11 USAGE CONVENTIONS Code listings assembly language instructions and labels commands typed on an operating system shell command line and file names are printed inthe Courier font e Underlined variables are vectors V 1 2 DEVELOPMENT RESOURCES This section discusses resources available from Analog Devices to help you develop applications using ADSP 21000 Family digital signal processors 12 1 Software Development Tools A full set of software tools support ADSP 21000 family program development including an assembler linker simulator PROM splitter and C Compiler The development tools also include libraries of assembly language modules and C functions See the ADSP 21000 Family Assembler Tools amp Simulator Manual the ADSP 21000 Family C Tools Manual and the AD
5. SP 21000 Family C Runtime Library Manual for complete details on the development tools Introduction 1 2 2 Hardware Development Tools Analog Devices offers several systems that let you test your programs on real hardware without spending time hardware prototyping as well as help you debug your target system hardware 12 2 1 24 EZ LAB evaluation boards are complete ADSP 210xx systems that include memory an audio codec an analog interface and expansion connectors on a single small printed circuit board Several programs are included that demonstrate signal processing algorithms You can download your own programs to the EZ LAB from your IBM PC compatible computer EZ LAB connects with EZ ICE described in the next section and an IBM PC compatible to form a high speed interactive DSP workstation that lets you debug and execute your software without prototype hardware EZ LAB is also available bundled with the software development tools in the EZ KIT packages Each member of the ADSP 21000 family is supported by its own EZ LAB 1 2 2 2 EZ ICE EZ ICE in circuit emulators give you an affordable alternative to large dedicated emulators without sacrificing features The EZ ICE software runs on an IBM PC and gives you a debugging environment very similar to the ADSP 210xx simulator The EZ ICE probe connects to the PC with an ISA plug in card and to the target system through a test connector on the target EZ ICE communicates
6. action and combined addition subtraction It is IEEE floating point compatible and allows either interrupt on arithmetic exception or latched status exception handling 1 3 3 2 Unconstrained Data Flow The ADSP 210xx has a Harvard architecture combined with a 10 port 16 word data register file In every cycle all of these operations can be executed the register file can read or write two operands off chip the ALU can receive two operands the multiplier can receive two operands the ALU and multiplier can produce two results three if the ALU operation is a combined addition subtraction The processors 48 bit orthogonal instruction word supports parallel data transfer and arithmetic operations in the same instruction 1 3 3 3 Extended IEEE Floating Point Support All members of the ADSP 21000 family handle 32 bit IEEE floating point format 32 bit integer and fractional formats twos complement and unsigned and an extended precision 40 bit IEEE floating point format These processors carry extended precision throughout their computation units limiting intermediate data truncation errors The fixed point formats have an 80 bit accumulator for true 32 bit fixed point computations 1 3 3 4 Dual Address Generators The ADSP 210xx has two data address generators DAGs that provide immediate or indirect pre and post modify addressing Modulus and bit reverse operations are supported without constraints on buffer placement 1 3
7. als from noisy environments 1 3 24 Ease Of Use Ideally floating point digital signal processors should be easier to use and allow a quicker time to market than DSPs that do not support floating point formats If the floating point processor s architecture is designed properly designers can spend time on algorithm development instead of assembly coding code paging and error handling The following features are hallmarks of a good floating point DSP architecture consistency with IEEE workstation simulations elimination of scaling high level language C ADA programmability large address spaces wide dynamic range 133 Why ADSP 21000 Family The ADSP 21020 and ADSP 21060 are the first members of Analog Devices ADSP 21000 family of floating point digital signal processors DSPs The ADSP 21000 family architecture meets the five central requirements for DSPs Fast flexible arithmetic computation units Unconstrained data flow to and from the computation units Extended precision and dynamic range in the computation units Dual address generators Efficient program sequencing 1 Introduction 1 3 3 1 Fast amp Flexible Arithmetic The ADSP 210xx can execute all instructions in a single cycle It provides one of the fastest cycle times available and the most complete set of arithmetic operations including Seed 1 X Seed 1 R x Min Max Clip Shift and Rotate in addition to the traditional multiplication addition subtr
8. ar buffers 16 primary register sets 16 secondary The DAGs automatically handle address pointer wraparound reducing overhead increasing performance and simplifying implementation Circular buffers can start and end at any memory location e Flexible Instruction Set The ADSP 210xx s 48 bit instruction word accommodates a variety of parallel operations for concise programming For example in a single instruction the ADSP 210xx can conditionally execute a multiply an add a subtract and a branch Serial Scan amp Emulation Features The ADSP 210xx supports the IEEE standard P1149 Joint Test Action Group JTAG standard for system test This standard defines a method for serially scanning the I O status of each component in a system This serial port also gives access to the ADSP 210xx on chip emulation features 142 ADSP 21020 DSP The ADSP 21020 is the first member of the ADSP 21000 family It is a complete implementation of the family base architecture Figure 1 1 shows the block diagram of the ADSP 21020 and Figure 1 2 shows a system diagram Introduction 1 JTAG TEST amp EMULATION DAG 1 PROGRAM Bx 4x32 SEQUENCER FLAGS PM ADDRESS BUS 24 DM ADDRESS BUS 2 2 gt PM DATA BUS 2 Connect 40 DM DATA BUS 1 h REGISTER FILE 16 x 40 MULTIPLIER ALU Se 2 Selects OE PROGR
9. csimiles may be sent to 617 461 3010 e You may log in to the DSP Bulletin Board System 8 1 N 1200 2400 4800 9600 14 400 at 617 461 4258 24 hours a day e The files on the DSP BBS are also available by anonymous ftp at ftp analog com 132 71 32 11 inthe directory pub dsp e Postal mail may be sent to DSP Applications Engineering Three Technology Way PO Box 9106 Norwood MA 02062 2106 Technical support is also available for Analog Devices Authorized Distributers and Field Applications Offices 1 1 Introduction 1 2 6 ADSP 21000 Family Classes Applications Engineering regularly offers a course in ADSP 21000 family architecture and programming Please contact Applications Engineering for a schedule of upcoming courses 1 3 ADSP 21000 FAMILY THE SIGNAL PROCESSING SOLUTION 1 3 1 Why DSP Digital signal processors are a special class of microprocessors that are optimized for computing the real time calculations used in signal processing Although it is possible to use some fast general purpose microprocessors for signal processing they are not optimized for that task The resulting design can be hard to implement and costly to manufacture In contrast DSPs have an architecture that simplifies application designs and makes low cost signal processing a reality The kinds of algorithms used in signal processing can be optimized if they are supported by a computer architecture specifically designed for
10. t 32 register 16 primary 16 secondary register file combined with the ADSP 21000 Harvard architecture allows unconstrained data flow between computation units and memory e Single Cycle Fetch of Instruction amp Two Operands The ADSP 210xx features an enhanced Harvard architecture in which the data memory DM bus transfers data and the program memory PM bus transfers both instructions and data see Figure 1 1 With its separate program and data memory buses and on chip instruction cache the processor can simultaneously fetch two operands and an instruction from the cache in a single cycle e Instruction Cache The ADSP 210xx includes a high performance instruction cache that enables three bus operation for fetching an instruction and two data values The cache is selective only the instructions whose fetches conflict with PM bus data accesses are cached This allows full speed execution of looped operations such as digital filter multiply accumulates and FFT butterfly processing 1 Introduction Data Address Generators with Hardware Circular Buffers The ADSP 210xx s two data address generators DAGs implement circular data buffers in hardware Circular buffers let delay lines and other data structures required in digital signal processing be implemented efficiently circular buffers are commonly used in digital filters and Fourier transforms The ADSP 210xx s two DAGs contain sufficient registers for up to 32 circul
11. them In order to handle digital signal processing tasks efficiently a microprocessor must have the following characteristics fast flexible computation units unconstrained data flow to and from the computation units extended precision and dynamic range in the computation units dual address generators efficient program sequencing and looping mechanisms 1 3 2 Why Floating Point A processor s data format determines its ability to handle signals of differing precision dynamic range and signal to noise ratios However ease of use and time to market considerations are often equally important 1 3 2 1 Precision The precision of converters has been improving and will continue to increase In the past few years average precision requirements have risen by several bits and the trend is for both precision and sampling rates to increase Introduction 1 3 2 2 Dynamic Range Traditionally compression and decompression algorithms have operated on signals of known bandwidth These algorithms were developed to behave regularly to keep costs down and implementations easy Increasingly the trend in algorithm development is to remove constraints on the regularity and dynamic range of intermediate results Adaptive filtering and imaging are two applications requiring wide dynamic range 1 3 2 3 Signal To Noise Ratio Radar sonar and even commercial applications like speech recognition require a wide dynamic range to discern selected sign
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