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7721 Group USER`S MANUAL

1. 17 56 7721 Group User s Manual APPENDIX Appendix 7 Hexadecimal instruction code table INSTRUCTION CODE TABLE 2 The first word s code of each instruction is 4216 Hexadecimal notation ORA ORA ORA ORA B SR B DIR B L DIR B IMM B ABS ORA ORA ORA ORA ORA B SR Y B DIR X B L DIR Y B ABS Y B ABS X AND AND AND AND AND B SR B DIR B L DIR B IMM B ABS AND AND AND AND AND SR Y B DIR X B L DIR Y B ABS Y B ABS X EOR EOR EOR B DIR B IMM B ABS EOR EOR EOR B DIR X B ABS Y B ABS X ADC ADC ADC B DIR B IMM B ABS ADC ADC ADC B DIR X B ABS Y B ABS X STA STA STA B DIR B L DIR B ABS STA STA STA STA B DIR X B L DIR Y B ABS Y B ABS X LDA LDA LDA LDA B DIR B L DIR B IMM B ABS LDA LDA LDA LDA B DIR X B L DIR Y B ABS Y B ABS X CMP CMP CMP CMP B DIR B L DIR B IMM B ABS CMP CMP CMP CMP B DIRX B L DIR Y B ABS Y B ABS X SBC SBC SBC SBC B DIR B L DIR B IMM B ABS SBC SBC SBC SBC B DIR X B L DIR Y B ABS Y B ABS X 7721 Group User s Manual 17 57 APPENDIX Appendix 7 Hexadecimal instruction code table INSTRUCTION CODE TABLE 3 The first word s code of each instruction is 8916 Hexadecimal notation 17 58 7721 Group User s Manual APPENDIX Appendix 8 Countermeasure against nois
2. U 6 2 W NA ASS s S s s s 6 3 6 2 2 Port LeGiSter c ececececscscceececceesescscscscecscscececevecscevevecsvavevevavsvevevevecevevevecevevecevereseseeesesereees 6 4 6 7 CHAPTER 7IINTERRUPTS EM O V AERE 7 2 7 4 7 3 ITO TU MC n o dEMCIDIMM UIT 7 5 ii 7721 Group User s Manual Table of contents CHAPTER 8 TIMER A 9 2 3 Timer Bi mode reCiSterh cccccccccecececcccecccecececacceceenenececececacacuuacauaesensnetstsceuaeauaenenens n 9 6 9 2 5 Pol P5 dilection FOCI SI SIT uu yu uuu uyaauamyliysahasisashus aaa bud eso pe eti Ri 9 7 u 9 8 9 10 9 93 2 COLE SOL C u Z uu ussumupaunamushumssanaunsizasassasnasshasaqay QapasasazywpisasuaQususauysaasayBasanuasusu 9 11 PE PE 2 S 55 n UU 9 12 X E 9 13 te ee ee eee se ee se le EN sn nb esse A ea 9 14 asss s n 9 16 usss E ee 9 17 Precautions for event coutner model l 9 18 7721 Group User s Manual iii Table of contents 10 2 3 Port P6 CIBUS Sd T H 10 6 10 2 4 Timers AO and Alfa ccccccccccccccccccccccececccecucecececenucuneaeauacseeeeueneneneneneauausustanenenenenss 10 6 10 3
3. 2 17 2 17 k AMNEM 2 18 2 5 Bus access qr W b a U rd docu f UR LR 2 23 CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES 3 4 1 Operation GESCIIDTION cccccccccececcccccecccececececececauaeaenecenecscacecuuaeaeaenenecscecsteuenauaeaeners Precautions for Hold function 7721 Group User s Manual j Table of contents CHAPTER A4 RESET 4 1 Hardware resell U u u u 4 2 5 55 5 5555 E 5 s 4 3 u 4 4 sas EE 4 11 uns 4 12 WINMNENENICUNENNC 4 13 5 2 V 5 2 5 1 2 Externally generated clock input examplel 5 2 ees a SS E NEEN 5 s s 5 3 5 2 1 Clocks generated in clock generating circuitl 5 4 PA e E AE C 5 5 S S Kf RD n s 5 5 RET r UW 5 8 PEEENENMNMMMMMgg gRRAA A AEAA N df 5 9 IOS SK So 5 9 Precautions for Wait mode l aa a arar ssss 5 11 CHAPTER 6 INPUT OUTPUT PINS einese ee cat Q Vouno 6 2 6 2 Programmable I O potrtsl
4. 16 1 Memory connection 16 2 Examples of using DMA controller 16 3 Comparison of sample program execution rate APPLICATION 16 1 Memory connection This chapter describes application Application shown here is just examples The user shall modify them according to the actual application and test them 16 1 Memory connection This section shows examples for memory and I O connection Refer to CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES for details about the functions and operations of used pins when connecting a memory or I O Refer to section Appendix 11 Electrical characteristics for timing requirements of the microcomputer 16 1 1 Memory connection model For the M37721 the level of the external data bus width select signal makes it possible to select the memory connection model from the four models listed in Table 16 1 1 1 2 3 4 Minimum model This is a connection model of which external data bus width is 8 bits and access space is expanded up to 64 Kbytes It is unnecessary to connect the address latch externally so this model gives priority to cost and is most suitable when connecting the memory of which data bus width is 8 bits Medium model A This is a connection model of which external data bus width is 8 bits and access space is expanded up to 16 Mbytes In this model the high order 8 bits of the external address bus Ass to A23 are multiplexed with the external data bus Therefore
5. O Instruction Queue Buffer Qo 8 8 QO W i 5 FO Instruction Queue Buffer Q1 8 Ke cO lt Memory control signal output A Instruction Register 8 x Ete Instruction Queue Buffer Q2 8 EENE M 5 c vlla Q a lt lt lt D zn 8 a M E l o g 3 Incrementer 24 D BO O c 7 yz mD s 24 gt c HE mom E B8 m Data Address Register DA 24 c E i oc cL m c r 5 O rO 3n o 9 a Or os 2 0 ui a o El Incrementer Decrementer 24 Si TATR O 0 m 2 g EM Program Counter PC 16 d gw C 5 gt Or gt l 5 2 TA 4 Program Bank Register PG 8 5 Oo 2 O a ag Data Bank Register DT 8 2 0 gt SO o _ n 3 l E o 1 5 O gt Input Buffer Register IB 16 o lt a amp O x au Pen dp S gt P Status Register PS 11 z rocessor Status Register 11 allelle I Bas oue A 5 gm pd ES gt i Direct Page Register DPR 16 O S E 5 E 5 8 5 baal a S E E E o aF Stack Pointer S 16 FF F Ei de o Lu or Index
6. Count source select bits b7 b6 0 0 f2 0 1 fie 1 0 fe4 1 1 f512 J Note For Timers AO and A1 set bits 0 to 5 to 0 Setting division ratio Timer AO register Addresses 4716 nm v WU d o Timer A1 register Addresses 4916 4816 Timer A2 register Addresses 4B16 4A16 YF Timer A register Addresses 4D s 41s N Timer A4 register Addresses 4F16 4E16 Can be set to 000016 to FFFFie n E Note The counter divides the count source frequency by n 1 Continue to Figure 8 3 3 on next page Fig 8 3 2 Initial setting example for registers relevant to timer mode 1 7721 Group User s Manual 8 1 1 TIMER A 8 3 Timer mode From preceding Figure 8 3 2 Setting interrupt priority level b7 bo _ 7 Timer Ai interrupt control register i 0 to 4 PLT Itt Addresses 7516 to 7916 Interrupt priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level J M Setting port P5 direction register b7 bO Port P5 direction register Address D1e TA2IN pin TA3IN pin TAAIN pin When gate function is selected set the bit corresponding to the TAjin pin to 0 Nec Setting count start bit to 1 b7 bO Count start register Address 4016 Timer AO count start bit Timer A1 count start bit Timer A2 count start bit Timer
7. Interrupt request of each peripheral function occurs Inputting DMA request signal to DMAREQi pin Software DMAO request bit Software DMA1 request bit 0 No request Software DMA2 request bit Software DMA3 request bit 1 Requested When writing 1 DMA request is generated F EEEE EEEE DMA transfer starts Fig 13 6 4 Initial setting example for registers relevant to repeat transfer mode 3 7721 Group User s Manual 13 65 DMA CONTROLLER 13 6 Repeat transfer mode 13 6 2 Operation in repeat transfer mode Figure 13 6 5 shows the operation flowchart of the repeat transfer mode and Figure 13 6 6 shows a timing diagram of the repeat transfer mode burst transfer mode For the cycle steal transfer mode refer to the following e All transfers except for the last 1 unit transfer Figure 13 8 12 Last 1 unit transfer Figure 13 8 13 Also refer to section 13 2 1 Bus access control circuit for the bus request sampling during transfer DMAi request bit 0 Only in cycle steal transfer mode 1 unit transfer Refer to section 13 4 Operation Burst Edge Burst Level L Cycle steal Requested DMAi request bit 0 BurstLevelH Cycle steal No request Burst Edge In burst transfer mode edge sense Burst Level L In burst transfer mode level sense with DMAREQi pin s input level L Burst Level H In burst transfer mode level sense with DMAREQIi pin s input level
8. Transfer destination s transfer start address 2 Transfer data s byte number 2 Next transfer parameter memory s start address 3 The above figure applies when 4 block transfer is performed 2 1 bus cycle transfer 4 bytes j Transfer source s transfer start address 1 Transfer data s byte number 1 Next transfer parameter memory s start address 2 Transfer data s byte number 3 address 3 Next transfer parameter memory s start address 4 gt Transfer data s byte number 2 Next transfer parameter memory s start address 3 e Transfer data s byte number 4 00000016 The above applies on the following conditions When data is transferred from memory to I O Transfer source s transfer start address 4 Transfer parameter P Transfer destination s transfer start address 4 address 4 last block N gt Transfer source s transfer start address 3 Transfer parameter Transfer source s transfer start address 2 Transfer parameter address 2 Transfer source s L Even address transfer start M address Transfer L Even address destination s transfer M start address Dummy data L Even address Transfer data s byte number H x90 q 104 S1e1eueaed 1eJsueJ Dummy data Next transfer L Even address parameter memorys M start address Dummy data Transfer source s transfer start address 2 Transfer parameter address 2 Transfer source s L
9. tsu DL E 2 30 tOEZ 0 20 tw RASH 60 min tw RASL 120 min tw CASL 55 min td E CASL 80 115 ta RW E 20 min lt gt lt gt R W Z MAo MAg A16 Do A23 D7 gt AC32 tPHL twcs 0 min tWCH 15 min gt AC32 tPHL gt r I gt lt th RAS RA 18 min owaddess J Column address lt gt gt td CA CAS 10 min th CAS CA 60 min mm o o gt tDH 15 min Specifications of MBM44400CJ 7 The others are specifications of M37721 Y th E DLQ 18 min Unit ns Fig 16 1 25 Timing chart for example of M5M44400CJ 1M X 4 bits connection external bus width z 8 bits 7721 Group User s Manual 16 29 APPLICATION 16 1 Memory connection 6 Example of DRAM connection external bus width 16 bits M37721 A16e Do A17 D1 A18 D2 A19 D3 A20 D4 A21 D5 Ae2 De A23 D7 As Ds A9 D9 A10 D10 A11 D11 A12 D12 A13 D13 A14 D14 A15 D15 BYTE XOUT _ 25 MHz AC157 M5M418160CJ 7 1 2 Make sure that the propagation delay time is within 20 ns Make sure that the propagation delay time is within 7 5 ns Memory map 00000016 00047F16 RAM area Not used 001FCO016 001FFF16 SFR area Not used M5M418160CJ Circuit condition DRAM area selec
10. Fig 11 3 10 Connection example 7721 Group User s Manual 11 27 SERIAL I O 11 3 Clock synchronous serial I O mode UARTi receive register Transfer clock gt UARTI receive buffer register Fig 11 3 11 Receive operation Receive enable bit Transmit enable bit Dummy data is set to UARTi transmit buffer register Transmit buffer q dy empty flag UARTIi transmit register UARTi transmit buffer register RTSi Received data taken in COCO OO Oe eo ee UARTi receive register gt UARTi receive buffer register UARTi receive buffer register is read out Receive complete flag LU e o 0 UARTi receive interrupt request bit 7t Cleared to 0 when interrupt request is accepted or cleared by software When the CLKi pin s input level is H satisfy the following conditions Transmit enable bit 1 Receive enable bit 1 fext Frequency of external clock Writing of dummy data to UARTi transmit buffer register The above timing diagram applies when the following setting conditions are satisfied External clock selected RTS function selected Fig 11 3 12 Example of receive timing when selecting external clock 11 28 7721 Group User s Manual SERIAL I O 11 3 Clock synchronous serial I O mode 11 3 6 Processing on detecting overrun error In the clock synchronous serial I O mode an overrun error can be detected An overrun error oc
11. 16 12 Precautions on memory connection As described in to below if specifications of the external memory do not match those of the M37721 some considerations must be incorporated into circuit design When using an external memory that requires a long access time When data is output from an external memory before falling edge of the E signal When using an external memory that outputs data for more than tpz e ouziouz after rising edge of the E signal When using external memory that requires long access time If the M37721 s tsupuon e Cannot be satisfied because the external memory requires a long access time try to carry out the following Lower f X Select software Wait is inserted Refer to section 3 2 Software Wait Use Ready function Refer to section 3 3 Ready function Figure 16 1 9 shows an example of using Ready function no software Wait Figure 16 1 10 shows an example of using Ready function software Wait Ready function is valid for the internal areas so that the circuits in Figures 16 1 9 and 16 1 10 use the chip select signal CS2 to specify areas where Ready function is valid In these cases the CS2 signal is externally generated 7721 Group User s Manual APPLICATION 16 1 Memory connection M37721 1 to 3 Make sure that the sum of propagation delay time is within As A Do Dis Data bus 15 ns s 3 to 5 Make sure
12. Do not select UART mode Transfer data length 7 bits UART mode Transfer data length 8 bits UART mode Transfer data length 9 bits Do not select Internal External clock select bit Internal clock External clock Stop bit length select bit One stop bit Valid in UART mode Note Two stop bits Odd Even parity select bit 0 Odd parity Valid in UART mode when 1 Even parity parity enable bit is 1 Note Parity enable bit Parity disabled Valid in UART mode Note Parity enabled Sleep select bit Sleep mode terminated Invalid Valid in UART mode Note Sleep mode selected Note Bits 4 to 6 are invalid in the clock Schone serial I O mode They may be either 0 or 1 Additionally fix bit 7 to 0 UARTO baud rate register Address 3116 UART1 baud rate register Address 3916 7 to 0 Can be set to 0016 to FF e Undefined WO Assuming that the set value n BRGi divides the count source frequency by n 1 Note Writing to this register must be performed while the transmission reception halts Use the LDM or STA instruction for writing to this register 7721 Group User s Manual 17 13 APPENDIX Appendix 3 Control registers UARTi transmit buffer register b15 b8 b7 bO b7 bO DS C UARTO transmit buffer register Addresses 3316 3216 UART1 transmit buffer register Addresses 3Bie 3A16 Transmit data is set
13. Timer B2 register 5516 5616 Timer A0 mode register 5716 Timer A1 mode register 5816 Timer A2 mode register 5916 Timer A3 mode register 5A16 Timer A4 mode register 5B16 Timer BO mode register 5C16 Timer B1 mode register 5D16 Timer B2 mode register 5E16 Processor mode register 0 5F1i6 Processor mode register 1 Notes 1 2 3 Always 0 at reading Always 1 at reading O Access characteristics Rw np Rw _ RW 9 Rw RW RW APPENDIX Appendix 2 Memory assignment in SFR area Nothing is assigned It is impossible to read the bit state The written value becomes invalid Always undefined at reading NS 0 immediately after reset Fix this bit to 0 State immediately after reset b7 bO oo oko ho 0 ebo OLA 0 0 0 0 0 0 ee 25 ZZ ZA The access characteristics at addresses 4A16 to 4F16 vary according to Timer A s operating mode Refer to CHAPTER 8 TIMER A The access characteristics at addresses 5016 to 5316 vary according to Timer B s operating mode Refer to CHAPTER 9 TIMER B The access characteristics for bit 5 at addresses 5B16 and 5C16 vary according to Timer B s operating mode Bit 5 at address 5D16 is invalid Refer to CHAPTER 9 TIMER B 0 Bit 1 at address 5F16 becomes 0 immediately after reset For the M37721S1BFP fix this bit to 7721 Group User s Manual 1
14. b b6 b5 b4 b3 b2 bli NENNEN ET DMAC control register L Address 6816 2 Fixed P t K bi a m TC pin validity bit Invalid es 0s pin functions as a programmable I O port CMOS 1 Valid m P103 pin functions as TC pin N channel open drain EDUC NNI EN Le meme Togas ERL Cs Pez ENLU ENL Notes 1 The state of bits 4 to 7 is not changed when writing 1 to these bits 2 When writing to this register while any of DMAi enable bits bits 4 to 7 at address 69 6 is 1 use the LDM or STA instruction in m flag 1 When DMAi request bit bits 4 to 7 at address 6816 must not be changed set DMAi request bit to 1 When writing to this register while all of DMAi enable bits bits 4 to 7 at address 69 6 are 0 m flag may be 0 or 1 Use the LDM or STA instruction for writing to this register When DMAi request bit bits 4 to 7 at address 6816 must not be changed set DMAi request bit to 1 Fig 13 2 4 Structure of DMAC control register L 13 10 7721 Group User s Manual DMA CONTROLLER 13 2 Block description 13 2 3 DMAC control register H Figure 13 2 5 shows the structure of DMAC control register H Each of bits 0 3 is a software DMAi i O to 3 request bit which corresponds to each channel When a software DMA source is selected as a DMA request source each of these bits is valid Refer to 13 3 2 DMA requests Bits 4 7 are described in section 13 3 1 DMA en
15. 15 to 0 These bits can be set to 000016 to FFFF e Undefined RW Assuming that the set value n the counter divides the count source frequency by n 1 When reading the register indicates the counter value Note Read from or write to this register in a unit of 16 bits b7 b6 b5 b4 b3 b2 bi Timer AO mode register Address 5616 T leTo o o o o Timer A1 mode register Address 57 6 SUN Fix these bits to 0 Se TERME Count source select bits b7 b6 00 fe 0 t fi6 a ee 10 fea 11 f512 b7 b6 b5 b4 b3 b2 bl Tol TT JoJo Timer Aj mode register j 2 to 4 Addresses 5816 to 5A 6 0 O Timer mode Pulse output function select bit O No pulse output TAjour pin functions as a programmable I O port 1 Pulse output TAjour pin functions as a pulse output pin b4 b3 0 0 No gate function 0 1 J TAj pin functions as a prog Gate function select bits rammable I O port 10 Counter counts only while TAjin pin s input signal is at L level 1 Counter counts only while TAjin pin s input signal is at H level b7 b6 00 fe 0 1 f16 1 0 fe4 1 1 f512 7721 Group User s Manual 17 19 APPENDIX Appendix 3 Control registers Event counter mode b15 b8 b7 bO b7 bO Timer A3 register Addresses 4D16 4C16 Timer A4 register Addresses 4F16 4E16 15 to 0 These bits can be set to 000016 to FFFF e Undefined RW Assuming that the set valu
16. 5 10 When an interrupt request occurs supply of cpruand 6 starts The interrupt request which occurred in is accepted The following interrupts are used to terminate Wait mode When a watchdog timer interrupt request occurs Wait mode is also terminated INTi interrupt i O to 2 eTimer Ai interrupt i O to 4 eTimer Bi interrupt i O to 2 eUARTi transmit interrupt i 0 1 UAHRTI receive interrupt i 0 1 A D converter interrupt Note Refer to CHAPTER 7 INTERRUPTS and each functional description about interrupts Before executing the WIT instruction interrupts used to terminate Wait mode must be enabled In addition the interrupt priority level of the interrupt used to terminate Wait mode must be higher than the processor interrupt priority level IPL of the routine where the WIT instruction is executed When multiple interrupts listed above are enabled Wait mode is terminated by the interrupt request which occurs first Termination by hardware reset The CPU and the SFR area are initialized in the same way as system reset However the internal RAM area retains the same contents as that before executing the WIT instruction The terminating sequence is the same as the internal processing sequence which is performed after reset Refer to CHAPTER 4 RESET for details about reset 7721 Group User s Manual CLOCK GENERATING CIRCUIT 5 4 Wait mode Precautions for Wait mode When ex
17. 8 P57 TB1in lt gt 9 P5e TBOm lt gt 10 P55 TA4in lt gt 11 P54 TA4our lt gt P53 TA3in lt gt 13 P52 TASout lt gt P51 TA2in lt gt 15 P5o TA2out lt gt P107 MAs lt gt P106 MAs lt gt P10s RAS lt gt P104 CAS lt gt P103 TC lt gt P102 INT2 lt gt 22 P10 INT lt gt 23 Ao MAo O N N N E S e N UJ Tl U P10vINTo 24 lt gt Ai4 Di4 P47 lt gt 25 lt gt Ais Dis P4 lt gt lt gt Aie Do P45 lt gt lt gt 7 D P4 lt gt 28 lt gt Ais D2 P4 lt gt lt gt A 9 Ds i lt 89 Outline 100P6S A Fig 1 2 1 M37721S2BFP pin configuration top view 7721 Group User s Manual 80 lt gt P8z TxD lt gt P9y DMAACKO lt gt P9i DMAREQO lt gt P92 DMAACK1 lt gt P93 DMAREGQ f lt gt P9 DMAACK2 lt gt P9 DMAREQ2 lt gt P9e DMAACK3 lt gt P9JDMAREQS DESCRIPTION 1 3 Pin description 1 3 Pin description Tables 1 3 1 to 1 3 3 list the pin description Table 1 3 1 Pin description 1 Pin Name Input Output Functions Vcc Vss Power supply Supply 5 V 10 to Vcc pin and O V to Vss pin CNVss CNVss Input Connect to Vss or Vcc pin RESET Reset input Input The microcomputer is reset when supplying L level to this pin RESETout Reset output Output When input to RESET pin is L this pin outputs L Output from this pin returns H after the release of
18. But when writing 1 to this bit this bit does not change Address Register name 6016 Watchdog timer register 6116 Watchdog timer frequency select register 6216 Real time output control register 6316 6416 DRAM control register 6516 6616 Refresh timer 6716 6816 DM AC control register L 6916 DMAC control register H 6A16 6B16 6C16 DMAO interrupt control register 6D16 DMA1 interrupt control register 6E16 DMA2 interrupt control register 6F16 DMAS interrupt control register 7016 A D conversion interrupt control register 7116 UARTO transmit interrupt control register 7216 UARTO receive interrupt control register 7316 UARTI transmit interrupt control register 7416 UART1 receive interrupt control register 7516 Timer AO interrupt control register 7616 Timer A1 interrupt control register 7716 Timer A2 interrupt control register 7816 Timer A3 interrupt control register 7916 Timer A4 interrupt control register 7A16 Timer BO interrupt control register 7Bi6 Timer B1 interrupt control register 7C16 Timer B2 interrupt control register 7D16 INTo interrupt control register TE16 INT interrupt control register TF16 INT2 interrupt control register Notes 5 17 6 7721 Group User s Manual Access characteristics RW It is possible to read the bit state at reading The written value becomes valid RO It is possible to read the bit state at reading The written value becomes invalid wo The written value becomes valid It is imposs
19. Fig 16 1 19 Timing chart for example of flash memory and SRAM connection maximum model 16 23 7721 Group User s Manual APPLICATION 16 1 Memory connection 3 Example of DRAM connection external bus width 8 bits M37721 M5M44800CJ 7 x Make sure that the propagation delay time is within 80 ns gt a c N gt Memory map 00000016 SFR area 00047F16 RAM area gt p gt gt gt gt gt gt gt X 6 amp cO JJ gt op Not used 001FFF16 ace O zio CoD A16 Do A17 D1 Ais D2 A19 D3 A20 D F00000 Acus IDRAM area A23 D u FFFFFF16 BYTE XOUT Not used Circuit condition DRAM area select bits bits 3 to 0 at address 6416 00012 Fig 16 1 20 Example of M5M44800CJ 512K X 8 bits connection external bus width 8 bits 16 24 7721 Group User s Manual APPLICATION 16 1 Memory connection lt When reading gt E tw EL 135 min OE RAS i tw RASL 120 min a tw RASH 60 min td RAS CAS 28 min td E RASL 30 max lt _ gt gt ARE td E CASL 77 5 max bw tw CASL 92 5 min CAS gt td RA RAS 5 min gt gt gt td CA CAS 5 min MAo MAg tOEA 20 max tAA 35 max tRAC 70 max A16 Do T J Aus cee sag rou dan tCLz 5 min lt td E CA 60 max gt lt lt lt
20. I O port P8 I O port P9 I O port P10 I O Port P4 is a 5 bit CMOS I O port This port has an I O direction register and each pin can be programmed for input or output Port P5 is an 8 bit I O port with the same function as P4 These pins can be programmed as I O pins for Timers A2 A4 and I O pins for Timers BO B1 Port P6 is an 8 bit I O port with the same function as P4 These pins can be programmed as output pins for the real time output Port P7 is an 8 bit I O port with the same function as P4 These pins can be programmed as input pins for A D converter Port P8 is an 8 bit I O port with the same function as P4 These pins can be programmed as I O pins for Serial I O Port P9 is an 8 bit I O port with the same function as P4 These pins can be programmed as I O pins for DMA controller Port P10 is an 8 bit I O port with the same function as P4 These pins can be programmed as I O pin for TC and output pins for DRAM controller P100 P102 also function as input pins for INTo INTe 7721 Group User s Manual DESCRIPTION 1 4 Block diagram 1 4 Block diagram Figure 1 4 1 shows the M37721 block diagram S ry S F O lt 2 3 BT Data Bus Even Cy o 252i E ame S EO T Data Bus Odd us mmis o Oo Data Buffer DBH 8 2 E C s Q Data Buffer DBL 8 lt LE ata Buffer L Address Bus M K E Or Lu
21. SJojeureJed JejsueJ JO JejsueJ Add OWN amp fido 9 Alowsaw JejeueJed 1eJsueJ S 4OO q 1S1IJ Jo sseJppe els uo 9 sJejeujejed jojsueJ ON ON pJeM04 pJeAu0J sung JoJsueJ o oKo snq z sq 91 SIIg 91 suonipuoo Buiwojo y uo sei dde ajdwexe siu e JejeueJed JejsueJ JO JoJsueJ sng esn 0 1uBu JO UOHlnISUEJ lt p snq sn o y iy anjea S HOL d Zep Lep Zes pes yem uoneursep J98JSUeJ eM NOS J9JSUEJ UOnoeuJip SSeuppe uorpeurisep JeJSueJ UOInoeJlp sseJppe eoJnos JeJsueJ epouu J8JSUeJ pouleuJ JeJSueJ yun JejsueJ UIpIM snq ejep euJ9 x3 OLS LIS L MOVVANG Dui dures sanba sng LQ eN 0Q0 9 V si g s i y eg ev ANJ 0V transfer mode burst transfer mode 1 In f array cha iagram o d iming Fig 13 7 7 T 13 77 7721 Group User s Manual DMA CONTROLLER 13 7 Array chain transfer mode snq esn oi 1uBu JO UONISUBL lt P i M E es AhY 9 els JoJSueJ 9jejs Aey 9 ElS JOJSUEJ 8 i p Buisseooud ejeuiuuo p pp JO J JSUPI OLS LIS Ndo L L L I4OVVIAG Dui dures 1senboij sng Lq eev oQq 9 V sIq siv 8sq ev V 0V MH 44 4L E aanbiy 6uipeeooJd woy Fig 13 7 8 Timing diagram of array chain transfer mode burst transfer mode 2 7721 Group User s Manual 13 8 DMA CONTROLLER
22. 10 3 Setting of real time output z From preceding Figure 10 3 1 Processing of avoiding undefined output before starting pulse output Note UN b7 b0 o o ojolo o o o Timer AO mode register Address 56 6 Timer A1 mode register Address 5716 E Select of count source fe b15 b8 b7 bO b7 bO i s O Ty 0016 Timer A1 register Addresses 4916 4816 NL _ L Set to 000016 Timer AO interrupt control register Address 7516 Timer A1 interrupt control register Address 7616 Interrupt disabled No interrupt request b7 bO Count start register Address 4016 Timer AO count start bit 1 Start counting Timer A1 count start bit When Timer AO or A1 underflows the contents of the pulse output data register 0 or 1 are output from the flip flop b7 b0 Count start register Address 4016 Timer AO count start bit 0 Stop counting Timer A1 count start bit Note This processing can be neglected if the system is not affected by undefined output Setting Timers AO A1 b7 bO oloo ooo Timer AO mode register Address 5616 L Timer A1 mode register Address 5716 a Count source select bits b7 b6 0 0 fe 0 1 f16 1 0 fea 1 1 f512 b15 b8 b7 bO b7 bO Timer AO register Addresses 4716 4616 iri a ae p R Can be set to 000016 FFFF16 n b7 b0 TT To T T Timer A
23. 1F C816 1FD21e 1FD0 e 1FD6 e 1FD4 e 1FDAice 1F D816 1FE21e 1FEO0 6 1FE6 e 1FE4 6 1FEA16 1F E816 1FF216 1FFOi6 1FF6 e 1FF4 16 1FFA e 1FF8 6 Oo MP O 13 12 7721 Group User s Manual DMA CONTROLLER 13 2 Block description Table 13 2 5 Functions of SARi DARi and TCRi Single transfer mode Repeat transfer mode Array chain transfer Link array chain Register mode transfer mode SARi SARi Indicates the transfer source address of the data to be transferred next SARi latch Maintains the transfer start address of the Indicates the start address of the transfer source parameter memory of the next block DARI DAR Indicates the transfer destination address of the data next to be transferred DARi latch Maintains the transfer start address of the Not used Not used destination TCRi TCR Indicates the number of remaining bytes of the block under transfer LN latch Maintains the byte number of the transfer Indicates the number Not used Note data of remaining blocks Note Any value other than 0 000001 e FFFFFF e must be written before DAM transfer 13 2 7 Incrementer Decrementer The incrementer decrementer is a 24 bit register After every 1 unit transfer that increments adds or decrements subtract the contents of SARi and DARi Table 13 2 6 lists the increment decrement values Table 13 2 6 Increment Decrement values Address directions Transfer unit Backward 16 bits 2 13 2 8 Decreme
24. 2 ws corresponding bit to 0 Ce ween Bits 3 to 7 are not used for external interrupts Fig 7 10 2 Relationship between port P10 direction register and input pins of external interrupt 7721 Group User s Manual 19 INTERRUPTS 7 10 External interrupts INTi interrupt 7 10 1 Functions of INTi interrupt request bit 1 Functions when edge sense is selected The interrupt request bit has the same functions as that of an internal interrupt That is when an interrupt request occurs the interrupt request bit is set to 1 and retains this state until the interrupt request is accepted When this bit is cleared to 0 by software the interrupt request is cancelled when this bit is set to 1 by software the interrupt request can be generated 2 Functions when level sense is selected The INTi interrupt request bit is ignored Interrupt requests continuously occur while the level of the INTi pin is the valid level when the INT pin s level changes from the valid level to the invalid level before the INT interrupt request is accepted this interrupt request is not retained Refer to Figure 7 10 4 Valid level This means the level selected by the polarity select bit bit 4 at addresses 7D e to 7Fie Invalid level This means the reversed level of valid level Level sense Edge sense E 0 select bit INTi pin Ps Interrupt request bit O So Interrupt request O Fig 7
25. 7700 SERIES Renesas Electronics WWW renesas com New publication 199709 keep safety first in your circuit designs Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with appropriate measures such as i placement of substitutive auxiliary circuits ii use of non flammable material or iii prevention against any malfunction or mishap Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Mitsubishi Electric Corporation or a third party Mitsubishi Electric Corporation assumes no responsibility for any damage or infringement of any third party s rights originating in the use of any product data diagrams charts or circuit application examples contained in these materials All information contained in these materials including product data diagrams and charts represent information on products at ine time of publication of these materials and are subject to change by Mits
26. 9VIN SV SVIN SV PVIW rV evIN v ev N ev WW V 0VIW 0V COSYVING 46d MOVVING 96d cO3dVINg S6d CMOVVING 6d LO3uVING 6d LM9VVINQ 6d OOSYVING 6d OMOVVING 6d Ix L 8d Lo Q N lt m LS lt gt cS lt gt 6S lt gt tS lt 12 lt gt 2 lt gt 4 lt gt v lt gt SZ lt gt 94 lt gt 4 lt gt 84 lt gt 62 lt 08 ie coles A xo x SE c om cO OD A Aje O co A P81 CLKo lt gt 8 P82 RxDo lt gt P8o CTSo RTSo gt P83 TxDo lt gt 3 EE o O O o 5 Z 3 s Pr 88 3 Ze ss oo mm ES islee fos re ze ree ve se o6 ze se eo po oouool222z22zz2 gt gt gt gt lt lt lt lt lt lt lt 7X D suzsu s amp poomom omo Saagaanaan a M37721S2BFP O Ea E Oc 61 Eq rm 91 GI E En EB m 01 6 8 2 9 S v E z 1 External address bus external data bus L 0 lt gt td Vyd lt gt Syd lt gt Vd lt gt rd lt gt 0LNI 00 Ld lt gt LLNI LO Ld lt gt 6 NI 20 Ld lt gt OLl 0Ld lt gt SVO OLd lt gt SVU S0ld lt gt 8VIN 90ld lt gt 6VIN 40ld lt gt 1N0 V1 9 Gd lt gt NIV L Sd lt gt INOEV1 eSd lt gt NISY L Gd lt gt 1n OpV Lr Sd lt gt NIPV1L SSd lt gt NI0g1 9Sd lt gt NIL 1L 2Sd lt gt 00d 1H 09d lt gt 0d1H 9d
27. Fig 16 1 23 Timing chart for example of M5M417800CJ 2M X 8 bits connection external bus width 8 bits 7721 Group User s Manual 16 27 APPLICATION 16 1 Memory connection 5 Example of DRAM connection external bus width 8 bits M37721 M5M44400CJ 7 M5M44400CJ 7 Make sure that the propagation delay time is within 80 ns A c m Memory map 00047F16 _ RAM area 00000016 oN O A A A A A5 A A A A E A16 Do A17 D1 A18 D2 A19 D3 A20 D4 M5M44400CJ A21 D5 A22 D6 A23 D7 XOUT Circuit condition DRAM area seleci bits bits 3 to 0 at address 6416 00012 Fig 16 1 24 Example of M5M44400CJ 1M X 4 bits connection external bus width 8 bits 16 28 7721 Group User s Manual APPLICATION 16 1 Memory connection lt When reading gt 9 mim RAS CAS MAo MAg A16 Do Address Lo sss stascusebusabasassqsukanaqpihasasmaq peered lt lt When writing gt m RAS CAS tw EL 135 min tw RASL 120 min tw RASH 60 min td RAS CAS 28 min td E RASL 30 max 2 td E CASL 77 5 max lt tw CASL 92 5 min Lc E RA RAS 5 min gt gt id CA CAS 5 min tOEA 20 max tAA 35 max tRAC 70 max td E CA 60 max tCLZ 5 min tCAC 20 max tw EL 135 min
28. INTERRUPTS 7 8 Return from interrupt routine 7 9 Multiple interrupts 7 8 Return from interrupt routine When the RTI instruction is executed at the end of the interrupt routine the contents of the program bank register PG program counter PC and processor status register PS which were pushed onto the stack area just before the INTACK sequence are automatically pulled After this the control returns to the original routine And then the suspended processing which was in progress before the acceptance of the interrupt request is resumed Before the RTI instruction is executed pull registers which were pushed by software in the interrupt routine using the PUL instruction etc 7 9 Multiple interrupts Just after a branch is made to an interrupt routine the following occur Interrupt disable flag 1 1 Interrupts are disabled eInterrupt request bit of accepted interrupt 0 Processor interrupt priority level IPL Interrupt priority level of accepted interrupt Accordingly as long as the IPL remains unchanged an interrupt request whose priority level is higher than that of the interrupt which is in progress can be accepted by clearing the interrupt disable flag I to 0 in an interrupt routine In this way multiple interrupts are processed Figure 7 9 1 shows the processing for multiple interrupts An interrupt request which has not been accepted because its priority level is lower is held When
29. UARTO receive buffer register Address 3616 UART1 receive buffer register Address 3E16 b7 bO N J ic 1 Receive data is read out from here Checking error UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 Overrun error flag b7 b0 SK 0 No overrun error 1 Overrun error detected Note This figure shows the bits and registers required for processing Refer to Figure 11 3 12 for the change of flag state and the occurrence timing of an interrupt Processing after reading out receive data request Fig 11 3 9 Processing after receive completion 11 26 7721 Group User s Manual SERIAL I O 11 3 Clock synchronous serial I O mode 11 3 5 Receive operation In the case of selecting an internal clock when the receive conditions described in section 11 3 4 Method of reception are satisfied a transfer clock is generated and the reception is started after 1 cycle of the transfer clock has passed In the case of selecting an external clock when the receive conditions are satisfied the UARTi enters the receive enable state and reception is started by input of an external clock to the CLKi pin In the case of selecting an external clock and the RTS function when the UARTIi enters the receive enable state the RTSi pin s output level becomes L to inform the transmitter side that reception is enabled
30. Y Timer AO register s address b23 b16b15 b8b7 b0 Transfer counter register 2 Addresses 1FEA16 to 1FE816 MEN Data number of Timer AO set value data table b7 bO 0 0 0 0 1 1 DMA2 control register Address 1FEE16 s DMA request source Timer AO DMAACK2 pin Invalid b7 bO ol l DMA2 interrupt control register Address 6E16 Interrupt priority level any of 0012 to 1112 X It may be O or 1 Fig 16 2 9 Initial setting example for relevant register 2 7721 Group User s Manual 16 51 APPLICATION 16 2 Examples of using DMA controller 7 b Port P6 register Address E16 RTPOo P6o RTPO3 P653 initial output H level b7 bO Port P6 direction register Address 1016 RTP0o P60 RTP03 P63 pin Output mode b7 bO TTT LIT DIL LG ELI Pulse output data register 0 Address 1416 LE First phase output data b7 bO 0 0 X 0 0 0 Timer AO mode register Address 56 6 Y Count source b7 bO de o t Real time output control register Address 6216 Te RTPO Pulse mode 0 b15 b8b7 bO Timer AO register Addresses 4716 4616 I First step time b7 bO Pf EL gd tp yy Count start register Address 4016 Timer AO count start b7 bO Jolo DMAC control register L Address 6816 DMA1 request bit t to 0 DMA2 request bit onan ha b7 bO DIT DMAC control register H Address 6916
31. at an underflow or 0000 16 at an overflow is read out If reading is performed in the period from when a value is set into the timer Aj register with the counter stopped until the counter starts counting the set value is correctly read out 1 For countdown 2 For countup Reload Reload C 9 Ta Ta Ie e Te 22825 propre ee Tes Read value gt 1 T T1 Read value 3 1 1 we 2 1 o FEF n i SC He _ FFFD FFFE FFFF 0000 Jdre Time Time n Reload register s contents n Reload register s contents Fig 8 4 9 Reading timer Aj register 2 The TAjour pin is used for all functions listed below Accordingly only one of these functions can be selected for each timer Switching between countup and countdown by TAjour pin s input signal Pulse output function wo phase pulse signal processing function 8 28 7721 Group User s Manual TIMER A 8 5 One shot pulse mode 8 5 One shot pulse mode In this mode the timer outputs a pulse which has an arbitrary width once Refer to Table 8 5 1 Timers A2 to A4 can be used in this mode When a trigger occurs the timer outputs H level from the TAjour pin for an arbitrary time Figure 8 5 1 shows the structures of the timer Aj mode register and timer Aj register in the one shot pulse mode Table 8 5 1 Specifications of one shot pulse mode Item Specifications Count source f2 f16 fe4 or f512 Count op
32. e Backward direction an address moves downward from the specified start address For details refer to section 13 4 1 3 Address directions in 2 bus cycle transfer and section 13 4 2 3 Address directions in 1 bus cycle transfer DMAO mode register L Address 1FCCte b7 b6 b5 b4 b3 b2 bi bO ister L rT FF Jol FT oma2 mode revister L nacre FECI DMAS mode register L Address 1FFCte Number of unit transfer bits 0 16 bits RW select bit Note 1 8 bits 1 Transfer method select bit 0 2 bus cycle transfer RW 1 1 bus cycle transfer 2 Transfer mode select bit 0 Burst transfer mode RW 1 Cycle steal transfer mode eU w m Transfer source address b5b4 direction select bits 0 0 Fixed 0 1 Forward 1 0 Backward 1 1 Do not select Transfer destination address b7b6 I I 00 Fixed direction select bits 0 1 Forward 1 0 Backward 1 1 Do not select Note When the external data bus has a width of 8 bits and 1 bus cycle transfer is selected set bit O to 1 Fig 13 2 6 Structure of DMAi mode register L 13 14 7721 Group User s Manual DMA CONTROLLER 13 2 Block description 13 2 11 DMAi mode register H Figure 13 2 7 shows the structure of DMAi mode register H Bits O and 1 are used in 1 bus cycle transfer For details refer to section 13 4 2 1 bus cycle transfer Bits 6 and 7 are the bits for selecting the continuous transfer mode For details refer to section 13 5
33. u tw EL 2 135 min E tw RASH 60 min tw RASL 120 min RAS K tw CASL 55 min CAS gt td E CASL 80 115 lt gt td R W E 20 min gt R W ACS32 tPHL E C32 tPHL twcs 0 min tWCH 10 min W td RA RAS 5 min lt Ttth RAS RA 18 min MAo MAg A16 D0 A23 D7 A8 D8 A15 D15 Row address Column address lt td CA CAS 10 min th CAS CA 60 min wm J gt tDH 15 min th E DLQ DH Specifications of M5M417800CJ 7 The others are specifications of M37721 Unit ns Y Y 18 min Fig 16 1 31 Timing chart for example of M5M417800CJ 2M X 8 bits connection external bus width 16 bits 7721 Group User s Manual 16 35 APPLICATION 16 1 Memory connection 9 Example of DRAM connection external bus width 16 bits M5M44400CJ 7 M37721 o Make sure that the propagation delay time is within 40 ns Co m O1 P gt P gt gt gt gt gt gt gt o A Memory map 00008016 Internal 00047F1e RAM area 00000016 BHE Not used A16 D0 001FC016 A17 D1 001FFF16 A18 D2 A19 D3 A20 D4 Not used SFR area A22 D6 A23 D7 M5M4400CJ A10 D10 A11 D11 A12 D12 A13 D13 A14 D14 A15 D15 Circuit condition DRAM area select bits bits 3 to 0 at address 6416 00102 Fig 16 1 32 Example of M5M44400CJ 1M X 4 bits connection external bus widt
34. 0 TB1 pin J Setting count start bit to 1 b7 bO Count start register Address 401e Count starts Timer BO count start bit Timer B1 count start bit Ne A Fig 9 4 2 Initial setting example for registers relevant to event counter mode 9 16 7721 Group User s Manual TIMER B 9 4 Event counter mode 9 4 2 Operation in event counter mode When the count start bit is set to 1 the counter starts counting of the count source s valid edges When a counter underflow occurs the reload register s contents are reloaded and counting continues The timer Bj interrupt request bit is set to 1 at the underflow in The interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to O by software Figure 9 4 3 shows an example of operation in the event counter mode n Reload register s contents FFFF16 Starts counting Stops counting I J I I I I Counter contents Hex 000016 Cleared to 0 t Set to 1 by software software Set to 1 by software gt Count start bit Timer Bj interrupt request bit I Cleared to 0 when interrupt request is accepted or cleared by software Fig 9 4 3 Example of operation in event counter mode 7721 Group User s Manual 9 17 TIMER B 9 4 Event counter mode Precautions for event cou
35. 0 in that bit O z UJ alaja J J 8 TEE j j e Makes the contents of the V flag 0 amp 2 CMP Acc M Compares the contents of the accumulator with the con Notes 1 2 tents of the memory 17 42 7721 Group User s Manual APPENDIX Instructions Ine Ins Appendix 6 Mach Processor status register Addressing modes E T O 18 jea Ah fe Oo Teo es e e o n o elna SS e e js s a es gt E PN wee pee c e eee e e pe s he 4 sc ie ia CS ja C s S 25 ee ee s E GENS tx emee Je je Jes uos rupe i e jue qoe spes qom o Be Le Fs Se a a CNN EN EN ee ee ee Ee Ee e ee g as Fel C NN CNN CUR CNRC CR 5 5 sS S 3 2 5 L Pee ee pee e zi zZz E G 2 m ues a gt soe pene s or oe S ae ee cnn LF wje lea pe pe dee e gt Ts e pe Ee 1 puc ue ec Tg ope qu oe 5 2 m er EN geb qp m 1 T1 m qq gp d mp m Wm F 3 LET C j F Co olx i h T F P S a P Pa T9 e ele 2 oe ep a o s e ee u sal Pw B 98 e e s o L L L L L L L L Pa 9 gjeje re e I Weer h 1 j 3 KACH 958 ses jsa L opo j j 8 98 eje L Le Le T L L L L L L e j o N NW 1 T pp nog ED
36. 1 7721 Group User s Manual SERIAL I O 11 2 Block description 11 2 3 UARTI transmit receive control register 1 Figure 11 2 4 shows the structure of UARTi transmit receive control register 1 For bits 4 to 7 refer to section 11 3 6 Processing on detecting overrun error and 11 4 7 Processing on detecting error b7 b6 b5 b4 b3 b2 bl l l f UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 Bitname Bitname Functions At reset reset RW LE enable bit T disabled ransmission enabled Transmit buffer empty flag 0 Data present in transmit buffer register 1 No data present in transmit buffer register Receive enable bit T Reception disabled Reception enabled Receive complete flag 0 d wy In receive uffer register 1 Data present in receive buffer register 4 Overrun error flag Note 1 0 No overrun error 1 Overrun error detected 5 Framing error flag Notes 1 2 No framing error Valid in UART mode Framing error detected Parity error flag Notes 1 2 D No parity error Valid in UART mode Parity error detected Error sum flag Notes 1 2 i No error Valid in UART mode Error detected Notes 1 Bit 4 is cleared to 0 when the receive enable bit is cleared to 0 or when the serial I O mode select bits bits 2 to 0 at addresses 3016 3816 are cleared to 0002 Bits 5 and 6 are cleare
37. 1 Transmission completed J hecking completion of transmission q Processing at completion of transmission p Fig 11 4 5 Detection of transmit completion 7721 Group User s Manual 11 37 SERIAL I O 11 4 Clock asynchronous serial I O UART mode 11 4 4 Transmit operation When the receive conditions described in section 11 4 3 Method of transmission are satisfied a transfer clock is generated and the following operations are automatically performed after 1 cycle of the transfer clock has passed he UARTi transmit buffer register s contents are transferred to the UARTi transmit register he transmit buffer empty flag is set to 1 he transmit register empty flag is cleared to 0 eA UARTI transmit interrupt request occurs and the interrupt request bit is set to 1 The transmit operations are described below Data in the UARTi transmit register is transmitted from the TxDi pin This data is transmitted bit by bit sequentially in order of ST DATA LSB 5 DATA MSB PAR SP according to the transfer data format The transmit register empty flag is set to 1 at the center of the stop bit or the second stop bit when selecting 2 stop bits indicating completion of transmission Additionally whether the transmit conditions for the next data are satisfied or not is examined When the transmit conditions for the next data are satisfied in step the start bit is genera
38. 104 1 1 Rising edge of 16 8 bit PWM mode Count source select b7 b6 00 fe 0 1 f16 10 fe4 11 f512 m 7 b0 alala Timer Aj mode register j 2 to 4 Addresses 5816 to 5A16 i Selection of PWM mode x Writing 1 to count start bit Internal trigger Falling edge of TAjin pin s input signal 0 Operates as 16 bit pulse width modulator 1 Operates as 8 bit pulse width modulator External trigger TAjin pin s input signal External trigger select bit bits P E Setting PWM pulse s period and H level width When operating as 16 bit pulse width modulator b15 b8 b7 bO b7 L d E 99 Timer A2 register Addresses 4Bie 4A16 Timer A3 register Addresses 4D16 4C16 Timer A4 register Addresses 4F e 4E16 When operating as 8 bit pulse width modulator b BO b7 V JN AY Can be set to 000016 to FFFE16 n es LL o0 Timer A2 register Addresses 4B16 4A 6 Timer A3 register Addresses 4D16 4C 6 22 EN Can be set to 0016 to FF16 m Timer A4 register Addresses 4F16 4E16 EN Can be set to 0016 to FE16 n A Note When operating as 8 bit pulse width modulator m 1 28 1 fi n m 1 fi fi Frequency of count source Period H level width However if n 0016 the pulse width modulator does not operate and the TAjour pin out
39. 1B16 1C416 Pulse output data register 1 1D16 1E16 A D control register 1F16 Access characteristics ea A D sweep pin select register Rw 7721 Group User s Manual 0 Always 0 at reading 1 Always 1 at reading Always undefined at reading NN 0 immediately after reset Fix this bit to 0 Nothing is assigned It is impossible to read the bit state The written value becomes invalid otate immediately after reset b7 bO 17 3 APPENDIX Appendix 2 Memory assignment in SFR area Access characteristics RW It is possible to read the bit state at reading The written value becomes valid RO It is possible to read the bit state at reading The written value becomes invalid WO The written value becomes valid It is impossible to read the bit state Nothing is assigned It is impossible to read the bit state The written value becomes invalid State immediately after a reset 0 0 immediately after reset 0 Always 0 at reading 1 1 1 immediately after reset Undefined immediately after Always 1 at reading reset Always undefined at reading W 0 immediately after reset Fix this bit to 0 Address Register name Access characteristics otate immediately after reset b7 bO b7 bO 2016 A D register 0 2116 2216 A D register 1 2316 2416 A D register 2 251
40. 2 m DMAC control register H Address 6916 Software DMAi request bit Valid in software DMA source selected Bit 0 Channel 0 Bit 1 Channel 1 Bit 2 Channel 2 Bit 3 Channel 3 DMAO enable bit DMA1 enable bit Di DMA2 enable bit I i DMA3 enable bit EN zi When selecting external When selecting internal When selecting internal DMA DMA source DMA source source except software BESEEEEEEEEREEREEBENERBEEEEENERESTDESEUBERRERERRERREEEREEREEREREREREREREREEREREREREREREREREREREREREREEREEREREREREERER When selecting software DMA request Interrupt request of each peripheral DMAC control register H Address 6916 function occurs Inputting DMA request 2 b7 b0 signal to DMAREQi pin Software DMAO request bit Software DMA1 request bit 0 No request Software DMA2 request bit Software DMA3 request bit 1 Requested C When writing 1 DMA request is generated J uuuma huuc DMA transfer starts Fig 13 8 5 Initial setting example for registers relevant to link array chain transfer mode 3 13 86 7721 Group User s Manual DMA CONTROLLER 13 8 Link array chain transfer mode 13 8 3 Operation in link array chain transfer mode Figure 13 8 6 shows the operation flowchart of the link array chain transfer mode and Figures 13 8 7 and 13 8 8 show timing diagrams of the link array chain transfer mode burst transfer mode In addition Figure 13 8 9 sh
41. 2M X 8 bits connection external bus width z 8 bits 16 26 7721 Group User s Manual APPLICATION 16 1 Memory connection lt When reading gt E tw EL 135 min OE RAS lt tw RASL 120 min L tw RASH 60 min td RAS CAS 28 min td E RASL 30 max CAS td E CASL 77 5 max lt tw CASL 92 5 min T td RA RAS 5 min lt lt gt td CA CAS 5 min MAo MAg tOEA 20 max tAA 35 max td E CA 60 max gt lt gt tpzx E DLZ 20 min tRAC 70 max IN A16 Do AMEN COOL e e ABIDI Address lt Ww C tCLZ 5 min as gt td AH E 15 min tCAC 20 max tsu DL E gt 30 tOEZ 0 15 A10 M5M417800AJ lt tASR 0 min 73 lt When writing gt tw EL 135 min E tw RASH 60 min tw RASL 120 min RAS lt gt ees tw CASL 55 min CAS ys td E CASL 80 115 td R W E 20 min lt gt R W gt lt AC32 tPHL AC32 tPHL twcs 0 min a tWCH 10 min td RA RAS 5 min gt K lt th RAS RA 18 mih gt Ke gt td CA CAS 10 min th CAS CA 60 min A16 Do V tDH 15 min Y th E DLQ 18 min Specifications of M5M417800CJ 7 The others are specifications of M37721 Unit ns
42. 5 Setup for I O ports Setup I O ports by hardware and software as follows lt Hardware protection gt Connect a resistor of 100 Q or more to an I O port in series lt Software protection gt Read the data of an input port several times to confirm that input levels are equal Since the output data may reverse because of noise rewrite data to the output port s Pi register periodically Rewrite data to port Pi direction registers periodically XU Port latch Osee lt Fig 12 Setup for I O ports 6 Reinforcement of the power source line For the Vss and Vcc lines use thicker wiring than that of other signal lines When using a multilayer printed circuit board the Vss and Vcc patterns must each be one of the middle layers Ihe following is necessary for double sided printed circuit boards On one side the microcomputer is installed at the center and the Vss line is looped or meshed around it The vacant area is filled with the Vss line On the opposite side the Vcc line is wired the same as the Vss line he power source lines of external devices which are connected by bus to the microcomputer must be connected to the microcomputer s power source lines with the shortest possible wiring Reasons With external devices connected to the microcomputer the levels of many of the signal lines total external address buses 24 bits may change simultaneously causing noise on the power source line 17 64
43. 7721 Group User s Manual 11 19 SERIAL I O 11 3 Clock synchronous serial I O mode When not using interrupts When using interrupts A UARTi transmit interrupt request occurs when the UARTi transmit buffer register becomes empty f Checking state of UARTi transmit buffer register UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3Dt6 b7 bO Le a Transmit buffer empty flag 0 Data present in transmit buffer register 1 No data present in transmit buffer register Writing of next transmit data is possible J UARTI transmit interrupt Note This figure shows the bits and registers required Writing of next transmit data for processing Refer to Figures 11 3 5 and 11 3 6 for the change of flag state and the occurrence timing of an interrupt request Va UARTO transmit buffer register Address 3216 UART1 transmit buffer register Address 3A16 bO J Set transmit data here Fig 11 3 2 Writing data after start of transmission When not using interrupts When using interrupts A UARTi transmit interrupt request occurs when the transmission starts d Checking start of transmission UARTO transmit interrupt control register Address 7116 UART1 transmit interrupt control register Address 7316 b7 bO m I Interrupt request bit 0 No interrupt requested 1 Interrupt requested X Tran
44. 7721 Group User s Manual 2 5 CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 2 1 8 Direct page register DPR The direct page register is a 16 bit register The contents of this register indicate the direct page area which is allocated in bank 0 e or in the space across banks O16 and 1 e The following addressing modes use the direct page register The contents of the direct page register indicate the base address the lowest address of the direct page area The space which extends to 256 bytes above that address is specified as a direct page The direct page register can contain a value from 0000 e to FFFF e When it contains a value equal to or more than FF0116 the direct page area spans the space across banks 0 e and 116 When the contents of low order 8 bits of the direct page register is 00 e the number of cycles required to generate an address is 1 cycle smaller than the number when its contents are not 00 e Accordingly the access efficiency can be enhanced in this case This register is cleared to 0000146 at reset Figure 2 1 4 shows a setting example of the direct page area eAddressing modes using direct page register Direct eDirect bit eDirect indexed X eDirect indexed Y eDirect indirect eDirect indexed X indirect eDirect indirect indexed Y eDirect indirect long eDirect indirect long indexed Y eDirect bit relative Direct page area when DPR 0000 e Direct page area when DPR
45. 9 TLILI UU UU UU LU D This is the term in which the bus is not l used so that sampling is performed every E 1 cycle of Q i Io I9 Q Sampling is performed after completion of Bus request sampling 1 bus cycle 16 bit data is accessed in a unit of 8 bits so that sampling is performed after ST1 STO 1 1 completion of the second bus cycle i Bus used by CPU I lt gt lt gt When access When 16 bit data is accessed is complete in in a unit of 8 bits 1 bus cycle Fig 13 2 3 Timing of bus request sampling 7721 Group User s Manual 13 9 DMA CONTROLLER 13 2 Block description 13 2 2 DMAC control register L Figure 13 2 4 shows the structure of DMAC control register L Bit 0 is described in section 13 3 3 Channel priority levels and bits 4 7 are also in section 13 3 2 DMA requests 1 TC pin validity bit Bit 1 When this bit is set to 1 port P10s functions as the TC pin The TC pin is of an N channel open drain type and provides the following functions Terminal count signal output When the transfer of an entire batch of data is normally terminated the pin outputs L for 1 cycle of Refer to section 13 3 5 1 Normal termination Forced termination signal input When the TC pin s input level goes from H to L during DMA transfer this DMA transfer is forced into termination Refer to section 13 3 5 2 Forced termination
46. CHAPTER 7 INTERRUPTS and the description of each internal peripheral device for details about each interrupt Before executing the STP instruction interrupts used to terminate Stop mode must be enabled In addition the interrupt priority level of the interrupt used to terminate Stop mode must be higher than the processor interrupt priority level IPL of the routine where the STP instruction is executed When multiple interrupts in Table 5 3 2 are enabled Stop mode is terminated by the first interrupt request There is a possibility that any of all interrupt requests occurs after the oscillation starts in and until supply of ceu and starts in The interrupt requests which occur during this period are accepted in order of priority after the watchdog timer s MSB becomes 0 For interrupts not to be accepted set their interrupt priority levels to level O interrupt disabled before executing the STP instruction 7721 Group User s Manual CLOCK GENERATING CIRCUIT 5 3 Stop mode Stop mode f XIN 01 QCPU Interrupt request used to terminate Stop mode Interrupt request bit Value of Watchdog timer CPU Operating Operating Internal peripheral devices Operating Stopped Operating Operating LN LN STP instruction lnterrupt request used to 6 Watchdog timer s MSB 0 is executed terminate Stop mode However watchdog timer interrupt occurs request does not occur Oscillation starts
47. Cleared to 0 when interrupt request is accepted or cleared by software The above timing diagram applies when the following conditions are Tenni Next transmit conditions are examined when this signal level is H satisfied TENDi is an internal signal Accordingly it cannot be read from the external Internal clock selected CTS function not selected Tc Tolk 2 n 1 fi fi BRGi count source frequency f2 f16 fe4 f512 n Value set in BRGi Fig 11 3 6 Example of transmit timing when selecting internal clock not selecting CTS function 11 22 7721 Group User s Manual SERIAL I O 11 3 Clock synchronous serial I O mode 11 3 4 Method of reception Figures 11 3 7 and 11 3 8 show initial setting examples for relevant registers when receiving Reception is started when all of the following conditions to are satisfied When an external clock is selected satisfy conditions to with the following precondition satisfied lt Precondition gt The CLKi pin s input is at H level Note When an internal clock is selected the above precondition is ignored Reception is enabled receive enable bit 1 Transmission is enabled transmit enable bit 1 Dummy data is present in the UARTi transmit buffer register transmit buffer empty flag O By connecting the RTSi pin receiver side and CTSi pin transmitter side the timing of transmission and that of reception can be m
48. Continue to Figure 13 6 4 on next page Fig 13 6 3 Initial setting example for registers relevant to repeat transfer mode 2 13 64 7721 Group User s Manual DMA CONTROLLER 13 6 Repeat transfer mode From preceding Figure 13 6 3 Selection of priority level and TC pin and setting DMAi request bit to 0 N b7 bO o ooo DMAC control register L Address 6816 Priority select bit 0 Fixed 1 Rotating TC pin validity bit 0 Invalid P103 pin functions as a programmable I O port 1 Valid E P105 pin functions as TC pin DMAO request bit DMA1 request bit DMA request bit DMAS request bit M z Note When the burst transfer mode edge sense is selected set bit 1 to 1 b7 b0 Y DMAC control register H Address 6916 0 No request Software DMAi request bit Valid in software DMA source selected Bit 0 Channel 0 Bit 1 Channel 1 Bit 2 Channel 2 Bit 3 Channel 3 DMAO enable bit DMA1 enable bit Di DMA2 enable bit Md DMAG3 enable bit l Ke When selecting external DMA source When selecting internal When selecting internal DMA DMA source source except software BESBSEEEBEEEEBBBESEBPERSUSESEHESAEREBREREREEEBEREERERRERREEREREREERERBREERERBBERERERREREREEREREREREREREEEREREEEERREERNR When selecting software DMA request m b7 bO B DMAC control register H Address 6916
49. DARI latch decrementer 2 TCR atch TCRi latch Transfer DMA latch destination 2 Write cycle DMAC Memory Data is read from memory and maintained in DMA Transfer destination address is specified by DARI Note SARi latch Contents of DARI are updated by incrementer Incrementer Transfer _ deotementer source Contents of DMA latch are written to memory DARi latch TCRi latch DMA latch i Transfer destination a When the transfer unit is 16 bits When an even address is accessed with 16 bit external data bus width data can be read or written at 1 bus cycle Accordingly the incrementer decrementer and the decrementer increment or decrement by 2 and sequences through are performed once When an odd address is accessed with 16 bit external data bus width or when 8 bits is used as external data bus width data is read or written at 2 bus cycles and sequences through or through are repeated twice The incrementer decrementer and the decrementer increment or decrement by 1 every time sequences through or through are performed once Note In the single transfer mode and repeat transfer mode only at the first transfer of the block the values read from SARi latch DARI latch and TCRi latch are used The results obtained by increment or decrement are written to SARI DARI and TCRi Except for the first transfer of the block the values
50. DMA1 enabled DMA2 enabled X It may be 0 or 1 Fig 16 2 10 Initial setting example for relevant register 3 16 52 7721 Group User s Manual APPLICATION 16 2 Examples of using DMA controller 16 2 3 Example of dynamic lighting for LED The following is an example of dynamic lighting for LED by using DMA3 and Timer BO 1 Specifications he eight 7 segment LEDs are lighted up port P6 outputs the segment data port P7 outputs the digit data Refer to Figure 16 2 11 he display data and the segment data are transferred from the data buffer to the port P6 and P7 registers by DMAS Digit switch interval is generated by Timer BO 16 bytes of RAM are used as the data buffer 1 digit display data consists of 2 bytes the digit data is placed in the high order byte the segment data is placed in the low order byte Refer to Table 16 2 2 When the digit data and segment data are 0 the LED is lighted up ON when they are 1 the light goes out OFF Assuming that the segment pattern is generated by another processing M37721 7 segment LED X 8 Data buffer driver Fig 16 2 11 Example of dynamic lighting for LED Table 16 2 2 Data buffer Data buffer Digit data segment pattern 00000001 00000010 00000100 Segment pattern of the 51 contents to be displayed 00010000 in each digit 00100000 01000000 10000000 Notes 1 This applies in the following ewhen the dig
51. H Cycle steal Requested In cycle steal transfer mode with any request of DMA0 3 Cycle steal No request In cycle steal transfer mode with no request of DMA0 3 Fig 13 6 5 Operation flowchart of repeat transfer mode 13 66 7721 Group User s Manual DMA CONTROLLER 13 6 Repeat transfer mode pej1doooe si pue si jeubis Bulj dwes sanba snq y SIUM pejduues si p oH 10 ySaujau NVHOG Aq pesneo 1senba sng eu e OYNA nd snq esn oj juDi G 1ep G Jes 9 en BA 19S YOL u8 9 IH VQ 0 18S SI YOIUM anj eA U Jep USA9 IHVS 01198 SI YOIUM NJLA OU Jes ON yem uoneunsep 419JSUJ ON yem anos J9JSUPJ PJEMIO4 uoroaeiJip sseJppe uoreursep J9JSUeJ pJeMJ0J uOnoeJip sseJppe 99Jnos J9JSUPJ sung poui J9JSUeA l9JsueJ 9 o o snq z POUJOW J9JSUPJ rep SIIq 9 yun J9JSUJ SIIq 9 YIPIM snq eyep u491X3 Kowey suonipuoo BuiwoJ oJ y uo Saljdde ejdurexe suu e puooes gyep jo uoreq eJnue JO JOJSUBI sng esn 0 1uOu JO UONISUBI I S114 BYEP Jo uo eq eJnue JO 19JsueJ F f repeat transfer mode burst transfer mode J9JSUEJ PUN town Fh as ts IOVVIAG ep Xora ues X gres zera tenen eea es oea Hep Korey ies X Od uep korea ues X lotes XraereqXvrer Xeleay rero nep iore nues X Hod Zq eeV 0d 9 V SIC SIV 8q 8V V 0V Wu Buiiduues 1senboi sng iagram o d iming Fig 13 6 6 T 13 67 7721 Group User s Manu
52. Make sure that the propagation delay time is within 25 ns Address bus Ao A15 Data bus Do D7 Memory map 000016 SFR area 008016 Internal RAM area goo External ROM area M5M28F101AEFP ACOA Li SFR area 200016 Circuit condition Software Wait External BON ares M5M28F101AFP Fig 16 1 16 Example of flash memory connection minimum model 16 20 7721 Group User s Manual APPLICATION 16 1 Memory connection lt When reading gt tw EL 135 min E OE tpzx E DLZ 20 min A16 Do A23 D7 X A ta R W E 20 min gt th E R W 18 max ta AD tsu A DL 130 max ACOA tPLH gt lt AC04 tPHL CE iDF 15 max External ROM Guaranteed as kit data output amp D tsu DL E gt 30 Specifications of MBM28F101AFP 10 The others are specifications of M37721 Fig 16 1 17 Timing chart for flash memory connection example minimum model 7721 Group User s Manual 16 21 APPLICATION 16 1 Memory connection 2 Example of flash memory and SRAM connection maximum model M37721 Address bus As A16 AC573 As Ds A15 D15 A16 Do A18 D2 AC573 Data bus odd Data bus even AC04 3 Memory map 000016 SFR area O I 008016 Internal RAM area AC32 Circuit condition Software Wait 048016 External ROM area M5M28F102AFP Mns 200016 1 2 Make sure that t
53. RW 010121 7 0 0 RNN s eee SE16 Processor mode registero RW jWORW Rw 0 KON 0 0 0 0 1 NX 5F16 Processor mode register RW Log 2 Notes 1 2 3 4 The access characteristics at addresses 4A16 to 4F16 vary according to Timer A s operating mode Refer to CHAPTER 8 TIMER A The access characteristics at addresses 5016 to 5316 vary according to Timer B s operating mode Refer to CHAPTER 9 TIMER B The access characteristics for bit 5 at addresses 5B16 and 5C16 vary according to Timer B s operating mode Bit 5 at address 5Dte is invalid Refer to CHAPTER 9 TIMER B Bit 1 at address 5F16 becomes 0 immediately after reset For the M37721S1BFP fix this bit to p Fig 4 1 6 State of SFR and internal RAM areas immediately after reset 3 7721 Group User s Manual 4 7 RESET 4 1 Hardware reset Address Register name Access characteristics State immediately after reset b7 bO b7 bO 6016 Watchdog timer register Note 5 6116 Watchdog timer frequency select register IRW C 0 6216 Real time output control register RW 0 0 0 0 0 0 0 0 2 6316 sss 6416 DRAM control register RW RW 6516 w sss 6616 Refresh timer 6716 as 6816 DMAC control register L Note RW 6916 DM AC control register H 6A16 See 6B16 FPC G tll l 6C16 DMAO interrupt control register 6D16 DMAt interrupt control register 6E
54. The written value becomes invalid Accordingly the written value may be 0 or 1 7721 Group User s Manual 17 9 APPENDIX Appendix 3 Control registers Port Pi register b7 b6 b5 b4 b3 b2 bl b0 Port Pi register i 4 to 10 Addresses A16 B16 E16 F16 1216 1316 1616 KW Port Pio s pin Data is input from or output to a pin j j by reading from or writing to the Port Pit s pin corresponding bit Port Pi2 s pin 0 L level Demum Note For bits 0 to 2 of the port P4 register nothing is assigned and these bits are fixed to 0 at reading Port Pi direction register b7 b6 b5 b4 b3 b2 bi b0 BERR Port Pi direction register i 4 to 10 Addresses Cie D16 1016 1116 1416 1516 1816 Tc ERE Port Pio direction bit Input mode The port functions as an input port r Port Pi direction bit 1 Output mode Port Bisdirection bit The port functions as an output port Ls ron arson Note For bits 0 to 2 of the port P4 direction register nothing is assigned and these bits are fixed to 0 at reading 17 10 7721 Group User s Manual APPENDIX Appendix 3 Control registers Pulse output data register 0 b7 b6 b5 b4 b3 b2 bl b0 Pulse output data register 0 Address 1A16 RTPOo pulse output data bit 0 L level output 1 H level output RTP01 pulse output data bit RTP02 pulse output data bit 2 E Valid in pulse mode 0 RTP03 pulse o
55. Undefined RW Set the start address of transfer parameter memory of block which is first transferred These bits can be set to 00000016 to FFFFFF 16 Read After a value is written to this register and until transfer starts the read value indicates the written value the start address of the transfer parameter memory of block which is first transferred After transfer starts the read value indicates the source address of data which is next transferred Note When writing to this register write to all 24 bits b23 b16 b15 b8 b7 b0 2 pb Destination address register 0 Addresses 1FC616 to 1FC416 DARO Destination address register 1 Addresses 1FD61e to 1FD416 DAR1 Destination address register 2 Addresses 1FE616e to 1FE416 DAR2 Destination address register 3 Addresses 1FF616 to 1FF416 DAR3 Need not to be set inii LLL LLL 23 to 0 i Read Undefined RW After transfer starts the read value indicates the destination address of data which is next transferred b23 b16 b15 b8 b7 b0 Addresses 1FCA16 to 1FC816 Addresses 1FDA e to 1FD816 Addresses 1FEAte to 1FE816 Addresses 1FFAie to 1F F816 TCRO TCR1 Transfer counter register O Transfer counter register 1 Transfer counter register 2 TCR2 Transfer counter register 3 TCR3 a Am 23 to 0 Write Undefined RW Set the dummy data These bits can be set to 00000116 to FFFFFF46 Read Af
56. Value of 24 bit address s middle 8 bit A1s As Value of 24 bit address s lower 8 bit A7 Ao Operation code Number of cycle Number of byte Number of transfer byte or rotation Number of registers pushed or pulled 17 55 APPENDIX Appendix 7 Hexadecimal instruction code table Appendix 7 Hexadecimal instruction code table INSTRUCTION CODE TABLE 1 Hexadecimal notation SEB ORA ORA ORA DIR b A DIR A IMM A ABS CLB ORA ORA ORA DIR b A DIR X A ABS Y A ABS X BBS AND AND AND DIR b R A DIR A IMM A ABS BBC AND AND AND DIR b R A DIR X A ABS Y A ABS X EOR EOR EOR A DIR A IMM A ABS EOR EOR EOR A DIR X A ABS Y A ABS X ADC ADC ADC A DIR A IMM A ABS ADC ADC ADC A DIR X A ABS Y A ABS X STA STA STA A DIR A L DIR A ABS STA STA STA STA A DIR X AL DIR A ABS Y A ABS X LDA LDA LDA LDA A DIR A L DIR A IMM A ABS LDA LDA LDA LDA A DIR X AL DIR A ABS Y A ABS X CMP CMP CMP CMP A DIR A L DIR A IMM A ABS CMP CMP CMP CMP A DIR X AL DIR A ABS Y A ABS X SBC SBC SBC SBC A DIR A L DIR A IMM A ABS SBC SBC SBC SBC A DIR X AL DIR A ABS Y A ABS X Notes 1 4216 specifies the contents of the INSTRUCTION CODE TABLE 2 About the second word s codes refer to the INSTRUCTION CODE TABLE 2 2 8916 specifies the contents of the INSTRUCTION CODE TABLE 3 About the second word s codes refer to the INSTRUCTION CODE TABLE 2
57. When Supply of cPu starts an external clock is input lnterrupt request which has been used from the XiN pin clock to terminate Stop mode is accepted input starts e Waichdog timer starts counting Fig 5 3 1 Stop mode terminating sequence by interrupt request occurrence 2 Termination by hardware reset Supply L level to the RESET pin by using the external circuit until the oscillation of the oscillator is stabilized The CPU and the SFH area are initialized in the same way as system reset However the internal RAM area retains the same contents as that before executing the STP instruction The terminating sequence is the same as the internal processing sequence which is performed after reset Refer to CHAPTER 4 RESET for details about reset 7721 Group User s Manual 5 7 CLOCK GENERATING CIRCUIT 5 3 Stop mode Precautions for Stop mode When executing the STP instruction after writing to an internal area or an external area three NOP instructions must be inserted to complete the write operation before the STP instruction is executed Refer to Figure 5 9 2 STA A XXXX Write instruction NOP NOP instruction inserted NOP I NOP STP STP instruction Fig 5 3 2 NOP instruction insertion example 5 8 7721 Group User s Manual CLOCK GENERATING CIRCUIT 5 4 Wait mode 5 4 Wait mode Wait mode is used to stop cru and when there is no need to operate the central proce
58. _ RHE gt Memory connection model Medium mode B Memory connection model Maximum model Notes 1 Refer to CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES for details about the functions and operations of used pins when connecting a memory Refer to section Appendix 11 Electrical characteristics for timing requirements 2 Because the address bus can be expanded up to 24 bits when connecting a memory strengthen the M37721 s Vss and Vcc lines on the system Refer to section Appendix 8 Countermeasure against noise 7721 Group User s Manual 16 3 APPLICATION 16 1 Memory connection 16 1 2 How to calculate timing Timings at which data is read or written when connecting a memory and precautions when connecting a memory are described below For timing requirements of the memory and detailed account except limits described below also refer to the memory s Data book etc When using bus buffers various logical circuits etc be sure to consider the propagation delay time etc 1 Timing for reading data When reading data the external data bus is placed in a floating state and data is read from the external memory This floating state is maintained after the falling edge of the E signal until an interval of toz E otz ouz has passed after the rising edge of the E signal Satisfy tsuovox e when inputting data read from the external memory The following are described below Timing for reading data from the flash
59. an n bit n lt 8 address latch is required for latching n bits of the address in Ass to Ags Medium model B This is a connection model of which external data bus width is 16 bits and access space is expanded up to 64 Kbytes This model gives priority to rate performance In this model the middle order 8 bits of the external address bus As to Ais are multiplexed with the external data bus Therefore an 8 bit address latch is required for latching As to Ais Maximum model This is a connection model of which external data bus width is 16 bits and access space is expanded up to 16 Mbytes In this model the high and middle order 16 bits of the external address bus As to A23 are multiplexed with the external data bus Therefore an 8 bit address latch for latching As to Ais and an n bit n lt 8 address latch for latching n bits of Ais to A23 are required 7721 Group User s Manual APPLICATION 16 1 Memory connection Table 16 1 1 Memory connection model Access space External data Maximum 64 Kbytes Maximum 16 Mbytes bus width M37721 M37721 BYTE Ao A7 Ao At15 n Ao A7 Ao A15 As Ais 8 bit width X As A15 A16 Do A23 D7 BYTE H ALE A16 Do A23 D7 Do D7 Do D7 Memory connection model Minimum model Memory connection model Medium model A M37721 M37721 16 n BYTE Ao Az7 Ao A15 n As Ds A15 D15 l l A8 D8 A15 D15 16 bit width A1e Do Aza D7 BYTE L ian Do Dt15
60. etc are performed sequentially All except the following After completion of 1 unit transfer At the end of each block B During transfer in burst transfer mode except the last block After the last 1 unit transfer of 1 block the subsequent 3 cycles of 9 and a read of the first 2 bytes in the array state of the next block are performed sequentially B During transfer in cycle steal transfer mode After the last 1 unit transfer of 1 block and the subsequent 3 cycles of are performed sequentially At the end of the last block After 1 unit transfer and terminate processing 3 cycles of 9 are performed sequentially At an array state After a read of 2 bytes of a transfer parameter CPU When an instruction is After completion of 1 bus cycle fetched into queue buffer At a read from or a write into After completion of 1 bus cycle or after completion of the second bus cycle if a 16 bit data is accessed in a unit of 8 bits Note 2 While CPU does not use bus Every 1 cycle of Notes 1 S Single transfer mode R Repeat transfer mode Array Array chain transfer mode Link Link array chain transfer mode 2 his applies when the data bus width is 8 bits or when memory is accessed starting at an odd address If a DRAM refresh request or a Hold request is generated during a data transfer in the burst transfer mode the request is accepted at the above mentioned bus request sampling Another DMA request including that
61. is indicated in the Function or Note column the bit is always 0 at reading See 4 above The written value becomes invalid Accordingly the written value may be 0 or 1 Table of contents Table of contents CHAPTER 1 DESCRIPTION 1 2 1 2 Pin configurationl nnn nnn nnh nna muuuu uuu u usan sR 1 3 U t 1 4 sus nas s nus ss Qs u s nus 1 7 CHAPTER 2 CENTRAL PROCESSING UNIT CPU 2 2 2 3 eee 2 3 MM s s 2 3 NENNEN P aaa 2 4 7 2 5 2 1 6 Program bank register PQ 9A d 2 5 WA odii dM 2 5 NNNM NINE 2 6 MM 6 WM D 2 2 Bus interface unitl U U u 2 9 W 2 9 actions of b nterface un d Reucuv 2 11 eee eee eset cee oes 2 13 d cC 2 15 TEE d WA d P O 2 16 EE 2 16 2 4 Memory assiqnmenLtll
62. lt gt o0d lH e9d lt gt 0d LH 9d lt gt OLd LH 9d lt gt L d Ld S9d lt gt ld1y 99d lt gt S dld z9d bus control signal 8 bits BYTE H External data bus width rgjoey lt gt q 6lV lt gt sy lt gt 9 LYWY lt L 9Vy N 9V lt L Sy N SV 99 YIN lt LA eyw ey lt 8 eyIN ey lt L8 IIN V lt 0 oyjN oy lt LE SOAYVING 46d lt gt L MOVVNWGQ 96d 1 COSYVING S6d lt gt LZ CMOVWING 6d lt gt LO3HVINd 6d lt gt LMOVWING 26d lt gt Z 0O3uviNQ ed lt gt OMOVWWIG 96d lt gt 5 LOXL 48d lt gt wo AA a N N lt lt ose co P83 TxDo lt gt teles OX x tO 5 co oO n n P84 CTS1 RTS1 lt gt N co P82 RxDo lt gt P81 CLKo lt gt 3 P8o CTSo RTSo lt gt e lss bs te ze e e ss s ze s s bo ouo rDPrTZ2z2 gt gt gt gt lt lt lt lt lt lt lt 7X D ouudsu s S pomom 5 I m n n B nO B lt nN A O e mH ees 8 gazutuirz oo Hos S LU X gt x r oxic M37721S2BFP 56 lt gt rd 77 lt gt 0LNI 00 Ld c lt gt LNI OLd 2 lt gt LNI 20L d 17 lt gt O L e0Ld 02 lt gt SVO OLd 6H lt gt SVH S0Ld 87 SVW 90Ld Zt lt gt SVW 0Ld St lt gt 1 nOcV L 0Gd ST lt gt NlzV Gd bt lt
63. n fi fi Frequency of count source fz fis fea or f512 Note Use the LDM or STA instruction for writing to this register Read from or write to this register in a unit of 16 bits b7 b6 b5 b4 b3 b2 bl TII E Io Timer Aj mode register j 2 to 4 Addresses 5816 to 5A 6 7 ESE EHI 1 0 One shot pulse mode b4 b3 7 0 0 Writing 1 to one shot start register 01 TAjin pin functions as a prog rammable I O port i Falling edge of TAjin pin s input signal Rising edge of TAjin pin s input signal b7 b6 00 fe 01 fie M 10 fea 1 f512 7721 Group Users Manual 17 21 APPENDIX Appendix 3 Control registers Pulse width modulation PWM mode lt When operating as a 16 bit pulse width modulator gt b15 b8 b7 bO b7 bO Timer A3 register Addresses 4D16 4C 6 Timer A4 register Addresses 4F16 4E16 Bt Functions faves RW 15 to O These bits can be set to 000016 to FFFE 6 Undefined WO Assuming that the set value n the H level width of the PWM pulse output from the TAjour pin is expressed as follows So l PWM pulse period l fi Frequency of count source f2 fie fe or fs12 Note Use the LDM or STA instruction for writing to this register Read from or write to this register in a unit of 16 bits lt When operating as an 8 bit pulse width modulator gt b15 b8 b7 bO b7 bO Timer A3 register Addres
64. selected Note DMAACKi validity bit 0 Invalid The pin functions as a programmable I O port Valid The pin functions as DMAACKi cA Nothing is assigned Undefined Note When a certain source other than an external source is selected by bits 0 to 3 or when the cycle steal transfer mode is selected set bit 4 to 0 Level sense can be selected only when both of the external source and the burst transfer mode are selected Fig 13 2 8 Structure of DMAi control register 13 16 7721 Group User s Manual DMA CONTROLLER 13 2 Block description 13 2 13 DMAi interrupt control register Figure 13 2 9 shows the structure of the DMAi interrupt control register For details about interrupts refer to CHAPTER 7 INTERRUPTS b7 b6 b5 b4 b3 b2 bi bO DMAi interrupt control register i 0 to 3 Addresses 6C46 to 6F 16 Iri b2 b1 b0 bi lle a G a 000 Level 0 Interrupt disabled RW 0 0 1 Level 1 Low level Level 6 10 Level2 1 1 Level 3 RW 00 Level 4 01 Level 5 10 11 RW Level 7 High level 3 Interrupt request bit 0 No interrupt requested RW 1 Interrupt requested Nothing is assigned Undened Fig 13 2 9 Structure of DMAi interrupt control register 1 Interrupt priority level select bits bits 2 to 0 These bits select a DMAi interrupt s priority level When using DMAi interrupts select one of the priority levels 1 to 7 When a DMAi interrupt request oc
65. td BLE BHE E 20 min tDH 15 min a AC157 tPHL th E DLQ DHQ 18 min Specifications of M5M418160CJ 7 The others are specifications of M37721 Unit ns Fig 16 1 27 Timing chart for example of M5M418160CJ 1M X 16 bits connection external bus width 16 bits 7721 Group User s Manual 16 31 APPLICATION 16 1 Memory connection 7 Example of DRAM connection external bus width 16 bits M37721 M5M44170CJ 7 1 Make sure that the propagation delay time is within 40 ns 2 Make sure that the propagation delay time is within 15 ns I RAS CAS E SFR area 00047Fie RAM area Not used R W BLE BHE A16 Do A17 D1 Ais D2 A19 D3 A20 D4 A21 D5 A22 De A23 D7 mem LIII soiree SFR area ootrrri SFR area Not used JUJUY NO O I ALE As Ds F0000016 Ao Do DRAM area Fir is TEER Erol M5 M44170CJ A11 D11 A12 D12 A13 D13 Not used A14 D14 FFFFFF16 A15 D15 XOUT Circuit condition DRAM area select bits bits 3 to 0 at address 6416 00012 Fig 16 1 28 Example of M5M44170CJ 256K X 16 bits connection external bus width 16 bits 16 32 7721 Group User s Manual APPLICATION 16 1 Memory connection lt When reading gt E _ OB tw EL 135 min RAS tw RASL 120 min tw RASH 60 min td RAS CAS 28 min td E RASL 30 max lt CAS
66. the DMAREQi pin s input level is L and the right to use bus is returned to the CPU when the DMAREQi pin s input level is H Even in this case any DMA request of the other channels is not accepted until the entire batch of data has been transferred For details refer to section 13 4 3 Burst transfer mode B Cycle steal transfer mode For each DMA request 1 transfer unit of data is transferred Hereafter transferring 1 transfer unit data which is 8 bit or 16 bit data in the M37721 is called 1 unit transfer When 1 unit transfer is complete and another DMA request including that of other channels is not generated the DMAC relinquishes the right to use bus to the CPU In the cycle steal transfer mode all of the DMA request sources are available For details refer to section 13 4 4 Cycle steal transfer mode Figure 13 1 1 shows the outline of the DMA transfer modes ll Burst transfer mode Edge sense DMAi request is accepted Rghttousebus CPU DAT _ Transfer of entire batch of data E Burst transfer mode Externa source DMAREQ level sense DMAREQi input Right to use bus CPU Dw amp CPU IDNA ll Cycle stea transfer mode DMAO request is accepted DMAO request is accepted DMA1 request is accepted Right to usebus CPU DMA0 CPU DMAO DMA1 CPU One transfer unit One transfer unit One transfer unit Fig 13 1 1 Outline of DM
67. to L The address bus signal changes from row address to column address within a period from a fall of RAS until a fall of CAS Pins Ate Do Az3 D7 and As Ds A s D s output addresses and input data in the same way as in reading external devices other than DRAM Write Cycle In the write cycle the CAS signal falls with a delay of 1 cycle of after the RAS signal has changed from H to L The address bus signal changes row address to column address within a period from a fall of RAS until a fall of CAS Pins A e Do Aes Dz and As De A s D s output addresses and data in the same way as in writing external devices other than DRAM Refresh Cycle In the refresh cycle the RAS signal falls with a delay of 0 5 cycle of after the CAS signal has changed from H to L R W is undefined One refresh request requires 5 cycle of including the time for passing the right to use buses 7721 Group User s Manual DRAM CONTROLLER 14 4 DRAMC operation a At reading 0 Lo L Ld z L o f R W MAo MAs Column address A16 Do A23 D7 M As Ds Ai5 D15 gt Read cycle 1 bus cycle lt b At writing 0 L 1 Lor q lt TD R W MAo MAs Column address A16 Do A23 D7 As Ds A15 D15 Write cycle 1 bus cycle Ww gt c At refresh et LI LI L j LI Ld Tmo R W Undefined MAo MAe Undefined A16 Do A23 D7 Floating NN EE Dhu Unde
68. 0 1 0 1 DMAO mode register L Address 1FCCt6 Transfer unit 8 bits 2 bus cycle transfer Cycle steal transfer mode Transfer source address direction Fixed Transfer destination address direction Forward b7 b0 0 0 0 0 0 0 x 0 DMAO mode register H Address 1FCD16 Transfer source Wait Transfer destination Wait Single transfer mode X It may be O or 1 Fig 16 2 3 Initial setting example for relevant register 1 7721 Group User s Manual 16 45 APPLICATION 16 2 Examples of using DMA controller b23 b16b15 b8b7 bO Source address register 0 Addresses 1FC216 to 1FC016 XN I Y Octal latch s address b23 b16b15 b8b7 bO Destination address register 0 Addresses 1FC616 to 1F C416 MV A Y Data buffer s start address b23 b16b15 b8b7 bO Transfer counter register 0 Addresses 1FCA16 to 1FC816 M A T Data buffer size unit byte b7 bO 0 1 1 1 1 0 Timer A2 mode register Address 5816 One shot pulse mode Trigger Rising edge of TA2IN pin s input signal Count source b7 b0 0 1 1 1 1 0 Timer A3 mode register Address 5916 One shot pulse mode Trigger Rising edge of TASiN pin s input signal Count source b15 b8 b7 b0 Timer A2 register Addresses 4Bie 4A16 t ACK signal s L level time T2 in Figure 16 2 2 b15 b8 b7 bO 2X Timer A3 register Addresses 4D16 4C16 l Period from
69. 1 bus cycle transfer from memory to I O All of the following transfer parameters are required for each block of data that is a transfer parameter memory consumes 12 bytes for each block Transfer source s transfer start address 24 bits Dummy data 8 bits Transfer data s byte number 24 bits Dummy data 8 bits e Start address of next transfer parameter memory 24 bits Note Dummy data 8 bits In 1 bus cycle transfer from I O to memory All of the following transfer parameters are required for each block of data that is a transfer parameter memory consumes 12 bytes for each block Transfer destination s transfer start address 24 bits Dummy data 8 bits Transfer data s byte number 24 bits Dummy data 8 bits e Start address of next transfer parameter memory 24 bits Note Dummy data 8 bits For the last block of data write 00000016 as the start address of the next transfer parameter memory 7721 Group User s Manual DMA CONTROLLER 13 8 Link array chain transfer mode 1 2 bus cycle transfer 4 bytes Transfer source s transfer start address 1 Transfer destination s transfer start address 1 Transfer data s byte number 1 Next transfer parameter memory s start address 2 Transfer data s byte number 4 00000016 Transfer destination s transfer start address 3 Transfer data s byte number 3 Next transfer parameter memory s start address 4
70. 10 2 cycles of RW 1 1 Do not select 6 Fixthisbitto o P 7 Stack bank select bit Bank O16 Bank FF e b b6 b5 b4 b3 b2 bl E A ES Nothing is assigned m _ Internal RAM area select bit 512 bytes addresses 8016 to 27F 16 Notes 1 2 1024 bytes addresses 8016 to TAA MIENNE Lo Nothing is assigned E Notes 1 For the M37721S1BFP fix bit 1 to 0 2 For the M37721S2BFP set bit 1 before setting the stack pointer Fig 2 4 4 Structure of processor mode registers 0 1 2 22 7721 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 5 Bus access right 2 5 Bus access right The M37721 s bus is used for DRAMC Hold function and DMAC besides CPU When the bus requests of two or more source are detected at the same timing the highest bus access priority levels get the access right The bus priority levels are fixed by hardware Additionally the bus use state is output from the status signal output pins STO and ST1 Table 2 5 1 lists the bus use priority levels and the status signals depending on the bus use state Table 2 5 1 Bus use priority levels and status signals depending on bus use state us use priority levels us use state Sn ST1 SIO 1 Highest DRAM refresh 2 3 DMAC 4 Lowest CPU Including the term that CPU does not use the bus during calculation etc Oo o For details refer to section 13 2 1 Bus access control circuit and chapter
71. 15 6 7721 Group User s Manual WATCHDOG TIMER 15 3 Precautions for Watchdog timer 15 3 Precautions for Watchdog timer 1 When dummy data is written to address 6016 with the 16 bit data length writing to address 6116 is simultaneously performed Accordingly when the user does not want to change a value of the watchdog timer frequency select bit bit O at address 61 6 write the previous value to the bit simultaneously with writing to address 6016 2 When the STP instruction is executed Watchdog timer stops Refer to section 5 3 Stop mode 3 Watchdog timer stops during DRAM refresh hold state and DMAC operation For Watchdog timer s structure refer to Figure 15 1 1 Accordingly when a bus request is changed in the period which is shorter than 1 cycle of the count source Note Watchdog timer s count may gain Refer to Figure 15 3 1 Note fs or fs12 which is selected by the watchdog timer frequency select bit 32 or f512 Bus request Count source which is actually 4 counted by Watchdog timer lt gt In case the bus request is changed in a period which is shorter than 1 cycle of fa2 or fs12 Fig 15 3 1 Count source for Watchdog timer 7721 Group User s Manual 15 7 WATCHDOG TIMER 15 3 Precautions for Watchdog timer MEMORANDUM 15 8 7721 Group User s Manual CHAP TIER 16 APPLICATION
72. 15 to 9 Nothing is assigned ume Note Use the LDM or STA instruction for writing to this register UARTi transmit receive control register 0 b7 b6 b5 b4 b3 b2 bi bO UARTO transmit receive control register 0 Address 3416 UART1 transmit receive control register 0 Address 3C e BRG count source select bits b1 b0 RW 0 0 f2 0 1 f16 RW 1 0 fe4 1 f512 CTS RTS select bit CTS function selected RTS function selected Transmit register empty flag 0 Data present in transmit register No transmission No data present in transmit register Transmission completed Nothing is assigned umeime 17 14 7721 Group User s Manual APPENDIX Appendix 3 Control registers UARTi transmit receive control register 1 b7 b6 b5 b4 b3 b2 bl bO UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 Bitname Bitname Functions Atreset reset RW rus enable bit EN Ru disabled Transmission enabled Transmit buffer empty flag 0 Data present in transmit buffer register 1 No data present in transmit buffer register Receive enable bit Reception disabled Reception enabled Receive complete flag 0 dus Bn in receive uffer register 1 Data present in receive buffer register 4 Overrun error flag Note 1 0 No overrun error 1 Overrun error detected 5 Framing error flag Notes 1 2 0 No framin
73. 4 3 Timing of acceptance of Hold request and termination of Hold state 3 7721 Group User s Manual 3 15 CONNECTION WITH EXTERNAL DEVICES 3 4 Hold function Precautions for Hold function When a DRAM refresh request occurs in Hold state DRAM refresh is performed immediately because the bus use priority level of DRAM refresh is higher than that of Hold function 3 16 7721 Group User s Manual CHAPTER 4 RESET 4 1 Hardware reset 4 2 Software reset RESET 4 1 Hardware reset 4 1 Hardware reset When the power source voltage satisfies the microcomputer s recommended operating conditions the microcomputer is reset by supplying L level to the RESET pin This is called a hardware reset Figure 4 1 1 shows an example of hardware reset timing RESET tgt 2 us or more 4 to 5 cycles of 0 sequence alter reset Program is executed b 18a8 et A a gt Internal processing D Note When the clock is stably supplied Refer to section 4 1 4 Time supplying L level to RESET pin Fig 4 1 1 Example of hardware reset timing The following explains how the microcomputer operates in periods to above D After supplying L level to the RESET pin the microcomputer initializes pins within a period of several ten ns Refer to Table 4 1 1 While the RESET pin is
74. 7 8 9 Access address Even and odd addresses Even address Odd address mae 2 MEE AUN access 1 ERE EN access 1 byte BLE BHE s o L Address latch enable signal ALE This signal is used to latch the address from the multiplexed signal which consists of the address and data This multiplexed signal is input to or output from the As De A s D s and A e Do Ae23 D pins When the ALE signal is H latch the address and simultaneously output the addresses When this signal is L retain the latched address Ready function related signal RDY This is the signal to use Ready function Refer to section 3 3 Ready function Hold function related signal HOLD This is the signal to use Hold function Refer to section 3 4 Hold function Status signals STO ST1 These signals indicate the bus use status Table 3 1 3 lists the bus use status indicated by the STO and ST1 signals 10 Clock 9 3 4 This signal has the same period as Table 3 1 3 Bus use status indicated by STO and ST1 signals ST1 STO Bus use status L L DRAM refresh L H Hold H L DMA H H CPU 7721 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 3 1 Signals required for accessing external devices 3 1 2 Operation of bus interface unit BIU Figures 3 1 2 and 3 1 3 show the examples of operating waveforms of the signals input from or output to the external when accessing external devices The follo
75. 8 A7 TIMER A 8 6 Pulse width modulation PWM mode MEMORANDUM 8 48 7721 Group User s Manual CHAPTER 9 TIMER B 9 1 Overview 9 2 Block description 9 3 Timer mode Precautions for timer mode 9 4 Event counter mode Precautions for event counter mode 9 5 Pulse period Pulse width measurement mode Precautions for pulse period pulse width measurement PWM mode TIMER B 9 1 Overview 9 2 Block description 9 1 Overview Timer B consists of three counters Timers BO to B2 each equipped with a 16 bit reload function Timers BO to B2 operate independently of one another Timer B has three operating modes listed below Timers BO and B1 have selective three operating modes listed below Timer B2 operates only in the timer mode 1 Timer mode Timers BO to B2 The timer counts an internally generated count source 2 Event counter mode Timers BO and B1 The timer counts an external signal 3 Pulse period Pulse width measurement mode Timers BO and B1 The timer measures an external signal s pulse period or pulse width In this chapter Timer Bi i 0 to 2 indicates Timers BO to B2 Timer Bj j 0 1 indicates Timers BO and B1 this is used when the timer B s input output pins are used etc Hereafter input output pins are called I O pins 9 2 Block description Figure 9 2 1 shows the block diagram of Timer B Explanation of registers relevant to Timer B is described below Count s
76. BHE L L M H H BLE Transfer source Even address Transfer destination _____2____ As De A15 D15 T T f l N ransfer destination H gt pr H gt y sSs address BHE BLE Data bus L L 16 bits Ds D15 8 bits s AsDe AsDis ames ciendum Qmm yo Transfer source Odd Away address BHE L L H H BLE Even m Transfer ination addr sue Databus gre adess Aras ii address orem E wo o mem Odd address address RN d LT address J When the memory is the internal memory or SFR data is output When the memory is the external memory it enters a floating state 13 44 7721 Group User s Manual DMA CONTROLLER 13 4 Operation 3 Address directions in 1 bus cycle transfer In 1 bus cycle transfer the transfer source and destination address directions of memory are selectable Refer to Figure 13 2 6 Addresses move in the specified direction by the transfer unit Tables 13 4 8 and 13 4 9 list address directions in 1 bus cycle transfer and examples of transfer results Table 13 4 8 Address directions in 1 bus cycle transfer and examples of transfer results 1 External data bus width 16 bits External data bus width 16 bits or 8 bits Address direction Transfer unit 16 bits Transfer unit 8 bits Transfer Transfer Data arrangement Data arrangement Tr m ansfer source destination on transfer source on transf
77. Bj interrupt request bit is set to 1 When the same value which has been set in these bits are written again the timer Bj interrupt request bit is not changed that is the bit retains the state If the input signal to the TBjw pin is affected by noise etc the counter may not perform the exact measurement We recommend to verify by software that the measurement values are within a constant range 7721 Group User s Manual 9 25 TIMER B 9 5 Pulse period Pulse width measurement mode MEMORANDUM 9 26 7721 Group User s Manual CHAP TIER 10 REAL TIME OUTPUT 10 1 Overview 10 2 Block description 10 3 Setting of real time output 10 4 Real time output operation REAL TIME OUTPUT 10 1 Overview 10 1 Overview The real time output has the function of changing the output level of several pins simultaneously at every period of the timer Figure 10 1 1 shows the block diagram of real time output per bit Real time output has two operating modes described below 1 Pulse mode 0 The 8 bit pulse output pins serve for two independent 4 bit outputs Figure 10 1 2 shows the configuration of real time output in the pulse mode O 2 Pulse mode 1 The 8 bit pulse output pins serve for a 2 bit and a 6 bit outputs Figure 10 1 3 shows the configuration of real time output in the pulse mode 1 Ti Aj _ ar PA signal Bit i of port P6 direction register L Pulse output data register p Flip flop P6i RTPOk
78. CAS i STO ST1 lo 2 mA V BLE BHE R W I MP Vo Low level output ALE lo 10 mA V voltage gt 2 mA 0 43 Vo Low level output E flo 10mA V voltage lo 2mA 3 Hysteresis HOLD RDY TA2m TA4n TBOw TB1w INTc INT2 mE ADrtrac CTSe CTS CLKo CLK V DMAREQ0 DMAREQS TC Vn Vr Hysteresis RESET 1 id 05 V Ve VrHysteresis Xt 03 V lin High level input Ae De A s D s A1e Do Azs D7 P4s P47 P5o P5 current P60 P67 P7o P 77 P amp P8 5 uA P9 P9 P10c P107 RDY HOLD BYTE CNVss Xin RESET li Low level input As Ds Ais D15 Ate Do Azs Dz P4s P47 P5o P5 current P6o P6 P7o P77 P8o P amp P9 P9 P10o P10 vov s uA RDY HOLD BYTE CNVss Xin RESET Vna Pon source eiit ici I V Icc Power source current f Xw 25 MHz Square mA waveform Ta 25 C when clock uA is stopped Ta 85 C when clock is stopped A D CONVERTER CHARACTERISTICS Vcc 5 V Vss 0 V Ta 20 to 85 C f Xin 25 MHz unless otherwise noted Resolution VREF Veer Voe rc J Bits ZELUM ee O a LSB Riaover Ladder resistance Vre Veo 4 o 1 2 t10 kO tow Conversion time L y y OS ys Ver Reference voltage C O 2 Ve V V Analoginputvoltage O O Ve V 17282 7721 Group User s Manual APPENDIX Appendix 11 Electrical characteristics Internal periphe
79. DATA 16 ROR A DEX DEX DEX BNE LOOP 1 STA A DEST Y SEM DATA 8 STA B DESTT2 Y CLM DATA 16 DEY DEY DEY BNE LOOPO 16 57 APPLICATION 16 3 Comparison of sample program execution rate 16 3 2 Comparison between software Wait f Xw 20 MHz and software Wait Ready f Xin 25 MHz Figure 16 3 3 shows the execution time ratio when sample programs in Figure 16 3 1 are executed on the two conditions in Table 16 3 2 Figure 16 3 2 shows the memory assignment at execution rate comparison The execution time ratio depends on the program or the usage conditions Table 16 3 2 Comparison conditions Processor mode Microprocessor mode 0 25 MHz External data bus width 16 bits Software Wait inserted Ready Valid only for external EPROM area Program area External EPROM Work area Internal or External SRAM M37721 memory map SFR area Internal SRAM Specify either area as work area External SRAM K Area where software Wait is valid Condition Ready valid area Program area Wai which MEME External EPROM nsert Wait which Is equivalent to 2 cycles of at access Software Wait included Fig 16 3 2 Memory assignment at execution rate comparison 16 58 7721 Group User s Manual APPLICATION 16 3 Comparison of sample program execution rate Figure 16 3 3 shows that there is almost no difference between conditions and about the execution time The bus buffers become unnecessary when us
80. DMA1 request sources are external sources Channel priority level Fixed Channel 0 Channel 1 Fig 13 4 8 Transfer example in the burst transfer mode edge sense DMAREQO DMAO request bit DMAO enable bit DMAREQ1 DMA1 request bit DMA1 enable bit DRAM refresh request UTI Right to use bus CPU JDMA REM CPU fomai DMAO CPU CP U Al Channel 1 Entire data transfer Channel 0 Entire data transfer This example applies on the following conditions e Channel priority level Fixed Channel 0 gt Channel 1 Fig 13 4 9 Transfer example in the burst transfer mode level sense 7721 Group User s Manual 13 49 DMA CONTROLLER 13 4 Operation Precautions for burst transfer mode 1 In the burst transfer mode edge sense the DMAi request bit is cleared to 0 when the transfer of an entire batch of data is complete or the transfer is forced into termination Therefore another DMA request of the same channel i is invalid if generated during DMAi transfer m Transition of right to use bus 1 unit transfer Termination processing from DMAC to CPU o J LI LILI LI Lo DMAi request bit is set to 0 Fig 13 4 10 Timing when clearing DMAi request bit to 0 in burst transfer mode 2 Because interrupt priority levels are determined while the CPU fetches an operation code interrupt requests are not accepted during a DMA transfer In the burst transfer mode edge sense therefore interrupt
81. DMAS enable bit z 0 Disabled 1 Enabled P When selecting external DMA source When selecting internal DMA source When selecting internal DMA source except software eee A ee A a Ae eee ee ee A ee ee ee eee eee When selecting software DMA request Inputting DMA request signal to DMAREQi pin DMAC control register H Address 6916 b0 Software DMAO request bit Software DMA1 request bit 0 No request Software DMA2 request bit 1 Requested M When writing 1 DMA request is generated Software DMAS request bit BEER DMA transfer starts Interrupt request of each peripheral function occurs Fig 13 5 4 Initial setting example for registers relevant to single transfer mode 3 13 58 7721 Group User s Manual DMA CONTROLLER 13 5 Single transfer mode 13 5 2 Operation in single transfer mode Figure 13 5 5 shows the operation flowchart of the single transfer mode and Figure 13 5 6 shows a timing diagram of the single transfer mode burst transfer mode For the cycle steal transfer mode refer to the following All transfers except for the last 1 unit transfer Figure 13 8 12 Last 1 unit transfer Figure 13 8 14 Also refer to section 13 2 1 Bus access control circuit for the bus request sampling during transfer DMAi request bit lt 0 Only in cycle steal transfer mode 1 unit transfer Refe
82. F Inside dotted line included Port P77 AN7 ADrac pane peswssw swesstewsewse wee Eus Ports P8 CTSoRTSo P8 1 CL Ko P84 CTSi RTS P8s CLK 0 I Direction register I devic O 3 output Port latch P OUR NT ER Direction register Data bus Port P103 TC E output pin Fig 6 2 5 Port peripheral circuits 2 6 6 7721 Group User s Manual INPUT OUTPUT PINS 6 3 Examples of handling unused pins 6 3 Examples of handling unused pins When unusing an I O pin some handling is necessary for the pin Examples of handling unused pins are described below The following are just examples The user shall modify them according to the user s actual application and test them Table 6 3 1 Examples of handling unused pins Pin name Handling example P43 to P47 P5 to P10 Set these pins to the input mode and connect each pin to Vcc or Vss via a resistor or set these pins to the output mode and leave them open Notes 1 and 2 BLE BHE ALE 1 STO ST1 Leave them open Xour Note 3 HOLD RDY Connect these pins to Vcc via a resistor pull up Note 2 CNVss Connect this pin to Vcc or Vss AVcc Connect this pin to Vcc AVss VREF Connect these pins to Vss Notes 1 When leaving these pins open after they are set to the output mode note the following these pins function as input ports from reset until they are switched to the output mode by software Th
83. ILL XAB ACSB Exchanges the contents of the accumulator A and the con 89 2 tents of the accumulator B 8 n2 E esl L T T TE d C k T L El Lodi d pop T mpm p d p p pae L j J J j j j j j j j jJ j Jj S J j ews ey S J Po p i j j j s R jj a EE 17 52 7721 Group User s Manual APPENDIX Instructions Ine ins Appendix 6 Mach Processor status register Addressing modes 4211 93 aud 42 7 3 83 S sss I p P sS S THEE G A GC NC GS 7 E A E e OO 17 53 7721 Group User s Manual APPENDIX Appendix 6 Machine instructions The number of cycles shown in the table is described in the case of the fastest mode for each instruction The number of cycles shown in the table is calculated for DPRL 0 The number of cycles in the addressing mode concerning the DPR when DPRL 0 must be incremented by 1 The number of cycles shown in the table differs according to the bytes fetched into the instruction queue buffer or according to whether the memory read write address is odd or even It also differs when the external region memory is accessed by BYTE H Notes 1 10 11 12 13 The operation code at the upper row is used for accumulator A and the operation at the lower row is used for accumulator B When setting flag m 0 to handle the data as 16 bit data in the immediate addressing mode the number of bytes increments by 1
84. Interrupt priority level 7 4 Interrupt priority level When the interrupt disable flag I 0 interrupts enabled and more than one interrupt request is detected at the same sampling timing which means a timing to check whether an interrupt request exists or not they are accepted in order of priority levels In other words the interrupt request with the highest priority level is accepted first Among a total of 23 interrupt sources the user can set the desired priority levels for 20 interrupt sources except software interrupts zero division and BRK instruction interrupts and the watchdog timer interrupt Use the interrupt priority level select bits to set their priority levels Priority levels of reset which is handled as the interrupt request with the highest priority and the watchdog timer interrupt are set by hardware Figure 7 4 1 shows the interrupt priority set by hardware Note that software interrupts are not affected by the interrupt priority levels Whenever the instruction is executed a program certainly branches to the interrupt routine Watchdog gt 000080080009 9008888808 gt timer 20 interrupt sources except software interrupts Priority levels determined by hardware and watchdog timer interrupt The user can set the desired priority levels inside of the dotted line Priority level High Fig 7 4 1 Interrupt priority level set by hardware 7721 Group User s Manual 1 9 INTERRUPTS 7 5 Interrup
85. Manual 2 15 CENTRAL PROCESSING UNIT CPU 2 3 Access space 2 3 1 Banks The access space is divided in units of 64 Kbytes This unit is called bank The high order 8 bits of address 24 bits indicate a bank which is specified by the program bank register PG or data bank register DT Each bank can be accessed efficiently by using an addressing mode that uses the data bank register DT If the program counter PC overflows at a bank boundary the contents of the program bank register PG is incremented by 1 If a borrow occurs in the program counter PC as a result of subtraction the contents of the program bank register PG is decremented by 1 Normally accordingly the user can program without concern for bank boundaries SFR Special Function Register and internal RAM are assigned in bank 016 For details refer to section 2 4 Memory assignment 2 3 2 Direct page A 256 byte space specified by the direct page register DPR is called direct page A direct page is specified by setting the base address the lowest address of the area to be specified as a direct page into the direct page register DPR By using a direct page addressing mode a direct page can be accessed with less instruction cycles than otherwise Note Refer also to section 2 1 Central processing unit 2 16 7721 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 4 Memory assignment 2 4 Memory assignment This sect
86. Master microcomputer and one specific slave microcomputer selected from multiple slave microcomputers ee ames some smo Fig 11 4 13 Sleep mode 7721 Group User s Manual 11 47 SERIAL I O 11 4 Clock asynchronous serial I O UART mode MEMORANDUM 11 48 7721 Group User s Manual CHAPTER 12 A D CONVERTER 12 1 Overview 12 2 Block description 12 3 A D conversion method 12 4 Absolute accuracy and differential non linearity error 12 5 One shot mode 12 6 Repeat mode 12 7 Single sweep mode 12 8 Repeat sweep mode 12 9 Precautions for A D converter A D CONVERTER 12 1 Overview 12 1 Overview Table 12 1 1 lists the performance specifications of the A D converter Table 12 1 1 Performance specifications of A D converter Item Performance specifications A D conversion method Successive approximation conversion method Resolution 8 bits Absolute accuracy 3 LSB Analog input pin 8 pins ANo to AN7 Note Conversion rate per analog input pin 57 ap cycles dav A D converter s operation clock The A D converter has the 4 operation modes listed below One shot mode This mode is used to perform the operation once for a voltage input from one selected analog input pin Hepeat mode This mode is used to perform the operation repeatedly for a voltage input from one selected analog input pin Single sweep mode This mode is used to perform the operation for voltages input from multip
87. NUN bed l e S js s pw am io ulel t Lies d 89 el j e dJa Je Ja la de 3 N ekpre 4 42 8 5 42 9 5 CF DF Peis esia sal j Ne 1 3 j 15 cO lt AN MOON C co st eo t co e o o ojo f j j jJ LL 988 amp X9 lel 8 e seis sel EEE se o je pe qu Ll cho up pz oclo j cd dq O C j 0 M co j E wd xc oq C pelo o fo o fo jJ j J 05 22 LLL LL fe mma Eee e TL j T dq 3 q jJ j j C 7 O X qd 3 j lesa i jej E E EO e e j s j j C j 28 C EEO i j j j 9 S e S j C p CO uc j C s C j Jj m Ee ed j j j l j j j j S i e 1o o o ft Jj j S Jj J j i so am ja ee j C j C jJ j C C C s C j j p 33e les ses ss e C j j go j j Jj o ooo ooo o jJ less S Nw o Je Jo j j j Jj j C j j l Jj je 19 ie iO le jd j j bj Jj j Jj j C jJ jJ S j sls E lsrls s5 T j j j ss MEG r co 3 N to tw o td jo G U jJ 7 7 i m ymi y ET mC ON X lt a s s s es s s jJ C C j I T Isis X ABS Y ABL b ABS ABS ABS 17 43 7721 Group User s Manual APPENDIX Appendix 6 Machine instructions Symbol Functions Details IMP bin DIR prx DIR Y DIR DIR X DIR Y
88. Overflow Wait mode A state where the oscillation circuit is operating however the Stop mode program execution is stopped By executing the WIT instruction the microcomputer enters the wait mode 2 7721 Group User s Manual MITSUBISHI SEMICONDUCTORS USER S MANUAL 7721 Group Sep First Edition 1997 Editioned by Committee of editing of Mitsubishi Semiconductor USER S MANUAL Published by Mitsubishi Electric Corp Semiconductor Marketing Division This book or parts thereof may not be reproduced in any form without permission of Mitsubishi Electric Corporation 1997 MITSUBISHI ELECTRIC CORPORATION 7721 Group User s Manual CENESAS Renesas Electronics Corporation 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan
89. P6i RTP1k Port P6i latch Waveform output select bit o O S a9 Q Fig 10 1 1 Block diagram of real time output per bit 10 2 7721 Group User s Manual REAL TIME OUTPUT 10 1 Overview Pulse output data register 0 b7 b0 ETT TT Lf mama S B _ O P6y RTPO x _ Pei RTPO I 1 I I I I Port P6i latch Ho i 0 7 2S P62 RTP02 mO P6s RTPOs Lo Bit 0 of waveform output select bits Pulse output data ied 1 T Dear Data bus even _ I OP6 RTPtc I a E P6s RTP1 Q OPP6 RTP1 8 Lio P67 RTP13 Ly Bit 1 of waveform output select bits Fig 10 1 2 Configuration of real time output in pulse mode 0 Pulse output data register 0 b7 bO TITI modum Bs O PeyRTPOo De 4 8 p 2O P6 RTPO Lr Bit 0 of waveform output select bits Pulse output data register 1 b7 bO E a Bt a D 2 2 O e _F O P62 RTP02 P6s RTPOs 0 O P64 RTP 1o P6s RTP1 O Pe RTP12 E urs Pez RTP 13 Bit 1 of waveform output select bits s aeee Fig 10 1 3 Configuration of real time output in pulse mode 1 7721 Group User s Manual 10 3 REAL TIME OUTPUT 10 2 Block description 10 2 Block description Relevant registers to real time output are described below 10 2 1 Real time output control register Figure 10 2 1 sh
90. PG lt ADu ADL 2 ABS X PCi lt ADu ADL X PCuc ADu ADL X 1 JSR ABS Saves the contents of the program counter also the con M S lt PCH tents of the program bank register for ABL into the stack SS i and jumps to the new address M S lt PCL Sc S 1 PCL AD PCuHc ADu ABL M S PG S lt S 1 M S lt PCuH S S 1 M S e PC S S 1 PCL AD PCHc ADuH PG ADc ABS X M S PCH S lt S 1 M S PC L S lt S 1 PCi lt ADu ADL X PCH lt ADu ADL X 1 Ooo 0E FF AiKs es i Jaje J Jel RR v jJ s 5 j Pa T T T T x jJ T F a 1 T s T Tj O j j 17 44 7721 Group User s Manual APPENDIX Instructions Ine INS Appendix 6 Mach Processor status register N N N 3 89 33 3 N V Z C 33 BL in V 2 7 3 42 53 a 09 c LO co fap cD 1 1 188 99 89 Addressing modes 17 45 7721 Group User s Manual APPENDIX Appendix 6 Machine instructions Addressing modes Symbol Functions Detail ALEX ois ox omy om 3 9 ale on THESE on Bis M LDA AcceM Enters the contents of the memory into the accummulator A9 2 2 Notes 1 2 42 3 42 42 42 A9 A5 B5 B2 LDM MeIMM Enters the immediate vaiue into the memory Note 5 DT lt IMM Enters the immediate value into the data bank regiater XEN into index regi I pj LSR Shifts th
91. RTPOi pun P6o RTPOo RTP OO 006000 0600 C006 660 6660646 S680 0000 56 546544 0000 6600 OO 000000 0600 bodo Port This functions as a programmable I O port HTP This functions as a pulse output pin Fig 10 2 1 Structure of real time output control register 10 4 7721 Group User s Manual REAL TIME OUTPUT 10 2 Block description 10 2 2 Pulse output data registers 0 and 1 Figure 10 2 2 shows the structure of the pulse output data registers O and 1 The bit position of the RTPO and RTPOs pulse output data bits differs according to the pulse mode Before setting the pulse output data registers 0 and 1 set of the pulse output mode select bit bit 2 at address 6216 The data written into the pulse output data registers 0 and 1 is output from the corresponding pulse output pins every underflow of Timers AO and A1 b7 b6 b5 b4 b3 b2 bl Pulse output data register O Address 1A16 ET RTPOo pulse output data bit 0 L level output 1 H level output RTP01 pulse output data bit RTP02 pulse output data bit 2 E Valid in pulse mode 0 RTP03 pulse output data bit K Valid in pulse mode 0 Nothing is assigned lucet Note Use the LDM or STA instruction for writing to this register b7 b6 b5 b4 b3 b2 bi Pulse output data register 1 Address 1C16 0 1 Nothing is assigned RTPO pulse output data bit 0 L level output unen WO Valid in pulse mode 1 1 H level output R
92. Setto 1 by software 4 Count start bit i Timer Ai interrupt j request bit fi frequency of count source I f2 fie fe4 f512 Cleared to 0 when interrupt request is accepted or cleared by software Fig 8 3 4 Example of operation in timer mode without pulse output and gate functions 8 14 7721 Group User s Manual TIMER A 8 3 Timer mode 8 3 4 Selectable functions The following describes the selectable gate function for Timers A2 to A4 and pulse output function 1 Gate function The gate function is selected by setting the gate function select bits bits 4 and 3 at addresses 5816 to 5A16 to 102 or 112 The gate function makes it possible to start or stop counting depending on the TAjw pin s input signal Table 8 3 3 lists the count valid levels Figure 8 3 5 shows an example of operation with the gate function selected When selecting the gate function set the port P5 direction registers bits which correspond to the TAjin pin for the input mode Additionally make sure that the TAjw pin s input signal has a pulse width equal to or more than two cycles of the count source Table 8 3 3 Count valid levels aale BOn n Count valid level Duration while counter counts 1 0 a While TAjw pin s input signal is at L level 1 1 While TAjin pin s input signal is at H level Note The counter does not count while the TAjin pin s input signal is not at the count valid leve
93. The access characteristics for the timer BO register and timer B1 register differ according to Timer B s operating mode 2 Read from or write to this register in a unit of 16 bits Timer Bi mode register b7 b6 b5 b4 b3 b2 bi b0 UM Timer Bi mode register i 0 to 2 Addresses 5B16 to 5D 6 pat on crees 0 emere Operating mode select bits Timer mode Event counter mode Pulse period Pulse width RW measurement mode Do not select ERLA 0 RW Undefined ES Undefined RO Note o RW o RW Noie Bit 5 is invalid in the timer and event counter modes its value is undefined at reading 7721 Group User s Manual 17 23 APPENDIX Appendix 3 Control registers Timer mode b15 b8 b7 bO b7 bO Timer BO register Addresses 5116 5016 PY Timer 1 register Addresses 531e 521s Timer B2 register Addresses 5516 5416 15 to 0 These bits can be set to 000016 to FFFF16 Undefined RW Assuming that the set value n the counter divides the count source frequency by n 1 When reading the register indicates the counter value Note Read from or write to this register in a unit of 16 bits b7 b6 bd De b3 b2 bl b1 bO 0 0 Timer mode b7 b6 00 fe 01 fie 10 fea 1 fs12 17 24 7721 Group User s Manual APPENDIX Appendix 3 Control registers Event counter mode b15 b8 b7 bO b7 00 Timer BO register Addresses 5116 501
94. Viu 4 0 V Output timing voltage Vor 0 8 V Vou 2 0 V 17 88 7721 Group User s Manual APPENDIX Appendix 11 Electrical characteristics Microprocessor mode with no Wait Note The limits depend on f Xin Table 4 lists calculation formulas for the limits Timing requirements Vcc 5 V 10 Vss 0 V Ta 20 to 85 C f Xin 25 MHz unless otherwise noted Symbol tc tw H tw L tr ti tsu PiD E th E PiD Switching characteristics Vcc 5 V 10 Vss 0 V Ta 20 to 85 C f Xin 25 MHz unless otherwise noted Symbol ta E PiQ la AL E ta E DHQ tpxz E DHZ td AM E td AM ALE la E DLQ tpxz E DLZ td AH E d AH ALE td ALE E tw ALE td BHE E td BLE E ta R W E t d E 91 th E AL th ALE AM th E DHO lpzx E DHZ lh E AM th ALE AH th E DLQ tpzx E DLZ th E BHE th E BLE th E R W tw EL lsu A DL tsu ALE DL tsu A DH lsu ALE DH Limits External clock input cycle time 40 External clock input high level pulse width 45 External clock input low level pulse width J 15 External clock input rising time a External clock input falling time o 8 Port Pi input setup time i 4 10 Port Pi input hold time i 4 10 oJ O o Parameter Parameter Port Pi data output delay time i 2 4 10 Address low order output delay time Data high order outp
95. When 1 cycle of has passed after the levels of the STO and ST1 pins are changed the R W BHE BLE pins and the external bus enter the floating state In Hold state when the HOLD pin s input level becomes H the STO and ST1 pins levels are changed at the next rising edge of 0 When 1 cycle of has passed after the levels of the STO and ST1 pins are changed the microcomputer terminates Hold state Figures 3 4 1 to 3 4 3 show timing of acceptance of Hold request and termination of Hold state Note has the same polarity and the same frequency as clock 6i However stops by acceptance of Ready request or executing the STP or WIT instruction Accordingly judgment of the input level of the HOLD pin is not performed during Ready state 3 12 7721 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 3 4 Hold function lt When inputting L level to HOLD pin while bus is unused gt State when inputting L level to HOLD pin External data bus Data length External data bus width Unused 16 8 16 Clock 1 Note 1 Bus request Hold Note 2 Bus request sampling Note 2 I I I I I I I I l I I I I External address bus x Floating External data bus gt lt a Address B Hold state Bus notin use lt j gt Bus in use Transfer of right to use bus Trans
96. When using these pins as Timer Aj s input pins set the corresponding bits of the port P5 direction register to O to set these port pins for the input mode When used as Timer Aj s output pins these pins are forcibly set to the output pins of Timer Aj regardless of the direction registers s contents Figure 8 2 5 shows the relationship between the port P5 direction register and the Timer Aj s I O pins b7 b6 b5 b4 b3 b2 bl Port P5 direction register Address D16 EN TA2ovr pin 0 Input mode oo Rw 1 Output mode When using these pins as Timer Aj TA3our pin s input pins set the corresponding FEET Po rw Ts ro Po rw De pw Bits 6 and 7 are not used for Timer A Fig 8 2 5 Relationship between port P5 direction register and Timer Aj s I O pins 8 8 7721 Group User s Manual TIMER A 8 3 Timer mode 8 3 Timer mode In this mode the timer counts an internally generated count source Refer to Table 8 3 1 Figure 8 3 1 shows the structures of the timer Ai mode register and timer Ai register in the timer mode Table 8 3 1 Specifications of timer mode Item Specifications Count source f2 fie fea Or fsi2 Count operation e Countdown e When a counter underflow occurs reload register s contents are reloaded and counting continues Division ratio 1 n 1 n Timer Ai register s set value Count start condition When the count start bit is set to 1 Count stop condition When the co
97. and that of reception can be matched For details refer to section 11 4 6 Receive operation When using interrupts it is necessary to set the relevant registers to enable interrupts For details refer to CHAPTER 7 INTERRUPTS Figure 11 4 10 shows processing after receive completion 7721 Group User s Manual 11 41 SERIAL I O 11 4 Clock asynchronous serial I O UART mode UARTO transmit receive mode register Address 3016 gt UART1 transmit receive mode register Address 3816 UARTO baud rate register BRGO Address 31 16 UN UART1 baud rate register BRG1 Address 3916 b2b1b0 b7 b0 100 UART mode 7 bits 1 1 0 UART mode 9 bits J F Internal External clock select bit 0 Internal clock 1 External clock V Can be set to 0016 to FF46 Stop bit length select bit 0 1 stop bit son P8 direction register Address 1416 1 2 stop bits b7 b0 Odd Even parity select bit 0 Odd parity 1 Even parity RxDo pin RxD1 pin Parity enable bit 0 Parity disabled 1 Parity enabled X Sleep select bit 0 Sleep mode terminated Invalid Ne 1 Sleep mode selected D Note Set the transfer data format in the same way as set on the transmitter side UARTO transmit receive control register 0 Address 3416 UART1 transmit receive control register 0 Address 3Ct6 b7 bO eee UARTO receive interrupt control register Ad
98. b16 b15 b8 S 7 b23 b16 b15 b8 M b7 b0 b7 b0b7 po Destination address register 0 Destination address register 1 Destination address register 2 Destination address register 3 I Transfer counter register 3 Addresses 1FFAte to 1FF816 Set the byte number of transfer data These bits can be set to 00000116 to FFFFFF e Set the transfer start address of transfer source These bits can be set to 00000016 to FFFFFF 6 Addresses 1FC616 to 1FC416 Addresses 1FD6 6e to 1FD416 Addresses 1FE616 to 1FE416 Addresses 1FF61 6 to 1FF4 16 DAR1 Non Set the transfer start address of destination These bits can be set to 00000016 to FFFFFF46 b7 b0 b7 b0b7 b0 Transfer counter register 0 Addresses 1FCA16 to 1FC816 TCRO l1 T Transfer counter register 1 Addresses 1FDA16 to 1FD816 TCR1 C gt Transfer counter register 2 Addresses 1FEA e to 1FE816 TCR2 TCR3 DARO DAR2 DAR3 Notes 1 When writing to these registers write to all 24 bits 2 Do not write 00000016 to TCRi j sauuuuuuEEENENEN Note 3 When data is transferred from memory to I O in 1 bus cycle transfer it is unnecessary to set DARi When data is transferred form I O to memory in 1 bus cycle transfer it is unnecessary to set SARi Note When an external source DMAREQi is selected or when the cycle steal transfer mode is selected set this bit
99. b6 b5 b4 b3 b2 bi b0 Pe EBEN DRAM control register Address 6416 w b3 b2 b1 bO DRAM area select bits 0 0 0 0 No DRAM area 000 1 F0000016s FFFFFF16 1 Mbyte 0 0 1 0 E00000is FFFFFF46 2 Mbytes D00000 e FFFFFF e 3 Mbytes 00000 e FFFFFF e 4 Mbytes BO000016 FFFFFF 6 5 Mbytes A000001e FFFFFF 6 6 Mbytes 9000001e FFFFFF 6 7 Mbytes 80000016 FFFFFF 6 8 Mbytes 70000016 FFFFFF 16 9 Mbytes 60000016 FFFFFF 16 10 Mbytes 5000001e FFFFFFie 11 Mbytes 400000 e FFFFFF e 12 Mbytes 3000001e FFFFFF 16 13 Mbytes 200000 e FFFFFF e 14 Mbytes 100000 e FFFFFF 6 15 Mbytes 6 to 4 Nothing is assigned The value is 0 at reading eM DRAM validity bit Note 0 Invalid P104 P107 pins function as programmable input ports Ao A pins function as address output pins Refresh timer stops counting 1 Valid P104 P107 pins function as CAS RAS MAs and MAs Ao Az function as MAo MA Refresh timer starts counting Le eee ee om omo mom lt m mo m m Note Set the refresh timer address 6616 before setting this bit to 1 Refresh timer b7 b0 Le Refresh timer Address 66 6 7 to 0 These bits can be set to 0116 to FF e Undefined WO Assuming that the set value n this register divides f e by n 1 Note Use the LDM or STA instruction for writing to this register Do not
100. be read out While counting is stopped When a value is written to the timer Bi register it is written to both of the reload register and counter While counting is in progress When a value is written to the timer Bi register it is written only to the reload register Transferred to the counter at the next reload time n Timer Bi register s set value 7721 Group User s Manual TIMER B 9 3 Timer mode b7 b6 b5 os b3 b2 bl b1 bO 00 Timer mode Undefined b7 b6 01 fie 10 fea RW 11 fs12 Timer BO register Addresses 5116 5016 Timer B1 register Addresses 5316 5216 Timer B2 register Addresses 5516 5416 15 to 0 These bits can be set to 0000 e to FFFF e Undefined RW Assuming that the set value n the counter divides the count source frequency by n 1 When reading the register indicates the counter value Note Read from or write to this register in a unit of 16 bits Fig 9 3 1 Structures of timer Bi mode register and timer Bi register in timer mode 7721 Group User s Manual 9 9 TIMER B 9 3 Timer mode 9 3 1 Setting for timer mode Figure 9 3 2 shows an initial setting example for registers relevant to the timer mode Note that when using interrupts set up to enable the interrupts For details refer to CHAPTER 7 INTERRUPTS scia timer mode and count source E Dr 00 Timer Bi mode register i 0 to 2 x x x 0 o Addresses 5B16 to 5D 6 E Selection of ti
101. between falling edges of measurement pulse Pulse period measurement Interval between rising edges of measurement pulse Pulse width measurement Interval from a falling edge to a rising edge and from a rising edge to a falling edge of measurement pulse 1 Do not select Nothing is assigned E tos 5 Timer Bj overflow flag No overflow Undefined acc depict Note Overflowed fie 1 0 fea 1 f512 Note The timer Bj overflow flag is cleared to 0 at the next count timing of the count source when a value is written to the timer Bj mode register with the count start bit 1 b15 b8 b7 bO b7 bO r Timer BO register Addresses 5116 5016 Timer B1 register Addresses 5316 5216 ES to 0 The measurement result of period or Undefined pulse width is read out Note Read from this register in a unit of 16 bits Fig 9 5 1 Structures of timer Bj mode register and timer Bj register in pulse period pulse width measurement mode 9 20 7721 Group User s Manual TIMER B 9 5 Pulse period Pulse width measurement mode 9 5 1 Setting for pulse period pulse width measurement mode Figure 9 5 2 shows an initial setting example for registers relevant to the pulse period pulse width measurement mode Note that when using interrupts set up to enable the interrupts For details refer to CHAPTER 7 INTERRUPTS U Selecting pulse period pulse width
102. changed In the cycle steal transfer mode not changed Note 0 Outputs L when the TC pin is valid Rotating when the rotating priority is selected Note In the cycle steal transfer mode the DMAi request bit is cleared to 0 when a DMA request is accepted This bit is does not change at normal termination At normal termination the CPU regains the right to use bus after the terminate processing 3 cycles of via the transition of the right to use bus 1 cycle of 9 Figure 13 3 3 shows a timing example at normal termination 7721 Group User s Manual 13 25 DMA CONTROLLER 13 3 Control 1 ALE R W Address Address Data DMAi enable bit DMAi request bit DO BUS REQUEST DMAC Bus request sampling DMAACKi TC ST1 STO DMAI interrupt request bit Transition of right to use bus Terminate processing When Burst transfer mode edge sense selected When Burst transfer mode level sense selected When Cycle steal transfer mode selected The above timing diagram applies on the following conditions e DMAACKi valid TC valid e External source DMAREQI Fig 13 3 3 Timing example at normal termination 13 26 7721 Group User s Manual DMA CONTROLLER 13 3 Control 2 Forced termination The methods of terminating DMAC other than normal termination are as follows Drives the TC pin s input level from H to L during a DMA transfer when the TC p
103. condition Software Wait 1 Make sure that the propagation delay time is within 20 ns 2 Make sure that the output disable time is within 20 ns Fig 16 1 14 Example for using bus buffers 2 connecting with memory requiring long data hold time for writing 16 18 7721 Group User s Manual APPLICATION 16 1 Memory connection lt When reading gt tw EL 135 min E OC AC245 tpzx E DLZ DHZ 20 min As Ds A15 D15 A16 Do A23 D7 X A gt lt AC32 tPHL AC32 tPLH RD AC245 AC245 Data output A from tPZH tPZL gt tPHZ tPLZ external memory AC245 0 e q4 KX D o oo ye When writing 01 tw EL 135 min u 1Q AC74 mil S J lt AC04 tPLH AC74 tPLH 2Q AC74 Z AC32 X 2 tPLH S ON As Ds Ais D 34 35 max 8 U8 A 15 U15 Aite Do Aes D7 C A X D Jj AC245 Data output B from tPHL tPLH i tPHZ tPLZ external memory AC245 0 777707 C X D jJ lt lt Write hold time Unit ns Fig 16 1 15 Timing chart for circuit example using bus buffers 2 7721 Group User s Manual 16 19 APPLICATION 16 1 Memory connection 16 1 3 Example of memory connection Examples of the flash memory SRAM and DRAM connection and the timing charts are described as follows 1 Example of flash memory connection minimum model M5M28F101AFP 10 x
104. contents of accumulator A into the stack Saves the contents of accumuator B into the stack ios na a bal MN ORA Logical sum per bit of the contents of the accumulator and pf l o Ss 1 d ARA c 5 ofj 55 Pw ee v wvm v X c oj vost L L LLL L PS cS PS E a a A cC no ooo o j SL 1 e s e j j _ E ee ewe J j j j 9 w s x x j eR S l 9S8 t SER zele ff c 1 1 S C Lb Jj j S 5 _ E a fe EY ET ee eR ee ej PO ewe eX 17 46 7721 Group User s Manual APPENDIX Instructions Ine INS Appendix 6 Mach ceo lelo J q e cq J q Jej qe C a J L 17 g N N j J N N JN N Ter fe fe N fe fr fer fe LLL oivi l te fe Te L Ll te Je Je jJ Le C o jJ LLL LEE LLL Le e O oj o e o l fe fe fe Le fe fete Le fe fr fe fe O O y e ALe ee ee ee i C 5 EM 2 S 7 SC CS s gt o o Jo o Jo fe fr fe fete fe Le fe fs fs s j Tr eer e j e s j j S 9 u e Se Lt Le o Jo Je jo Je o jo C o Jj oO O e O LLLA ECT ERE EA eo T oO Se ee a l a a e O Se rr OO O H EET I s ES a L wai L T ABS REL DIR b R Addressing modes ABL 89 E MS LL CN LL T b st LO N LL N LL lt lt lt oO co N O CN O gt lt M X Pete sss js 188 j j je
105. control signal from the address comparator and is output to the MAo MAs pins The time sharing method depends on the external bus width Table 14 2 2 lists the time sharing method for the address at DRAM access When the 8 bit external bus width is selected Ao A19 are time shared and are output when the 16 bit external bus width is selected Ai Azo are time shared and are output Table 14 2 2 Time sharing method for address at DRAM access meea A2 MA2 As MAs A4 MA1 As MAs As MAs A7 MA7 P106 MAs P107 MAg os width Br war Pin name 14 6 7721 Group User s Manual DRAM CONTROLLER 14 3 Setting for DRAMC 14 3 Setting for DRAMC Figure 14 3 1 shows an initial setting example for registers relevant to DRAMC Division ratio setting for refresh timer b7 bO O Refresh timer Address 6616 V J Loo Can be set to 0016 to FF 16 n Refresh timer divides f16 by n 1 DRAM area setting and DRAM validity selection DRAM control register Address 6416 DRAM area select bits b3 b2b1 bO 0 00 0 No DRAM area 0 0 0 1 Addresses F000001e FFFFFFt1e 1 Mbyte 0 0 1 0 Addresses E0000016e FFFFFF16 2 Mbytes 0 0 1 1 Addresses D0000016e FFFFFF16e 3 Mbytes 0 100 Addresses C0000016e FFFFFF16e 4 Mbytes 0 101 Addresses B000001e FFFFFF 16 5 Mbytes 0 1 1 0 Addresses A000001e FFFFFF 16 6 Mbytes 0 1 1 1 Addresses 90000016 FFFFFF 16 7 Mbytes 1
106. conversion start bit A D conversion start bit bit 6 When internal trigger is selected Setting this bit to 1 generates a trigger causing the A D converter to start operating Clearing this bit to O causes the A D converter to stop operating In the one shot mode or single sweep mode this bit is cleared to O after the operation is completed In the repeat mode or repeat sweep mode the A D converter continues operating until this bit is cleared to O by software When external trigger is selected When the ADTRG pin level goes from H to L with this bit 1 a trigger occurs causing the A D converter to start operating The A D converter stops when this bit is cleared to 0 In the one shot mode or single sweep mode this bit remains set to 1 even after the operation is completed In the repeat mode or repeat sweep mode the A D converter continues operating until this bit is cleared to O by software A D conversion frequency ab select bit bit 7 As listed in Table 12 2 1 the conversion time of the A D converter varies depending on the operating clock dap selected by this bit Since the A D converter s comparator consists of capacity coupling amplifiers keep that 4 gt 250 kHz during A D conversion Table 12 2 1 Conversion time per one analog input pin unit ps AD A D conversion frequency ao select bit i EE 1 fo 4 f2 2 Conversion time f Xin 8 MHz
107. depend on f Xin Table 5 lists calculation formulas for the limits Read twm RAS low level pulse width Note x ss ns twcaso CAS low level pulse width Note 925 ns twrast CAS high level pulse width Not 60 ns tanas cas HAS CAS delay time Not 28 ns LatRA RAS Bow address delay time before RAS __ Nete _5_ ns thimas RA Row address hold M 81 ns taica cas ns inteas on Column address hol ime aer CRS Note s ns lanw nas R W delay time before RAS Note 18 X ms twoas aw R W hold time after CAS Nte 18 X ns tae ca Column address delay time after E s low level Note 65 ns tae wso RAS delay time after Es low level boa 30 ns tae ons CAS delay time after E s low level Note 77 5 ns ta amp Ras RAS delay time after E s high level 20 ns tae casH CAS delay time after E s high level 0 20 ns Note Figure 13 shows the test circuit Write twrast RAS low level pulse width Note m ME tw CAsL CAS low level pulse width Note 55 ns twrash CAS high level pulse width Note seol ns taRas cas RAS CAS delay time Note 60 ns taRA RAs Row address delay time before RAS Note 5 ns tniRas RA Row address hold time after RAS Note ns taca cas Column address delay time bef
108. edge when edge sense is selected Level sense Edge sense E Edge sense select bit Level sense 7 ED Nothing is assigned ume MM cg gcc cc ee eB ee Be ee Note The interrupt request bits of INTo to INT2 interrupts are invalid when the level sense is selected 17 32 7721 Group User s Manual APPENDIX Appendix 3 Control registers Source address register i b23 Destination address register i b23 Transfer counter register i b23 b16 b15 b16 b15 b16 b15 b8 b7 b8 b7 b8 b7 bO bO bO Source address register 0 Addresses 1FC216 to 1FC016 Source address register 1 Addresses 1FD216 to 1FD016 Source address register 2 Addresses 1FE216 to 1FE016 Source address register 3 Addresses 1FF216 to 1FF016 23 to 0 These bits have different functions according to the Undefined RW operating mode Note When writing to this register write to all 24 bits Addresses 1FC616 to 1FC4416 Addresses 1F D616 to 1FD4416e Addresses 1FE616e to 1FE416 Addresses 1FF616e to 1FF416 Destination address register O Destination address register 1 Destination address register 2 Destination address register 3 23 to 0 These bits have different functions according to the Undefined RW operating mode Note When writing to this register write to all 24 bits SQ nS Addresses 1FCA te to 1FC816 Addresses 1FDA te to 1FD816 Addresses 1FEAte to 1FE816 Addresses 1FF
109. error is 24 20 4 mV 0 2 LSB Measurement conditions Vcc 5 V Vrer 5 12 V f Xin 25 MHz Ta 25 C ab fe divided by 2 TT r CUT T hn a R O NA mein hederae der em ede e Per a ume eem Rene LLLI Lol pe ERROR mV l 1LSB WIDTH mV ANAA m ss tp peepee ms LL 428 136 144 152 160 168 176 184 koa 200 208 216 224 256 ERROR mV 1LSBWIDTH mV 7721 Group User s Manual 17 109 APPENDIX Appendix 12 Standard characteristics MEMORANDUM 17 110 7721 Group User s Manual GLOSSARY GLOSSARY This section briefly explains the terms used in this user s manual The terms defined here apply to this manual only Term Meaning Relevant term Access Means performing read write or read and write Access space An accessible memory space of up to 16 Mbytes Access Access characteristics Means whether accessible or not Access Branch Means moving the program s execution point address to another location Bus control signal A generic name for ALE E R W BLE BHE RDY HOLD HLDA BYTE STO and ST1 signals Countdown Countup Count source A signal that is counted by timers A and B the UARTi baud rate register BRGi and the watchdog timer That is f2 f16 fe4 f512 selected by the count source select bits and others Countup Means increasing by 1 and counting Countdown External area An accessible area for external devices connected It is up
110. f XiN td E RASL 30 td E CASL 1 X 10 1375 f XiN la E CA 1 X 10 f Xin tpzx E DLZ 1X 10 20 tpzx E DHZ f Xin tsu DL E 30 tsu DH E Note When accessing DRAM Wait is always inserted regardless of the contents of the Wait bit source s Wait bit and destination s Wait bit RAS access time TRAC Column address access time TAA CAS access time CAC o E 2 Y Qu D O O lt 13 14 15 16 External clock input frequency f XIN Fig 16 1 4 Relationship between tcac trac taa and f Xin 7721 Group User s Manual 16 7 APPLICATION 16 1 Memory connection 2 Timing for writing data When writing data the output data is stabilized when an interval of tao a pug has passed after the falling edge of the E signal This data is continuously output until when an interval of tne o o nuo has passed after the rising edge of the E signal Data to be written to an external memory must satisfy the data set up time tsu for DRAM the data hold time to of the external memory The following are described below Timing for writing data to flash memory SRAM and DRAM Calculation formulas which are for tsuo and ton to be satisfied Timing for writing data to flash memory and SRAM External memory write s
111. for each peripheral devices 7721 Group User s Manual 2 23 CENTRAL PROCESSING UNIT CPU 2 5 Bus access right MEMORANDUM 2 24 7721 Group User s Manual CHAP TIER CONNECTION WITH EXTERNAL DEVICES 3 1 Signals required for accessing external devices 3 2 Software Wait 3 3 Ready function 3 4 Hold function Precautions for Hold function CONNECTION WITH EXTERNAL DEVICES 3 1 Signals required for accessing external devices 3 1 Signals required for accessing external devices The functions and operations of the signals which are required for accessing the external devices are described below When connecting an external device that requires long access time refer to sections 3 2 Software Wait 3 3 Ready function and 3 4 Hold function as well as this section When the external DRAM is controlled by using DRAM controller refer to CHAPTER 14 DRAM CONTROLLER 3 1 1 Descriptions of signals Figure 3 1 1 shows the pin configurations when the external data bus width is 16 bits and 8 bits 1 2 3 4 External buses Ao A As Ds A s D s A1e Do Az23 D7 The external area is specified by the address Ao Azs output The As Azs pins of the external address bus and the Do D s pins of the external data bus are assigned to the same pins When the BYTE pin level described later is L external data bus width is 16 bits the As Ds A1s Dis and A1e Do
112. gw 7721 Group User s Manual APPENDIX Appendix 11 Electrical characteristics Table 5 Calculation formulas for DRAM control bus timing depending of f Xin Vcc 5 V 10 Vss 0 V Ta 20 to 85 C Read Symbol Calculation formula Symbol Calculation formula Unit tw RASL 4 x 10 th CAS CA 4 X 10 40 _ ns f Xin FOXin 60 w CASL d R W RAS f XiN w RASH 9 h CAS R W 2 X 10 1 X 10 i f Xin Xin td RAS CAS 1 x 10 Tene 1 7 10 2 ns f Xin ELE td RA RAS 1 X 10 d E CASL 1 x 10 375 ns f Xin f Xin o TDO f XiN Write Symbol Calculation formula Symbol Calculation formula Unit tw RASL 4 X 10 ld CA CAS 9 f Xm f XiN IN w CASL 2 u T CAS CA 3 x 109 Z ns RR ep f XiN n tw RASH 9 d R W RAS 2 X 10 1 X 10 25 e f XiN f XiN ta RAS CAS 2 x 10 h CAS R W 1 X 10 22 ns f Xin f Xin ta RA RAS 1 X 109 d E CASL 2 X 10 Xn 35 f Xin 35 0 ns n RAS RA 1 X 10 anm MAI m The value within is for the minimum value Refresh Symbol Calculation formula Symbol Calculation formula Unit tw RASL 4 X 10 ld CAS RAS 1 X 102 40 ns 22 ns f Xm f Xin lw CASL 2 x 10 h RAS CAS 9 ns ns f Xin l 7721 Group User s Manual 17 105 APPENDIX Appendix 11 Electrical characteristics Table 6 Calculation formulas for DMA transfer bus timing depending on f Xin
113. in 2 bus cycle transfer and section 13 4 2 2 Bus operation in 1 bus cycle transfer Also for the time from DMA request generation until the start of the DMA transfer refer to section 13 3 4 Processing from DMA request until DMA transfer execution and for that from issuing instructions for forced termination until returning the right to use bus to the CPU refer to section 13 3 5 2 Forced termination 13 9 1 Cycle steal transfer mode 1 1 unit transfer In the following cases 1 unit transfer is performed at one DMAi transfer Refer to Figure 13 8 12 e Single transfer mode except for the last 1 unit transfer Repeat transfer mode except for the last 1 unit transfer of a block Array chain transfer mode except for the first and last 1 unit transfers of each block Link array chain transfer mode except for the first and last 1 unit transfers of each block Right to use Transition Transfer Transition iN Fig 13 9 1 1 unit transfer Transition of the right to use bus from CPU to DMAC 1 cycle DMA transfer per 1 transfer unit e In 2 bus cycle transfer Read cycle Write cycle Add a value which satisfies the read write conditions Refer to Table 13 4 1 e In 1 bus cycle transfer Refer to Table 13 4 5 Transition of the right to use bus from DMAC to CPU 1 cycle Example 2 bus cycle transfer transfer unit 216 bits external data bus width 16 bits and under the following conditi
114. instruction is executed this flag s contents determine whether the program causes a branch or not Use the SEP instruction to set this flag to 1 and use the CLP instruction to clear it to 0 Note This flag is invalid in the decimal mode addition the ADC instruction 3 Bit 2 Interrupt disable flag I It disables all maskable interrupts interrupts other than watchdog timer the BRK instruction and zero division Interrupts are disabled when this flag is 1 When an interrupt request is accepted this flag is automatically set to 1 to avoid multiple interrupts Use the SEI or SEP instruction to set this flag to 1 and use the CLI or CLP instruction to clear it to 0 This flag is set to 1 at reset 4 Bit 3 Decimal mode flag D It determines whether addition and subtraction are performed in binary or decimal Binary arithmetic is performed when this flag is 0 When it is 1 decimal arithmetic is performed with 8 bits treated as two digits decimal the data length flag m 1 or 16 bits treated as four digits decimal the data length flag m 2 0 Decimal adjust is automatically performed Decimal operation is possible only with the ADC and SBC instructions Use the SEP instruction to set this flag to 1 and use the CLP instruction to clear it to 0 This flag is cleared to 0 at reset 5 Bit 4 Index register length flag x It determines whether each of index re
115. is 1 When the switching between countup and countdown is set while counting is in progress this switching is actually performed when the count source s next valid edge is input 1 Switching by up down bit Countdown is performed when the up down bit is 0 and countup is performed when the up down bit is 1 Figure 8 4 5 shows the structure of the up down register 2 Switching by TAjour pin s input signal Countdown is performed when the TAjour pin s input signal is at L level and countup is performed when the TAjour pin s input signal is at H level When using the TAjour pin s input signal to switch countup from and to countdown set the port P5 direction register s bit which corresponds to the TAjour pin for the input mode b7 b6 b5 b4 b3 b2 bi bO folol Up down register Address 4416 al Fix these bits to 0 W 3 E Ed 1 Countup 3 Timer A3 up down bit This function is valid when the contents of the up down register is selected as the up Timer A4 up down bit down switching factor 5 Timer A2 two phase pulse signal 9 Two phase pulse signal processing select bit Note processing function disabled 1 Two phase pulse signal m Timer A3 two phase pulse signal processing function enabled rocessing select bit Note P 9 When not using the two phase pulse 7 Timer A4 two phase pulse signal de processing function set the bit processing select bit Note The value is 0 at reading Not
116. is compared with the processor interrupt priority level IPL The requested interrupt is enabled only when its priority level is higher than the IPL However this applies when the interrupt disable flag I 0 To disable UARTI transmit receive interrupts set these bits to 0002 level 0 2 Interrupt request bit bit 3 The UARTi transmit interrupt request bit is set to 1 when data is transferred from the UARTI transmit buffer register to the UARTi transmit register The UARTI receive interrupt request bit is set to 1 when data is transferred from the UARTi receive register to the UARTi receive buffer register However when an overrun error occurs it does not change Each interrupt request bit is automatically cleared to 0 when its corresponding interrupt request is accepted This bit can be set to 1 or 0 by software 11 14 7721 Group User s Manual SERIAL I O 11 2 Block description 11 2 8 Port P8 direction register I O pins of UARTi are multiplexed with port P8 When using pins P82 and P86e as serial data input pins RxDi set the corresponding bits of the port P8 direction register to O to set these pins for the input mode When using pins P8o P8 P8s to P8s and P87 as I O pins CTS RTSi CLK TxDi of UARTi these pins are forcibly set as I O pins of UARTi regardless of the port P8 direction register s contents Figure 11 2 13 shows the relationship between the port P8 direction re
117. is completed Accordingly the operation of the A D converter can be performed again from step when the level of the ADrne pin changes from H to L When the level of the ADrace pin changes from H to L during operation the operation at that point is cancelled and is restarted from step Figure 12 7 2 shows the conversion operation in the single sweep mode 7721 Group User s Manual A D CONVERTER 12 7 Single sweep mode Trigger occur Convert input voltage from Conversion result ANo pin lt gt A D register 0 Convert input voltage from Conversion result AN pin A D register 1 Convert input voltage from Conversion result A ANi pin A D register A D converter interrupt request occur A D converter halt Fig 12 7 2 Conversion operation in single sweep mode 7721 Group User s Manual 12 23 A D CONVERTER 12 8 Repeat sweep mode 12 8 Repeat sweep mode In the repeat sweep mode the operation for the input voltages from the multiple selected analog input pins is performed repeatedly The A D converter is operated in ascending sequence from the ANo pin In this mode no A D conversion interrupt request occurs Additionally the A D conversion start bit bit 6 at address 1E e remains set to 1 until it is cleared to 0 by software and the operation is performed repeatedly while the A D conversion start bit is 1 12 8 1 Settings for repeat sweep mode Figure 1
118. is selected eA UARTI transmit interrupt request occurs and the interrupt request bit is set to 1 The transmit operations are described below Data in the UARTI transmit register is transmitted from the TxDi pin synchronously with the falling edge of the transfer clock This data is transmitted bit by bit sequentially beginning with the least significant bit When 1 byte data has been transmitted the transmit register empty flag is set to 1 This indicates the completion of transmission Figure 11 3 4 shows the transmit operation When an internal clock is selected when the transmit conditions for the next data are satisfied at completion of the transmission the transfer clock is generated continuously Accordingly when performing transmission continuously set the next transmit data to the UARTi transmit buffer register during transmission when the transmit register empty flag 0 When the transmit conditions for the next data are not satisfied the transfer clock stops at H level Figures 11 3 5 and 11 3 6 show examples of transmit timing b7 bO UARTI transmit buffer register Transmit data V MSB LSB Transfer clock UARTI transmit register D7 De Ds D4 Ds D2 Di Do ET Tos os es os e os gt ox ESI p os os bs ps pz P WU p bs bs ba p D2 ARRRRRRRIE Ss gt Fig 11 3 4 Transmit operation 7721 Group User s Manual 11 21 SERIAL I O 11 3 Clock
119. is used the setting for enabling the interrupt is also required For details refer to CHAPTER 7 INTERRUPTS When external DMA source is selected When internal DMA source is selected Setting port P9 direction register b7 bO Port P9 direction register Address 1516 DMAREQO pin DMAREQ pin DMAREQ2 pin DMAREQOS pin Clear the corresponding bit to 0 PORE ce ipe err errr creer erry Setting interrupt priority level b7 bO DMAi interrupt control register i 0 to 3 Addresses 6Cie to 6F 6 Interrupt priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 A Continue to Figure 13 7 4 on next page Fig 13 7 3 Initial setting example for registers relevant to array chain transfer mode 1 13 72 7721 Group User s Manual DMA CONTROLLER 13 7 Array chain transfer mode From preceding Figure 13 7 3 Selection of transfer mode and each function b7 fo bO bO MV a DMAO mode register L Address 1FCCie b7 DMA1 mode register L Address 1FDCie DMA2 mode register L Address 1FEC16 DMAS mode register L Address 1FFCie Number of unit transfer bits select bit 0 16 bits 1 8 bits Transfer method select bit 0 2 bus cycle transfer 1 1 bus cycle transfer Transf
120. memory SRAM and DRAM Calculation formulas for the external memory s access time which are for tsupupr s to be satisfied The memory output enable signal OE is assumed to be generated from the E signal Timing for reading data from flash memory and SRAM External memory output enable signal Read signal External memory chip select signal CE S pues Address Address output and Data input As Ds A15 D15 x A16 Do A23 D7 ta AD tsu A DL DH ta ce tars tor tdis OE ten cE tens External memory data output Specifications of the M37721 The others are specifications of external memory 1 This applies when the external data bus has a width of 16 bits BYTE L k2 If data is output from the external memory before the falling edge of E there is a possibility that the tail of address collides with the head of data Refer to section 3 Precautions on memory connection k3 If one of the external memory s specifications is greater than tpzx E pLZ DH2 there is a possibility that the tail of data collides with the head of address Refer to section 3 Precautions on memory connection Note tsu A DL DH tsu A DL OF tsu A DH tpzx E DLZ DHZ tpzx E DLZ Or tpzx E DHZ tsu DL DH E tsu DL E Or tsu DH E Fig 16 1 1 Timing for reading data from flash memory and SRAM 16 4 7721 Group User s Manual APPLICATION 16 1 Memory connection Address ac
121. of handling unused pins Examples of handling unused pins are described below These descriptions are just examples The user shall modify them according to the actual application and test them Table 1 Examples of handling unused pins Pins Handling example P43 to P47 P5 to P10 Connect these pins to the Vcc or Vss pin via resistors after these pins are set to the input mode or leave these pins open after they are set to the output mode Notes 1 2 BLE BHE ALE STO ST1 Leave this pin open Xout Note 3 Leave this pin open HOLD RDY Connect these pins to the Vcc pin via resistors These pins are pulled high Note 2 CNVss Connect this pin to the Vcc pin or Vss pin AVcc Connect this pin to the Vcc pin AVss VREF Connect these pins to the Vss pin Notes 1 When leaving these pins open after they are set to the output mode note the following these pins function as input ports from reset until they are switched to the output mode by software Therefore voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports Accordingly set these ports to the output mode immediately after reset Software reliability can be enhanced when the contents of the above ports direction registers are set periodically This is because these contents may be changed by noise a program runaway which occurs to noise etc 2 For unused pins use the shortest possible wiring wi
122. of the A D sweep pin select register must be performed while the A D converter halts before a trigger occurs Fig 12 8 1 Initial setting example for registers relevant to repeat sweep mode 7721 Group User s Manual 12 25 A D CONVERTER 12 8 Repeat sweep mode 12 8 2 Repeat sweep mode operation description 1 2 When an internal trigger is selected The operation for the input voltage from the ANo pin starts when the A D conversion start bit is set to 1 The A D conversion of the input voltage from the ANo pin is completed after 57 cycles of Then the contents of the successive approximation register conversion result are transferred to the A D register O For all of the selected analog input pins the A D conversion is performed The conversion result is transferred to the A D register i each time each pin is converted For all of the selected analog input pins the A D conversion is performed again The operation is performed repeatedly until the A D conversion start bit is cleared to 0 by software When an external trigger is selected The A D converter starts operation for the input voltage from the ANo pin when the input level to the ADtra pin changes from H to L while the A D conversion start bit is 1 The A D conversion of the input voltage from the ANo pin is completed after 57 cycles of ab Then the contents of the successive approximation register c
123. of the count source Fig 9 5 2 Initial setting example for registers relevant to pulse period pulse width measurement mode 7721 Group User s Manual 9 21 TIMER B 9 5 Pulse period Pulse width measurement mode 9 5 2 Count source In the pulse period pulse width measurement mode the count source select bits bits 6 and 7 at addresses 5B e and 5Cie select the count source Table 9 5 2 lists the count source frequency Table 9 5 2 Count source frequenc Count source Count Count source frequency select bits source z 56 Xs 25 MHz O 9 22 7721 Group User s Manual TIMER B 9 5 Pulse period Pulse width measurement mode 9 5 3 Operation in pulse period pulse width measurement mode When the count start bit is set to 1 the counter starts counting of the count source The counter value is transferred to the reload register when an valid edge of the measurement pulse is detected Refer to section 1 Pulse period Pulse width measurement The counter value is cleared to 0000 e after the transfer in and the counter continues counting The timer Bj interrupt request bit is set to 1 when the counter value is cleared to 0000 16 in Note The interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to O by software The timer repeats operations to above Note No timer Bj interrupt re
124. op code fetch cycles 1 If the next interrupt request b occurs before sampling pulse for the RTI instruction is gener ated the microcomputer executes the INTACK sequence for b without executing the main rou tine not even one instruction It is because that sampling is completed while executing the RTI instruction v Interrupt request b D Sampling pulse et E RTI instruction Interrupt routine a gt INTACK sequence for interrupt b If the next interrupt request b occurs immediately after sampling pulse is generated the microcomputer executes one instruction of the main routine before executing the INTACK sequence for b It is because that the interrupt request is sampled by the next sampling pulse Q wv Interrupt request b D Sampling puse JT LP LESS RTI instruction One instruction executed Interrupt routine a Main routine gt INTACK sequence for interrupt b 17 68 7721 Group User s Manual APPENDIX Appendix 9 7721 Group Q amp A Interrupt Suppose that there is a routine which should not accept one certain interrupt request The other interrupt request are acceptable Although when the interrupt priority level select bits for the above interrupt are set to 0002 in other words when this interrupt is set to be disabled this interrupt request is actually accepted immediately after change of the priority level Why did this occur and what s
125. p Qu d D D Q empty flag UARTI transmit register UARTi transmit buffer register TENDi topped because transmit enable bit O Start bit Stop bit Stop bit TxDi Transmit register empty flag UARTi transmit interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software The above timing diagram applies when T i Q ai te LI n the following conditions are satisfied TENDi Next transmit conditions are examined when this signal level is H Parity disabled TENDi is an internal signal Accordingly it cannot be read from the external 2 stop bits CTS function disabled Tc 16 n 1 fi or 16 n 1 fExT fi BRGi count source frequency f2 f16 fe4 f512 fExT BRGi count source frequency external clock n Value set in BRGi Fig 11 4 8 Example of transmit timing when transfer data length 9 bits when parity disabled selecting 2 stop bits not selecting CTS function 11 40 7721 Group User s Manual SERIAL I O 11 4 Clock asynchronous serial I O UART mode 11 4 5 Method of reception Figure 11 4 9 shows an initial setting example for relevant registers when receiving Reception is started when all of the following conditions and OQ are satisfied Reception is enabled receive enable bit 1 The start bit is detected By connecting the RTSi pin receiver side and CTSi pin transmitter side the timing of transmission
126. read signals for I Os when the M37721 outputs write signals Figure 13 4 5 shows an example of the circuit generating a write signal and a read signal for I Os M37721 Generating circuit for read and write signals to I Os DMA acknowledge DMAREQi DMA request Fig 13 4 5 Example of circuit generating write signal and read signal for I Os 7721 Group User s Manual 13 39 DMA CONTROLLER 13 4 Operation 1 Register operation in 1 bus cycle transfer Figure 13 4 6 shows a basic operation of registers for 1 unit transfer in 1 bus cycle transfer For register values to be specified refer to section 13 5 Single transfer mode through section 13 8 Link array chain transfer mode It is because these values vary depending on each continuous transfer mode In 1 bus cycle transfer a read and write of 1 transfer unit data are simultaneously performed during 1 bus cycle e When transferring from memory to I O DMAC Memory Transfer source address is specified by SARI Note Contents of TCRi are updated by decrementer Transfer Note when value read from TCRi is 0 transfer source of 1 data block is terminated Contents of SARi are updated by incrementer decrementer I O is specified by DMAACKi Data is output from memory and is written to I O I O simultaneously R W H level Transfer destination SARI SARi latch Incrementer Decrementer DARI DARi latch TOR TC
127. reading Software DMAG request bit DMAO enable bit 0 Disabled 1 Enabled DMA1 enable bit EB DMA2 enable bit DMA3 enable bit Note When any of bits 4 to 7 is set to 1 use the CLB or SEB instruction for writing to this register 7721 Group User s Manual 17 31 APPENDIX Appendix 3 Control registers Interrupt control register b7 b6 b5 b4 b3 b2 bi bO DMAO to DMA3 A D conversion UARTO and 1 transmit UARTO and 1 receive timers AO to A4 timers BO to B2 interrupt control registers Addresses 6C 6 to 7C16 3 Interrupt priority level select bits Level 0 Interrupt disabled Level 1 ew Level 2 Mp rm Level 3 RW Level 4 l Level 5 is Level 6 Level 7 po 52 3 Interrupt request bit 0 No interrupt requested 1 Interrupt requested SEDLEEEZELLLLLLLLLEEEELLLLL Nothing is assigned b7 b6 b5 b4 b3 b2 bl b0 INTo to INT2 interrupt control registers Addresses 7D16 to 7F 6 Cm me Crea Tee au Pu corms j Level 0 Interrupt disabled pere 0 1 Level 1 Level 2 Level 3 RW Level 4 Level 5 Level 6 ELLE EMEN Interrupt requested Polarity select bit Interrupt request bit is set to 1 at H level when level sense is selected this bit is set to 1 at falling edge when edge sense is selected Interrupt request bit is set to 1 at L level when level sense is selected this bit is set to 1 at rising
128. register 0 1 TAjin pin functions as a prog rammable I O port Falling edge of TAjin pin s input signal Rising edge of TAjin pin s input signal b7 b6 00 fe 01 fie beets nccmeeteeeeeteeeoees 1 0 fea 1 fs12 615 b8 b7 bO b7 bO Timer A3 register Addresses 4D16 4C16 Timer A4 register Addresses 4F16 4E16 15 to 0 These bits can be set to 000116 to FFFF e Undefined WO Assuming that the set value n the H level width of the one shot pulse output from the TAjour pin is expressed as follows n fi fi Frequency of count source fe He fea or f512 Note Use the LDM or STA instruction for writing to this register Head from or write to this register in a unit of 16 bits Fig 8 5 1 Structures of timer Aj mode register and timer Aj register in one shot pulse mode 8 30 7721 Group User s Manual TIMER A 8 5 One shot pulse mode 8 5 1 Setting for one shot pulse mode Figures 8 5 2 and 8 5 3 show an initial setting example for registers relevant to the one shot pulse mode Note that when using interrupts set up to enable the interrupts For details refer to INTERRUPTS Selecting one shot pulse mode and each function b Selection of one shot pulse mode Trigger select bits b4 b3 7 bO To alilo Timer Aj mode register j 2 to 4 Addresses 58 6 to 5A 6 CHAPTER 7 A Writing 1 to one shot start bit Internal trigger 1
129. register 0 Addresses 1FCAte to 1FC816 Transfer counter register 1 Addresses 1FDAte to 1FD8 6 Transfer counter register 2 Addresses 1FEAte to 1FE816 Transfer counter register 3 Addresses 1FFA16 to 1FF816 Write Set the dummy data iei RU These bits can be set to 00000116 to FFFFFFt e Read After a value is written to this register and until transfer starts the read value indicates the written value dummy data After transfer starts the read value indicates the remaining byte number of the block which is being transferred Note When writing to this register write to all 24 bits Do not write 00000016 to this register 7721 Group User s Manual 17 37 APPENDIX Appendix 3 Control registers DMAi mode register L DMAO mode register L Address 1FCCte b7 b6 b5 b4 b3 b2 bi bO ister L NENRDRER E 73 77 DMAS mode register L Address 1FFCte Number of unit transfer bits 0 16 bits RW select bit Note 1 8 bits 1 Transfer method select bit 0 2 bus cycle transfer RW 1 1 bus cycle transfer 2 Transfer mode select bit 0 Burst transfer mode RW 1 Cycle steal transfer mode r 9 nw Fic this bito 0 Transfer source address b5b4 direction select bits 0 0 Fixed 0 1 Forward 1 0 Backward 1 1 Do not select Transfer destination address b7b6 I I I 00 Fixed direction select bits 0 1 Ear 1 0 Backward 1 1 Do not select Note When the external data bus ha
130. requests cannot be accepted until the transfer of an entire batch of data is complete or the transfer is forced into termination 13 50 7721 Group User s Manual DMA CONTROLLER 13 4 Operation 13 4 4 Cycle steal transfer mode When the transfer mode select bit 1 and the edge sense level sense select bit 0 this mode is selected Refer to Figures 13 2 6 and 13 2 8 In this mode all of the DMA request sources are available Figure 13 4 11 shows a transfer example in the cycle steal transfer mode 1 transfer unit data is transferred for each DMA request The BUS REQUEST signal is sampled basically at every completion of 1 unit transfer Refer to Table 13 2 3 When a DRAM refresh request or Hold request is generated at this time the right to use bus is not returned to the CPU and the request is accepted When several DMA requests are generated the request of the channel which has the highest priority among them is accepted and DMA transfer is performed without returning the right to use bus to the CPU When any request is not generated the CPU gains the right DMAREQO DMAO request bit DMAO enable bit DMAREQ f DMA1 request bit DMA1 enable bit DRAM refresh request m o amp J j Right to use bus CPU DMA1 IDMAO0 CPU DMA 1 DMA1 DMAO BRAM DMA1 cPU This example applies on the following conditions e Both of DMAO and DMA 1 request sources are external sources Channel priority leve
131. reset When writing 1 to the software reset bit this pin outputs L XIN Clock input Input These are I O pins of the internal clock generating circuit Connect a ceramic resonator or quartz crystal an Clock output Output oscillator between pins Xin and Xout en using an external clock the clock source should be input to Xin pin and Xour pin should be left open E Enable output Output Data instruction code read or data write is performed when output from this pin is L level BYTE Exernal data bus width Input Input level to this pin determines whether the external selection input data bus has a 16 bit width or an 8 bit width The width is 16 bits when the level is L and 8 bits when the level is H STO Status signal output Output The bus use state is output in 2 bit code ST 0 0 DRAM refresh oji 1 a AVcc Analog supply input The power supply pin for the A D converter Connect AVss AVcc to Vcc pin Connect AVss to Vss pin VREF Reference voltage input Input This is a reference voltage input pin for the A D converter 7721 Group User s Manual DESCRIPTION 1 3 Pin description Table 1 3 2 Pin description 2 Pin Ao MAo A7 MAz As Ds Ais Di5 A16e Do Aes D HOLD RDY 1 Name Address low order DRAM address Address middle order data high order Address high order data low order Memory control signal output Input Output Functions Low or
132. synchronizes with a clock generated by the oscillation circuit If noise enters clock I O pins clock waveforms may be deformed This may cause a malfunction or a program runaway M37721 M37721 Also if the noise causes a potential difference between the Vss level of the microcomputer and the Vss level of an oscillator the correct clock will not be input in the microcomputer XIN XOUT Vss Not acceptable Acceptable Fig 4 Wiring for clock input output pins 7721 Group User s Manual 17 59 APPENDIX Appendix 8 Countermeasure against noise 3 Wiring for CNVss pin Connect CNVss pin to the Vss pin with the shortest possible wiring Reason The processor mode of the microcomputer is influenced by a potential at the CNVss pin when the CNVss pin and the Vcc or Vss M37721 Noise M37721 pin are connected If the noise causes a potential difference between the CNVss pin CNVss and the Vss or Vcc pin the X processor mode may become Vss unstable This may cause a microcomputer malfunction or a pred Not Acceptable Acceptable When connecting the C NVssand Vcc pins connect them in the shortest possible distance also Fig 5 Wiring for CNVss pin 2 Connection of bypass capacitor between Vss and Vcc lines Connect an approximate 0 1 uF bypass capacitor as follows Connect a bypass capacitor between the Vss and Vcc pins at equal lengths The wiring connecting the bypass capacitor between the Vss and Vcc pins sh
133. that of reception can be matched Figure 11 4 11 shows an connection example The receive operation is described below The input signal of the RxDi pin is taken into the most significant bit of the UARTi receive register synchronously with the transfer clock s rising edge The contents of the UARTI receive register are shifted by 1 bit to the right Steps and are repeated at each rising edge of the transfer clock When one set of data has been prepared in other words when the shift has been performed several times according to the selected data format the UARTi receive register s contents are transferred to the UARTi receive buffer register Simultaneously with step the receive complete flag is set to 1 Additionally a UARTi receive interrupt request occurs and its interrupt request bit is set to 1 The receive complete flag is cleared to 0 when the low order byte of the UARTI receive buffer register is read out The RTSi pin s output level becomes L simultaneously with step when selecting the RTS function Figure 11 4 12 shows an example of receive timing when the transfer data length 8 bits Transmitter side Receiver side Fig 11 4 11 Connection example 11 44 7721 Group User s Manual BRGi count source SERIAL I O 11 4 Clock asynchronous serial I O UART mode UUL Receive enable bit RxDi Transfer clock Receive complete flag RTSi UARTI rece
134. the interrupt disable flag I to 0 Clear the level sense edge sense select bit to 0 Edge sense is selected Clear the interrupt request bit to 0 Set the interrupt priority level to one of levels 1 7 INTi interrupt request is acceptable or clear the interrupt disable flag I to 0 INTi interrupt request is acceptable y Note The above settings must be done separately Multiple settings must not be done at the same time in other words they must not be done only by 1 instruction Fig 7 10 5 Example of switching procedure for INTi interrupt request occurrence factor 7721 Group User s Manual 1 21 INTERRUPTS 7 11 Precautions for interrupts 7 11 Precautions for interrupts When changing the interrupt priority level select bits bits 0 to 2 at addresses 6Cie to 7F e 2 to 7 cycles of are required until the interrupt priority level is changed Therefore when the interrupt priority level of a certain interrupt source is repeatedly changed in a very short time which consists of a few instructions it is necessary to reserve the time required for the change by software Figure 7 11 1 shows a program example to reserve the time required for the change Note that the time required for the change depends on the contents of the interrupt priority detection time select bits bits 4 and 5 at address 5E e Table 7 11 1 lists the correspondence between the number of instructions inserted in Figure 7 11
135. the interrupt priority level detection time has passed after sampling starts an interrupt request is accepted The interrupt priority level detection time can be selected by software Figure 7 6 1 shows the interrupt priority level detection time Usually select 2 cycles of as the interrupt priority level detection time 1 Interrupt priority detection time select bits b7 b6 bd b4 b3 b2 bl LBLLLLLI Processor mode register 0 Address 5E16 L t Processor mode bits i Se Wait bit l Software reset bit l l l l l l l l l l l l l l Interrupt priority detection time select bits l l l 00 7 cycles of 0 a shown below l l l l l l l l l l l l l 4 cycles of b shown below 2 cycles of c shown below 11 Do not select peg s eS a Must be fixed to 0 L Clock 1 output select bit 2 Interrupt priority level detection time o gt lLUUU UU UU Lo Op code fetch cycle Sampling pulse Note 7cydes l emere tema a c 2cycles Co Note The pulse resides when 2 cycles of 6 is selected Fig 7 6 1 Interrupt priority level detection time 712 7721 Group User s Manual INTERRUPTS 7 7 Sequence from acceptance of interrupt request until execution of interrupt routine 7 7 Sequence from acceptance of interrupt request until execution of interrupt routine The sequence from the acceptance of interr
136. time 0 400 CE Timer A input Two phase pulse input in event counter mode MM Symbol Parameter MM MAX Unit te TA TAjw input cycle time 800 ns IsuTAi TAou TAjin input setup time 200 ns tsu TAjour Tajn TAjout input setup time 2e00 ns 7721 Group User s Manual 17 83 APPENDIX Appendix 11 Electrical characteristics Internal peripheral devices eCount input in event counter mode Gating input in timer mode External trigger input in one shot pulse mode External trigger input in pulse width modulation mode TAJN input Up down input and count input in event counter mode TAjour input Up down input TAjour input Up down input TAjiN input When counted at falling edge TAJN input When counted at rising edge AY th Tin UP tsu UP Tin lt gt lt DC OU Two phase pulse input in event counter mode TAJN input TAjour input Test conditions Vcc 5 V 1096 tc TA tsu TAjin TAjout tsu TAjin TAjout lt T tsu TAjout TAjin tsu TAjout TAjin Input timing voltage Vi 1 0 V ViH 4 0 V 17 84 7721 Group User s Manual APPENDIX Appendix 11 Electrical characteristics Timer B input Count input in event counter mode x terre TBjin input cycle time one edge count 80 ns tw TBL TBji input low level pulse width one edge count 40 ns ics 60 ns t
137. two phase pulse signal processing normal processing and quadruple processing In Timers A2 and A3 normal processing is performed in timer A4 quadruple processing is performed For some bits of the port P5 direction register correspond to pins used for two phase pulse input set these bits for the input mode b7 b6 b5 b4 b3 b2 bi b0 x xo 1 o o o 1 Timer a3 mode register Address 59 9 Timer A4 mode register Address 5Aie X It may be either 0 or 1 Fig 8 4 6 Timer Aj mode registers when two phase pulse signal processing function is selected e Normal processing Countup is performed at the rising edges input to the T Aki pin when the phase has the relationship that the TAkin pin s input signal level goes from L to H while the TAkour k 2 and 3 pin s input signal is at H level Countdown is performed at the falling edges input to the TAkin pin when the phase has the relationship that the TAkin pin s input signa level goes from H to L while the TAkour pin s input signal is at H level Refer to Figure 8 4 7 TAKkour x x TAkIN x x k 2 3 Counted Counted Counted Counted Counted Counted up up up down down down 1 1 1 1 _1 1 Fig 8 4 7 Normal processing 8 26 7721 Group User s Manual TIMER A 8 4 Event counter mode eQuadruple processing Countup is performed at all rising and falling edges input to the TA4ourt and TA4in pins
138. used and the contents of the high order 8 bits is unchanged In an addressing mode in which index register X is used as an index register the address obtained by adding the contents of this register to the operand s contents is accessed In the MVP or MVN instruction a block transfer instruction the contents of index register X indicate the low order 16 bits of the source address The third byte of the instruction is the high order 8 bits of the source address Note Refer to 7700 Family Software Manual for addressing modes 2 1 3 Index register Y Y Index register Y is a 16 bit register with the same function as index register X Just as in index register X the index register length flag x determines whether this register is used as a 16 bit register or as an 8 bit register In the MVP or MVN instruction a block transfer instruction the contents of index register Y indicate the low order 16 bits of the destination address The second byte of the instruction is the high order 8 bits of the destination address 7721 Group User s Manual 2 3 CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 2 1 4 Stack pointer S The stack pointer S is a 16 bit register It is used for a subroutine call or an interrupt It is also used when addressing modes using the stack are executed The contents of S indicate an address stack area for storing registers during subroutine calls and interrupts Stack area is selected by
139. w 01234 Note 1 FFFF16 lil 1000016 1000F1 Bank 116 Ez Direct page area when DPR FF10 e Note 2 6 The number of cycles required to generate an address is 1 cycle smaller when the low order 8 bits of the DPR are 00 e The direct page area spans the space across banks O16 and 116 when the DPR is FF01 e or more Fig 2 1 4 Setting example of direct page area 2 6 7721 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 2 1 9 Processor status register PS The processor status register is an 11 bit register Figure 2 1 5 shows the structure of the processor status register b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 bd b4 b3 b2 bi ololololo e In vel e i 2 e tees register PS Note Bits 11 15 is always 0 at reading Fig 2 1 5 Processor status register structure 1 Bit 0 Carry flag C It retains a carry or a borrow generated in the arithmetic and logic unit ALU during an arithmetic operation This flag is also affected by shift and rotate instructions When the BCC or BCS instruction is executed this flag s contents determine whether the program causes a branch or not Use the SEC or SEP instruction to set this flag to 1 and use the CLC or CLP instruction to clear it to O 2 Bit 1 Zero flag Z It is set to 1 when a result of an arithmetic operation or data transfer is 0 and cleared to 0 when otherwise When the BNE or BEQ
140. when all Notes 3 5 the contents of the specified bit is 0 BBS Mb 1 Tests the specified bit of the memory Branches when all Notes 3 5 the contents of the specified bit is 1 C 0 BCC Branches when the contents of the C flag is 0 Note 3 BCS C21 Branches when the contents of the C flag is 1 Note 3 Z 1 Branches when the contents of the Z flag is 1 N 1 Branches when the contents of the N flag is 1 BNE Z 0 Branches when the contents of the Z flag is 0 Note 3 BPL N 0 Branches when the contents of the N flag is O Note 3 BRA PC lt PC offset Jumps to the address indicated by the program counter Note 4 PGc PG 1 plus the offset value when carry occurs PGc PG 1 when borrow occurs BRK PC lt PC 2 Executes software interruption M S PG Sc S 1 M S lt PCH Sc S 1 M S e PC Sc S 1 M S lt PSH Sc S 1 M S PSL Sc S 1 1 PCL ADL PCH ADun PG lt 0016 BVC V 0 Branches when the contents of the V flag is 0 Note 3 BVS Vel Branches when the contents of the V flag is 1 Note 3 Mb lt 0 Makes the contents of the specified bit in the memory 0 Note 5 Makes the contents of the C flag 0 Makes the contents of the flag 0 58 2 Makes the contents of the m flag 0 CLP PSb lt 0 Specifies the bit position in the processor status register by the bit pattern of the second byte in the instruction and sets
141. when the phase has the relationship that the TA4in pin s input signal level goes from L to H while the TA4out pin s input signal is at H level Countdown is performed at all rising and falling edges input to the TA4our and TA4in pins when the phase has the relationship that the TA4in pin s input signal level goes from H to L while the TA4ovur pin s input signal is at H level Refer to Figure 8 4 8 Table 8 4 3 lists the relationship between the input signals to the TA4our and TA4m pins and count operation when the quadruple processing is selected TA4out Counted up at all edges Counted down at all edges 1 1 1 1 l Counted up at all edges 1 1 1 1 41 Fig 8 4 8 Quadruple processing Table 8 4 3 Relationship between input signals to TA4our and TA4w pins and count operation when quadruple processing is selected RN Input signal to TA40uT pin Input signal to TA4IN pin Up count H level Rising edge L level Falling edge L level H level Down count Falling edge Rising edge H level Falling edge L level 7721 Group User s Manual 8 27 TIMER A 8 4 Event counter mode Precautions for event counter mode 1 While counting is in progress by reading the timer Aj register the counter value can be read out at any timing However if the timer Aj register is read at the reload timing shown in Figure 8 4 9 the value FFFF e
142. writing data to DRAM td E CASL DRAM write signal W A rede Row address Column address Address output and Data I O A8 D8 A15 D15 Address A16 Do A23 D7 This applies when the external data bus has a width of 16 bits BYTE L th E DLQ DHQ Specifications of the M37721 The others are specifications of DRAM Fig 16 1 7 Timing for writing data to DRAM Data hold time ton twet tae casL th E DLQ DHQ Table 16 1 5 lists the calculation formula and value for each parameter in Figure 16 1 7 Figure 16 1 8 shows the relationship between ton and f Xin 16 10 7721 Group User s Manual APPLICATION 16 1 Memory connection Table 16 1 5 Calculation formula and value for each parameter in Figure 16 1 7 unit ns Ha Calculation formula and Value lw EL 4 X 10 f Xin es td E CASL 80 to 115 td E DLQ 35 td E DHQ th E DLQ 1 X 10 th E DHQ Xin 22 Note When accessing DRAM Wait is always inserted regardless of the contents of the Wait bit source s Wait bit and destination s Wait bit I OQ O E D O C 2 G e 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 295 MHz External clock input frequency f XIN Fig 16 1 8 Relationship between ton and f Xw 7721 Group User s Manual 16 11 APPLICATION 16 1 Memory connection 3
143. 0 Falling edge of TAjin pin s input signal External trigger 1 1 Rising edge of TAjin pin s input signal External trigger Count source select bits b7 b6 00 f2 0 1 f16 1 0 fe4 1 1 f512 ia a Setting H level width of one shot pulse b15 b8 b7 bO b7 bO M Timer A4 register Addresses 4Ft1e 4E16 EK Can be set to 000116 to FFFF e x Timer A2 register Addresses 4Bie 4A16 Timer A3 register Addresses 4D16 4C 6 n A Note H level width fi Frequency of count source Setting interrupt priority level b7 bO m Timer Aj interrupt control register j 2 to 4 Addresses 7716 to 7916 Interrupt priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 A Continue to Figure 8 5 3 Fig 8 5 2 Initial setting example for registers relevant to one shot pulse mode 1 7721 Group User s Manual 8 31 TIMER A 8 5 One shot pulse mode When external trigger is selected From preceding Figure 8 5 2 qm port P5 direction register S b7 bO Port P5 direction register Address Die TA2IN pin TASIN pin TA4IN pin Set the corresponding bit to 0 E a 7 b7 etting count start bit to 1 bO Count start register Address 4016 Timer A2 count start bit T
144. 0 max tRAC 70 max AigDO As3 DT 0M Ademen Vooseruccosecusbisebsticzensmsrldseszscag tCLZ 5 min at AC157 tPHL td BLE BHE E 20 min tCAC 20 max r gt AC157 tPHL BLE BHE I lt When writing gt gt tsu DL DH E gt 30 oEZ 0 20 tw EL 135 min E tw RASH 60 min tw RASL 120 min ND lt tw CASL 55 min gt CAS J lt td E CASL 80 115 A ag AINE 20 min gt R W HL gt lt AC32 tPHL AC32 tPHL twcs 0 min tWCH 15 min gt lt W td RA RAS 5 min th RAS RA 18 min gt x MAo MAs Row Address i Column address lt gt A td CA CAS 10 min th CAS CA 60 min A16 D0 A23 D7 V i tDH 15 mi x td BLE BHE E 20 min 15 min lt AC157 tPHL th E DLQ DHQ 18 min Specifications of M5M44260CJ 7 The others are specification of M37721 Unit ns Fig 16 1 35 Timing chart for example of M5M44260CJ 256K X 16 bits connection external bus width 16 bits 7721 Group User s Manual 16 39 APPLICATION 16 1 Memory connection 16 1 4 Example of I O expansion 1 16 40 Example of port expansion circuit using M66010FP Figure 16 1 36 shows an example of a port expansion circuit using the M66010FP Make sure that the frequency of Serial I O transfer clock must be 1
145. 00 0 Addresses 8000001e FFFFFF 16 8 Mbytes 100 1 Addresses 7000001e FFFFFF 16 9 Mbytes 1 0 1 0 Addresses 6000001e FFFFFF 6 10 Mbytes 101 1 Addresses 5000001e FFFFFF 6 11 Mbytes 1 1 0 0 Addresses 40000016e FFFFFF 6 12 Mbytes 1 10 1 Addresses 3000001e FFFFFF 6 13 Mbytes 1 1 1 0 Addresses 2000001e FFFFFF 6 14 Mbytes 111 1 Addresses 10000016 FFFFFF 16 15 Mbytes DRAM is valid BEEN P104 P107 pins function as CAS RAS MAs and MAe Ao A 7 function as MAo MA7 when accessing the DRAM area Refresh timer starts counting During DRAM area access CAS RAS and MAo MAg are output Each time an underflow of the refresh timer occurs CAS and RAS for refresh are output During refresh STO and ST1 output L level Fig 14 3 1 Initial setting example for registers relevant to DRAMC 7721 Group User s Manual 14 7 DRAM CONTROLLER 14 4 DRAMC operation 14 4 DRAMC operation 14 4 1 Waveform example of DRAM control signals Figure 14 4 1 shows a waveform example of the DRAM control signals When DRAM is accessed the bus cycle is always with wait the low level width of E is equivalent to 2 cycles of It is not affected by the wait bit the wait bit of the transfer source and the wait bit of the transfer destination 1 2 3 14 8 Read Cycle In the read cycle the CAS signal falls with a delay of 0 5 cycle of after the RAS signal has changed from H
146. 000043168 S O 00004416 00004516 S 00004616 Timer AO register 00004716 00004816 Timer A1 register 00004916 00004A16 Timer A2 register 00004B16 Y00045 00004E16 Timer A4 register 00004F16 00005016 Timer B0 register 00005116 ot goos 00005616 00005716 00005816 00005916 00005A16 00005B16 00005C16 00005D16 00005E16 00005F16 00006016 00006116 00006216 Real time output control register 00000816 00006416 00006516 00006616 00006716 00006816 DMAC control register L DMAC controlregisterL O 00006916 00006A16 E DMAO interrupt control register A D conversion interrupt control register 00006B16 00006C16 DMAO interrupt control register 00006D16 00006E 6 00006F16 00007016 A D conversion interrupt control register 00007116 00007216 00007316 00007416 00007516 00007616 00007716 00007816 00007916 00007A16 00007B16 00007C16 00007D16 00007E16 00007F 16 7721 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 4 Memory assignment Address 001FC11i6 Source address register 0 M 001FC216 H OMFC346 rr 001FC416 L 001FC516 Destination address register 0 M 001FC616 H 001FC718 001FC816 L 001FC916 Transfer counter register 0 M 001FCA16 H 001FCB168 001FCCt16 001FCD16 001FCE16 OO1FCFie j L 001FD016 001FD116 Source address register 1 M 001FD216 H UPON 001FD416 L 001FD516 Destination address register 1 M 001FD616
147. 0CJ 7 1 Make sure that the propagation delay time is within 40 ns Make sure that the propagation delay time is within 15 ns Memory map 00000016 SFR area 00008016 Internal 00047Fie RAM area Not used 001FCO016 ooiFFF SFR area A18 D2 A19 D3 A20 D4 A21 D5 A22 De A23 D7 Not used M5M417800CJ A10 D10 A11 D11 A12 D12 A13 D13 A14 D14 A15 D15 XOUT Circuit condition DRAM area select bits bits 3 to 0 at address 6416 00102 Fig 16 1 30 Example of M5M417800CJ 2M X 8 bits connection external bus width z 16 bits 16 34 7721 Group User s Manual lt When reading gt E OE RAS tw RASH 60 min td E RASL 30 max 9 gt CAS td E CASL 77 5 Max td RA RAS 5 min MAo MAg APPLICATION 16 1 Memory connection tw EL 135 min tw RASL 120 min td RAS CAS 28 min gt Row address Column address tw CASL 92 5 min td CA CAS 5 min td E CA 60 max A16 D0 A23 D7 7 lt gt td AH E 15 min A10 M5M417800AJ When writing tOEA 20 max tAA 35 max tRAC 70 max Y Y Y tCLZ 5 min tCAC 20 max tsu DL DH E 2 30 Input data s l tpzx E DLZ DHZ 20 min tOEZ 0 15
148. 1 Data bus Ds D15 Transfer source wait bit Valid in DMA transfer 0 Wait 1 No wait Transfer destination wait bit Valid in DMA transfer 0 Wait 1 No wait Selection of array chain transfer mode i Continue to Figure 13 7 5 on next page ju X b16 b b epp GB b0b7 bO b23 b7 V T b16 b15 b8 b0b7 b0b7 T b0 Ns Z i Transfer counter register 3 Source address register 0 Source address register 1 Source address register 2 Source address register 3 Addresses 1FC216 to 1FCO 6 Addresses 1FD216 to 1FD0O 6 Addresses 1FE216 to 1FE016 Addresses 1FF21e to 1FF016 SARO SAR1 SAR2 SAR3 _ Set the start address of transfer parameter memory These bits can be set to 00000016 to FFFFFF te Transfer counter register 0 Transfer counter register 1 Transfer counter register 2 Addresses 1FCAte to 1FC816 TCRO Addresses 1FDAte to 1FD816 TCR1 Addresses 1FEA e to 1FE816 TCR2 Addresses 1FFA e to 1FF816 TCR3 Set the number of transfer blocks These bits can be set to 00000116 to FFFFFF te Notes 1 When writing to these registers 2 Do not write 00000016 to TCRi Fig 13 7 4 Initial setting write to all 24 bits ee Note When an external source DMAREQ is selected or when the cycle steal transfer mode is select
149. 1 Group User s Manual connection eere nennen nnn 16 1 2 How to calculate timina Appendix 3 Control registers Appendix 4 Package outlinel L Appendix 8 Countermeasure against noisel Appendix 11 Electrical characteristics Vii Table of contents MEMORANDUM viii 7721 Group User s Manual CHAPTER 1 DESCRIPTION 1 1 Performance overview 1 2 Pin configuration 1 3 Pin description 1 4 Block diagram DESCRIPTION 1 1 Performance overview 1 1 Performance overview Table 1 1 1 lists the performance overview of the M37721 Table 1 1 1 M37721 performance overview Parameters Number of basic instructions Instruction execution time External clock input frequency f Xin Memory sizes ROM Functions 103 160 ns the minimum instruction at f Xw 25 MHz 25 MHz maximum External M37721S2BFP 1024 bytes PAN M37721S1BFP 512 bytes Programmable Input Output P5 P10 8 bits X 6 ports P4 5 bits X 1 Multifunctional timers TAO TAA4 16 bits X 5 TBO TB2 16 bits X 3 Serial I O UARTO UART1 A D converter Watchdog timer DMA controller DRAM controller Real time output Interrupts Clock generating circuit Supply voltage Power dissipation Port Input Output characteristics Memory expansion Operating temp
150. 1 Interrupt disable flag I All maskable interrupts can be disabled by this flag When this flag is set to 1 all maskable interrupts are disabled when this flag is cleared to 0 those interrupts are enabled Because this flag is set to 1 at reset clear this flag to O when enabling interrupts 7 3 2 Interrupt request bit When an interrupt request occurs this bit is set to 1 This bit remains set to 1 until the interrupt request is accepted it is cleared to O when the interrupt request is accepted This bit can also be set to O or 1 by software The INT interrupt request bit i 0 to 2 is ignored when the INTi interrupt is used with level sense 7 3 3 Interrupt priority level select bits and processor interrupt priority level IPL The interrupt priority level select bits are used to determine the priority level of each interrupt When an interrupt request occurs its interrupt priority level is compared with the processor interrupt priority level IPL The requested interrupt is enabled only when the comparison result meets the following condition Accordingly an interrupt can be disabled by setting its interrupt priority level to O Each interrupt priority level Processor interrupt priority level IPL Table 7 3 1 lists the setting of interrupt priority level and Table 7 3 2 lists the interrupt enabled level corresponding to IPL contents The interrupt disable flag l interr
151. 1 and the interrupt priority detection time select bits LDM B 0XH 00XXH Write instruction for the interrupt priority level select bits NOP Inserted NOP instruction Note NOP NOP LDM B 0XH OOXXH Write instruction for the interrupt priority level select bits Note Except the write instruction for address XXt6 any instruction which has the same cycles as the NOP instruction can also be inserted For the number of inserted NOP instructions refer to Table 7 11 1 XX any of 6C to 7F Fig 7 11 1 Program example to reserve time required for change of interrupt priority level Table 7 11 1 Correspondence between number of instructions to be inserted in Figure 7 11 1 and interrupt priority detection time select bits Interrupt priority detection time select bits Note Interrupt priority level Number of inserted b5 detection time NOP instructions 0 moZ 7cydesof 4 or more 0 2 or more I N 0 cycles of or more 1 Do not select Note We recommend b5 1 b4 0 7 22 7721 Group User s Manual CHAPTER TIMER A 8 1 Overview 8 2 Block description 8 3 Timer mode Precautions for timer mode 8 4 Event counter mode Precautions for event counter mode 8 5 One shot pulse mode Precautions for one shot pulse mode 8 6 Pulse width modulation PWM mode Precautions for pulse width modulation PWM mode TIMER A 8 1 Overview 8 1 Overview Timer A consists of fiv
152. 1 block e In 2 bus cycle transfer Read cycle Write cycle x the number of transfers 3 1 Add a value which satisfies the read write conditions Refer to Table 13 4 1 3 2 When the transfer unit is 16 bits the number of transfers the number of transfer bytes 2 When the transfer unit is 8 bits the number of transfers the number of transfer bytes e In 1 bus cycle transfer Refer to Table 13 4 5 Terminate processing 3 cycles DMA transfer of the block at the TC input above The number of transfers is assumed to be up to the DMA transfer of 1 unit transfer which was in progress at the TC input Transition of the right to use bus from DMAC to CPU 1 cycle Example External data bus width 16 bits 2 bus cycle transfer transfer unit 216 bits the number of the transfer bytes 10 bytes and under the following conditions Transfer source address direction forward start address of data even with Wait Transfer destination address direction backward start address of data even without Wait e TC is input when the m th byte m even of the n th block is in transfer n 1 9 0 1 n 1 5 3 4 3 m 2 1 38n m 2 36 cycles 13 102 7721 Group User s Manual DMA CONTROLLER 13 9 DMA transfer time 3 Array chain transfer mode and Link array chain transfer mode Right to use bus Transition Array state Transfer O O a2 1 block Fig 13 9 6 Ar
153. 10 3 INTi Interrupt request When the INTi pin s level changes to the invalid level before an interrupt request is accepted the interrupt Interrupt request is accepted request is not retained Return to main routine Valid x INTi pin level Invalid bs Main routine Main routine First interrupt routine Second interrupt Third interrupt routine routine Fig 7 10 4 Occurrence of INT interrupt request when level sense is selected 7 20 7721 Group User s Manual INTERRUPTS 7 10 External interrupts INTi interrupt 7 10 2 Switching of INTi interrupt request occurrence factor When the INTi interrupt request occurrence factor is switched in one of the following ways the interrupt request bit may be set to 1 Switching the level sense to the edge sense Switching polarity Therefore after this switching make sure to clear the interrupt request bit to O Figure 7 10 5 shows an example of the switching procedure for the INTi interrupt request occurrence factor 1 Switching level sense to edge sense 2 Switching polarity Set the interrupt priority level to level 0 Set the interrupt priority level to level 0 or set the interrupt disable flag l to 1 or set the interrupt disable flag I to 1 INTi interrupt is disabled INTi interrupt is disabled Set the polarity select bit Clear the interrupt request bit to 0 Set the interrupt priority level to one of levels 1 7 or clear
154. 116 UARTO baud rate register 3216 UARTO transmit buffer register 5 3316 3416 UARTO transmit receive control register 0 3516 UARTO transmit receive control register 1 3616 UARTO receive buffer register 3716 3816 UART1 transmit receive mode register 3916 UART1 baud rate register 3A16 UART1 transmit buffer register 3B16 3C16 UART1 transmit receive control register 0 3D16 UART1 transmit receive control register 1 3E16 3F16 UART1 receive buffer register Fig 4 1 5 State of SFR and internal RAM areas immediately after reset 2 4 6 7721 Group User s Manual RESET 4 1 Hardware reset Address 4016 4116 4216 4316 4416 4516 4616 4716 4816 4916 4A16 4B16 4C16 4D16 4E16 4F16 5016 5116 5216 5316 5416 5516 5616 5716 5816 5916 5A16 5B16 5C16 5D16 Register name Access characteristics immediately after inum b7 Count start register w s One shot start register lololo RSS ae Up down register 0 0 0 0 0 0 RSs Timer AO register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer BO register Timer B1 register Timer B2 register Timer AO mode register 0 10 RRR MAVAWN Timer A1 mode register 0 o SORORIS Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer BO mode register RW Jes RW 010 1 0 0 0 O Timer B1 mode register RW pe RW 0 0 0 0 0O 0 Timer B2 mode register RW me
155. 12 V RTP13 J a Setting port P6 direction register Sx b7 b0 Port P6 direction register Address 1016 RTP0o Set the bits corresponding to the RTPO1 selected pulse output pins to 1 RTPO2 RTPOs RTP1o RTP1 RTP12 RTP1s Ne 4 Setting pulse output mode UN b7 bO ee e Real time output control register Address 6216 P6o P67 pins functions as the programmable I O port Pulse output mode select bit 0 Pulse mode 0 1 Pulse mode 1 M A When pulse mode 0 is selected POSS RRR CCP eee When pulse mode 1 is selected f Setting output data N f Setting output data N b0 b7 b7 b0 Pulse output data register 0 x x Pulse output data register 0 Address 1A16 xix p Address 1 RTPOo RTPOo 0 L level RTPO RTPO dis 1 H level RTPO02 0 L level 1 RTPOs ewe X It may be either 0 or 1 b7 b0 Pulse output data register 1 Pulse output data register 1 Address 1C 6 Address 1C 6 RTP02 RTP1o RTPOs RTP11 ae RTP1o 0 L level RTP1 gt ria RTP1 1 H level RTP1s PES RTP12 RTP1s X It may be either 0 or 1 E Ke wv Continue to Figure 10 3 2 Fig 10 3 1 Initial setting example for registers relevant to real time output 1 7721 Group User s Manual 10 7 REAL TIME OUTPUT
156. 13 2 Performance ove O 2 ed nets EEO 13 2 3 1 2 Bus use priority TOVCISN ccc teascecsveesaccanaspoimscesadveesceateeenciatiaaadeareiaateecebeaniwentensaccdestriennad 13 3 us wd 7 A 13 3 EE 13 6 13 2 1 Bus access control circuitl mmm 13 7 13 2 2 DMR aentrol register Ll nnn 13 10 13 2 3 DMA Control register H eeeeeeerrrennnnnnm mmn 13 11 13 2 4 Source address register i SARI 13 12 13 2 5 Destination address register i DARIi I 13 12 13 2 6 Transfer counter register i TCR 13 12 E 13 13 13 2 8 BI Tel IRAN ENCRNET m 13 13 T 13 13 13 2 10 DMAi mode register L1 sssciroeuueuco toda a Exe PROxuT Rete nexu ruber bnt uy au Fbd rk usPS ntt ar Rvr rax EER 13 14 13 211 DMAI mode register Fi e u uu uu d luce toes teme piens 13 15 13 2 12 DNIAL control Tm 13 16 7721 Group User s Manual V Table of contents een it ere li nee YX 13 19 13 19 3 562 DMA OU OG mec 13 20 hannel prio aen mee T 13 21 13
157. 13 7 Array chain transfer mode Precautions for array chain transfer mode If the following two conditions are satisfied when the transfer unit is 16 bits and the address direction of transfer source or destination is fixed the array chain transfer mode can be used The external data bus width 16 bits or the internal memory is used e The transfer start address on the address direction fixed side is an even address 7721 Group User s Manual 13 79 DMA CONTROLLER 13 8 Link array chain transfer mode 13 8 Link array chain transfer mode This mode is used to transfer several blocks of data According to the information of each block stored in memory area Note several blocks of data are transferred Transfer parameters can be located in separate memory locations in a unit of one block s parameters Table 13 8 1 lists the specifications of the link array chain transfer mode and Figure 13 8 1 shows the register structures of SARi DARi and TCRi in this mode Note Each of the following information is called transfer parameter transfer start addresses of transfer source and destination and transfer datas byte number Table 13 8 1 Specifications of link array chain transfer mode ltem Transfer parameter memory Condition of normal termination Conditions of forced termination Interrupt request generation timing Functions of registers Performance specifications Required In 2 bus cycle transfer 16 bytes per
158. 16 DM A2 interrupt control register 6F16 DM AS interrupt control register 7016 A D conversion interrupt control register 7116 UARTO transmit interrupt control register 7216 UARTO receive interrupt control register W 7316 UART1 transmit interrupt control register 7416 UARTI receive interrupt control register pf RW pf RW Lp RW Lp RW EN nH G RWA 7 EN 407 ENERO Lp rw O aoe RW LE RW ee Fw _ RW o Pw L Pw _ L RW _ RW 7516 Timer A0 interrupt control register 7616 Timer A1 interrupt control register 7716 Timer A2 interrupt control register 7816 Timer A3 interrupt control register 7916 Timer A4 interrupt control register 7A16 Timer BO interrupt control register 7TB16 Timer B1 interrupt control register EID 7C16 Timer B2 interrupt control register H 010 00 7D16 INTo interrupt control register Rw 2 0 0 0 0 01 0 TE16 INT interrupt control register 2 0 0 0 0 0 0 7F16 INT2 interrupt contro register 2 0 0 0 0 0 0 Notes 5 By writing dummy data to address 6016 the value FFF 16 is set to the watchdog timer The dummy data is not retained anywhere 6 The value FFF 16 is set to the watchdog timer Refer to CHAPTER 15 WATCHDOG TIMER T It is possible to read the bit state at reading When writing 0 to this bit this bit becomes 0 But when writing 1 to this bit this bit does not change Fig 4 1 7 State of SFR
159. 2 8 1 shows an initial setting example for registers relevant to the repeat sweep mode 12 24 7721 Group User s Manual A D CONVERTER 12 8 Repeat sweep mode A D control register and A D sweep pin select register b7 bO 0 jt tjxixix A D control register address 1E 6 A D sweep pin select register address 1F 6 b7 bO AAL A D sweep pin select bits b1 bO 0 0 ANo AN 2 pins Repeat sweep mode Trigger select bit 0 1 ANo ANs 4 pins 0 Internal trigger 1 0 ANo ANSs 6 pins 1 External trigger 1 1 ANoc AN 8 pins A D conversion start bit 0 Stop A D conversion A D conversion frequency AD select bit 0 f2 divided by 4 1 f2 divided by 2 x 0 or 1 4 Port P7 direction register N b7 b0 Port P7 direction register address 1116 ANo AN AN2 Set the bits corresponding AN3 to analog input pins to 0 AN4 Set bit 7 to 0 when ANs selecting external trigger ANe C AN7 J amp Z Set A D conversion start bit to 1 b7 b0 1 th _4 A D control register address 1E 6 A D conversion start bit M d When external trigger is selected Vv Input falling edge to ADrnc pin When internal trigger is selected A Trigger occur Operation start Note Writing to each bit except bit 6 of the A D control register and each bit
160. 23 E 13 25 13 3 6 DMA transfer restart after terminationl 13 28 Precautions for 2 bus cycle transfer 3 4 2 1 bus cvcle transfer Precautions for 1 bus cycle transfer 13 7 1 Transfer parameter memory in array chain transfer model 14 2 Block descriptiony ec U U nennen nennen nnn hh nena u 14 2 1 DRAM control regisStIer u t eet u u odes kem ER NES eu iR as UE Teo tei ran tuse pue end RS ES 14 3 14 2 2 Refresh IRR IAS RNC Oe m 14 5 14 2 3 Address comparatorl a a a 14 6 14 2 4 RAS and CAS generating circuill 14 6 THEE 14 6 14 3 Setting for DRAMC 14 7 14 8 4 C lll I E EE EEEE maw aasan 14 8 14 4 2 Re s l I GI C C I uu E 14 10 M 14 12 vi 7721 Group User s Manual CHAPTER 15 WATCHDOG TIMER Table of contents 16 1 Memor 6 1 1 Memor connection model ADDeNC vemo anme Appendix OUD Q amp A Append U L arence etween Appendix 12 Standard characteristics GLOSSARY 772
161. 28 5 Xa 16 MHz 1425 f Xin 25 MHz 18 24 9 12 7721 Group User s Manual 12 5 A D CONVERTER 12 2 Block description 12 2 2 A D sweep pin select register Figure 12 2 3 shows the structure of the A D sweep pin select register b7 b6 b5 b4 b3 b2 bl A D sweep pin select register Address 1F 6 A D sweep pin select bits bibo 1 RW Valid in single sweep and repeat 0 0 ANo AN 2 pins sweep mode Note 1 0 1 ANo to ANs 4 pins 1 1 0 ANo to ANs 6 pins 1 RW 1 1 ANo to AN 8 pins Note 2 Nothing is assigned Notes 1 These bits are invalid in the one shot and repeat modes They may be either O or 4 7 2 When selecting an external trigger the AN7 pin cannot be used as an analog input pin 3 Writing to each bit of the A D sweep pin select register must be performed while the A D converter halts Fig 12 2 3 Structure of A D control register 1 1 A D sweep pin select bits bits 1 and 0 These bits are used to select analog input pins in the single sweep mode or repeat sweep mode In the single sweep mode and repeat sweep mode pins which are not selected as analog input pins function as programmable I O ports 12 6 7721 Group User s Manual 12 2 3 A D register i i 0 to 7 A D CONVERTER 12 2 Block description Figure 12 2 4 shows the structure of the A D register i When the A D conversion is completed the conversion result contents of the successive approximation register is
162. 40 160 180 200 220 Analog input voltage mV Fig 12 4 1 Absolute accuracy of A D converter 12 12 7721 Group User s Manual A D CONVERTER 12 4 Absolute accuracy and differential non linearity error 12 4 2 Differential non linearity error The differential non linearity error indicates the difference between the 1 LSB step width the ideal analog input voltage width while the same output code is expected to output of an A D converter with ideal characteristics and the actual measured step width the actual analog input voltage width while the same output code is output For example when Veer 5 12 V the 1 LSB width of an A D converter with ideal characteristics is 20 mV however when the differential non linearity error is 1 LSB the actual measured 1 LSB width is 0 to 40 mV Output code A D conversion result 0916 1 LSB width with ideal 0816 A D conversion characteristics 0716 0616 0516 0416 0316 0216 0116 Differential non linearity error 0016 20 40 60 80 100 120 140 160 180 Analog input voltage mV Fig 12 4 2 Differential non linearity error 7721 Group User s Manual 12 13 A D CONVERTER 12 5 One shot mode 12 5 One shot mode In the one shot mode the operation for the input voltage from the one selected analog input pin is performed once and the A D conversion interrupt request occurs when the operation is completed 12 5 1 Settings for one shot mode Figure 12 5 1 sh
163. 6 15 to O These bits can be set to 000016 to FFFF e Undetinea RW Assuming that the set value n the counter divides the count source frequency by n 1 When reading the register indicates the counter value Note Read from or write to this register in a unit of 16 bits b7 b6 b5 b4 b3 b2 bi b0 ola Timer Bj mode register j 0 1 Addresses 5B16 5C 6 Bit Biname Functions aesa RW 9 w ni rating m lect bi K u aa hpls 01 Pil counter mode i Lom m Count polarity select bits b3 b2 RW 0 0 Count at falling edge of external signal 0 1 Count at rising edge of external signal 1 0 Counts at both falling and rising edges oa ee of external signal RW 1 1 Do not select NE cd Nothing is assigned o ee A P eee This bit is invalid in event counter mode its value is undefined at Undefined nr reading ME CHE of These bits are invalid in event counter mode 0 RWI L1 KECI 7721 Group User s Manual 17 25 APPENDIX Appendix 3 Control registers Pulse period pulse width measurement mode b15 b8 b7 bO b7 bO Timer BO register Addresses 5116 5016 Timer B1 register Addresses 5316 5216 15 to 0 The measurement result of pulse period or Undefined pulse width is read out Note Read from this register in a unit of 16 bits b7 b6 b5 b4 b3 b2 bi b0 LIB ao Timer Bj mode register j 0 1 Addresses 5B16 5C16 Bi ENL
164. 6 2616 D register 2716 2816 A D register 4 2916 2A16 A D register 5 2B16 2C16 A D register 6 2D16 A D register 7 2F16 3016 UARTO transmit receive mode register 3116 UARTO baud rate register 3216 UARTO transmit buffer register 5 3316 3416 UARTO transmit receive control register O 3516 UARTO transmit receive control register 1 3616 UARTO receive buffer register 3 16 3816 UART1 transmit receive mode register 3916 UART1 baud rate register SA16 UART1 transmit buffer register 3B16 3C16 UART1 transmit receive control register 0 3D16 UART1 transmit receive control register 1 3E16 3F16 UART1 receive buffer register 17 4 7721 Group User s Manual Access characteristics RW It is possible to read the bit state at reading The written value becomes valid RO It is possible to read the bit state at reading The written value becomes invalid WO The written value becomes valid It is impossible to read the bit state State immediately after reset 0 0 immediately after reset 1 1 immediately after reset Undefined immediately after reset Address Register name 4016 Count start register 4116 4216 One shot start register 4316 4416 Up down register 4516 4616 Timer AO register 4716 4816 Timer A1 register 4916 4A16 Timer A2 register 4B16 4016 Timer A3 register 4D16 4E16 Timer A4 register 4F16 1 one Timer BO register 5116 9216 Timer B1 register 0316 5416
165. 7 5 APP ENDIX Appendix 2 Memory assignment in SFR area Access characteristics RW It is possible to read the bit state at reading The written value becomes valid RO It is possible to read the bit state at reading The written value becomes invalid WO The written value becomes valid It is impossible to read the bit state Nothing is assigned It is impossible to read the bit state The written value becomes invalid State immediately after reset 1 1 immediately after reset Undefined immediately after 0 0 immediately after reset 0 1 reset Always 0 at reading Always 1 at reading Always undefined at reading NSS 0 immediately after reset Fix this bit to 0 Access characteristics Note 5 _ RW pt RW m RW RW O Note 7 i t q _ O JJ 2J PTET TTT TTT ETE TEE TTP TTT EP Ey yy JI IU U DDI JD 2J ZU seuss RW The dummy data is not retained anywhere 6 The value FFF16 is set to the watchdog timer Refer to CHAPTER 15 WATCHDOG TIMER State immediately after reset b7 b Note 6 5 0 0 0 0 0 0 0 0 e e By writing dummy data to address 6016 the value FFFt16 is set to the watchdog timer 7 t is possible to read the bit state at reading When writing 0 to this bit this bit becomes 0
166. 721 Group User s Manual SERIAL I O 11 2 Block description 11 2 5 UARTi receive register and UARTi receive buffer register Figure 11 2 7 shows the block diagram for the receiver Figure 11 2 8 shows the structure of UARTi receive buffer register Data bus odd Data bus even o jo 0j0jO JO 0 De NEN NEN buffer register SP Stop bit 8 bit UART PAR Parity bit Parity 9 bit UART 9 bit UART Clock enabled UART OCK Sync i se osr MP he M O O O O Clock sync 7 bit UART 7 bit UART 8 bit UART UARTi receive register Clock sync UARTO receive buffer register Addresses 3716 3616 UART1 receive buffer register Addresses 3F 16 3E16 Receive data is read out from here Undefined RO 15 to 9 Nothing is assigned The value is 0 at reading Fig 11 2 8 Structure of UARTi receive buffer register 7721 Group User s Manual 11 11 SERIAL I O 11 2 Block description The UARTi receive register is used to convert serial data which is input to the RxDi pin into parallel data This register takes in the signal input to the RxDi pin in a unit of 1 bit synchronously with the transfer clock The UARTi receive buffer register is used to read out receive data When reception is completed the receive data which is taken in the UARTIi receive register is automatically transferred to the UARTI receive buffer register Note that the contents of the UARTI receive buffer register is updated when the next da
167. 7721 Group User s Manual APPENDIX Appendix 9 7721 Group Q amp A Appendix 9 7721 Group Q amp A Information which may be helpful in fully utilizing the 7721 Group is provided in Q amp A format In Q amp A as a rule one question and its answer are summarized within one page The upper box on each page is a question and a box below the question is its answer If a question or an answer extends to two or more pages there is a page number at the lower right corner At the upper right corner of each page the main function related to the contents of description in that page is listed 7721 Group User s Manual 17 65 APPENDIX Appendix 9 7721 Group Q amp A SFR Is there any SFR to which a certain instruction cannot be used for writing 1 Use the LDM or STA instruction to write to the registers or the bits listed below Do not use read modify write instructions i e CLB SEB ASL ASR DEC INC LSR ROL and ROR Pulse output data register 0 1 addresses 1A e 1C e UARTO 1 baud rate register addresses 3116 39 6 UARTO 1 transmit buffer register addresses 3316 32 e 3Bie 3A16 Timer A2 A4 two phase pulse signal processing select bit bits 5 7 at address 4416 Timer A2 A4 register addresses 4A e 4F e one shot pulse mode or pulse width modulation mode Refresh timer address 66 6 Use the SEB or CLB instruction to write to the following register DMAC control register H address 69 e when
168. 8 16 bit data access gt e Access beginning at even address E ALE Ao to AT As to A15 A16 Do to A23 D7 BLE BHE 8 bit data access 16 bit data access f Access beginning at odd address E AN v7Z ALE N N Ao to Ar As to Ars A16 Do to A23 D7 BE YOK BEL 0 N 8 bit data access 16 bit data access Note When accessing 16 bit data 2 times of access are performed the low order 8 bits are accessed first and after that the high order 8 bits are accessed Fig 3 1 3 Examples of operating waveforms of signals input from or output to the external 2 7721 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 3 2 Software Wait 3 2 Software Wait Software Wait provides a function to facilitate access to external devices that require long access time To select the software Wait use the wait bit bit 2 at address 5E e Figure 3 2 1 shows the structure of processor mode register 0 address 5E e Figure 3 2 2 shows examples of bus timing when software Wait is used Software Wait is valid only for the eternal area The internal area is always accessed with no Wait b7 b6 b5 b4 b3 b2 bli Tol TT T o Processor mode register 0 Address 5E16 x EN Fix this bit to 0 o RW 1 Nothing is assigned 1 The value is 1 at reading 2 Wait bit 0 Software Wait is inserted when RW accessing external area 1 No software Wait is inserted when accessing external ar
169. 8 V Vin 2 5 V 7721 Group User s Manual 17 99 APPENDIX Appendix 11 Electrical characteristics At DMA transfer 1 bus transfer timing 1 DMAACKi Ao A7 output As Ds A15 D15 output BYTE L Do D15 input A16 Do A23 D7 output Do D7 output ALE output BHE output BLE output R W output 17 100 30 V A SN J w ie td o1 DAK td o1 DAK td AL E lt th E AL Wes toxz E DHZ tpzx E DHZ AdiN O U U I O l D dres tsu DH E th E DH td data XC oa td o1 DAK td AL E td 1 DAK lt gt l th E AL Gre X Xss td data toxz E DLZ oo dres tsu DL E tw ALE AC td ALE E tw ALE A td ALE E lt gt ld BHE E F th E BHE lt gt la BLE E lt gt lh E BLE AX MX s td R W E lt gt th E R W Test conditions Vcc 2 5V 1096 lt gt td BHE E td BLE E td R W E fo Output timing voltage Vor 0 8 V Vor 2 0 V eDo D15 input Vir 0 8 V ViH 2 5 V 7721 Group User s Manual tpzx E DLZ th E BHE pio th E BLE lt y th E R W APPENDIX Appendix 11 Electrical characteristics At DMA transfer Transfer complete timing 01 i W TG tw TC STO td 1 DAK DMAACKi lt td AL E GOENMO Ue EX Das X omen eros XX ata BYTE L dress lt gt td AM E BYTE H Ad
170. 8 bits of vector address Low order 8 bits of CPU internal address bus ADH Contents of vector address High order address CPU internal data bus for odd address AD Contents of vector address Low order address CPU internal data bus for even address Fig 7 7 2 INTACK sequence timing at minimum 7 7 1 Change in IPL at acceptance of interrupt request When an interrupt request is accepted the processor interrupt priority level IPL is replaced with the interrupt priority level of the accepted interrupt This results in easy control of the processing for multiple interrupts Refer to section 7 9 Multiple interrupts At reset or when a watchdog timer interrupt or a software interrupt is accepted a value listed in Table 7 7 1 is set into the IPL Table 7 7 1 Change in IPL at acceptance of interrupt request Interrupts Change in IPL Heset Level 0 0002 is set Watchdog timer Level 7 1112 is set Zero division Not changed BRK instruction Not changed Other interrupts Accepted interrupt priority level is set 7 14 7721 Group User s Manual INTERRUPTS 7 7 Sequence from acceptance of interrupt request until execution of interrupt routine 7 7 2 Push operation for registers The push operation for registers performed in the INTACK sequence depends on whether the contents of the stack pointer S at acceptance of an interrupt request are even or odd When the contents of the stack pointer S are even the c
171. 9 2 2 shows the structure of the count start register b7 b6 b5 b4 b3 b2 bl b0 Count start register Address 4016 sirens res la EN Timer AO count start bit Stop counting Start counting EN Timer A1 count start bit Ls inert comson J Bits 0 to 4 are not used for Timer B Fig 9 2 2 Structure of count start register 9 4 7721 Group User s Manual TIMER B 9 2 Block description 9 2 3 Timer Bi mode register Figure 9 2 3 shows the structure of the timer Bi mode register The operating mode select bits are used to select the operating mode of Timer Bi Bits 2 3 and bits 5 to 7 have different functions according to the operating mode These bits are described in the paragraph of each operating mode b7 b6 b5 b4 b3 b2 bi Timer mode Event counter mode Pulse period Pulse width RW measurement mode Do not select t KL e Undefined RO Note o RW o w Note Bit 5 is invalid in the timer and event counter modes its value is undefined at reading Fig 9 2 3 Structure of timer Bi mode register 7721 Group User s Manual 9 5 TIMER B 9 2 Block description 9 2 4 Timer Bi interrupt control register Figure 9 2 4 shows the structure of the timer Bi interrupt control register For details about interrupts refer to CHAPTER 7 INTERRUPTS b7 b6 b5 b4 b3 b2 bi bO Timer Bi interrupt control register i 0 to 2 Addresses 7A16 to 7C16 Interrupt prior
172. 923 MHz or less About Serial I O control in this expansion example is described below In this example 8 bit data transmission reception is performed 3 times by using UARTO so that 24 bit port expansion is realized Setting of UARTO is described below Clock synchronous serial I O mode Transmission Reception enable state internal clock is selected Transfer clock frequency is 1 66 MHz LSB first The control procedure is described below Output L level from port P4s Expanded I O ports of the M66010FP enter a floating state by this signal Output H level from port P4s Output L level from port P44 Transmit Receive 24 bit data by using UARTO Output H level from port P44 Figure 16 1 37 shows the serial transfer timing between the M37721 and the M66010FP 7721 Group User s Manual APPLICATION 16 1 Memory connection M37721 TxDo RxDo CLKo P44 P45 RTSo A0 A7 As Ds A15 D15 Expanded input ports A16 Do A23 D7 ALE Circuit conditions UARTO used in clock synchronous serial I O mode Internal clock selected p Frequency of transfer clock 1 5625 MHz ha 2 3 1 Fig 16 1 36 Example of port expansion circuit using M66010FP 7721 Group User s Manual 16 41 APPLICATION 16 1 Memory connection SuomneJedo JO seuueu s uid S d J0LO99IN 9Je sJeuio au eueuuldS 2 eW INdINO urejp uedo j UUBYO N s SUOd O pepuedxe jo einjon
173. A e to 1FF8 6 Transfer counter register O Transfer counter register 1 Transfer counter register 2 Transfer counter register 3 23 to 0 These bits have different functions according to the Undefined RW operating mode Note When writing to this register write to all 24 bits Do not write 00000016 to this register lt 7721 Group User s Manual 17 33 APPENDIX Appendix 3 Control registers Single transfer mode b23 b16 b15 b8 b7 bO Source address register O Source address register 1 Source address register 2 Source address register 3 Addresses 1FC216 to 1FC016 Addresses 1FD216 to 1FD016 Addresses 1FE216 to 1FE016 Addresses 1FF216 to 1FF0 6 lt b23 b16 b15 b8 b7 bO b23 b16 b15 b8 b7 bO 23 to 0 Write Undefined RW Set the transfer start address of the source These bits can be set to 00000016 to FFFFFF e Read The read value indicates the source address of data which is next transferred Note When writing to this register write to all 24 bits Destination address register O Destination address register 1 Destination address register 2 Destination address register 3 E Set the transfer start address of the destination These bits can be set to 00000016 to FFFFFF e Addresses 1FCA16 to 1F C816 Addresses 1FDA te to 1FD816 Read The read value indicates the destination address of Addresses 1FEAte to 1FE816 Add
174. A transfer modes 13 4 7721 Group User s Manual DMA CONTROLLER 13 1 Overview 4 Continuous transfer mode B Single transfer mode 1 block of data is transferred once For details refer to section 13 5 Single transfer mode E Repeat transfer mode 1 block of data is transferred repeatedly For details refer to section 13 6 Repeat transfer mode B Array chain transfer mode several blocks of data are transferred The transfer parameters transfer source and destination addresses the number of transfer bytes of each block must be located on the memory in series For details refer to section 13 7 Array chain transfer mode B Link array chain transfer mode Several blocks of data are transferred Transfer parameters for each block can be located on the memory in separate in a unit of 1 block s parameters For details refer to section 13 8 Link array chain transfer mode 7721 Group User s Manual 13 5 DMA CONTROLLER 13 2 Block description 13 2 Block description Figures 13 2 1 and 13 2 2 show the DMAC block diagrams and relevant registers are described below Address bus dem Incrementer Decrementer Source address register 0 SARO Destination address register 0 DARO Source address register 1 SAR1 Transfer counter register 0 TCRO Source address register 2 SAR2 Transfer counter register 1 TCR1 Destination address register 2 DAR2 Transfer counter register 2 TCR2 Source address r
175. A3 count start bit Timer A4 count start bit J Count starts Fig 8 3 3 Initial setting example for registers relevant to timer mode 2 8 12 7721 Group User s Manual TIMER A 8 3 Timer mode 8 3 2 Count source In the timer mode the count source select bits bits 6 and 7 at addresses 5616 to 5A e select the count source Table 8 3 2 lists the count source frequency Table 8 3 2 Count source frequency Count source Count Count source frequency select bits source b7 b6 f Xin 8 MHz f Xin 16 MHz f Xin 25 MHz 0 0 12 5 MHz 0 500 kHz 1 5625 MHz 1 0 125 kHz 250 kHz 390 625 kHz 1 1 15625 Hz 31250 Hz 48 8281 kHz 7721 Group User s Manual 8 13 TIMER A 8 3 Timer mode 8 3 3 Operation in timer mode When the count start bit is set to 1 the counter starts counting of the count source When a counter underflow occurs the reload register s contents are reloaded and counting continues The timer Ai interrupt request bit is set to 1 at the underflow in The interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to O by software Figure 8 3 4 shows an example of operation in the timer mode n Reload register s contents FFFF16 Starts counting Stops countin 1 1 X n1 P d Restarts counting Counter contents Hex 000016 Set to 1 by software Cleared to 0 by software
176. AO interrupts This interrupt occurs every 64 ms See flow chart Flow chart Timer AO Main routine Interrupt routine i Port P104 CAS L level output Bits 4 5 of port P10 register 1 address 1616 Bit 4 of port P10 register O address 1616 Ports P104 P10s neve ouput Port P10s RAS L level output Bits 4 5 of port P10 direction 1 register address 18 6 Bit 5 of port P10 register 0 address 16 6 DRAM validity bit c 0 bit 7 at address 64 6 Port P104 CAS H level output Bit 4 of port P10 register 1 DRAMC stopped address 16 Port P10s RAS H level output Timer AO mode lt 110000007 t counted register address 56 6 Bit 5 of port P10 register 1 address 1616 Timer AO register lt 3124 Timer value set addresses 4716 4616 One cycle 64 ms Interrupt priority level set Timer AO interrupt XXXX00012 evel 4 or more Interrupt control register address 75 6 enabled Return to main routine Timer AO count start lt T Timer AO count started bit bit 0 at address 4016 Interrupt enable flag lt 0 Interrupt enabled WIT instruction Wait mode Wait mode completed Y Note By using 1 bit of RAM judge whether this interrupt is for return from the wait mode or for refresh 2 2 7721 Group User s Manual 17 75 APPE
177. Az3 D7 pins perform address output and data input output with time sharing When the BYTE pin level is H external data bus width is 8 bits the A1e Do Azs D7 pins perform address output and data input output with time sharing and the As Ais pins output the address External data bus width switching signal BYTE pin level This signal is used to select the external data bus width from 8 bits and 16 bits The width is 16 bits when the level is L and 8 bits when the level is H Fix this signal to either H or L level This signal is valid only for the external area When accessing the internal area the data bus width is always 16 bits Enable signal E This signal becomes L level while reading or writing data from and to the data bus Refer to Table 3 1 1 Read Write signal R W This signal indicates the state of the data bus This signal becomes L level while writing data to the data bus Table 3 1 1 lists the state of the data bus indicated with the E and R W signals Table 3 1 1 State of data bus indicated with E and R W signals E State of data bus H Not used L Read data Write data 7721 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 3 1 Signals required for accessing external devices L External data bus width 16 bits BYTE rq ozy eq e v zq siy Ig Ziy 0q 91V SIQ sly riq rly ei g erv e gewv ug iiy oLg orv eq ev eq ev AN W AN
178. BRGi s output divided by 2 becomes the transfer clock Additionally the transfer clock is output from the CLKi pin By setting this bit to 1 in order to select an external clock the clock input to the CLKi pin becomes the transfer clock E UART mode By clearing this bit to 0 in order to select an internal clock the clock which is selected with the BRG count source select bits bits 0 and 1 at addresses 3416 3C e becomes the count source of the BRGi described later Then the CLKi pin functions as a programmable l O port By setting this bit to 1 in order to select an external clock the clock input to the CLK pin becomes the count source of BRGi Always in the UART mode the BRGi s output divided by 16 becomes the transfer clock 7721 Group User s Manual 11 5 SERIAL I O 11 2 Block description 11 2 2 UARTI transmit receive control register 0 Figure 11 2 3 shows the structure of UARTi transmit receive control register 0 For bits 0 and 1 refer to section 11 2 1 1 Internal External clock select bit bit 3 b7 b6 b5 b4 b3 b2 bl UARTO transmit receive control register 0 Address 34 6 UART1 transmit receive control register 0 Address 3C e BRG count source select bits b1 bO RW 00 f2 01 f16 RW 10 fea 1 1 f512 CTS RTS select bit A CTS function selected RTS function selected Transmit register empty flag 0 Data present in transmit register Ne transmission No data present in tra
179. Block description 14 2 1 DRAM control register Figure 14 2 2 shows the structure of the DRAM control register b7 b6 b5 b4 b3 b2 bi b0 DRAM control register Address 6416 Bit name Functions At reset b3 b2 b1 bO DRAM area select bits 0000 No DRAM area 0001 F0000016 FFFFFF16 1 Mbyte E000001e FFFFFF 16 2 Mbytes D00000 e FFFFFF e 3 Mbytes C00000 FFFFFF e 4 Mbytes e O O B0000016 FFFFFF16 5 Mbytes A0000016 FFFFFF 16 6 Mbytes 90000016 FFFFFF 6 7 Mbytes 8000001e FFFFFF 16 8 Mbytes 70000016 FFFFFF 6 9 Mbytes 600000ie FFFFFF 16 10 Mbytes 500000 e FFFFFF e 11 Mbytes 4000001e F FFFFF 16 12 Mbytes 30000016 FFFFFF 16 13 Mbytes 2000001e FFFFFF 6 14 Mbytes 1000001 FFFFFF46 15 Mbytes 6 to 4 Nothing is assigned The value is 0 at reading DRAM validity bit Note 0 Invalid P104 P107 pins function as programmable input ports Ao A pins function as address output pins Refresh timer stops counting 1 Valid P104 P107 pins function as CAS RAS MAs and MAs Ao Az function as MAo MA Refresh timer starts counting I I I I I I I I I I I I I I I I I I I I E Note Set the refresh timer address 66 6 before setting this bit to 1 Fig 14 2 2 Structure of DRAM control register 7721 Group User s Manual 14 3 DRAM CONTR
180. DMAC control register H Address 6916 0 No request 1 Requested Interrupt request of each peripheral function occurs 2S E E m EEEE DMA transfer starts Fig 13 7 5 Initial setting example for registers relevant to array chain transfer mode 3 13 74 7721 Group User s Manual DMA CONTROLLER 13 7 Array chain transfer mode 13 7 3 Operation in array chain transfer mode Figure 13 7 6 shows the operation flowchart of the array chain transfer mode and Figures 13 7 7 and 13 7 8 show timing diagrams of the array chain transfer mode burst transfer mode For the cycle steal transfer mode refer to the following Transfer of transfer parameters in an array state Figures 13 8 10 and 13 8 11 All transfers except in an array state and except the last 1 unit transfer of each block Figure 13 8 12 Last 1 unit transfer of each block except the last block Figure 13 8 13 Last 1 unit transfer of the last block Figure 13 8 14 The processing performed in the array chain transfer mode consists of an array state and a transfer state 1 Array state In an array state transfer parameters are read from the transfer parameter memory in a unit of 2 bytes and transferred to registers SARi DARI and TCRi and their latches As shown in Figure 13 7 2 a transfer parameter consists of 4 bytes 24 bits of data 8 bits of dummy data One bus cycle always consumes 3 cycles of During an array state the DMAACK
181. E output BHE output BLE output R W output 17 98 tsu DRQ 1 tw DRQ td 1 STi Address Address Mises Dam Yars X i U TE td 1 DAK td AL E Address a th E AL CT ess y nations Rares ta E DHQ SC Dua 3 Address td AM E th ALE AM rares Address X Adress Adress td AH E td E DLQ tw ALE td ALE E A td BHE E gt lt y td BLE E lt gt td R W E lt gt Test conditions Vcc 5 V 10 Output timing voltage Vor 0 8 V Vor 2 0 V Do Di5 input Vir 0 8 V Viu 2 5 V DMAREQi input Vi 0 8 V Vin 2 5 V 7721 Group User s Manual Data Address Ad sey gt lt th ALE AH th E BHE th E BLE th E R W APPENDIX Appendix 11 Electrical characteristics At DMA transfer Cycle steal transfer timing External source DMAREQi 1 E tsu DRQ 61 tw EL DMAREQi hO ta g1 STi STO td 1 STi td o1 DAK td o1 DAK DMAACKi td AL E gt lt th E AL As Ds A15 D15 output Data AFN LLL Ll Ad N LL LLL td AM E gt lt th E AM As Ds A15 D tout td AH E 3L le pvtbe AevDr ouput Ades Eje Qe n aa tw ALE td ALE E ALE output td BHE E 5 l lt th E BHE BHE output ta R W E R W output Test conditions Vcc 5 V 1096 Output timing voltage Vor 0 8 V Vor 2 0 V Do Dis input Vi 0 8 V Vin 2 5 V DMAREQi input Vit 0
182. E stops at H level for 1 cycle of cru clock 61 indicated by 32222 and CPU stops at L level E The L level which is input to the RDY pin is not accepted however CPU stops at L level ALE 3 The L level which is input to the RDY pin is accepted so that E stops at L level for 1 cycle of f OOOO r ai y clock 01 indicated by 3888 and CPU stops RDY i at L level Bus not in use Bus in use Ready state is terminated The L level which is input to the RDY pin is not accepted because it is sampled immediately before f Wait by software Wait indicated by GY lt Wait gt however CPU stops at L level RDY pin input level 9 sampling timing l T L L l Clock 6 R R R cpu l l f l l l l 1 l Ep EE E i I lt l rar l ALE l m RDY l l Bus in use ER Fig 3 3 1 Timing of acceptance of Ready request and termination of Ready state 7721 Group User s Manual 3 1 1 CONNECTION WITH EXTERNAL DEVICES 3 4 Hold function 3 4 Hold function When composing the external circuit which accesses the bus without using the central processing unit CPU Hold function is used to generate a timing for transferring the right to use the bus from the CPU to the external circuit The microcomputer enters Hold state by input of L level to the HOLD pin and retains this state while th
183. ER 14 DRAM CONTROLLER Stop mode When states to are terminated Watchdog timer restarts counting from the state before it stops operation For Watchdog timer s operation when state is terminated refer to section 15 2 3 Operation in Stop mode 15 2 3 Operation in Stop mode In Stop mode Watchdog timer stops operation Immediately after Stop mode is terminated Watchdog timer operates as follows Refer to section 5 3 Stop mode 1 When Stop mode is terminated by hardware reset Supply of and cru starts immediately after Stop mode is terminated and the microcomputer performs operation after reset Refer to CHAPTER 4 RESET ihe watchdog timer frequency select bit becomes 0 and Watchdog timer starts counting of fsi2 from FFFie 2 When Stop mode is terminated by interrupt request occurrence Immediately after Stop mode is terminated Watchdog timer starts counting of fs from FFF e regardless of the contents of watchdog timer frequency select bit bit O at address 6116 Supply of and creu starts when Watchdog timer s most significant bit becomes 0 At this time a watchdog timer interrupt request does not occur When supply of cru starts the microcomputer executes the routine of the interrupt which is used to terminate Stop mode Watchdog timer restarts counting of the count source fs2 or fs12 which was counted immediately before executing the STP instruction from FFF46
184. Even address transfer start M address Dummy data E Transfer data s byte number Even address Even address x90 g 104 Sje1eueaed 1eJsueJ Transfer source s transfer start address 4 Transfer parameter address 4 last block When transferring from I O to memory replace all the above mentioned Transfer source s transfer start address with Transfer destination s transfer start address 4 block transfer Fig 13 8 2 Transfer parameter memory map in link array chain transfer mode 7721 Group User s Manual 13 83 DMA CONTROLLER 13 8 Link array chain transfer mode 13 8 2 Setting of link array chain transfer mode Figures 13 8 3 through 13 8 5 show an initial setting example for registers relevant to the link array chain transfer mode In addition when timer A timer B UART or the A D converter is selected as a DMA request source the setting for the peripheral is required For details of the setting refer to the chapter of each peripheral function When a DMAi interrupt is used the setting for enabling the interrupt is also required For details refer to CHAPTER 7 INTERRUPTS When external DMA source is selected When internal DMA source is selected a Setting port P9 direction register N b7 0 Port P9 direction register Address 1516 DMAREQO pin DMAREQ1 pin DMAREQ2 pin DMAREQ3 pin Clear the corresponding bit to 0 BEER ERE L Setting interru
185. FE616 to 1F E416 DAR2 Destination address register 3 Addresses 1FF616e to 1FF416 DAR3 Need not to be set lalis sss sss sss 23 to 0 i Read Undefined RW After transfer starts the read value indicates the destination address of data which is next transferred b23 b16 b15 bg b7 b0 Transfer counter register 0 Transfer counter register 1 Addresses 1FCA16 to 1FC816 TCRO Addresses 1FDA16 to 1FD816 TCR1 Transfer counter register 2 Addresses 1FEA16 to 1FE816 TCR2 Transfer counter register 3 Addresses 1FFA16 to 1FF816 TCR3 L Write l Set the number of transfer blocks Undefined Fey These bits can be set to 00000116 to FFFFFF e Read e After a value is written to this register and until transfer starts the read value indicates the written value the transfer block number After transfer starts the read value indicates the remaining byte number of the block which is being transferred Note When writing to this register write to all 24 bits Do not write 00000016 to this register Fig 13 7 1 Register structures of SARi DARi and TCRi in array chain transfer mode 7721 Group User s Manual 13 69 DMA CONTROLLER 13 7 Array chain transfer mode 13 7 1 Transfer parameter memory in array chain transfer mode The transfer parameters required for each transfer method are described below These parameters must be located in series starting at an even addres
186. FP M37720S1AFP Internal RAM size 1024 bytes Note 512 bytes External clock input frequency 25 MHz maximum 16 MHz maximum Instruction execution time minimum 250 ns Bit configuration of 4 bits X 2 channels or 4 bits X 2 channels real time output channel 6 bits X 1channel and 2 bits X 1channel g Port latch state after Retains the value before using Undefined nil using real time output Limitation for instruction used when writing Nothing LDM STA instructions Exists LDM STA instructions to interrupt control register cannot be used Timing when overrun error flag One of the following One of the following becomes 0 When setting the receive enable When setting the receive bit to 0 enable bit to 0 When setting the serial O mode When setting the serial I O select bits to 000 mode select bits to 0002 When reading the receive buffer register When all of the following are signal in clock synchronous serial I O satisfied satisfied mode RHeceive enable bit 1 RHeceive enable bit 1 Reception is stopped Reception is stopped Serial I O Conditions for outputting L of RTS When all of the following are Dummy data is present in the transmit buffer register DMA shortest transfer rate 12 5 Mbytes sec 8 Mbytes sec At 1 bus cycle transfer Note 512 bytes can be selected by software For the M37721S1BFP its internal RAM size is 512 bytes 7721 Group
187. FREREETEETE y X M CPX Compares the contents of the index register X with the Note 2 contents of the memory CPY Y M Compares the contents of the index register Y with the Note 2 contents of the memory DEC Acc cAcc 1 or Decrements the contents of the accumlator or memory by Note 1 M lt M 1 1 Decrements the contents of the index register X by 1 H Decrements the contents of the index register Y by 1 DIV A quotient B A M Notes 2 10 B remainder The numeral that places the contents of accumlator B to the higher order and the contents of accumulator A to the lower order is divided by the contents of the memory The quotient is entered into accumula tor A and the remainder into accumulator B EOR Acc AccvM Logical exclusive sum is obtained of the contents of the 49 45 55 5 52 41 7 2151 Notes 1 2 accumulator and the contents of the memory The result is placed into the accumulator 42 42 4017 42 3 4 49 45 55 52 51 Acc cAcc 1 or Increments the contents of the accumulator or memory by M lt M 1 Increments the contents of the index register X by 1 INY Increments the contents of the index register Y by 1 JMP Places a new address into the program counter and jumps to that new address Co p 9 8 Je w P gt Pr PCH lt ADH ABL PCL AD PCHc ADuH PG ADc ABS PCi lt ADu ADL PCH lt ADu ADL 1 L ABS PCi lt ADu ADL PCH lt ADu AD 1
188. H only 1 byte of the instruction is fetched When the instruction which is next fetched is located at an odd address the BIU fetches only 1 byte with the timing of waveform a The contents at the even address are not taken into the instruction queue buffer When reading or writing data to and from the memory l O device When accessing a 16 bit data which begins at an even address waveform a is applied The 16 bits of data are accessed at a time When accessing a 16 bit data which begins at an odd address waveform b is applied The 16 bits of data are accessed separately in 2 operations 8 bits at a time Invalid data is not fetched into the data buffer When accessing an 8 bit data at an even address waveform a is applied The data at the odd address is not fetched into the data buffer When accessing an 8 bit data at an odd address waveform a is applied The data at the even address is not fetched into the data buffer For instructions that are affected by the data length flag m and the index register length flag x operation or is applied when flag m or x 0 operation G or is applied when flag m or x Ie 7721 Group User s Manual 2 13 CENTRAL PROCESSING UNIT CPU 2 2 Bus interface unit Internal address bus Ao tO A23 Internal data bus Do to D7 Data Even address Internal data bus Ds to D15 Data Odd address NL QN Internal address bus Ao tO A23 Address Odd a
189. H 001FD716 rr i O 001FD816 b 001FD916 Transfer counter register 1 M 001FDAt16 H OOIFDBis aea AY 001FDC16 001FDDte 001FDEte odFDFis aw R 001FE016 001FE116 Source address register 2 001FE216 001FE416 L 001FE616 H 001FE816 L 001FE916 Transfer counter register 2 M x O 001FEB16 001FEC16 DMA2 mode register L 001FED16 DMA2 mode register H 001FEE16 DMA2 control register OMFEFis 001FF016 L 001FF116 Source address register 3 M 001FF216 H OMFFBig 001FF416 L 001FF516 Destination address register 3 M 001FF616 H OFF 001FF816 L 001FF916 Transfer counter register 3 M 001FFA16 H oB 001FFC16 001FFD16 DMA3 mode register H 001FFE16 DMAS control register 001FFF16 Fig 2 4 3 SFR area s memory map 2 7721 Group User s Manual 2 21 CENTRAL PROCESSING UNIT CPU 2 4 Memory assignment b7 b6 b5 b4 b3 b2 bi b0 fo jo Processor mode register O Address 5E16 Fix this bit to 0 EN IS assigned EN value is 1 at reading 2 Wait bit 0 Software Wait is inserted when accessing external area 1 No software Wait is inserted when accessing external area E Cert Interrupt priority detection time Ded eodcm Software reset bit The microcomputer is reset by WO writing 1 to this bit The value is 0 at reading EE select bits 0 0 7 cycles of 0 1 4 cycles of M c
190. I I Z Z Z Z Z O O O O O mmh ah amp mmo ha Do O O O w uas w lt O m D s O1 OO OO OO O CO Co O 00 Co O O O IN O1 O1 O1 O1 O1 lt a O1 01 O1 Q2 OO gt a O a O Co Oi oO I Z Z Z O O O mmh h amp DIOD w es ee m O p D Note Figure 13 shows the test circuit 7721 Group User s Manual Unit ns ns ns ns ns ns ns Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 17 89 APPENDIX Appendix 11 Electrical characteristics Test conditions port Pi Vcc 5 V 10 17 90 Microprocessor mode with no Wait lt Write gt f XiN 1 E Address output A0 A7 Address output A8 A15 BYTE H Address Data output As Ds A15 D15 BYTE L Data input Do D15 BYTE L Address Data output A16 Do A23 D7 Data input Do D7 ALE output BHE output BLE output R W output Port Pi output i 2 4 10 tw L tw H tr d tc PIR ARPS td E 61 la E 61 tw EL R 7A td AL E lt gt Address j td AM E Adres j th E AL th E AM td AM E lt gt lt gt ta E DHQ th E DHQ ues Daa Y lt td AM ALE th ALE AM td AH E E td E DLQ th E DLQ Test conditions except port Pi Vcc 5 V 10 Input timing vo
191. L level and within a period of 4 to 5 cycles of after the RESET pin goes from L to H the microcomputer initializes the central processing unit CPU and SFR area At this time the contents of the internal RAM area become undefined except when Stop or Wait mode is terminated Refer to Figures 4 1 3 to 4 1 9 After the microcomputer performs Internal processing sequence after reset Refer to Figure 4 1 10 The microcomputer executes a program beginning with the address set into the reset vector addresses FFFE e and FFFFie 4 2 7721 Group User s Manual RESET 4 1 Hardware reset 4 1 1 Pin state Table 4 1 1 lists the microcomputer s pin state while RESET pin is at L level Figure 4 1 2 shows the RESETour output retaining timing Table 4 1 1 Pin state while RESET pin is at L level Pin Bus Port name Pin state Ao MAo A MA As Ds Ais Dis Aie Do A23 D7 BHE BLE Outputs H or L level R W E STO ST1 Outputs H level ALE RESETour Outputs L level i Outputs HOLD RDY P4s P47 P5 P10 Floating When RESET pin input level goes from L to H in this period lt I LE LE LP L A LILIN L RESET lt q 3 5 cycles of 61 RESETour Fig 4 1 2 RESETour output retaining timing 7721 Group User s Manual 4 3 RESET 4 1 Hardware reset 4 1 2 State of CPU SFR area and internal RAM area Figure 4 1 3 shows the sta
192. LE pulsewidth Note f BHE output delay time oZ o Not 20 BLE output delay time o Z o 1 o Not 20 RW output delay ime O O Not 20 Address low order hold ime gt Not 18 Address middle order hold time BYTE L 9 Data high order hold time BYTE L Not 18 Data high order floating release delay time BYTE L Note 20 Address middle order hold time BYTE Note 18 Address high order hold time 9 Data low order hold time Note 18 Data low order floating release delay time Note 20 BHE hold time Note 18 BLE hold time m Wf N 4 IR Whold time C Note hold time Noti 8 E deles f QU ss width Note s Copy delay time delay time Te ouput sey ea TC output pulse width Not 50 TC input setup time E TC input setup time TC input pulse width 86 Note Figures 13 and 14 show the test circuits 7721 Group User s Manual ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 17 97 APPENDIX Appendix 11 Electrical characteristics At DMA transfer Burst transfer timing External source DMAREQi 01 DMAREQI STO DMAACKi Ao A7 output As Ds A15 D15 output BYTE L As Ds A15 D15 output BYTE H A16 Do A23 D7 output AL
193. Level sense The INT interrupt request occurs by detecting the state of pin INT all the time Therefore when the user does not use the INT interrupt set the INT interrupt s priority level to level O 7 18 7721 Group User s Manual INTERRUPTS 7 10 External interrupts INTi interrupt b7 b6 b5 b4 b3 b2 bli INTo to INT2 interrupt control registers Addresses 7D16 to 7F16 Bit name Functions At reset Interrupt priority level select bits Level 0 Interrupt disabled Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 1 Interrupt requested Polarity select bit 0 Interrupt request bit is set to 1 at H level when level sense is selected this bit is set to 1 at falling edge when edge sense is selected Interrupt request bit is set to 1 at L at level when level sense is selected this bit is set to 1 at rising edge when edge sense is selected 5 Level sense Edge sense 0 Edge sense select bit 1 Level sense 7 6 Nothing is assigned Undefined Note The interrupt request bits of INTo to INT2 interrupts are invalid when the level sense is selected Fig 7 10 1 Structure of INTi i 0 to 2 interrupt control register b7 b6 b5 b4 b3 b2 bl b0 LLL LLL TL Td d Port P10 direction register Address 1816 EN ERE INTo pin 0 Input mode 1 Output mode 1 INT pin When using a pin as an input pin INT2 pin for an external interrupt clear the
194. MA request acceptance Figure 13 3 2 shows an example of timing from the determination of a DMA request until the DMA transfer execution Refer to section 13 9 DMA transfer time for the time from DMA request generation until the CPU s regaining the right to use bus via DMA transfer Note In the following cases BUS REQUEST DMAC does not go 1 However the DMAi request bit remains set to 1 Accordingly after completion of each state the channel priority levels and bus use priority levels are determined and BUS REQUEST DMAC goes 1 if any DRAM refresh request or Hold request is not generated e When a DMA request is generated during a burst transfer or in an array state However if a DRAM refresh request or Hold request is generated during this term its BUS REQUEST goes 1 e When a DMA request is not accepted with a DRAM refresh request or Hold request generated 7721 Group User s Manual 13 23 DMA CONTROLLER 13 3 Control When DMAi request is to use bus sampled at this point 1 unit transfer R W Address Address Data DMAi enable bit DMAREGI DMAi request bit Q BUS REQUEST DMAC Bus request sampling DMAACKi TC ST1 STO DMAi interrupt request bit Transition of right Channel priority level determination and bus use priority level determination 1 5 cycles of 6 Read cycle Write cycle e i 8 j 7 When Burst tra
195. MA transfer as the previous one from the beginning At normal and forced termination the latches of SARi DARi and TCRi maintain their values written before the transfer start Refer to Figure 13 3 4 a Therefore DMA transfer must be restarted according to the following procedures In single or repeat transfer mode Set the DMAi enable bit to 1 It is not necessary to re set the values of SARi DARi and TCRi by software Refer to Figure 13 3 4 b In array chain or link array chain transfer mode Re set the values of SARi and TCRi Set the DMAi enable bit to 1 Restarting transfer of data subsequent to one which has been transferred just before forced termination When reading values at the addresses of SARi DARi and TCRi after forced termination the values of these registers counters can be read These read values are the transfer source address the transfer destination address which were to be transferred subsequently and the number of remaining bytes When writing these read values to the addresses of SARI DARI and TCRi respectively the same values are also written to their latches When setting the DMAi enable bit to 1 under this condition transfer of data subsequent to one which has been transferred just before forced termination is restarted Refer to Figure 13 3 4 c In single transfer mode The remaining data can be transferred by the following procedure Read the values at addre
196. MAi s I O pins Precautions for DMAC Do not access the registers relevant to DMAC by using DMA transfers the address of the accessing register collides with that of the accessed one on the DMAC internal bus 13 18 7721 Group User s Manual DMA CONTROLLER 13 3 Control 13 3 Control The conditions for performing DMA transfer of DMAi i 0 3 are as follows Neither a DRAM refresh request nor a Hold request is generated A request of the channel with a higher priority than that of DMAi is not generated or the request is disabled though it has been generated DMAi is enabled DMAi enable bit 1 e A DMAi request is generated DMAi request bit 1 The control method for each channel is described below 13 3 1 DMA enabling Each of DMA channels 0 3 has a DMAi enable bit bits 4 7 at address 6916 Table 13 3 1 lists the conditions for changing each DMAi enable bit Table 13 3 1 Conditions for changing DMAi enable bit DMAi enable bit Conditions for bit change Is set to 1 A write of 1 to the DMAi enable bit Is cleared to 0 e A write of 0 to the DMAi enable bit Transfer of an entire batch of data is complete normal termination A change of TC input level from H to L during a DMA transfer of DMAi Note Forced termination when TC pin is valid Note In the burst transfer mode level sense however the term from the DMA transfer start until the transfer completion of an ent
197. MAo MAo R W output X tw RASL RAS output At refreshing td CAS RAS th RAS CAS lt gt lt CAS output tw CASL Test conditions Vcc 25V 10 Output timing voltage Vor 0 8 V Vor 2 0 V Do D s input Vi 0 8 V Viu 2 5 V 17 96 7721 Group User s Manual APPENDIX Appendix 11 Electrical characteristics DMAC switching characteristics Vcc 5 V 10 Vss 0 V Ta 20 to 85 C f Xin 25 MHz unless otherwise noted Note The limits depend on f Xin Table 6 lists calculation formulas for the limits tsu DRQ 1 tw DRQ td 1 STi td 1 DAK ta AL E ta E DHQ lpxz E DHZ tda AM E td E DLQ pxz E DLZ ta AH E td ALE E tw ALE td BHE E td BLE E ta R W E th E AL th ALE AM th E DHQ lpzx E DHZ th E AM th ALE AH th E DLQ lpzx E DLZ th E BHE th E BLE th E R W tw EL la data ta oi TO tw TO tsu TCin lw TCiN DMAREGI DMAREQi input setup ime IU setup time MPEG et ee we e STO STi output delay time J 40 DMAACKi output delay time 6 Address low order output delay ime Note 15 Data high order output delay time BYTE 0 8 Data high order floating start time mE L ana CU Data low order Guibut delay time 85 Data low order EIE start delay time s Address high order output delay time I Note 15 ALE ouput sim a A
198. NDIX Appendix 9 7721 Group Q amp A DRAM How is the program execution time affected when using DRAM 17 76 When the M37721 uses DRAM the execution time is affected as follows CPU stops and DRAM refresh cycle is inserted 1 bus cycle becomes 36 when accessing DRAM 1 Refresh method of the M37721 s DRAMC is the dispersion refresh and 5 cycles of are necessary for one refresh The rate occupied by the DRAM refresh cycle during the program execution time is described below Rate occupied by DRAM refresh cycle during program execution time Rate occupied by DRAM refresh cycle f Xin 25 MHz f Xin 16 MHz Todos Hs 2 6 96 4 2 Case of 512 refresh cycles every 8 ms Pes 0 3 96 0 5 95 Case of 512 refresh cycles every 64 ms Hefresh interval 2 The comparison results of two sample programs execution times are listed below one is for the case where SRAM is used and the other is for the case where DRAM is used Use conditions Execution program Sample program B See 2 2 f Xin 16 MHz External data bus width 16 bits Refresh interval 13 us Memory used as work area Software wait valid area Speed comparison SRAM 1 00 SRAM 1 47 DRAM bank FF 1 15 DRAM bank FF s 1 53 1 2 7721 Group User s Manual APPENDIX Appendix 9 7721 Group Q amp A DRAM Sample program B SEP X CLM DATA 16 INDEX 8 LDY 69 LOOPO LDX 69 LOOP1 ASL SOUR X SEM DATA 8 ROL SOUR 2 X ROL B CLM DATA 16
199. O 1 0 DMAC 1 1 CPU 1 unit transfer Terminate processing 4 jp Transition of Transition of right to use bus right to use bus The above figure is the example of the last term for processing the second block in Figure 13 8 9 The Bus request caused by DRAM refresh Hold or DMA is sampled while the bus request sampling signal is H and is accepted Fig 13 8 14 Timing diagram of cycle steal transfer mode 5 13 96 7721 Group User s Manual DMA CONTROLLER 13 8 Link array chain transfer mode Precautions for link array chain transfer mode If the following two conditions are satisfied when the transfer unit is 16 bits and the address direction of transfer source or destination is fixed the link array chain transfer mode can be used The external data bus width 16 bits or the internal memory is used e The transfer start address on the address direction fixed side is an even address 7721 Group User s Manual 13 97 DMA CONTROLLER 13 9 DMA transfer time 13 9 DMA transfer time Calculation of time from the CPU s relinquishing the right to use bus until its regaining the right under the following conditions is described with reference to cycles of 6 A DMAi request is generated while the CPU holds the right to use bus The above right is returned to the CPU after completion of DMA transfer for one DMA request For the time per 1 unit transfer refer to section 13 4 1 2 Bus operation
200. O interrupt control register Address 7516 tt oL Timer A1 interrupt control register Address 7616 EN Interrupt priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 Continue to Figure 10 3 3 Fig 10 3 2 Initial setting example for registers relevant to real time output 2 10 8 7721 Group User s Manual REAL TIME OUTPUT 10 3 Setting of real time output Continue to Figure 10 3 2 When pulse mode 0 is selected BEER ERE RRR RRR RRR RRR RRR RRR RRR RRR RRR eee m m f senina real time output port bO Real time output control register Address 6216 Waveform output select bits b1 b0 0 1 RTPOo RTPOs RTP10 RTP13 RTPOo RTPOs and RTP1o RTP1s 10 11 Pulse mode 0 MEM Va When pulse mode 1 is selected qu real time output port b7 bO E Setting count start bit to 1 b7 bO Count start register Address 4016 Timer AO count start bit Timer A1 count start bit Pulse output starts after overflow of Timer AO or A1 E Real time output control register Address 6216 Waveform output select bits b1 bO 0 1 RTPOo RTPO 1 0 RTP02 RTPOs and RTP1o RTP13 RTPOc RTPOs and RTP1o RTP1s 11 L Pulse mode 1 T N Fig 10 3 3 Initial setting example for registers relevant to real time output 3 7721 Group Use
201. OLLER 14 2 Block description 1 DRAM area select bits bits 0 to 3 These 4 bits specify a DRAM area of 15 Mbytes maximum in a unit of 1 Mbyte Figure 14 2 3 shows setting examples of DRAM areas 1 Mbyte 4 Mbytes 8 Mbytes 15 Mbytes 00000016 00000016 00000016 00000016 10000016 80000016 Maximum C0000016 F0000016 FFFFFF16 Minimum FFFFFF16 FFFFFF16 FFFFFF16 DRAM area 00012 DRAM area select bits Bits 3 0 Fig 14 2 3 Setting examples of DRAM areas 2 DRAM validity bit bit 7 When this bit is set to 1 pin functions for DRAM control become valid and the refresh timer starts counting Table 14 2 1 lists the pin functions for DRAM control Table 14 2 1 Pin functions for DRAM control Pins DRAM Operation Ao MAo P10s MAs P104 CAS A16 Do A23 D7 STO ST1 validity bit A7 MAz P107 MAs P105 RAS As Ds Ais D15 R W E BLE BHE CAS RAS Aie Do Az3 D7 STO ST1 bid As Ds Ai15 D15 R W E BLE BHE 1 DRAM refresh CAS RAS A16 Do Az3 D7 STO ST1 As Ds Ais D1s 0 0 is R W E BLE BHE output Other than CAS RAS Aie Do Az3 D7 STO ST1 the above As Ds Ais Di5 R W E BLE BHE P104 P10s Aie Do Az3 D7 STO ST1 As Ds Ais Di5 R W E BLE BHE Accessing MAo MA 7 DRAM area 14 4 7721 Group User s Manual DRAM CONTROLLER 14 2 Block description 14 2 2 Refresh timer The refresh timer is an 8 bit timer with a reload register and is used to ge
202. Overview 7 1 Overview The M37721 provides 23 interrupt sources to generate interrupt requests Figure 7 1 1 shows the interrupt processing sequence When an interrupt request is accepted a branch is made to the start address of the interrupt routine set in the interrupt vector table addresses FFCE e to FFFF e Set the start address of each interrupt routine to the corresponding interrupt vector address in the interrupt vector table Interrupt routine Interrupt processing RTI instruction Fig 7 1 1 Interrupt processing sequence TD 7721 Group User s Manual INTERRUPTS 7 1 Overview When an interrupt request is accepted the following registers contents just before acceptance of an interrupt request are automatically pushed onto the stack area O gt in that order Program bank register PG Program counter PCL PCu Processor status register PSL PS Figure 7 1 2 shows the state of the stack area just before entering the interrupt routine Execute the RTI instruction at the end of this interrupt routine to return to the routine that the microcomputer was executing before the interrupt request was accepted By executing the RTI instruction the register contents pushed onto the stack area are pulled Q OQ in that order Then the suspended processing is resumed from where it left off Stack area Address S 5 S 4 Processor status register s low order byte PSL S 3 Processo
203. Po a L EE 17 50 7721 Group Users Manual APPENDIX Instructions Ine ins Appendix 6 Mach Processor status register Addressing modes o 2 gt wy D E o O D o A And the other cases are no Value saved in stack 17 51 7721 Group User s Manual APPENDIX Appendix 6 Machine instructions Addressing modes Symbol Functions Details A DIR DIR DIR X DIR Y DIR DIR X mE efe efre SEB Mbe 1 Makes the contents of the specified bit in the memory 1 04 3 Note 5 PSb lt 1 Set the specified bit of the processor status register s lower E2 3 2 byte PSL to 1 M lt Acc Stores the contents of the accumulator into the memory Note 1 9 oo N J co N 2 sP Stops the oscillation of the oscillator plsi I Stores the contents of the index register X into the memory DERREN e C e evene Stores the contents of the index register Y into the memory the contents of the index register Y into the memory DERREN DPR lt A Transmits the contents of the accumulator A to the direct 5B 2 1 page register ee Transmits the contents of the accumulator A to the stack pointer aeh X A Transmits the contents of the accumulator A to the index JAA 2 1 register X TAY YA Transmits the contents of the accumulator A to the index JA8 2 1 register Y TBD DPR B Transmits the contents o
204. Processor interrupt priority level Fig 2 1 1 CPU registers structure DD 7721 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 2 1 1 Accumulator Acc Accumulators A and B are available 1 Accumulator A A Accumulator A is the main register of the microcomputer The transaction of data such as calculation data transfer and input output are performed mainly through accumulator A It consists of 16 bits and the low order 8 bits can also be used separately The data length flag m determines whether the register is used as a 16 bit register or as an 8 bit register When an 8 bit register is selected only the low order 8 bits of accumulator A are used and the contents of the high order 8 bits is unchanged 2 Accumulator B B Accumulator B is a 16 bit register with the same function as accumulator A Accumulator B can be used instead of accumulator A The use of accumulator B however except for some instructions requires more instruction bytes and execution cycles than that of accumulator A Accumulator B is also controlled by the data length flag m just as in accumulator A 2 1 2 Index register X X Index register X consists of 16 bits and the low order 8 bits can also be used separately The index register length flag x determines whether the register is used as a 16 bit register or as an 8 bit register When an 8 bit register is selected only the low order 8 bits of index register X are
205. R A 8 2 Block description 8 2 2 Count start register This register is used to start and stop counting Each bit of this register corresponds to each timer Figure 8 2 2 shows the structure of the count start register b7 b6 b5 b4 b3 b2 bi b0 Count start register Address 4016 Cm serene rm Tee K Timer A0 count start bit T Stop counting Start counting KN Timer A1 count start bit Timer A2 count start bit S Timer Bt count start bit Bits 5 to 7 are not used for Timer A Fig 8 2 2 Structure of count start register 7721 Group User s Manual 8 5 TIMER A 8 2 Block description 8 2 3 Timer Ai mode register Figure 8 2 3 shows the structure of the timer Ai mode register The operating mode select bits are used to select the operating mode of Timer Ai Bits 2 to 7 have different functions according to the operating mode These bits are described in the paragraph of each operating mode b7 b6 b5 b4 b3 b2 bl bO Timer Ai mode register i 0 to 4 Addresses 5616 to 5A16 Cm me res ea Operating mode select bits b1 bO 00 Timer mode 0 1 Event counter mode 1 1 0 One shot pulse mode 1 1 Pulse width modulation PWM mode Fig 8 2 3 Structure of timer Ai mode register 8 6 7721 Group User s Manual TIMER A 8 2 Block description 8 2 4 Timer Ai interrupt control register Figure 8 2 4 shows the structure of the timer Ai interrupt control register For details about in
206. RH LL 20 4 8920 5 OF 89 19 4 89 aa eoa 1814 ABS ABS b ABS X ABS Y ABL 20 89 0D J EE ET Eo xr m ze S do EL L S L L S IS e L S S SA T E ae a 3E CL j G A 5 F p 24 3 89 17 S 17 47 7721 Group User s Manual APPENDIX Appendix 6 Machine instructions Addressing modes Symbol Functions Details S e DPRu Saves the contents of the direct page register into the sos 1 stack S DPR ed 1 S e PSu Saves the contents of the program status register into the Ar 1 stack M S PS 1 Saves the contents of the index register Y into the stack Restores the contents of the stack on the accumulator A Restores the contents of the stack on the accumulator B Restores the contents of the stack on the direct page reg ister Restores the contents of the stack on the processor status register PLT S lt S 1 Restores the contents of the stack on the data bank reg DT lt M S ister PLX Restores the contents of the stack on the index register X 17 48 7721 Group User s Manual APPENDIX Instructions Ine ins Appendix 6 Mach Processor status register Addressing modes 17 49 7721 Group User s Manual APPENDIX Appendix 6 Machine instructions Addressing modes Symbol Functions Details we wm 4 om om orx iay oro Restores the contents of the stack on the index register Y PSH Saves the re
207. ROR A DEX DEX DEX BNE LOOP 1 STA A DEST Y SEM DATA 8 STA B DEST 2 Y CLM DATA 16 DEY DEY DEY BNE LOOPO SOUR DEST Work areas 2 2 7721 Group User s Manual 17 77 APPENDIX Appendix 9 7721 Group Q amp A Watchdog timer When detecting the software runaway by the watchdog timer if the same value as the contents of the reset vector address is set to the watchdog timer interrupt vector address not performing software reset how does it result in When branching to the reset branch address within the watchdog timer interrupt routine how does it result in The CPU registers and the SFR are not initialized in the above mentioned way Accordingly the user must initialize all of them by software Note that the processor interrupt priority level IPL retains 7 of the watchdog timer interrupt priority level and is not initialized Consequently all interrupt requests cannot be accepted When rewriting the IPL by software save once the 16 bit immediate value to the stack area and then restore that 16 bit immediate value to all bits of the processor status register PS When a software runaway occurs we recommend to use software reset in order to initialize the microcomputer 17 78 7721 Group User s Manual APPENDIX Appendix 10 Differences between 7721 Group and 7720 Group Appendix 10 Differences between 7721 Group and 7720 Group Table 2 Differences between M37721S2BFP and M37720S1AFP Item M37721S2B
208. Register Y 16 4 esee 5 a KS J J o 9 u Index Register X 16 ijelsirig 3A o e e ao E 9 5 o o olls a Accumulator B 16 EVE El EWE lt EE E E F D x 2 ue 4 Accumulator A 16 uio 2 Pid Bo 5 gt SA s 2 ou Oc wv o 8 2 Ed a 2 8 p x 8 5 2 o Arithmetic Logic o E Unit 16 AX 8 m O O 52 E 3t x E o 9 O Note For the M37721S1BFP the RAM size is 512 bytes Fig 1 4 1 M37721 block diagram 7721 Group User s Manual 1 7 DESCRIPTION 1 4 Block diagram MEMORANDUM 1 8 7721 Group User s Manual CHAPTER 2 CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 2 2 Bus interface unit 2 3 Access space 2 4 Memory assignment 2 5 Bus access right CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 2 1 Central processing unit The CPU Central Processing Unit has the ten registers as shown in Figure 2 1 1 b15 b8 b7 b0 b15 b8 b7 b0 iint b15 b8 b7 bO b15 b8 b7 bO b15 b8 b7 bO b7 bO Data bank register DT b23 b16 b15 b8 b7 bO b7 b0 Ku R70 707007 Program bank register PG b15 b8 b7 b0 b15 b8 b7 b0 PSH PSL Processor status register PS b15 bl0 b8 b7 b6 b5 b4 b3 b2 bi bo ojojojojo mt jNjV m x D I Z C Carry flag Zero flag Interrupt disable flag Decimal mode flag Index register length flag Data length flag Overflow flag Negative flag
209. Ri latch DMAACKi DMA latch e When transferring from I O to memory DMAC Memory SARI Transfer source address is specified by DARi Note Contents of TCRi are updated by decrementer Note SARI latch when value read from TCRi is 0 transfer of 1 data ncrementer H Transfer block is terminated destination 9 Contents of DARi are updated by incrementer DARi decrementer pend I O is specified by DMAACKI Data is output from I O and is written to memory Q TCRi simultaneously R W L level TCRi latch I O DMAACKi Transfer DMA latch source When the transfer unit is 16 bits the incrementer decrementer and the decrementer increment or decrement by 2 Note In the single transfer mode and repeat transfer mode only at the first transfer of the block the values read from SARi latch DARi latch and TCRi latch are used The results obtained by increment or decrement are written to SARi DARi and TCRi Except for the first transfer of the block the values read from SARi DARi and TCRi are used Fig 13 4 6 Basic operation of registers for 1 unit transfer in 1 bus cycle transfer 13 40 7721 Group User s Manual DMA CONTROLLER 13 4 Operation 2 Bus operation in 1 bus cycle transfer The time required for 1 unit transfer in 1 bus cycle transfer is given by the following formulas e Transfer from memory to I O Transfer time per 1 unit transfer Read cycle of me
210. Setting of real time outpull J J J U U U U u 10 7 10 4 Real time output operation L J eere nennen nnn 10 10 CHAPTER 11 SERIAL I O 11 1 Overview cc error eu er ru rr rrr nne he U U nr 11 2 11 2 Block descriptionL eec eeeeer erneuern nennen nnne 11 3 11 2 1 VARI transmit receive mode register ee 11 4 OMM 11 13 11 14 O 11 17 m M 11 18 11 21 M E 11 23 n S E E 5 D 11 27 u n ties 11 29 t 11 30 C U OROL 11 4 3 Method of transmissionl mmm 11 34 V V 11 38 11 41 11 4 6 Receive operation l nettement tna 11 44 n 11 46 UR E EIS sh 11 47 IV 7721 Group User s Manual Table of contents CHAPTER 12 A D CONVERTER 12 2 de eidfelal RETOUR TE 12 3 A D control reaisterL eseseeee rnm m Hmmm Imm RR 12 4 12 2 2 A D sweep pin select register 12 2 3 A D register i i 0 10 7 usesretesits uisu tese aduer aES e zk ea RE x Erbe e tratar deb
211. Single transfer mode through section 13 8 Link array chain transfer mode 1 Transfer source wait bit and Transfer destination wait bit bits 4 and 5 When each of these bits is set to 1 1 bus cycle in a DMA transfer consumes 3 cycles of and when cleared to 0 2 cycles of 9 These bits are valid for the internal and external areas In the DRAM area however 1 bus cycle consumes 3 cycles of regardless of the states of these bits Refer to CHAPTER 14 DRAM CONTROLLER The wait bit bit 2 at address 5E e is invalid in DMA transfer However Ready function is still valid in DMA transfer DMAO mode register H Address 1FCD 6 b7 b6 b5 b4 b3 b2 bl EET hss aes aes EER DMA3 mode H Address 1FFDt e Bitname name Functions At reset reset RW Cima direction select bit 0 MC memory to I O mw Used in 1 bus cycle transfer Note 1 1 From I O to memory I O connection select bit Refer to below RW Valid in 1 bus cycle transfer 2 Fi these bits to 0 Continuous transfer mode select b7b6 bits 0 0 Single transfer 0 1 Repeat transfer 1 0 Array chain transfer 1 Link array chain transfer Notes 1 Set bit 0 to 0 in 2 bus cycle transfer 2 Bits 4 and 5 are valid to the external and internal areas However DRAM area is always handled with Wait regardless of the contents of these bits The wait bit bit 2 at address 5E e is invalid in DMA transfer Setting for I O connection
212. TP03 pulse output data bit Undefined WO Valid in pulse mode 1 4 RrP 0 RTPtopulseoutputdatabit output RTPtopulseoutputdatabit bit Undefined WO RTP11 pulse output data bit Undefined WO m Za RTP12 pulse output data bit Undefined WO RTP13 pulse output data bit Undefined WO Note Use the LDM or STA instruction for writing to this register Fig 10 2 2 Structure of pulse output data registers 0 and 1 7721 Group User s Manual 10 5 REAL TIME OUTPUT 10 2 Block description 10 2 3 Port P6 direction register The pulse output pins are shared with port P6 When using these pins as pulse output pins of real time output set the corresponding bits of the port P6 direction register to 1 to set these ports for the output mode Figure 10 2 3 shows the relationship between the port P6 direction register and the pulse output pins b7 b6 b5 b4 b3 b2 bi Port P6 direction register Address 1016 C ee mm foe RTPOo pin 0 Input mode 1 Output mode 1 TPO pi I n When using these pins as pulse RIP0a pin output pins set the corresponding O nw pe pe Ce aro FEET o w Note When setting these bits to 0 the corresponding pins serve as input port floated regardless of the state of the waveform output select bits bits 0 and 1 at address 6216 Fig 10 2 3 Relationship between port P6 direction register and pulse output pins After reset the state of the por
213. The number of cycles increments by 2 when branching The operation code on the upper row is used for branching in the range of 128 to 127 and the operation code on the lower row is used for branching in the range of 32768 to 32767 When handling 16 bit data with flag m 0 the byte in the table is incremented by 1 Type of register A B X Y DPR DT PG PS Number of cycles The number of cycles corresponding to the register to be pushed are added The number of cycles when no pushing is done is 12 i1 indicates the number of registers among A B X Y DPR and PS to be saved while i indicates the number of registers among DT and PG to be saved Type of register A B X Y DPR DT PS The number of cycles corresponding to the register to be pulled are added The number of cycles when no pulling is done is 14 i1 indicates the number of registers among A B X Y DT and PS to be restored while i221 when DPR is to be restored The number of cycles is the case when the number of bytes to be transferred is even When the number of bytes to be transferred is odd the number is calculated as 7 i2 X 7 4 Note that i 2 shows the integer part when i is divided by 2 The number of cycles is the case when the number of bytes to be transferred is even When the number of bytes to be transferred is odd the number is calculated as 9 i 2 X 7 5 Note that i 2 shows the integer p
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215. User s Manual 17 79 APPENDIX Appendix 11 Electrical characteristics Appendix 11 Electrical characteristics The electrical characteristics of the M37721S2BFP are described below For the latest data inquire of addresses described last xx CONTACT ADDRESSES FOR FURTHER INFORMATION Absolute maximum ratings Symbo Parameter Conditions Ratings Unit Voc 0 3 to 7 V AVcc d M 0 3 to 7 V Vi Input voltage RESET CNVss BYTE 0 3 to 12 V Vi Input voltage As Ds As Dis AulDc AcsiDz P43 P47 P5o P5 P6o P67 P7o P7 P80 P87 P90 P97 0 3 to Vec 0 3 P10c P107 RDY HOLD Xin Vner Vo Output voltage Ao MAo A MA As Ds A 5 Dis Aie Do Az23 D7 P43 P 47 P5o P5 P60 P67 P7o P77 P80 P87 P9o P9 P10c P107 0 3 to Vec 0 3 1 RESETour Xour E STO ST1 ALE BLE BHE R W Pa Power dissipation Ta 25 C mW Topr Operating temperature uw 20 to 85 C Tstg Storage temperature ws 40 to 150 eC 17 80 7721 Group User s Manual APPENDIX Appendix 11 Electrical characteristics Recommended operating conditions Vcc 5 V 10 96 Ta 20 to 85 C unless otherwise noted Symbol Vcc AVcc Vss AVss Vin Vin VIL VIL lou peak lou avg lot peak lot avg f XiN Notes 1 2 zn Analog power source voltage y Vc Power source voltage O0 Analog power source voltage O0 H
216. Vcc 5 V 10 Vss 0 V Ta 20 to 85 C Symbol Calculation formula Unit td AL E 1 X 10 td AM E 25 ns ld AH E f Xin Tw ALE 1 X 10 1 n Xin E s td BLE E 1 x 10 ta BHE E 20 ns ta R W E f Xin th E AL 1 x 10 th E AM Xin ns h E DLQ 1 X 10 th e 22 h E DHQ Xin ns tpzx E DLZ 1 x 10 tpzx E DHZ Xin 20 ns th E BLE 9 th E BHE E 22 ns th E R W f Xin twED Transfer source Transfer 2 X 10 _ 95 11 4 Ns destination wait bit 1 f XiN Transfer source Transfer 4x10 25 ae destination wait bit 0 f Xin ne 2 X 10 ns f XiN ds Ao MAo A7 MA7 As Ds A15 D15 A16 Do A23 D7 P4 P5 P6 P7 Fig 13 Test circuit for each pin Fig 14 Test circuit for TC output delay time and TC output pulse width 17 106 7721 Group User s Manual APPENDIX Appendix 12 Standard characteristics Appendix 12 Standard characteristics Standard characteristics described below are just examples of the M37721S2BFP s characteristics and are not guaranteed For each parameter s limits refer to section Appendix 11 Electrical characteristics 1 Programmable I O port CMOS output standard characteristics 1 P channel lor Vor characteristics 30 0 24 0 18 0 Ta 85 C loH mA 12 0 6 0 1 0 2 0 3 0 4 0 5 0 VoH V 2 N channe
217. When reception is started the RTSi pin s output level becomes H Accordingly by connecting the RTS pin to the CTSi pin of the transmitter side the timing of transmission and that of reception can be matched When an internal clock is selected do not use the RTS function It is because the RTS output becomes undefined Figure 11 3 10 shows a connection example The receive operations are described below The input signal of the RxDi pin is taken into the most significant bit of the UARTi receive register synchronously with the rising edge of the transfer clock The contents of the UARTI receive register are shifted by 1 bit to the right Steps and are repeated at each rising edge of the transfer clock When 1 byte data is prepared in the UARTi receive register the contents of this register are transferred to the UARTi receive buffer register Simultaneously with step the receive complete flag is set to 1 and a UARTi receive interrupt request occurs and its interrupt request bit is set to 1 The receive complete flag is cleared to 0 when the low order byte of the UARTI receive buffer register is read out The RTSi pin outputs H level until the receive conditions are next satisfied when selecting the RTS function Figure 11 3 11 shows the receive operation and Figure 11 3 12 shows an example of receive timing when selecting an external clock Transmitter side Heceiver side
218. When writing gt tw EL 135 min ri X Y tw RASH 60 min tw RASL 120 min RAS lt gt tw CASL 55 min CAS td E CASL 80 115 td R W E 20 min gt lt gt R W J gt lt AC32 tPHL gt AC32 tPHL E tWCS 0 min tWCH 15 min W lt gt lt gt td RA RAS 5 min th RAS RA 18 min lt gt lt TECA CAS 10 min th CAS CA 60 min di A16 Do Y tDH 15 min Y th E DLQ 18 min Specifications of M5M44800CJ 7 The others are specifications of M37721 Unit ns Fig 16 1 21 Timing chart for example of M5M44800CJ 512K X 8 bits connection external bus width 8 bits 7721 Group User s Manual 16 25 APPLICATION 16 1 Memory connection 4 Example of DRAM connection external bus width 8 bits M37721 M5M417800CJ 7 1 Make sure that the propagation delay time is within 80 ns 2 Make sure that the propagation delay time is within 15 ns P gt gt gt gt Memory map 00000016 gt 00008016 Internal 00047F s RAM area Not used 001FCO016 SFR 001FFF16 ae gt gt A16 Do A17 D1 Ais D2 A19 D3 A20 D4 A21 D5 d A22 D6 d OE DRAM area M5M417800CJ FFFFFF e Not used Circuit condition DRAM area select bits bits 3 to 0 at address 6416 00102 Fig 16 1 22 Example of M5M417800CJ
219. a copy delay time ta data M37721 Data bus Ds D15 p Pee Data bus Do D7 Even address woy Memory Note Data is copied from data bus Do D7 to Ds D15 or from data bus Ds D15 to Data bus Do D in the M37721 s DMAC Note the data copy delay time td data 16 bits De Dis 9 bits M37721 Data bus Ds D15 Data bus Do D7 Odd address Data bus Even address 8 bits Do D7 8 bits and Data bus Do D7 Odd address Note When the memory is the internal memory or SFR the above case for external data bus width 16 bits applies 7721 Group User s Manual 13 43 DMA CONTROLLER 13 4 Operation Table 13 4 7 Outputs of address bus data bus and bus control signals in 1 bus cycle transfer Output of address bus data bus and bus control signals External Read Write Transferred from memory to I O Transferred from I O to memory Qala b I O Transfer connection unit address of E width memory HL R W L ees Cere ED ES address dada address Data bus Even rasis y Biondi A16 Do A23 D7 Cu m y Transfer destination V 16 bits Do D7 16 bits address address daa __ and ane BHE De Dis Odd address L L LE L L Transf ransfer destination sopa zee tua mem s Even address _ diiit Q address address SHE H J e o BLE L L 16 bits Data bus 8 bits Transf nae it ransfer destination Transfer source ransfer destination N N L odg ADe uum address
220. a formats in each operating mode 11 2 7721 Group User s Manual SERIAL I O 11 2 Block description 11 2 Block description Figure 11 2 1 shows the block diagram of Serial I O Registers relevant to Serial I O are described below Data bus odd Data bus even UARTiI receive fo fo 0 0 0 0 0 b 2Ps bs o ps be o oe kurer register RxDi C UARTI receive register BRG count source 1 Receive Transfer clock select bits Clock control circuit f2 o synchronous fie O s B 3 iis I UART f512 o Clock synchronous Transmit control n Transfer clock circuit Clock synchronous internal clock selected UARTi transmit register transmit UARTi transmit register Clock synchronous Clock So oi internal clock selected external clock selected PO oo CLKi O dd CTSi RTSi O EN bus odd n Values set in UARTi baud rate register BRGi U Fig 11 2 1 Block diagram of Serial I O 7721 Group User s Manual 11 3 SERIAL I O 11 2 Block description 11 2 1 UARTI transmit receive mode register Figure 11 2 2 shows the structure of UARTi transmit receive mode register The serial l O mode select bits are used to select a UARTi s operating mode Bits 4 to 6 are described in section 11 4 2 Transfer data format and bit 7 is done in section 11 4 8 Sleep mode b7 b6 b5 b4 b3 b2 bli UARTO transmit receive mode register Address 3016 UART1 transmit r
221. a xux RP r kt spr S bred ur bars 12 7 12 2 4 A D conversion interrupt control reqisterl mene 12 8 12 2 5 Port P7 direction reqisterl a eua trie crunt re Bets 12 9 T 12 10 12 4 Absolute accuracy and differential non linearity errorL 12 12 osolute a ded e ia un um unas ananassa 12 12 12 4 2 Differential non linearity errorl rr 12 13 Fans nn 12 14 12 14 12 5 2 One shot mode operation descriptionl 12 16 _ sassa sassa sa sassa sas sasan sassa sassa sassssasassa sas sasassasas sassa o 12 6 1 Settings for repeat mode 12 6 2 Repeat mode operation description 12 7 Single sweep model eere U U U u l lity T JI aa aaaaaaa 12 20 12 7 2 Single sweep mode operation descriptionl 12 22 B Repe p O 12 24 uE uuu uns 12 24 3 2 Renea yeep mode opera OTM MORTE 12 26 ie ce REIR RE 12 28 CHAPTER 13 DMA CONTROLLER I o S
222. able 13 3 3 lists the conditions for changing the DMAi request bit For the timing of changing the DMAi request bit refer to Figures 13 3 2 and 13 3 3 Table 13 3 3 Conditions for changing DMAi request bit Burst transfer mode DMAi Cycle steal transfer mode Is set to 1 Generation of DMAi request Generation of DMAi request Generation of DMAi request Note Refer to Table 13 3 2 L level input to the Refer to Table 13 3 2 DMAREQi pin Is cleared to 0 Normal termination H level input to the Start of 1 unit transfer Changgol Nay pin s Input PHAREQI pin Change of the TC pin s input level from H to L during Change of the TC pin s input level from H to L during DMA transfer when the TC aver from H to L when DMA transfer when the TC pnis valo the TC pin is valid pin is valid A write of 0 to the DMAi A write of 0 to the DMAI request bit request bit A write of 0 to the DMAi A write of 0 to the DMAi enable bit enable bit Note While the DMAi enable bit is 0 the DMAi request bit is not set to 1 even if a DMA request is generated When the DMAi enable bit is cleared to 0 also the DMAi request bit is cleared to 0 However the DMA request generated while the DMAi enable bit 0 is maintained and when the DMAi enable bit is set to 1 the DMAi request bit is also set to 1 except for the burst trans
223. able within 1 cycle of oap 2 his resistor and thermistor are used to divide resistance Fig 7 Countermeasure example against noise for analog input pin using thermistor 7721 Group User s Manual 17 61 APPENDIX Appendix 8 Countermeasure against noise 2 Processing for analog power source pins etc Use independent power sources for the Vcc AVcc and Vrer pins Insert capacitors between the AVcc and AVss pins and between the Vrer and AVss pins Reasons Prevents the A D converter from noise on the Vcc line M37721 Reference values C1 2 0 47 uF C2 2 0 47 uF Note Connect capacitors using the thickest shortest wiring possible sensor etc Fig 8 Processing for analog power source pins etc 17 62 7721 Group User s Manual APPENDIX Appendix 8 Countermeasure against noise 4 Oscillator protection The oscillator which generates the basic clock for the microcomputer operations must be protected from the affect of other signals 1 Distance oscillator from signal lines with large current flows Install the microcomputer especially the oscillator as far as possible from signal lines which handle currents larger than the microcomputer current value tolerance Reason The microcomputer is used in systems which contain signal lines for controlling motors LEDs thermal heads etc Noise occurs due to mutual inductance when a large current flows through the signal lines M37721 m Mut
224. abling b7 b6 b5 b4 b3 b2 bi bO DMAC control register H Address 6916 Valid when software DMA source The value is 0 atreading Software DMAS request bit DMAO enable bit 0 Disabled 1 Enabled DMA enable bit EN DMA2 enable bit DMA3 enable bit Note When any of bits 4 to 7 is set to 1 use the CLB or SEB instruction for writing to this register Fig 13 2 5 Structure of DMAC control register H 7721 Group User s Manual 13 11 DMA CONTROLLER 13 2 Block description 13 2 4 Source address register i SARi Source address register i hereafter called SARi is a 24 bit register with a latch SARi indicates the transfer source address of the data to be transferred next The SARi latch has the following functions Maintains the value written to the address of SARi in the single transfer and repeat transfer modes e Indicates the start address of the transfer parameter memory of the next block in the array chain transfer and link array chain transfer modes When a value is written into the address of SARI the same value is written into SARi and the SARi latch When writing a value to the address of SARi all 24 bits must be written The contents of SARi can be read by reading the address of SARi however the value of the SARi latch cannot be read Refer to Tables 13 2 4 and 13 2 5 13 2 5 Destination address register i DARi Destination address register i hereafter called DARI is a 24 bit regi
225. according to selection of odd even parity in such a way that the sum of 1 s in this bit and character bits is always an odd or even number SP H level signal equivalent to 1 or 2 character bits which is added immediately after Stop bit the character bits or parity bit when parity is enabled It indicates finish of data transmission 7721 Group User s Manual 11 33 SERIAL I O 11 4 Clock asynchronous serial I O UART mode 11 4 3 Method of transmission Figure 11 4 3 shows an initial setting example for relevant registers when transmitting The difference due to selection of transfer data length 7 bits 8 bits or 9 bits is only that data length When selecting a 7 or 8 bit data length set the transmit data into the low order byte of the UARTI transmit buffer register When selecting a 9 bit data length set the transmit data into the low order byte and bit O of the high order byte Transmission is started when all of the following conditions to are satisfied Transmit is enabled transmit enable bit 1 Transmit data is present in the UARTi transmit buffer register transmit buffer empty flag O The CTSi pin s input is at L level when the CTS function selected Note When the CTS function is not selected condition is ignored By connecting the RTSi pin receiver side and CTSi pin transmitter side the timing of transmission and that of reception can be matched For details
226. agram are as follows Signal levels The upper line indicates 1 and the lower line indicates 0 Input output levels of pin The upper line indicates H and the lower line indicates L For the exception the level is shown on the left side of a signal 4 Register structure Below is the structure diagram for all registers x b7 b6 b5 b4 b3 b2 bf XXX register Address XX16 x3 Ld Ee Pp E lI select bit flag 0 pe ae a This bit is invalid in mode AP o mw Blank Set to 0 or 1 according to the usage 0 Set to 0 at writing 1 Set to 1 at writing x Invalid depending on the mode or state It may be 0 or 1 Nothing is assigned 2 0 0 immediately after reset 1 1 immediately after reset Undefined Undefined immediately after reset 3 RW It is possible to read the bit state at reading The written value becomes valid RO It is possible to read the bit state at reading The written value becomes invalid Accordingly the written value may be 0 or 1 WO The written value becomes valid It is impossible to read the bit state The value is undefined at reading However when 0 at reading is indicated in the Function or Note column the bit is always 0 at reading See 4 above It is impossible to read the bit state The value is undefined at reading However when 0 at reading
227. al Read signal td E RASL a ie Row address td E CA lpzx E DLZ DHZ Address output and Data I O A8 D8 A15 D15 Y 4 Address A16 Do A23 D7 lt gt tOEZ k2 DRAM data output Data l l l l tsu DL DH E 1 This applies when the external data bus has a width of 16 bits BYTE L 2 If one of DRAM s specifications is greater than tpzx E DLZ DHZ there is a possibility that the tail of data collides with the head of address Refer to section 3 Precautions on Specifications of the M37721 memory connection The others are specifications of DRAM Note tpzx E DLZ DHZ tpzx E DLZ Or tpzx E DHZ tsu DL DH E tsu DL E or tsu DH E Fig 16 1 3 Timing for reading data from DRAM CAS access time tcac RAS access time trac Column address access time taa lt twet taE cA tsu DL DH E OE access time tora lt tw EL tsu DL DH E tw EL ta E CAsL tsu DL DH E lw EL IA IA EL ta E RAsL tsu DL DH E Table 16 1 3 lists the calculation formula and value for each parameter in Figure 16 1 3 Figure 16 1 4 shows the relationship between tcac trac taa and f Xin 16 6 7721 Group User s Manual APPLICATION 16 1 Memory connection Table 16 1 3 Calculation formula and Value for each parameter in Figure 16 1 3 unit ns sss Calculation formula and Value tw EL 4X 10 25
228. al DMA CONTROLLER 13 7 Array chain transfer mode 13 7 Array chain transfer mode This mode is used to transfer several blocks of data According to the information of each block stored in memory area Note several blocks of data are transferred All of the transfer parameters must be located in series Table 13 7 1 lists the specifications of the array chain transfer mode and Figure 13 7 1 shows the register structures of SARi DARi and TCRi in this mode Note Each of the following information is called transfer parameter transfer start addresses of transfer source and destination and transfer data s byte number Table 13 7 1 Specifications of array chain transfer mode ltem Transfer parameter memory Condition of normal termination Conditions of forced termination Interrupt request generation timing Functions of registers Performance specifications Required In 2 bus cycle transfer 12 bytes per one block transfer source s transfer start address transfer destination s transfer start address transfer data s byte number In 1 bus cycle transfer 8 bytes per one block from memory to I O transfer source s transfer start address transfer data s byte number from I O to memory transfer destination s transfer start address transfer data s byte number TCRi latch 0 and TCHi 0 e Falling edge of the TC pin s input from H to L when the TC pin validity bit 1 Write 0 to the DMAi ena
229. am runaway and the most significant bit of Watchdog timer becomes 0 This means that a program runaway has occurred In order to reset the microcomputer when a program runaway is detected write 1 to the software reset bit bit 3 at address 5E e in the watchdog timer interrupt routine Main routine Watchdog timer register a 8 bit dummy data Watchdog timer initialized Address 6016 Value of watchdog timer FFF16e Note 1 Watchdog timer interrupt request occur program runaway detected Watchdog timer interrupt routine Software reset bit 1 Note 2 Address 5Ete b3 Reset microcomputer Notes 1 Initialize Waichdog timer before the most significant bit of Watchdog timer becomes 0 Write dummy data to address 6016 before a watchdog timer interrupt request occurs 2 When a program runaway occurs values of the data bank register DT direct page register DPR etc may be changed When 1 is written to the software reset bit by the addressing mode using DT DPR etc set values to DT and DPR again Fig 15 2 1 Example of program runaway detection by Watchdog timer 7721 Group User s Manual 15 5 WATCHDOG TIMER 15 2 Operation description 15 2 2 Stop period Watchdog timer stops operation in the following period Hold state Refer to section 3 4 Hold function During DMAC operation Refer to CHAPTER 13 DMA CONTROLLER During DRAM refresh Refer to CHAPT
230. ample for registers relevant to repeat mode 12 18 7721 Group User s Manual A D CONVERTER 12 6 Repeat mode 12 6 2 Repeat mode operation description 1 When an internal trigger is selected The A D converter starts operation when the A D conversion start bit is set to 1 The first A D conversion is completed after 57 cycles of 4 Then the contents of the successive approximation register conversion result are transferred to the A D register i The A D converter repeats operation until the A D conversion start bit is cleared to O by software The conversion result is transferred to the A D register i each time the conversion is completed 2 When an external trigger is selected The A D converter starts operation when the input level to the ADtra pin changes from H to L while the A D conversion start bit is 1 The first A D conversion is completed after 57 cycles of 4 Then the contents of the successive approximation register conversion result are transferred to the A D register i The A D converter repeats operation until the A D conversion start bit is cleared to 0 by software The conversion result is transferred to the A D register i each time the conversion is completed When the level of the ADtra pin changes from H to L during operation the operation at that point is cancelled and is restarted from step Figure 12 6 2 shows the conversion opera
231. and internal RAM areas immediately after reset 4 4 8 7721 Group User s Manual RESET 4 1 Hardware reset Address Register name E Access characteristics m tate immediately after reset pa 1FC016 1FC116 Source address register 0 1FC216 1FC316 1FC416 1FC516 Destination address register 0 1FC616 1FC716 1FC816 1FC916 Transfer counter register O 1FCA16 1FCBt16 1FCCt16 DMAO mode register L 1FCD16 DMAO mode register H 1FCE16 DMAO control register 1FCFt16 1FD016 1FD116 Source address register 1 1FD216 1FD316 1FD416 1FD516 Destination address register 1 1FD616 1FD716 1FD816 1FD916 Transfer counter register 1 1FDAt6 1FDBt16 1FDC16 DMA1 mode register L 1FDD16 DMA1 mode register H 1FDE16 DMA1 control register 1FDF16 Fig 4 1 8 State of SFR and internal RAM areas immediately after reset 5 7721 Group User s Manual 4 9 RESET 4 1 Hardware reset Address Register name Access characteristics tate immediately after reset T 1FE016 1FE116 Source address register 2 1FE216 1FE316 1FE416 1FE516 Destination address register 2 1FE616 1FE716 1FE816 1FE916 Transfer counter register 2 1FEA16 1FEB16 1FEC16 DMA2 mode register L olololo RN 0 0 0 1FED16 DMA2 mode register H 0 0 0 0 RAS 0 O 1FEE16 DMA2 control register L212 0 0 0 0 0 0 1FEF16 1FF016 1FF116 Source address register 3 1FF216 1FF316 1FF416 1FF516 Destination address register 3 1FF616 1FF716 1FF816 1FF916 Transfe
232. ansfer data format for both transmitter and receiver sides Figure 11 4 2 shows an example of transfer data format Table 11 4 5 lists each bit in transmit data Transfer data length of 7 bits 1ST 7DATA 1SP 1ST 7DATA 2SP 1ST 7DATA 1PAR 1SP 1ST 7DATA 1PAR 2SP Transfer data length of 8 bits 1ST 8DATA 1SP 1ST 8DATA 2SP 1ST 8DATA 1PAR 1SP 1ST 8DATA 1PAR 2SP Transfer data length of 9 bits 1ST 9DATA 1SP 1ST 9DATA 2SP ST Start bit 1ST 9DATA 1PAR 1SP DATA Character bit Transfer data 1ST 9DATA 1PAR 2SP PAR Parity bit SP Stop bit Fig 11 4 1 Transfer data format For the case where 18T 8DATA 1PAR 1SP ime K jransmit Receive data gt gt Next transmit receive data DATA 8 bits When continuously transferring st iss Iws mm selsr Fig 11 4 2 Example of transfer data format Table 11 4 5 Each bit in transmit data Name Functions ST L signal equivalent to 1 character bit which is added immediately before the Start bit character bits It indicates start of data transmission DATA Transmit data which is set in the UARTi transmit buffer register Character bit PAR A signal that is added immediately after the character bits in order to improve data Parity bit reliability The level of this signal changes
233. any of bits 4 to 7 1 17 66 7721 Group User s Manual APPENDIX Appendix 9 7721 Group Q amp A Reset STP instruction WIT instruction Is it possible to distinguish power on reset from hardware reset for terminating the stop or wait mode The contents of the internal RAM is undefined after power on reset On the other hand the contents of the internal RAM are retained when performing hardware reset in the stop or wait mode with Vcc gt 2 V Accordingly write a certain data to the internal RAM before executing STP or WIT instruction and judge by checking the contents of the internal RAM after hardware reset 7721 Group User s Manual 17 67 APPENDIX Appendix 9 7721 Group Q amp A Interrupt If an interrupt request b occurs while executing an interrupt routine a is it true that the main routine is not executed at all from when the execution of the interrupt routine a is completed until the execution of the INTACK sequence for the next interrupt b starts Sequence of execution RTI instruction Interrupt routine a gt Main routine INTACK sequence for interrupt b Conditions is cleared to 0 by executing the RTI instruction linterrupt priority level of interrupt b is higher than IPL of main routine Interrupt priority detection time is 2 cycles of 6 sampling for interrupt requests is performed by sampling pulses generated synchronously with the CPU s
234. are i Cleared to 0 by software Set to 1 by software Count start bit Pulse output from TAjour pin Timer Aj interrupt request bit N Z Cleared to 0 when interrupt request is accepted or cleared by software Fig 8 3 6 Example of operation selecting pulse output function 8 16 7721 Group User s Manual TIMER A 8 3 Timer mode Precautions for timer mode By reading the timer Ai register the counter value can be read out at any timing However if the timer Al register is read at the reload timing shown in Figure 8 3 7 the value FFFF e is read out If reading is performed in the period from when a value is set into the timer Ai register with the counter stopped until the counter starts counting the set value is correctly read out Reload cows Ta Taf o CR CES Read value He 2 1 Ferr n t n Reload register s contents Time Fig 8 3 7 Reading timer Ai register 7721 Group User s Manual 8 17 TIMER A 8 4 Event counter mode 8 4 Event counter mode In this mode the timer counts an external signal Refer to Tables 8 4 1 and 8 4 2 Timers A2 to A4 can be used in this mode Figure 8 4 1 shows the structures of the timer Aj mode register and timer Aj register in the event counter mode Table 8 4 1 Specifications of event counter mode when not using two phase pulse signal processing function ltem Count source Count operation Di
235. are available Figure 13 4 8 shows a transfer example in the burst transfer mode edge sense When once a DMA request is accepted in this mode an entire batch of data is transferred the right to use bus is not returned to the CPU until the transfer is complete During a burst transfer any DMA request including that of other channels cannot be accepted However the BUS REQUEST signal is sampled basically at every completion of 1 unit transfer Refer to Table 13 2 3 When a DRAM refresh request or Hold request is generated at this time the right to use bus is not returned to the CPU and the request is accepted When the transfer of an entire batch of data is complete the DMAC relinquishes the right to use bus to the CPU When the next DMA request is generated the right is once returned to the CPU to sample the DMA request Burst transfer mode level sense When the transfer mode select bit 0 and the edge sense level sense select bit 1 this mode is selected Refer to Figures 13 2 6 and 13 2 8 In this mode only the external source is used as a DMA request source Set the DMA request source select bits to 00012 Refer to Figure 13 2 8 Figure 13 4 9 shows a transfer example in the burst transfer mode level sense When the DMAREQi pin s input level L the DMAi request bit is cleared to 0 when this pin s input level L the DMAi request bit is set to 1 Therefore when the DMAREQi p
236. area The internal RAM also functions as the temporary area or the register file which is accessed frequently because the internal RAM can be accessed with no Wait Accordingly it is expected that the capacity will lack to be used as the stack area As for the M37721 DRAM area can be set as the stack area because cheap DRAM can be connected Use bank 0 which is assigned to the internal RAM area as the stack area when DRAM is not connected or the internal RAM is sufficient to be used as the stack area 17 792 7721 Group User s Manual APPENDIX Appendix 9 7721 Group Q amp A DRAM WIT instruction Are there methods to refresh DRAM in the wait mode 7721 Group User s Manual 17 73 APPENDIX Appendix 9 7721 Group Q amp A In the wait mode DRAM refresh function does not operate but the watchdog timer timer A and timer B operate Accordingly DRAM can be refreshed by using these timers and ports 1 Method using watchdog timer Interval of watchdog timer interrupt Return from the wait mode by the watchdog f Xin fs2 selected fs selected timer interrupt Control ports P104 P10s by 25 MHz 2 621 ms 41 943 ms and perform the CAS before RAS 16 MHz 4 096 ms 65 536 ms Example 1 A case in 1024 refresh cycles every 16 4 ms f Xin 16 MHz watchdog timer count source fs2 DRAM refresh is performed 256 times This refresh is performed by every watchdog timer interrupt See flow chart Watchdog timer i
237. ared to 0 when interrupt request is accepted or cleared by software The above figure shows an example of he following conditions Pulse mode 0 selected RTPOo RTPOs selected Timer AO register set value n 000316 Fig 10 4 1 Example of real time output operation 10 10 7721 Group User s Manual CHAP TIER 11 SERIAL I O 11 1 Overview 11 2 Block description 11 3 Clock synchronous serial I O mode Precautions for clock synchronous serial l O mode 11 4 Clock asynchronous serial I O UART mode SERIAL I O 11 1 Overview 11 1 Overview Serial I O consists of 2 channels UARTO and UART1 They each have a transfer clock generating timer for the exclusive use of them and can operate independently UARTO and UART1 have the same functions UARTi i 0 and 1 has the following 2 operating modes 1 Clock synchronous serial I O mode Transmitter and receiver use the same clock as the transfer clock Transfer data has a length of 8 bits 2 Clock asynchronous serial I O UART mode Transfer rate and transfer data format can arbitrarily be set The user can select a transfer data length of 7 bits 8 bits or 9 bits Figure 11 1 1 shows the transfer data formats in each operating mode eClock synchronous serial I O mode Transfer data length of 8 bits UART mode Transfer data length of 7 bits E Transfer data length of 8 bits Transfer data length of 9 bits Fig 11 1 1 Transfer dat
238. art when i is divided by 2 The number of cycles is the case in the 16 bit 8 bit operation The number of cycles is incremented by 16 for 32 bit 16 bit operation The number of cycles is the case in the 8 bit X 8 bit operation The number of cycles is incremented by 8 for 16 bit X 16 bit operation When setting flag x 0 to handle the data as 16 bit data in the immediate addressing mode the number of bytes increments by 1 When flag m is 0 the byte in the table is incremented by 1 17 54 7721 Group User s Manual Symbols in machine instructions table Symbol Symbol lt gt 7 14 52 lt 3 OTFNO Implied addressing mode Immediate addressing mode Accumulator addressing mode Direct addressing mode Direct bit addressing mode Direct indexed X addressing mode Direct indexed Y addressing mode Direct indirect addressing mode Direct indexed X indirect addressing mode Direct indirect indexed Y addressing mode Direct indirect long addressing mode Direct indirect long indexed Y addressing mode Absolute addressing mode Absolute bit addressing mode Absolute indexed X addressing mode Absolute indexed Y addressing mode Absolute long addressing mode Absolute long indexed X addressing mode Absolute indirect addressing mode Absolute indirect long addressing mode Absolute indexed X indirect addressing mode Stack addressing mode Relative addressing mode Direct bit relative addressing mode Absolute bit relative a
239. asures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporati
240. ata input Port P8 direction register s corresponding bit 0 Can be used as an I O port when performing only transmission Transfer clock output Internal External clock select bit 0 Transfer clock input Internal External clock select bit 1 CTS input CTS RTS select bit 0 RTS output CTS RTS select bit 1 Port P8 direction register address 1416 Internal External clock select bit bit 3 at addresses 3016 38 6 CTS RTS select bit bit 2 at addresses 34 e 3C e Note The TxDi pin outputs H level until transmission starts after UARTi s operating mode is selected 11 16 7721 Group User s Manual SERIAL I O 11 3 Clock synchronous serial I O mode 11 3 1 Transfer clock Synchronizing clock Data transfer is performed synchronously with the transfer clock For the transfer clock the user can select whether to generate the transfer clock internally or to input it from the external The transfer clock is generated by operation of the transmit control circuit Accordingly even when performing only reception set the transmit enable bit to 1 and set dummy data in the UARTi transmit buffer register in order to make the transmit control circuit active 1 Internal generation of transfer clock The count source selected with the BRG count source select bits is divided by the BRGi and the BRGi output is further divided by 2 This is the transfer clock The transfer clock is output
241. ata length flag m is 0 the overflow flag is set to 1 when the result of addition or subtraction exceeds the range between 32768 and 3276 7 and cleared to 0 in all other cases When the data length flag m is 1 the overflow flag is set to 1 when the result of addition or subtraction exceeds the range between 128 and 127 and cleared to 0 in all other cases The overflow flag is also set to 1 when a result of division exceeds the register length to be stored in a division instruction DIV When the BVC or BVS instruction is executed this flag s contents determine whether the program causes a branch or not Use the SEP instruction to set this flag to 1 and use the CLV or CLP instruction to clear it to 0 Note This flag is invalid in the decimal mode Bit 7 Negative flag N It is set to 1 when a result of arithmetic operation or data transfer is negative Bit 15 of the result is 1 when the data length flag m is 0 or bit 7 of the result is 1 when the data length flag m is 1 It is cleared to O in all other cases When the BPL or BMI instruction is executed this flag determines whether the program causes a branch or not Use the SEP instruction to set this flag to 1 and use the CLP instruction to clear it to O Note This flag is invalid in the decimal mode Bits 10 to 8 Processor interrupt priority level IPL These three bits can
242. atched For details refer to section 11 3 5 Receive operation When using interrupts it is necessary to set the relevant registers to enable interrupts For details refer to CHAPTER 7 INTERRUPTS Figure 11 3 9 shows processing after receive completion 7721 Group User s Manual 11 23 SERIAL I O 11 3 Clock synchronous serial I O mode UARTO transmit receive mode register Address 3016 UART1 transmit receive mode register Address 3816 b7 bO Clock synchronous serial I O mode Internal External clock select bit 0 Internal clock 1 External clock X It may be 0 or 1 j UARTO transmit receive control register 0 Address 34 6 UART1 transmit receive control register 0 Address 3C 6 b7 bO L BRG count source select bits b1 bO 00 f2 01 f16 10 fe4 1 1 f512 CTS RTS select bit 0 CTS function selected 1 RTS function selected f UARTO baud rate register BRGO Address 31 6 UART1 baud rate register BRG1 Address 39 6 b7 bO L NY aa I Can be set to 0016 to FF16 x Necessary only when an internal clock is selected Continued to Figure 11 3 8 on next page Fig 11 3 7 Initial setting example for relevant registers when receiving 1 11 24 7721 Group User s Manual SERIAL I O 11 3 Clock synchronous serial I O mode From preceding Figure 11 3 7 Port P8 direction register Addres
243. ate the oscillator s oscillation does not stop Accordingly the internal peripheral devices can operate Ready function is valid for the internal and external areas Table 3 3 1 Microcomputer s state in Ready state Item otate Oscillation Operating QcPu Stopped at L Pins Ao to Az As Ds to A1s5 D15 A16 Do to Aezs Dz E R W Retain the state when Ready request was accepted BHE BLE STO ST1 ALE Pins P4s to P47 P5 to P10 Note Pin Q Outputs clock Watchdog timer Operating Note This applies when this functions as a programmable I O port 3 10 7721 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 3 3 Ready function 3 3 1 Operation description The input level of the RDY pin is judged at the falling edge of clock When L level is detected at this point the microcomputer enters Ready state This is called Acceptance of Ready request In Ready state the input level of the RDY pin is judged at every falling edge of clock When H level is detected at this point the microcomputer terminates Ready state at the next rising edge of clock qu Figure 3 3 1 shows timing of acceptance of Ready request and termination of Ready state Refer also to section 16 1 Memory connection for usage of Ready function No Wait RDY pin input level sampling timing Nb Clock 01 Q Q Q A A A D The L level which is input to the RDY pin is accepted so that
244. ated by an interrupt request occurrence or the hardware reset 5 3 1 Stop mode When the STP instruction is executed the oscillator stops oscillating This state is called Stop mode In Stop mode the contents of the internal RAM can be retained intact when Vcc power source voltage is 2 V or more Additionally the microcomputer s power consumption is lowered It is because the CPU and all internal peripheral devices using clocks fz to fs12 stop the operation Table 5 3 1 lists the microcomputer s state and operation in and after Stop mode Table 5 3 1 Microcomputer s state and operation in and after Stop mode Item State in Stop mode ceu Clock 91 f2 to f512 Can operate only in event counter mode State and Operation Stopped Serial I O Can operate only when an external clock is selected 2 DMA controller E DRAM controller Stopped Note g Watchdog timer Stopped Retains the same state in which the STP instruction was executed Operation By interrupt request Supply of ceu and starts after a certain time measured by after terminating occurrence Watchdog timer has passed Stop mode By hardware reset Operates in the same way as hardware reset Note DRAM refresh is not performed because the refresh timer also stops 7721 Group User s Manual CLOCK GENERATING CIRCUIT 5 3 Stop mode 1 Termination by interrupt request occurrence When terminating Stop mode by interrupt request occurrenc
245. ates the transfer start address of data block at the transfer destination DARI Indicates the address of the next transfer destination TCRi latch Indicates the number of transfer bytes TCRi Indicates the number of remaining bytes being transferred TC pin validity bit Bit 1 at address 6816 7721 Group User s Manual 13 61 DMA CONTROLLER 13 6 Repeat transfer mode b23 b16 b15 b8 b7 b0 Addresses 1FC216 to 1FC016 SARO Addresses 1FD216 to 1FD016 SAR1 Addresses 1FE216e to 1FE016 SAR2 Addresses 1FF21e to 1FF016e SAR3 Source address register O Source address register 1 Source address register 2 Source address register 3 I it i i E 23 to 0 Write Undefined RW Set the transfer start address of the source These bits can be set to 00000016 to FFFFFF e Read The read value indicates the source address of data which is next transferred Note When writing to this register write to all 24 bits b23 b16 b15 b8 b7 b0 Addresses 1FC6 6e to 1FC416 Addresses 1FD616 to 1FD416 Addresses 1FE61e to 1FE4416 Addresses 1FF616 to 1FF416 DARO DAR1 DAR2 DAR3 Destination address register O Destination address register 1 Destination address register 2 Destination address register 3 Um Umm Umm mm mm N M L Write Set the transfer start address of the destination a RN These bits can be set to 00000016 to FFFFFFF46 Read The read value indicates the destination a
246. ay time Note 15 ns d AH ALE Address high order output delay time Note 5 ns 4 Waem ALE output delay time amp ge I 45 ao ALE pulse width 1 1 1 11 1 1 1 1 Not 22 ns tee BHE output delaytime o Not 20 ns twee BLE output delay time Note 20 ns tw R Woutputdelay ime Note 20 ns wee output delay ime 4 of 18 ns te a Address low order hold time 1 1 Not 18 J ns thara Address middle order hold time BYTE L 9 ns tea Data high order hold time BYTE L Note 18 ns lpzx E bHz Data high order floating release delay time BYTE L Note 20 ns te am Address middle order hold time BYTE H Note 18 ns te Address high order hold time ns tecta Data low order hold time Not 18 X ns t e 2 Data low order floating release delay time Note 20 ns tes BHE hold time Not 18 X ns teas BLE hold time o 1 Not 18 ns tes R Whodtim Not 18 ns wn E pulse width Not 135 J ns two Data low order setup time after address stabilization Note 130 ns teo Data low order setup time after rising of ALE Note 135 ns two Data high order setup time after address stabilization Note 130 ns two Da
247. b1 bO Operating mode select bits 1 0 Pulse period Pulse width measurement mode Measurement mode select bits Pulse period measurement Interval between falling edges of measurement pulse Pulse period measurement Interval between rising edges of measurement pulse Pulse width measurement Interval from a falling edge to a rising edge and from a rising edge to a falling edge of measurement pulse Do not select TE EE E 4 Nothing is assigned ZEE i 5 Timer Bj overflow flag rf No overflow Undefined ay Note Overflowed b7 b6 roo YQ Count source select bits 00 f 01 fie 10 fea RW 1 1 fs12 Note The timer Bj overflow flag is cleared to 0 at the next count timing of the count source when a value is written to the timer Bj mode register with the count start bit 1 17 26 7721 Group User s Manual APPENDIX Appendix 3 Control registers Processor mode register 0 b7 b6 b5 b4 b3 b2 bl b0 EN Fix this bit to 0 o nw 1 Nothing is assigned 1 The value is 1 at reading 2 Wait bit 0 Software Wait is inserted when RW accessing external area 1 No software Wait is inserted when accessing external area Software reset bit The microcomputer is reset by writing 1 to this bit The value is 0 at reading b5 b4 00 7 cycles of 01 4 cycles of 6 10 2 cycles of 1 Do not select Interrupt priority detection time select b
248. ber of transfer bytes 12 bytes e Third block transfer source s data start address odd transfer destination s data start address odd the number of transfer bytes 14 bytes O 04 044 440404 4 04 0 0 6 1 19 5 2 4 4 3 4 19 62 3 3 4 19 7 4 3 3 4 1 177 cycles 7721 Group User s Manual 13 103 DMA CONTROLLER 13 9 DMA transfer time MEMORANDUM 13 104 7721 Group User s Manual CHAPTER 14 DRAM CONTROLLER 14 1 Overview 14 2 Block description 14 3 Setting for DRAMC 14 4 DRAMC operation 14 5 Precautions for DRAMC DRAM CONTROLLER 14 1 Overview 14 2 Block description 14 1 Overview Table 14 1 1 lists the performance specifications of DRAM controller hereafter called DRAMC Table 14 1 1 Performance specifications of DRAMC ltem Performance specifications DRAM area 0 to 15 Mbytes programmable in a unit of 1 Mbyte Refreshing method CAS before RAS dispersive refreshing Refresh timer 8 bits Multiplexed address pins 10 14 2 Block description Figure 14 2 1 shows the block diagram of DRAMC Registers relevant to DRAMC are described below Refresh request Bus Access controller RAS and CAS Refresh timer U du 1 n 1 generating circuit Bits 0 3 DRAM Address comparator control register A20 A23 Address Address multiplexer MAo MAg Fig 14 2 1 Block diagram of DRAMC 14 2 7721 Group User s Manual DRAM CONTROLLER 14 2
249. bit Note For bits 0 to 2 of the port P4 register nothing is assigned and these bits are fixed to 0 at reading 1 H level Port Pi3 s pin Fig 6 2 3 Structure of port Pi i 4 to 10 register 6 4 7721 Group User s Manual INPUT OUTPUT PINS 6 2 Programmable I O ports Figures 6 2 4 and 6 2 5 show the port peripheral circuits Inside dotted line not included Ports P4s to P4e Direction register Ex Inside dotted line included Data bus Ports P47 P5 1 TA2 in P53 TA3in P5s TA4in P5e TBOm P57 TB1in P82 RxDo P8e RxD1 P9 DMAREQ0O P93 DMAREQ1 P9 DMAREQ2 P97 DMAREQ3 P10o INTo P10 INTi P102 INT2 a ge There is no hysteresis for P82 RxDo and P8e RxDi lt Inside dotted line not included Ports P83 TxDo P8z TxDi P9 DMAACKO P92 DMAACK1 P94 DMAACK2 P9e DMAACK3 P104CAS P10s RAS P106 MAs P107 MAe Inside dotted line included Ports P5o TA2ovr P52 TAS3ovur P54 TA4 our Direction register l ee utput o Port latch O O Data bus PASS SSeS ARS s Y s sy Ports P60 RTPOo to P6z RTP1s Direction register Data bus Timer underflow signal Fig 6 2 4 Port peripheral circuits 1 7721 Group User s Manual 6 5 INPUT OUTPUT PINS 6 2 Programmable I O ports Inside dotted line not included Ports P7o ANo to P7e ANe f Direction register x Port latch I
250. bits can be set to 00000016 to FFFFFF46 T Notes 1 When writing to these registers write to all 24 bits 2 Do not write 00000016 to TCRi Set the dummy data These bits can be set to 00000116 to FFFFFF 6e Zee PPE Addresses 1FC216 to 1FCO 6 Addresses 1FD216 to 1F D016 Addresses 1FE216 to 1FE016 Addresses 1FF216 to 1F F016 Set the start address of transfer parameter memory Wey Ed 3 ram po Transfer counter register 0 Addresses 1FCAte to 1FC816 TCRO Transfer counter register 1 Addresses 1FDA e to 1FD816 TCR1 l Transfer counter register 2 Addresses 1FEAte to 1FE816 TCR2 p Transfer counter register 3 Addresses 1FFA e to 1FF816 TCR3 SARO SAR1 SAR2 SAR3 _ Fig 13 8 4 Initial setting example for registers relevant to link array chain transfer mode 2 7721 Group User s Manual 13 85 DMA CONTROLLER 13 8 Link array chain transfer mode From preceding Figure 13 8 4 a Selection of priority level and TC pin and setting DMAi request bit to 0 B b7 bO o ooo DMAC control register L Address 6816 Priority select bit 0 Fixed 1 Rotating TC pin validity bit 0 Invalid P105 pin functions as a programmable O port 1 Valid NN P105 pin functions as TC pin DMAO request bit DMA1 request bit DMA2 request bit DMAS request bit 0 No request lt
251. ble bit At normal termination SARi latch Indicates the transfer parameter memory s start address of the next block SARI Indicates the address of the next transfer source DARi latch Not used DARI Indicates the address of the next transfer destination TCRi latch Indicates the number of remaining transfer blocks TCRi Indicates the number of remaining transfer bytes TC pin validity bit Bit 1 at address 6816 13 68 7721 Group User s Manual DMA CONTROLLER 13 7 Array chain transfer mode b23 b16 b15 b8 b7 bO I Source address register 0 Addresses 1FC216 to 1FC016 SARO Source address register 1 Addresses 1FD216 to 1FD016 SAR1 Source address register 2 Addresses 1FE216 to 1FE016 SAR2 Source address register 3 Addresses 1FF2 e to 1FF016 SAR3 Write SPD Set the start address of transfer parameter memory ese c These bits can be set to 000000 e to FFFFFF 6 Read After a value is written to this register and until transfer starts the read value indicates the written value the start address of the transfer parameter memory After transfer starts the read value indicates the source address of data which is next transferred Note When writing to this register write to all 24 bits b23 b16 b15 b8 b7 bO 2 pb Destination address register 0 Addresses 1FC616 to 1 C416 DARO Destination address register 1 Addresses 1FD616e to 1FD416 DAR1 Destination address register 2 Addresses 1
252. block Note The above figure applies when 2 bus cycle transfer is performed When data is transferred from memory to I O in 1 bus cycle transfer there is no DARic Transfer parameter When data is transferred from I O to memory in 1 bus cycle transfer there is no SARic Transfer parameter Fig 13 8 6 Operation flowchart of link array chain transfer mode 13 88 7721 Group User s Manual DMA CONTROLLER 13 8 Link array chain transfer mode 4 88 e1nBi4 0 enuyjUuoD ojeis Aey SJejeureJed 1oJsueJ JO JejsueJ OVINQ 0 pejdoooe si pue Si jeubis Bui duies 1s nb i sng y aym pejduues si pjoH JO usaJjeJ WWHG 4q pesneo 1senbaiJ sng sul e JejeueJed 1 JSUB1 JO JeJsueJ snq esn o1 1ufu JO UOnISUeJ OLS LIS OL IMOVVING Builduies 1s nb i sng Lq eey oq 9 v sys v sq ev V 0V Wu JIV Fig 13 8 7 Timing diagram of link array chain transfer mode burst transfer mode 1 13 89 7721 Group User s Manual DMA CONTROLLER 13 8 Link array chain transfer mode sng esn 0 1uDu Jo uonisueJ lt i BuisseooJd ejeuriuuo q be ag pg O IMa i Qye S JoJsueJ i ojeis Aey l e s JOJSUeI l 1s eny I L t J l elep Jo J JSUPJ p JoJsueJ PUn 4L 8 L e1nBi4 Duipeoeud wod lt OLS LLS L IMOVVIAG Builduues sanba sng LQ eev o 0 9 V si g s i v eg ev V 0V Wu 31V Fi
253. bus to request bit of another channel becomes 1 during CPU once DMAC regains the right and this term on condition that DMAi request bit of restarts DMA transfer if DMAi request another channel becomes 1 at the timing bit of another channel becomes 1 satisfying tsu DRQ 1 during this term When a DMA request is generated at the following timing it is not in time to the next bus request sampling Therefore DMAC returns the right to use bus to the CPU Then the DMAC regains the right and restarts DMA transfer Except for the last 1 unit transfer is selected without Wait In addition a time of 0 5 cycle of 0 is less than tsupna 61 Fig 13 4 13 Conditions for performing DMA transfers of another channel subsequently 7721 Group User s Manual 13 53 DMA CONTROLLER 13 5 Single transfer mode 13 5 Single transfer mode This mode is used to transfer a block of data once Table 13 5 1 lists the specifications of the single transfer mode and Figure 13 5 1 shows the register structures of SARi DARi and TCRi in this mode Table 13 5 1 Specifications of single transfer mode Item Transfer parameter memory Condition of normal termination Conditions of forced termination Interrupt request generation timing Functions of registers Performance specifications Not required TCRi 0 e Falling edge of the TC pin s input from H to L when the TC pin validity bit 2 1 Write 0 to
254. ceive register and that is transferred to the UARTi receive buffer register i e when reception is completed This flag is cleared to 0 when one of the following is performed Reading the low order byte of the UARTI receive buffer register out Clearing the receive enable bit bit 2 to 0 Clearing the serial I O mode select bits bits 2 to 0 at addresses 3016 3816 to 0002 7721 Group User s Manual SERIAL I O 11 2 Block description 11 2 4 UARTi transmit register and UARTi transmit buffer register Figure 11 2 5 shows the block diagram for the transmitter Figure 11 2 6 shows the structure of UARTI transmit buffer register Data bus odd Data bus even UARTi transmit buffer register SP Stop bit PAR Parity bit 8 bit UART 9 bit UART _ bIt UART Parity Clock sync 2SP enabled UART O O O O SP SP PAR O E 1SP x ex Clock sync 7 bit UART i I 7 bit UART l disabled 8 bit UART oe UAHRTI transmit register Clock sync 0 Fig 11 2 5 Block diagram for transmitter UARTO transmit buffer register Addresses 3316 3216 UART1 transmit buffer register Addresses 3B16 3A16 Transmit data is set 15 to 9 Nothing is assigned umts Note Use the LDM or STA instruction for writing to this register Fig 11 2 6 Structure of UARTi transmit buffer register 7721 Group User s Manual 11 9 SERIAL I O 11 2 Block description Transmit data is set into
255. ceive register with the receive 0002 complete flag 1 i e data is present Clear the receive enable bit to 0 in the UARTi receive buffer register In other words when the next data is prepared before the contents of the UARTI receive buffer register are read out Note UARTi receive interrupt request bit is not Framing error flag When the number of detected stop bits Clear the serial I O mode select bits to does not match the set number of stop 0002 bits Clear the receive enable bit to 0 UARTi receive interrupt request bit is set Read out the low order byte of the UARTi to 1 receive buffer register Parity error flag When the sum of 1 s in the parity bit Clear the serial I O mode select bits to and character bits does not match the 0002 set number of 1 s Clear the receive enable bit to 0 UARTi receive interrupt request bit is set Read out the low order byte of the UARTi to 1 receive buffer register Error sum flag When 1 or more errors listed above occur Clear the all error flags which are overrun framing and parity error flags Note The next data is written into the UARTI receive buffer register When an error occurs during reception initialize the error flag and the UARTi receive buffer register and then perform reception again When it is necessary to perform retransmission owing to an error which occurs in the receiver side durin
256. cess time taan tsu a pL oH address latch delay time OE access time tag tweet tsu DL DH E Chip select access time tas lt tsua oupu address decode time address latch delay time Address latch delay time Delay time required when latching address Unnecessary in minimum model Address decode time Time required for validating chip select signal after decoding address Table 16 1 2 lists the calculation formulas and values for each parameter in Figure 16 1 1 Figure 16 1 2 shows the relationship between tsua puoH and f Xin Table 16 1 2 Calculation formulas and Values for each parameter in Figure 16 1 1 unit ns Calculation formulas and Values Wait lw EL 2 X 10 4 X 10 f Xin DES f Xin Des tsu A DL 3X 10 5 X 109 70 tsu A DH f Xin f XiN tpzx E DLZ 1 X 10 lpzx E DHZ f XiN eM tsu DL E 30 tsu DH E Wait e No Wait O D N S G o o YW D D O G C z D E O mD V G G C 9 10 11 12 13 14 15 16 17 18 19 20 21 External clock input frequency f XIN Fig 16 1 2 Relationship between tsu a pupi and f Xin 7721 Group User s Manual 16 5 APPLICATION 16 1 Memory connection Timing for reading data from DRAM DRAM output enable sign
257. chdog timer s count source Figure 15 1 3 shows the structure of the watchdog timer frequency select register b7 b6 b5 b4 b3 b2 bl b0 Watchdog timer frequency select register Address 6116 EJ to 1 Nothing is assigned uei Fig 15 1 3 Structure of watchdog timer frequency select register 7721 Group User s Manual 15 3 WATCHDOG TIMER 15 2 Operation description 15 2 Operation description 15 2 1 Basic operation Watchdog timer starts counting down from FFFie When the Watchdog timer s most significant bit becomes 0 counted 2048 times a watchdog timer interrupt request occurs Refer to Table 15 2 1 When the interrupt request occurs at above a value FFF e is set to Watchdog timer The watchdog timer interrupt is a non maskable interrupt When the watchdog timer interrupt request is accepted the processor interrupt priority level IPL is set to 1112 Table 15 2 1 Occurrence interval of watchdog timer interrupt request Watchdog timer f Xin 25 MHz frequency select bit Occurrence interval 41 94 ms 1 f32 2 62 ms 15 4 7721 Group User s Manual WATCHDOG TIMER 15 2 Operation description Write dummy data to the watchdog timer register address 6016 before the most significant bit of Watchdog timer becomes 0 When Watchdog timer is used to detect a program runaway a watchdog timer interrupt request occurs if writing to address 6016 is not performed owing to a progr
258. cks 5 2 1 Clocks generated in clock generating circuit 1 2 3 4 It is the operation clock of BIU It is also the clock source of cpu stops by acceptance of Ready request or execution of the STP or WIT instruction It is not stopped by acceptance of bus request CPU It is the operation clock of CPU ceu stops by the following Execution of the STP or WIT instruction Acceptance of Ready request L level input to the RDY pin CPU wait request from BIU Acceptance of bus request is included Clock 6 It has the same period as and is output to the external from the pin Clock stops by execution of the STP instruction It is not stopped by acceptance of Ready or bus request or execution of the WIT instruction f2 to fs12 Each of them is the internal peripheral devices operation clock Note Refer to each functional description for details Execution of STP instruction 5 3 Stop mode Execution of WIT instruction 5 4 Wait mode dzcco e 3 3 Ready function Bus requesl 13 2 1 Bus access control circuit 7721 Group User s Manual CLOCK GENERATING CIRCUIT 5 3 Stop mode 5 3 Stop mode Stop mode is used to stop oscillation when there is no need to operate the central processing unit CPU The microcomputer enters Stop mode when the STP instruction is executed Stop mode can be termin
259. count start bit Stop counting Start counting a Timer A1 count start bit Timer A2 count start bit S Timer Bt count start bit x One shot start register b7 b6 b5 b4 b3 b2 ITT ToT One shot start register Address 4216 FIM SL DOLES Fix these bits to 0 The value is 0 at reading 1 Timer A2 one shot start bit 1 Start outputting one shot pulse valid when internal trigger is Timer A3 one shot start bit selected The value is 0 at reading Timer A4 one shot start bit Nothing is assigned IT F lt lt 17 16 7721 Group User s Manual APPENDIX Appendix 3 Control registers Up down register b7 b6 b5 b4 b3 b2 bi bO Ltt EL fofo Up down register Address 4416 0 Fix these bits to 0 o RWI 3 o nw Timer A2 up down bit 0 Countdown o RW 1 Countup kusa SACER Timer A3 up down bit This function is valid when the contents of o Rw the up down register is selected as the up P Timer A4 up down bit down switching factor H o w METRE 5 Timer A2 two phase pulse signal 9 Two phase pulse signal WO i processing select bit Note processing function disabled 1 Two phase pulse signal DDR Timer A3 two phase pulse signal processing function enabled pe ww rocessing select bit Note B When not using the two phase pulse miele RS SCs aie nisin e Inm pae einai 7 Timer A4 two phase p
260. counting is not in progress is set to the counter and reload register The value written into the timer Ai register while counting is in progress is set only to the reload register In this case the reload register s updated contents are transferred to the counter at the next reload time The value obtained when reading out the timer Ai register varies according to the operating mode Table 8 2 2 lists reading from and writing to the timer Ai register Table 8 2 1 Memory assignment of timer Ai register Timer Ai register High order byte Low order byte Timer AO register Address 4716 Address 4616 Timer A1 register Address 49 e Address 4816 Timer A2 register Address 4B e Address 4A e Timer A3 register Address 4D e Address 4Cie Timer A4 register Address 4F e Address 4E e Note At reset the contents of the timer Ai register are undefined Table 8 2 2 Reading from and writing to timer Ai register Operating mode Write Timer mode Counter value is read out While counting Event counter mode Note 1 Written only to reload register lt While not counting gt One shot pulse mode Undefined value is read out Written to both of the counter Pulse width modulation PWM mode and reload register Notes 1 Also refer to Precautions for timer mode and Precautions for event counter mode 2 When reading from and writing to the timer Ai register perform it in a unit of 16 bits 8 4 7721 Group User s Manual TIME
261. curs its priority level is compared with the processor interrupt priority level IPL The requested interrupt is enabled only when its priority level is higher than the IPL However this applies when the interrupt disable flag I 0 To disable DMAi interrupts set these bits to 0002 level 0 2 Interrupt request bit bit 3 This bit is set to 1 when a DMAi interrupt request occurs after the DMA transfer is complete This bit is automatically cleared to 0 when the DMAi interrupt request is accepted This bit can be set to 1 or cleared to 0 by software 7721 Group User s Manual 13 17 DMA CONTROLLER 13 2 Block description 13 2 14 Port P9 direction register I O pins of DMAi are multiplexed with port P9 When using these pins as the DMAREQi input pins set the corresponding bits of the port P9 direction register to O to set these port pins for the input mode When using these pins as the DMAACKi output pins these pins are forcibly set to the DMAACKi output pins regardless of the direction register s contents Figure 13 2 10 shows the relationship between the port P9 direction register and DMAi s I O pins b7 b6 b5 b4 b3 b2 bl Port P9 direction register Address 1516 s 0 Input mode o mw 1 Output mode ome When using pins P9 P93 P95 and W Q Lo m Cs mes p Le Pes FEET r ee ERE Fig 13 2 10 Relationship between port P9 direction register and D
262. curs when the next data is prepared in the UARTi receive register with the receive complete flag 1 data is present in the UARTi receive buffer register and next data is transferred to the UARTi receive buffer register in other words when the next data is prepared before reading out the contents of the UARTi receive buffer register When an overrun error occurs the next receive data is written into the UARTi receive buffer register and the UARTi receive interrupt request bit is not changed An overrun error is detected when data is transferred from the UARTIi receive register to the UARTi receive buffer register and the overrun error flag is set to 1 The overrun error flag is cleared to 0 by clearing the serial I O mode select bits to 0002 or clearing the receive enable bit to 0 When an overrun error occurs during reception initialize the overrun error flag and the UARTi receive buffer register before performing reception again When it is necessary to perform retransmission owing to an overrun error which occurs in the receiver side set the UARTi transmit buffer register again before starting transmission again The method of initializing the UARTi receive buffer register and that of setting the UARTi transmit buffer register again are described below 1 Method of initializing UARTi receive buffer register Clear the receive enable bit to 0 Reception disabled Set the receive enable bit to 1 aga
263. d to 0 when one of the following is performed Clearing the receive enable bit to 0 Reading the low order byte of the UARTi receive buffer register addresses 3616 3E16 out Clearing the serial I O mode select bits bits 2 to 0 at addresses 3016 3816 to 0002 Bit 7 is cleared to 0 when all of bits 4 to 6 become 0 2 Bits 5 to 7 are invalid in the clock synchronous serial I O mode Fig 11 2 4 Structure of UARTi transmit receive control register 1 7721 Group User s Manual 11 7 SERIAL I O 11 2 Block description 1 2 3 4 Transmit enable bit bit 0 By setting this bit to 1 UARTi enters the transmission enable state By clearing this bit to 0 during transmission UARTi enters the transmission disable state after the transmission which is in progress at that time is completed Transmit buffer empty flag bit 1 This flag is set to 1 when data set in the UARTi transmit buffer register is transferred from the UARTi transmit buffer register to the UARTi transmit register This flag is cleared to 0 when data is set in the UARTi transmit buffer register Receive enable bit bit 2 By setting this bit to 1 UARTi enters the reception enable state By clearing this bit to 0 during reception UARTi quits the reception immediately and enters the reception disable state Receive complete flag bit 3 This flag is set to 1 when data is ready in the UARTi re
264. ddress Address Even address Internal data bus Do tO D7 Invalid data Data Even address Internal data bus Ds tO D15 Data Odd address Invalid data Fig 2 2 3 Basic operating waveforms of bus interface unit BIU 2 14 7721 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 3 Access space 2 3 Access space Figure 2 3 1 shows the M37721 s access space By combination of the program counter PC which is 16 bits of structure and the program bank register PG a 16 Mbyte space from addresses 0 e to FFFFFF e can be accessed For details about access of an external area refer to CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES The memory and I O devices are assigned in the same access space Accordingly it is possible to perform transfer and arithmetic operations using the same instructions without discrimination of the memory from I O devices 00000016 SFR area 00007F46 00008016 Internal RAM area 00047F16 Bank 016 OOFFFF 01000016 Bank 116 02000016 FEO00001 6e Bank FE16 Indicates the memory assignment FF0000 6 of the internal areas Bank FF16 FFFFFFie Hi Indicates that nothing is assigned Note Memory assignment of internal RAM area varies according to the type of microcomputer This figure shows the case of the M37721S2BFP Refer to Figure 2 4 1 for the M37721S1BFP SFR Special Function Register Fig 2 3 1 M37721 s access space 7721 Group User s
265. ddress of data which is next transferred Note When writing to this register write to all 24 bits b23 b16 b15 b8 b7 b0 Transfer counter register 0 Addresses 1FCA16 to 1FC816 TCRO Transfer counter register 1 Addresses 1FDA e to 1FD816 TCR1 Transfer counter register 2 Addresses 1FEAte to 1FE816 TCR2 Transfer counter register 3 Addresses 1FFA e to 1FF816e TCR3 k Write Undefined RW Set the byte number of transfer data These bits can be set to 00000116 to FFFFFF 16 Read The read value indicates the remaining byte number of the block which is being transferred Note When writing to this register write to all 24 bits Do not write 00000016 to this register Fig 13 6 1 Register structures of SARi DARi and TCRi in repeat transfer mode 13 62 7721 Group User s Manual DMA CONTROLLER 13 6 Repeat transfer mode 13 6 1 Setting of repeat transfer mode Figures 13 6 2 through 13 6 4 show an initial setting example for registers relevant to the repeat transfer mode In addition when timer A timer B UART or the A D converter is selected as a DMA request source the setting for the peripheral is required For details of the setting refer to the chapter of each peripheral function In this mode only the forced termination can terminate the DMA transfer Refer to section 13 3 5 2 Forced termination Therefore in the burst transfer mode edge sense selected be sure to validate
266. ddress register 1 Addresses 1FD216 to 1FD016 S Phase output data table s start address b23 b16b15 b8b7 bO Destination address register 1 Addresses 1FD616 to 1FD416 DUE sue output data register O s address b23 b16b15 b8b7 b0 Transfer counter register 1 Addresses 1FDAte to 1FD816 7 E C pyc output data table s data number 0 0 0 0 1 1 DMAT1 control register Address 1FDE 6 V Y AC DMA request source Timer A0 DMAACK1 pin Invalid b7 b0 0 0 0 DMAt interrupt control register Address 6D16 Interrupt disabled X It may be O or 1 Fig 16 2 8 Initial setting example for relevant register 1 16 50 7721 Group User s Manual APPLICATION 16 2 Examples of using DMA controller b7 bo ojoj 0 1 0 0 DMA2 mode register L Address 1FEC16 Transfer unit 16 bits 2 bus cycle transfer Cycle steal transfer mode Transfer source address direction At slow up 012 Forward At slow down 102 Backward Transfer destination address direction Fixed b7 b0 0 0 1 0 0 0 X 0 DMA2 mode register H Address 1FED 6 Transfer source Wait No transfer destination Wait Single transfer mode b23 b16b15 b8b7 b0 Source address register 2 Addresses 1FE216 to 1FEO016 XS a I Timer AO set value data table s start address b23 b16b15 b8b7 bO Destination address register 2 Addresses 1FE616 to 1FE416 MV I
267. ddressing mode Stack pointer relative addressing mode Stack pointer relative indirect indexed Y addressing mode Block transfer addressing mode Carry flag Zero flag Interrupt disable flag Decimal operation mode flag Index register length selection flag Data length selection flag Overflow flag Negative flag Processor interrupt priority level Addition Subtraction Multiplication Division Logical AND Logical OR 7721 Group User s Manual APPENDIX Appendix 6 Machine instructions Exclusive OR Negation Movement to the arrow direction Accumulator Accumulator s upper 8 bits Accumulator s lower 8 bits Accumulator A Accumulator A s upper 8 bits Accumulator A s lower 8 bits Accumulator B Accumulator B s upper 8 bits Accumulator B s lower 8 bits Index register X Index register X s upper 8 bits Index register X s lower 8 bits Index register Y Index register Y s upper 8 bits Index register Y s lower 8 bits Stack pointer Program counter Program counter s upper 8 bits Program counter s lower 8 bits Program bank register Data bank register Direct page register Direct page register s upper 8 bits Direct page register s lower 8 bits Processor status register Processor status register s upper 8 bits Processor status register s lower 8 bits Processor status register s b th bit Contents of memory at address indicated by stack pointer b th memory location Value of 24 bit address s upper 8 bit Aes A 6
268. der 8 bits Ao A of the address are output When the DRAM is accessed the row and column addresses are output with the time sharing OG External data bus width 8 bits When the BYTE pin is H level Middle order 8 bits As A s of the address are output Ge External data bus width 16 bits When the BYTE pin is L level Data De D s input output and output of the middle order 8 bits As A s of the address are performed with the time sharing Data Do D7 input output and output of the high order 8 bits A e As of the address are performed with the time sharing R W The Read Write signal indicates the data bus state The state is read while this signal is H level and write while this signal is L level BHE L level is output when an odd numbered address is accessed eBLE L level is output when an even numbered address is accessed eALE This is used to obtain only the address from address and data multiplex signals Hold input Input The microcomputer is in Hold state while L level is Ready input Input The microcomputer is in Ready state while L level is Clock output Output This is the output pin 7721 Group User s Manual 1 5 DESCRIPTION 1 3 Pin description Table 1 3 3 Pin description 3 Pin P43 P47 P5o P5 P60 P67 P7o P77 P80 P87 P9o P9 P10o P107 Name Input Output Functions I O port P4 I O port P5 I O port P6 I O port P7
269. des Tables 11 4 3 and 11 4 4 list the setting examples of transfer rate Table 11 4 3 Setting examples of transfer rate 1 f Xi 24 576 MHz f Xi 25 MHz BRGi s BRGi s set d time BRGi s BHOGi s set Actual time count source count source bps 300 a Sur sooo e 8 OH 30 6 600 599 12 1200 79 4F s fis 80 5016 1205 63 2400 te 39 27 240 00 fe 401 2381 86 4800 t pear ed co 162 A216 4792 94 9600 f 79 4Fw 960000 f 80 509 9645 06 14400 MECT amp sos 14467 59 19200 f 29 gn guo t 40 28s _ 19054 58 38400 at omno d Table 11 4 4 Setting examples of transfer rate 2 f Xw 22 1184 MHz T f ibd BRGi s BHGi s set Actual time rate bps count source value bps 300 f 71 4716 300 00 Transfer rate bps O NO Qo D O 600 600 00 1200 fis 71 4736 1200 00 2400 fie 35 2316 2400 00 4800 143 8F s 4800 00 9600 71 47 9 9600 00 14400 7 14400 00 47 2Fw 19200 35 2316 19200 00 28800 23 17 6 28800 00 31250 31418 18 38400 17 1116 38400 00 57600 57600 00 115200 5 05 6 115200 00 230400 2 0216 230400 00 11252 7721 Group User s Manual SERIAL I O 11 4 Clock asynchronous serial I O UART mode 11 4 2 Transfer data format The transfer data format can be selected from formats shown in Figure 11 4 1 Bits 4 to 6 at addresses 30 16 and 3816 select the transfer data format Refer to Figure 11 2 2 Set the same tr
270. determine the processor interrupt priority level to one of levels 0 to 7 The interrupt is enabled when the interrupt priority level of a required interrupt which is set in each interrupt control register is higher than IPL When an interrupt request is accepted IPL is stored in the stack area and IPL is replaced by the interrupt priority level of the accepted interrupt request There are no instruction to directly set or clear the bits of IPL IPL can be changed by storing the new IPL into the stack area and updating the processor status register with the PUL or PLP instruction The contents of IPL is cleared to 0002 at reset 7721 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 2 Bus interface unit 2 2 Bus interface unit A bus interface unit BIU is built in between the central processing unit CPU and memory l O devices BIU s function and operation are described below When externally connecting devices refer to CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES 2 2 1 Overview Transfer operation between the CPU and memory l O devices is always performed via the BIU The BIU reads an instruction from the memory before the CPU executes it When the CPU reads data from the memory l O device the CPU first specifies the address from which data is read to the BIU The BIU reads data from the specified address and passes it to the CPU When the CPU writes data to the memory l O device the CPU first specifies the addres
271. dge of the TAjw pin s input signal when bit 3 at addresses 5816 to 5Aie is 0 or at its rising edge when bit 3 is 1 However the trigger input is accepted only when the count start bit is 1 When using an external trigger set the port P5 direction registers bits which correspond to the TAjin pins for the input mode 8 42 7721 Group User s Manual TIMER A 8 6 Pulse width modulation PWM mode 8 6 4 Operation in PWM mode When the PWM mode is selected with the operating mode select bits the TAjour pin outputs L level When a trigger is generated the counter pulse width modulator starts counting and the TAjour pin outputs a PWM pulse Notes 1 and 2 The timer Aj interrupt request bit is set to 1 each time the PWM pulse level goes from H to L The interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to O by software Each time a PWM pulse has been output for one period the reload register s contents are reloaded and the counter continues counting The following explains operations of the pulse width modulator 1 16 bit pulse width modulator When the 16 8 bit PWM mode select bit is set to 0 the counter operates as a 16 bit pulse width modulator Figures 8 6 4 and 8 6 5 show operation examples of the 16 bit pulse width modulator 2 8 bit pulse width modulator When the 16 8 bit PWM mode select bi
272. dge sense Burst Level L In burst transfer mode level sense with DMAREQI pin L Burst Level H In burst transfer mode level sense with DMAREQi pin H Cycle steal Requested In cycle steal transfer mode with any request of DMAO 3 Cycle steal No request In cycle steal transfer mode with no request of DMA0 3 SARi latch indicates the start address of the transfer parameter memory of the next block TCRi latch indicates the number of remaining transfer blocks Note The above figure applies when 2 bus cycle transfer is performed When data is transferred from memory to I O in 1 bus cycle transfer there is no DARI Transfer parameter When data is transferred from I O to memory in 1 bus cycle transfer there is no SARI lt Transfer parameter Fig 13 7 6 Operation flowchart of array chain transfer mode 13 76 7721 Group User s Manual DMA CONTROLLER 13 7 Array chain transfer mode u zep u zes u zep u zes Jajsued yoojq puooas cep ces w ep W Les uJ ep UJ4 es JOJSU J 490JQ 1S1Id Lep es Mowe AOowsy 9jels JoJSUeJ ejep Jo JoJsuelJ lt JeJsueJ jun eDed 1xeu uo g z e1nBi4 o1 enunuo2 SJo ouJeJed joJsueJ S 4o9o qg puooegs SJo eujeJed JeJSUEJ S 490 q ISUI4 pejdoooe si pue SI jeubis Buljdwes 1s nb 1 sng y ejuw pejduues si p oH 10 usaJjaJ NYHa Aq pesneo 1s nb sng eu e ojeis Aey
273. dress j Address Address X Address lt gt td AH E Auos AaiOroupt EX Daa K naes YRS EE Data dress BHE output BLE output th E R W td R W E R W output Test conditions Vcc 25V 10 96 Output timing voltage Vor 0 8 V Vou 2 0 V Do Dt s input Vii 0 8 V VH 2 5 V 7721 Group User s Manual 17 101 APPENDIX Appendix 11 Electrical characteristics When DMA transfer is forcedly completed by TC input TC input timing 1 TC input STO DMAACKi Ao A7 output As Ds A15 D15 output BYTE L As Ds A15 D15 output BYTE H ALE output R W output 17 102 td AL E gt lt Source address Destination address Address Source Destination address address Data X p eres emen td AM E gt _ lt td AH E 3L l lt address A16 Do A23 D7 output Data X Destination address Destination address tw ALE td o1 STi tw TCin td 1 DAK th E AL d E DHQ th E AM CX th ALE AM lt Source Destination td E DLQ address l oe CX se c la ALE E E th ALE AH M j ta R W E th E R W Test conditions Vcc 5 V 10 96 Output timing voltage Vor 0 8 V Vor 2 0 V Do D15 input Vir 0 8 V Vu 2 5 V TC input Vi 0 8 V Viu 2 2 5 V 7721 Group User s Manual APPENDIX Appendix 11 Electrical characteristics Table 3 Calculation formulas for internal periphe
274. dress 7216 UART1 receive interrupt control register Address 7416 b7 bO Smm Interrupt priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 a BRG count source select bits a UARTO transmit receive control register 1 Address m UART1 transmit receive control register 1 Address 3D16 0 0 f2 01 fie b7 bO Pt ttt l 11 f512 CTS RTS select bit Receive enable bit 0 CTS function selected 1 RTS function selected i C 1 Reception i Heception starts when the start bit is detected Fig 11 4 9 Initial setting example for relevant registers when receiving 11 42 7721 Group User s Manual SERIAL I O 11 4 Clock asynchronous serial I O UART mode When not using interrupts fo UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 b7 bO EL TEES hecking completion of reception Receive complete flag 0 Reception not completed V 1 Reception completed F Checking error UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 Framing error flag Parity error flag Error sum flag 0 No error S 1 Error detected N When using interrupts A UARTi receive interrupt
275. dress register Then the CPU writes data into the data buffer The BIU outputs the address received from the CPU onto the address bus and writes data in the data buffer into the specified address The CPU advances to the next processing without waiting for completion of BIU s write operation However if the BIU uses the bus for instruction prefetch when the CPU requires to write data the BIU keeps the CPU waiting Bus control To perform the above operations 1 to 3 the BIU inputs and outputs the control signals and controls the address bus and the data bus The cycle in which the BIU controls the bus and accesses the memory l O device is called the bus cycle Refer to CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES about the bus cycle at accessing the external devices 7721 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 2 Bus interface unit 2 2 3 Operation of bus interface unit BIU Figure 2 2 3 shows the basic operating waveforms of the bus interface unit BIU About signals which are input output externally when accessing external devices refer to CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES 1 2 When fetching instructions into the instruction queue buffer When the instruction which is next fetched is located at an even address the BIU fetches 2 bytes at a time with the timing of waveform a However when accessing an external device which is connected with the 8 bit external data bus width BYTE
276. e Appendix 8 Countermeasure against noise General countermeasure examples against noise are described below Although the effect of these countermeasure depends on each system refer to the following when an noise related problem occurs 1 Short wiring length The wiring on a printed circuit board may function as an antenna which feeds noise into the microcomputer The shorter the total wiring length by mm unit the less possibility of noise insertion into the microcomputer 1 Wiring for RESET pin Make the length of wiring connected to the RESET pin as short as possible In particular connect a capacitor between the RESET pin and the Vss pin with the shortest possible wiring within 20 mm Reason If noise is input to the RESET pin the microcomputer restarts operation before the internal state of the microcomputer is completely initialized This may cause a program runaway M37721 M37721 Reset Reset circuit circuit Not acceptable Acceptable Fig 3 Wiring for RESET pin 2 Wiring for clock input output pins e Make the length of wiring connected to the clock input output pins as short as possible Make the length of wiring between the grounding lead of the capacitor which is connected to the oscillator and the Vss pin of the microcomputer as short as possible within 20 mm Separate the Vss pattern for oscillation from all other Vss patterns Refer to Figure 11 Reason Ihe microcomputer s operation
277. e n the counter divides the count source frequency by n 1 during countdown or by FFFF e n 1 during countup When reading the register indicates the counter value Note Read from or write to this register in a unit of 16 bits b b6 b5 b4 b3 b2 bl A ORGIDEE Timer Aj mode register j 2 to 4 Addresses 5816 to 5A16 Bt Bitname Q J Functions atrset Rw KECA e Operating mode select bits Q1 Event counter mode KECI Pulse output function select bit 0 No pulse output TAjour pin functions RW as a programmable O port Pulse output TAjour d functions as a pulse output pin Count polarity select bit E Counts at falling edge of external signal Counts at rising edge of external signal TIS eee aes eae Up down switching factor select Contents of up down register bit Input signal to TAjour pin Mesum poem eater A Fix this bit to 0 in event counter mode e Ma scalis SCC These bits are invalid in event counter mode nm EECA p 17 20 7721 Group User s Manual APPENDIX Appendix 3 Control registers One shot pulse mode b15 b8 b7 bO b7 bO Timer A3 register Addresses 4D16 4C16 Timer A4 register Addresses 4F16 4E16 15 to 0 These bits can be set to 000116 to FFF F16 Undefined WO Assuming that the set value n the H level width of the one shot pulse output from the TAjout pin is expressed as follows
278. e Use the LDM or STA instruction for writing to bits 5 to 7 Fig 8 4 5 Structure of up down register 8 24 7721 Group User s Manual TIMER A 8 4 Event counter mode 8 4 4 Selectable functions The following describes the selectable pulse output and two phase pulse signal processing functions 1 Pulse output function The pulse output function is selected by setting the pulse output function select bit bit 2 at addresses 5816 to 5A16 to 1 When this function is selected the TAjour pin is forcibly set for the pulse output pin regardless of the corresponding bit of the port P5 direction register The TAjour pin outputs pulses of which polarity is inverted each time a counter underflow or overflow occurs Refer to Figure 8 3 6 When the count start bit address 4016 is O count stopped the TAjour pin outputs L level 7721 Group User s Manual 8 25 TIMER A 8 4 Event counter mode 2 Two phase pulse signal processing function The two phase pulse signal processing function is selected by setting the two phase pulse signal processing select bits bits 5 to 7 at address 4416 to 1 Refer to Figure 8 4 5 Figure 8 4 6 shows the timer Aj mode registers when the two phase pulse signal processing function is selected For timers with the two phase pulse signal processing function selected the timer counts two kinds of pulses of which phases differ by 90 degrees There are two types of the
279. e instructions are executed after a certain time measured by the watchdog timer has passed When an interrupt request occurs the oscillator starts oscillating Simultaneously supply of clock Q1 Foto fs12 starts The watchdog timer starts counting owing to the oscillation start The watchdog timer counts fs2 regardless of the watchdog timer frequency select bit s bit 0 at address 6116 contents When the watchdog timer s MSB becomes 0 supply of ceu and starts At the same time the watchdog timer s count source returns to fs or fs12 that is selected by the watchdog timer frequency select bit The interrupt request which occurred in is accepted Table 5 3 2 lists the interrupts used to terminate Stop mode Table 5 3 2 Interrupts used to terminate Stop mode Interrupt Conditions for using each function to generate interrupt request INTi interrupt i O to 2 Timer Ai interrupt i 2 to 4 In event counter mode Timer Bi interrupt i 2 O 1 UARTi transmit interrupt i 0 1 When external clock is selected UARTi receive interrupt i 0 1 Notes 1 Since the oscillator has stopped oscillating interrupts not listed above cannot be used Also even the interrupts listed above cannot be used when the above conditions are not satisfied The A D converter does not operate also 2 When multiple interrupts listed above are enabled Stop mode is terminated by the interrupt request which occurs first 3 Refer to
280. e level of the HOLD pin is at L Table 3 4 1 lists the microcomputer s state in Hold state In Hold state the oscillation of the oscillator does not stop Accordingly the internal peripheral devices can operate However Watchdog timer stops operating Table 3 4 1 Microcomputer s state in Hold state Item State Oscillation Operating Operating cpu Stopped at L E Stopped at H Pins Ao to Az As Ds to A1s Dis A16 Do to A23 D7 R W Floating BHE BLE Pins ALE ST1 Output L level Pin STO Outputs H level Pin Q Outputs clock Pins P4s to P47 P5 to P10 Note Retain the state when Hold request was accepted Watchdog timer Stopped Note This applies when this functions as a programmable I O port 3 4 1 Operation description Judgment of the HOLD pin input level is performed at every falling edge of When L level is detected at judgment of the input level bus request Hold becomes 1 when H level is detected bus request Hold becomes 0 Bus request Hold is sampled within a period when the bus request sampling signal is 1 and bus request is accepted when there is no bus request DRAMC This is called Acceptance of Hold request For bus request refer to section 13 2 1 Bus access control circuit When Hold request is accepted ceu stops at L level at the next rising edge of and the STO pin s level becomes H the ST1 pin s level becomes L
281. e products contained therein REVISION DESCRIPTION LIST 7721 Group User s Manual DESCRIPTION LIST 7721 REVISION DESCRIPTION LIST 7721 Group User s Manual User s Manual Hev date 1 0 Edition 970926 Revision x cOn O 1 1 Preface This manual describes the hardware of the Mitsubishi CMOS 16 bit microcomputers 7721 Group After reading this manual the user will be able to understand the functions so that their capabilities can fully be utilized BEFORE USING THIS MANUAL 1 Constitution This user s manual consists of the following chapters Refer to the chapters relevant to the products Chapter 1 DESCRIPTION through Chapter 16 APPLICATION Functions which are common to the M37721S1BFP and the M37721S2BFP are explained using the M37721S2BFP as an example Differences between the M37721S1BFP and the M37721S2BFP are described as notes Appendix Practical information for using the 7721 Group is described 2 Remark Product expansion Refer to the latest catalog and data book or contact the appropriate office as listed in CONTACT ADDRESSES FOR FURTHER INFORMATION on the last page Electrical characteristics Refer to the latest data book Software Refer to 7700 Family Software Manual Development support tools Refer to the latest data book of the develooment support tools 3 Signal levels in Figure As a rule signal levels in each operation example and timing di
282. e 16 3 1 lists the sample program Refer to Figure 16 3 1 execution time ratio depending on these selection and usable memory areas Table 16 3 1 Sample program execution time ratio external data bus width and software Wait Memory area i i i y External data bus Software Wait Sample program execution time ratio RAM width unit bit Sample A Sample B 1 08 SEE 1 46 None 1 00 1 00 Inserted 1 17 aes basu 1 13 Inserted 1 65 Calculated value 0 90 Calculated value The value is calculated from the shortest execution cycle number of each instruction described in 7700 Family Software Manual 16 56 7721 Group User s Manual Sample A SEP M X LDA B A 40 STA A DEST 64 STA A DEST 65 STA A DEST 66 LDX B 63 ITALIC LDA A SOUR X TAY AND B A 00000011B STA A DEST X TYA AND B A 00001100B ORA A DEST 1 X STA A DEST 1 X TYA AND B A 00110000B ORA A DEST 2 X STA DDS ey TYA AND B A 11000000B ORA A DEST X DIA A DESOTO x DEX BPL ITALIC SOUR DEST Work area Direct page area Access this area by using the following modes eDirect addressing mode lOOP US LOOP1 Direct Indexed X addressing mode Absolute Indexed Y addressing mode Fig 16 3 1 Sample program list 7721 Group User s Manual APPLICATION 16 3 Comparison of sample program execution rate Sample B SEP X CLM DATA 16 INDEX 8 LDY 69 LDX 69 ASL SOUR X SEM DATA 8 ROL SOUR 2 X ROL B CLM
283. e contents of the accumulator or the contents of Note 1 the memory one bit to the right The bit O of the accumu dini EEEo lator or the memory is entered into the C flag 0 is en m 1 tered into bit 15 bit 7 when the m flag is 1 gt bz bo gt C gt ep e l al F MPY f Multiplies the contents of accumulator A and the contents of the memory 3189 21 m 22 3 Notes 2 11 The higher order of the result of operation are entered into accumulator B and the lower order into accumulator A 89 19 3 ela On Transmits the data block The transmission is done from the lower order address of the block Transmits the data block Transmission is done form the higher order address of the data block C1 UJ N C1 or e AB no ce on Notes 1 2 the contents of the memory is obtained The result is en tered into the accumulator O c n qp no Po S e IMM2 The 3rd and the 2nd bytes of the instruction are saved into dp the stack in this order M S IMM Sc S 1 M S amp M DPR IMM Specifies 2 sequential bytes in the direct page in the 2nd 1 byte of the instruction and saves the contents into the S lt S 1 stack M S M DPR IMM S lt S 1 EAR lt PC IMM2 IMM Regards the 2nd and 3rd bytes of the instruction as 16 bit M S lt EARH numerals adds them to the program counter and saves S lt S 1 the result into the stack M S EAR Saves the
284. e counters Timers AO to A4 each equipped with a 16 bit reload function Timers AO to A4 operate independently of one another Timer A has four operating modes listed below Timers AO and A1 operate in the timer mode only Timers A2 to A4 have selective four operating modes listed below 1 2 3 4 Timer mode Timers AO to A4 The timer counts an internally generated count source For Timers A2 to A4 the following functions can be used in this mode Gate function Pulse output function Event counter mode Timers A2 to A4 The timer counts an external signal The following functions can be used in this mode Pulse output function wo phase pulse signal processing function One shot pulse mode Timers A2 to A4 The timer outputs a pulse which has an arbitrary width once Pulse width modulation PWM mode Timers A2 to A4 Timer outputs pulses which have an arbitrary width in succession The counter functions as one of the following pulse width modulators 16 bit pulse width modulator 8 bit pulse width modulator In this chapter Timer Ai i O to 4 indicates Timers AO to A4 Timer Aj j 2 to 4 indicates Timers A2 to A4 this is applies when the timer A s input output pins are used etc Hereafter input output pins are called I O pins 7721 Group User s Manual TIMER A 8 2 Block description 8 2 Block description Figure 8 2 1 shows the block diagram of Timer A Explanation of registers rele
285. e following conditions Transfer source address direction forward start address of data even with Wait Transfer destination address direction backward start address of data odd with Wait O 090 904 021425 8 4 1 34 cycles Table 13 9 1 Time required for processing in array state Mod External data T f hod Number of transfer Number of reads of Time required for He bus width rangiert Meng parameters a transfer parameter processing in array state Unit cycle Array e M e cycle transfer 3 J 2 3x2x34 12 19 transfer mode Including internal bus 1 bus cycle transfer 2 2 2x2x3 4 1 18 2 bus cycle transfer 3 4 3x4x 341 37 1 bus cycle transfer 2 4 2x4x3 1 25 Link array chain 16 bits 2 bus cycle transfer 4 4x2x3 1 25 transfer mode Including internal bus 1 bus cycle transfer 3 2x2x3412 19 8 bits 2 bus cycle transfer 4 4 4x4x3 4 1 49 1 bus cycle transfer 3 4 3x4x3 1 37 13 100 7721 Group User s Manual DMA CONTROLLER 13 9 DMA transfer time 13 9 2 Burst transfer mode 1 Single transfer mode use CPU EE DMAC EN CPU Transition Transfer TerminationTransition 8 98 Mesc94 4 2 3 4 Fig 13 9 4 Single transfer mode burst transfer mode selected Transition of the right to use bus from CPU to DMAC 1 cycle DMA transfer per an entire batch of data e In 2 bus cycle transfer Read cycle Write cycle x the number of tra
286. e successive approximation register conversion result are transferred to the A D register i At the same time as step the A D conversion interrupt request bit is set to 1 The A D conversion stops The A D conversion start bit remains set to 1 after the operation is completed Accordingly the operation of the A D converter can be performed again from step when the level of the ADrne pin changes from H to L When the level of the ADtra pin changes from H to L during operation the operation at that point is cancelled and is restarted from step Figure 12 5 2 shows the conversion operation in the one shot mode Trigger occur Conversion result Convert input voltage from mee ANi pin A D conversion interrupt request occurs A D converter halt Fig 12 5 2 Conversion operation in one shot mode 12 16 7721 Group User s Manual A D CONVERTER 12 6 Repeat mode 12 6 Repeat mode In the repeat mode the operation for the input voltage from the one selected analog input pin is performed repeatedly In this mode no A D conversion interrupt request occurs Additionally the A D conversion start bit bit 6 at address 1E e remains set to 1 until it is cleared to 0 by software and the operation is performed repeatedly while the A D conversion start bit is 1 12 6 1 Settings for repeat mode Figure 12 6 1 shows an initial setting example for registe
287. ea Software reset bit The microcomputer is reset by writing 1 to this bit The value is 0 at reading b5 b4 0 0 7 cycles of 0 1 4 cycles of 10 2 cycles of 1 1 Do not select Interrupt priority detection time select bits Fix this bit to 0 7 Stack bank select bit ne Bank O16 Bank FF e Bits 0 1 and 3 to 6 are not used for accessing external area Fig 3 2 1 Structure of processor mode register 0 3 8 7721 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 3 2 Software Wait No Wait 1 bus cycle Clock 01 E x ALE AoA Note As D8 A15 D15 A16 Do A23 D7 internal areas are always accessed with this waveform 1 bus cycle Clock 61 E ALE Ao A7 Note i As D8 A15 D15 A16 D0 A23 D7 Note When the external data bus is 8 bits wide BYTE H As Ds to A15 D15 operate with the same bus timing as Ao to A7 Fig 3 2 2 Examples of bus timing when software Wait is used BYTE L 7721 Group User s Manual 3 9 CONNECTION WITH EXTERNAL DEVICES 3 3 Ready function 3 3 Ready function Ready function provides the function to facilitate access to external devices that require long access time The microcomputer enters Ready state by input of L level to the RDY pin and retains this state while the level of the RDY pin is at L Table 3 3 1 lists the microcomputer s state in Ready state In Ready st
288. ead and a write cycle it consumes a minimum of 2 bus cycles for 1 unit transfer Figure 13 4 1 shows an example of connecting external memories in 2 bus cycle transfer M37721 Address bus Data bus Ds D15 Data bus Do D7 nos J9JSUEJ sseJppe ppo KJOUJ9UJ SSolppe uo 3 UOIJEUNSEP JaJSUeJ sseJppe ppo KJOUJ9UJ UOIjeursep J9JSUJ TI w o 3 2 D lt 0 v O D Note The external circuit such as an address latch is disregarded Fig 13 4 1 Example of connecting external memories in 2 bus cycle transfer 13 30 7721 Group User s Manual DMA CONTROLLER 1 Register operation in 2 bus cycle transfer 13 4 Operation Figure 13 4 2 shows a basic operation of registers for 1 unit transfer in 2 bus cycle transfer For register values to be specified refer to section 13 5 Single transfer mode through section 13 8 Link array chain transfer mode It is because that these values vary according to continuous transfer modes In 2 bus cycle transfer the data read at a read cycle is maintained temporarily in the DMA latch and the contents of this latch are written to a memory at a write cycle 1 Read cycle DMAC Memory Transfer source address is specified by SARI Note SARI latch Ing Contents of TCRi are updated by decrementer Transfer Note when value read from TCRi is 0 transfer source of 1 data block is terminated Contents of SARi are updated by incrementer
289. eceive mode register Address 3816 b2 b1 b0 Serial I O mode select bits 00 0 Serial l O disabled P8 functions as a programmable I O port Clock synchronous serial I O mode Do not select Do not select UART mode Transfer data length 7 bits UART mode Transfer data length 8 bits UART mode Transfer data length 9 bits Do not select Internal External clock select bit Internal clock External clock Stop bit length select bit m One stop bit Valid in UART mode Note Two stop bits Odd Even parity select bit 0 Odd parity RW Valid in UART mode when 1 Even parity parity enable bit is 1 Note Parity enable bit 0 Parity disabled RW Valid in UART mode Note 1 Parity enabled Sleep select bit 0 Sleep mode terminated Invalid RW Valid in UART mode Note 1 Sleep mode selected Note Bits 4 to 6 are invalid in the clock synchronous serial I O mode They may be either 0 or 1 Additionally fix bit 7 to 0 Fig 11 2 2 Structure of UARTi transmit receive mode register 11 4 7721 Group User s Manual SERIAL I O 11 2 Block description 1 Internal External clock select bit bit 3 Bl Clock synchronous serial I O mode By clearing this bit to O in order to select an internal clock the clock which is selected with the BRG count source select bits bits 0 and 1 at addresses 3416 3C e becomes the count source of the BRGi described later The
290. ected may be different In such a case data is copied from the data bus of a transfer source to that of a transfer destination by using the DMA latch For the combination that data copy may occur data copy delay time taqata must be taken into consideration Table 13 4 6 lists the data flows on the data bus in 1 bus cycle transfer and Table 13 4 7 lists the outputs of the address bus the data bus and the bus control signals in 1 bus cycle transfer 7721 Group User s Manual 13 41 DMA CONTROLLER 13 4 Operation Internal clock ILI LI LI LI LI LL A D AX D 3 LI ALE i AID A 1X D ALE xl ALE A D A XA1X D A Address D Data 4 Transfer term per 1 unit transfer Fig 13 4 7 Bus cycle operation waveforms in 1 bus cycle transfer 13 42 7721 Group User s Manual DMA CONTROLLER 13 4 Operation Table 13 4 6 Data flows on data bus in 1 bus cycle transfer External data I O Transfer Read Write address bus width connection unit of memory Data flow M37721 Data bus Data bus Ds D15 Do D7 Even address 16 bits and 16 bits and Data bus Do D7 Ds D15 Odd address M37721 Data bus Ds D15 Even address Data bus Do D7 Data bus 16 bits Do D7 8 bits Data bus Ds D15 Data bus Do D7 Odd address Note Data is copied from data bus Do D7 to Ds D15 or from data bus Ds D15 to Do D7 in the M37721 s DMAC Note the dat
291. ecuting the WIT instruction after writing to an internal area or an external area three NOP instructions must be inserted to complete the write operation before the WIT instruction is executed Refer to Figure 5 4 1 STA A XXXX Write instruction NOP NOP instruction inserted NOP NOP WIT WIT instruction Fig 5 4 1 NOP instruction insertion example 7721 Group User s Manual 5 11 CLOCK GENERATING CIRCUIT 5 4 Wait mode MEMORANDUM 5 12 7721 Group User s Manual CHAP TIER 6 INPUT OUTPUT PINS 6 1 Overview 6 2 Programmable I O ports 6 3 Examples of handling unused pins INPUT OUTPUT PINS 6 1 Overview 6 2 Programmable I O ports 6 1 Overview Input output pins hereafter called I O pins have functions as programmable I O ports internal peripheral devices s I O pins external buses etc For the basic functions of each I O pin refer to section 1 3 Pin description For the I O functions of the internal peripheral devices refer to relevant sections of each internal peripheral device For the external address bus external data bus bus control signals etc refer to CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES This chapter describes the programmable I O ports and examples of handling unused pins 6 2 Programmable I O ports The programmable I O ports have direction registers and port registers in the SFR area Figure 6 2 1 shows the memory map of direction registers and por
292. ed Level 1 Level 2 B Au Level 3 Level 4 Level 5 Level 6 Level 7 beeen enna anne 3 Interrupt request bit 0 No interrupt requested 1 Interrupt requested 7 to 4 Nothing is assigned Undefined b7 b6 b5 b4 b3 b2 bl bO INTo to INT2 interrupt control registers Addresses 7D16 to 7F16 Interrupt priority leve select bits Level O Interrupt disabled Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 3 Interrupt request bit Note 0 No interrupt requested 1 Interrupt requested T0 22220c22 2 c 4 Polarity select bit 0 Interrupt request bit is set to 1 I 00008 00 o002 O 0 0 08 at H level when level sense is selected this bit is set to 1 at falling edge when edge sense is selected Interrupt request bit is set to 1 at L level when level sense is selected this bit is set to 1 at rising edge when edge sense is selected 5 Level sense Edge sense 0 Edge sense select bit 1 Level sense zc p C IU M EM M ME 7 6 Nothing is assigned Note The interrupt request bits of INTo to INT2 interrupts are invalid when the level sense is selected F sss ew ee lm rm1l 1 kckckkcccc cCoc01cr1 2 292 211 0 7 l 701 01 Fig 7 3 2 Structures of interrupt control register 7 6 7721 Group User s Manual INTERRUPTS 7 3 Interrupt control 7 3
293. ed set this bit example for registers relevant to array chain transfer mode 2 7721 Group User s Manual 13 73 DMA CONTROLLER 13 7 Array chain transfer mode When selecting external DMA source From preceding Figure 13 7 4 ZU of priority level and TC pin and setting DMAi request bit to 0 b7 bO ojojolo DMAC control register L Address 6816 Priority select bit 0 Fixed 1 Rotating TC pin validity bit 0 Invalid P103 pin functions as a programmable l O port 1 Valid NN P105 pin functions as TC pin DMAO request bit DMA1 request bit DMA2 request bit DMAS request bit 0 No request TX ES di b7 bO N DMAC control register H Address 6916 Software DMAi request bit Valid in software DMA source selected Bit 0 Channel 0 Bit 1 Channel 1 Bit 2 Channel 2 Bit 3 Channel 3 DMAO enable bit DMA1 enable bit DMA2 enable bit DMAS3 enable bit 0 Disabled 1 Enabled P When selecting internal DMA source When selecting internal DMA source except software BERR REPRE RRR RRR RRR RRR Kee When selecting software 7 DMA request Inputting DMA request signal to DMAREQi pin k b7 bO Software DMAO request bit Software DMA1 request bit Software DMA2 request bit Software DMAS request bit When writing 1 DMA request is generated Ne
294. ed in the period from when a value is set into the timer Bi register with the counter stopped until the counter starts counting the set value is correctly read out omes TT Do Tees Head value He 2 1 0 fnt n Reload register s contents Time Fig 9 3 4 Reading timer Bi register 7721 Group User s Manual 9 13 TIMER B 9 4 Event counter mode 9 4 Event counter mode In this mode the timer counts an external signal Refer to Table 9 4 1 Figure 9 4 1 shows the structures of the timer Bj mode register and the timer Bj register in the event counter mode Table 9 4 1 Specifications of event counter mode ltem Count source Count operation Division ratio Count start condition Count stop condition Interrupt request occurrence timing TBjin pin s function Head from timer Bj register Write to timer Bj register 9 14 Specifications External signal input to the TBjin pin he count source s valid edge can be selected from the falling edge the rising edge and both of the falling and rising edges by software Countdown When a counter underflow occurs reload register s contents are reloaded and counting continues 1 n 1 When the count start bit is set to 1 When the count start bit is cleared to 0 When a counter underflow occurs Count source input Counter value can be read out While counting is stopped When a value is written to the timer Bj register it is written t
295. egister Addresses 3316 3216 UART1 transmit buffer register Addresses 3B16 3A16 b15 b8 b7 b0 SS 3 UARTO transmit receive control register 0 Address 3416 Z UART1 transmit receive control register 0 Address 3C 6 CTS RTS selecl bit 0 CTS function selected 1 RTS function selected CTS function disabled b7 bO Set transmit data here BRG count source select bits d A UARTO transmit receive control register 1 Address 3516 Q ais UART1 transmit receive control register 1 Address 3D16 1 0 f64 b7 bO 1 1 f512 ptt Tt tt yt Transmit enable bit 1 Transmission enabled Xs Transmission starts In the case of selecting the CTS function transmission starts when the CTSi pin s input level is L Fig 11 4 3 Initial setting example for relevant registers when transmitting 7721 Group User s Manual 11 35 SERIAL I O 11 4 Clock asynchronous serial I O UART mode When using interrupts A UARTI transmit interrupt request occurs when the UARTi transmit buffer register becomes empty When not using interrupts Checking state of UARTi transmit buffer register N UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 UARTI transmit interrupt b7 bO ptt tt tt hii Transmit buffer empty flag 0 Data present in transmit buffer register 1 No data present in transmit buffer registe
296. egister 3 SAR3 Transfer counter register 3 TCR3 Destination address register 3 DAR3 jae Data bus Even Data bus Odd LJ Microcomputer s internal bus DMAC s internal bus Fig 13 2 1 DMAC block diagram 1 DRAMC DRAM refresh BIU DES request Hold function BUS REQUEST Hold Hold request rce DMAREQO Software Timer AO Timer A1 control circuit E Bus access Channel 1 Channel 2 Channel 3 BUS REQUEST Request sou selection Channel priority level determination DMAACKO DMAACK1 DMAACK2 DMAACK3 Acknowledge signal generation Fig 13 2 2 DMAC block diagram 2 13 6 7721 Group User s Manual DMA CONTROLLER 13 2 Block description 13 2 1 Bus access control circuit In the M37721 the bus is used by DRAMC Hold function DMAC and CPU When each request of DRAM refresh Hold and DMA is generated each of DRAMC Hold function and DMAC issues its bus request to the bus access control circuit in DMAC Refer to Figure 13 2 2 Table 13 2 1 lists the bus request generating sources Table 13 2 1 Bus request generating sources Bus request BUS REQUEST DRAM refresh request Bus request generating source DRAMC Generated by an underflow of the refresh timer BUS REQUEST Hold request Hold Generated by L level input to the HOLD pin BUS REQUEST DMA request DMAC Generated by a DMA request source The bus access control circuit relinquis
297. el which is sent from the preceding comparator X in Figure 7 5 2 the interrupt with the higher priority level is sent to the next comparator Z in Figure 7 5 2 Initial comparison value of X is 0 For an interrupt which is not requested the comparison is not performed and the priority level which is sent from the preceding comparator is forwarded to the next comparator as it is When the two priority levels are found the same by comparison the priority level which is sent from the preceding comparator is forwarded to the next comparator Accordingly when the same priority level is set by software the interrupt priority levels are handled as follows DMA3 gt DMA2 gt DMA1 gt DMAO gt A D conversion gt UART1 transmit gt UART1 receive gt UARTO transmit gt UARTO receive gt Timer B2 gt Timer B1 gt Timer BO gt Timer A4 gt Timer A3 gt Timer A2 gt Timer A1 gt Timer AO gt INT gt INT gt INTo Among the multiple interrupt requests sampled at the same time one request with the highest priority level is detected by the above comparison Then this highest interrupt priority level is compared with the processor interrupt priority level IPL When this interrupt priority level is higher than the processor interrupt priority level IPL and the interrupt disable flag 1 is 0 the interrupt request is accepted A interrupt request which is not accepted here is held until it is accepted or its interrupt request b
298. elected ANe selected ANs selected AN4 selected ee ANs selected ANe selected AN7 selected Note 2 A D operation mode select bits 0 0 One shot mode 0 1 Repeat mode 1 0 Single sweep mode 1 1 Repeat sweep mode 5 Trigger select bit 0 Internal trigger 1 External trigger A D conversion siart bit 0 Stop A D conversion 1 Start A D conversion A D conversion frequency 0 f2 divided by 4 0 AD select bit 1 fe divided by 2 Notes 1 These bits are ignored in the single sweep and repeat sweep mode They may be either 0 or 1 2 When an external trigger is selected the AN7 pin cannot be used as an analog input pin 3 Writing to each bit except bit 6 of the A D control register must be performed while the A D converter halts Fig 12 2 2 Structure of A D control register 1 Analog input select bits bits 2 to O These bits are used to select an analog input pin in the one shot mode and repeat mode Pins which are not selected as analog input pins function as programmable I O ports These bits must be set again when the user switches the A D operation mode to the one shot mode or repeat mode after A D conversion is performed in the single sweep mode or repeat sweep mode 2 4 7721 Group User s Manual A D CONVERTER 12 2 Block description 2 3 4 Trigger select bit bit 5 This bit is used to select the source of trigger occurrence Refer to section 3 A D
299. ement timing of RDY pin s input level 01 E ZZ E EL level stopped by software Wait 1Q GED E L level stopped by Ready function e 2Q 2 CS2 RDY AC04 AC74 AC32 S q pig lt P tho 1 RDY propagation delay time tsu RDY 61 Fig 16 1 10 Example of using Ready function software Wait 16 14 7721 Group User s Manual APPLICATION 16 1 Memory connection When data is output from external memory before falling edge of E signal Because the external memory outputs data before the falling edge of the E signal there is a possibility that the tail of address collides with the head of data In such a case generate the external memory read signal OE by using E Refer to Figure 16 1 11 External memory output enable signal Read signal Address output External memory data output e Specifications of external memory ten OE Note Make sure that d 2 0 is satisfied when generating the external memory read signal OE Fig 16 1 11 Example of making data output timing delayed When using external memory that outputs data for more than tpz e oiziuz after rising edge of E signal Because the external memory outputs data for more than tpzxe p zonz after the rising edge of the E signal there is a possibility that the tail of data collides with the head of address In such a case try to carry out the following Cut the tail of data output from the m
300. emory by using for example a bus buffer Use the Mitsubishi s memory chips that can be connected without a bus buffer Figures 16 1 12 to 16 1 15 show examples of using bus buffers and the timing charts Table 16 1 6 lists the Mitsubishi s memory chips that can be connected without a bus buffer When using one of these memory chips timing parameters tor and taisos listed below are guaranteed Accordingly no bus buffer is necessary for the system where the external memory s read signal OE goes high within tpzxe piz 0Hz toF Or taisoe ns after the rising edge of the E signal Table 16 1 6 Mitsubishi s memory chips that can be connected without bus buffers Memory tpe tasoe Maximum Flash memory M5M28F101AP FP J VP RV 85 10 15 ns M5M28F102AFP J VP 85 10 Guaranteed as kit M5M5256DP FP KP VP RV 45LL 45XL 55LL 55XL Note 70LL 70XL SRAM M5M5278DP J 12 6 ns M5M5278DP FP J 15 15L 7 ns M5M5278DP FP J 20 20L 8 ns Note tor or tais og listed above is guaranteed when these memory chips are connected with the M37721 When the user wants specifications of these memory chips add a comment tor tdisi oe 15 ns microcomputer and kit 7721 Group User s Manual 16 15 APPLICATION 16 1 Memory connection M37721 Address bus AC245 As Ds A15 D15 A B Data bus odd DIR OC A16 Do A23 D7 Data bus even aa E ACSR a d 03 o TEM W D i ix Circuit condi
301. en connecting a ceramic resonator quartz crystal oscillator between pins Xin and Xour The circuit constants such as Rf Rd Cin and Cour shown in Figure 5 1 1 depend on the resonator oscillator These values shall be set to the values recommended by the resonator oscillator manufacturer 5 1 2 Externally generated clock input example M37721 Figure 5 1 2 shows an input example of the clock which is externally generated The external clock must be input from the Xin pin and the Xovr pin must be left open Fig 5 1 1 Connection example using resonator oscillator M37721 Open Externally generated clock vot LJ LE LI Vss Fig 5 1 2 Externally generated clock input example 5 2 7721 Group User s Manual CLOCK GENERATING CIRCUIT 5 2 Clocks 5 2 Clocks Figure 5 2 1 shows the clock generating circuit block diagram f2 fte Operation clock for fea internal peripheral devices Interrupt request f512 Watchdog timer 512 d frequency select bit STP instruction f O 32 Watchdog e Ready request CPU wait request from BIU Bus request DRAMC Hold DMAC J CPU Central Processing Unit BIU Bus Interface Unit Watchdog timer frequency select bit Bit 0 at address 6116 Note This signal is generated when the watchdog timer s most significant bit becomes 0 Fig 5 2 1 Clock generating circuit block diagram 7721 Group User s Manual 5 3 CLOCK GENERATING CIRCUIT 5 2 Clo
302. enerated at the following timings it is not in time to the next bus request sampling amp Therefore DMAC returns the right to use bus to the CPU Then DMAC regains the right and restarts the DMA transfer Except for the last 1 unit transfer 1 bus cycle transfer is selected without Wait e Except for the last 1 unit transfer 1 bus cycle transfer is selected with Wait In addition a time of 0 5 cycle of 6 is less than tsu DRQ 91 Fig 13 4 12 Conditions for performing DMA transfers of the same channel continuously 13 52 7721 Group User s Manual DMA CONTROLLER 13 4 Operation 2 When a DMA transfer of another channel is subsequently performed In the cycle steal transfer mode it takes 1 5 cycles of from the generation of a DMA request until that of a BUS REQUEST DMAC Therefore if a DMA request of another channel is generated during a DMAi transfer in the cycle steal mode either one of the following two cases occurs depending on its timing of request generation e The DMAC performs the DMA transfer subsequently without returning the right to use bus e After returning the right to use bus to the CPU once the DMAC regains the right and performs the DMA transfer 1 unit transfer Bus request sampling DMA transfer is subsequently performed if DMAi After returning the right to use
303. equires at least 13 cycles of internal clock 4 Figure 7 7 2 shows the INTACK sequence timing After the INTACK sequence is completed the instruction execution starts from the start address of the interrupt routine Interrupt request is accepted Interrupt request c Time Jneucin instruction INTACK sequence Instructions in interrupt routine Dp On UI Interrupt priority level detection time Time from the occurrence of an interrupt request until the instruction execution which is in progress at that time is completed Time from when execution of an instruction next to begins Note until the instruction execution which is in progress at completion of interrupt priority level detection Note At this time detection of interrupt priority level begins Time required to execute the INTACK sequence 13 cycles of at minimum Fig 7 7 1 Sequence from acceptance of interrupt request until execution of interrupt routine 7721 Group User s Manual 7 13 INTERRUPTS 7 7 Sequence from acceptance of interrupt request until execution of interrupt routine When stack pointer S s contents are even and no Wait Internal clock OcPu P Xo Aoo X o X o Xo Xo Xoo X vm X vm Interrupt disable flag INTACK sequence CPU standard clock Not used High order 8 bits of CPU internal address bus S Contents of stack pointer S Middle order 8 bits of CPU internal address bus XX1e Low order
304. er Transfer timing Timing at which counter is cleared to 000016 Count start bit Timer Bj interrupt request bit Cleared to 0 when interrupt request is accepted or ft Timer Bj overflow flag e ear py collate D Counter is initialized by completion of measurement Counter overflow Fig 9 5 4 Operation during pulse width measurement 9 24 7721 Group User s Manual TIMER B 9 5 Pulse period Pulse width measurement mode Precautions for pulse period pulse width measurement mode 1 A timer Bj interrupt request is generated by the following sources Input of measured pulse s valid edge Counter overflow When the overflow generates the interrupt request the timer Bj overflow flag is set to 1 After reset the timer Bj overflow flag is undefined When a value is written to the timer Bj mode register with the count start bit 1 this flag is cleared to O at the next count timing of the count source An undefined value is transferred to the reload register when the first valid edge is input after the counter starts counting In this case no timer Bj interrupt request occurs The counter value at start of counting is undefined Accordingly a timer Bj interrupt request may be generated by an overflow immediately after the counter starts counting If the contents of the measurement mode select bits are changed after the counter starts counting the timer
305. er 11 30 7721 Group User s Manual SERIAL I O 11 4 Clock asynchronous serial I O UART mode 11 4 Clock asynchronous serial I O UART mode Table 11 4 1 lists the performance overview in the UART mode and Table 11 4 2 lists the functions of I O pins in this mode Table 11 4 1 Performance overview in UART mode Item Transfer data Start bit 1 bit format Character bit Transfer data 7 bits 8 bits or 9 bits Parity bit O bit or 1 bit Odd or even can be selected bit or 2 bits Transfer rate When selecting internal clock BRGi s output divided by 16 When selecting external clock Maximum 312 5 kbps 4 types Overrun Framing Parity and Summing Presence of error can be detected only by checking error sum flag Functions Error detection Table 11 4 2 Functions of I O pins in UART mode Pin name Functions Method of selection TxDi P83 P87 Note 1 Serial data output Cannot be used as a programmable I O port even when performing only reception RxDi P82 P86 Serial data input Port P8 direction register s corresponding bit 0 Can be used as a programmable I O port when performing only transmission Programmable I O port Internal External clock select bit 0 internal External clock select bit 1 CTS input CTS RTS function select bit 0 RTS output CTS RTS function select bit 1 CLK P81 P8s CTS RTSi P80 P84 Note 2 Port P8 direction
306. er Address E16 NSS See Output L level Lights go out si b0 ojojojojo jo o o Port P7 register Address F16 Output L level All digits OFF Mu l oli b0 Port P7 direction register Address 1 116 Output mode b15 b8 b7 bO _ TimerB0register Addresses 5116 5016 x c Digit switch interval b7 b0 x x x 0 0 Timer BO mode register Address 5B16 Timer mode Count source b7 b0 0 0 0 Timer BO interrupt control register Address 7A16 Interrupt disabled b7 b0 A Count start register Address 4016 Timer BO count started b7 bO o DMAC control register L Address 68 6 DMAS request bit 0 b7 bO a BMAC control register H Address 6916 DMAS3 enabled X It may be 0 or 1 Fig 16 2 13 Initial setting example for relevant register 2 7721 Group User s Manual 16 55 APPLICATION 16 3 Comparison of sample program execution rate 16 3 Comparison of sample program execution rate Sample program execution rates are compared in this paragraph The execution time ratio depends on the program or the usage conditions 16 3 1 Differences depending on data bus width and software Wait Internal areas are always accessed with data bus of which width is 16 bits and no software Wait In the external areas the external data bus width and software Wait are selectable Tabl
307. er mode select bit 0 Burst transfer mode 1 Cycle steal transfer mode bO EN NI Transfer source address direction select bits 0 0 Fixed 0 1 Forward 1 0 Backward 1 1 Do not select Transfer destination address direction select bits 00 Fixed e DMAO control register DMAt control register DMA2 control register DMAS control register ON DMA request source select bits 0000 External source DMAREQI Software DMA source Timer AO Timer A1 Timer A2 Timer A3 Timer A4 Edge sense Level sense select bit Note Do not select 0 Edge sense 1 Level sense DMAACKi validity bit 0 Invalid 1 Valid n cn cl Ce S COO OC OC Oo OO O O O O Address 1FCE16 Address 1FDE16 Address 1FEE16 Address 1FFE16 Timer BO Timer B1 Timer B2 UARTO receive UARTO transmit UARTI receive UARTI transmit A D conversion 0 1 Forward 1 0 Backward 1 1 Do not select to 0 DMAO mode register H Address 1FCDi6 DMA1 mode register H Address 1FDDs e DMA2 mode register H Address 1FED16 DMAS mode register H Address 1FFDi6 Transfer direction select bit Used in 1 bus cycle transfer 0 From memory to I O 1 From I O to memory I O connection select bit Valid in 1 bus cycle transfer 0 Data bus Do D7 or Do D15
308. er reset Underfined immediately after H ways T atreadng reset Always undefined at reading NN 0 immediately after reset Fix this bit to 0 Address Register name Access characteristics T State immediately after reset a 016 116 216 316 416 516 616 716 816 916 A16 Port P4 register 2 0 0 0 B16 Port P5 register C16 Port P4 direction register D16 Port P5 direction register E16 Port P6 register F16 Port P7 register 1016 Port P6 direction register 1116 Port P7 direction register 1216 Port P8 register 1316 Port P9 register 1416 Port P8 direction register 1516 Port P9 direction register jojojojojo ojoJo x 006 1616 Port P10 register 1716 1816 Port P10 direction register 00066 19s 1A16 Pulseoutputdataregistero WO 1B16 1Cig Pulse output data register 1 1D16 1E16 A D control register 1F16 A D sweep pin select register L FL FS RW ES Fig 4 1 4 State of SFR and internal RAM areas immediately after reset 1 7721 Group User s Manual 4 5 RESET 4 1 Hardware reset Address Register name Access characteristics State immediately after reset b7 bO b7 bO 2016 A D register 0 2116 2216 A D register 1 2316 2416 A D register 2 2516 2616 A D register 3 2716 2816 A D register 4 2916 2A16 A D register 5 2B16 2C16 A D register 6 2D16 2E16 A D register 7 oF 16 3016 UARTO transmit receive mode register 0016 3
309. er source sequence eee memory I O memory sequence memory Fixed JN Forward Low order Data 1 High order Low order Data 2 High order Low order Data 3 Backward ok E Transfer start 7721 Group User s Manual 13 45 DMA CONTROLLER 13 4 Operation Table 13 4 9 Address directions in 1 bus cycle transfer and examples of transfer results 2 External data bus width 16 bits External data bus width 16 bits or 8 bits Address direction Transfer unit 16 bits Transfer unit 8 bits Transfer Transfer Data arrangement on Data arrangement on source destination Transfer source Transfer transfer destination Transfer source Transfer transfer destination I O memory I O Sequence memory transfer result I O SEQUENCE memory transfer result Fixed Low order Low order Data x Data Data High order High order Forward Low order Low order Data High order Low order Data Low order Data Backward Low order Data High order Low order Data High order Low order Data High order x Transfer start 13 46 7721 Group User s Manual DMA CONTROLLER 13 4 Operation Precautions for 1 bus cycle transfer Is The area that overlaps with internal RAM and SFRs must not be assigned to an external memory When the contents in the overlapped area are read the data of internal RAM or SFRs and that of external memory are simultaneously placed o
310. eration Countdown When the counter value becomes 000016 reload register s con tents are reloaded and counting stops f a trigger occurs during counting reload registers contents are reloaded and counting continues Output pulse width H n aan b S n Timer Aj register s set value Count start condition When a trigger occurs Note Internal or external trigger can be selected by software Count stop condition e When the counter value becomes 000016 When the count start bit is cleared to 0 Interrupt request occurrence timing When counting stops TAjin pin s function Programmable I O port or trigger input TAjour pin s function One shot pulse output Read from timer Aj register An undefined value is read out Write to timer Aj register e While counting is stopped When a value is written to the timer Aj register it is written to both of the reload register and counter While counting is in progress When a value is written to the timer Aj register it is written only to the reload register Transferred to the counter at the next reload time Note The trigger is generated with the count start bit 1 7721 Group User s Manual 8 29 TIMER A 8 5 One shot pulse mode b7 b6 b5 b4 b3 b2 bi b0 lof lililo Timer Aj mode register j 2 to 4 Addresses 5816 to 5A16 sit Biname Functions arrese RW EAE b1 bO 1 0 One shot pulse mode 0 0 Writing 1 to one shot start
311. erature range Device structure Package Output current UART or clock synchronous serial I O X 2 8 bit Successive approximation method X 1 8 channels 12 bits X 1 4 channels Maximum transfer rate 12 5 Mbytes sec at f Xin 25 MHz 1 bus cycle transfer Maximum transfer rate 6 25 Mbytes sec at f Xin 25 MHz 2 bus cycle transfer CAS before RAS refreshing method 4 bits X 2 channels or 6 bits X 1 channel 2 bits X 1 channel 3 external 20 internal priority levels O to 7 can be set for each interrupt with software Built in externally connected to a ceramic resonator or a quartz crystal oscillator 5 V 10 96 135 mW at f Xin 25 MHz typ Input Output withstand voltage 5 V 5 mA Maximum 16 Mbytes 20 C to 85 C CMOS high performance silicon gate process 100 pin plastic molded QFP 1 2 7721 Group User s Manual DESCRIPTION 1 2 Pin configuration 1 2 Pin configuration Figure 1 2 1 shows the M37721S2BFP pin configuration SSA SSAV re N E C1 Eq I EX oo E no s BJA co E EJ N lt gt SH V NV z d OOAY 99A lt gt 9S1u S 19 8d 8 gt W19 8d amp gt GQxt4 28d lt gt S1u Sl19 8d 8 lt QXL 8d lt 10 58d gt Q u 8d 3 Co P67 RTP13 lt gt P6e RTP12 lt gt P6s RTP11 lt gt P64 RTP10 lt gt P63 RT P03 lt gt P62 RTPO2 lt gt 6 P6 RTPO1 lt gt P60 RTPOo lt gt
312. erefore voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports After reset immediately set these ports to the output mode Software reliability can be enhanced by setting the contents of the above ports direction registers periodically This is because these contents may be changed by noise a program runaway which occurs owing to noise etc 2 For unused pins use the shortest possible wiring within 20 mm from the microcomputer s pins 3 This applies when a clock externally generated is input to the Xm pin When setting ports to input mode When setting ports to output mode P43 P47 P5 P10 P43 P47 P5 P10 Left open STO SI Left open Left open Left open Left open CNVss can be connected to Vcc too Fig 6 3 1 Examples of handling unused pins 7721 Group User s Manual 6 7 INPUT OUTPUT PINS 6 3 Examples of handling unused pins MEMORANDUM 6 8 7721 Group User s Manual CHAPTER 7 INTERRUPTS 7 1 Overview 7 2 Interrupt sources 7 3 Interrupt control 7 4 Interrupt priority level 7 5 Interrupt priority level detection circuit 7 6 Interrupt priority level detection time 7 Sequence from acceptance of interrupt request until execution of interrupt routine 7 8 Return from interrupt routine 7 9 Multiple interrupts 7 10 External interrupts INTi interrupt 7 11 Precautions for interrupts INTERRUPTS 7 1
313. ess 00000016 00000116 00000216 00000316 00000416 00000516 00000616 00000716 00000816 00000916 00000A16 00000B16 00000C16 00000D16 00000E16 00000F16 00001016 00001116 00001216 00001316 00001416 00001516 00001616 00001716 00001816 00001916 00001A16 00001B16 00001C16 00001D16 00001E16 00001F16 00002016 000021 16 00002216 00002316 00002416 00002516 00002616 00002716 00002816 00002916 00002A16 00002B16 00002C16 00002D16 00002E16 00002F 16 00003016 00003116 00003216 00003316 00003416 00003516 00003616 00003716 00003816 00003916 00003A16 00003B16 00003C16 00003D16 00003E16 00003F16 Port P4 register ee C PulseoutputdataregisterO Pulse output data register 0 Pulse output data register 1 A D control register A D sweep pin select register A D register O rr r ee 3 K gt A D register 7 UARTO transmit receive mode register UARTO baud rate register BRGO UARTO transmit buffer register UARTO transmit receive control register 1 UART1 transmit receive mode register UART1 baud rate register BRG1 UART1 transmit buffer register UART1 transmit receive control register 0 UART1 transmit receive control register 1 UART1 receive buffer register UARTO transmit receive control register 0 UARTO receive buffer register Fig 2 4 2 SFR area s memory map 1 2 20 Address 00004016 00004116 000 0 00004216
314. ess implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the informat
315. f the accumulator B to the direct 1421412 page register 5B TBS S B Transmits the contents of the accumulator B to the stack 42 4 2 pointer 1B _ j Jj jJ j j TBX XB Transmits the contents of the accumulator B to the index 42 4 2 register X AA TBY Y B Transmits the contents of the accumulator B to the index 42 4 2 register Y A8 TDA A DPR Transmits the contents of the direct page register to the 7B 2 1 accumulator A Be DPR Transmits the contents of the direct page register to the 42 4 2 accumulator B 7B je eene Transmits the contents Transmits the contents of he stack pointer to the accumulator A the stack pointer to the accumulator A 3 2 p Transmits the contents of the stack pointer to the accu 4 2 mulator B XS Transmits the contents of the stack pointer to the index BA 2 1 register X Transmits the contents of the index register X to the ac 8 21 cumulator A Transmits the contents of the index register X to the ac T 2 cumulator B a the contents of the index eo ete nie a sa X to the stack 9A 2 WENN a emer Transmits the contents of the index register X to the index 2 1 register Y AY Transmits the contents of the index register Y to the ac 2 1 cumulator A TYB BY Transmits the contents of the index register Y to the ac 42 4 2 cumulator B 98 TYX Xc Y Transmits the contents of the index register Y to the index BB 2 1 register X I __ Stops the interna clock een
316. falling edge of ACK signal until falling edge of BUSY signal T3 in Figure 16 2 2 Fig 16 2 4 Initial setting example for relevant register 2 16 46 7721 Group User s Manual APPLICATION 16 2 Examples of using DMA controller LT Tilololololi DMAO control register Address 1FCE16 DMA request source External source DMAREQO Edge sense selected DMAACKO pin Valid b7 bO ett ft fol ff DMAO interrupt control register Address 6C16 Interrupt priority level any of 0012 to 1112 b7 b0 4 4 Count start register Address 4016 Timer A2 count start Timer A3 count start b7 bO Jo DMAC control register L Address 68 6 DMAO request flag is set to 0 sl b0 1 DMAC control register H Address 69 6 DMAO enabled b7 bO 10 Port P4 register Address Ate P43 output L level Fig 16 2 5 Initial setting example for relevant register 3 7721 Group User s Manual 16 47 APPLICATION 16 2 Examples of using DMA controller 16 2 2 Example of stepping motor control The following is an example where the slow up or slow down control for the stepping motor is performed by using DMA1 DMA2 and RTPO 1 Specifications DMA1 transfers the stepping motor s phase output data from the phase output data table to the RTPO pulse output data register Refer to Figure 16 2 6 and Table 16 2 1 DMA transfers the step time f
317. fer clock In the UART mode the BRGi is always valid and the BRGi s output divided by 16 becomes the transfer clock The data which is written to the UARTi baud rate register BRGi is written to both the timer and the reload register whether transmission reception is in progress or not Accordingly writing to these register must be performed while transmission reception is stopped Figure 11 2 10 shows the structure of the UARTi baud rate register BRGi Figure 11 2 11 shows the block diagram of transfer clock generating section UARTO baud rate register Address 3116 UART1 baud rate register Address 3916 7 to 0 Can be set to 00 e to FF e Undefined WO Assuming that the set value n BRGi divides the count source frequency by n 1 Note Writing to this register must be performed while the transmission reception halts Use the LDM or STA instruction for writing to this register Fig 11 2 10 Structure of UARTi baud rate register BRGi Clock synchronous serial I O mode i u2 o fi L BRGi e Transfer clock for transmit operation fEXT Transfer clock for receive operation UART mode Transfer clock for transmit operation Transfer clock for receive operation fi o fi Clock selected by BRG count source select bits fz fie fe4 or f512 fext Clock input to CLKi pin external clock Fig 11 2 11 Block diagram of transfer clock generating section 7721 Group Use
318. fer mode level sense 13 20 7721 Group User s Manual DMA CONTROLLER 13 3 Control 13 3 3 Channel priority levels When the DMA enable bits of several channels are 1 and their DMA request bits are set to 1 the request of the channel with the highest priority is accepted first The fixed or rotating channel priority can be selected by the priority select bit bit O at address 6816 The priority levels themselves cannot be specified arbitrary The channel priority levels are determined after the DMA requests are determined 1 2 Fixed priority The fixed priority is selected when the priority select bit bit O at address 6816 0 In the fixed priority the channel priority levels are as follows channel 0 gt channel 1 gt channel 2 gt channel 3 Rotating priority The rotating priority is selected when the priority select bit 1 After reset the priority levels are the same descending order as in the fixed priority channel 0 gt channel 1 gt channel 2 gt channel 3 Then after every normal termination of a DMA transfer the priority levels rotate in such a way that the lowest priority is given to the channel having been performed When DMA transfer is forced into termination the channel priority levels does not rotate Figure 13 3 1 shows an example of determining the channel priority levels 7721 Group User s Manual 13 21 DMA CONTROLLER 13 3 Control Priority leve
319. fer of right to use bus This is the period in which the bus is not used so that not a new address but the address which was output immediately before is output again Notes 1 Clock 1 has the same polarity and the same frequency as o Timing of signals to be input from or output to the external is ordained on the basis of clock 61 2 Bus request Hold and bus request sampling are internal signals Fig 3 4 1 Timing of acceptance of Hold request and termination of Hold state 1 7721 Group User s Manual 3 13 CONNECTION WITH EXTERNAL DEVICES 3 4 Hold function When inputting L level to HOLD pin while bus is used when data access is completed with 1 bus cycle State when inputting L level to HOLD pin External data bus Data length External data bus width es ee _ Used 16 Access beginning at even address IE Address A D External address bus Floating External data bus KX Data 2 Address B MNEBE o TIL BLE BHE HOLD Bus request Hold Note 3 Bus request sampling Note 3 STO Hold state lt lt Bus in lt j lt q p Bus in use USE Transfer of Transfer of right to use bus right to use bus When a Hold request is accepted not a new address but the address which was output immediately before is output again Notes 1 The above diagram shows the case of no Wait 2 Clock o1 has the
320. fer parameter Note Transfer source s transfer start address DARi Transfer parameter Note Transfer destination s transfer start address TCRi Transfer parameter Byte number of transfer data SARi latch Transfer parameter Start address of next transfer parameter memory DMAi request bit 0 Only in cycle steal transfer mode 1 unit transfer Refer to section 13 4 Operation Burst Edge Burst Level L Cycle steal Requested Transfer completion of 1 block Burst Edge Burst Level L Cycle steal Requested DMAi request bit Transfer completion of all blocks SARi latch 0 0 Burst Level H Cycle steal No request Y Completion TC L output Note DMAi request bit DMAi interrupt request bit 1 DMAi enable bit 0 0 Note When TC pin validity bit is 1 Burst Level H Cycle steal No request DMAi request bit 0 Only in burst transfer mode edge sense Burst Edge In burst transfer mode edge sense Burst Level L In burst transfer mode level sense with DMAREQi pin s input level L Burst Level H In burst transfer mode level sense with DMAREQi pin s input level H Cycle steal Requested In cycle steal transfer mode with any request of DMA0 3 Cycle steal No request In cycle steal transfer mode with no request of DMA0 3 SARi latch indicates the start address of the transfer parameter memory of the next
321. fined Transition of right to use bus Refresh cycle Transition of right to use bus lt gt lt gt lt gt Fig 14 4 1 Waveform example of DRAM control signals 7721 Group User s Manual 14 9 DRAM CONTROLLER 14 4 DRAMC operation 14 4 2 Refresh request When the DRAM validity bit is set to 1 the refresh timer starts counting down The count source is fie When the contents of the refresh timer reach 00 e a refresh request occurs The refresh timer reloads the contents of address 6616 and continues counting Refresh requests are sampled as bus requests DRAMC by using the bus access controller As soon as a refresh request is acknowledged by sampling the following is performed because DRAM refresh has the highest priority in using the bus However when the CPU or DMAC uses the bus no bus request is sampled until the CPU or DMAC releases the bus Therefore in a period from when a refresh request occurs until DRAM refresh is performed the delay listed in Table 14 4 1 occurs depending on the refresh request generating timing Figures 14 4 2 and 14 4 3 show refresh delay time examples when CPU is operating and during DMA transfer For a bus request refer to 13 2 1 Bus access control circuit When the refresh request is accepted the right to use the bus is passed to DRAM refresh 1 cycle of Q0 Both of the output levels of ST1 and STO are L The bus status is indicated as O 0 The RAS and
322. flag and error flags do not change and a UARTi receive interrupt request does not occur The following shows an usage example of the sleep mode when the transfer data is 8 bits length Set the same transfer data format for the master and slave microcomputers Select the sleep mode for the slave microcomputers Transmit data which has 1 in bit 7 and the address of the slave microcomputer to be communicated in bits O to 6 from the master microcomputer to all slave microcomputers All slave microcomputers receive data of step At this time a UARTi receive interrupt request occurs For all slave microcomputers check in the interrupt routine whether bits 0 to 6 in the receive data match their own addresses For the slave microcomputer of which address matches bits 0 to 6 in the receive data terminate the sleep mode Do not terminate the sleep mode for the other slave microcomputers By performing steps to the microcomputer which performs transfer is specified Transmit data which has 0 in bit 7 from the master microcomputer Only the microcomputer specified in steps to can receive this data The other microcomputers do not receive this data By repeating step transfer can be performed between two specific microcomputers continuously When communicating with another microcomputer perform steps to in order to specify the new slave microcomputer Data is transferred between the master
323. following Table Undefined Pulse output mode select bit E Pulse mode 0 Pulse mode 1 Note When using the P60 P67 pins as the pulse output pins for real time output set the corresponding bits of the port P6 direction register address 10 6 to 1 P67 RTP13 P66 RTP 12 P6s5 RTP1 P64 RTP10 P63 RTPOs P62 RTPO2 P6 RTPO P6o RTPOo Port Port P67 RTP13 P66 RTP 12 P6s RTP1 P64 RTP 10 P63 RTPOs P62 RTPO2 P61 RTPO P6o RTPOo Port RTP P67 RTP13 P66 RT P12 P6s RTP1 P64 RTP10o P63 RTPOs P62 RTPO2 P6i RTPO P6o RTPOo RTP Port P67 RTP13 P66 RTP12 P6s5 RTP11 P64 RTP 10 P63 RTPOs P62 RTPO2 P6 RTPO P6o RTPOo RTP RTP When pulse mode 1 is selected OO 666666 OOOO OOOO P67 RTP13 P66 RTP12 P6s RTP1 P64 RTP1o P63 RTPOs P62 RTPO2 P61 RTPO1 dn wp Port Port This functions as a programmable I O port RTP This functions as a pulse output pin OO 660066 0006 OOOO P67 RTP13 P6s RTP12 P6s RTP1 P64 RTP1o P63 RTPOs P62 RTPO2 P61i RTPOi EE Mti gt Port 66 666654 0006 6000 P67 RTP13 P66 RTP12 P6s5 RTP11 P64 RTP1o P6s RTPO0s P62 RTPO P61 RTP01 ada SR gt RTP OO OOOOOO OOOO 0000 P67 RTP13 P66 RT P12 P6s5 RTP11 P64 RTP1o P63 RTPOs P62 RTPO P61i RTPO ERI M gt RTP 7721 Group User s Manual 17 29 APPENDIX Appendix 3 Control registers DRAM control register b
324. from the CLKi pin Setting for relevant registers Select an internal clock bit 3 at addresses 3016 38 e O Select the BRGi s count source bits 0 and 1 at addresses 3416 3Cie Set division value 1 n 00 e to FF e to the BRGi addresses 3116 39 6 fi Transfer clock s frequency d 2 n 1 fi Frequency of BRGi s count source fo Hs fes fs12 Enable transmission bit 0 at addresses 3516 S3D e 1 Set data to the UARTi transmit buffer register addresses 3216 3A16 Pin s state eA transfer clock is output from the CLK pin Serial data is output from the TxDi pin Dummy data is output when performing only reception 2 Input of transfer clock from the external A clock input from the CLKi pin is the transfer clock Setting for relevant registers Select an external clock bit 3 at addresses 30 e 3816 1 Enable transmission bit O at addresses 3516 S3D e 1 Set data to the UARTi transmit buffer register addresses 3216 3A e Pin s state eA transfer clock is input from the CLK pin Serial data is output from the TxDi pin Dummy data is output when performing only reception 7721 Group User s Manual 11 17 SERIAL I O 11 3 Clock synchronous serial I O mode 11 3 2 Method of transmission Figure 11 3 1 shows an initial setting example for relevant registers when transmitting Transmission is started when all of the followi
325. g 13 8 8 Timing diagram ot link array chain transfer mode burst transfer mode 2 7721 Group User s Manual 13 90 DMA CONTROLLER 13 8 Link array chain transfer mode Figure 13 8 9 shows the conditions necessary for timings shown in Figures 13 8 7 13 8 8 and 13 8 10 through 13 8 14 External data bus width 16 bits Transfer unit 16 bits Transfer method 2 bus cycle transfer Transfer mode Burst Figure 13 8 7 and Figure 13 8 8 Cycle steal Figure 13 8 10 through Figure 13 8 14 Transfer source address direction Forward Transfer destination address direction Forward Transfer source Wait No Transfer destination Wait No sal sa2 da1 da2 Transfer parameter even tp1 Start address of first block s transfer parameter memory Transfer block s number 2 Right to use bus CPU gt DMAC gt CPU Memory dal First block transfer First block s transfer da1 4m 1 parameter dal m da2 Second block transfer sa2 n 1 sa2 n Second block s transfer parameter tp2 12 00000016 Fig 13 8 9 Conditions necessary for timings shown in Figures 13 8 7 13 8 8 and 13 8 10 through 13 8 14 7721 Group User s Manual 13 91 DMA CONTROLLER 13 8 Link array chain transfer mode ejeis Aee ue ui pejdoooe zou aJe sjeuueuo JOUIO aui JO SIsenba ywa eur peideooe si pue sng esn o1 yp y jo uonisueJ eui ul SI L upis Bull dwes 1senboi sng y eju pajdwes s vig Ag pesneo 1senbai
326. g error Valid in UART mode 1 Framing error detected Parity error flag Notes 1 2 0 No parity error Valid in UART mode 1 Parity error detected 7 Error sum flag Notes 1 2 0 No error Valid in UART mode 1 Error detected Notes 1 Bit 4 is cleared to 0 when the receive enable bit is cleared to 0 or when the serial I O mode select bits bits 2 to 0 at addresses 3016 3816 are cleared to 0002 Bits 5 and 6 are cleared to 0 when one of the following is performed Clearing the receive enable bit to 0 Reading the low order byte of the UARTi receive buffer register addresses 3616 3E16 out Clearing the serial I O mode select bits bits 2 to 0 at addresses 3016 3816 to 0002 Bit 7 is cleared to 0 when all of bits 4 to 6 become 0 2 Bits 5 to 7 are invalid in the clock synchronous serial I O mode UARTi receive buffer register b15 b8 b7 bO b7 bO UARTO receive buffer register Addresses 3716 3616 UART1 receive buffer register Addresses 3F 16 3E16 Panta 8100 to 0 8 to 0 Receive data is read out from here data i Receive data is read out from here read out from here Undefined RO 15 to 9 Nothing is assigned The value is 0 at reading 7721 Group User s Manual 17 15 APPENDIX Appendix 3 Control registers Count start register b7 b6 b5 b4 b3 b2 bi b0 Count start register Address 4016 Fm sn Cree Tela FE Timer AO
327. g transmission set the UARTi transmit buffer register again and then restarts transmission The method of initializing the UARTi receive buffer register and that of setting the UARTi transmit buffer register again are described below 1 Method of initializing UARTi receive buffer register Clear the receive enable bit to 0 reception disabled Set the receive enable bit to 1 again reception enabled 2 Method of setting UARTI transmit buffer register again Clear the serial I O mode select bits to 0002 serial I O invalid Set the serial I O mode select bits again Set the transmit enable bit to 1 transmission enabled and set the transmit data to the UARTi transmit buffer register 11 46 7721 Group User s Manual SERIAL I O 11 4 Clock asynchronous serial I O UART mode 11 4 8 Sleep mode This mode is used to transfer data between the specified microcomputers which are connected by using UARTi The sleep mode is selected by setting the sleep select bit bit 7 at addresses 3016 3816 to 1 when receiving In the sleep mode receive operation is performed when the MSB Ds when the transfer data is 9 bits length D7 when it is 8 bits length De when it is 7 bits length of the receive data is 1 Receive operation is not performed when the MSB is 0 The UARTIi receive register s contents are not transferred to the UARTi receive buffer register Additionally the receive complete
328. ges when subroutines are nested or when multiple interrupt requests are accepted Therefore make sure of the subroutine s nesting depth not to destroy the necessary data Note Refer to 7700 Family Software Manual for addressing modes Stack area Address ee aie S 1 Program counter s high order byte PCH S Program bank register PG S is the initial address that the stack pointer S indicates at accepting an interrupt request The S s contents become S 5 after storing the above registers Fig 2 1 2 Stored registers of the stack area 2 4 7721 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 2 1 5 Program counter PC The program counter is a 16 bit counter that indicates the low order 16 bits of the address 24 bits at which an instruction to be executed next in other words an instruction to be read out from an instruction queue buffer next is stored The contents of the high order program counter PC become FF e and the low order program counter PCL becomes FE e at reset The contents of the program counter becomes the contents of the reset s vector address addresses FFFE e FFFF e immediately after reset Figure 2 1 3 shows the program counter and the program bank register Fig 2 1 3 Program counter and program bank register 2 1 6 Program bank register PG The access space is divided in units of 64 Kbytes This unit is called bank Refe
329. gger is selected when the trigger select bits bits 4 and 3 at addresses 5816 to 5A e are 002 or O12 an external trigger is selected when the bits are 102 or 112 If a trigger is generated during counting the reload register s contents are reloaded and the counter continues counting If generating a trigger during counting make sure that a certain time which is equivalent to one cycle of the timer s count source or more has passed between the previously generated trigger and a new trigger 1 When selecting internal trigger A trigger is generated when writing 1 to the one shot start bit bits 2 to 4 at address 4216 Figure 8 5 4 shows the structure of the one shot start register 2 When selecting external trigger A trigger is generated at the falling edge of the TAjw pin s input signal when bit 3 at addresses 5816 to 5Aie is 0 or at its rising edge when bit 3 is 1 When using an external trigger set the port P5 direction registers bits which correspond to the TAjin pins for the input mode b7 b6 b5 b4 b3 b2 bi bO jojo One shot start register Address 4216 IE KI Fix these bits to 0 The value is 0 at reading o wo o wo Timer A2 one shot start bit 1 Start outputting one shot pulse o wo valid when internal trigger is mu Timer A3 one shot start bit selected He The value is 0 at readin J Timer A4 one shot start bit 9 Nothing is assigned Fig 8 5 4 S
330. gister X and index register Y is used as a 16 bit register or an 8 bit register That register is used as a 16 bit register when this flag is 0 and as an 8 bit register when it is 1 Use the SEP instruction to set this flag to 1 and use the CLP instruction to clear it to 0 This flag is cleared to 0 at reset Note When transferring data between registers which are different in bit length the data is transferred with the length of the destination register but except for the TXA TYA TXB TYB and TXS instructions Refer to 7700 Family Software Manual for details 7721 Group User s Manual 2 CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 6 7 8 9 Bit 5 Data length flag m It determines whether to use a data as a 16 bit unit or as an 8 bit unit A data is treated as a 16 bit unit when this flag is 0 and as an 8 bit unit when it is 1 Use the SEM or SEP instruction to set this flag to 1 and use the CLM or CLP instruction to clear it to 0 This flag is cleared to 0 at reset Note When transferring data between registers which are different in bit length the data is transferred with the length of the destination register but except for the TXA TYA TXB TYB and TXS instructions Refer to 7700 Family Software Manual for details Bit 6 Overflow flag V It is used when adding or subtracting with a word regarded as signed binary When the d
331. gister and UARTi s I O pins For details refer to the description of each operating mode b7 b6 b5 b4 b3 b2 bli Port P8 direction register Address 1416 0 Orere 0 Input mode 1 Output mode CL Ko pin 2 When using pins P82 and P8s as RxDo pin serial data input pins RxDo RxD1 set the corresponding bits to 0 3 TxDo pin CTS1 RTSi pin 4 CLK pin RxD1 pin TxD pin Fig 11 2 13 Relationship between port P8 direction register and UARTi s I O pins 7721 Group User s Manual 11 15 SERIAL I O 11 3 Clock synchronous serial I O mode 11 3 Clock synchronous serial I O mode Table 11 3 1 lists the performance overview in the clock synchronous serial I O mode and Table 11 3 2 lists the functions of I O pins in this mode Table 11 3 1 Performance overview in clock synchronous serial l O mode Item Functions Transfer data format Transfer data has a length of 8 bits LSB first Transfer rate When selecting internal clock BRGi s output divided by 2 When selecting external clock Maximum 5 Mbps Transmit Receive control CTS function or RTS function can be selected by software Table 11 3 2 Functions of I O pins in clock synchronous serial I O mode Pin name TxDi P83 P87 Note RxD P82 P86 CLK P81 P8s CTSi RTSi P80 P84 Functions Method of selection Serial data output LLL NJ l amp Dummy data is output when performing only reception Serial d
332. gisters among accumulator index register direct Note 6 page register data bank register program bank register or processor status register specified by the bit pattern of 5s 9 EF ES i ES Ez EN the second byte of the instruction into the stack PUL Restores the contents of the stack to the registers among Note 7 accumulator index register direct page register data bank register or processor status register specified by the bit pattern of the second byte of the instruction RLA m 0 Rotates the contents of the accumulator A n bits to the Note 13 n bit rotate left left m 1 n bit rotate left man ROL m 0 Links the accumulator or the memory to C flag and rotates Note 1 result to the left by 1 bit bis e c m 1 L bz bo ral ROR m 0 Links the accumulator or the memory to C flag and rotates Note 1 result to the right by 1 bit C ss Too m 1 Ac 5 n Toc Returns from the interruption routine bank register are also restored Returns from the subroutine The contents of the program bank register are not restored TH po mrs ull 0 Wu o S S G S fe Po Cele ce Returns from the subroutine The contents of the program SBC Acc C Acc M C Subtracts the contents of the memory and the borrow from Notes 1 2 the contents of the accumulator A EZES T j j j RE e mE jJ ou o s o o S e e o o o IE CN i i EE pe TI no
333. gt 1nogeV L eGd 1 lt gt NISY L SGd ct lt gt 10OvV L rGd H lt gt NITV 1L SGd Ot lt gt NIOG1 9Sd 6 lt gt NILG1 4Gd 8 lt gt 00d 1H 09d 2 lt gt Od 1u 9d 9 lt gt 0d 1H 9d S lt gt 0d 1H 9d lt gt 0 d Ldl r9d lt gt Ld 1H S9d Lc lt gt Ld 1H 99d PT lt Ld1H 9d External address bus external data bus bus control signal Note For the DRAM control signals refer to CHAPTER 14 DRAM CONTROLLER Fig 3 1 1 Pin configurations when external data bus width is 16 bits and 8 bits top view 3 3 7721 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 3 1 Signals required for accessing external devices 5 Byte low enable signal BLE Byte high enable signal BHE The BLE signal indicates the access to an even address This signal becomes L level when accessing only an even address or when simultaneously accessing both an even and an odd address The BHE signal indicates the access to an odd address This signal becomes L level when accessing only an odd address or when simultaneously accessing both an odd and an even address These signals are used to connect memories or I O devices of which data bus width is 8 bits when the external data bus width is 16 bits Table 3 1 2 lists levels of the BLE and BHE signals and access addresses Table 3 1 2 Levels of BLE and BHE signals and access addresses 6
334. gure 9 2 5 shows the relationship between port P5 direction register and the Timer Bj s input pins b7 b6 b5 b4 b3 b2 bi bO EERE Port P5 direction register Address Die Corresponding pin name Functions EN TA2our pin 0 Input mode RW 1 Output mode TAZ pin RW When using these pins as RW TASout pin Timer Bj s input pins set the TA3N pin corresponding bits to 0 RW TA4 N pin TBO pin 7 TB1Ipin Bits 0 to 5 are not used for Timer B ES o EN o oe w EN EN o Fig 9 2 5 Relationship between port P5 direction register and Timer Bj s input pins 7721 Group User s Manual 9 7 TIMER B 9 3 Timer mode 9 3 Timer mode In this mode the timer counts an internally generated count source Refer to Table 9 3 1 Figure 9 3 1 shows the structures of the timer Bi mode register and timer Bi register in the timer mode Table 9 3 1 Specifications of timer mode Item Count source Count operation Division ratio Count start condition Count stop condition Interrupt request occurrence timing TBjin pin s function Head from timer Bi register Write to timer Bi register Specifications f2 fie fea or fs12 Countdown When a counter underflow occurs reload register s contents are reloaded and counting continues 1 n 1 When the count start bit is set to 1 When the count start bit is cleared to 0 When a counter underflow occurs Programmable I O port Counter value can
335. h 16 bits 16 36 7721 Group User s Manual APPLICATION 16 1 Memory connection lt When reading gt Tes tw EL 135 min RAS tw RASL 120 min tw RASH 60 min td RAS CAS 28 min td E RASL 30 max CAS td E CASL 77 5 max lt tw CASL 92 5 min gt PAPAS 5 min L gt td CA CAS 5 min V Y tOEA 20 max gt tAA 35 max td E CA 60 max gt lt I gt tpzx E DLZ DHZ 20 min lt tRAC 70 max gt lt gt IN A16 DO A23 D7 f LIIIIIIII II II I I IIIII f L LLL Lll tCLZ 5 min tCAC 20 max tsu DL DH E gt 30 oEz 0 20 lt When writing gt u tw EL 135 min E tw RASH 60 min TS tw RASL 120 min RAS lt tw CASL 55 min CAS gt td E CASL 80 115 c gt td R W E 20 min lt gt R W gt lt AC32 tPHL X 2 AC32 tPHL X 2 twcs 0 min tWCH 10 min WL WH gt lt gt td RA RAS 5 min f 29 h RAS RA 18 min MAo MA 9 Row address Column address lt gt gt td CA CAS 10 min th CAS CA 60 min A16 D0 A23 D7 A8 D8 A15 D15 Address Data gt td E 20 min tDH 15 min lt gt th E DLQ DHQ 18 min Specifications of M5M44400CJ 7 The others are specificat
336. he sum of propagation delay time is within 30 ns External ROM area 3 4 Make sure that the sum of propagation delay time is within 20 ns M5M28F102AFP 5 Make sure that the propagation delay time is within 5 ns External RAM area M5M5256DP X 2 Fig 16 1 18 Example of flash memory and SRAM connection maximum model 16 22 7721 Group User s Manual APPLICATION 16 1 Memory connection tw EL 135 min lt When reading gt u E O Oo td AL E 15 min lt AA 1 A CA As Ds Ai5 D15 Aie Do Ais D2 NV A N 2 2 2 222222222022 lt P tpzx E DLZ DHZ 20 min D3 D7 AC573 tPHL tPLH AC139 tPHL CE S gt 3 1 amp AC32 tPLH OE tDF tdis OE 2 15 max Guaranteed as kit AC32 tPHL External memory data output tsu DL DH E 30 tsu A DL DH 130 max ta AD AC573 tPHL tPLH When writing tw EL 135 min u lt E in td AL E 15 m lt Ar AT m Q A XA As Ds A15 D nc D fal X D XA th E DLQ DHQ 18 min A16 Do A18 D2 D3 D7 tsu D gt 30 td E DLQ DHQ 35 max lt AC573 tPHL AC139 tPHL AC32 tPLH AC32 tPHL x Specifications of M5M28F102AFP 10 Specifications of M5M5256DP 70LL The others are specifications of M37721 Unit ns
337. hes the right to use bus to the function with the highest priority among functions which issue bus requests when the BUS REQUEST signal is sampled This is the bus request acceptance If any bus request is not generated at bus request sampling the CPU gains the right to use bus The bus use priority levels are fixed by hardware and the bus status is reported by status signal outputs STO and ST1 Table 13 2 2 lists the relationship between the bus use priority level bus status and status signals Table 13 2 2 Relationship between bus use priority level bus status and status signals Bus use Bus status Status signals priority level STI STO 1 Highest DRAM refresh 2 Hold O O 3 DMAC 4 Lowest CPU Including the term while the CPU does not use the bus for example the term when the CPU is calculating and does not use the bus 7721 Group User s Manual 13 7 DMA CONTROLLER 13 2 Block description The BUS REQUEST signal is sampled at a break in bus use Table 13 2 3 and Figure 13 2 3 shows the timings of bus request sampling Also bus request sampling signals are shown in them Table 13 2 3 Bus request sampling timing Bus user Bus request sampling timing DRAM refresh After completion of a DRAM refresh cycle Hold Every 1 cycle of DMAC S R All except the following After completion of 1 unit transfer Note 1 At the end of each block After 1 unit transfer and terminate processing 3 cycles Q0
338. hould do about it Interrupt request is LDM 00H XXXIC Writes 0002 to interrupt priority level select bits accepted in this gt Clears interrupt request bit to 0 interval LDA A DATA Instruction at the beginning of the routine which should not accept one certain interrupt request As for the change of the interrupt priority level when the following are met the microcomputer may pretend to accept an interrupt request immediately after this interrupt is set to be disabled he next instruction in the above example it is the LDA instruction is already stored into a instruc tion queue buffer for the BIU Conditions for accepting the instruction which should not be accepted are satisfied immediately before the next instruction in the instruction queue buffer is executed When writing to a memory or an I O the CPU passes the address and data to the BIU Then the CPU executes the next instruction in the instruction queue buffer while the BIU is writing data into the actual address Detection of interrupt priority level is performed at the beginning of each instruc tion In the above case the CPU executes the next instruction before the BIU completes the change of the interrupt priority level Therefore when the interrupt priority level is detected synchronously with the execution of the next instruction the interrupt priority level before the change is detected and its interrupt request is accepted Interrupt reques
339. i I T I I I i D E X 1 x x x x EEN j 9100 QU i l D L L f 9120 oo i To I I I D I I I gt i jeubis L Z X L uu X 4 4 L Z x w X Y eis 10 94 914 zj eounos JUNOD jo KouenbejJ J indui S uid NI V L N 1NOS JUNOD uid 1nofy wo indino es nd INAAd Fig 8 6 7 Operation example of 8 bit pulse width modulator when counter value is updated during pulse output 7721 Group User s Manual 8 46 TIMER A 8 6 Pulse width modulation PWM mode Precautions for PWM mode 1 If the count start bit is cleared to 0 while outputting PWM pulses the counter stops counting When the TAjout pin was outputting H level at that time the output level becomes L and the timer Aj interrupt request bit is set to 1 When the TAjour pin was outputting L level the output level does not change and a timer Aj interrupt request does not occur 2 When the timer s operating mode is set by one of the following procedures the timer Aj interrupt request bit is set to 1 e When the PWM mode is selected after reset e When the operating mode is switched from the timer mode to the PWM mode e When the operating mode is switched from the event counter mode to the PWM mode Accordingly when using the timer Aj interrupt interrupt request bit be sure to clear the timer Aj interrupt request bit to 0 after the above setting 7721 Group User s Manual
340. i pin outputs H level For the bus request sampling in an array state refer to section 13 2 1 Bus access control circuit 2 Transfer state Data is transferred in a transfer state For the bus request sampling in a transfer state refer to section 13 2 1 Bus access control circuit 7721 Group User s Manual 13 75 DMA CONTROLLER 13 7 Array chain transfer mode On and after second First of 1 block SARi lt Transfer parameter Note Transfer source s transfer start address DARi lt Transfer parameter Note Transfer destination s transfer start address TCRi lt Transfer parameter Byte number of transfer data TCRi latch TCRi latch 1 DMAi request bit 0 Only in cycle steal transfer mode 1 unit transfer Refer to section 13 4 Operation BurstesEdge Burst Level L Cycle steal Requested Transfer completion of 1 block Burst Edge Burst Level L Cycle steal Requested DMAi request bit Transfer completion of all blocks JI CRI latch 0 0 Burst Level H Cycle steal No request Y Completion TC L output Note DMAi request bit DMAi interrupt request bit 1 DMAi enable bit lt 0 0 Note When TC pin validity bit is 1 Burst Level H Cycle steal No request DMAi request bit 0 Only in burst transfer mode edge sense Burst Edge In burst transfer mode e
341. ible to read the bit state Nothing is assigned It is impossible to read the bit state The written value becomes invalid State immediately after reset 0 0 immediately after reset 1 1 immediately after reset Undefined immediately after reset Address 1FCO016 1FC116 1FC216 1FC316 1FC416 1FC516 1FC616 1FC716 1FC816 1FC916 1FCA16 1FCB16 1FCC16 1FCD16 1FCE16 1FCF16 1FD016 1FD116 1FD216 1FD316 1FD416 1FD516 1FD616 1FD716 1FD816 1FD916 1FDA16 1FDB16 1FDC16 1FDD16 1FDE16 1FDF16 T O Register name Source address register 0 Destination address register 0 Transfer counter register O DMAO mode register L DMAO mode register H DMAO control register Source address register 1 Destination address register 1 Transfer counter register 1 DMA1 mode register L DMA1 mode register H DMA1 control register Always 0 at reading Always 1 at reading Always undefined at reading Access characteristics 7721 Group User s Manual APPENDIX Appendix 2 Memory assignment in SFR area 0 immediately after reset Fix this bit to 0 tate immediately after reset ojooro RY of oo EXEXERESSSSSEEET K oo N ENSE NSNSSS S o ZL e M B BBB EZ B E E B e 17 7 APPENDIX Appendix 2 Memory assignment in SFR area Access characteristics RW It is possible to read
342. ified Example External I O devices 13 1 1 Performance overview Table 13 1 1 lists the performance overview Table 13 1 1 DMAC performance overview ltem Performance specifications Number of channels 4 channels Transfer space 16 Mbytes between arbitrary spaces Number of transfer Maximum of 16 Mbytes bytes DMA request source Internal 14 sources and External 1 source Channel priority Fixed or Rotating Transfer rate Maximum of 12 5 Mbytes sec at f Xin 25 MHz 1 bus cycle transfer Maximum of 6 25 Mbytes sec at f Xin 25 MHz 2 bus cycle transfer Data transfer 1 bus cycle or 2 bus cycle transfer method Transfer unit 8 or 16 bits Address direction of Fixed Forward or Backward transfer Directions of source and destination are independently selectable Transfer mode Burst transfer or Cycle steal transfer mode Continuous transfer Single transfer Repeat transfer Array chain transfer or Link array chain transfer mode mode 13 2 7721 Group User s Manual DMA CONTROLLER 13 1 Overview 13 1 2 Bus use priority levels The bus use priority levels are fixed by hardware as follows DRAMC gt Hold function gt DMAC gt CPU DRAM refresh Because DMAC has the third priority it actually operates as follows e When DRAM refresh request or Hold request is generated during DMA transfer After the transfer of one transfer unit 8 bit or 16 bit data which is being performed at that time is complete DMAC reli
343. igh level input voltage P43 P47 P5o P5 P6o P67 P7o P77 P80 P87 P9c P9 P100 P107 RDY 0 8 Vcc Vcc HOLD BYTE CNVss RESET Xin Vrer High level input voltage As De Ais Dis Ate Do Aza Dz 0 5 Vec Vec Low level input voltage P43 P47 P5o P57 P6o P67 P7o P77 P8o P8 P90 P97 P100 P107 RD Y 0 2 Vec HOLD BYTE CNVSS RESET XN l VREF Low level input voltage As Ds A1s Dis A16 Do A23 D7 O J 0 6 Vee High level peak output current Ao MAc A7 MAz As Ds Ais Dis Aie Do Az23 D7 P43 P 47 P5o P5z P60 P67 P7o P77 P80 P87 P9o P9 P100 P107 RESE Tour STO ST1 ALE BLE BHE R W High level average output Ao MAo A7 MAz7 As Ds Ai15 Dis current Aie Do Az23 D7 P43 P47 P50 P57 P60 P67 P70 P77 P8o P87 P9o P9 P100 P107 1 RESETour STO ST1 ALE BLE BHE R W Low level peak output current A MAo A7 MA As Ds Ai5 D15 Aie Do Az23 D7 P43 P 47 P5o P57 P60 P67 P7o P7 P8o P87 P9o P9 P100 P107 RESETour STO ST1 ALE BLE BHE R W Low level average Ao MAo A MA As De A s D s output current A16 Do A23 Dz P4s P47 P5o P57 P6o P6 P7o P77 P8o P87 P9o P9 P100 P107 1 RESETour STO ST1 ALE BLE BHE R W lt lt lt lt lt lt lt lt External clock input frequency 2 MHz Average output current is the average value of a 100 ms
344. ignal External memory e chip select signals CE S Address output and Data input As Ds A15 Dis Address Ai6 Do Az23 D7 _ Specifications of the M37721 The others are specifications of external memory This applies when the external data bus has a width of 16 bits BYTE L Fig 16 1 5 Timing for writing data to flash memory and SRAM Data setup time tsup lt twL ta E bLa puo Table 16 1 4 lists the calculation formulas and values for each parameter in Figure 16 1 5 Figure 16 1 6 shows the relationship between tsup and f Xin 16 8 7721 Group User s Manual APPLICATION 16 1 Memory connection Table 16 1 4 Calculation formulas and Values for each parameter in Figure 16 1 5 unit ns Calculation formulas and Values Wait tw EL 2 X 10 4 X 10 f Xin pes f XN an td E DLQ 35 td E DHQ th E DLQ 1 X 10 th E DHQ f XiN 22 Wait No Wait ab E O o o G C 157 S eee 145 79 18 129 116 108 494 68 60 22 46 40 35 30 95 21 18 15 13 14 15 16 17 18 19 20 21 22 23 24 295 MHz 95 External clock input frequency f XIN Fig 16 1 6 Relationship between tsup and f Xin 7721 Group User s Manual 16 9 APPLICATION 16 1 Memory connection Timing for
345. imer A3 count start bit Timer A4 count start bit k input to TAjiN 3 EZ is selected etting count start bit to 1 b7 b0 Count start register Address 4016 Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit When internal trigger ON J N Setting one shot start bit to 1 One shot start register Address 4216 Timer A2 one shot start bit Timer A3 one shot start bit Timer A4 one shot start bit B P Trigger generated Count starts Fig 8 5 3 Initial setting example for registers relevant to one shot pulse mode 2 8 32 7721 Group User s Manual TIMER A 8 5 One shot pulse mode 8 5 2 Count source In the one shot pulse mode the count source select bits bits 6 and 7 at addresses 5816s to 5A e select the count source Table 8 5 2 lists the count source frequency Table 8 5 2 Count source frequency Count source Count saja pus Count source frequency source b7 b6 f Xin 25 MHz 0 0 12 5 MHz 0 I 1 5625 MHz 0 390 625 kHz 1 48 8281 kHz 7721 Group User s Manual 8 33 TIMER A 8 5 One shot pulse mode 8 5 3 Trigger The counter is enabled for counting when the count start bit address 4016 is set to 1 The counter starts counting when a trigger is generated after counting has been enabled An internal or external trigger can be selected as that trigger An internal tri
346. in Reception enabled 2 Method of setting UARTI transmit buffer register again Clear the serial I O mode select bits to O002 Serial I O invalid Set the serial I O mode select bits to 0012 again Set the transmit enable bit to 1 Transmission enabled and set the transmit data to the UARTi transmit buffer register 7721 Group User s Manual 11 29 SERIAL I O 11 3 Clock synchronous serial I O mode Precautions for clock synchronous serial I O mode 1 The transfer clock is generated by operation of the transmit control circuit Accordingly even when performing only reception transmit operation setting for transmission must be performed In this case dummy data is output from the TxDi pin When receiving simultaneously set the receive enable bit and the transmit enable bit to 1 When receiving data write dummy data to the low order byte of the UARTi transmit buffer register for each reception of 1 byte data When selecting an external clock satisfy the following 3 conditions with the input to the CLKi pin H level lt When transmitting gt Set the transmit enable bit to 1 Write transmit data to the UARTi transmit buffer register Input L level to the CTSipin when selecting the CTS function When receiving Set the receive enable bit to 1 Set the transmit enable bit to 1 Write dummy data to the UARTi transmit buffer regist
347. in is valid e Writes 0 to the DMAi enable bit Table 13 3 5 lists the states of DMAC at forced termination Table 13 3 5 States of DMAC at forced termination Item State DMAi interrupt request bit Not changed DMAi request bit 0 DMAi enable bit 0 TC output Not changed Channel priority levels Not changed When the TC pin is used for forced termination select TC pin valid bit 1 at address 6816 1 Forced termination by the TC input is valid in the following cases During a DMA transfer in the burst transfer mode edge sense During the term from the DMA transfer start until the transfer completion of an entire batch of data in the burst transfer mode with the level sense selected it is also valid while the CPU has the right to use bus During a DMA transfer in the cycle steal transfer mode Forced termination by the TC input is invalid while the CPU has the right to use bus The TC pin s input is determined at the falling edge of and DMAC will relinquish the right to use bus to the CPU upon completion of the 1 unit transfer under execution at that time At the forced termination by the DMAi enable bit 0 is written to this bit at the rising edge of E of a write cycle to the DMAi enable bit Accordingly DMAi is disabled after this write 7721 Group User s Manual 13 27 DMA CONTROLLER 13 3 Control 13 3 6 DMA transfer restart after termination 1 2 13 28 Restarting the same D
348. in s input level is L with the DMAi enable bit 1 a DMA transfer starts When the DMAREQi pin s input level goes from L to H the right to use bus will be returned to the CPU at completion of 1 unit transfer under execution at that time When the DMAREQi pin s input level goes L again the DMA transfer restarts at the next address Once a DMAi transfer starts any DMA request including that of other channels cannot be accepted even if the DMAREQi pin s input level is H until the transfer is terminated normally or forcibly However the BUS REQUEST signal is sampled basically at every completion of 1 unit transfer Refer to Table 13 2 3 When a DRAM refresh request or Hold request is generated at this time the right to use bus is not returned to the CPU and the request is accepted When the transfer of an entire batch of data is complete the DMAC relinquishes the right to the CPU If the next DMA request is generated the right is once returned to the CPU to sample the DMA request 7721 Group User s Manual DMA CONTROLLER 13 4 Operation DMAREQO DMAO request bit DMAO enable bit DMAREQ1 DMA1 request bit DMA1 enable bit DRAM refresh request Right to use bus CPU DMA DMA1 DMAO CPU 4 lt lt Channel 1 Entire data transfer Channel 0 Entire data transfer This example applies on the following conditions e Both of DMAO and
349. inating Stop mode Refer to section 5 3 Stop mode 15 1 Block description Figure 15 1 1 shows the block diagram of Watchdog timer O gt Watchdog timer Watchdog timer interrupt request Bus request DRAMC TF ic peer is set Bus request Hold gt CPU wait request Bus request DMAC Writing to watchdog timer register address 6016 97 2Vcc RESET O detection circuit STP instruction Fig 15 1 1 Block diagram of Watchdog timer 15 2 7721 Group User s Manual WATCHDOG TIMER 15 1 Block description 15 1 1 Watchdog timer Watchdog timer is a 12 bit counter where the count source which is selected with the watchdog timer frequency select bit bit O at address 6116 is counted down A value FFF e is automatically set in Watchdog timer in the cases listed below An arbitrary value cannot be set to Watchdog timer e When dummy data is written to the watchdog timer register Refer to Figure 15 1 2 When the most significant bit of Watchdog timer becomes 0 e When the STP instruction is executed Refer to section 5 3 Stop mode At reset b7 b0 Watchdog timer register Address 6016 Initializes Watchdog timer Undefined When dumny data is written to this register Watchdog timer s value is initialized to FFF16 Dummy data 0016 to FF46 Fig 15 1 2 Structure of watchdog timer register 15 1 2 Watchdog timer frequency select register This is used to select a Wat
350. ing data from programmable I O port set to output mode By writing data to the corresponding bit of the port register the data is written into the port latch The data is output from the pin according to the contents of the port latch By reading the port register of a port set to the output mode the contents of the port latch is read out instead of the pin state Accordingly the output data is correctly read without being affected by an external load etc Refer to Figures 6 2 4 and 6 2 5 e When inputting data from programmable I O port set to input mode A pin which is set to the input mode enters the floating state By reading the corresponding bit of the port register the data which is input from the pin can be read out By writing data to the port register of a programmable I O port set to the input mode the data is written only into the port latch and is not output to the external Note The pin remains floating Note When executing a read modify write instruction CLB SEB INC DEC ASL ASR LSR ROL ROR to the port register of a programmable I O port set to the input mode the instruction is executed to the data which is input from the pin and the result is written into the port register b7 b6 b5 b4 b3 b2 bl b0 Port Pi register i 4 to 10 Addresses A16 Bis E16 Fie 1216 1316 1616 Zn Port Pio s pin Data is input from or output to a pin by reading from or writing to the 1 Port Pit s pin corresponding
351. ing the specified memory Refer to Table 16 1 6 Considering this the case where software Wait is inserted with f Xin 20 MHz condition is superior in the cost performance Sample A excution time ratio Sample B excution time ratio 59 Condition 9 _ Condition Fig 16 3 3 Execution time ratio 7721 Group User s Manual 16 59 APPLICATION 16 3 Comparison of sample program execution rate MEMORANDUM 16 60 7721 Group User s Manual Appendix 1 Appendix 2 Appendix 3 Appendix 4 Appendix 5 Appendix 6 Appendix 7 Appendix 8 Appendix 9 Appendix 10 Appendix 11 IA IP P S INI ID L2 Memory assignment of 7721 Group Memory assignment in SFR area Control registers Package outline Examples of handling unused pins Machine instructions Hexadecimal instruction code table Countermeasure against noise 7721 Group Q amp A Differences between 7721 Group and 7720 Group Electrical characteristics Appendix 12 Standard characteristics APPENDIX Appendix 1 Memory assignment of 7721 Group Appendix 1 Memory assignment of 7721 Group Microprocessor mode M37721S2BFP M37721S1BFP SFR area MEN 000000 e D aaa BENE 00007Fi6 SFR area J SFR area 00008016 a 00000216 512 bytes Case of internal RAM area Internal RAM area ia External area 512 bytes Gase of item soe External area 00027F 6 00000916 internal RAM area p Ca
352. interval The sum of loea for P8 P9 Ao MAo A7 MAz As Ds Ais Dis Ais Do Az3 D7 STO ST1 ALE BLE BHE and R W must be 80 mA or less the sum of loHipeak for P8 P9 Ao MAc Az MAz As Ds Ais Dis Aie Do Az3 D7 STO ST1 ALE BLE BHE and R W must be 80 mA or less the sum of lo pea for P4 P5 P6 P7 P10 and must be 80 mA or less the sum of loHpeak for P4 P5 P6 P7 P10 and i must be 80 mA or less 7721 Group User s Manual 17 81 APPENDIX Appendix 11 Electrical characteristics Electrical characteristics Vcc 5 V Vss 0 V Ta 20 to 85 f Xin 25 MHz unless otherwise noted Limits VoH High level output A MAc Az MA As Ds Ais Dis A16 Do A23 D7 P43 voltage P47 P5o P5 P6 P67 P7o P77 P8o P87 P9o P9 P10c P 107 i RESETour STO lou 10 mA ST1 ALE BLE BHE R W VoH High level output A MAc Az MA As Ds A s Dis Aie Do Az3 D7 MAs voltage MA RAS CAS STO ST1 BLE BHE R W Vox High level output ALE Urera voltage los 400 uA 4 8 M Von High level output E llon2 10mA 34 voltage lon 400uA 48 V lt VoL Low level output Ao MAo A7 MA7 As Ds A15 D15 voltage A16 Do A23 D7 P43 P47 P5o P5 P6o P67 lo 10 mA 2 P7o P7 P8e P8 P90 P97 P10o P107 i RESETour STO ST1 ALE BLE BHE R W VoL Low level output A MAc Az MAz As Ds A15 D1s voltage Aie Do Aza D7 MAs MA RAS
353. ion the number of cycles extended by Ready must be added Indicates the corresponding waveform in Figure 13 4 3 Note When a transfer destination applies to this condition 2 bus cycle transfer cannot be performed When a transfer source applies to this condition and a transfer destination is in the DRAM area 2 bus cycle transfer cannot also be performed 13 32 7721 Group User s Manual DMA CONTROLLER 13 4 Operation memacdoko LJ LJ LI L I AD CAXPOXC x a lt x a AX p Az X D x A m Cap CO AX p X x mr LL AID CARN D AA D ye m ALE A Address D Data 4 4 Read or write term per 1 unit transfer Fig 13 4 3 Bus cycle operation waveforms in 2 bus cycle transfer 7721 Group User s Manual 13 33 DMA CONTROLLER 13 4 Operation 3 Address directions in 2 bus cycle transfer In 2 bus cycle transfer the address direction of a transfer source and that of a transfer destination each can be selected independently Refer to Figure 13 2 6 Addresses move in the specified direction by the transfer unit Tables 13 4 2 through 13 4 4 list address directions in 2 bus cycle transfer and examples of transfer result Tables 13 4 2 Address directions in 2 bus cycle transfer and examples of transfer result 1 External data bus width 16 bits or 8 bits Address direction Transfer unit 16 bits Transfer unit 8 b
354. ion describes the internal area s memory assignment For more information about the external area refer also to CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES Figure 2 4 1 shows the memory assignment 2 4 1 Memory assignment in internal area SFR Special Function Register and internal RAM are assigned in the internal area 1 SFR area 2 The registers for setting internal peripheral devices are assigned at addresses 016 to 7Fie and 1FCOt e to 1FFF e This area is called SFR Figures 2 4 2 and 2 4 3 show the SFR area s memory assignment For each register in the SFR area refer to each functional description in this manual For the state of the SFR area immediately after reset refer to section 4 1 2 State of CPU SFR area and internal RAM area Internal RAM area The M37721S2BFP Note 1 assigns the 1024 byte static RAM at addresses 8016 to 47F e 512 bytes of that can be selected either it is used as the internal RAM or it is used as the external area Note 2 The internal RAM area is used as a stack area Note 3 as well as an area to store data Accordingly note that set the nesting depth of a subroutine and multiple interrupts level not to destroy the necessary data Notes 1 The M37721S1BFP assigns the 512 byte static RAM at addresses 80 e to 27F e 2 The internal RAM area becomes 512 bytes after reset because the internal RAM area select bit is 0 3 Either bank Oise or bank FF e can be selected as the stac
355. ion included in thisdocument but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liabi hatsoever for any damages incurred by you resulting from errors in or omissions from the information included herei Renesas Electronics products are classified according to the following three quality tandard High Quality and Specific The recommended applications for each Renesas Electronics produc n the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics prod ct before using it in a particular application You may not use any Renesas Electronics product for any applicati egorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Re ctronics product for any application for which it is not intended without the prior written consent of Renesas E s Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties aris the use of any Renesas Electronics product for an application categorized as Specific or for which the product 1 ed where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Ren ctronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets o S etc fr Standard Computers office equipment com equipment home electronic ap
356. ions of M37721 Unit ns Fig 16 1 33 Timing chart for example of M5M44400CJ 1M X 4 bits connection external bus width z 16 bits 7721 Group User s Manual 16 37 APPLICATION 16 1 Memory connection 10 Example of DRAM connection external bus width 16 bits M37721 M5M44260CJ 7 1 Make sure that the propagation delay time is within 20 ns 2 Make sure that the propagation delay time is within 7 5 ns Dre C lu 1Y 2Y Memory map 00000016 SFR area 00008016 Internal E 00047Fi6 RAM area RAW Not used i 001FFF16 aed A19 D3 A20 D4 A21 D5 pean Not used 23 D7 As Ds A9 D9 A10 D10 A11 D11 ADS DRAM area A13 D13 F7FFFF16 M5M44260CJ A14 D14 A15 D15 Not used XOUT FFFFFF 16 E 25 MHz F0000016 Circuit condition DRAM area select bits bits 3 to 0 at address 6416 00012 Fig 16 1 34 Example of M5M44260CUJ 256K X 16 bits connection external bus width 16 bits 16 38 7721 Group User s Manual APPLICATION 16 1 Memory connection lt When reading gt E tw EL 135 min OE RAS tw RASL 120 min tw RASH 60 min td RAS CAS 28 min td E RASL 30 max lt gt lt CAS td E CASL 77 5 max lt tw CASL 92 5 min L td RA RAS 5 min l gt gt td CA CAS 5 min MAo MAs Row address tOEA 20 max tAA 35 max td E CA 6
357. ire batch of data is applied It is also valid while the CPU has the right to use bus 7721 Group User s Manual 13 19 DMA CONTROLLER 13 3 Control 13 3 2 DMA requests 1 DMA request sources DMA request sources are specified by the DMA request source select bits and the edge sense level sense select bit Refer to Figure 13 2 8 Table 13 3 2 lists the conditions for generating a DMA request Table 13 3 2 Conditions for generating DMA request DMA request sources Condition for generating DMA request External source L level input to the DMAREQi pin only in the burst transfer mode DMAREQI Edge sense Change of the DMAREQi input pin s level from H to L Software DMAi request A write of 1 to the software DMAi request bit each of bits 0 3 at address 6916 refer to Figure 13 2 5 Timers A0 A4 When the interrupt request bit of each peripheral is set to 1 by the activity of Timers BO B2 peripherals If 1 is written to any of these interrupt request bits by software UARTO UART1 the DMAi request bit does not change Also whatever value within 0 7 an A D converter interrupt priority level takes this does not affect DMA requests 2 Change of DMAi request bit A read of the DMAi request bits each of bits 4 7 at address 6816 indicates whether the corresponding channel 0 3 is generating its DMA request or not The DMAi request bit changes synchronized with the falling edge of T
358. is transferred to the reload register at valid edge of measurement pulse and counting continues after clearing the counter value to 000016 Count start condition When the count start bit is set to 1 Count stop condition When the count start bit is cleared to 0 Interrupt request occurrence timing 6 When valid edge of measurement pulse is input Note 1 When a counter overflow occurs Timer Bj overflow flag is set to 1 simultaneously TBJIN pin s function Measurement pulse input Head from timer Bj register The value obtained by reading timer Bj register is the reload register s contents Measurement result Note 2 Write to timer Bj register Invalid Timer Bj overflow flag The bit used to identify the source of an interrupt request occurrence Notes 1 No interrupt request occurs when the first valid edge is input after the counter starts counting 2 The value read out from the timer Bj register is undefined after the counter starts counting until the second valid edge is input 7721 Group User s Manual 9 19 TIMER B 9 5 Pulse period Pulse width measurement mode b7 b6 b5 b4 b3 b2 bl bO Measurement mode select bits Count source select bits 01 b7 b6 F 5 e eee os ete ee eee eee 00 fe LIE 10 Timer Bj mode register j 0 1 Addresses 5B16 5C 6 LINNC NENNEN EN Operating mode select bits 0 Pulse period Pulse width measurement mode Pulse period measurement Interval
359. it data is 0 the light goes out ewhen the digit data is 1 the LED is lighted up 2 Assuming that the segment pattern is generated by another processing 7721 Group User s Manual 16 53 APPLICATION 16 2 Examples of using DMA controller b7 b0 o 0 0 14 0 1 0 0 DMA3 mode register L Address 1FFC16 Transfer unit 16 bits 2 bus cycle transfer Cycle steal transfer mode Transfer source address direction Forward Transfer destination address direction Fixed b7 b0 0 1 1 1 0 0 X 0 DMA3 mode register H Address 1FFDte No transfer source Wait No transfer destination Wait Repeat transfer mode b23 b16b15 b8b7 b0 Source address register 3 Addresses 1FF216 to 1FFO16 ERE Data buffer s start address b23 b16b15 b8b7 bO Destination address register 3 Addresses 1FF616 to 1FF416 b23 b16b15 b8b7 bO Transfer counter register 3 Addresses 1FFAt16e to 1FF816 LL Data number unit byte Port P6 P7 register s address b7 bO 0 0 1 0 0 0 DMAS control register Address 1FFE16 DMA request source Timer BO DMAACKS pin Invalid b7 bO jojojo DMAG interrupt control register Address 6F 16 Interrupt disabled X It may be 0 or 1 Fig 16 2 12 Initial setting example for relevant register 1 16 54 7721 Group User s Manual APPLICATION 16 2 Examples of using DMA controller b7 o o o o o 0 0 0 Port P6 regist
360. it is cleared to 0 by software The interrupt priority is detected when the CPU fetches an op code which is called the CPU s op code fetch cycle However when an op code fetch cycle starts during detection of an interrupt priority a new interrupt priority detection does not start Refer to Figure 7 6 1 Since the state of the interrupt request bit and interrupt priority levels are latched during the interrupt priority detection even if they change the interrupt priority detection is performed for the previous state before the change occurred The interrupt priority level is detected when the CPU fetches an op code Therefore in the following execution or states after the execution or state is terminated no interrupt request is accepted until the CPU fetches the op code of the next instruction Execution of an instruction which requires many cycles such as the MVN or MVP instruction During DRAM refreshment eDuring Hold state During DMA transfer Interrupt source Y Comparator X Priority level sent from the preceding Priority level comparator Highest priority at this point comparison Y Priority level of interrupt source Y Z Highest priority at this point When X 2 Y then Z X When X lt Y then Z Y Fig 7 5 2 Interrupt priority level detection model 7721 Group User s Manual 7 11 INTERRUPTS 7 6 Interrupt priority level detection time 7 6 Interrupt priority level detection time When
361. its Fix this bit to 0 7 Stack bank select bit h Bank 016 Bank FFie Processor mode register 1 b7 b6 b5 b4 b3 b2 bi b0 Processor mode register 1 Address 5F 16 Nothing is assigned Undefined Internal RAM area select bit 0 512 bytes addresses 8016 to 27F 6 Notes 1 2 1 1024 bytes addresses 8016 to TAA Nothing is assigned Undefined Notes 1 For the M37721S1BFP fix bit 1 to 0 2 For the M37721S2BFP set bit 1 before setting the stack pointer 7721 Group User s Manual 17 27 APPENDIX Appendix 3 Control registers Watchdog timer register b7 b0 Le Watchdog timer register Address 6016 Initializes Watchdog timer Undefined When dumny data is written to this register Watchdog timer s value is initialized to FFF16 Dummy data 0016 to FF46 Watchdog timer frequency select register b7 b b5 b4 b3 b2 bl bO Watchdog timer frequency select register Address 6116 E pene timer frequency select A o w fa2 Nothing is assigned 17 28 7721 Group User s Manual APPENDIX Appendix 3 Control registers Real time output control register b7 b6 b5 b4 b3 b2 bli bO BEEEEN III Real time output control register Address 6216 Jr K mom mom om om om om om m m m m m m m ELLE s m eee S sa us S When pulse mode 0 is selected 7 to 3 Nothing is assigned The value is 0 at reading See the
362. its Data arrangement Data arrangement on Data arrangement Data arrangement on pia Ed on transfer source Mud transfer destination on transfer source Mud iransfer destination memory transfer result memory q memory transfer result Fixed Fixed eas ss h Fixed Forward Low order sk Fixed Backward Transfer start address 13 34 7721 Group User s Manual DMA CONTROLLER 13 4 Operation Tables 13 4 3 Address directions in 2 bus cycle transfer and examples of transfer result 2 External data bus width 16 bits or 8 bits Address direction Transfer unit 16 bits Transfer unit 8 bits Data arrangement Data arrangement on Data arrangement on transfer source transfer destination on transfer source memory memory transfer result memory Data arrangement on transfer destination memory transfer result Transfer sequence Transfer sequence Transfer Transfer source destination Forward Fixed Forward Forward Forward Backward The position relationship between low order byte and high order byte is not reversed Transfer start address 7721 Group User s Manual 13 35 DMA CONTROLLER 13 4 Operation Tables 13 4 4 Address directions in 2 bus cycle transfer and examples of transfer result 3 Address direction Transfer destination Transfer source Backward Transfer unit 16 bits Data arrangement on transfer source memory L
363. ity level select bits Level 0 Interrupt disabled ii Level 1 Low level Level 2 Level 3 RW Level 4 Level 5 RW Level 6 Level 7 High level 3 Interrupt request bit 0 No interrupt requested RW 1 Interrupt requested Nothing is assigned Undefined Fig 9 2 4 Structure of timer Bi interrupt control register 1 Interrupt priority level select bits bits 2 to 0 These bits select a timer Bi interrupt s priority level When using timer Bi interrupts select one of the priority levels 1 to 7 When a timer Bi interrupt request occurs its priority level is compared with the processor interrupt priority level IPL The requested interrupt is enabled only when its priority level is higher than the IPL However this applies when the interrupt disable bit I 0 To disable timer Bi interrupts set these bits to 0002 level 0 2 Interrupt request bit bit 3 This bit is set to 1 when a timer Bi interrupt request occurs This bit is automatically cleared to 0 when the timer Bi interrupt request is accepted This bit can be set to 1 or cleared to 0 by software 9 6 7721 Group User s Manual TIMER B 9 2 Block description 9 2 5 Port P5 direction register Input pins of Timer Bj are multiplexed with port P5 When using these pins as Timer Bj s input pins set the corresponding bits of the port P5 direction register to O to set these port pins for the input mode Fi
364. ive interrupt request bit Stop bit Received data taken in At falling edge of start bit transfer clock UARTI receive register gt UARTI receive buffer register is generated and reception started en The above timing diagram applies when the Cleared to 0 when interrupt request is accepted following conditions are satisfied or cleared by software Parity disabled 1 stop bit RIS function selected Fig 11 4 12 Example of receive timing when transfer data length 8 bits when parity disabled selecting 1 stop bit selecting RTS function 7721 Group User s Manual 11 45 SERIAL I O 11 4 Clock asynchronous serial I O UART mode 11 4 7 Processing on detecting error In the UART mode 3 types of errors can be detected Each error can be detected when the data in the UARTi receive register is transferred to the UARTi receive buffer register and the corresponding error flag is set to 1 When any error occurs the error sum flag is set to 1 Accordingly presence of errors can be judged by using the error sum flag Table 11 4 6 lists conditions for setting each error flag to 1 and method for clearing it to 0 Table 11 4 6 Conditions set to 1 and method cleared to 0 for each error flac Error flag Conditions for being set to 1 Method for being cleared to 0 Overrun error flag When the next data is prepared in the Clear the serial I O mode select bits to UARTi re
365. ivided by 4 1 f2 divided by 2 lnterrupt priority level D b7 b0 BEEN A D conversion interrupt control register address 70 6 E Interrupt priority level select bits Set to a level between 1 to 7 when using this interrupt Set to a level 0 when disabling this interrupt b d Pon P7 direction register gt b7 b0 Port P7 direction register address 1116 ANo AN AN2 Set the bits corresponding AN3 to analog input pins to 0 AN3 Set bit 7 to 0 when ANS selecting external trigger ANe V AN7 J gt vA N A D conversion start bit to 1 b7 b0 e dt A D control register address 1E 6 S A D conversion start bit When external trigger is selected BERR RRR REPRE RRP wv Input falling edge to ADrnc pin When internal trigger is selected Trigger occur Operation start Note Writing to each bit except bit 6 of the A D control register and each bit of the A D sweep pin select register must be performed while the A D converter halts before a trigger occurs Fig 12 7 1 Initial setting example for registers relevant to single sweep mode 7721 Group User s Manual 12 21 A D CONVERTER 12 7 Single sweep mode 12 7 2 Single sweep mode operation description 1 2 12 22 When an internal trigger is selected The operation for the inp
366. k area by the stack bank select bit bit 7 at address 5E1 Figure 2 4 4 shows the structure of the processor mode registers O 1 7721 Group User s Manual 2 17 CENTRAL PROCESSING UNIT CPU 2 4 Memory assignment 2 4 2 External area Table 2 4 1 lists the external area When connecting the external device follow the procedure described bellow Connect the ROM to addresses FFCE e to FFFFie because they are interrupt vector table Stack area can be assigned to bank 0 e or bank FF e Select the stack area by the stack bank select bit bit 7 at address 5E e Refer to Figure 2 4 4 When using the DRAM controller DRAM area can be selected from address FFFFFF e toward the low order address in a unit of 1 Mbytes Refer to CHAPTER 14 DRAM CONTROLLER In the case connecting an external device to the area where overlaps the internal area when reading out the overlapping area the central processing unit CPU take in data of the internal area and do not take in data of the external area When writing to the overlapping area data is written to the internal area The signal is output to the external at the same timing when data is written to the internal area Table 2 4 1 External area Type name M37721S2BFP M37721S1BFP Internal RAM area select bit 1 0 o Fix this bit to 0 216 916 216 916 External area 4801e 1FBF 6 2801e 1FBF e 2000 e FFFFFF e 2000 e FFFFFF e Internal RAM area select bi
367. l n Reload register s contents Starts counting gt lt eb o c O c O O c gt O O Count start bit Count valid TAjin pin s level input Signal Invalid level Timer Aj interrupt request bit The counter counts when the count start bit 1 and the TAjin pin s input signal is at the count valid level l Wr l U Interrupt request Is The counter stops counting while the TAjin pin s input signal is not at the count valid level and the din cleared counter value is retained by software Cleared to 0 when Fig 8 3 5 Example of operation selecting gate function 7721 Group User s Manual 8 15 TIMER A 8 3 Timer mode 2 Pulse output function The pulse output function is selected by setting the pulse output function select bit bit 2 at addresses 5816 to 5A16 to 1 When this function is selected the TAjour pin is forcibly set for the pulse output pin regardless of the corresponding bits of the port P5 direction register The TAjour pin outputs pulses of which polarity is inverted each time a counter underflow occurs When the count start bit address 4016 is O count stopped the TAjour pin outputs L level Figure 8 3 6 shows an example of operation with the pulse output function selected n Reload register s contents Starts counting Starts counting Restarts counting Counter contents Hex 000016 Set to 1 by softw
368. l Fixed Channel 0 Channel 1 Fig 13 4 11 Transfer example in cycle steal transfer mode 7721 Group User s Manual 13 51 DMA CONTROLLER 13 4 Operation Precautions for cycle steal transfer mode 1 When DMA transfers of the same channel are continuously performed In the cycle steal transfer mode the DMAi request bit is cleared to O in every 1 unit transfer Also it takes 1 5 cycles of from the generation of a DMA request until that of a BUS REQUEST DMAC Therefore if another DMA request of the same channel i is generated during a DMAi transfer in the cycle steal transfer mode any one of the following three cases occurs depending on the timing of request generation he DMA request becomes invalid The DMA transfer continues without returning the right to use bus After returning the right to use bus to the CPU the DMAC regains the right and restarts the DMA transfer 1 unit transfer Bus request sampling 44 gt DMAi request bit is cleared to 0 during this term AA DMAi request is invalid DMA transfers are After returning the right to use bus even when DMAi request continuously performed if to CPU DMAC regains the right and bit becomes 1 DMAi request bit becomes 1 restarts DMA transfer if DMAi request during this term on condition bit becomes 1 during this term that DMAi request bit becomes 1 at the timing satisfying tsu DRQ 61 When a DMAi request is g
369. l Fixed priority Bus request sampling U OU LJ LI LJ LJ LI LI LI DMAO request bit DMA1 request bit DMA2 request bit DMAS request bit Channel priority level 0 gt 1 gt 2 gt 3 DMA transfer execution channel Priority level Rotating priority Bus request sampling PLP LI LP_LP LILI LI l PLP L DMAO request bit x 3 x x 3 DMA1 request bit DMA2 request bit DMA3 request bit Channel priority level lt Z lt 1 lt 0 L 0 e z 2 1 0 CO V V L V N E lt c lt 8 Q l lt O lt lt o lt 1L lt QO lt lt lt lt l lt O lt lt 6 L 0 lt lt lt 1 O lt E lt c lt 1 DMA transfer execution channel The above timing diagram applies on the following conditions No DRAM refresh request no Hold request All of DMAi enable bits are 1 Fig 13 3 1 Example of determining channel priority levels 13 22 7721 Group User s Manual DMA CONTROLLER 13 3 Control 13 3 4 Processing from DMA request until DMA transfer execution DMA requests are sampled at every falling edge of when requested the DMAi request bit is set to 1 Then the channel priority levels and bus use priority levels are determined and BUS REQUEST DMAC goes 1 if any DRAM refresh request or Hold request is not generated Note BUS REQUEST DMAC signal is sampled while the bus request sampling signal is 1 and is accepted D
370. l function When a DMAi interrupt is used the setting for enabling the interrupt is also required For details refer to CHAPTER 7 INTERRUPTS When external DMA source is selected When internal DMA source is selected Setting port P9 direction register b7 bO Port P9 direction register Address 1516 DMAREQO pin DMAREQ pin DMAREQ2 pin DMAREQOS pin Clear the corresponding bit to 0 eee ret Q c RR NAAR Setting interrupt priority level b7 bO DMAi interrupt control register i 0 to 3 Addresses 6C e to 6F 16 Interrupt priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 Continue to Figure 13 5 3 on next page Fig 13 5 2 Initial setting example for registers relevant to single transfer mode 1 13 56 7721 Group User s Manual DMA CONTROLLER 13 5 Single transfer mode From prec eding Figure 13 5 2 b7 bO b7 bO EN e Selection of transfer mode and each function 2 b7 ES DMAO mode register L Address 1FCC e DMA1 mode register L Address 1FDCt6 DMA2 mode register L Address 1FECte DMAS mode register L Address 1FFCt6 Number of unit transfer bits select bit 0 16 bits 1 8 bits Transfer method select bit 0 2 bus cycle transfer 1 1 bus cycle transfer Transfer mode se
371. l 8 E anB14 Duipeoeud W014 lt 01S LLS L POVVIAG Builduies 1senbeij sng q ee y 0 9 v s q srv 8q 8v ANI 0V MW LLI jV f cycle steal transfer mode 2 iagram o d iming Fig 13 8 11 T 13 93 7721 Group User s Manual DMA CONTROLLER 13 8 Link array chain transfer mode 1 unit transfer 1 unit transfer is performed with a DMAi request on the following conditions e Single transfer mode except for the last 1 unit transfer Repeat transfer mode except for the last 1 unit transfer of block Array chain transfer mode except for the first and last 1 unit transfers of each block e Link array chain transfer mode except for the first and last 1 unit transfers of each block R W AA X PCL salr2 X dat 2n X PCL As Ds Ais Dis X PCa Xara DatanXat 2 X Datan X PO Aie Do Aes Dz X PG Xesr2 Daa Xaatz2X Daa X PG Bus request sampling DMAACKi H TC ST1 STO 1 0 DMAC 1 1 CPU 1 unit transfer i I I I Transition of right Transition of right to use bus to use bus The above figure is the example of the second 1 unit transfer for processing the first block in Figure 13 8 9 The Bus request caused by DRAM refresh Hold or DMA is sampled while the Bus request sampling signal is H and is accepted Fig 13 8 12 Timing diagram of cycle steal transfer mode 3 13 94 7721 Group User s Manual DMA CONTROLLER 13 8 Link array chain t
372. l lo Vo characteristics bd 30 0 24 0 18 0 IOL mA 12 0 6 0 0 1 0 2 0 3 0 4 0 5 0 VoL V 7721 Group User s Manual 17 107 APPENDIX Appendix 12 Standard characteristics 2 Icc f Xin standard characteristics 1 Icc f Xin characteristics on operating and at reset Measurement condition Vcc 5 0 V Ta 25 C f XiN square waveform microprocessor mode 30 20 On operating At reset 10 Icc mA 0 5 10 15 20 25 30 f XiN MHz 2 Wait mode Measurement condition Vcc 5 0 V Ta 25 f XiN square waveform microprocessor mode 10 N Icc mA i at 0 5 10 15 20 25 30 f XiN MHz 17 108 7721 Group User s Manual APPENDIX Appendix 12 Standard characteristics 3 A D converter standard characteristics The lower lines of the graph indicate the absolute precision errors These are expressed as the deviation from the ideal value when the output code changes For example the change in output code from 0 to 1 should occur at 10 mV but the measured value is 2 mV Accordingly the measured point of change is 10 2 12 mV The upper lines of the graph indicate the input voltage width for which the output code is constant For example the measured input voltage width for which the output code is 15 is 24 mV so that the differential non linear
373. le selected analog input pins one at a time Repeat sweep mode This mode is used to perform the operation repeatedly for voltages input from multiple selected analog input pins 2 2 7721 Group User s Manual A D CONVERTER 12 2 Block description 12 2 Block description Figure 12 2 1 shows the block diagram of the A D converter Registers relevant to the A D converter are described below o f2 1 2 1 2 C VREF e Resistor Vref AVss O ladder network Successive approximation register A D sweep pin select register gt A D control register A D register 0 A D register 1 A D register 2 A D register 3 A D register 4 Decoder A D register 5 A D register 6 A D register 7 EE Data bus over INN ANo C AN AN2 C ANs C AN4 C ANs C ANe C ANz ADTRe C Comparator VIN IIb lli i Selector Fig 12 2 1 Block diagram of A D converter 7721 Group User s Manual 12 3 A D CONVERTER 12 2 Block description 12 2 1 A D control register Figure 12 2 2 shows the structure of the A D control register The A D operation mode select bit selects the operation mode of the A D converter The other bits are described below b7 b6 b5 b4 b3 b2 bl A D control register Address 1E16 Analog input select bits Valid in one shot and repeat ANo selected Undefined modes Note 1 AN1 s
374. lect bit 0 Burst transfer mode 1 Cycle steal transfer mode Address 1FCEt6e Address 1FDEt6e Address 1FEEt16 Address 1FFE16 bo DMAO control register DMA1 control register DMA2 control register DMAS control register DMA request source select bits 0000 Do not select 1000 Timer BO 000 1 External source DMAREQi 100 1 Timer B1 001 0 Software DMA source 1010 Timer B2 0011 Timer AO 101 1 UARTO receive 0100 Timer A1 1100 UARTO transmit 0101 Timer A2 1101 UART1 receive 0110 Timer A3 1110 UART1 transmit 0111 Timer A4 111 1 A D conversion Transfer source address direction select bits 0 0 Fixed 0 1 Forward 1 0 Backward Edge sense Level sense select bit Note 0 Edge sense 1 Level sense 1 1 Do not select Transfer destination address direction select bits 00 Fixed x DMAACKi validity bit 0 Invalid 1 Valid 0 1 Forward 1 0 Backward 1 1 Do not select to 0 DMAO mode register H Address 1FCDs 6 DMA1 mode register H Address 1FDDs 6 DMA2 mode register H Address 1FED16 DMAS mode register H Address 1FFD16 Transfer direction select bit Used in 1 bus cycle transfer 0 From memory to I O 1 From I O to memory I O connection select bit Valid in 1 bus cycle transfer 0 Data bus Do D7 or Do D15 1 Data bus De D s Transfer source wait bit Valid in DMA transfer 0 Wait 1 No wait Transfer de
375. lected by the level sense edge sense select bit and the polarity select bit bits 5 and 4 at addresses 7D e to 7F e shown in Figure 7 10 1 Table 7 10 1 lists the occurrence factor of INT interrupt request When using P100 INTo to P102 INT2 pins as input pins of external interrupts set the corresponding bits at address 18 e port P10 direction register to 0 Refer to Figure 7 10 2 The signals input to the INT pin require H or L level width of 250 ns or more independent of f Xin Additionally even when using the pins P100 INTo to P102 INT2 as the input pins of external interrupts the user can obtain the pin s state by reading bits O to 2 at address 16 e port P10 register Note When selecting an input signal s falling or L level as the occurrence factor of an interrupt request make sure that the input signal is held L for 250 ns or more When selecting an input signal s rising or H level as that make sure that the input signal is held H for 250 ns or more Table 7 10 1 Occurrence factor of INT interrupt request b5 INTi interrupt request occurrence factor 0 o Interrupt request occurs at the falling edge of a signal input to pin INTi Edge sense Interrupt request occurs at the rising edge of a signal input to pin INTi Edge sense 0 Interrupt request occurs when pin INT is at H level Level sense Interrupt request occurs when pin INTi is at L level
376. lled instruction prefetch The CPU reads instructions from the instruction queue buffer and executes them so that the CPU can operate at high speed without waiting for access to the memory which requires a long access time When the instruction queue buffer becomes empty or contains only 1 byte of an instruction the BIU performs instruction prefetch The instruction queue buffer can store instructions up to 3 bytes The contents of the instruction queue buffer is initialized when a branch or jump instruction is executed and the BIU reads a new instruction from the destination address When instructions in the instruction queue buffer are insufficient for the CPU s needs the BIU extends the pulse duration of clock CPU in order to keep the CPU waiting until the BIU fetches the required number of instructions or more Reading data from memory l O device The CPU specifies the storage address of data to be read to the BIU s data address register and requires data The CPU waits until data is ready in the BIU The BIU outputs the address received from the CPU onto the address bus reads contents at the specified address and takes it into the data buffer The CPU continues processing using data in the data buffer However if the BIU uses the bus for instruction prefetch when the CPU requires to read data the BIU keeps the CPU waiting Writing data to memory l O device The CPU specifies the address of data to be written to the BIU s data ad
377. lock which is being transferred Note When writing to this register write to all 24 bits Do not write 00000016 to this register 17 36 7721 Group User s Manual APPENDIX Appendix 3 Control registers Link array chain transfer mode Source address register 0 Addresses 1FC216 to 1FCO 6 Source address register 1 Addresses 1FD216 to 1FD016 Source address register 2 Addresses 1FE216 to 1FE016 Source address register 3 Addresses 1FF216 to 1FF016 23 to 0 Write Undefined RW Set the start address of transfer parameter memory of block which is first transferred These bits can be set to 00000016 to FFFFFF te Read After a value is written to this register and until transfer starts the read value indicates the written value the start address of the transfer parameter memory of block which is first transferred After transfer starts the read value indicates the source address of data which is next transferred Note When writing to this register write to all 24 bits Destination address register 0 Addresses 1FC616 to 1F C416 Destination address register 1 Addresses 1FD616 to 1FD416 Destination address register 2 Addresses 1FE616e to 1FE4 6 Destination address register 3 Addresses 1FF616 to 1FF416 23 to 0 Need not to set Undefined RW Read After transfer starts the read value indicates the destination address of data which is next transferred Transfer counter
378. log input pin 3 Writing to each bit except bit 6 of the A D control register must be performed while the A D converter halts A D sweep pin select register b7 b6 b5 b4 b3 b2 bi b0 A D sweep pin select register Address 1F46 A D sweep pin select bits P v Valid in single sweep and repeat 0 0 ANo AN 2 pins sweep modes Note 1 0 1 ANo to ANs 4 pins T ANo to ANs 6 pins ANo to AN 8 pins Note 2 Nothing is assigned E Notes 1 These bits are invalid in the one shot and repeat modes They may be either 0 or 1 2 When selecting an external trigger the AN7 pin cannot be used as an analog input pin 3 Writing to each bit of the A D sweep pin select register must be performed while the A D converter halts Petts ee ee ee ee ee eee eee ee E a isa siway i i SS A D register i b7 b0 A D register i i O to 7 Addresses 2016 2216 2416 2616 2816 2A16 2C16 2E16 7 to 0 Reads an A D conversion result Undefined Po 17 12 7721 Group User s Manual APPENDIX Appendix 3 Control registers UARTI transmit receive mode register b7 b6 UARTi baud rate register b7 bb b4 b3 b2 bi UARTO transmit receive mode register Address 3016 UART1 transmit receive mode register Address 3816 Bitname Bitname Functions b2 b1 bO 000 Serial I O disabled P8 functions as a programmable JJ JG I O port Clock synchronous serial I O mode Do not select
379. ls refer to section 13 4 2 1 bus cycle transfer 2 Transfer unit B 8 bit transfer A minimum unit of DMA transfer is 8 bits that is an 8 bit data is transferred for one DMA request in the cycle steal transfer mode In the burst transfer mode if a DRAM refresh request or a Hold request is generated during DMA transfer or if TC input is driven from H to L to force DMA transfer into termination DMAC relinquishes the bus after completion of 8 bit data transfer which is being performed at that time B 16 bit transfer A minimum unit of DMA transfer is 16 bits that is a 16 bit data is transferred for one DMA request in the cycle steal transfer mode In the burst transfer mode if a DRAM refresh request or a Hold request is generated during DMA transfer or if TC input is driven from H to L to force DMA transfer into termination DMAC relinquishes the bus after completion of 16 bit data transfer which is being performed at that time 7721 Group User s Manual 13 3 DMA CONTROLLER 13 1 Overview 3 Transfer modes B Burst transfer mode When once a DMA request is accepted in this mode an entire batch of data is transferred Neither is the right to use bus returned to the CPU nor the DMA request of the channel with the higher priority is accepted until the transfer is complete However if an external source DMAREQi is selected as a DMA request source with the level sense selected DMA transfer is performed when
380. lse mode Tu If the count start bit is cleared to 0 during counting the counter becomes as follows he counter stops counting and the reload register s contents are reloaded into the counter he TAjour pin s output level becomes L he timer Aj interrupt request bit is set to 1 2 A one shot pulse is output synchronously with an internally generated count source Accordingly when selecting an external trigger there will be a delay equivalent to one cycle of the count source at maximum from when a trigger is input to the TAjw pin until a one shot pulse is output Trigger input TAjin pin s di input signal I Neen Count source Y output from TAjour pin Starts outputting of one shot pulse One shot pulse 4 U Note The above applies when an external trigger falling edge of TAjin pin s input signal is selected Fig 8 5 6 Output delay in one shot pulse output 3 4 When the timer s operating mode is set by one of the following procedures the timer Aj interrupt request bit is set to 1 e When the one shot pulse mode is selected after reset e When the operating mode is switched from the timer mode to the one shot pulse mode e When the operating mode is switched from the event counter mode to the one shot pulse mode Accordingly when using the timer Aj interrupt interrupt request bit be sure to clear the timer Aj interrupt request bit to 0 after the abo
381. ltage Vi 1 0 V Viu 4 0 V Output timing voltage Output timing voltage Vor 0 8 V Vor 2 0 V 7721 Group User s Manual Data input Vit 0 8 V Vor 0 8 V Vor 2 0 V Vin 2 5 V APPENDIX Appendix 11 Electrical characteristics Microprocessor mode with no Wait lt Read gt tw L tw H t dr tc IV PRL PPS 01 E td AL E th E AL b td AM E __ gt gt lh E AM Address output BYTE H td AM E I lt gt lt gt toxz E DHZ lpzx E DHZ Address Data output As Ds A15 D15 Address by pee BYTE L td AM ALE le th ALE AM tsu DH E l th E DH Data input Dr Dis Usa ees BYTE L E DLZ k 9 tpzx E DLZ Address Data output 7 NA aaaea N Loo ed A16 Do A23 D7 ALE AH tsu DL E Dampi 5 gt gt th E DL tant a e tw ALE td ALE E ALE output td BHE E lt l th E BHE I BLEE lt th E BLE td R W E k th E R W R W output tsu PiD E x te La E PiQ Port Pi input x X i 4 10 Test conditions port Pi Test conditions except port Pi Vcc 2 5 V 10 96 Vcc 2 5V 10 96 Input timing voltage Vit 1 0 V Viu 4 0 V Output timing voltage Vor 0 8 V Vor 2 0 V Output timing voltage Vor 0 8 V Vou 2 0 V Data input Vit 0 8 V Vi
382. lue indicates the written value the start address of the transfer parameter memory After tranfer starts the read value indicates the source address of data which is next transferred Note When writing to this register write to all 24 bits Addresses 1FC216 to 1FC016 Addresses 1FD216 to 1FD016 Addresses 1FE216 to 1FE016 Addresses 1FF216 to 1FF0 6 b23 b16 b15 b8 b7 bO Destination address register 0 Addresses 1FC616 to 1FC416 Destination address register 1 Addresses 1FD616 to 1FD416 Destination address register 2 Addresses 1FE616e to 1FE416 Destination address register 3 Addresses 1FF616 to 1FF416 ween ce deen eee ence ec e ne eeene 23 to 0 Need not to set Undefined RW Read After transfer starts the read value indicates the destination address of data which is next transferred b23 b16 b15 b8 b7 bO Transfer counter register 0 Transfer counter register 1 Transfer counter register 2 Transfer counter register 3 Addresses 1FCA16 to 1FC816 Addresses 1FDA16 to 1FD816 Addresses 1FEAte to 1FE816 Addresses 1FFA16 to 1FF816 lt Undefined RW Set the number of transfer blocks These bits can be set to 00000116 to FFFFFFt e Read After a value is written to this register and until transfer starts the read value indicates the written value the transfer block number After transfer starts the read value indicates the remaining byte number of the b
383. measurement mode and each function b0 1 lilo Timer Bj mode register i 0 1 Addresses 5B e 5C16 ESI Selection of pulse period pulse width measurement mode Measurement mode select bits b3 b2 0 0 Pulse period measurement Interval between falling edges of measurement pulse 0 1 Pulse period measurement Interval between rising edges of measurement pulse 1 0 Pulse width measurement 1 1 Do not select Timer Bj overflow flag Note 0 No overflow 1 Overflowed Count source select bits b7 b6 0 0 f2 0 1 f16 1 0 fe4 1 1 f512 Se E Setting interrupt priority level b7 bO Timer Bj interrupt control register j 0 1 EEEE LL Addresses 7A16 7B16 Interrupt priority level select bits When using interrupts set these bits to one of levels 1to7 C When disabling interrupts set these bits to level 0 J Setting port P5 direction register b7 b0 Port P5 direction register Address D16 TBOi pin TB1iwpin Clear the corresponding bit to 0 Ne A N Setting count start bit to 1 b7 b0 Count start register Address 4016 Timer BO count start bit Timer B1 count start bit M Note The timer Bj overflow flag is a read only bit This bit is undefined after reset When a value is written to the timer Bj mode register with the count start bit 1 this bit is cleared to 0 at the next count timing
384. mer mode Count source select bits b7 b6 00 f2 0 1 16 10 fea 1 1 f512 X It may be either 0 or 1 i e ji Setting division ratio b15 b8 p o b7 bo Timer BO register Addresses 5116 5016 Timer B2 register Addresses 5516 5416 L Can be set to 0000 e to FFFF e n Note The counter divides the count source by n 1 E Xe Setting interrupt priority level b7 bO 8 Timer Bi interrupt control register i O to 2 Addresses 7A16e to 7C16 Interrupt priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level O iN a k Setting count start bit to 1 b7 b0 Count start register Address 4016 Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit J Count Starts Fig 9 3 2 Initial setting example for registers relevant to timer mode 9 10 7721 Group User s Manual TIMER B 9 3 Timer mode 9 3 2 Count source In the timer mode the count source select bits bits 6 and 7 at addresses 5B16e to 5D16 select the count source Table 9 3 2 lists the count source frequency Table 9 3 2 Count source frequency Count source Count Count source frequency select bits source b7 b6 f Xin 8 MHz f Xin 16 MHz f Xin 25 MHz 0 0 12 5 MHz 0 500 kHz 1 5625 MHz 1 0 125 kHz 250 kH
385. mory Transfer from I O to memory Transfer time per 1 unit transfer Write cycle of memory In 1 bus cycle transfer 1 transfer unit data is accessed in 1 bus cycle so that limitations are imposed on the transfer conditions to be applied Table 13 4 5 lists the conditions of 1 bus cycle transfer and the transfer time per 1 unit transfer and Figure 13 4 7 shows the bus cycle operation waveforms in 1 bus cycle transfer Table 13 4 5 Conditions of 1 bus cycle transfer and Transfer time per 1 unit transfer External Transfer Address directions Data s start Read Write ce eae o 16 bits 16 bits Fixed Forward Even i 2 3 c including Low internal Backward Even 7 L L Odd 2 i bus i li Backward 8 bits 16 bits Fixed Forward Even Odd me emo Backward Backward Address directions Refer to section 13 4 2 3 Address directions in 1 bus cycle transfer There is no address direction on the I O side i A term of E L in 1 bus cycle i 1 at No Wait and i 2 at With Wait or DRAM area When Ready function is used Refer to section 3 3 Ready function the number of cycles extended by Ready must be added Indicates the corresponding waveform in Figure 13 4 7 1 bus cycle transfer cannot be performed When the external data bus width 16 bits and the transfer unit 8 bits are selected the data bus which the memory uses and the data bus to which I O is conn
386. n the data bus and they collide with each other For the system that transfers data with 16 bit external data bus width from an external memory to an 8 bit I O the external memory must be composed to be read in a unit of 8 bits If the external memory cannot be read in a unit of 8 bits the data read from the external memory at data copy collides with the copied data on the data bus Under the following conditions 1 bus cycle transfer cannot be performed Refer to Table 13 4 5 External data bus width 16 bits Transfer unit 16 bits Address direction of memory Fixed or Forward Data s start address of memory Odd External data bus width 16 bits Transfer unit 16 bits Address direction of memory Backward Data s start address of memory Even External data bus width 16 bits Transfer unit 16 bits Target memory of DMA transfer DRAM area Address direction of memory Backward Data s start address of memory Odd External data bus width 8 bits Transfer unit 16 bits 7721 Group User s Manual 13 47 DMA CONTROLLER 13 4 Operation 13 4 3 Burst transfer mode The burst transfer mode can operate in either edge sense or level sense mode 1 2 13 48 Burst transfer mode edge sense When the transfer mode select bit O and the edge sense level sense select bit 0 this mode is selected Refer to Figures 13 2 6 and 13 2 8 In this mode all of the DMA request sources
387. nder the following conditions Transfer source address direction forward start address of data even with Wait Transfer destination address direction backward start address of data even without Wait O Q04 0 2 1 3 4 3 4 1 12 cycles 7721 Group User s Manual 13 99 DMA CONTROLLER 13 9 DMA transfer time 3 Transfer of array state In the following cases the processing in an array state and the first 1 unit transfer are performed sequentially Refer to Figures 13 8 10 and 13 8 11 Array chain transfer mode the first transfer of each block Link array chain transfer mode the first transfer of each block Right to use bus CPU NE DMAC EN CPU Transition Array state Transfer Transition lt _ gt m a i mo Fig 13 9 3 Transfer of array state Transition of the right to use bus from CPU to DMAC 1 cycle Array state The number of transfer parameters x the number of reads of a transfer parameter x the number of bus cycles for a read 1 cycle Refer to Table 13 9 1 DMA transfer per 1 unit transfer e In 2 bus cycle transfer Read cycle Write cycle Add a value which satisfies the read write conditions Refer to Table 13 4 1 e In 1 bus cycle transfer Refer to Table 13 4 5 Transition of the right to use bus from DMAC to CPU 1 cycle Example Link array chain transfer mode external data bus width 16 bits 2 bus cycle transfer transfer unit 16 bits and under th
388. nerate refresh requests for DRAM data Assuming that the set value of the refresh timer n the refresh timer counts fie n 1 times Figure 14 2 4 shows the structure of the refresh timer and the following formula gives the value to be written to the refresh timer n m us x UL 1 n a set value of the refresh timer n 0116 FFie m a refresh interval Examples of m an average of 15 625 us for 512 refresh cycles at 8 ms intervals an average of 125 us for 512 refresh cycles at 64 ms intervals Refresh timer Address 6616 7 to O These bits can be set to 0116 to FF e Undefined WO Assuming that the set value n this register divides fie by n 1 Note Use the LDM or STA instruction for writing to this register Do not set this register to 00 6 Fig 14 2 4 Structure of refresh timer 7721 Group User s Manual 14 5 DRAM CONTROLLER 14 2 Block description 14 2 3 Address comparator The address comparator examines whether the address to be accessed is within the DRAM area When this address is within DRAM area control signals are sent to the RAS and CAS generating circuit and the address multiplexer 14 2 4 RAS and CAS generating circuit The RAS signal a timing signal to latch a row address and the CAS signal a timing signal to latch a column address are generated by a control signal from the address comparator 14 2 5 Address multiplexer Address data is time shared by the
389. ng conditions to are satisfied When an external clock is selected satisfy conditions to with the following precondition satisfied lt Precondition gt The CLKi pin s input is at H level Note When an internal clock is selected the above precondition is ignored Transmission is enabled transmit enable bit 1 Transmit data is present in the UARTI transmit buffer register transmit buffer empty flag 0 The CTSi pin s input is at L level when the CTS function selected Note When the CTS function is not selected condition is ignored By connecting the RTSi pin receiver side and CTSi pin transmitter side the timing of transmission and that of reception can be matched For details refer to section 11 3 5 Receive operation When using interrupts it is necessary to set the relevant registers to enable interrupts For details refer to CHAPTER 7 INTERRUPTS Figure 11 3 2 shows writing data after start of transmission and Figure 11 3 3 shows detection of transmit completion 11 18 7721 Group User s Manual UARTO transmit receive mode register Address 3016 UART1 transmit receive mode register Address 3816 b7 b0 Clock synchronous serial I O mode Internal External clock select bit 0 Internal clock 1 External clock Ne X It may be 0 or 1 al UARTO transmit receive control register 0 Address 3416 UART1 transmit receive c
390. nput EN tc Ck a tw CKH CLKi input th C Q RxDi input tw INL INTi input tw INH Test conditions Vcc 5 V 10 Input timing voltage Vi 1 0 V Viu 4 0 V Output timing voltage Vor 0 8 V Vor 2 0 V 17 86 7721 Group User s Manual APPENDIX Appendix 11 Electrical characteristics Ready and Hold Timing requirements Vcc 5 V 10 Vss 0 V Ta 20 to 85 C f Xw 25 MHz unless otherwise noted zm tsuRDY 1 RDY input setup time 55 La ns tsu HOLD 1 HOLD input setup time O e ns th i RDY RDY input hold time pol ns th i HoLD HOLD input hold time pj j ns Switching characteristics Vcc 5 V 10 Vss 0 V Ta 20 to 85 C f Xin 25 MHz unless otherwise noted taw st STO ST1 output delay time 40 ns Note Figure 13 shows the test circuit 7721 Group User s Manual 17 87 APPENDIX Appendix 11 Electrical characteristics Ready function With no Wait 1 E output RDY input tsu RDY 1 lt gt th o1 RDY gt lt With Wait o1 E output RDY input tsu RDY 1 th o1 RDY wp Test conditions Vcc 5 V 10 96 Input timing voltage Vit 1 0 V Viu 4 0 V Output timing voltage Vor 0 8 V Vor 2 0 V Hold function 1 tsu HOLD 1 th o1 HOLD HOLD input td 1 STi td 1 STi STi output Test conditions Vcc 5 V 10 eInput timing voltage Vit 1 0 V
391. nput pins to 0 ANa Set bit 7 to O when ANs selecting external trigger AN6 AN7 F while the A D converter halts before a trigger occurs Fig 12 5 1 4 b7 bO pat TT 11 b Set A D conversion start bit to 1 A D control register address 1E16 A D conversion start bit P When external trigger is selected Input Input falling edge to ADrRG i When internal trigger is selected Y Trigger occur Operation start Initial setting example for registers relevant to one shot mode 7721 Group User s Manual 12 15 A D CONVERTER 12 5 One shot mode 12 5 2 One shot mode operation description 1 When an internal trigger is selected The A D converter starts operation when the A D conversion start bit is set to 1 The A D conversion is completed after 57 cycles of dav Then the contents of the successive approximation register conversion result are transferred to the A D register i At the same time as step G the A D conversion interrupt request bit is set to 1 The A D conversion start bit is cleared to O and the A D converter stops operation 2 When an external trigger is selected The A D converter starts operation when the input level to the ADtra pin changes from H to L while the A D conversion start bit is 1 The A D conversion is completed after 57 cycles of dav Then the contents of th
392. nquishes the bus to a DRAM refresh or a Hold function When DMAC regains the right to use bus after the DRAM refresh ends or the Hold state is removed DMA transfer is restarted at the following address e When DMA request is generated during DRAM refresh or in Hold state DMAC gains the right to use bus after the DRAM refresh ends or the Hold state is removed e When DMA request is generated while CPU uses bus Upon end of the bus cycle DMAC gains the right to use bus if any DRAM refresh request or Hold request is not generated at that time If a DRAM refresh request or a Hold request is generated when the bus cycle ends DMAC gains the right to use bus after the DRAM refresh ends or the Hold state is removed For details refer to section 13 2 1 Bus access control circuit and bus request sampling signals in timing diagrams 13 1 3 Modes DMAC has the following transfer methods and modes Because these methods and modes are independent each other any combination between them is selectable 1 Data transfer method E 2 bus cycle transfer This is a method used to transfer data between memories A DMA transfer consumes 2 cycles a read and a write cycle of data For details refer to section 13 4 1 2 bus cycle transfer B 1 bus cycle transfer This is a method used to transfer data between a memory and an l O A read and write of data is carried out at the same time in 1 bus cycle so that high speed transfer can be accomplished For detai
393. nsfer mode edge sense selected When Burst transfer mode level sense selected When Cycle steal transfer mode selected VIl TJ S The above timing diagram applies on the following conditions e Single transfer mode or Repeat transfer mode 2 bus cycle transfer e No Wait DMAACKi valid TC valid e External source DMAREQi After DMAi request occurs L is input to the DMAREQ i pin the right to use bus is relinquished to DMAC at the shortest time Fig 13 3 2 Example of timing from determination of DMA request until DMA transfer execution 13 24 7721 Group User s Manual DMA CONTROLLER 13 3 Control 13 3 5 Termination of DMA transfer As the methods of terminating DMA transfer normal and forced termination are used 1 Normal termination All of the DMAi transfers terminate and DMAC stops This method is used in the single transfer array chain transfer and link array chain transfer modes In the repeat transfer mode however normal termination cannot be applied to terminating transfer then forced termination must be used Refer to 2 Forced termination of this section Table 13 3 4 lists the states of DMAC at normal termination Table 13 3 4 States of DMAC at normal termination Item DMAi interrupt request bit DMAi request bit DMAi enable bit TC output Channel priority levels State 1 In the burst transfer mode edge sense 0 In the burst transfer mode level sense not
394. nsfers 3 1 Add a value which satisfies the read write conditions Refer to Table 13 4 1 3 2 When the transfer unit is 16 bits the number of transfers the number of transfer bytes 2 When the transfer unit is 8 bits the number of transfers the number of transfer bytes e In 1 bus cycle transfer Refer to Table 13 4 5 Terminate processing 3 cycles Transition of the right to use bus from DMAC to CPU 1 cycle Example External data bus width 16 bits 2 bus cycle transfer transfer unit 216 bits the number of the transfer bytes 10 bytes and under the following conditions Transfer source address direction forward start address of data even with Wait Transfer destination address direction backward start address of data even without Wait 1 4 45 8 4 8 1 40 cycles 7721 Group User s Manual 13 101 DMA CONTROLLER 13 9 DMA transfer time 2 Repeat transfer mode In the repeat transfer mode of burst transfer edge sense the method of terminating DMA transfer is only the forced termination by the TC input Therefore the time from the CPU s relinquishing the right to use bus until regaining the right depends on the timing of the TC input TC input Right to use bus Transfer Transition 2E 1 block Fig 13 9 5 Repeat transfer mode burst transfer mode and edge sense selected Transition of the right to use bus from CPU to DMAC 1 cycle DMA transfer per
395. nsmit register Transmission completed Nothing is assigned umeime Fig 11 2 3 Structure of UARTi transmit receive control register 0 1 2 CTS RTS select bit bit 2 By clearing this bit to 0 in order to select the CTS function pins P80 and P8 function as CTS input pins and the input signal of L level to these pins becomes one of the transmission conditions By setting this bit to 1 in order to select the RTS function pins P80 and P84 become RTS output pins When the receive enable bit bit 2 at addresses 3516 3D e is 0 reception disabled the RTS output pin outputs H level In the clock synchronous serial I O mode the output level of the RTS pin becomes L when reception conditions are satisfied and it becomes H when reception starts Note that when an internal clock is selected bit 3 at addresses 3016 38 e 0 the RTS output is undefined Accordingly do not select the RTS function In the clock asynchronous serial I O mode the output level of the RTS pin becomes L when the receive enable bit is set to 1 It becomes H when reception starts and it becomes L when reception is completed Transmit register empty flag bit 3 This flag is cleared to 0 when the UARTi transmit buffer register s contents are transferred to the UARTi transmit register When transmission is completed and the UARTi transmit register becomes empty this flag is set to
396. nter The decrementer is a 24 bit register After every 1 unit transfer that decrements the contents of TCRi by 1 when the transfer unit is 8 bits and by 2 when 16 bits In the array chain transfer mode every time a transfer parameter is read the contents of the TCRi latch are also decremented by 1 13 2 9 DMA latch The DMA latch is a 16 bit latch In 2 bus cycle transfer mode the DMA latch maintains the value read from the transfer source memory with a read cycle until this value is written into the transfer destination memory In 1 bus cycle transfer mode the DMA latch is used to copy data For copy refer to section 13 4 2 1 bus cycle transfer 7721 Group User s Manual 13 13 DMA CONTROLLER 13 2 Block description 13 2 10 DMAi mode register L Figure 13 2 6 shows the structure of DMAi mode register L For bit 0 refer to section 13 1 3 2 Transfer unit For bit 1 refer to section 13 4 1 2 bus cycle transfer and section 13 4 2 1 bus cycle transfer for bit 2 refer to section 13 4 3 Burst transfer mode and section 13 4 4 Cycle steal transfer mode 1 Transfer source address direction select bits bits 4 and 5 and Transfer destination address direction select bits bits 6 and 7 Address direction means an order of accessing memory in DMA transfer and is defined as follows Fixed direction an address does not move Forward direction an address moves upward from the specified start address
397. nter mode While counting is in progress by reading the timer Bj register the counter value can be read out at any timing However if the timer Bj register is read at the reload timing shown in Figure 9 4 4 the value FFFF16 is read out If reading is performed in the period from when a value is set into the timer Bj register with the counter stopped until the counter starts counting the set value is correctly read out Reload omes Tata Do Te Tes Head value Meg 2 1 0 FFFr n 1 Time n Reload register s contents Fig 9 4 4 Reading timer Bj register 9 18 7721 Group User s Manual TIMER B 9 5 Pulse period Pulse width measurement mode 9 5 Pulse period Pulse width measurement mode In this mode the timer measures an external signal s pulse period or pulse width Refer to Table 9 5 1 Timers BO and B1 can be used in this mode Figure 9 5 1 shows the structures of the timer Bj mode register and timer Bj register in the pulse period pulse width measurement mode Pulse period measurement The timer measures the pulse period of the external signal that is input to the TBjin pin Pulse width measurement The timer measures the pulse width L level and H level widths of the external signal that is input to the TBjw pin Table 9 5 1 Specifications of pulse period pulse width measurement mode Item Specifications Count source f2 f16 f64 or f512 Count operation Countup Counter value
398. nter mode Pulse output function select bit 0 No pulse output 1 Pulse output Count polarity select bit 0 Counts at falling edge of external signal 1 Counts at rising edge of external signal Up down switching factor select bit 0 Contents of up down register 1 Input signal to TAjour pin C X It may be either 0 or 1 Setting up down register b7 b0 jojo Up down register Address 4416 Set the corresponding up down bit when the contents of the up down register are selected as the up down Timer A2 up down bit Switching factor Timer A3 up down bit 0 Countdown Timer A4 up down bit 1 Countup Timer A2 two phase pulse signal processing select bit Timer A3 two phase pulse signal processing select bit Timer A4 two phase pulse signal processing select bit Set the corresponding bit to 1 when the two phase pulse signal processing function is selected for timers A2 to A4 0 Two phase pulse signal processing function disabled 1 Two phase pulse signal processing C function enabled x Setting division ratio gt b15 b8 t b7 0 b7 bO Timer A3 register Addresses 4D16 4C16 Timer A4 register Addresses 4F16 4E16 Can be set to 0000 e to FFFF e n J The counter divides the count source frequency by n 1 when counting down or by FFFF e n 1 when counting up ES Continue to Figure 8 4 3
399. nterrupt routine Bit 4 of port P10 register O address 1616 Bit 5 of port P10 register 0 address 1616 Bit 4 of port P10 register 1 address 16 6 Bit 5 of port P10 register lt 1 address 16 6 Flow chart Main routine i Port P104 CAS L level output Watchdog timer frequency 1 Watchdog timer count select bit bit 0 at address 6116 source fs selected Port P10s RAS Bits 4 5 of port P10 register 1 L level output address 16 6 Ports P104 P10s H level output Port P104 CAS H level output Bits 4 5 of port P10 direction 1 register address 18 6 Port P105 RAS DRAM validity bit c 0 H level output bit 7 at address 64 6 DRAMC stopped I WIT instruction Wait mode Y Wait mode completed Return to main routine y Note By using 1 bit of RAM judge whether this interrupt is for return from the wait mode or for refresh 1 2 17 74 7721 Group User s Manual APPENDIX Appendix 9 7721 Group Q amp A DRAM WIT instruction 2 Method using timer A or timer B Return from the wait mode by a timer A or timer B interrupt every definite time Control ports P104 P10s by software and perform the CAS before RAS refresh Example 2 A case in 512 refresh cycles every 64 ms f Xin 25 MHz timer AO used DRAM refresh is performed 512 times by timer
400. o both of the reload register and counter While counting is in progress When a value is written to the timer Bj register it is written only to the reload register Transferred to the counter at the next reload time n Timer Bj register s set value 7721 Group User s Manual TIMER B 9 4 Event counter mode b7 b6 b5 b4 b3 b2 bi b0 X gt gt 1 Timer Bj mode register j 0 1 Addresses 5B16 5C16 xxXE ol m Sume Fios sm n Um ae EE Operating mode select bits nr 01 Event counter mode RW L Count polarity select bits b3 b2 0 0 Count at falling edge of external signal 0 1 Count at rising edge of external signal 1 0 Counts at both falling and rising edges ooo S S of external signal RW l 1 1 Do not select fo nef Nothing is assigned s ld AE es sts This bit is invalid in event counter mode its value is undefined at Undefined reading Bees 2 U ee eee 6 These bits are invalid in event counter mode b7 bO b7 bO Timer BO register Addresses 5116 5016 15 to 0 These bits can be set to 000016 to FFFF e Undefined RW Assuming that the set value n the counter divides the count source frequency by n 1 When reading the register indicates the counter value Note Read from or write to this register in a unit of 16 bits Fig 9 4 1 Structures of timer Bj mode register and timer Bj register in event counter mode 7721 Group U
401. o the INT pin changes its level This is independent of clock i In the edge sense the interrupt request bit is set to 1 at this time 2 There are two methods one uses external interrupt s level sense and the other uses the timer s event counter mode Method using external interrupt s level sense As for hardware input a logical sum of multiple interrupt signals e g a b and c to the INT pin and input each signal to each corresponding port As for software check the ports input levels in the INTi interrupt routine in order to detect which signal a b or c was input M37721 O O w Method using timer s event counter mode As for hardware input interrupt signals to the TAiw pins or TBin pins As for software set the timer s operating mode to the event counter mode Then set a value 000016 into the timer register and select the valid edge The timer s interrupt request occurs when an interrupt signal selected valid edge is input 7721 Group User s Manual 17 71 APPENDIX Appendix 9 7721 Group Q amp A otack DRAM What are there the stack bank select bit bit 7 at address 5E e for It is supposed that DRAM is used as the stack area When connecting DRAM the stack pointer addressing mode or stack operation instruction etc can be used It is because all of 64 Kbytes can be used as the stack area when bank FF e which is assigned to DRAM is set as the stack
402. ode register H Address 1FCDs 6 Address 1FDD16 DMA2 mode register H Address 1FEDs 6 DMAS mode register H Address 1FFD16 Transfer direction select bit Used in 1 bus cycle I O connection select bit Valid in 1 bus cycle Transfer source wait bit Valid in DMA a b7 k b0 X DMAO control register DMA1 control register DMA2 control register DMAS control register Noms DMA request source select bits 0000 Do not select 1000 0 00 1 External source DMAREQi 1 0 0 1 0010 Software DMA source 1010 0011 Timer AO 1011 0100 Timer A1 1100 0101 Timer A2 1101 0110 Timer A3 1110 01141 Timer A4 1111 Edge sense Level sense select bit Note 0 Edge sense 1 Level sense DMAACKi validity bit 0 Invalid 1 Valid Address 1FCE16 Address 1FDEte Address 1FEE16 Address 1FFEt16 Timer BO Timer B1 Timer B2 UARTO receive UARTO transmit UARTI receive UARTI transmit A D conversion to 0 transfer 0 Wait 1 No wait Transfer destination wait bit Valid in DMA transfer 0 Wait 1 No wait N Selection of repeat transfer mode y b23 b16 b15 b8 b7 b0b7 b0b7 b0 Source address register 0 Addresses 1FC216 to 1FC016 SARO V Source address register 1 Addresses 1FD216 to 1FD016 SAR1 a Source address register 2 Addresses 1FE216 to 1FE016 SAR2 Source address register 3 Addresses 1FF21e to 1FF01e SAR3 b23
403. of other channels cannot be accepted until the DMA transfer which is in progress normally terminates or is forced into termination If a DRAM refresh request a Hold request or another DMA request including that of other channels is generated during a data transfer in the cycle steal transfer mode the bus request with the highest priority is accepted at the above mentioned bus request sampling If only several DMA requests are generated the request of the channel whose priority is highest is accepted If any bus request is not generated at the above mentioned bus sampling the right to use bus is relinquished to the CPU Note that no DMA request is accepted in array states 13 8 7721 Group User s Manual DMA CONTROLLER 13 2 Block description mg DRAM refresh 0 D This is the term in which the bus is not used so that sampingis performed every 1 cycle of 0 Sampling is performed after completion of a refresh cycle Sampling is performed after completion of E Refresh request BUS REQUEST DRAMC 1 bus cycle D Q e Q Bus request sampling E N STI STO 1 1 0 0 1 1 0 0 1 1 ME LL 1 i i Refresh i Bus em by Refresh Transition of right Transition of right Transition of right Transition of right to use bus to use bus to use bus to use bus E Hold Q m m EE BM D This is the term in which the bus is not E 1 TE T i used so that sampling is performed eve
404. of this bit is 0 at reading Interrupt priority detection 7 cycles of gt time select bits 4 cycles of 2 cycles of Do not select Fix this bit to 0 Bank FF 6 Bits 0 to 2 and bits 4 to 7 are not used for software reset Software reset bit The microcomputer is reset by writing 1 to this bit Fig 4 2 1 Structure of processor mode register 0 7721 Group User s Manual 4 13 RESET 4 2 Software reset When the software reset bit is set to 1 the RESETour pin s output level becomes L In a period of 4 5 cycles of clock after the software reset bit is set to 1 the RESETour pin s output level is L Figure 4 2 2 shows the RESETour output timing at software reset a Set software reset bit to 1 RESETour Fig 4 2 2 RESETovr output timing 4 14 7721 Group User s Manual CHAPTER S CLOCK GENERATING CIRCUIT 5 1 Oscillation circuit examples 5 2 Clocks 5 3 Stop mode Precautions for Stop mode 5 4 Wait mode Precautions for Wait mode CLOCK GENERATING CIRCUIT 5 1 Oscillation circuit examples 5 1 Oscillation circuit examples To the oscillation circuit a ceramic resonator or a quartz crystal oscillator can be connected or the clock which is externally generated can be input Oscillation circuit examples are shown below 5 1 1 Connection example using resonator oscillator Figure 5 1 1 shows an example wh
405. om the external Fig 11 4 6 Example of transmit timing when transfer data length 8 bits when parity enabled selecting 1 stop bit not selecting CTS function es Transfer clock Transmit enable bit I Data is set in UARTIi transmit buffer register Transmit buffer Qa d p empty flag Em UARTi transmit register UARTI transmit buffer register CTSi TENDi Parity Stop Stopped because CTS H Stopped because transmit i Start bit Y enable bit 0 TxDi Transmit register empty flag UARTI transmit interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software The above timing diagram applies TENDi Next transmit conditions are examined when this signal level is H id at following conditions are TEND is an internal signal Accordingly it cannot be read from the external Parity enabled 1 stop bit e CTS function selected Tc 16 n 1 fi or 16 n 1 fEXT fi BRGi s count source frequency f2 f16 fe4 f512 fExT BRGi s count source frequency external clock n Value set in BRGi Fig 11 4 7 Example of transmit timing when transfer data length 8 bits when parity enabled selecting 1 stop bit selecting CTS function 7721 Group User s Manual 11 39 SERIAL I O 11 4 Clock asynchronous serial I O UART mode Transfer clock Transmit enable bit Data is set in UARTi transmit buffer register Transmit buffer
406. omparator Therefore this pin cannot be used as an analog input pin When the AN pin is selected as an analog input pin while an external trigger is selected the A D converter operates however an undefined value is stored into the A D register 7 Refer to Appendix 8 Countermeasure against noise when using the A D converter 12 28 7721 Group User s Manual CHAP TIER 13 DMA CONTROLLER 13 1 Overview 13 2 Block description Precautions for DMAC 13 3 Control 13 4 Operation Precautions for 2 bus cycle transfer Precautions for 1 bus cycle transfer Precautions for burst transfer mode Precautions for cycle steal transfer mode 13 5 Single transfer mode 13 6 Repeat transfer mode 13 7 Array chain transfer mode Precautions for array chain transfer mode 13 8 Link array chain transfer mode Precautions for link array chain transfer mode 13 9 DMA transfer time DMA CONTROLLER 13 1 Overview 13 1 Overview The DMA controller hereafter called DMAC transfers data using the bus and bypassing the CPU DMAC of the M37721 provides four independent channels of DMAO DMAS which have the same function each In this chapter the source and destination of each DMA transfer are represented as follows e Memory A device which needs its own address to be specified Examples Internal RAM and SFRs external memory and memory mapped I Os e 1 0 A device which does not need its own address to be spec
407. on and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics To all our customers Regarding the change of names mentioned in the document such as Mitsubishi Electric and Mitsubishi XX to Renesas Technology Corp The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April Ist 2003 These operations include microcomputer logic analog and discrete devices and memory chips other than DRAMs flash memory SRAMS etc Accordingly although Mitsubishi Electric Mitsubishi Electric Corporation Mitsubishi Semiconductors and other Mitsubishi brand names are mentioned in the document these names have in fact all been changed to Renesas Technology Corp Thank you for your understanding Except for our corporate trademark logo and corporate statement no changes whatsoever have been made to the contents of the document and these changes do not constitute any alteration to the contents of the document itself Note Mitsubishi Electric will continue the business operations of high frequency amp optical devices and power devices Renesas Technology Corp Customer Support Dept April 1 2003 24 NE SAS Renesas Technology Corp C T CD c T ST 2 16 7721 Group User s Manual MITSUBISHI 16 BIT SINGLE CHIP MICROCOMPUTER 7700 FAMILY
408. on next page Fig 8 4 2 Initial setting example for registers relevant to event counter mode 1 7721 Group User s Manual 8 21 TIMER A 8 4 Event counter mode From preceding Figure 8 4 2 Setting interrupt priority level b7 bO Timer Aj interrupt control register j 2 to 4 Addresses 7716 to 7916 Interrupt priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 Setting port P5 direction register b7 bO Port P5 direction register Address D16 TA20UT pin TA2IN pin TASOUT pin TASIN pin TA40uT pin TA4IN pin Clear the bit corresponding to the TAjin pin to 0 When selecting the TAjour pin s input signal as the up down switching factor set the bit corresponding to the TAjour pin to 0 When selecting the two phase pulse signal processing function set the bit corresponding to the TAjour pin to 0 Setting the count start bit to 1 b7 b0 Count start register Address 4016 Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Count starts Fig 8 4 3 Initial setting example for registers relevant to event counter mode 2 8 99 7721 Group User s Manual TIMER A 8 4 Event counter mode 8 4 2 Operation in event counter mode When the count start bit is set to 1 the counter starts counting of the coun
409. one block transfer source s transfer start address transfer destination s transfer start address transfer data s byte number next transfer parameter memory s start address e n 1 bus cycle transfer 12 bytes per one block from memory to I O transfer source s transfer start address transfer data s byte number next transfer parameter memory s start address from I O to memory transfer destination s transfer start address transfer data s byte number next transfer parameter memory s start address SARi latch 0 and TCHi 0 Falling edge of TC pin s input from H to L when the TC pin validity bit 1 e Write 0 to the DMAi enable bit At normal termination SARi latch Indicates the transfer parameter memory s start address of the next block SARI Indicates the address of the next transfer source DARi latch Not used DARI Indicates the address of the next transfer destination TCRi latch Not used TCRi Indicates the number of remaining bytes being transferred TC pin validity bit Bit 1 at address 6816 13 80 7721 Group User s Manual DMA CONTROLLER 13 8 Link array chain transfer mode b23 b16 b15 b8 b7 b0 Vo 1 Source address register 0 Addresses 1FC21e to 1FC016 SARO Source address register 1 Addresses 1FD21e to 1FD0 6 SAR1 Source address register 2 Addresses 1FE216 to 1FE016 SAR2 Source address register 3 Addresses 1FF216 to 1FF016e SAR3 23 to o Write
410. ons Transfer source address direction forward start address of data even with Wait Transfer destination address direction backward start address of data even without Wait O Q O2 1 3 4 1 9 cycles 13 98 7721 Group User s Manual DMA CONTROLLER 13 9 DMA transfer time 2 Last transfer of each block In the following cases 1 unit transfer and the processing for 3 cycles are performed sequentially Refer to Figures 13 8 13 and 13 8 14 e Single transfer mode the last 1 unit transfer Repeat transfer mode the last 1 unit transfer of a block Array chain transfer mode the last 1 unit transfer of each block including the last block Link array chain transfer mode the last 1 unit transfer of each block including the last block use CPU EN DMAC W CPU Transition Transfer Termination yan sition 04 998 2 M D Fig 13 9 2 Last transfer of each block Transition of the right to use bus from CPU to DMAC 1 cycle DMA transfer per 1 unit transfer e In 2 bus cycle transfer Read cycle Write cycle Add a value which satisfies the read write conditions Refer to Table 13 4 1 e In 1 bus cycle transfer Refer to Table 13 4 5 Terminate processing or the last processing of each block 3 cycles Transition of the right to use bus from DMAC to CPU 1 cycle Example 2 bus cycle transfer transfer unit 216 bits external data bus width 16 bits and u
411. ontents of the program counter PC and the processor status register PS are simultaneously pushed in a unit of 16 bits When the contents of the stack pointer S are odd each of these registers is pushed in a unit of 8 bits Figure 7 7 3 shows the push operation for registers In the INTACK sequence only the contents of the program bank register PG program counter PC and processor status register PS are pushed onto the stack area The other necessary registers must be pushed by software at the start of the interrupt routine By using the PSH instruction all CPU registers except the stack pointer S can be pushed 1 When contents of stack pointer S are even Address S l 5 0 orae hush S 4 even 9 Pushed in a unit of 16 bits Si 9 oca SI 2 een Pushed in a unit of 16 bits SI ttes a S even 4 0 Program bank register PG Pushed in 3 times 2 When contents of stack pointer S are odd Address S 5 even Ohhh Order for push 4 oa o S1 3 oven s S 2 odd lt r Pushed in a unit of 8 bits S1 oven lt o S odd Program bank register PG L j S is an initial address that the stack pointer S indicates when an interrupt request is accepted The S s contents become S 5 after all of the above registers are pushed Pushed in 5 times Fig 7 7 3 Push operation for registers 7721 Group User s Manual 7 15
412. ontrol register 0 Address 3C16 b7 b0 T BRG count source select bits b1 b0 00 fe 0 1 f16 1 0 f64 1 1 f512 CTS RTS select bit 0 CTS function selected 1 RTS function selected CTS function disabled 2 UARTO baud rate register BRG0 Address 3116 UART1 baud rate register BRG1 Address 3916 b7 b0 x JA Can be set to 0016 to FF46 Necessary only when internal clock is selected i UARTO transmit interrupt control register Address 7116 UART1 transmit interrupt control register Address 7316 b7 bO LH Interrupt priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 M 2 P a lt P SERIAL I O 11 3 Clock synchronous serial l O mode ES UARTO transmit buffer register Address 3216 UART1 transmit buffer register Address 3A16 b7 bO J C I ES Transmit data is set f UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 b7 bO BREED NE Transmit enable bit ies 1 Transmission enabled E Transmission starts In the case of selecting the CTS function transmission starts when the CTSi pin s input level is L Fig 11 3 1 Initial setting example for relevant registers when transmitting
413. onversion result are transferred to the A D register O For all of the selected analog input pins the A D conversion is performed The conversion result is transferred to the A D register i each time each pin is converted For all of the selected analog input pins the A D conversion is performed again The operation is performed repeatedly until the A D conversion start bit is cleared to 0 by software When the level of the ADtra pin changes from H to L during operation the operation at that point is cancelled and is restarted from step Figure 12 8 2 shows the conversion operation in the repeat sweep mode 12 26 7721 Group User s Manual A D CONVERTER 12 8 Repeat sweep mode Trigger occur Conversion result Convert input voltage from ANo pin lt A D register 0 N Conversion result l Convert input voltage from AN1 pin A D register 1 l Conversion result Convert input voltage from ANi pin A D register i Fig 12 8 2 Conversion operation in repeat sweep mode 7721 Group User s Manual 12 27 A D CONVERTER 12 9 Precautions for A D converter 12 9 Precautions for A D converter 1 Writing to the following must be performed before a trigger occurs while the A D converter halts Each bit except bit 6 of the A D control register Each bit of the A D sweep pin select register When an external trigger is selected the AN7 ADrrc pin is disconnected from the c
414. or slow up or slow down from the timer AO set value data table to the timer AO register Refer to Figure 16 2 6 After slow up or slow down is completed a DMA2 interrupt occurs Phase output is performed by RTPO pulse output mode 0 Refer to Figures 16 2 6 and 16 2 7 eAfter slow up or slow down is completed the motor operates with the definite rate M37721 Phase output B B qata table RT HN SS MI otepping motor Motor driver Timer AO set lue data tabl UD S value data table Fig 16 2 6 Example of stepping motor control 16 48 7721 Group User s Manual APPLICATION 16 2 Examples of using DMA controller Table 16 2 1 Example of phase output data table 22 phase 1 2 phase 0 0011 2 100 3 1000 4 1100 6 0110 7 0010 Fig 16 2 7 Example of phase output 7721 Group User s Manual 16 49 APPLICATION 16 2 Examples of using DMA controller 2 Initial setting example for relevant register b7 bO OO 14 0 1 DMA1 mode register L Address 1FDC16 Transfer unit 8 bits 2 bus cycle transfer Cycle steal transfer mode Transfer source address direction At regular turning 012 Forward At reverse turning 102 Backward Transfer destination address direction Fixed b7 b0 0 14 1 0 0 0 X 0 DMA1 mode register H Address 1FDDie Transfer source Wait No transfer destination Wait Repeat transfer mode b23 616615 b8b7 b0 Source a
415. ore CAS Note I tnicas ca Column address hold time afrer CAS Note ns intoAs em Bi hold ime after EMEN ZZ Ls s ns to e RASL B LatE CASD GAS ey ime aher E swa iis aa 118 ns tae rast RAS delay time after E s high level ts late CASH CAS delay time after E s high level SSE 20 ns Note Figure 13 shows the test circuit ta R w RaAs R W delay dme before R HAS nae agl o ns Refresh state tras RAS low level pulse wan moo a ns twoas CAS low level pulse width Note 55 ns tacas ras CAS RAS delay time Note 175 ns tneas oas CAS hold time after RAS Note 175 d ns Note Figure 13 shows the test circuit 7721 Group User s Manual 17 95 APPENDIX Appendix 11 Electrical characteristics At DRAM control ON Z NF NF NSN E ta RAS CAS tw RASH lt y tw RASL Sac lt 9 th RAS RA la E RASH p RAS output td RA RAS ta R W RAS X gt te td E RASL td E CASH th CAS R W w CASL 4 9 At read ld CA CAS Kk th CAS CA DUE Row address X Column address y td E CA R W output td RAS CAS lt a 5 tw RASH tw RASL a lt y th RAS RA ta E RASH i ta R W RAS gt L lt ta E RASL s h CAS R W I lt CAS output d E CASL tw CASL lt gt At write td CA CAS 49 th CAS CA i
416. ould be as short as possible Use thicker wiring for the Vss and Vcc lines than that for the other signal lines Bypass capacitor Wiring pattern Wiring pattern Vss Vcc M37721 Fig 6 Bypass capacitor between Vss and Vcc lines 17 60 7721 Group User s Manual APPENDIX Appendix 8 Countermeasure against noise 3 Wiring for analog input pins analog power source pins etc 1 Processing for analog input pins Connect a resistor to the analog signal line which is connected to an analog input pin in series Additionally connect the resistor to the microcomputer as close as possible Connect a capacitor between the analog input pin and the AVss pin as close to the AVss pin as possible Reason A signal which is input to the analog input pin is usually an output signal from a sensor The sensor which detects changes in status is installed far from the microcomputer s printed circuit board Therefore this long wiring between them becomes an antenna which picks up noise and feeds it into the microcomputer s analog input pin If a capacitor between an analog input pin and the AVss pin is grounded far away from the AVss pin noise on the GND line may enter the microcomputer through the capacitor Note 2 Acceptable M37721 Thermistor Heference values RI Approximate 100 Q to 1000 Q CI Approximate 100 pF to 1000 pF Notes 1 Design an external circuit for the ANi pin so that charge discharge is avail
417. ount start bit Timer A3 count start bit Timer A4 count start bit Trigger input to TAjin pin uununnununuunnumuunu unnun unnun un nun n nun unnunuun unn un nunununun ee Trigger generated Count Fig 8 6 3 Initial setting example for registers relevant to PWM mode 2 7721 Group User s Manual 8 41 TIMER A 8 6 Pulse width modulation PWM mode 8 6 2 Count source In the PWM mode the count source select bits bits 6 and 7 at addresses 5816 to 5A e select the count source Table 8 6 2 lists the count source frequency Table 8 6 2 Count source frequency Count source Count Count source frequency select bits source b7 b6 f Xin 25 MHz 0 0 12 5 MHz 0 I 1 5625 MHz 0 390 625 kHz t 48 8281 kHz 8 6 3 Trigger When a trigger is generated the TAjour pin starts outputting PWM pulses An internal or an external trigger can be selected as that trigger An internal trigger is selected when the trigger select bits bits 4 and 3 at addresses 5816 to 5A e are 002 or O12 an external trigger is selected when the bits are 102 or 112 A trigger generated during outputting of PWM pulses is invalid and it does not affect the pulse output operation 1 When selecting internal trigger A trigger is generated when 1 is written to the count start bit address 401s 2 When selecting external trigger A trigger is generated at the falling e
418. ource select bits Data bus odd f2 o f 16 9 N Data bus even f 64 O f 512 _o High order 8 bits Timer mode Pulse period Pulse width measurement mode Event counter Timer Bi mode o m interrupt request bit Count start bit Timer Bj Count start bit Lg flag Valid in pulse period pulse width measurement mode Counter reset circuit i 0 2 j 0 1 Polarity switching and edge pulse generating circuit Fig 9 2 1 Block diagram of Timer B 9 2 7721 Group User s Manual TIMER B 9 2 Block description 9 2 1 Counter and reload register timer Bi register Each of timer Bi counter and reload register consists of 16 bits and has the following functions 1 Functions in timer mode and event counter mode 2 Countdown in the counter is performed each time the count source is input The reload register is used to store the initial value of the counter When a counter underflow occurs the reload register s contents are reloaded into the counter A value is set to the counter and reload register by writing the value to the timer Bi register Table 9 2 1 lists the memory assignment of the timer Bi register The value written into the timer Bi register when the counting is not in progress is set to the counter and reload register The value written into the timer Bi register when the counting is in progress is set only to the reload register In this case the reload register s updated con
419. ow order Data 3 High order Low order Data 2 High order Low order Data 1 High order Transfer sequence Data arrangement on transfer destination memory transfer result Data arrangement on transfer source memory External data bus width 16 bits or 8 bits Transfer unit 8 bits Data arrangement on transfer destination memory transfer result Transfer sequence Backward Forward Low order Data 3 High order Low order Data 2 High order Low order Data 1 High order Low order Data 1 High order Low order Data 2 High order Low order Data 3 High order Backward Backward Transfer start address Low order Data 3 High order Low order Data 2 High order Low order Data 1 High order Low order Data 3 High order Low order Data 2 High order Low order Data 1 High order 13 36 7721 Group User s Manual DMA CONTROLLER 13 4 Operation Precautions for 2 bus cycle transfer When the 16 bit external data bus width 16 bits and the transfer unit 16 bits under the following conditions 2 bus cycle transfer cannot be performed Refer to Table 13 4 1 Conditions for transfer destination Transfer destination DRAM area Address direction Backward Data s start address Odd address e Conditions for transfer source and destination Transfer source DRAM area Address direction Backward Data s start addre
420. ows an initial setting example for registers relevant to the one shot mode When using an interrupt it is necessary to set the relevant registers to enable the interrupt Refer to CHAPTER 7 INTERRUPTS for more descriptions 2 14 7721 Group User s Manual A D CONVERTER 12 5 One shot mode Y a A D control register o jojo A D control register address 1 E16 b7 bO ae Analog input select bits b2 b1 bO 0 ANo selected AN1 selected AN2 selected ANs selected AN4 selected ANs selected ANe selected AN7 selected OOO O OO 0o O One shot mode Trigger select bit 0 Internal trigger 1 External trigger A D conversion start bit 0 Stop A D conversion b A D conversion frequency AD select bit 0 f2 divided by 4 1 f2 divided by 2 P lnterrupt priority level Interrupt priority level select bits Set to a level between 1 to 7 when using this interrupt Set to a level 0 when disabling this interrupt A D conversion interrupt control register address 7016 aN d Port P7 direction register b7 bO d Note Writing to each bit except bit 6 of the A D control register must be performed mi Port P7 direction register address 1116 ANo AN1 AN Setthe bits corresponding AN O analog i
421. ows the conditions necessary for timings shown in Figures 13 8 7 13 8 8 and 13 8 10 through 13 8 14 For the cycle steal transfer mode refer to the following Transfer of transfer parameters in an array state Figures 13 8 10 and 13 8 11 All transfers except for that in an array state and except for the last 1 unit transfer of each block Figure 13 8 12 Last 1 unit transfer of each block except for the last block Figure 13 8 13 Last 1 unit transfer of the last block Figure 13 8 14 The processing performed in the link array chain transfer mode consists of an array state and a transfer state 1 Array state In an array state transfer parameters are read from the transfer parameter memory in a unit of 2 bytes and transferred to registers SARi DARi and TCRi and their latches As shown in Figure 13 8 2 a transfer parameter consists of 4 bytes 24 bits of data 8 bits of dummy data One bus cycle always consumes 3 cycles of 4 During an array state the DMAACKi pin outputs H level For the bus request sampling in an array state refer to section 13 2 1 Bus access control circuit 2 Transfer state Data is transferred in a transfer state For the bus request sampling in a transfer state refer to section 13 2 1 Bus access control circuit 7721 Group User s Manual 13 87 DMA CONTROLLER 13 8 Link array chain transfer mode On and after second First of each block SARI Trans
422. ows the structure of the real time output control register b7 b6 b5 b4 b3 b2 bi b0 as III Real time output control register Address 6216 See the following Table E Pulse output mode select bit re Pulse mode 0 Pulse mode 1 7 to 3 Nothing is assigned Undefined The value is 0 at reading f AL mom eee eee eee om mom mo momo mo momo momo m L L a TT w l s eeu ee me Note When using the P6o P6 7 pins as the pulse output pins for real time output set the corresponding bits of the port P6 direction register address 1016 to 1 P67 RTP13 P66 RT P12 P6s RTP1 P64 RTP1o P6s RTPOs P62 RTPO02 P6i RTPO Port P60o RTP0o P67 RI P13 P66 RI P12 P65 RTP1 P64 RTP10o P63 RTPOs P62 RTPO2 P61 RTPO P6o RTPOo P67 RTP13 P6e RTP 12 P6s5 RTP11 P64 RTP1o P6s RTPOs P62 RT P02 P6i RTPO Port P6o RTPOo P67 RTP13 P6e RTP 12 P6s5 RTP11 P64 RTP1o P6s RTP0s P62 RT P02 P6 RTPO RTP Peo RTPOo Port RTP When pulse mode 0 is selected P67 RTP13 P6s RTP12 P6s RTP11 P64 RTP1o P63 RTPOs P62 RTPO2 P6 RTPO E FH P67 RTP13 P6e RTP 12 P6s RTP1 P64 RTP1o P63 RTPO3 P62 RTPO2 P67 RTP13 gt P66 RTP12 P6s RTP11 P64 RTP10 RTP P6s RTPOs P62 RTPO2 J P61 RTPO EE PS P67 RTP13 P6e RTP 12 P6s5 RTP11 P64 RTP1o P63 RTPOs P62 RTPO2 gt Port When pulse mode 1 is selected P61i RTPOi P6o RTPOo P61
423. p mode refer to section 5 3 Stop mode For details about clocks refer to CHAPTER 5 CLOCK GENERATING CIRCUIT Powered on here Fig 4 1 11 Power on reset conditions The delay time is about 11 ms when Ca 0 033 pF taz 0 34 X Ca us Ca pF Fig 4 1 12 Example of power on reset circuit 4 12 7721 Group User s Manual RESET 4 2 Software reset 4 2 Software reset When the power source voltage satisfies the microcomputer s recommended operating conditions the microcomputer is reset by writing 1 to the software reset bit bit 3 at address 5E e This is called Software reset In this case the microcomputer initializes pins CPU and SFR area just as in the case of a hardware reset However the microcomputer retains the contents of the internal RAM area Refer to Table 4 1 1 and Figures 4 1 3 to 4 1 9 Figure 4 2 1 shows the structure of the processor mode register 0 address 5Et After completing initialization the microcomputer performs internal processing sequence after reset Refer to Figure 4 1 10 After that it executes a program beginning from the address set into the reset vector addresses FFFEi6 and FFFFie b7 b6 b5 b4 b3 b2 bli s e e Fix this bit to 0 Nothing is assigned This bit is 1 at reading Wait bit 0 Software Wait is inserted when accessing external area 1 No software Wait is inserted when accessing external area The value
424. pli s equipment test and measurement equipment audio and visual chine tools personal electronic equipment and industrial robots High Quality Transportation equipment au crime systems safety equipme trains ships etc traffic control systems anti disaster systems anti medical equipment not specifically designed for life support Specific Aircraft aerospace systems for life suppo intervention ipment submersible repeaters nuclear reactor control systems medical equipment or tificial life support devices or systems surgical implantations or healthcare tc and any other applications or purposes that pose a direct threat to human life s products described in this document within the range specified by Renesas Electronics rating operating supply voltage range movement power voltage range heat radiation r product characteristics Renesas Electronics shall have no liability for malfunctions or Renesas Electronics products beyond such specified ranges especially with respect t characteristics installatio damages arising out of the u Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety me
425. pt priority level b7 b0 DMAI interrupt control register i 0 to 3 ity Addresses 6C16 to 6F 16 Interrupt priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 z Continue to Figure 13 8 4 on next page Fig 13 8 3 Initial setting example for registers relevant to link array chain transfer mode 1 13 84 7721 Group User s Manual DMA CONTROLLER 13 8 Link array chain transfer mode From preceding Figure 13 8 3 Selection of transfer mode and each function b7 b0 DMAO mode register L Address 1FCCte L O DMA1 mode register L Address 1FDCte DMA2 mode register L Address 1FECt6 DMA3 mode register L Address 1FFC16 Number of unit transfer bits select bit 0 16 bits 1 8 bits Transfer method select bit 0 2 bus cycle transfer 1 1 bus cycle transfer Transfer mode select bit 0 Burst transfer mode 1 Cycle steal transfer mode Transfer source address direction select bits 0 0 Fixed 0 1 Forward 1 0 Backward 1 1 Do not select Transfer destination address direction select bits 00 Fixed 0 1 Forward 1 0 Backward 1 1 Do not select b7 bO DMAO mode register H Address 1FCD16 DMA1 mode register H Address 1FDD16 DMA2 mode register H Address 1FED16 DMA3 mode register H Address 1FFD16 Transfer direction select bit Used in 1 bus cycle tran
426. put A0 A7 Address output As A15 BYTE H Address Data output As Ds A15 D15 BYTE L Data input Ds D15 BYTE L Address Data output A16 Do A23 D7 Data input Do D7 ALE output BHE output BLE output R W output Port Pi input i 2 4 10 Test conditions port Pi VVcc 5V t10 eInput timing voltage Vit 1 0 V Viu 4 0 V Output timing voltage Vor 0 8 V Vou 2 0 V tw L tw H t t t PIR U A JA JA AA A td AL E gt th E AL Addess ta AM E gt lh E AM CL Ades td AM E tpxz E DHZ MM td AM ALE gt th ALE AM tsu A DH tsu DH E gt gt mE re e AIT S tsu ALE DH td AH E gt lt gt tpxz E DLZ th ALE AH tsu A DL M EE tsu DL E td AH ALE modb HEN M E lsuALE DL tw ALE E td ALE E td BHE E gt th E BHE r BLE E th gt gt lt th E DL ae Se ye gt y Th E BLE th E R W ta R W E tsu PiD E Test conditions except port Pi Vcc 25V 10 Output timing voltage Vor 0 8 V Vor 2 0 V Data input Vi 0 8 V Viu 2 5 V 7721 Group User s Manual APPENDIX Appendix 11 Electrical characteristics DRAM control switching characteristics Vcc 5 V 10 Vss 0 V Ta 20 to 85 C f Xin 25 MHz unless otherwise noted Note The limits
427. puts L level At this time no timer Aj interrupt request occurs Continue to Note When operating as 16 bit pulse width modulator Period H level width fi Frequency of count source However if n 000016 the pulse width modulator does not operate and the TAjour pin outputs L level At this time no timer Aj interrupt request occurs Figure 8 6 3 Fig 8 6 2 Initial setting example for registers relevant to PWM mode 1 8 40 7721 Group User s Manual TIMER A 8 6 Pulse width modulation PWM mode From preceding Figure 8 6 2 Setting interrupt priority level b7 bO Timer Aj interrupt control register j 2 to 4 CAE Addresses 7716 to 7916 Interrupt priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 ise A When internal trigger is selected When external trigger is selected a Setting port P5 direction register gt S E b etting count start bit to 1 b7 0 Port P5 direction register b7 bO Address Die Count start register Address 4016 TAIN pin Timer A2 count start bit TAIN pin TAIN pin Timer A3 count start bit Timer A4 count start bit Clear the corresponding bit to 0 a y A UN Setting count start bit to 1 b7 bO Count start register Address 4016 Timer A2 c
428. quest occurs when the first valid edge is input after the counter starts counting 1 Pulse period Pulse width measurement The measurement mode select bits bits 2 and 3 at addresses 5B e and 5C e specify whether the pulse period of an external signal is measured or its pulse width is done Table 9 5 3 lists the relationship between the measurement mode select bits and the pulse period pulse width measurements Make sure that the measurement pulse interval from the falling edge to the rising edge and vice versa are two cycles of the count source or more Additionally use software to identify whether the measurement result indicates the H level or the L level width Table 9 5 3 Relationship between measurement mode select bits and pulse period pulse width measurements b3 b2 Measurement interval Valid edges o o From falling edge to falling edge Falling edges 0 1 From rising edge to rising edge Rising edges 1 0 From falling edge to rising edge and vice versa Falling and rising edges 2 Timer Bj overflow flag A timer Bj interrupt request occurs when a measurement pulse s valid edge is input or a counter overflow occurs The timer Bj overflow flag is used to identify the cause of the interrupt request that is whether it is an overflow occurrence or a valid edge input The timer Bj overflow flag is set to 1 by an overflow Accordingly the cause of the interrupt request occurrence is identified by checking the time
429. r Writing of next transmit data is possible E B Note This figure shows the bits and registers required for processing Refer to Figures 11 4 6 to 11 4 8 for the change of flag state and the occurrence timing of an interrupt request f Writing of next transmit data UARTO transmit buffer register Addresses 3316 3216 UART1 transmit buffer register Addresses 3B16 3A16 b15 b8 b7 bO 1 1 D V I V Set transmit data here E Fig 11 4 4 Writing data after start of transmission 11 36 7721 Group User s Manual SERIAL I O 11 4 Clock asynchronous serial I O UART mode When not using interrupts When using interrupts A UARTI transmit interrupt request occurs when transmission starts z Checking start of transmission UARTO transmit interrupt control register Address 7116 UART1 transmit interrupt control register Address 7316 UARTi transmit interrupt b7 bO i 175 Interrupt request bit 0 No interrupt requested 1 Interrupt requested V Transmission has P fo UN Note This figure shows the bits and registers required for processing UARTO transmit receive control register 0 Address 3416 Hefer to Figures 11 4 6 to 11 4 8 for the UART1 transmit receive control register 0 Address 3C16 change of flag state and the occurrence timing b7 b0 of an interrupt request imum 175 Transmit register empty flag 0 During transmission
430. r Bj overflow flag in the interrupt routine When a value is written to the timer Bj mode register with the count start bit 1 the timer Bj overflow flag is cleared to 0 at the next count timing of the count source The timer Bj overflow flag is a read only bit Use the timer Bi interrupt request bit to detect the overflow timing Do not use the timer Bi overflow flag for this detection Figure 9 5 3 shows the operation during pulse period measurement Figure 9 5 4 shows the operation during pulse width measurement 7721 Group User s Manual 9 23 TIMER B 9 5 Pulse period Pulse width measurement mode Count source MHL UP Measurement pulse Transferred Transferred Reload register lt Counter undefined value measured value Transfer timing _ fL C C j 5 D Timing at which counter is 7 cleared to 000016 Count start bit Timer Bj interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software Timer Bj overflow flag Counter is initialized by completion of measurement Counter overflow Note The above applies when measurement is performed for an interval from one falling edge to the next falling edge of the measurement pulse Fig 9 5 3 Operation during pulse period measurement Count source Measurement pulse Transferred measured Transferred UT measured measured i value i value Reload register lt Count
431. r counter register 3 1FFA16 1FFB16 w 1FFC16 DMA3 mode register L 0 0 0 05 930 0 0 1FFD16 DMA3 mode register H 0 0 0 0 ESO o o 1FFE16 DMAS control register ojojojojojo 1FFF16 internal RAM area addresses 8016 to 27F 16 eAt hardware reset Except the case where Stop or Wait mode is terminated Undefined At software reset Retains the state immediately before reset At termination of Stop or Wait mode Hardware reset is used to terminate it Retains the state immediately before the STP or WIT instruction is executed For the M37721S2BFP the internal RAM area can be assigned to addresses 8016 to 47F16 by setting the internal RAM area select bit bit 1 at address 5F16 Refer to section 2 4 Memory assignment Fig 4 1 9 State of SFR and internal RAM areas immediately after reset 6 4 10 7721 Group User s Manual RESET 4 1 Hardware reset 4 1 3 Internal processing sequence after reset Figure 4 1 10 shows the internal processing sequence after reset External bus width 16 bits BYTE L 9 cpu Ao A7 P4 00 6 FEt6 X ADL x As Ds Ais D15 pu Seg 0016 x FF46 P pU AD alix zum Next op sade or s Ko Aie Do A23 D7 X 00 g
432. r mode are selected Note DMAACKi validity bit 7 6 Nothing is assigned Undefined b3b2b1b0 0000 Do not select 0001 External source DMAREQI 0010 Software DMA source 0011 Timer AO Timer A1 Timer A2 Timer A3 Timer A4 Timer BO Timer B1 Timer B2 UARTO receive UARTO transmit i UART1 receive UART1 transmit A D conversion O00 00 00 O 0 0 0 0 0 0 Edge sense Falling edge 1 Level sense L level 0 Invalid The pin functions as a programmable l O port 1 Valid The pin functions as DMAACKi Note When a certain source other than an external source is selected by bits 0 to 3 or when the cycle steal transfer mode is selected set bit 4 to 0 Level sense can be selected only when both of the external source and the burst transfer mode are selected 7721 Group User s Manual 17 39 APPENDIX Appendix 4 Package outline Appendix 4 Package outline 100P6S A Plastic 1 OOpin 14x 20mm body QFP EIAJ Package Code JEDEC Code Weight g Lead Material QFP100 P 1420 0 65 158 Aloy42 Scale 2 1 Symbol Dimension in Millimeters Min Nom Max A 30 TA 0o 01 02 0 ms 0 200 202 0 65 _ 08 L ts l 146 2 0 0 14 0 35 ME 17 40 7721 Group User s Manual APPENDIX Appendix 5 Examples of handling unused pins Appendix 5 Examples
433. r s Manual 10 9 REAL TIME OUTPUT 10 4 Real time output operation 10 4 Real time output operation When the timer Ai i 0 1 count start bit is set to 1 the counter starts counting of the count source The contents of pulse output data register are output from the pulse output pins at every underflow of Timer Ai The timer is reloaded with the contents of the reload register and continues counting The timer Ai interrupt request bit is set to 1 when the counter underflows in The interrupt request bit retains 1 until the interrupt request is accepted or it is cleared by software Write the next output data into the pulse output data register i during the timer Ai interrupt routine or after the recognition of the timer Ai interrupt request occurrence Figure 10 4 1 shows an example of real time output operation Starts counting Starts pulse outputting Hex 000316 Counter contents 000016 1 1 1 1 r ok ow Undefined 00112 01102 11002 10012 00112 MOM d QA C IER mJ RTPO0s output Undefined 2 RTP02 output Undefined 2 RTP01 output Undefined 2 RTPOo output Undefined 2 l x3 3 3 3 3 Timer AO interrupt request bit 1 Written by software 2 To avoid undefined output for these terms follow the procedure Processing of avoiding undefined output before starting pulse output in Figures 10 3 1 and 10 3 2 3 Cle
434. r s Manual 11 13 SERIAL I O 11 2 Block description 11 2 7 UARTi transmit interrupt control and UARTi receive interrupt control registers When using UARTi 2 types of interrupts which are UARTi transmit and UARTI receive interrupts can be used Each interrupt has its corresponding interrupt control register Figure 11 2 12 shows the structure of UARTi transmit interrupt control and UARTI receive interrupt control registers For details about interrupts refer to CHAPTER 7 INTERRUPTS b7 b6 b5 b4 b3 b2 bi UARTO transmit interrupt control register Address 7116 UARTO receive interrupt control register Address 7216 UART1 transmit interrupt control register Address 73 6 UARTI receive interrupt control register Address 7416 Interrupt priority level select bits j Level 0 Interrupt disabled 0 1 Level 1 Low level Level 2 Level 3 Level 4 Level 5 RW Level 6 Level 7 High level 3 Interrupt request bit 0 No interrupt requested RW 1 Interrupt requested Nothing is assigned Undefined Fig 11 2 12 Structure of UARTi transmit interrupt control and UARTi receive interrupt control registers 1 Interrupt priority level select bits bits 0 to 2 These bits select a priority level of the UARTi transmit interrupt or UARTi receive interrupt When using UARTi transmit receive interrupts select one of the priority levels 1 to 7 When a UARTI transmit receive interrupt request occurs its priority level
435. r status register s high order byte PSH S 2 Program counter s low order byte PCL 9 1 Program counter s high order byte PCH S Program bank register PG X S isan initial address that the stack pointer S indicates when an interrupt request is accepted The S s contents become S 5 after all of the above registers are pushed Fig 7 1 2 State of stack area just before entering interrupt routine 7721 Group User s Manual 3 INTERRUPTS 7 2 Interrupt sources 7 2 Interrupt sources Table 7 2 1 lists the interrupt sources and the interrupt vector addresses When programming set the start address of each interrupt routine at the vector addresses listed in this table Table 7 2 1 Interrupt sources and interrupt vector addresses Interrupt source Interrupt vector addresses vector Interrupt vector addresses Remarks Reference High order Low order address address Ress FFFF FFFE amp Nonmaskabe 4 RESET Ze dU 7700 Family Software BRK instruction Manual DBC Note Watchdog timer 15 WATCHDOG TIMER INTo Maskable external interrupts 7 10 External interrupts INT FFF2 e INTi interrupt INT Timer A1 Timer A2 Timer A3 FFE9 6 FFEB8 6 Timer A4 FFE7 6 FFEO6 16e Timer BO Timer B UARTO receive UARTO transmit UART1 transmit A D conversion 12 A D CONVERTER DMAO Maskable internal interrupts 13 DMA CONTROLLER DMA2 FFD1 6e FFDOte DMA3 FFCFie FFCE te Note The DBC in
436. r to section 13 4 Operation Transfer completion of 1 block Burst Edge Burst Level L Cycle steal Requested DMAi request bit TC L output Note DMAi interrupt request bit 1 DMAi enable bit 0 Burst Level H Cycle Steal No request Note When TC pin validity bit is 1 DMAi request bit 0 Only burst edge Burst Edge In burst transfer mode edge sense Burst Level L In burst transfer mode level sense with DMAREQ i pin s input level L Burst Level H In burst transfer mode level sense with DMAREQi pin s input level H Cycle steal Requested In cycle steal transfer mode with any request of DMAO 3 Cycle steal No request In cycle steal transfer mode with no request of DMA0 3 Fig 13 5 5 Operation flowchart of single transfer mode 7721 Group User s Manual 13 59 DMA CONTROLLER 13 5 Single transfer mode pajdeooe si pue si jeubis Builiduies sanba snq eui SIUM poejduues SI pjoH 10 usaJja1 INVuG Aq pesneo sanba sng aul e Ndo amp OYNA amp d snq esn ol y i4 Gtiep Gties 9 en EA 9S HD u9A9 IH VQ 0119S S YOIUM en eA 9u Jep u A IHVS 01 18S SI YOIUM NJLA U Jes ON yem uoneunsap 19JSUeJ ON HEM 92Jnos JeJSUeJ pJeMJ04 uomnoailp ssoeJppe uormeursep J9JSueJ pJeM0J uonoaJip ssoaJppe 92Jnos 19JSUPJ sung opouu JoJSUeJ J9JsueJ e oKo snq z POUJOW J9JSueaJ rep m sq 9 U HUN J9jSueJ s q 9 U1pIM Snq ejep
437. r to section 2 3 Access space The program bank register is an 8 bit register This register indicates the high order 8 bits bank of the address 24 bits at which an instruction to be executed next in other words an instruction to be read out from an instruction queue buffer next is stored These 8 bits are called bank When a carry occurs after adding the contents of the program counter or adding the offset value to the contents of the program counter in the branch instruction and others the contents of the program bank register is automatically incremented by 1 When a borrow occurs after subtracting the contents of the program counter the contents of the program bank register is automatically decremented by 1 Accordingly there is no need to consider bank boundaries in programming usually This register is cleared to 0016 at reset 2 1 7 Data bank register DT The data bank register is an 8 bit register In the following addressing modes using the data bank register the contents of this register is used as the high order 8 bits bank of a 24 bit address to be accessed Use the LDT instruction to set a value to this register This register is cleared to 0016 at reset e Addressing modes using data bank register eDirect indirect eDirect indexed X indirect eDirect indirect indexed Y Absolute Absolute bit Absolute indexed X Absolute indexed Y Absolute bit relative Stack pointer relative indirect indexed Y
438. ral devices input output timing depending on f Xin Vcc 5 V x 10 9o Vss 0 V Ta 20 to 85 C Timer A input Gating input in timer mode Symbol Calculation formula Unit tera 8 5 M ns lw TAH 4 X 10 ns tw TAL 4 X 10 ns f XiN Timer A input External trigger input in one shot pulse mode Symbol Calculation formula Unit c TA 4 X 10 ns f XiN Timer B input Pulse period measurement mode Symbol Calculation formula Unit tere 8 X 10 ns f XiN tw TBH 4 X 10 ns f XiN tw TBL 4 X 10 ns f XiN Timer B input Pulse width measurement mode Symbol Calculation formula Unit tere 8 X 10 ns f XiN lw TBH 4 X 10 ns f XiN tw TBL 4 x 109 ns f XiN 7721 Group User s Manual 17 103 APPENDIX Appendix 11 Electrical characteristics Table 4 Calculation formulas for bus timing depending on f Xw lpzx E DLZ lpzx E DHZ th E BLE th E BHE th E R W w EL su A DL Wait bit 1 lsu A DH Wait bit 0 Wait bit 1 Wait bit 0 tsu ALE DL tsu ALE DH 17 104 Vcc 5 Vt 10 Vss 0 V Ta 20 to 85 C Iculation formula Unit 1 X 10 Wait bit 1 Wait bit 0 PO NN f 9 i E 35 ns 9 eer c ee 9 oy T20 ns 9 ET 22 ns 1 X 10 Xn s 9 T 20 ns 9 pond ms 9 9 s 9 N 70 ns 9 s 9 9
439. ral devices timing requirements Vcc 5 V 10 96 Vss 0 V Ta 20 to 85 C f Xin 25 MHz unless otherwise noted Note The limits depend on f Xin Table 3 lists calculation formulas for the limits Timer A input Count input in event counter mode Symbol Uni teta TAjw input cycle time 8 amp l ns tw TAH TAjin input high level pulse width 40 ns tw TAL TAjin input low level pulse width 40 ns Timer A input Gating input in timer mode Unit Symbol Parameter nl terra TAjin input cycle time Note 320 ns tw TAH TAjw input high level pulse width Note 469 ns tw TAL TAjin input low level pulse width Note 160 ns Timer A input External trigger input in one shot pulse mode Symbol in Lgs Ur to TA TAjin input cycle time Note oe ns tw TAH TAjin input high level pulse width g80 ns tw TAL TAjin input low level pulse width 80 ns Timer A input External trigger input in pulse width modulation mode Symbol Parameter Max Unit tw TAH TAjw input high level pulse width 80 ns tw TAL TAjin input low level pulse width gol ns Timer A input Up down input in event counter mode tum TAjvrinputcycletime O O 2000 ns beue TAjovr input high level pulse width 1000 ns twue TAjowr input low level pulse width 1000 ns kuupa TAjour input setup time T 400 ns tmwue TAjow input hold
440. ransfer mode Last transfer of each block At the last term except for the last block for processing of each block in the repeat array chain and link array chain transfer modes 1 unit transfer is performed with one DMAi request and the right to use bus is relinquished after 3 cycles of 9 PLU UU UU UU Uu Ao A7 sal m 2 L X dat BUR sa14 m PCL As De Ais Dis Kao gt m 7 A16 Do Azs D7 CPS oma aa ama C aa Bus request sampling DMAACKi H I I TC ST1 STO 1 0 DMAC 1 1 CPU 1 unit transfer p 4 jp Transition of right Transition of right to use bus to use bus The above figure is the example of the last term for processing the first block in Figure 13 8 9 The Bus request caused by DRAM refresh Hold or DMA is sampled while the bus request sampling signal is H and is accepted Fig 13 8 13 Timing diagram of cycle steal transfer mode 4 7721 Group User s Manual 13 95 DMA CONTROLLER 13 8 Link array chain transfer mode Last transfer of last block At the last term for processing the last block in the single array chain and link array chain transfer modes 1 unit transfer and terminate processing are subsequently performed with one DMAi request 1 ALE Ao A7 sa2 n 2 2 L da2 n 2 t 2 L As Ds A1s D15 ese esee Ey A16 Do A23 D7 COENE Pes Bus request sampling DMAACKi H i i TC ST1 ST
441. ray chain transfer mode and Link array chain transfer mode Transition of the right to use bus from CPU to DMAC 1 cycle Array state The number of transfer parameters x the number of reads of a transfer parameterx the number of bus cycles for a read 1 cycle Refer to Table 13 9 1 DMA transfer per an entire batch of data e In 2 bus cycle transfer Read cycle Write cycle x the number of transfers 1 Add a value which satisfies the read write conditions Refer to Table 13 4 1 3 2 When the transfer unit is 16 bits the number of transfers the number of transfer bytes 2 When the transfer unit is 8 bits the number of transfers the number of transfer bytes e In 1 bus cycle transfer Refer to Table 13 4 5 Last processing of each block 3 cycles Terminate processing 3 cycles Transition of the right to use bus from DMAC to CPU 1 cycle Example Array chain transfer mode exiernal data bus width 16 bits 2 bus cycle transfer transfer unit 16 bits the number of transfer blocks 3 and under the following conditions Transfer source address direction forward without Wait Transfer destination address direction backward without Wait First block transfer source s data start address even transfer destination s data start address even the number of transfer bytes 10 bytes e Second block transfer source s data start address even transfer destination s data start address odd the num
442. read from SARI DARi and TCRi are used Fig 13 4 2 Basic operation of registers for 1 unit transfer in 2 bus cycle transfer 7721 Group User s Manual 13 31 DMA CONTROLLER 13 4 Operation 2 Bus operation in 2 bus cycle transfer The time required for 1 unit transfer in 2 bus cycle transfer is given by the following formula Transfer time per 1 unit transfer Read cycle Write cycle Since any area can be specified as a transfer source or a transfer destination a read cycle varies with the conditions of a transfer source and a write cycle with that of a transfer destination Table 13 4 1 lists the time required for a read or write cycle per 1 unit transfer in 2 bus cycle transfer and Figure 13 4 3 shows the bus cycle operation waveforms in 2 bus cycle transfer Table 13 4 1 Time required for a read or write cycle per 1 unit transfer in 2 bus cycle transfer External Transfer Address directions Data s start Read Write cycle Unit cycle 16 bits 16 bits Fixed Forward Even 3 d including Odd 6 f bus Odd 2 i 3 4 e 4 e Note Backward 8 bits 16 bits Fixed Forward Even Odd 2 2i 4 c 6 f 8 bits ee DIM NONI SO 3 d Backward Address directions Refer to section 13 4 1 3 Address directions in 2 bus cycle transfer i A term of E L in 1 bus cycle i 1 at No Wait and i 2 at With Wait or DRAM area When Ready function is used Refer to section 3 3 Ready funct
443. refer to section 11 4 6 Receive operation When using interrupts it is necessary to set the relevant registers to enable interrupts For details refer to CHAPTER 7 INTERRUPTS Figure 11 4 4 shows writing data after start of transmission and Figure 11 4 5 shows detection of transmit completion 11 34 7721 Group User s Manual SERIAL I O 11 4 Clock asynchronous serial I O UART mode UARTO transmit receive mode register Address 3016 b a ETEEN UART1 transmit receive mode register Address 3816 7 d UARTO baud rate register BRGO Address 3116 E fo fof fat 4 UART1 baud rate register BRG1 Address 3916 Ki b2 b1 b0 1 0 1 UART mode 8 bits 1 1 0 UART mode 9 bits E Y d C Can be set to 0016 to FF16 Internal External clock select bit 0 Internal clock 1 External clock Stop bit length select bit 0 1 stop bit 1 2 stop bits UARTO transmit interrupt control register Address 7116 UART1 transmit interrupt control register Address 7316 b7 bO LH Interrupt priority level select bits Odd Even parity select bit 0 Odd parity 1 Even parity When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 Parity enable bit 0 Parity disabled 1 Parity enabled Sleep select bit 0 Sleep mode terminated Invalid 1 Sleep mode selected J M UARTO transmit buffer r
444. register address 1416 Internal External clock select bit bit 3 at addresses 30 e 38 16 CTS RTS select bit bit 2 at addresses 3416 3C e Notes 1 The TxDi pin outputs H level while transmission is not performed after selecting UARTi s operating mode 2 The CTS RTSi pin can be used as an input port when performing only reception and not using the RTS function when selecting CTS function 7721 Group User s Manual 11 31 SERIAL I O 11 4 Clock asynchronous serial I O UART mode 11 4 1 Transfer rate Frequency of transfer clock The transfer rate is determined by the BRGi addresses 3116 3916 When setting n into BRGi BRGi divides the count source frequency by n 1 The BRGi s output is further divided b 16 and the resultant clock becomes the transfer clock Accordingly n is expressed by the following formula F n Value set in BRGi 00 e to FFie ie lt p F BRGi s count source frequency Hz B Transfer rate bps An internal clock or an external clock can be selected as the BRGi s count source with the internal external clock select bit bit 3 at addresses 3016 3816 When an internal clock is selected the clock selected with the BRG count source select bits bits 0 and 1 at addresses 3416 3C e becomes the BRGi s count source When an external clock is selected the clock input to the CLKi pin becomes the BRGi s count source Set the same transfer rate for both transmitter and receiver si
445. rem TBjw input high level pulse width both edges count nl o X n treo TBjw input low level pulse width both edges count UI U 8oj ns Timer B input Pulse period measurement mode S Unit ymbol Parameter toe TBjwinput cycle time Nte 32o ms Timer B input Pulse width measurement mode T Symbol Parameter ni tc TB TBjw input cycle time Note 320 J ns tw TBH TBji input high level pulse width Note 160 ns tw TBL TBjin input low level pulse width Note 160 ns A D trigger input Symbol Parameter Max Unit lc AD ADrnes input cycle time trigger enabled minimum 1000 ns tw ADL ADrtre input low level pulse width 125 ns Serial I O ymbol Parameter tco _ CLKiinput cycle time y y y 200 ms twee CLKi input high level pulse width O 100 ns lace CLKi input low level pulse width woof ns buo RxDi input setup time y y 20 X ns ic o jRxDiinputhold time i 9 ns External interrupt INTi input Unit Symbol Parameter ni tw INH INTi input high level pulse width 25 ns 250 tw INL INTi input low level pulse width 250 ns 7721 Group User s Manual 17 85 APPENDIX Appendix 11 Electrical characteristics Internal peripheral devices TBjiN input tc AD ADrna i
446. requency of count source fz fis fe4 or f512 Note Use the LDM or STA instruction for writing to this register Read from or write to this register in a unit of 16 bits lt When operating as an 8 bit pulse width modulator gt b15 b8 b7 bO b7 bO Timer A3 register Addresses 4D16 4C16 Timer A4 register Addresses 4F16 4E16 7 to 0 These bits can be set to 0016 to FF e Undefined WO Assuming that the set value m PWM pulse s period output from the TAjour pin is expressed as follows m 1 2 1 fi 15 to 8 These bits can be set to 0016 to FE e Undefined WO Assuming that the set value n the H level width of the PWM pulse output from the TAjour pin is expressed as follows n m 1 fi fi Frequency of count source f2 fis fe4 or f512 Note Use the LDM or STA instruction for writing to this register Read from or write to this register in a unit of 16 bits Fig 8 6 1 Structures of timer Aj mode registers and timer Aj registers in PWM mode 7721 Group User s Manual 8 39 TIMER A 8 6 Pulse width modulation PWM m ode 8 6 1 Setting for PWM mode Figures 8 6 2 and 8 6 3 show an initial setting example for registers relevant to the PWM mode Note that when using interrupts set up to enable the interrupts For details refer to INTERRUPTS CHAPTER 7 f es Selecting PWM mode and each function b Trigger select bits b4 b3 01
447. request occurs when reception is completed UARTI receive interrupt 7 Heading of receive data UARTO receive buffer register Addresses 3716 3616 UART1 receive buffer register Addresses 3F16 3E16 b15 b8 b7 bO iN J V Read out receive C Checking error UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 b7 bO o9 ESOS Overrun error flag 0 No overrun error L C 1 Overrun error apa C Processing after reading out receive data Fig 11 4 10 Processing after receive completion Note This figure shows the bits and registers required for processing Refer to Figure 11 4 12 for the change of flag state and the occurrence timing of an interrupt request 7721 Group User s Manual 11 43 SERIAL I O 11 4 Clock asynchronous serial I O UART mode 11 4 6 Receive operation When the receive enable bit is set to 1 the UARTI enters the receive enable state After this reception starts when ST is detected and a transfer clock is generated In the case of selecting the RTS function when the reception is enabled the RTS pin s output level becomes L to inform the transmitter side that reception is enabled When reception is started the RTSi pin s output level becomes H Accordingly by connecting the RTSi pin to the CTSi pin of the transmitter side the timing of transmission and
448. resh timer Fig 14 4 2 Refresh delay time example when CPU is operating Refresh request i Bus request DRAMC i Bus request sampling ST1 STO 10 DMAC 00 Refresh f M Sw gt Delay time Max 12 5 cycles of Refresh cycle Transition of right to use bus The following are internal signals Refresh request Bus request DRAMC Bus request sampling Refresh request becomes 0 at an underflow of the refresh timer Fig 14 4 3 Refresh delay time example during DMA transfer 7721 Group User s Manual 14 11 DRAM CONTROLLER 14 5 Precautions for DRAMC 14 5 Precautions for DRAMC 1 Set the refresh timer address 6616 to any of 01 FF46 2 When a DRAM refresh request occurs during Hold state a refresh cycle is activated regardless of the bus state It is because a bus request is always sampled during Hold state Therefore in order to use the DRAMC together with the Hold function an external circuit which is controlled depending on the states of STO and ST1 is required 3 DRAM refresh is not performed in Stop or Wait mode 14 12 7721 Group User s Manual CHAPTER 19 WATCHDOG TIMER 15 1 Block description 15 2 Operation description 15 3 Precautions for Watchdog timer WATCHDOG TIMER 15 1 Block description Watchdog functions as follows Detects a program runaway Measures a certain time from when oscillation starts owing to term
449. resses 1FC616 to 1FC416 Addresses 1FD61e to 1FD416 Addresses 1FE616 to 1FE446 Addresses 1FF616e to 1FF416 lt 23 to 0 Write mM Undefined RW Set the transfer start address of the destination These bits can be set to 00000016 to FFFFFF e Read The read value indicates the destination address of data which is next transferred Note When writing to this register write to all 24 bits Transfer counter register 0 Addresses 1FCAte to 1F C816 Transfer counter register 1 Addresses 1FDA te to 1FD8 6 Transfer counter register 2 Addresses 1FEAte to 1FE816 Transfer counter register 3 Addresses 1FFA e to 1FF816 23 to 0 Write Undefined RW Set the byte number of the transfer data These bits can be set to 00000116 to FFFFFF e Read The read value indicates the remaining byte number of the block which is being transferred Note When writing to this register write to all 24 bits Do not write 00000016 to this register 7721 Group User s Manual 17 35 APPENDIX Appendix 3 Control registers Array chain transfer mode b23 b16 b15 b8 b7 bO Source address register 0 Source address register 1 Source address register 2 Source address register 3 Write Undefined RW Set the start address of transfer parameter memory These bits can be set to 00000016 to FFFFFF46 Read eAfter a value is written to this register and until transfer starts the read va
450. resses 1FFA e to 1FF8 6 Addresses 1FC616 to 1F C416 Addresses 1FD616 to 1FD4 6 Addresses 1FE616 to 1FE41e Addresses 1FF6 e to 1FF416 data which is next transferred Note When writing to this register write to all 24 bits Transfer counter register O Transfer counter register 1 Transfer counter register 2 Transfer counter register 3 23 to O Write Set the byte number of the transfer data These bits can be set to 00000116 to FFFFFF 16 Read The read value indicates remaining byte number of the transfer data Lnd S iu S z wWqillss Undefined Note When writing to this register write to all 24 bits Do not set this register to 00000016 17 34 7721 Group User s Manual APPENDIX Appendix 3 Control registers Repeat transfer mode Source address register 0 Addresses 1FC216 to 1FC016 Source address register 1 Addresses 1FD216 to 1FD016 Source address register 2 Addresses 1FE216 to 1FE016 Source address register 3 Addresses 1FF216 to 1FF016 23 to 0 Write Undefined RW Set the transfer start address of the source These bits can be set to 00000016 to FFFFFFt 6 Read The read value indicates the source address of data which is next transferred Note When writing to this register write to all 24 bits Destination address register O Destination address register 1 Destination address register 2 Destination address register 3 Add
451. resses 1FFAte to 1FF816 Set the byte number of transfer data These bits can be set to 00000116 to FFFFFF e TCRO TCR1 TCR2 TCR3 Notes 1 When writing to these registers write to all 24 bits 2 Do not write 00000016 to TCRi Note 3 When data is transferred from memory to I O in 1 bus cycle transfer it is unnecessary to set DARI When data is transferred form I O to memory in 1 bus cycle transfer it is unnecessary to set SARi QPP PEPPER Fig 13 5 3 Initial setting example for registers relevant to single transfer mode 2 7721 Group User s Manual 13 57 DMA CONTROLLER 13 5 Single transfer mode From preceding Figure 13 5 3 0 l l Salecion of priority level and TC pin b7 bO o ooo DMAC control register L Address 6816 Priority select bit 0 Fixed 1 Rotating TC pin validity bit P10s pin functions as a programmable I O port 1 Valid mE P105 pin functions as TC pin DMAO request bit DMA1 request bit DMA request bit DMAS request bit N and setting DMAi request bit to 0 nvalid 0 No request b7 b0 Ses DMAC control register H Address 6916 Software DMAi request bit Valid in software DMA source selected Bit 0 Channel 0 Bit 1 Channel 1 Bit 2 Channel 2 Bit 3 Channel 3 DMAO enable bit DMA1 enable bit DMA2 enable bit
452. reviously generated trigger and a new trigger The one shot pulse output from the TAjour pin can be disabled by clearing the timer Aj mode register s bit 2 to 0 Accordingly Timer Aj can be also used as an internal one shot timer that does not perform the pulse output In this case the TAjour pin functions as a programmable I O port 7721 Group User s Manual 8 35 TIMER A 8 5 One shot pulse mode FFFF46 n Reload register s contents Stops 4 Starts counting counting Starts counting Stops counting 4 Counter contents Hex 000116 Time Set to 1 by software Count start bit Trigger during counting TAji pin input signal 1 fi X n 1 fi X n 1 One shot pulse output from TAjout pin Timer Aj interrupt request bit fi Frequency of count source f2 His fe4 Or f512 Cleared to 0 when interrupt request is accepted or cleared by software When the count start bit 0 counting stopped the TAjour pin outputs L level When a trigger is generated during counting the counter counts the count source n 1 times after a new trigger is generated Note The above applies when an external trigger rising of TAji pin s input signal is selected Fig 8 5 5 Example of operation in one shot pulse mode selecting external trigger 8 36 7721 Group User s Manual TIMER A 8 5 One shot pulse mode Precautions for one shot pu
453. roximation register Table 12 3 1 lists the relationship between the successive approximation register s contents and Vre Table 12 3 2 lists changes of the successive approximation register and Vre during the A D conversion Figure 12 3 1 shows the ideal A D conversion characteristics Table 12 3 1 Relationship between successive approximation register s contents and Veet Successive approximation register s contents n Vret V 0 0 Vner 1 2 X n 0 5 to 255 Em Vner Reference voltage 12 10 7721 Group User s Manual A D CONVERTER 12 3 A D conversion method Table 12 3 2 Change in successive approximation register and Vre during A D conversion ice Successive approximation register Change of Vref b7 A D converter halt l1folololololo 1st comparison 1 0 0 0 0 0 0 n7 1 us 2nd comparison Inz 1 0 0 0 0 0 V n7 0 1st comparison resul M 3rd comparison n7 ne 1 0 0 0 0 0 Mii V en e 1 512 v 2nd comparison result 8th aros ni 1 REF 4 i VREF VREF V Conversion complete n7 ne ns na na na n1 A D conversion result Ideal A D conversion characteristics VREF VREF VREF o56 X253 gt 56 X254 7256 x255 VREF Analog input voltage Fig 12 3 1 Ideal A D conversion characteristics 7721 Group User s Manual 12 11 A D CONVERTER 12 4 Absolute accuracy and differential non linearit
454. rs at the second and the following 1 unit transfers Latch Transfer source destination address is specified Contents are updated by incrementer decrementer and decrementer Previously written values Addresses which were to be transferred subsequently or the number of remaining bytes Updated contents are written c When reading values at addresses of SARI DARI and TCRi after forced termination and rewriting them Latch Previously written values Hegister Addresses which were to be transferred subsequently or the number of remaining bytes Written by software Addresses which were to be transferred subsequently or the number of remaining bytes Read by software Fig 13 3 4 States of SARi DARi TCRi after forced termination 7721 Group User s Manual 13 29 DMA CONTROLLER 13 4 Operation 13 4 Operation Operation of 1 unit transfer varies according to the data transfer method 2 bus cycle or 1 bus cycle transfer In addition how many units of transfer data are transferred for a DMA request varies according to the transfer mode burst transfer or cycle steal transfer mode These data transfer methods and modes are described below 13 4 1 2 bus cycle transfer When the transfer method select bit Refer to Figure 13 2 6 0 2 bus cycle transfer is selected 2 bus cycle transfer is the method used to transfer data between memories Since this method has a r
455. rs relevant to the repeat mode 7721 Group User s Manual 12 17 A D CONVERTER 12 6 Repeat mode a N A D control register b7 bO fot loli I A D control register address 1Et16 LT Analog input select bits b2 b1 bO ANo selected AN selected AN2 selected ANs selected AN4 selected AN5 selected ANe selected AN7 selected O O oO o OO O O O O O O Repeat mode Trigger select bit 0 Internal trigger 1 External triggeer A D conversion start bit 0 Stop A D conversion A D conversion frequency AD select bit 0 fe divided by 4 1 fe divided by 2 Pon P7 direction register b7 b0 Port P7 direction register address 1116 ANo AN AN2 Set the bits corresponding AN3 to analog input pins to 0 AN4 Set bit 7 to 0 when ANs selecting external trigger ANe V AN7 J N fg A D conversion start bit to 1 b7 b0 i j d A D control register address 1E 6 A D conversion start bit d When external trigger is selected Input falling edge to ADrnc pin When internal trigger is selected A Trigger occur Operation start Note Writing to each bit except bit 6 of the A D control register must be performed while the A D converter halts before a trigger occurs Fig 12 6 1 Initial setting ex
456. ry P3 4 NE 1 cycle of 9 HOLD E EE E d This is at Hold state so that sampling is i 1 i i i 1 i performed every 1 cycle of 0 jooi 1 i I E Sampling is performed after completion of BUS REQUEST Hold 1 bus cycle D 1 1 1 4 L 4 i 4A 4 i Bus request sampling i ST1 STO 1 1 0 1 1 1 1 1 0 1 1 1 TEN Hua NEG 4 S 1 ola state I Bus used by f Hold state gt Transition of right Transition of right CPU Transition of right Transition of right to use bus to use bus to use bus to use bus B DMA transfer 0 _ H o ib w This is the term in which the bus is not E TE i a i i used so that sampling is performed every AE i i i 1 cycle of 0 DMAREQi 1 Wa Sampling is performed after completion of TN a 1 unit transfer i i l i Sampling is performed after completion of DMAi request bit mE Eo i i 1 bus cycle BUS REQUEST DMAC SC S oo ZEE D Q Bus request sampling i ST1 STO 1 1 1 0 1 1 1 1 1 0 1 1 DMA transfer Bus used i OMA transfer i i Transition of right Transition of right by CPU Transition of right Transition of right to use bus to use bus to use bus to use bus The above applies on the following conditions Cycle steal transfer mode DMA request source external request DMAREQi 1 bus cycle transfer No Wait E CPU
457. s 1416 V RxD1 pin E N UARTO receive interrupt control register Address 7216 UART1 receive interrupt control register Address 7416 b7 b0 er usa priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 UARTO transmit buffer register Address 3216 UART1 transmit buffer register Address 3A16 b7 b0 Set dummy data here UARTO transmit receive control register 1 Address 3516 N UART1 transmit receive control register 1 Address 3D16 b7 bO et TL ft Transmit enable bit 1 Transmission enabled Receive enable bit 1 Reception enabled Note Set the receive enable bit and the transmit enable bit to 1 simultaneously Reception starts Fig 11 3 8 Initial setting example for relevant registers when receiving 2 7721 Group User s Manual 11 25 SERIAL I O 11 3 Clock synchronous serial I O mode When not using interrupts When using interrupts A UARTi receive interrupt request occurs when reception is completed Checking completion of reception UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 b7 bO Pt ET YT tty tt Receive complete flag 0 Reception not completed 1 Reception completed J UARTI receive interrupt Heading of receive data
458. s a width of 8 bits and 1 bus cycle transfer is selected set bit O to 1 DMAi mode register H DMAO mode register H Address 1FCD16 b7 b6 b5 b4 b3 b2 bi bO LE olo oua2 mode register n fee iFEDi DMAS mode register H Address 1FFD e Transfer direction select bit 0 From memory to I O RW Used in 1 bus cycle transfer Note 1 1 From I O to memory 1 I O connection select bit Refer to Fig 13 2 7 RW Valid in 1 bus cycle transfer Fi these ts to 0 o mw o Rw Transfer source wait bit Note 2 0 Wait o RW 1 No Wait Ls m LS Continuous transfer mode select b7b6 EAL bits 0 0 Single transfer 0 1 Repeat transfer fi 1 0 Array chain transfer RW 1 1 Link array chain transfer Notes 1 Set bit 0 to 0 in 2 bus cycle transfer 2 Bits 4 and 5 are valid to the external and internal areas However DRAM area is always handled with Wait regardless of the contents of these bits The wait bit bit 2 at address 5E e is invalid in DMA transfer 17 38 7721 Group User s Manual APPENDIX Appendix 3 Control registers DMAi control register b7 b6 b5 b4 b3 b2 bl bO Address 1FCE16 Address 1FDE16 Address 1FEE16 Address 1FFE16 DMAO control register DMA1 control register DMA2 control register DMAS control register yF Bi DMA request source select bits Edge sense Level sense select bit Used when external source and burst transfe
459. s register b15 bO Data bujier Fig 2 2 2 Register structure of bus interface unit BIU Table 2 2 1 Functions of each register Name Functions Program address register Indicates the storage address for the instruction which is next taken into the instruction queue buffer Instruction queue buffer Temporarily stores the instruction which has been taken in Data address register Indicates the address for the data which is next read from or written to Data buffer Temporarily stores the data which is read from the memory l O device by the BIU or which is written to the memoryel O device by the CPU 7721 Group User s Manual 2 11 CENTRAL PROCESSING UNIT CPU 2 2 Bus interface unit The CPU and the bus send or receive data via BIU because each operates based on different clocks Note The BIU allows the CPU to operate at high speed without waiting for access to the memory I O devices that require a long access time The BIU s functions are described bellow Note The CPU operates based on cPU The period of CPU is normally the same as that of 0 The internal 1 2 3 4 bus operates based on the E signal The period of the E signal is twice that of at a minimum Reading out instruction Instruction prefetch When the CPU does not require to read or write data that is when the bus is not in use the BIU reads instructions from the memory and stores them in the instruction queue buffer This is ca
460. s to which data is written to the BIU and write data The BIU writes the data to the specified address To perform the above operations to the BIU inputs and outputs the control signals and control the bus Figure 2 2 1 shows the bus and bus interface unit BIU 7721 Group User s Manual 2 9 CENTRAL PROCESSING UNIT CPU 2 2 Bus interface unit Sng euJo xe y Jo sjeuDis jou09 1noqe S39IA3G 1VNH31X3 HLIM NOLLO3NNOO H31dVHO 01 J9J8H Z Jeujoue auo JO juepuedepuir aJe snq eujejxe pue Sng seal sng NdA SUL ZL SIJON Jaysibay uoun eroedg HJS T E s euDis oJ1u02 SIA D c In9JI9 Lq eev 0 0g 91y 1 uoisjeAuoo leue lt s Q sIV 0 8q 8V V O1 OY snq euJ91x3 H49 I SIA D eJeudued m euJeju p i nig dO jo0uJ9UJ ecV O OV SNQ euJo9 u euJ81u EN Lu cmd lun yun ECT 1q 0 oq sng jeujelul 99EJ9 ul DuisseoouUd sng e1 u 3 p sidq 0 8q snq eujeiu snq eu49 u SNQ Nd LoLZEW 7721 Group User s Manual Fig 2 2 1 Bus and bus interface unit BIU 2 10 CENTRAL PROCESSING UNIT CPU 2 2 Bus interface unit 2 2 2 Functions of bus interface unit BIU The bus interface unit BIU consists of four registers shown in Figure 2 2 2 Table 2 2 1 lists the functions of each register bO Program address register b7 bO l L Instruction queue buffer q b23 bO Data addres
461. same polarity and the same frequency as o Timing of signals to be input from or output to the external is ordained on the basis of clock 01 3 Bus request Hold and bus request sampling are internal signals Fig 3 4 2 Timing of acceptance of Hold request and termination of Hold state 2 3 14 7721 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 3 4 Hold function When inputting L level to HOLD pin while bus is used when data access is completed with continuous 2 bus cycle State when inputting L level to HOLD pin External data bus Data length Used Clock 1 Note 2 Floating R W External address bus Floating External data bus Address B External address bus N Floating BLE BHE HOLD Bus request Hold Note 3 Bus request sampling Note 3 lt am Hold state Bus in use lt q j lt q jp Bus in use Transfer of right Transfer of right to use bus to use bus When a Hold request is accepted not a new address but the address which was output immediately before is output again Notes 1 The above diagram shows the case of 2 0 access in low speed running 2 Clock 01 has the same polarity and the same frequency as 9 Timing of signals to be input from or output to the external is ordained on the basis of clock 1 3 Bus request Hold and bus request sampling are internal signals Fig 3
462. se of internal RAM area 512 bytes gt select bit T External area External aree Bank 016 Notes 1 Interrupt vector table is assigned to addresses FFCEt6e to FFFF 6 SFR area SFR area Make sure to set a ROM to this area 2 For the M37721S1BFP fix the internal RAM area select bit to 0 External area Note 1 Note 1 Fig 1 Memory assignment microprocessor mode 17 2 7721 Group User s Manual Appendix 2 Memory assignment in SFR area Access characteristics APPENDIX Appendix 2 Memory assignment in SFR area RW It is possible to read the bit state at reading The written value becomes valid RO It is possible to read the bit state at reading The written value becomes invalid WO The written value becomes valid It is impossible to read the bit state State immediately after reset 0 0 immediately after reset 1 1 immediately after reset Undefined immediately after reset Address Register name 016 116 216 316 416 016 616 716 816 916 A16 Port P4 register B16 Port P5 register C16 Port P4 direction register D16 Port P5 direction register E16 Port P6 register F16 Port P7 register 1016 Port P6 direction register 1116 Port P7 direction register 1216 Port P8 register 1316 Port P9 register 1416 Port P8 direction register 1516 Port P9 direction register 1616 Port P10 register 1716 1816 Port P10 direction register 1916
463. select bit Transfer method External data bus width I O connection Setting for I O connection select bit 16 bits Do D15 16 bit 1 0 X 1 or 8 bit I O X 2 Do D7 8 bit I O Ds D15 1 8 bit I O Fig 13 2 7 Structure of DMAi mode register H 7721 Group User s Manual 13 15 DMA CONTROLLER 13 2 Block description 13 2 12 DMAi control register Figure 13 2 8 shows the structure of the DMAi control register For bits 0 4 refer to section 13 3 2 1 DMA request sources 1 DMAACKi validity bit bit 5 When this bit is set to 1 the corresponding pin of port P9 serves as the DMAACKi pin and outputs L during a DMA transfer For details refer to each timing diagram of section 13 5 Single transfer mode through section 13 8 Link array chain transfer mode DMAO control register Address 1FCEt 6 DMA1 control register Address 1FDE1e DMA2 control register Address 1FEEt6 DMAS control register Address 1FFEt6 DMA request source select bits b3b2b1b0 RW Note 0000 Do not select External source DMAREQi Software DMA source Timer AO Timer A1 Timer A2 Timer A3 Timer A4 Timer BO Timer B1 Timer B2 UARTO receive UARTO transmit UART1 receive UART1 transmit A D conversion b7 b6 b5 b4 b3 b2 bi b0 Edge sense Level sense select 0 Edge sense Falling edge bit Used when external source 1 Level sense L level and burst transfer mode are
464. ser s Manual 9 15 TIMER B 9 4 Event counter mode 9 4 1 Setting for event counter mode Figure 9 4 2 shows an initial setting example for registers relevant to the event counter mode Note that when using interrupts set up to enable the interrupts For details refer to CHAPTER 7 INTERRUPTS Selecting event counter mode and count polarity B Timer Bj mode register j 0 1 Addresses 5Bte 5C16 b7 b0 XIXIX REDE Selection of event counter mode Count polarity select bits b3 b2 0 0 Counts at falling edge of external signal 0 1 Counts at rising edge of external signal 1 0 Counts at both of falling and rising edges of external signal 1 1 Do not select M X It may be 0 or 1 b t Setting division ratio L b15 b8 T li ae Timer BO register Addresses 5116 5016 Do Timer B1 register Addresses 5316 5216 L Can be set to 000016 to FFFF e n J Note The counter divides the count source by n 1 Se Setting interrupt priority level b7 bO Timer Bj interrupt control register j 0 1 Addresses 7A16 7B16 Interrupt priority level select bits When using interrupts set these bits to one of levels 1 to 7 When disabling interrupts set these bits to level 0 lt UN Setting port P5 direction register b7 bO Port P5 direction register Address Die TBOn pin Clear the corresponding bit to
465. ses Figure 13 7 2 shows a transfer parameter memory map in the array chain transfer mode 1 In 2 bus cycle transfer All of the following transfer parameters are required for each block of data that is a transfer parameter memory consumes 12 bytes for each block Transfer source s transfer start address 24 bits Dummy data 8 bits Transfer destination s transfer start address 24 bits Dummy data 8 bits Transfer data s byte number 24 bits Dummy data 8 bits 2 In 1 bus cycle transfer from memory to I O All of the following transfer parameters are required for each block of data that is a transfer parameter memory consumes 8 bytes for each block Transfer source s transfer start address 24 bits Dummy data 8 bits Transfer data s byte number 24 bits Dummy data 8 bits 3 In 1 bus cycle transfer from I O to memory All of the following transfer parameters are required for each block of data that is a transfer parameter memory consumes 8 bytes for each block Transfer destination s transfer start address 24 bits Dummy data 8 bits Transfer data s byte number 24 bits Dummy data 8 bits 13 70 7721 Group User s Manual DMA CONTROLLER 13 7 Array chain transfer mode 1 2 bus cycle transfer 4 bytes Transfer L Even address 4 bytes source s transfer M 4 bytes start address H Wand L Even address destination s transfer M satades H Transfer data s byte number 3 L Even addre
466. ses 4D e 4C16 Timer A4 register Addresses 4F16 4E16 7 to 0 These bits can be set to 0016 to FF16 Undefined WO Assuming that the set value m PWM pulse s period output from the TAjour pin is expressed as follows M we 1 i These bits can be set to 0016 to FE 6 Undefined WO Assuming that the set value n the H level width of the PWM pulse output from the TAjour pin is expressed as follows n m 1 fi fi Frequency of count source f2 fie fea or fs12 Note Use the LDM or STA instruction for writing to this register Read from or write to this register in a unit of 16 bits b7 b6 b5 b4 b3 b2 bl b0 111111 Timer Aj mode register j 2 to 4 Addresses 5816 to 5A16 LLL LED USNEM NENNEN NNNM LU EV Ls mw 1 i PWM mode b4 b3 00 Writing 1 to count start register 0 1 TAjin pin functions as a pro grammable I O port Soho Heiner inim E Falling edge of TAjin pin s input signal A edge of Lia pin s input signal b7 b6 00 f2 01 f16 he m ee E 10 f64 1 1 f512 17 22 7721 Group User s Manual APPENDIX Appendix 3 Control registers Timer Bi register b15 b8 b7 bO b7 bO Timer BO register Addresses 5116 5016 PY Timer 81 register Addresses 531e 521e Timer B2 register Addresses 5516 5416 m Fin eaw 15 to 0 These bits have different functions according Undefined RW to the operating mode Note 1 Notes 1
467. set this register to 00 6 17 30 7721 Group User s Manual APPENDIX Appendix 3 Control registers DMAC control register L b7 b6 b5 b4 b3 b2 bi b0 Ll E DMAC control register L Address 6816 i Bit name Functions x Fixed P E id Rotating KAGA E PUE TC pin validity bit Invalid i urs 0s pin functions as a MER programmable I O port CMOS od 1 Valid i P10s pin functions as TC pin N 6 d channel open drain Ss T aaa gem De mese eges ENL MEN s DMAtrequestbt Requested Note 1 Doo Rw D s ewan KEGI KACI Notes 1 The state of bits 4 to 7 are not changed when writing 1 to these bits 2 When writing to this register while any of DMAi enable bits bits 4 to 7 at address 69 6 is 1 set m flag to 1 and use the LDM or STA instruction When DMAi request bit bits 4 to 7 at address 6816 must not be changed set DMAi request bit to q When writing to this register while all of DMAi enable bits bits 4 to 7 at address 69 6 are 0 m flag may be 0 or 1 Use the LDM or STA instruction for writing to this register When DMAi request bit bits 4 to 7 at address 68 e must not be changed set DMAi request bit to 1 DMAC control register H b7 b6 b5 b4 b3 b2 bi b0 DMAC control register H Address 6916 a mum me ene me Software DMAO request bit DMA request Valid when software DMA source The value is 0 at
468. sfer 0 From memory to I O 1 From I O to memory O connection select bit Valid in 1 bus cycle transfer 0 Data bus Do D7 or Do D15 1 Data bus Ds D15 Transfer source wait bit Valid in DMA transfer 0 Wait 1 No wait Transfer destination wait bit Valid in DMA transfer 0 Wait 1 No wait Selection of link array chain transfer mode bo DMAO control register Address 1FCEt16 DMA1 control register Address 1FDEt16 DMA2 control register Address 1FEEt6 DMAS control register Address 1FFE16 o d DMA request source select bits 0000 Do not select 1000 Timer BO 0 0 0 1 External source DMAREQi 1 0 0 1 Timer B1 0010 Software DMA source 1010 Timer B2 001 1 Timer AO 101 1 UARTO receive 0100 Timer A1 1100 UARTO transmit 0101 Timer A2 1101 UART1 receive 0110 Timer A3 1110 UARTI transmit 011 1 Timer A4 111 1 A D conversion Edge sense Level sense select bit Note 0 Edge sense 1 Level sense DMAACKi validity bit 0 Invalid 1 Valid N ARF Note When an external source DMAREQi is selected or when the cycle steal transfer mode is selecied set this bit to 0 Continue to Figure 13 8 5 on next page b23 b16 b15 b8 b7 b0b7 b0b7 b0 Source address register 0 J L Source address register 1 c Source address register 2 Source address register 3 of block which is first transferred These
469. smission has started UARTI transmit interrupt z Checking completion of transmission Note This figure shows the bits and registers required for processing UARTO transmit receive control register 0 Address 3416 Refer to Figures 11 3 5 and 11 3 6 for the UART1 transmit receive control register 0 Address 3C16 change of flag state and the occurrence timing of an b7 b0 interrupt request mir Transmit register empty flag 0 During transmitting 1 Transmitting completed P C Processing at completion of transmission Fig 11 3 3 Detection of transmit completion 11 20 7721 Group User s Manual SERIAL I O 11 3 Clock synchronous serial I O mode 11 3 3 Transmit operation When the transmit conditions described in section 11 3 2 Method of transmission are satisfied in the case of selecting an internal clock a transfer clock is generated and the following operations are automatically performed after 1 cycle of the transfer clock has passed When the transmit conditions are satisfied and the external clock is input to the CLKi pin in the case of selecting an external clock the following operations are automatically performed The UARTi transmit buffer register s contents are transferred to the UARTI transmit register he transmit buffer empty flag is set to 1 he transmit register empty flag is cleared to 0 8 transfer clocks are generated when an internal clock
470. sng aul e peideooe si pue si feubis Buljdwes 1s nb i sng y ejiuw p jdwes si p oH JO useJjeJ WWHG Ag pesneo 1senbai sng eu e 4 6 9 L inBi3 ui y5olq ISU eui Buisseooud 104 w19 eniur jo ejduiexe y si euni eA oqe au e sng esn 0 1uBu jo uonisueJ lt P i 9jeis Aey bp SJ9 ouJeJed JOJSULJ JO JaJSUBI OYING 0 4 OLS LLS OL IMOVVIAG Huljdwes 1senboi sng L eev oq 9 v SL Q sry eqq ev AIMO MW lt J LSE inBiq 0 enunuo senbaiJ IVIg euo Ag peuuopned A snonumnuoo si 18JsueJ pun 1941 4 0 9jejs Aee ue wo uoreJedo eu sopow Jajsues uieuo Aee xui pue ureuo Aee ui 490 q uoee DBuisseooud io uuo eniu e Fig 13 8 10 Timing diagram of cycle steal transfer mode 1 7721 Group User s Manual 13 92 DMA CONTROLLER 13 8 Link array chain transfer mode sng esn 0 juu JO uonisuea lt JeJSUeJ UN ISJI4 areis Aee ue ui pajdoooe jou aJe sjeuueuo 1940 aui JO sisenbai WIG Su L peidoooe si pue sng esn o 1uDu y JO uonisueJ ul L SI z jeuDis Buidwes sanba sng eui e iuw pajdwes si vi uq Ag pesneo 1senbai sng ou e peidoooe si pue si euDis Bui dures 1senboi sng eui ejuw pejduues si p oH 10 usaJieJ NYHA Aq pesneo 1senbai sng sul e Z JO w13 y JOU SI 3194 pejoeJes SI epoui 1 suL1 ureuo Aee y UBUM 6 9 L inB 3 Ul YOO G 1S4 y Buissadojd JO Wd jenu jo ejdurexe y s euni eAoqe eu e O
471. ss Transfer source s transfer start address 4 Transfer data s M byte number Transfer destination s transfer start address 4 H y9olq JO Seaweed 1eJsueJ Transfer destination s transfer start address 3 Dummy data Transfer data s byte number 4 Dummy data The above applies when 4 block transfer is performed 2 1 bus cycle transfer Transfer data s byte number 1 source s transfer M start address H Dummy data x L Even address E Transfer source s transfer start address 1 Transfer L Even address yoo JO S19 euJeJed 18JsueJ Transfer data s byte number 4 The above applies on the following conditions When data is transferred from memory to I O When transferring from I O to memory replace all the above mentioned Transfer source s transfer start address with Transfer destination s transfer start address 4 block transfer Fig 13 7 2 Transfer parameter memory map in array chain transfer mode 7721 Group User s Manual 13 71 DMA CONTROLLER 13 7 Array chain transfer mode 13 7 2 Setting of array chain transfer mode Figures 13 7 3 through 13 7 5 show an initial setting example for registers relevant to the array chain transfer mode In addition when timer A timer B UART or the A D converter is selected as a DMA request source the setting for the peripheral is required For details of the setting refer to the chapter of each peripheral function When a DMAi interrupt
472. ss Odd address Transfer destination DRAM area 7721 Group User s Manual 13 37 DMA CONTROLLER 13 4 Operation 13 4 2 1 bus cycle transfer When the transfer method select bit Refer to Figure 13 2 6 1 1 bus cycle transfer is selected 1 bus cycle transfer is the method used to transfer data between a memory and an I O In this method a read and write of 1 tansfer unit data are simultaneously performed during 1 bus cycle The address bus BHE BLE and R W indicate the states of memory Figure 13 4 4 shows an example of connecting external memories and I Os in 1 bus cycle transfer M37721 Address bus DMAACKi DMAREQGI Note The external circuit such as an address latch is disregarded Fig 13 4 4 Example of connecting external memories and l Os in 1 bus cycle transfer 13 38 7721 Group User s Manual DMA CONTROLLER 13 4 Operation In 1 bus cycle transfer the following considerations must be taken in designing the system Achieve the condition that 1 transfer unit data can be accessed in 1 bus cycle Refer to Table 13 4 5 e Specify the transfer address direction and I O connections Refer to Figure 13 2 7 e Compose the read and write signal generating circuit externally These signals are for I Os The M37721 outputs signals to the memory Accordingly make sure to compose the circuit which generates write signals for I Os when the M37721 outputs read signals which generates
473. sses of SARI DARI and TCRi Then rewrite these values into these addresses Set the DMAi enable bit to 1 In repeat transfer array chain transfer and link array chain transfer modes The remaining data of the block that was interrupted by forced termination can be transferred by the following procedure Switch over the current mode to the single transfer mode Read the values at addresses of SARi DARi and TCRi Then rewrite these values into these addresses Set the DMAi enable bit to 1 Refer to Figure 13 3 4 c In order to transfer the next block switch over the current mode to the previous mode after the above mentioned transfer is normally terminated Then re set the values of SARI DARI and TCRi In the array chain or the link array chain transfer mode information such as the next transfer parameters etc cannot be read from each latch 7721 Group User s Manual DMA CONTROLLER 13 3 Control a State at forced termination Latch Previously written values Register Addresses which were to be transferred subsequently or the number of remaining bytes b When setting DMAi enable bit to 1 without rewriting values at addresses of SARI DARi and TCRi A value read from each latch is used by hardware only at the first 1 unit transfer The contents updated by the incrementer decrementer and the decrementer are loaded in each register Values are used by reading them from registe
474. ssing 8 bit data at an odd address waveform d or the first half of f is applied For instructions that are affected by the data length flag m and the index register length flag x operation or is applied when flag m or x 0 operation G or is applied when flag m or x Ec The setup of flags m and x and the selection of the external data bus width do not affect each other 7721 Group User s Manual 3 5 CONNECTION WITH EXTERNAL DEVICES 3 1 Signals required for accessing external devices External data bus width 16 bits BYTE L lt 16 bit data access gt a Access beginning at even address AES TIN MENS ALE N oto A7 As Ds to A15 D15 Data odd A16 Do to A23 D7 Data even BLE 77 BHE b Access beginning at odd address E NN ALE N Aoto A7 As De to At5 Di5 A16 Do to A23 D7 BE y W N 5X BETON 0 0 NX lt 8 bit data access C Access to even address d Access to odd address E E NN gH o ALE ALE N Aa to Ar Aoto Ar As Ds to A15 D15 AddressX As Ds to A15 D15 Data odd A16 Do to A23 D7 Data even A16 Do to A23 D7 Address X BLE BLE y N BHE N K BHE Fig 3 1 2 Examples of operating waveforms of signals input from or output to the external 1 3 6 7721 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 3 1 Signals required for accessing external devices External data bus width 8 bits BYTE H lt
475. ssing unit CPU The microcomputer enters Wait mode when the WIT instruction is executed Wait mode can be terminated by an interrupt request occurrence or the hardware reset 5 4 1 Wait mode When the WIT instruction is executed ceu and stop The oscillator s oscillation is not stopped This state is called Wait mode In Wait mode the microcomputer s power consumption is lowered though Vcc power source voltage is maintained Table 5 4 1 lists the microcomputer s state and operation in and after Wait mode Table 5 4 1 Microcomputer s state and operation in and after Wait mode Item State and Operation State in Oscillation Operating Clock 91 f2 to f512 Operating Timer A uua Operating Serial I O A D converter DMA controller Stopped DRAM controller Stopped Note Watchdog timer Operating Retains the same state in which the WIT instruction was executed Operation after By interrupt request occurrence Supply of cPU and starts just after the termination aes By hardware reset Operates in the same way as hardware reset Wait mode Note The refresh timer operates but DRAM refresh is not performed because the bus request DRAMC does not occur Refer to section Appendix 9 7721 Group Q amp A Ww O 2 gt o O w o Nen Q o Q w o c 7721 Group User s Manual 5 9 CLOCK GENERATING CIRCUIT 5 4 Wait mode 1 Termination by interrupt request occurrence 2
476. ster with a latch DARI indicates the transfer destination address of the data to be transferred next The DARI latch maintains the value written to the address of DARI When a value is written into the address of DARI the same value is written into DARI and the DARI latch When writing a value to the address of DARi all 24 bits must be written The contents of DARi can be read by reading the address of DARi however the value of the DARi latch cannot be read Refer to Tables 13 2 4 and 13 2 5 13 2 6 Transfer counter register i TCRi Transfer counter register i hereafter called TCRi is a 24 bit register with a latch TCRi indicates the number of remaining bytes of the block under transfer The TCRi latch has the following functions e Maintains the value written to the address of TCRi in the single transfer and repeat transfer modes e Indicates the number of remaining blocks in the array chain transfer mode When a value is written into the address of TCRi the same value is written into TCRi and the TCRi latch When writing a value to the address of TCRi all 24 bits must be written The contents of TCRi can be read by reading the address of TCRi however the value of the TCRi latch cannot be read Refer to Tables 13 2 4 and 13 2 5 Table 13 2 4 Addresses of SARI DARI and TCRi nans Source address register i Destination address Transfer counter register i SARI register i DARi TCRi 1FC21e 1FCO 6 1FC616 1F C416 1FCAis
477. stination wait bit Valid in DMA transfer 0 Wait 1 No wait Selection of single transfer mode A Note When an external source DMAREQi is selected or when the cycle steal transfer mode is selected set this bit Continue to Figure 13 5 4 on next page b23 b16 b15 b8 iA PROD BOb7 bO e i V I A b23 b16 b15 b8 b7 b0 b7 b0b7 bO L T b23 b16 b15 b8 b7 b0b7 b0b7 b0 j JT T Ve Source address register 0 Addresses 1FC216 to 1FC016 SARO Source address register 1 Addresses 1FD216 to 1FD016 SAR1 Source address register 2 Addresses 1FE216 to 1FE016 SAR2 Source address register 3 Addresses 1FF216 to 1FF0 6e SAR3 Set the transfer start address of transfer source These bits can be set to 00000016 to FFFFFF e Addresses 1FC616e to 1FC416 Addresses 1FD616 to 1FD4416 Addresses 1FE616e to 1FE416 Addresses 1FF6 6e to 1FF446 Destination address register 0 Destination address register 1 Destination address register 2 Destination address register 3 DARO DAR1 DAR2 DAR3 Nom lt Set the transfer start address of destination These bits can be set to 00000016 to FFFFFF ie Transfer counter register 0 Addresses 1FCA te to 1FC816 Transfer counter register 1 Addresses 1FDA16 to 1FD816 Transfer counter register 2 Addresses 1FEAt6 to 1FE816 Transfer counter register 3 Add
478. stored into this register Each A D register i corresponds to an analog input pin ANi b7 b6 b5 b4 b3 m Fig 12 2 4 Structure b2 bl 7 to 0 of A D register i A D register 0 Addresses 2016 A D register 1 Addresses 2216 A D register 2 Addresses 2416 A D register 3 Addresses 2616 A D register 4 Addresses 2816 A D A D A D register 5 Addresses 2A16 register 6 Addresses 2C16 register 7 Addresses 2E16 7721 Group User s Manual Heads an A D conversion result Baotined RO 12 7 A D CONVERTER 12 2 Block description 12 2 4 A D conversion interrupt control register Figure 12 2 5 shows the structure of the A D conversion interrupt control register For details about interrupts refer to CHAPTER 7 INTERRUPTS b7 b6 b5 b4 b3 b2 bi bo Ab IHI A D conversion interrupt control register Address 7016 Level 0 Interrupt disabled a Level 1 Low level Level 6 Level 2 Level 3 RW Level 4 Level 5 RW Level 7 High level 3 Interrupt request bit A No interrupt requested Interrupt requested Nothing is assigned Undefined Fig 12 2 5 Structure of A D conversion interrupt control register 1 Interrupt priority level select bits bits 2 to 0 These bits select an A D conversion interrupts priority level When using A D conversion interrupts select one of the priority levels 1 to 7 When an A D conversion interrupt request occurs its priori
479. synchronous serial I O mode Ec Transfer clock Transmit enable bit Data is set in UARTi transmit buffer register o Transmit buffer qd dw Q D d p empty flag P UARTi transmit register amp UARTI transmit buffer register CTSi TCLK Stopped because CTSi H Stopped because transmit enable bit 0 CLKi wo XX6X9X6X9X6X8X6 26X9X99636906 90369696396 Transmit register empty flag l UARTi transmit kaa Cleared to 0 when interrupt request is accepted or cleared by software interrupt request bit The above timing diagram applies when the following conditions are satisfied TENpi Next transmit conditions are examined when this signal level is H Internal clock selected TENDi is an internal signal Accordingly it cannot be read from the external CTS function selected Tc Terk 2 n 1 fi fi BRGi count source frequency f2 f16 fe4 f512 n Value set in BRGi Fig 11 3 5 Example of transmit timing when selecting internal clock selecting CTS function Transfer clock Transmit enable bit Data is set in UARTi transmit buffer register Transmit buffer b empty flag UARTi transmit register UARTI transmit buffer register TCLK Stopped because transmit enable bit 0 CLKi TENDi 10 X6X96X9X9969 OME NENEXEXENE__YONENEXEXEXNENE Transmit register empty flag UARTI transmit interrupt request bit
480. t lt 0016 X 0016 aa ooo E a R W ALE kN e External bus width 8 bits BYTE H Q Q cpu Ao A7 00 6 FEt6 X FFie X AD xX As A15 00 6 FFie FFie X ADH x Ais Do Aezs Dz X 00622 0016 X 00 EE o ed nes CDU que est E R W ALE Fig 4 1 10 Internal processing sequence after reset 7721 Group User s Manual 4 1 1 RESET 4 1 Hardware reset 4 1 4 Time supplying L level to RESET pin Time supplying L level to the RESET pin varies according to the state of the clock oscillation circuit e When the oscillator is stably oscillating or a stable clock is input from the XiN pin supply L level for 2 Ls or more e When the oscillator is not stably oscillating including the case at power on reset or in Stop mode supply L level until the oscillation is stabilized The time required for stabilizing oscillation varies according to the oscillator For details contact the oscillator manufacturer Figure 4 1 11 shows the power on reset conditions Figure 4 1 12 shows an example of a power on reset circuit For details about Sto
481. t bit 1 at address 5F e 2 18 7721 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 4 Memory assignment M37721S2BFP M37721S1BFP 00000066 1 4 SFR area Note 1 SFR area Note 1 00007F 6 BEER 00008016 512 bytes Case of Internal RAM Internal RAM area area select bit 0 512 bytes Note 2 00027F Internal RAM J Interrupt vector table area Case of Internal RAM OOFFCEt6 DMA3 512 bytes area select bit 1 00047Ft16 i OOFFDO16 DMA OOFFD216 DMA1 OOFFD416 DMAO OOFFD616 A D conversion Lr i OOFFD816 UART1 transmit 001FCO016 OOFFDAt6 UART1 receive H H H OOFFDCi6 OOIFFFie l lh h OO0FFDE te OOFFEO16 Timer B2 L OOFFE216 Timer B1 E OOFFE416 Timer BO E Q0FFCEe eee O C r Iuda X JM OOFFESi6 O0FFEA s O0FFECs 00FFEE16 OOFFFOte INT E OOFFF216 O0FFF4 e dii ibd OOFFFAte BRK instruction OOFFFCte zero divide OOFFFEt16 aera r ari JJ m ep m IHTT FFFFFFi6 The internal memory is not assigned SFR area Refer to Figure 2 4 2 and Figure 2 4 3 Notes 1 Addresses 216 to 916 are the external memory area 2 For the M37721S1BFP fix the internal RAM area select bit to 0 3 DBC is an interrupt only for debugging do not use this interrupt Fig 2 4 1 Memory assignment 7721 Group User s Manual 2 19 CENTRAL PROCESSING UNIT CPU 2 4 Memory assignment Addr
482. t P6 pins are floated since these pins are in the input mode The output levels of the pulse output pins are undefined until Timer AO or A1 underflows first after the data for the timer is written Because the pulse output data registers 0 and 1 are undefined after reset When these conditions should be avoided follow the procedure Processing of avoiding undefined output before starting pulse output in Figures 10 3 1 and 10 3 2 When reading the port P6 register address Eis the output values of the real time output pins can be read out 10 2 4 Timers AO and A1 The data written into the pulse output registers 0 and 1 is output from the pulse output pins every underflow of Timer AO or A1 Refer to section 8 3 Timer mode for the setting of Timers AO and A1 10 6 7721 Group User s Manual REAL TIME OUTPUT 10 3 Setting of real time output 10 3 Setting of real time output Figures 10 3 1 to 10 3 3 show an initial setting example for registers relevant to the real time output Note that when using interrupts set up to enable the interrupts For details refer to CHAPTER 7 INTERRUPTS Z Processing of avoiding undefined output before starting pulse output We b7 bO Port P6 register Address E16 Note This processing can be neglected if the system is not affected by RTPOo Setto initial output level undefined output RTPO of real time output RTPO02 0 L level RTPOs 1 H level RTP1o RTP1 RTP
483. t bits bits 3 to 0 at address 6416 00102 Fig 16 1 26 Example of M5M418160CJ 1M X 16 bits connection external bus width z 16 bits 16 30 7721 Group User s Manual APPLICATION 16 1 Memory connection lt When reading gt E tw EL 135 min OE RAS i tw RASL 120 min La tw RASH 60 min td RAS CAS 28 min td E RASL 30 max 9 CAS td E CASL 77 5 max lt tw CASL 92 5 min td RA RAS 5 min C gt gt id CA CAS 5 min tOEA 20 max tAA 35 max tRAC 70 max Aie Do A23 D7 VN tCLZ 5 min u S G tsu DL DH E gt 30 td BLE BHE E 20 min lt m gt toEZ 0 15 ac gt tCAC 20 max AC157 tPHL BLE BHE When writing tpzx E DLZ DHZ 20 min td E CA 60 max gt lt m 4 Y Y Y E tw EL 135 min tw RASH 60 min HS tw RASL 120 min RAS lt gt tw CASL 55 min CAS S gt td E CASL 80 115 td R W E 20 min gt lt gt R W gt AC32 tPHL gt AC32 tPHL twcs 0 min tWCH 10 min gt lt W td RA RAS 5 min th RAS RA 18 min gt lt MAo MAg Row Address p Column address T CA CAS 10 min th CAS CA 60 min gt A16 Do A23 D7 V
484. t generated Sequence of execution Interrupt request accepted Interrupt priority detection time Previous instruction LDM instruction LDA instruction CPU operation executed executed BIU operation Instruction prefetched Interrupt priority level select bits set Change of interrupt priority levels completed 7721 Group User s Manual 17 69 APPENDIX Appendix 9 7721 Group Q amp A Interrupt To prevent this problem after change of the interrupt priority level is completed use software to execute the routine that should not accept a certain interrupt request The following shows a sample program Sample program After an instruction which writes 0002 to the interrupt priority level select bits fill the instruction queue buffer with the NOP instruction to make the next instruction not to be executed before the writing is completed LDM 00H XXXIC Sets the interrupt priority level select bits to 0002 NOP NOP NOP LDA A DATA Instruction at the beginning of the routine that should not accept a certain interrupt request 17 70 7721 Group User s Manual APPENDIX Appendix 9 7721 Group Q amp A Interrupt 1 Which timing of clock is the external interrupts input signals to the INTi pin detected 2 How can four or more external interrupt input pins INTi be used 1 In both the edge sense and level sense external interrupt requests occur when the input signal t
485. t is set to 1 the counter is divided into 8 bit halves Then the high order 8 bits operate as an 8 bit pulse width modulator and the low order 8 bits operate as an 8 bit prescaler Figures 8 6 6 and 8 6 7 show operation examples of the 8 bit pulse width modulator Notes 1 If a value 000016 is set into the timer Aj register when the counter operates as a 16 bit pulse width modulator the pulse width modulator does not operate and the output from the TAjour pin remains L level The timer Aj interrupt request does not occur Similarly if a value 0016 is set into the high order 8 bits of the timer Aj register when the counter operates as an 8 bit pulse width modulator the same is performed 2 When the counter operates as an 8 bit pulse width modulator after a trigger is generated the TAjour pin outputs L level which has the same width as H level width of the PWM pulse which was set After that the PWM pulse output starts from the TAjour pin 7721 Group User s Manual 8 43 TIMER A 8 6 Pulse width modulation PWM mode 1 fix 216 1 Count source PULL TAjin pin s input signal ME Trigger is not generated by this signal 1 fix n PWM pulse output from TAjour pin Timer Aj interrupt request bit fi Frequency of count source f2 f16 fe4 or f512 Cleared to 0 when interrupt request is accepted or cleared by software Note The above applies when reload regis
486. t priority level detection circuit 7 5 Interrupt priority level detection circuit The interrupt priority level detection circuit selects the interrupt with the highest priority level when more than one interrupt request occurs at the same sampling timing Figure 7 5 1 shows the interrupt priority level detection circuit Interrupt priority level Level 0 initial value Y DMA3 DMA2 7 DMA1 x DMAO i NZ Interrupt priority level 5 i UART1 transmit N eeh NZ V DART Transmit J Timem y V UARTO receive y y INT2 7 y amd TimerBO BO INTo NEN ANZ V t i IPL Interrupt with the highest priority level I o Processor interrupt priority level Interrupt O E disable flag I Watchdog timer interrupt gt Accepting of interrupt request Reset Fig 7 5 1 Interrupt priority level detection circuit 7 10 7721 Group User s Manual INTERRUPTS 7 5 Interrupt priority level detection circuit The following explains the operation of the interrupt priority detection circuit using Figure 7 5 2 The interrupt priority level of a requested interrupt Y in Figure 7 5 2 is compared with the resultant priority lev
487. t registers Addresses 1816 Port P10 direction register Fig 6 2 1 Memory map of direction registers and port registers 6 2 7721 Group User s Manual INPUT OUTPUT PINS 6 2 Programmable I O ports 6 2 1 Direction register This register determines the I O direction of programmable I O ports Each bit of this register corresponds one for one to each pin of the microcomputer Figure 6 2 2 shows the structure of port Pi i 4 to 10 direction register b7 b6 b5 b4 b3 b2 bi b0 Port Pi direction register i 4 to 10 Addresses C16 D16 1016 1116 1416 1516 1816 m C m ERE Port Pio direction bit 0 Input mode The port functions as an input port Ep Port Pi direction bit 1 Output mode The port functions as an output port e ronron Note For bits 0 to 2 of the port P4 direction register nothing is assigned and these bits are fixed to 0 at reading Fig 6 2 2 Structure of port Pi i 4 to 10 direction register 7721 Group User s Manual 6 3 INPUT OUTPUT PINS 6 2 Programmable I O ports 6 2 2 Port register Data is input from or output to the external by writing reading data to from a port register A port register consists of a port latch which holds the output data and a circuit which reads the pin state Each bit of the port register corresponds one for one to each pin of the microcomputer Figure 6 2 3 shows the structure of the port Pi i 4 to 10 register When outputt
488. t source s valid edges When a counter underflow or overflow occurs the reload register s contents are reloaded and counting continues The timer Aj interrupt request bit is set to 1 at the underflow or overflow in The interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software Figure 8 4 4 shows an example of operation in the event counter mode n Reload register s contents FFFF16 Counter contents Hex 000016 Set to 1 by software Count start bit Up down bit Timer Aj interrupt request bit Cleared to O when interrupt request is accepted or cleared by software Note The above applies when the up down bit s contents are selected as the up down switching factor i e up down switching factor select bit 0 Fig 8 4 4 Example of operation in event counter mode without pulse output and two phase pulse signal processing functions 7721 Group User s Manual 8 23 TIMER A 8 4 Event counter mode 8 4 3 Switching between countup and countdown The up down register address 4416 or the input signal from the TAjour pin is used to switch countup from and to countdown This switching is performed by the up down bit when the up down switching factor select bit bit 4 at addresses 5816 to 5A16 is 0 and by the input signal from the TAjour pin when the up down switching factor select bit
489. ta is ready in the UARTI receive register before the data which has been transferred to the UARTi receive buffer register is read out i e an overrun error occurs The UARTi receive buffer register is initialized by setting the receive enable bit bit 2 at addresses 3516 3D e to 1 after clearing it to 0 Figure 11 2 9 shows the contents of the UARTi receive buffer register when reception is completed High order byte Low order byte addresses 3716 3F 6 addresses 3616 3E16 b7 b7 b0 b0 Transfer data length bits e o ooo oo fo p Receive data 9 bits In clock synchronous serial l O mode in UART mode ofofojojofofof Transfer data length 8 bits Same value as bit i 7 in low order byte a PEE MUN 7 bits ooo C Receive data 8 bits V v n Same value as bit f Fig 11 2 9 Contents of UARTi receive buffer register when reception is completed 11 12 7721 Group User s Manual SERIAL I O 11 2 Block description 11 2 6 UARTi baud rate register BRGi The UARTi baud rate register BRGi is an 8 bit timer exclusively used for UARTi to generate a transfer clock It has a reload register Assuming that the value set in the BRGi is n n 0016 to FF e the BRGi divides the count source frequency by n 1 In the clock synchronous serial I O mode the BRGi is valid when an internal clock is selected and the BRGi s output divided by 2 becomes the trans
490. ta high order setup time after rising of ALE Note 135 ns Note Figure 13 shows the test circuit 17 92 7721 Group User s Manual APPENDIX Appendix 11 Electrical characteristics Microprocessor mode with Wait lt Write gt tw L tw H tr tf tc 01 E td AL E amp gt th E AL Add tout porous Address output d AM E h E AM va BYTE H Address Data output d AM E 4 d E DHQ lt gt th E DHQ BYTE L Data lt Data input i I Do Dig IMAM ALE UNALE AM ee eee ee eee iac c Deen ee Pee td AH E 3 td E DLQ lt p th E DLQ Address Data output ps E Data input ld AH ALE th ALE AH Dos esee NSIEq eem pu ns S sS 7 ooo ene ecu uerius tw ALE gt td ALE E ALE output td BHE E th E BHEJ gt td BLE E lt gt th E BLEJ td R W E th E R W HE lt I R W output N EB td E PiQ lt gt Port Pi output P i 4 10 Test conditions port Pi Test conditions except port Pi Vcc 5V t10 Vcc 5 V 10 Input timing voltage Vi 1 0 V ViH 4 0 V Output timing voltage Vor 0 8 V Vor 2 0 V Output timing voltage VoL 0 8 V Vor 2 0 V Data input Vit 0 8 V Vir 2 5 V 7721 Group User s Manual 17 93 APPENDIX Appendix 11 Electrical characteristics 17 94 Microprocessor mode with Wait lt Read gt f Xin 1 E Address out
491. tart condition Count stop condition Interrupt request occurrence timing TAjin TAjour pin function Read from timer Aj register Write to timer Aj register Specifications External signal two phase pulse input to the TAjw or TAjour pin Countup or countdown can be switched by external signal two phase pulse When a counter overflow or underflow occurs reload register s contents are reloaded and counting continues For countdown 1 n 1 n Timer Aj registers set value For countup 1 FFFF e n 1 When the count start bit is set to 1 When the count start bit is cleared to 0 When a counter overflow or underflow occurs Two phase pulse input Counter value can be read out While counting is stopped When a value is written to the timer Aj register it is written to both of the reload register and counter While counting is in progress When a value is written to the timer Aj register it is written only to the reload register Transferred to the counter at the next reload time 7721 Group User s Manual 8 19 TIMER A 8 4 Event counter mode b7 b6 b5 b4 b3 b2 bl b0 x x o ofa Timer Aj mode register j 2 to 4 Addresses 5816 to 5A16 Lm Bienen me nw o w EN Operating mode select bits nr 01 P counter mode L Pulse output function select bit 0 No pulse output TAjour pin functions as a programmable O port Pulse output TAjour a func
492. td E CASL 77 5 max lt tw CASL 92 5 min gt td RA RAS 5 min s td CA CAS 5 min MAo MA7 tOEA 20 max tAA 35 max td E CA 60 max gt lt tRAC 70 max A16 D0 A23 D7 D AupRees Wan ete celle cate eR u at d ned CLZ 5 min lt gt td AH E 15 min tCAC 20 max tsu DL DH E gt 30 tggzx 0 20 As A9 M5M44170AJ When writing tw EL 135 min m tw RASH 60 min EM tw RASL 120 min RAS lt gt P tw CASL 55 min CAS P s td E CASL 80 115 td R W E 20 min gt lt gt R W gt AC32 tPHL X 2 gt C32 tPHL X 2 twcs 0 min tWCH 15 min gt lt WL WH td RA RAS 5 min gt th RAS RA 18 min fa A CAS 10 min th CAS CA 60 min e A16 Do A23 D7 V As Ds A15 D15 Address Data gt td BLE BHE E 20 min tDH 15 min fo min min lt gt th E DLQ DHQ 18 min Specification of M5M44170CJ 7 The others are specifications of M37721 Unit ns Fig 16 1 29 Timing chart for example of M5M44170CJ 256K X 16 bits connection external bus width 16 bits 7721 Group User s Manual 16 33 APPLICATION 16 1 Memory connection 8 Example of DRAM connection external bus width 16 bits M37721 M5M41780
493. te Set the transfer start address of the destination a J These bits can be set to 00000016 to FFFFFF46 Read The read value indicates the destination address of data which is next transferred Note When writing to this register write to all 24 bits GS OOO b23 b16 b15 b8 b7 b0 Addresses 1FCA16 to 1FC816 Addresses 1FDAie to 1FD816 Addresses 1FEAte to 1FE816 Addresses 1FFAt 6e to 1FF816 TCR0 TCR1 TCR2 TCR3 Transfer counter register 0 Transfer counter register 1 Transfer counter register 2 Transfer counter register 3 Write Set the byte number of the transfer data Undefined RW These bits can be set to 00000116 to FFFFFF e Read unm dmm i a 17 The read value indicates remaining byte number of the transfer data Note When writing to this register write to all 24 bits Do not set this register to 0000001e Fig 13 5 1 Register structures of SARi DARi and TCRi in single transfer mode 7721 Group User s Manual 13 55 DMA CONTROLLER 13 5 Single transfer mode 13 5 1 Setting of single transfer mode Figures 13 5 2 through 13 5 4 show an initial setting example for registers relevant to the single transfer mode In addition when timer A timer B UART or the A D converter is selected as a DMA request source the setting for the peripheral is required For details of the setting refer to the chapter of each periphera
494. te of the CPU registers immediately after reset Figures 4 1 4 to 4 1 9 show the state of the SFR and internal RAM areas immediately after reset 0 0 immediately after reset o Always 0 at reading 1 1 immediately after reset Undefined immediately after reset Register name State immediately after reset b15 b8 b7 bO Accumulator A A b15 b8 b7 bO Accumulator B B b15 b8 b7 bO index register X 00 b15 b8 b7 bO Index register Y Y b15 b8 b7 bO Stack pointer S b7 bO b7 bO b15 b8 b7 bO Program counter PC Contents at address FFFF16 Contents at address FFFE16 b15 b8 b7 bO Direct page register DPR b15 b8 b7 bO Processor status register PS 0 0 0 0 0 0 0 0j 0j0 0 1 2 IPL N Vm x D 1I Z C Fig 4 1 3 State of CPU registers immediately after reset 4 4 7721 Group User s Manual RESET 4 1 Hardware reset SFR area 016 to 7F16 1FC016 to 1FFF16 Access characteristics RW It is possible to read the bit state at reading The written value becomes valid RO It is possible to read the bit state at reading The written value becomes invalid WO The written value becomes valid It is impossible to read the bit state Nothing is assigned It is impossible to read the bit state The written value becomes invalid State immediately after reset 0 0 immediately after reset 0 Always 0 at reading 1 1 immediately aft
495. ted following the stop bit and the next data is transmitted When performing transmission continuously set the next transmit data in the UARTI transmit buffer register during transmission when the transmit register empty flag O When the transmit conditions for the next data are not satisfied the TxDi pin outputs H level and the transfer clock stops Figures 11 4 6 and 11 4 7 show examples of transmit timing when the transfer data length 8 bits and Figure 11 4 8 shows an example of transmit timing when the transfer data length 9 bits 11 38 7721 Group User s Manual SERIAL I O 11 4 Clock asynchronous serial I O UART mode Transfer clock Transmit enable bit Data is set in UARTi transmit buffer register Transmit buffer D Nb empty flag UARTI transmit register UARTI transmit buffer register TENDi TxDi Transmit register empty flag UARTi transmit interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software The above timing diagram applies when the following conditions are satisfied Parity enabled 1 stop bit Tc 16 n 1 fi or 16 n 1 fEXT CTS function not selected fi BRGi s count source frequency f2 f16 fe4 512 fExT BRGi s count source frequency external clock n Value set in BRGi TENDi Next transmit conditions are examined when this signal level is H TENDi is an internal signal Accordingly it cannot be read fr
496. tents are transferred to the counter when the next underflow occurs The counter value is read out by reading out the timer Bi register Note When reading from or writing to the timer Bi register perform it in a unit of 16 bits For more information about the value obtained by reading the timer Bi register refer to Precautions for timer mode and Precautions for event counter mode Functions in pulse period pulse width measurement mode Countup in the counter is performed each time the count source is input The reload register is used to retain the pulse period or pulse width measurement result When a valid edge is input to the T Bj pin the counter value is transferred to the reload register In this mode the value obtained by reading the timer Bj register is the reload register s contents so that the measurement result is obtained Note When reading from the timer Bj register perform it in a unit of 16 bits Table 9 2 1 Memory assignment of timer Bi registers Timer Bi register High order byte Low order byte Timer BO register Address 5116 Address 5016 Timer B1 register Address 5316 Address 5216 Timer B2 register Address 5516 Address 5416 Note At reset the contents of the timer Bi register are undefined 7721 Group User s Manual 9 3 TIMER B 9 2 Block description 9 2 2 Count start register This register is used to start and stop counting Each bit of this register corresponds to each timer Figure
497. ter n 000316 and an external trigger rising edge of TAJN pin s input signal is selected Fig 8 6 4 Operation example of 16 bit pulse width modulator n Reload register s contents 1 f X 216 1 1 fi X 216 1 4 I Counter contents Hex 000116 Restarts counting TAjin pin s input signal PWM pulse output from TAjour pin FFFE e is set to timer Aj 000016 is set to timer Aj 200016 is set to timer Aj fi Frequency of count source register register register f2 fie fea or f512 When an arbitrary value is set to the timer Aj register after setting 000016 to it the timing at which the PWM pulse goes H depends on the timing at which the new value is set Note The above applies when an external trigger rising edge of TAjin pin s input signal is selected Fig 8 6 5 Operation example of 16 bit pulse width modulator when counter value is updated during pulse output 8 44 7721 Group User s Manual TIMER A 8 6 Pulse width modulation PWM mode 1 fi X m 1 X 28 1 1 Count source L TAji pin s input signal 1 f x m 1 2 8 bit prescaler s underflow signal PWM pulse output from TAjour pin Timer Aj interrupt request bit fi Frequency of count source fo fre fea or fs12 Cleared to O when interrupt request is accepted or cleared by software D The 8 bit prescaler co
498. ter a value is written to this register and until transfer starts the read value indicates the written value dummy data After transfer starts the read value indicates the remaining byte number of the block which is being transferred Note When writing to this register write to all 24 bits Do not write 00000016 to this register Fig 13 8 1 Register structures of SARi DARi and TCRi in link array chain transfer mode 7721 Group User s Manual 13 81 DMA CONTROLLER 13 8 Link array chain transfer mode 13 8 1 Transfer parameter memory in link array chain transfer mode The transfer parameters required for each transfer method are described below These parameters can be located in separate memory locations in a unit of one block s parameters However these parameters must be located starting at an even address Figure 13 8 2 shows a transfer parameter memory map in the link array chain transfer mode 1 2 3 Note 13 82 In 2 bus cycle transfer All of the following transfer parameters are required for each block of data that is a transfer parameter memory consumes 16 bytes for each block Transfer source s transfer start address 24 bits Dummy data 8 bits Transfer destination s transfer start address 24 bits Dummy data 8 bits Transfer data s byte number 24 bits Dummy data 8 bits e Start address of next transfer parameter memory 24 bits Note Dummy data 8 bits In
499. ter compares the comparison voltage Vre which is internally generated according to the contents of the successive approximation register with the analog input voltage Vin which is input from the analog input pin ANi By reflecting the comparison result on the successive approximation register Vin is converted into a digital value When a trigger is generated the A D converter performs the following processing D Determining bit 7 of the successive approximation register The A D converter compares Vre with Vin At this time the contents of the successive approximation register is 100000002 initial value Bit 7 of the successive approximation register changes according to the comparison result as follows When Vret lt Vin bit 7 1 When Vret gt Vin bit 7 0 Determining bit 6 of the successive approximation register After setting bit 6 of the successive approximation register to 1 the A D converter compares Vret with Vin Bit 6 changes according to the comparison result as follows When Vret lt Vin bit 6 1 When Vre gt Vin bit 6 0 Determining bits 5 to 0 of the successive approximation register Operations in are performed for bits 5 to 0 When bit 0 is determined the contents conversion result of the successive approximation register is transferred to the A D register i The comparison voltage Vre is generated according to the latest contents of the successive app
500. terrupt is used exclusively for debugger control Maskable internal interrupts 8 TIMER A Maskable internal interrupts 9 TIMER B Maskable internal interrupts 11 SERIAL I O eMaskable interrupt An interrupt of which request s acceptance can be disabled by software Non maskable interrupt including Zero division BRK instruction Watchdog timer interrupts An interrupt which is certain to be accepted when its request occurs These interrupts do not have their interrupt control registers and are not affected by the interrupt disable flag I 7 4 7721 Group User s Manual INTERRUPTS 7 3 Interrupt control 7 3 Interrupt control The maskable interrupts are controlled by the following eInterrupt request bit Interrupt priority level select bits Processor interrupt priority level IPL Assigned to the processor status register PS eInterrupt disable flag I Assigned to the interrupt control register of each interrupt Figure 7 3 1 shows the memory assignment of the interrupt control registers and Figure 7 3 2 shows their structures Address Fig 7 3 1 Memory assignment of interrupt control registers 7721 Group User s Manual 7 5 INTERRUPTS 7 3 Interrupt control b7 b6 b5 b4 b3 b2 bi b0 DMAO to DMA3 A D conversion UARTO and 1 transmit UARTO and 1 receive timers AO to A4 timers BO to B2 interrupt control registers Addresses 6C 6 to 7C 6 Edd Pie ee Level 0 Interrupt disabl
501. terrupts refer to CHAPTER 7 INTERRUPTS b7 b6 b5 b4 b3 b2 bli Timer Ai interrupt control register i O to 4 Addresses 7516 to 7916 level His ia iu Level 0 Interrupt disabled 0 1 Level 1 Low level Level 6 Level 2 Level 3 Level 4 Level 5 RW NA Level7 High level Interrupt request bit T No interrupt requested Interrupt requested 7104 to 4 7 to 4 Nothing i is assigned LL Fig 8 2 4 Structure of timer Ai interrupt control register 1 Interrupt priority level select bits bits 2 to 0 These bits select a timer Ai interrupt s priority level When using timer Ai interrupts select one of the priority levels 1 to 7 When a timer Ai interrupt request occurs its priority level is compared with the processor interrupt priority level IPL The requested interrupt is enabled only when its priority level is higher than the IPL However this applies when the interrupt disable flag I 0 To disable timer Ai interrupts set these bits to 0002 level 0 2 Interrupt request bit bit 3 This bit is set to 1 when a timer Ai interrupt request occurs This bit is automatically cleared to 0 when the timer Ai interrupt request is accepted This bit can be set to 1 or cleared to 0 by software 7721 Group User s Manual 8 7 TIMER A 8 2 Block description 8 2 5 Port P5 direction register The I O pins of Timers A2 to A4 are multiplexed with port P5
502. that the sum of ns Pede gt CS propagation delay time is within circuit circuit gt CS2 72 ns A0 A7 Address bus RDY m 1 Validate Ready function only for areas accessed by CS2 ACOA 4 Circuit conditions f XIN lt 15 7 MHz no software Wait td E 61 lc Ready request is accepted at A Termination request for Ready state is accepted amp Judgement timing of RDY pin s input level ru GSD E L level stopped by Ready function The condition satisfy tsu RDY 91 gt 55 ns is tc E gt 63 5 ns This applies when AC32 s propagation delay time is within 8 5 ns Accordingly when f XIN lt 15 7 MHz this circuit example satisfies tsu RDY 1 gt 55 ns CS Q RDY gt _ lt tsu RDY 91 AC32 tPHL Fig 16 1 9 Example of using Ready function no software Wait 7721 Group User s Manual 16 13 APPLICATION 16 1 Memory connection M37721 1 to 3 Make sure that the sum of propagation delay time is within 25 Data bus Ns ns Address gt CSi atc ecoae circuit circuit CS2 Ao A7 Address bus RDY 3 AC32 m Validate Ready function only for areas accessed by CS2 o1 AC74 2 Circuit conditions f XIN lt 25 MHz software Wait A 01 Y D Ready request is accepted at A Termination request for Ready state is accepted at B LI A B Judg
503. the TC pin When external DMA source is selected When internal DMA source is selected Setting port P9 direction register b7 b0 Port P9 direction register Address 1516 DMAREQO pin DMAREQ1 pin DMAREQ2 pin DMAREQOS pin Clear the corresponding bit to 0 Continue to Figure 13 6 3 on next page Fig 13 6 2 Initial setting example for registers relevant to repeat transfer mode 1 7721 Group User s Manual 13 63 DMA CONTROLLER 13 6 Repeat transfer mode From preceding Figure 13 6 2 g Selection of transfer mode and each function b7 b0 DMAO mode register L ITT mode resister L DMA2 mode register L DMAS mode register L 0 16 bits 1 8 bits Transfer method select bit 0 2 bus cycle transfer 1 1 bus cycle transfer Transfer mode select bit 0 Burst transfer mode 1 Cycle steal transfer mode 0 0 Fixed 01 Forward 1 0 Backward 1 1 Do not select 0 0 Fixed 0 1 Forward 1 0 Backward 1 1 Do not select DMA1 mode register H transfer 0 From memory to I O 1 From I O to memory transfer 0 Data bus Do D7 or Do D15 1 Data bus Ds Dis Address 1FCC1e Address 1FDC1e Address 1FECie Address 1FFC16 Number of unit transfer bits select bit Transfer source address direction select bits Transfer destination address direction select bits DMAO m
504. the CAS signals are output and the DRAM data is refreshed refresh cycle 3 cycles of The right to use the bus is passed to the CPU DRAM or Hold 1 cycle of The outputs of ST1 and STO change Note In Stop or Wait mode DRAM refresh is not performed because no refresh request occurs Table 14 4 1 Delay time from when refresh request occurs until DRAM refresh is performed Delay time unit cycle es Tas no pe Maximum with Wait CPU 6 5 Transfer a unit of 1 transfer 12 5 DMAC Transfer a unit of 1 transfer Complete cycle l 1 15 5 Amaystate Amaystate 6 5 Hold 15 Note The above is applied when Ready is not used The FEES time includes the time for passing the right to use buses to DRAM refresh 1 cycle Source of using bus 14 10 7721 Group User s Manual DRAM CONTROLLER 14 4 DRAMC operation Q E R W Refresh request Bus request DRAMC Bus request sampling ST1 STO Co o XA j 11 CPU 00 Refresh Delay time Min 1 5 cycles of Refresh cycle Delay time Max 6 5 cycles of Refresh cycle amp gt lt i lt gt i lt gt lt gt lt gt lt gt Transition of right to use bus Transition of right to use bus Transition of right to use bus Transition of right to use bus The following are internal signals Refresh request Bus request DRAMC Bus request sampling Refresh request becomes 0 at an underflow of the ref
505. the DMAi enable bit At normal termination SARI latch Indicates the transfer start address of data block at the transfer source SARI Indicates the address of the next transfer source DARi latch Indicates the transfer start address of data block at the transfer destination DARI Indicates the address of the next transfer destination TCRi latch Indicates the number of transfer bytes TCRi Indicates the number of remaining transfer bytes TC pin validity bit Bit 1 at address 68 e 13 54 7721 Group User s Manual DMA CONTROLLER 13 5 Single transfer mode b23 b16 b15 b8 b7 b0 Addresses 1FC216 to 1FC016e SARO Addresses 1FD216 to 1FD016 SAR1 Addresses 1FE216 to 1FE016 SAR2 Addresses 1FF216e to 1FF0 e SAR3 Source address register 0 Source address register 1 Source address register 2 Source address register 3 Umm 23 to 0 Write Undefined RW Set the transfer start address of the source These bits can be set to 000000 e to FFFFFF e Read The read value indicates the source address of data which is next transferred Note When writing to this register write to all 24 bits b23 big b15 bg b7 bO Addresses 1FC616 to 1FC416 DARO Addresses 1FD616 to 1FD416 DAR1 Addresses 1FE616 to 1FE416 DAR2 Addresses 1FF616e to 1FF416 DAR3 Destination address register 0 Destination address register 1 Destination address register 2 Destination address register 3 L Wri
506. the RTI instruction is executed the interrupt priority level of the routine which was in progress at acceptance of an interrupt request is pulled into the IPL Therefore if the following relationship is satisfied when interrupt priority level detection is performed next the held interrupt request is accepted Held interrupt request s priority level gt Processor interrupt priority level IPL 7 16 7721 Group User s Manual INTERRUPTS 7 9 Multiple interrupts Interrupt request generated Nesting Time Main routine Interrupt 1 pee II Interrupt priority level 3 a Interrupt 1 Interrupt 2 IPL 3 Multiple interrupts Interrupt priority level 5 yee Interrupt 2 IPL 25 Interrupt 3 RT Interrupt priority level 2 IPL 3 DENEN RTI This request cannot be accepted because its priority level is lower than the interrupt 1 s one estesa IPL 0 The instruction in the main routine is not executed Interrupt disable flag IPL Processor interrupt priority level L They are automatically set _ They must be set by software Fig 7 9 1 Processing for multiple interrupts 7721 Group User s Manual 7 17 INTERRUPTS 7 10 External interrupts INTi interrupt 7 10 External interrupts INTi interrupt An external interrupt request occurs by an input signal to the INTi i 0 to 2 pin The occurrence factor of the interrupt request can be se
507. the UARTi transmit buffer register Set the transmit data into the low order byte of this register when the microcomputer operates in the clock synchronous serial I O mode or when a 7 bit or 8 bit length of transfer data is selected in the UART mode When a 9 bit length of transfer data is selected in the UART mode set the transmit data into the UARTi transmit buffer register as follows Bit 8 of the transmit data into bit O of high order byte of this register Bits 7 to 0 of the transmit data into the low order byte of this register The transmit data which is set in the UARTi transmit buffer register is transferred to the UARTI transmit register when the transmission conditions are satisfied and then it is output from the TxDi pin synchronously with the transfer clock The UARTi transmit buffer register becomes empty when the data which is set in the UARTI transmit buffer register is transferred to the UARTi transmit register Accordingly the user can set the next transmit data When quitting the transmission which is in progress and setting the UARTi transmit buffer register again follow the procedure described bellow Clear the serial I O mode select bits bits 2 to 0 at addresses 30 e 3816 to 0002 Serial I O disabled Set the serial I O mode select bits again Set the transmit enable bit bit 0 at addresses 3516 3D e to 1 transmission enabled and set transmit data in the UARTi transmit buffer register 11 10 7
508. the bit state at reading The written value becomes valid RO It is possible to read the bit state at reading The written value becomes invalid WO The written value becomes valid It is impossible to read the bit state Nothing is assigned It is impossible to read the bit state The written value becomes invalid State immediately after reset 0 0 immediately after reset 1 1 immediately after reset Undefined immediately after Always 0 at reading Always 1 at reading 4 BEE 17 8 reset Always undefined at reading 0 immediately after reset Fix this bit to 0 Address Register name Access characteristics late immediately after reset 1FE016 1FE116 Source address register 2 1FE216 1FE316 1FE416 1FE516 Destination address register 2 1FE616 1FE716 1FE816 1FE916 Transfer counter register 2 1FEA16 1FEB16 1FEC16 DMA2 mode register L 0 0 0 0 SN 0 0 0 1FED16 DMA2 mode register H 0 0 0 0 NNS 0 0 1FEE16 DMA2 control register 1 2 2 0 0 0 0 0 0 1FEF16 1FF016 1FF116 Source address register 3 1FF216 1FF316 1FF416 1FF516 Destination address register 3 1FF616 1FF716 1FF816 1FF916 Transfer counter register 3 1FFA16 1FFB16 1FFC16 DMA3 mode register L NN O0j0 1FFD16 DMAS mode register H NNN 1FFE16 DMAS control register f 0 0 0 1FFFi6 7721 Group User s Manual APPENDIX Appendix 3 Control registers Appendi
509. the stack bank select bit described later bit 7 at address 5E e The stack area is specified to bank 0 s when the stack bank select bit is 0 and the stack area is specified to bank FF ewhen it is 1 When an interrupt request is accepted the microcomputer stores the contents of the program bank register PG at the address indicated by the contents of S and decrements the contents of S by 1 Then the contents of the program counter PC and the processor status register PS are stored The contents of S after accepting an interrupt request is equal to the contents of S decremented by 5 before the accepting of the interrupt request Refer to Figure 2 1 2 When completing the process in the interrupt routine and returning to the original routine the contents of registers stored in the stack area are restored into the original registers in the reverse sequence PS PC gt PG by executing the RTI instruction The contents of S is returned to the state before accepting an interrupt request The same operation is performed during a subroutine call however the contents of PS is not automatically stored The contents of PG may not be stored This depends on the addressing mode The user should store registers other than those described above with software when the user needs them during interrupts or subroutine calls Additionally initialize S at the beginning of the program because its contents are undefined at reset The stack area chan
510. thin 20 mm from the microcomputer s pins 3 This applies when a clock externally generated is input to the Xin pin When setting ports to input mode When setting ports to output mode P43 P47 P5 P10 P43 P47 P5 P10 eft open STO STO STI STI BLE Left open BLE Left open BHE BHE ALE ALE 01 01 Xour Left open Xour Left open Vcc Vcc CNVss pin can be connected to Vcc pin Fig 2 Examples of handling unused pins 7721 Group User s Manual 17 41 APPENDIX Appendix 6 Machine instructions Appendix 6 Machine instructions Addressing modes Symbol Functions Details IMP IMM A DIR pno DIR X DIR Y DIR DIR X DIR Y ADC Acc C Acc M C Notes 1 2 Adds the carry the accumulator and the memory contents The result is entered into the accumulator When the D flag is 0 binary additions is done and when the D flag is 1 decimal addition is done AND Acc AccAM Obtains the logical product of the contents of the accumu Notes 1 2 lator and the contents of the memory The result is en tered into the accumulator Shifts the accumulator or the memory contents one bit to the left 0 is entered into bit O of the accumulator or the memory The contents of bit 15 bit 7 when the m flag is 1 of the accumulator or memory before shift is entered into the C flag m 0 e ps Te9 o 1 m lt b7 f bo JO BBC Mb 0 Tests the specified bit of the memory Branches
511. tion Software Wait 25 MHz 1 Make sure that the propagation delay time is within 20 ns 2 3 Make sure that the sum of output disable time in 2 and propagation delay time in 3 is within 20 ns 4 Make sure that the propagation delay time is within 15 ns Fig 16 1 12 Example of using bus buffers 1 16 16 7721 Group User s Manual APPLICATION 16 1 Memory connection lt When reading gt tw EL 135 min Ti tpzx E DLZ DHZ 20 min As Ds A15 D15 Aie Do Aos Dz iw OA rrr s gt lt AC32 tPHL AC32 tPLH cacas AB SOS Y TS gt nop Data output A from teZH tP2L tPHZ tPLZ external memory AC245 J XD 0 ye When writing tw EL 135 min lt E Id E DL Q DHQ 35 max gt As Ds A15 D15 I Aie Do Aes D7 A 7 X 1 ee B XA ACS2 ipHL gt AC32 tPLH OC AC245 WO WE ee peat gt Data output B from tPHL tPLH tPHz tPLz external memory AC245 rrr A D J Unit ns Fig 16 1 13 Timing chart for circuit example using bus buffers 1 7721 Group User s Manual 16 17 APPLICATION 16 1 Memory connection M37721 Address bus dcc AC245 As Ds A15 D15 A B Data bus odd eam A16 Do A23 D7 A B Y Data bus even These circuits make the occurrence of the write signal s rising edge earlier by 1 2 1 so that the write hold time is extended Circuit
512. tion in the repeat mode Trigger occur Conversion result Convert input voltage from IM A D register ANi pin Fig 12 6 2 Conversion operation in repeat mode 7721 Group User s Manual 12 19 A D CONVERTER 12 7 Single sweep mode 12 7 Single sweep mode In the single sweep mode the operation for the input voltage from multiple selected analog input pins is performed one at a time The A D converter is operated in ascending sequence from the ANo pin The A D conversion interrupt request occurs when the operation for all selected input pins are completed 12 7 1 Settings for single sweep mode Figure 12 7 1 shows an initial setting example for registers relevant to the single sweep mode When using an interrupt it is necessary to set the relevant registers to enable the interrupt Refer to CHAPTER 7 INTERRUPTS for more information 12 20 7721 Group User s Manual A D CONVERTER 12 7 Single sweep mode A D control register and A D sweep pin select register b7 bO 0 H lojx x x b7 bO A D control register address 1E16 LLU TU Tt A D sweep pin select register address 1F 16 Single sweep mode er SEI pin select bits 0 0 ANo AN 2 pins Trigger select bit 0 1 ANo ANs 4 pins 0 Internal trigger 1 0 ANo ANS 6 pins 1 External trigger 1 1 ANo AN 8 pins A D conversion start bit 0 Stop A D conversion A D conversion frequency 6 AD select bit 0 f2 d
513. tion select bits b7 b6 00 fe2 01 f16 10 f64 11 f512 615 b8 Timer AO register Addresses 4716 4616 b7 bO b7 bO Timer A1 register Addresses 4916 4816 Timer A3 register Addresses 4D16 4C16 Timer A4 register Addresses 4F16 4E16 15 to 0 These bits can be set to 000016 to FFFF16 Undefined RW Assuming that the set value n the counter divides the count source frequency by n 1 When reading the register indicates the counter value Note Read from or write to this register in a unit of 16 bits Fig 8 3 1 Structures of timer Ai mode register and timer Ai register in timer mode 8 10 7721 Group User s Manual TIMER A 8 3 Timer mode 8 3 1 Setting for timer mode Figures 8 3 2 and 8 3 3 show an initial setting example for registers relevant to the timer mode Note that when using interrupts set up to enable the interrupts For details refer to section CHAPTER 7 INTERRUPTS Selecting timer mode and each function UN b7 bO lol lojo E ES Timer Ai mode register i 0 to 4 Addresses 5616 to 5A16 Selection of timer mode Pulse output function select bit 0 No pulse output 1 Pulses output Gate function select bits b4 b3 b No gate function 01 1 0 Gate function Counter counts only while TAjin pin s input signal is at L level 1 1 Gate function Counter counts only while TAjin pin s input signal is at H level
514. tions as a pulse output pin Po f 1 1 1 2 2 2 Count polarity select bit Counts at falling edge of external signal i Counts at rising edge of external signal 225222 Up down switching factor select 4 Contents of up down register bit Input signal to TAjout pin SSeS a SSS Seas 5 Fix this bit to O in event counter mode EE ee MEME H These bits are invalid in event counter mode De b7 bO b7 bO Timer A3 register Addresses 4D16 4C16 Timer A4 register Addresses 4F16 4E16 15 to 0 These bits can be set to 000016 to FFFF e Undefined RW Assuming that the set value n the counter divides the count source frequency by n 1 during countdown or by FFFF e n 1 during countup When reading the register indicates the counter value Note Read from or write to this register in a unit of 16 bits Fig 8 4 1 Structures of timer Aj mode register and timer Aj register in event counter mode 8 20 7721 Group User s Manual TIMER A 8 4 Event counter mode 8 4 1 Setting for event counter mode Figures 8 4 2 and 8 4 3 show an initial setting example for registers relevant to the event counter mode Note that when using interrupts set up to enable the interrupts For details refer to CHAPTER 7 INTERRUPTS a Selecting event counter mode and each function k b7 bO DN E Timer Aj mode register j 2 to 4 Addresses 5816 to 5A16 Selection of event cou
515. to Figure 16 2 2 P45 is used for BUSY signal generation When outputting H level the next transfer can wait In that case the contents of the preceding transfer are hold in the octal latch When the data buffer is filled in other words DMA transfer is completed a DMA interrupt occurs 7721 Group User s Manual 16 43 APPLICATION 16 2 Examples of using DMA controller M37721 Octal latch AC574 Data bus DMAREQO TASoutT one shot output TASIN DMAACKO TA2IN P43 TA2outT one shot output Fig 16 2 1 Example of Centronics interface configuration DMAACKO TA2outT TAS3ouT ACK T2 Timer A2 s set time T3 Timer A3 s set time BUSY SiC Fig 16 2 2 Relationship between ACK and BUSY 16 44 7721 Group User s Manual APPLICATION 16 2 Examples of using DMA controller 2 Initial setting example for relevant register 4 Port P4 register Address A16 P43 output H level b7 b7 b7 b0 b0 1 Port P5 register Address B16 b0 G b0 TA3our output H level D F F initialized 1 Port P4 direction register Address Cie P43 Output mode b7 lojio Port P5 direction register Address Dis TA2IN pin Input mode TA3our pin Output mode D F F initialized TAIN pin Input mode b7 bO 0 Port P9 direction register Address 1516 DMAREQO pin Input mode b7 b0 0 1 0 0
516. to 16 Internal area External bus A generic name for the external address bus and the external data bus External device Devices connected externally to the microcomputer A generic name for a memory an I O device and a peripheral IC Internal area An accessible internal area A generic name for areas of the External area internal RAM and the SFH Interrupt routine A routine that is automatically executed when an interrupt request is accepted Set the start address of this routine into the interrupt vector table Overflow A state where the countup resultant is greater than the counter Underflow resolution Countup Read modify write An instruction that reads the memory contents modifies them instruction and writes back to the same address Helevant instructions are the ASL ASR CLB DEC INC LSR ROL ROR SEB instructions Signal required for access A generic name for bus control address bus and data bus signals Bus control to external device signal Stop mode A state where the oscillation circuit halts and the program execution Wait mode is stopped By executing the STP instruction the microcomputer enters the stop mode UART Clock asynchronous serial I O When used to designate the name Clock of a functional block this term also means the serial I O which synchronous can be switched to the cock synchronous serial I O serial I O Underflow A state where the countdown resultant is greater than the counter
517. tructure of one shot start register 8 34 7721 Group User s Manual TIMER A 8 5 One shot pulse mode 8 5 4 Operation in one shot pulse mode When the one shot pulse mode is selected with the operating mode select bits the TAjout pin outputs L level When the count start bit is set to 1 the counter is enabled for counting After that counting starts when a trigger is generated When the counter starts counting the TAjour pin outputs H level When the counter value becomes 000016 the output from the TAjour pin becomes L level Additionally the reload register s contents are reloaded and the counter stops counting there Simultaneously with the timer Aj interrupt request bit is set to 1 This interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to O by software Figure 8 5 5 shows an example of operation in the one shot pulse mode When a trigger is generated after above the counter and TAjour pin perform the same operations beginning from again Furthermore if a trigger is generated during counting the counter performs countdown once after this new trigger is generated and it continues counting with the reload register s contents reloaded If generating a trigger during counting make sure that a certain time which is equivalent to one cycle of the timer s count source or more has passed between the p
518. ty level is compared with the processor interrupt priority level IPL The requested interrupt is enabled only when its priority level is higher than the IPL However this applies when the interrupt disable flag I 0 To disable A D conversion interrupts set these bits to 0002 level 0 2 Interrupt request bit bit 3 This bit is set to 1 when an A D conversion interrupt request occurs This bit is automatically cleared to 0 when the A D conversion interrupt request is accepted This bit can be set to 1 or cleared to 0 by software 12 8 7721 Group User s Manual A D CONVERTER 12 2 Block description 12 2 5 Port P7 direction register Input pins of the A D converter are multiplexed with port P7 When using these pins as A D converter s input pins set the corresponding bits of the port P7 direction register to O to set these port pins for the input mode Figure 12 2 6 shows the relationship between the port P7 direction register and A D converter s input pins b7 b6 b5 b4 b3 b2 bi b0 Port P7 direction register Address 1116 o wem one nos ome 1 Output mode o mw hoc TAE corresponding bits to 0 hon o rw o aw GCS o aw K lt gt ILII Fig 12 2 6 Relationship between port P7 direction register and A D converter s input pins 7721 Group User s Manual 12 9 A D CONVERTER 12 3 A D conversion method 12 3 A D conversion method The A D conver
519. u 2 5 V 7721 Group User s Manual 17 91 APPENDIX Appendix 11 Electrical characteristics Microprocessor mode with Wait Note The limits depend on f Xin Table 4 lists calculation formulas for the limits Timing requirements Vcc 5 V 10 Vss 0 V Ta 20 to 85 C f Xin 25 MHz unless otherwise noted te External clock input cycle time 40 ns tw External clock input high level pulse width 45 ns twit External clock input low level pulse width 15 ns tr External clock input rising time 8 ns tr External clock input falling time 8 ns tsupip e Port Pi input setup time i 4 10 60 ns lagi Port Pi input hold time i 4 10 0 ns Switching characteristics Vcc 5 V 10 96 Vss 0 V Ta 20 to 85 C f Xw 25 MHz unless otherwise noted 35 la E Pio Port Pi data output delay time gol taa E Address low order output delay time Note 15 tae pHa Data high order output delay time BYTE L lt tpxz E DHz Data high order floating start delay time BYTE L Was 35 0 tuam Address middle order output delay tme Note 15 ns taaw atey _ Address middle order output delay time Note 5 teo _ Data low order output delay time 1 1 jns towie o1z_ Data low order floating start delay time 0 ns tae Address high order output del
520. uJ91X3 ROWN suonipuoo Buiwoj oJ eui uo s i dde ajdwexe siu e snq esn 0j yb snq esn oj 1uBu JO UOHISUPJ J JO UOnISUPJ J i Duisseooud ejyeuiuue L J9JSU84 PUN i i lt lt _ oe P A ep oelA ejo o pe y i488 pq OVW 0 1 OLS ILS L MOVVING La ezy 0q 91Y sys v eq sv V 0V NH Builduies 1senboj sng le transfer mode burst transfer mode lagram of sing d iming Fig 13 5 6 T 7721 Group User s Manual 13 60 DMA CONTROLLER 13 6 Repeat transfer mode 13 6 Repeat transfer mode This mode is used to transfer one block of data repeatedly Table 13 6 1 lists the specifications of the repeat transfer mode and Figure 13 6 1 shows the register structures of SARi DARi and TCRi in this mode Table 13 6 1 Specifications of repeat transfer mode Item Performance specifications Transfer parameter memory Not required Condition of normal termination No normal termination Conditions of forced termination Falling edge of the TC pin s input from H to L when the TC pin validity bit 1 Write 0 to the DMAi enable bit Interrupt request generation timing No request is generated Functions of registers SARi latch Indicates the transfer start address of data block at the transfer source SARI Indicates the address of the next transfer source DARi latch Indic
521. ual inductance M Large current Fig 9 Wiring for signa lines where large current flows 2 Distance oscillator from signal lines with frequent potentia level changes Install an oscillator and its wiring pattern away from signal lines where potential levels change frequently Do not cross these signal lines over the clock related or noise sensitive signal lines Reason Signal lines with frequently changing potential levels may affect other signal lines at a rising or falling edge In particular if the lines cross over a clock related signal line clock waveforms may be deformed which causes a microcomputer malfunction or a program runaway 3 Oscillator protection using Vss pattern Print a Vss pattern on the bottom soldering side of a double sided printed circuit board under the oscillator mount position Connect the Vss pattern to the Vss pin of the microcomputer with the shortest possible wiring separating it from other Vss patterns 7721 Group User s Manual M37721 Do not cross I O pin for signal with frequently changing potential levels Fig 10 Wiring for signal lines where potential levels frequently change An example of Vss pattern on the underside of an oscillator M37721 Mounted pattern example of oscillator unit Separate Vss lines for oscillation and supply Fig 11 Vss pattern underneath mounted oscillator 17 63 APPENDIX Appendix 8 Countermeasure against noise
522. ubishi Electric Corporation without notice due to product improvements or other reasons It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use e The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials if these products or technologies are subject to the Japanese export control restrictions they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of JAPAN and or the country of destination is prohibited Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or th
523. uis 1nding US vrcoa veld pzq Hod O I p puedxg zoa _ _ Q ol zoa A ae Zza uod Qj pepuedx3 Lod V Hd Id uodoj pepuedx3 Q Fe oe bond ZZ voa Xezoa ezoa Kizoa azoa Tenas ui indino si 1891s B 1 jus Jo ejeq NT FY T Z J81siD8u uius oj 1ndui si ejep jenas x19 STO S 1491816981 uius 0 1ndino si suod O pepuedxe Jo eq so Wd Suod o pepuedxe ol 1ndino si z 18 s 6 1 yius jo ejeg ejeis ueo Wo pesee jaJ eie suod O pepuedxj S Std _ F T vO oDD Y _ Fig 16 1 37 Serial transfer timing between M37721 and M66010FP 7721 Group User s Manual 16 42 APPLICATION 16 2 Examples of using DMA controller 16 2 Examples of using DMA controller 16 2 1 Example of Centronics interface configuration The following is an example of Centronics interface configurated by using DMAO Timers A2 and A3 1 Specifications Octal latch s contents are transferred to the data buffer RAM by using DMAO The trigger is the STB signal Refer to Figure 16 2 1 L level width of the ACK signal is generated by using Timer A2 one shot pulse mode the trigger is the rising edge of the DMAACKO signal Refer to Figure 16 2 2 Timer A3 generates the time from when the ACK signal rises until the BUSY signal falls one shot pulse mode the trigger is the rising edge of the DMAACKO signal Refer
524. ulse signal die procggemg tagon set the bit WO processing select bit Note The val e is x t reading Note Use the LDM or STA instruction for writing to bits 5 to 7 7721 Group User s Manual 17 17 APPENDIX Appendix 3 Control registers Timer Ai register b15 b8 Timer AO register Addresses 4716 4616 b7 bO b7 bO Timer A1 register Addresses 4916 4816 Timer A3 register Addresses 4D16 4C16 Timer A4 register Addresses 4F 16 4E16 EJ nn 15 to 0 These bits have different functions according Undefined gd to the operating mode Note 1 Notes 1 The access characteristics for the timer A2 register timer A3 register and timer A4 register differ according to Timer A s operating mode 2 Read from or write to this register in a unit of 16 bits Timer Ai mode register b7 b6 b5 b4 b3 b2 bl bO Timer Ai mode register i 0 to 4 Addresses 5616 to 5A16 Cm ame ues eem Operating mode select bits b1 bO 0 0 Timer mode 0 1 Event counter mode 1 1 0 One shot pulse mode 1 1 Pulse width modulation PWM mode These bits have different functions according to the operating mode 17 18 7721 Group User s Manual APPENDIX Appendix 3 Control registers Timer Mode b15 b8 Timer AO register Addresses 4716 4616 b7 bob bO Timer A1 register Addresses 4916 48 6 Timer A3 register Addresses 4D16 4C16 Timer A4 register Addresses 4F16 4E16
525. unt siart bit is cleared to 0 At falling edge of PWM pulse Programmable I O port or trigger input PWM pulse output An undefined value is read out While counting is stopped When a value is written to the timer Aj register it is written to both of the reload register and counter While counting is in progress When a value is written to the timer Aj register it is written only to the reload register Transferred to the counter at the next reload time Note The trigger is generated with the count start bit 1 8 38 7721 Group User s Manual TIMER A 8 6 Pulse width modulation PWM mode b7 b6 b5 b4 b3 b2 bi bO EBENHBEEE Timer Aj mode register j 2 to 4 Addresses 5816 to 5A16 P eee me pem i PWM mode b4 b3 00 Writing 1 to count start register 0 1 TAjiN pin functions as a pro grammable I O port i Falling edge of TAjin pin s input signal Sus edge of EN pin s input signal b7 b6 00 f2 0 1 f16 ba 10 f64 11 f512 lt When operating as a 16 bit pulse width modulator gt b15 b8 b7 bO b7 bO Timer A3 register Addresses 4D16 4C16 Timer A4 register Addresses 4F16 4E16 x 15 to 0 These bits can be set to 000016 to FFFE 6e Undefined WO Assuming that the set value n the H level width of the PWM pulse output from the TAjour pin is expressed as follows l PWM pulse period TD l fi F
526. unt start bit is cleared to 0 Interrupt request occurrence timing When a counter underflow occurs TAjin pin s function Programmable I O port or gate input TAjour pin s function Programmable I O port or pulse output Head from timer Ai register Counter value can be read out Write to timer Ai register While counting is stopped When a value is written to the timer Ai register it is written to both of the reload register and counter While counting is in progress When a value is written to the timer Ai register it is written only to the reload register Transferred to the counter at the next reload timing 7721 Group User s Manual 8 9 TIMER A 8 3 Timer mode b7 b6 b5 b4 b3 b2 bi bd Jofofofojo Timer AO mode register Address 5616 Timer A1 mode register Address 57 6 L 2255 eee eee eee ee Count source select bits b7 b6 00 f2 01 f16 eee 5 eee eee 10 fe4 11 512 b7 b6 b5 b4 b3 b2 bli To T Tofo Timer Aj mode register j 2 to 4 Addresses 5816 to 5A16 b1 bO 00 Timer mode Pulse output function select bit 0 No pulse output TAjour pin functions as a programmable I O port 1 Pulse output TAjour pin functions as a pulse output pin b4 b3 00 No gate function 0 1 TAji pin functions as a prog rammable I O port Counter counts only while TAjin pin s input signal is at L level Counter counts only while TAjin pin s input signal is at H level Gate func
527. unts the count source The 8 bit pulse width modulator counts the 8 bit prescaler s underflow signal Note The above applies when the reload register s high order 8 bits n 0216 and low order 8 bits m 0216 and an external trigger falling edge of TAjin pin input signal is selected Fig 8 6 6 Operation example of 8 bit pulse width modulator 7721 Group User s Manual 8 45 TIMER A uul uul 8 6 Pulse width modulation PWM mode Dp 15 s si JeuBis ndul s uid Nify L Jo Bp GHurjye 19661 eui91x ue u uA s lildde e oqe au 91ON JOS SI n 8A MOU OU YOIYM ye Hulu oy uo spuedep H s206 A9 8s nd NMd Ou YoIUM 1e Buruy eui 0 00 Bunes aye 191sI 6 1 fy JoW eui 0 Jes SI enjeA Meqe ue ueuM D SIIq 8 19pJO MO 19 SI691 peojoJ JO slu luoo uJ 19181691 y 1 uun 0 18S S 20VO 19181691 y Jeuun 0 18S S 9 2000 19181691 y 1 uun 0 18S S rz0ro0 K i b 1 88 R o q i L7 gZ X I u X J qo x I Buljunoo 6ununoo i sueisoy sdolg i i i 8 4 M i i i 9LLO O O I I C LES Ln i I I c lt r NI ee eee 9170 o I I l I Q I I I I I I i O I I I I I I i 5 i l i i i D I I I I I I e z eee saa Iisa d x pp DE LL n a a a o I I I
528. upt request bit interrupt priority level select bits and processor interrupt priority level IPL are independent of one another they do not affect one another Interrupt requests are accepted only when the following conditions are satisfied Interrupt disable flag Il 0 Interrupt request bit 1 Interrupt priority level Processor interrupt priority level IPL 7721 Group User s Manual 1 7 INTERRUPTS 7 3 Interrupt control Table 7 3 1 Setting of interrupt priority level Interrupt priority level select bits Interrupt priority level Priority bo bl b O O Level 0 Interrupt disabled U x O 1 lear j Lw 1 o fiwa 4 0 O O1 1 jleelg 0 0 x O o jlevld o pO 1 evel S 9 teste LL NENNEN High Table 7 3 2 Interrupt enabled level corresponding to IPL contents IPL Enabled interrupt priority level 0 0 Enable level 1 and above interrupts 0 1 Enable level 2 and above interrupts 1 O Enable level 3 and above interrupts level 4 and above interrupts 0 o Enable level 5 and above interrupts O 1 Enable level 6 and level 7 interrupts 01 0 Enable only level 7 interrupt Lt oe Disable all maskable interrupts IPLo Bit 8 in processor status register PS IPLi Bit 9 in processor status register PS IPL2 Bit 10 in processor status register PS tit TI 2 D o D 7 8 7721 Group User s Manual INTERRUPTS 7 4
529. upt request until the execution of the interrupt routine is described below When an interrupt request is accepted the interrupt request bit of the accepted interrupt is cleared to 0 And then the interrupt processing starts from the cycle just after the completion of the instruction which was executed at accepting the interrupt request Figure 7 7 1 shows the sequence from acceptance of interrupt request to execution of interrupt routine After execution of an instruction at accepting the interrupt request is completed an INTACK Interrupt Acknowledge sequence is executed and a branch is made to the start address of the interrupt routine allocated in addresses O16 to FFFFie The INTACK sequence is automatically performed in the following order The contents of the program bank register PG just before performing the INTACK sequence are pushed onto stack The contents of the program counter PC just before performing the INTACK sequence are pushed onto stack The contents of the processor status register PS just before performing the INTACK sequence is pushed onto stack The interrupt disable flag I is set to 1 The interrupt priority level of the accepted interrupt is set into the processor interrupt priority level IPL The contents of the program bank register PG are cleared to 0016 and the contents of the interrupt vector address are set into the program counter PC Performing the INTACK sequence r
530. ut delay time BYTE L Data high order floating start delay time BYTE L Address middle order output delay time Address middle order output delay time Data low order output delay time Data low order floating start delay time Address high order output delay time Not lt O E D bd O r D gt gt gt rra mi mj 2 D OIO N 25 D c 2 em Q lo gt 9 gt Q lt io jio pic m d O Cc em Q D o lt 3 D lt O mmp Qo 0 Oo 4 gt ww w w BHE output delay time BLE output delay time R W output delay time output delay time Address low order hold time Address middle order hold time BYTE L Data high order hold time BYTE L Data high order floating release delay time BYTE L i BYTE H Address high order hold time Data low order hold time Data low order floating release delay time BHE hold time BLE hold time R W hold time E pulse width Data low order setup time after address stabilization Data low order setup time after rising of ALE Data high order setup time after address stabilization Data high order setup time after rising of ALE Z Z Z O O O mh eh s D O w ee O p D bd Y I alia O O amh D gt A D o o 3 Q Q T A Q D A y Q ct 3 D lt r D om
531. ut voltage from the ANo pin starts when the A D conversion start bit is set to 1 The A D conversion of the input voltage from the ANo pin is completed after 57 cycles of ab Then the contents of the successive approximation register conversion result are transferred to the A D register O For all of the selected analog input pins the A D conversion is performed The conversion result is transferred to the A D register i each time each pin is converted When step is completed the A D conversion interrupt request bit is set to 1 amp The A D conversion start bit is cleared to 0 and the A D converter stops operation When an external trigger is selected The A D converter starts operation for the input voltage from the ANo pin when the input level to the ADtra pin changes from H to L while the A D conversion start bit is 1 The A D conversion of the input voltage from the ANo pin is completed after 57 cycles of ab Then the contents of the successive approximation register conversion result are transferred to the A D register O For all of the selected analog input pins the A D conversion is performed The conversion result is transferred to the A D register i each time each pin is converted When step is completed the A D conversion interrupt request bit is set to 1 amp The A D conversion stops The A D conversion start bit remains set to 1 after the operation
532. utput data bit 3 ES Valid in pulse mode 0 Nothing is assigned undefined Note Use the LDM or STA instruction for writing to this register Pulse output data register 1 b7 b6 b5 b4 b3 b2 bi b0 Pulse output data register 1 Address 1Cie Nothing is assigned 9 RTP02 pulse output data bit 0 L level output Undefined WO Valid in pulse mode 1 1 H level output Note Use the LDM or STA instruction for writing to this register 7721 Group User s Manual 17 11 APPENDIX Appendix 3 Control registers A D control register b7 b6 b5 b4 b3 b2 bl b0 A D control register Address 1 E16 Ee ee 5 eee E Analog input select bits l Undefined RW Valid in one shot and repeat ANo selected modes Note 1 0 1 AN selected AN2 selected ANs selected Undefined RW AN selected ANs selected ANs selected Undefined RW AN7 selected Note 2 EN A D operation mode select bit 0 0 One shot mode 0 1 Repeat mode l Single sweep mode Repeat sweep mode ET trigger B E Tugger sergep UE External trader mG Bee ee tte ss 2 nl ane eee A D conversion start bit 0 Stop A D conversion 1 Start A D conversion 7 A D conversion frequency 0 fe divided by 4 RW UTR MAD select bit 1 f2 divided by 2 Notes 1 These bits are invalid in the single sweep and repeat sweep mode They may be either O or 1 2 When selecting an external trigger the AN7 pin cannot be used as an ana
533. vant to Timer A is described below Count source Data bus odd fo select bits o f 16 O Data bus even f64 o f512 Low order 8 bits A 4 High order 8 bits Timer mode Timer Ai reload Timer Ai reload register 16 16 One shot pulse mode PWM mode Timer mode Timer Ai Gate function B interrupt Timer Ai counter 16 Ai counter 16 request bit Polarity Event counter mode Countup Countdown TAj INO itchi switchin switching g Count start bit Always count down except for event counter mode Trigger Countdown p Up down bit O m Pulse output function select bit TAjour O i i 0 4 j 2 4 Fig 8 2 1 Block diagram of Timer A 7721 Group User s Manual 8 3 TIMER A 8 2 Block description 8 2 1 Counter and reload register timer Ai register Each of timer Ai counter and reload register consists of 16 bits Countdown in the counter is performed each time the count source is input In the event counter mode it can also function as an up counter The reload register is used to store the initial value of the counter When a counter underflow or overflow occurs the reload register s contents are reloaded into the counter A value is set to the counter and reload register by writing the value to the timer Ai register Table 8 2 1 lists the memory assignment of the timer Ai register The value written into the timer Ai register while
534. ve setting Don not set 000016 to the timer Aj register 7721 Group User s Manual 8 37 TIMER A 8 6 Pulse width modulation PWM mode 8 6 Pulse width modulation PWM mode In this mode the timer continuously outputs pulses which have an arbitrary width Refer to Table 8 6 1 Timers A2 to A4 can be used in this mode Figure 8 6 1 shows the structures of the timer Aj mode registers and timer Aj registers in the PWM mode Table 8 6 1 Specifications of PWM mode Item Count source Count operation PWM period H level width Count start condition Count stop condition Interrupt request occurrence timing TAjw pin s function TAjour pin s function Head from timer Aj register Write to timer Aj register Specifications f2 fie fes Or fs12 Countdown operating as an 8 bit or 16 bit pulse width modulator Reload register s contents are reloaded at rising edge of PWM pulse and counting continues A trigger generated during counting does not affect the counting lt 16 bit pulse width modulator gt e Is H level width s Period n Timer Aj register s set value 8 bit pulse width modulator m Timer Aj register low order 8 bits m 1 29 1 Period 7 s set value e l n m taf n Timer Aj register high order 8 HI ENEA MIU fi s bits set value When a trigger is generated Note Internal or external trigger can be selected by software When the co
535. vision ratio Count start condition Count stop condition Interrupt request occurrence timing TAjw pin s function TAjour pin s function Head from timer Aj register Write to timer Aj register Specifications External signal input to the TAjin pin The count source s valid edge can be selected from the falling edge and the rising edge by software Countup or countdown can be switched by external signal or software When a counter overflow or underflow occurs reload register s contents are reloaded and counting continues For countdown 1 n 1 n Timer Aj register s set value For countup 1 FFFF e n 1 When the count start bit is set to 1 When the count start bit is cleared to 0 When a counter overflow or underflow occurs Count source input Programmable I O port pulse output or countup countdown switch signal input Counter value can be read out While counting is stopped When value is written to the timer Aj register it is written to both of the reload register and counter While counting is in progress When a value is written to the timer Aj register it is written only to the reload register Transferred to the counter at the next reload time 7721 Group User s Manual TIMER A 8 4 Event counter mode Table 8 4 2 Specifications of event counter mode when using two phase pulse signal processing function Item Count source Count operation Division ratio Count s
536. wing explains these waveforms being compared with the basic operating waveform Refer to section 2 2 3 Operation of bus interface unit BIU 1 When fetching instructions into instruction queue buffer 2 When the instruction which is next fetched is located at an even address When the external data bus width is 16 bits the BIU fetches 2 bytes of the instruction at a time with waveform a When the external data bus width is 8 bits the BIU fetches only 1 byte of the instruction with the first half of waveform e When the instruction which is next fetched is located at an odd address When the external data bus width is 16 bits the BIU fetches only 1 byte of the instruction with waveform d When the external data bus width is 8 bits the BIU fetches only 1 byte of the instruction with the first half of waveform f When a branch to an odd address is caused by a branch instruction etc with the 16 bit external data bus width the BIU first fetches 1 byte of the instruction with waveform d and after that fetches instructions in a unit of 2 bytes with waveform a When reading or writing data from and to memories or I O devices When accessing 16 bit data which begins at an even address waveform a or e is applied When accessing 16 bit data which begins at an odd address waveform b or f is applied amp When accessing 8 bit data at an even address waveform c or the first half of e is applied When acce
537. x 3 Control registers The control registers allocated in the SFR area are shown on the following pages Below is the structure diagram for all registers x b7 b6 b5 b4 b3 b2 bi x Blank 2 C T Undefined S3 RW RO WO XXX register Address XX16 Lu n e n ER cpm TEC E 3 Select bit 0 m Li messa m 1 9 sw iw Noting isassigned r 4 Set to 0 or 1 according to the usage Set to 0 at writing Set to 1 at writing Invalid depending on the mode or state It may be 0 or 1 Nothing is assigned 0 immediately after reset 1 immediately after reset Undefined immediately after reset It is possible to read the bit state at reading The written value becomes valid It is possible to read the bit state at reading The written value becomes invalid Accordingly the written value may be 0 or 1 The written value becomes valid It is impossible to read the bit state The value is undefined at reading However when 0 is at reading is indicated in the Function or Note column the bit is always 0 at reading See 4 above It is impossible to read the bit state The value is undefined at reading However when O is at reading is indicated in the Function or Note column the bit is always 0 at reading See 4 above
538. y error 12 4 Absolute accuracy and differential non linearity error The A D converter s accuracy is described below Refer to section Appendix 12 3 A D converter standard characteristics also 12 4 1 Absolute accuracy The absolute accuracy is the difference expressed in the LSB between the actual A D conversion result and the output code of an A D converter with ideal characteristics The analog input voltage when measuring the accuracy is assumed to be the mid point of the input voltage width that outputs the same output code from an A D converter with ideal characteristics For example when Vereer 5 12 V 1 LSB width is 20 mV and 0 mV 20 mV 40 mV 60 mV 80 mV are selected as the analog input voltages The absolute accuracy 3 LSB indicates that when the analog input voltage is 100 mV the output code expected from an ideal A D conversion characteristics is 005 6 however the actual A D conversion result is between 00216 to 00816 The absolute accuracy includes the zero error and the full scale error The absolute accuracy is degraded when Vrer is lowered Any of the output codes for analog input voltages from Vner to AVcc is FFte Output code A D conversion result OB16 OA16 0916 4 4 4 F d FK 4 a 4 9 r d MP 4 4 Fil 4 4 0816 i 4 J Ideal A D conversion 0716 a characteristics 0616 0516 0416 0316 0216 0116 0016 40 60 80 100 120 1
539. z 390 625 kHz 1 1 15625 Hz 31250 Hz 48 8281 kHz 7721 Group User s Manual TIMER B 9 3 Timer mode 9 3 3 Operation in timer mode When the count start bit is set to 1 the counter starts counting of the count source When a counter underflow occurs the reload register s contents are reloaded and counting continues The timer Bi interrupt request bit is set to 1 at the underflow in The interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software Figure 9 3 3 shows an example of operation in the timer mode n Reload register s contents FFFF 16 Starts counting Restarts counting I a I I I I I Counter contents Hex 000016 Set to 1 by software Cleared to 0 by software Set to 1 by software Count start bit Timer Bi interrupt request bit fi frequency of count source A A f2 fte fea f512 Cleared to 0 when interrupt request is accepted or cleared by software Fig 9 3 3 Example of operation in timer mode 9 12 7721 Group User s Manual TIMER B 9 3 Timer mode Precautions for timer mode While counting is in progress by reading the timer Bi register the counter value can be read out at any timing However if the timer Bi register is read at the reload timing shown in Figure 9 3 4 the value FFFF 16 is read out If reading is perform

7721 Group USER`S MANUAL

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