User Manual - General Standards Corporation
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1. 4 3 6 Discrete Data Input Register DDIR 0x68 32 RO This register reports the logic state of the signals on all 25 port bits If a bit is configured as an input then the reported value is per the state induced by the attached device If a bit is programmed for output then the reported value is the value programmed from the DDOR 18 General Standards Corporation Phone 256 880 8787 DIO24 User Manual Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Field DI PORTC Default 0 0 0 0 0 0 0 0 0x00 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Field PORTB PORTA Default 0x00 0x00 Bit Field Description 31 24 Reserved 24 DI Dedicated Input This is the input value for the state of the Dedicated Input pin 23 16 PORTC Port C This is the input value for the state of the Port C pins 15 8 PORTB Port B This is the input value for the state of the Port B pins 7 0 PORTA Port A This is the input value for the state of the Port A pins 19 General Standards Corporation Phone 256 880 8787 DIO24 User Manual 5 PLX PCI9080 Registers These registers are provided by the PCI interface chip which is the PLX PCI9080 Since many of the PCI9080 features are not utilized in on the DIO24 it is beyond the scope of this document to duplicate the PCI9080 User s Manual2. Vi 5 Nn o zg Pin 49 Pi Y OO OO oo OO E Connector oo Pl ela oo OO OO OO G ER Dr Key oo OO OO OO OO OO OO OO Pin 1 Pin 2 Table 3 External I O connector P1 pins and descriptions Pin No Cable Signal Name Pin No Cable Signal Name 1 PORT A DO 26 PORT B DA 11 General Standards Corporation Phone 256 880 8787 DIO24 User Manual 2 PORT A DO 27 PORT B D5 3 PORTA DI 28 PORT B DS 4 PORT A D1 29 PORT B D6 5 PORT A D2 30 PORT B D6 6 PORT A D2 31 PORT B D7 7 PORT A D3 32 PORT B D7 8 PORT A D3 33 PORT C D0 9 PORT A D4 34 PORT C DO 10 PORT A D4 35 PORT C DI 11 PORT A D5 36 PORT C D1 12 PORT A D5 37 PORT C D2 13 PORT A D6 38 PORT C D2 14 PORT A D6 39 PORT C D3 15 PORT A D7 40 PORT C D3 16 PORT A D7 41 PORT C D4 17 PORT B DO 42 PORT C D4 18 PORT B DO 43 PORT C D5 19 PORT B DI 44 PORT C DS 20 PORT B D1 45 PORT C D6 21 PORT B D2 46 PORT C D6 22 PORT B D2 47 PORT C D7 23 PORT B D3 48 PORT C D7 24 PORT B D3 49 Dedicated INPUT Clk Out 25 PORT B D4 50 Dedicated INPUT Clk Out 2 3 Jumpers 2 3 1 Jumper Block J2 Jumper block J2 is a 4x2 header that accommodates four 2 pin jumpers Pin one is at the upper left and pin eight is at the lower right The jumper
3. The following reference material may be of particular benefit in using the DIO24 The specifications provide the information necessary for an in depth understanding of the specialized features implemented on this board e The applicable DIO24 Device Driver User Manuals from General Standards Corporation e The PCI 9080 PCI Bus Master Interface Chip data handbook from PLX Technology Inc PLX Technology Inc 870 Maude Avenue Sunnyvale California 94085 USA 1 800 759 3735 http www plxtech com e EJA 422 A Electrical Characteristics of Balanced Voltage Digital Interface Circuits EIA order number EIA RS 422A e EJA 485 Standard for Electrical Characteristics of Generators and Receivers for Use in Balanced Digital Multipoint Systems EIA order number EIA RS 485 e PCI Local Bus Specification Revision 2 1 June 1 1995 PCI Special Interest Group NE 2575 Kathryn Street 17 Hillsboro OR 97124 http www pcisig com EIA Standards and Publications are available from 8 General Standards Corporation Phone 256 880 8787 DIO24 User Manual GLOBAL ENGINEERING DOCUMENTS 15 Inverness Way East Englewood CO 80112 Phone 800 854 7179 http global ihs com 9 General Standards Corporation Phone 256 880 8787 DIO24 User Manual 2 Physical Description This section presents a physical description of the DIO24 and its features Refer to Figure 2 The DIO24 is a simple 25 bit discrete I O interface board It c
4. Only those registers that clarify DIO24 details are given here Please refer to the PCI9080 User s Manual see Related Publications for more detailed information 5 1 PCI Configuration Registers NOTE Most PCI configuration registers are initialized by a system s BIOS or firmware at boot time Additionally information on PCI configuration registers is normally of more use to device driver writers then to application writers Table 6 Register map of the PCI Configuration Registers PCI Local CFG Offset PCI Local Register Name Value after Addr Addr Writable Reset 0x10 0x10 Y PCI Base Addr 0 for Memory Mapped Local Runtime DMA 0x00000000 Registers PCIBARO 0x14 0x14 Y PCI Base Addr 1 for I O Mapped Local Runtime DMA 0x00000001 Registers PCIBAR1 PCI Base Addr 2 for Local Addr Space 0 PCIBAR2 0x00000000 Unused 0x2C 0x2C Local Subsystem ID Subsystem Vendor ID PCI Base Address to Local Expansion ROM Unused 0x00000000 Y 7 0 Local Max_Lat Min_Gnt Interrupt Pin Interrupt Line 0x00000100 5 1 1 PCI Configuration ID Register Offset 0x00 Reset 0x908010B5 D15 0 Vendor ID 0x10B5 PLX Technology D31 16 Device ID 0x9080 PCI9080 5 1 2 PCI Command Register Offset 0x04 Reset 0x0017 DO VO Space A l allows the device to respond to I O space accesses D1 Memory Space A l allows the device to respond to memory space accesses D2 PCI Master Enable A l allows the device to b
5. Register for Memory Access to Local Runtime DMA Register 22 5 1 10 PCI Base Address Register for I O Access to Local Runtime DMA Register 23 5 1 11 PCI Base Address Register for Memory Access to Local Address Space U N 23 5 1 12 PCI Subsystem Device Vendor ID Register 23 341 13 PCT Interrupt Line Register tere eect sock Maaco deed hoses ann Eeer Bn Be 23 5 114 RCIInterrupt Pin Regist ci a ee Me ias 23 Sle L PCT MinGnt Register voc Eeer ee e e Een ae ee 24 SL lp RCI Max at Register Sgr ee ee Rese Beene ege Ie RE eA 24 5 2 Local Configuration Regist n 24 5 2 1 Local Address Space 0 Range Register for PCI to Local Bus 24 5 2 2 Mode Arbitration Registr cvesaceiee i eii E ei 25 5 2 3 Big Little Endian Descriptor Register ccccecccsssessesssessceescesecesecesecesecnaecaaecaeecaeecaeeeaeseeeseeenreneeenseeneeaees 25 5 2 4 Local Address Space 0 Expansion ROM Bus Region Descriptor Register 25 5 3 Runtime Resistersy EE 26 5 3 1 Interrupt Control Status ii idad 26 5 3 2 Serial EEPROM Control PCI Command Codes User I O Control Init Control Register 27 5 3 3 PCI Permanent Configuration ID Register ccccecccesecsseesseeeeeeeceeeceseecaecseecseecaeecaeeeaeeeeeeeeeeeeneeneeneenaees 27 5 3 4 PCI Permanent Revision ID Register 27 DMA Rea aaa 28 2 3 Messaging Queue RESisters cuota a ebe 28 Ss Lee ee EE EE EE 29 5 General Standards Corporation Phone 256 880 8787 DIO24 User
6. access is given as it means that the access details are given with the register s description 4 1 PCI Configuration Registers The PCI Configuration Registers are built into the DIO24 s PCI interface chip which is the PLX PCI9080 This set of registers is governed by the PCI bus specification Access to these registers is via PCI bus cycles and is beyond the scope of document Read the details of these registers before using them The PCI registers are described in section 5 1 4 2 PLX PCI9080 Internal Registers These registers are provided as a part of the feature set for this PCI interface chip The chip is hardwired so that PCI registers PCIBARO and PCIBARI identify where these internal registers are located These registers are set during the system s PCI enumeration and initialization process The registers occupy a block of 256 contiguous bytes accessible as bytes words or long words PCIBARO gives the block s base address in memory space PCIBAR1 gives the block s base address in I O space Read the details of these registers before using them The PCI9080 internal registers are described beginning in section 5 2 4 3 GSC Specific Registers These registers are provided as a part of the feature set for the DIO24 The location and size of the GSC specific register block is determined by accessing PCI registers PCIBAR2 The address is generally determined by the BIOS during the boot up process The size of the block is
7. block is located in the lower right corner of the board as illustrated in Figure 2 A more detailed view is given in Figure 4 below In the default factory configuration jumpers are installed on all four horizontal jumper pairs Figure 4 Jumper block J2 Jumper Block J2 uc O 2 O Omd O Op O O 8 QA UU 12 General Standards Corporation Phone 256 880 8787 DIO24 User Manual 2 3 1 1 PLX Default Configuration J2 1 2 This jumper connects the PCI interface chip the PLX PCI9080 to the On board Configuration EEPROM Serial EEPROM U42 When the jumper is installed the PCI interface chip will initialize some of its registers from the content of the EEPROM This initialization is necessary for correct PCI configuration If the EEPROM becomes corrupted the invalid parameters can prevent proper host and DIO24 operation Removing this jumper will force the PCI interface chip into a default configuration that should allow PCI configuration to proceed This will permit proper host booting and allow for reprogramming of the EEPROM In the default factory configuration this jumper is installed WARNING This jumper should only be removed following factory consultation The board will not function correctly if this jumper is removed 2 3 1 2 FPGA Reload J2 3 4 This jumper connects the PCI reset signal to the FPGA chip When the jumper is installed an FPGA reload o
8. specified by the DIO24 as 512 bytes PCIBAR2 is configured to give the base address in memory space The following gives details of the GSC specific registers All offsets are given relative to the register block s base address Table 5 Register map of the GSC specific registers Offset Size Access Register Name 0x00 32 RO Firmware Revision Register FRR 0x04 32 RW Board Control Register BCR 0x08 32 RO Board Status Register BSR 0x60 32 RW T O Control Register IOCR 0x64 32 RW Discrete Data Output Register DDOR 0x68 32 RO Discrete Data Input Register DDIR All other locations within the register block are reserved 4 3 1 Firmware Revision Register FRR 0x00 32 RO This register gives revision and type information for the board and the firmware Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field SID Default 1 0 0 0 0 0 0 0 0x0B 16 General Standards Corporation Phone 256 880 8787 DIO24 User Manual Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field PR FR Default 0x02 A X IX xX xX xX IK IK Bit Field Description 31 24 Reserved 23 16 SID Sub ID This identifies the board s type within the product family 15 8 PR PCB Revision This identified the board s PCB re
9. 00 General Standards HPDI32 used by PCI DIO24 GD1 5 1 13 PCI Interrupt Line Register Offset 0x3C Reset 0x00 D7 0 Interrupt Line Routing Value Indicates which input of the system interrupt controller s to which the interrupt line of the device is connected 5 1 14 PCI Interrupt Pin Register Offset 0x3D Reset 0x01 D7 0 Interrupt Pin register Indicates which interrupt pin the device uses O1 INTA Note PCI 9080 supports only one PCI interrupt pin INTA 23 General Standards Corporation Phone 256 880 8787 DIO24 User Manual 5 1 15 PCI Min_Gnt Register Offset 0x3E Reset 0x00 D7 0 Minimum Grant Specifies the minimum burst period the device needs assuming a clock rate of 33 MHz Value is in 250 nsec increments A 0 indicates no stringent requirement 5 1 16 PCI Max_Lat Register Offset 0x3F Reset 0x00 D7 0 Maximum Latency Specifies the maximum burst period the device needs assuming a clock rate of 33 MHz Value is in 250 nsec increments A 0 indicates no stringent requirement 5 2 Local Configuration Registers The Local Configuration registers give information on the Local side implementation Since Local Expansion ROM Local Address Space 1 and Direct Master accesses are not implemented on the DIO24 the descriptions of these registers have been omitted Most of the Local Configuration Registers are preloaded from the serial EEPROM at system reset Table 7 Register map of the Local Conf
10. 1 18 Reserved User Jumper 1 This reports the status of User Jumper 1 which is jumper block J2 pins 7 8 If a 17 UJ1 jumper is installed the value is one The value is zero if a jumper is not installed In the factory configuration the jumper is installed User Jumper 0 This reports the status of User Jumper 0 which is jumper block J2 pins 5 6 If a 16 UJO jumper is installed the value is one The value is zero if a jumper is not installed In the factory configuration the jumper is installed 15 0 Reserved 17 General Standards Corporation Phone 256 880 8787 DIO24 User Manual 4 3 4 UO Control Register OCH 0x60 32 RW This register is used to configure the I O ports and bits as either inputs or outputs Setting a bit to one programs the port bit as an output Setting a bit to zero programs the port bit as an input Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field CO1 PC7 PC6 PCS PC4 PC3 PC2 PC1 PCO PB PA Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Field Description 31 11 Reserved 10 CO1 Clock Out 1 This controls the enable of Clock Out cable signal 9 PC7 Port C Pin 7 This controls the direction of Port C bit 7 8
11. DIO24 PCI DIO24 PMC DIO24 PCI DIO24 GD1 User Manual Manual Revision June 12 2002 General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Fax 256 880 8788 URL www generalstandards com E mail sales generalstandards com E mail support generalstandards com DIO24 User Manual 2 General Standards Corporation Phone 256 880 8787 DIO24 User Manual Preface Copyright 2002 General Standards Corporation Additional copies of this manual or other literature may be obtained from General Standards Corporation 8302A Whitesburg Dr Huntsville Alabama 35802 Phone 256 880 8787 FAX 256 880 8788 URL www generalstandards com E mail sales generalstandards com General Standards Corporation makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Although extensive editing and reviews are performed before release to ECO control General Standards Corporation assumes no responsibility for any errors that may exist in this document No commitment is made to update or keep current the information contained in this document General Standards Corporation does not assume any liability arising out of the application or use of any product or circuit described herein nor is any license conveyed under any patent rights or any rights of others General Standards Corp
12. EPROM U4 2 eessen ge SEA 13 2 4 2 Termination Resistors RP1 RP7 cccccccecccesssececescorseceeceessosececessccueecescecessostecesessteecessecevesseeeessssecesees 13 A Eege SE NOS 14 2 3 1 Loop Back TestCablenii eat 14 3 OQ A LD SA Eet 15 KEE 15 33 10 Programming naaa les 15 34 10 Reads add Writes EENS EE EES ENEE EE de 15 4 Regi 16 A A O O 4 1 PCI Configuration Register iia as E E E aras 16 4 2 PLX PCI9080 Internal Registers ouer sede setsecdeceedacsedvacnddvdeedsuetceaceddveevdesieciacesdedsaceleecoteecdvssrtess 16 4 3 GSC Dette RESIStES ege Eed a E E de 16 4 3 1 Firmware Revision Register FRR 0x00 32 RO 16 4 3 2 Board Control Register BCR 0X04 32 RW 17 4 3 3 Board Status Register BSR 0X08 32 RO ron n corn nn nr nnnronnrnnnrnn rra 17 4 3 4 I O Control Register IOCR 0X60 32 RW 18 4 3 5 Discrete Data Output Register DDOR 0x64 32 RWi nono nronnronncnnncnn ninos 18 4 3 6 Discrete Data Input Register DDIR 0x68 32 RO 18 4 General Standards Corporation Phone 256 880 8787 DIO24 User Manual a PLA PCI9080 Register cia A a a A 5 1 PCT Configuration Register ii d as 20 5 1 1 PCT Configuration ID Regist 20 5 1 2 PCI Command Regist td 20 KEE ON E EIERE 21 5 1 4 PCT Revision ID RE 22 5 15 PEI Class Code Register tdi 22 5 1 6 PCT Cache Line Size Read td 22 5 1 7 PCT Latency Timer Regist ted 22 5 1 8 PCT Header Type Register ui dad 22 5 1 9 PCI Base Address
13. Manual Table of Figures Figure 1 DIO24 simple block diagram cecccsseesseeeesseeesceeceseceseceaecaecsaecsaecseeeseceaeeaeeeeseesseeeaecesecaeceaecsaeceeeeeenes 7 Figure 2 An illustration of a PCI DIO24 nennen sinici E E E AEE a E i i 10 Figure 3 External T O Connector Plinio 11 Figure 4 Jumper block Ti ii 12 Table of Tables Table 1 Register level identification of the DIO24 coco cococococococonononoconcnnnonnonnnonncnnnonnncn nor nn corr nnn ron n ran ran rr nn rn nnnnannns 10 Table 2 Register level identification of the PCI DIO24 GDL cooonccnoccnoconononononononnconnonnnconocononnnronnronnrnnnrnn nr nnrrnnnnnnrnanns 11 Table 3 External I O connector P1 pins and descriptions ccceeccesccessceseceseceecseecseeeneeeeeeeeeeeeeeseenseeeseenaecnseeeeeseeeas 11 Table 4 Register level identification of the DIO24 cococccocococococonononccononnnonononnnonnonnncnnnnnn nn rincon ron nronn ran ran rr nn rr rnnrannnns 15 Table 5 Register map of the GSC specific registers ccccceescessceescesecesecsecececseecaeeeaeeneceeeseeseeeeseeaeeaecnaeceeeeeeneeses 16 Table 6 Register map of the PCI Configuration Registers c ccsccesccsssceseesseceecseeeneeneceeeeseeeseeeseceseeaecaeceeeaeeeneenss 20 Table 7 Register map of the Local Configuration Register 24 Table 8 Register map of the Runtime Register 26 6 General Standards Corporation Phone 256 880 8787 DIO24 User Manual 1 Introduction 1 1 Purpose The pur
14. Memory Write Command Code for Direct Master Unused General Purpose Output Unused General Purpose Input Unused Reserved Serial EEPROM clock for Local or PCI bus reads or writes to Serial EEPROM Serial EEPROM chip select Write bit to serial EEPROM Read serial EEPROM data bit Serial EEPROM present Reload Configuration Registers PCI Adapter Software Reset Local Init Status A l indicates Local initialization done 5 3 3 PCI Permanent Configuration ID Register PCI 0x70 Reset 0x10B59080 D15 0 D31 16 Permanent Vendor ID 0x10B5 Permanent Device ID 0x9080 5 3 4 PCI Permanent Revision ID Register PCI 0x74 D7 0 Permanent Revision ID 27 General Standards Corporation Phone 256 880 8787 DIO24 User Manual 5 4 DMA Registers The DMA Registers are not used on the DIO24 5 5 Messaging Queue Registers The Messaging Queue Registers are not used on the DIO24 28 General Standards Corporation Phone 256 880 8787 DIO24 User Manual Document History Revision Description December 3 2001 Initial Release December 11 2001 Added Plug and Play information February 13 2002 Added system resource and loop back cable information October 23 2002 Added information about the new subsystem ID of 0x2606 29 General Standards Corporation Phone 256 880 8787
15. PC6 Port C Pin 6 This controls the direction of Port C bit 6 7 PC5 Port C Pin 5 This controls the direction of Port C bit 5 6 PC4 Port C Pin 4 This controls the direction of Port C bit 4 5 PC3 Port C Pin 3 This controls the direction of Port C bit 3 4 PC2 Port C Pin 2 This controls the direction of Port C bit 2 3 PC1 Port C Pin 1 This controls the direction of Port C bit 1 2 PCO Port C Pin 0 This controls the direction of Port C bit 0 1 PB Port B This controls the direction of all eight Port B bits 0 PA Port A This controls the direction of all eight Port A bits 4 3 5 Discrete Data Output Register DDOR 0x64 32 RW This register holds the data that will appear on I O pins programmed as output All 24 bits are latched so that reading the register returns the last programmed value Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field PORTC Default 0 0 0 0 0 0 0 0 0x00 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field PORTB PORTA Default 0x00 0x00 Bit Field Description 31 24 Reserved 23 16 PORTC Port C This is the output value for Port C pins programmed as output 15 8 PORTB Port B This is the output value for Port B when programmed as output 7 0 PORTA Port A This is the output value for Port A when programmed as output
16. andards Corporation Phone 256 880 8787 DIO24 User Manual 5 1 4 PCI Revision ID Register Offset 0x08 D7 0 Revision ID The silicon revision of the PCI9080 5 1 5 PCI Class Code Register Offset 0x09 0B Reset 0x068000 D7 0 Register level programming interface 0x00 Queue Ports at 0x40 and 0x44 0x01 Queue Ports at 0x40 and 0x44 Int Status and Int Mask at 0x30 and 0x34 D15 8 Sub class Code 0x80 Other bridge device D23 16 Base Class Code 0x06 Bridge Device 5 1 6 PCI Cache Line Size Register Offset Ox0C Reset 0x00 D7 0 System cache line size in units of 32 bit words 5 1 7 PCI Latency Timer Register Offset Ox0D Reset 0x00 D7 0 PCI Latency Timer Units of PCI bus clocks the amount of time the PCI9080 as a bus master can burst data on the PCI bus 5 1 8 PCI Header Type Register Offset OxOE Reset 0x00 D6 0 Configuration Layout Type 0 D7 Header Type 0 5 1 9 PCI Base Address Register for Memory Access to Local Runtime DMA Registers Offset 0x010 Reset 0x00000000 DO Memory Space Indicator A 0 indicates register maps into Memory space Note Hardcoded to 0 D2 1 Location of Register 00 Locate anywhere in 32 bit memory address space Note Hardcoded to 0 D3 Prefetchable Note Hardcoded to 0 D7 4 Memory Base Address Default Size 256 bytes Note Hardcoded to 0 D31 8 Memory Base Address Memory base address for access to Local Runtime and DMA regis
17. ansceivers The transceivers are the 25 small gray outlined squares in Figure 2 running down the center of the board If the transceivers have four unpopulated solder pads to their right then the transceivers are RS485 style The GD1 variation of the DIO24 is identical to the base version except for the PCI identification register values given in the below table Table 2 Register level identification of the PCI DIO24 GD1 Register Value Description PCIIDR 0x908010B5 The lower 16 bits is the Vendor ID and identifies PLX Technology The upper 16 bits is the Device ID and identifies the chip is a PCI9080 PCISVID 0x10B5 This identifies the PCISID as being assigned by PLX Technologies PCISID 0x2400 This identifies the board as a member of the HPDI32 product series FRR OxXXOBXXXX The value in the third byte identifies this as a DIO24 2 2 Connectors 2 2 1 External UO Connection P1 Connector Pl is the external I O connector that gives the user access to the board s I O pins This is a 50 pin connector that includes two pins for each of the board s 25 I O lines Pin one is at the lower right and pin 50 is at the upper left The connector is manufactured by Tyco and has the part number AMP 1 103311 0 The part number of the mating connector is AMP 1 746285 Figure 3 shows the connector as seen from the left side of Figure 2 The pin assignments are given in Table 3 Figure 3 External I O connector P1
18. ccurs from EPROM U42 with each PCI reset in compliance with the PCI spec In the default factory configuration this jumper is installed WARNING This jumper should only be removed following factory consultation 2 3 1 3 User Jumper 0 J2 5 6 This jumper is provided for end user use The jumper may be installed or removed at the user s discretion and may be read by examining bit 16 of the Board Status Register described later If the jumper is installed the bit returns a one 1 If the jumper is removed the bit returns a zero 0 In the default factory configuration this jumper is installed One potential use of the jumper is to aid in distinguishing individual boards when multiple DIO24 boards are installed 2 3 1 4 User Jumper 1 J2 7 8 This jumper is provided for end user use The jumper may be installed or removed at the user s discretion and may be read by examining bit 17 of the Board Status Register described later If the jumper is installed the bit returns a one 1 If the jumper is removed the bit returns a zero 0 In the default factory configuration this jumper is installed One potential use of the jumper is to aid in distinguishing individual boards when multiple DIO24 boards are installed 2 4 Components 2 4 1 FPGA EPROM U42 This EPROM contains the firmware for the DIO24 FPGA The EPROM is located towards the center of the board s right edge Pin one is at the upper left The EPROM may be replaced with fact
19. ed Input The same procedure applies to all remaining pins 14 General Standards Corporation Phone 256 880 8787 DIO24 User Manual 3 Operation This section gives a brief description of the operation of the DIO24 3 1 Identification The DIO24 can be uniquely identified by examining the following list of registers Full register descriptions are given later in this document Table 4 Register level identification of the DIO24 Register Value Description PCIIDR 0x908010B5 The lower 16 bits is the Vendor ID and identifies PLX Technology The upper 16 bits is the Device ID and identifies the chip is a PCI9080 PCISVID 0x10B5 This identifies the board as a product of General Standards Corporation PCISID 0x2606 This identifies the board as a member of the DIO24 product series FRR OxXXOBXXXX The value in the third byte identifies this as a DIO24 NOTE The PCI DIO24 GD1 variation of the DIO24 has different identification register values as described in Table 2 3 2 Reset The board is reset by writing a one to the Reset bit of the GSC Board Control Register The operation completes within the given register write cycle A reset programs all 1 O pins as inputs and programs the data output latches to zero 3 3 UO Programming The I O pins are programmed via the I O Control Register One bit controls Port A another bit controls Port B and eight additional bits individually control the eigh
20. ehave as a PCI bus master Note This bit must be set for the PCI 9080 to perform DMA cycles D3 Special Cycle Not Supported D4 Memory Write Invalidate 20 General Standards Corporation Phone 256 880 8787 D5 D6 D7 Ds D9 DIO24 User Manual A 1 enables memory write invalidate VGA Palette Snoop Not Supported Parity Error Response 0 indicates that a parity error is ignored and operation continues A 1 indicates that parity checking is enabled Wait Cycle Control Controls whether the device does address data stepping A 0 indicates the device never does address data stepping Note Hardcoded to 0 SERR Enable A 1 allows the device to drive the SERR line Fast Back to Back Enable Indicates what type of fast back to back transfers a Master can perform on the bus A 1 indicates fast back to back transfers can occur to any agent on the bus A 0 indicates fast back to back transfers can only occur to the same agent as the previous cycle D15 10 Reserved 5 1 3 PCI Status Register Offset 0x06 Reset 0x0280 D5 0 D6 D7 D8 D10 9 D11 D12 D13 D14 D15 Reserved User Definable Features Supported A 1 indicates UDF are supported Note User Definable Features are Not Implemented Fast Back to Back Capable A l indicates the adapter can accept fast back to back transactions Master Data Parity Error Detected A 1 indicate
21. es bit is included in address decode Local Address Space 0 value OxFFFFF000 maps a 4kbyte range Since entire Local Address Space can be mapped into 4kb range the remap register is not used 5 2 2 Mode Arbitration Register PCI 0x08 D7 0 D8 15 D16 D17 D18 D20 19 D21 D22 D23 D24 D25 D26 D27 D28 D29 D31 30 Local bus Latency Timer Unused Local bus Pause Timer Unused Local bus Latency Timer Enable Unused Local bus Pause Timer Enable Unused Local bus BREQ Enable Unused DMA Channel Priority 00 Rotational priority 01 Channel 2 priority 10 Channel 1 priority 11 Reserved Local bus direct slave give up bus mode A value of 1 indicates local bus will be released when PCI9080 write FIFO empty or read FIFO full Direct slave LLOCKo Enable Unused PCI Request Mode PCI Rev 2 1 Mode PCI Read No Write Mode PCI Read with Write Flush Mode Gate the Local Bus Latency Timer with BREQ Unused PCI Read No Flush Mode Reads Device Vendor ID or SubDevice SubVendor ID Reserved 5 2 3 Big Little Endian Descriptor Register PCI 0x0C Since local bus is little endian all bits should be left zero 5 2 4 Local Address Space 0 Expansion ROM Bus Region Descriptor Register PCI 0x18 Reset 0x40030143 D1 0 D5 2 D6 D7 Memory Space 0 Local Bus Width 11 indicates 32 bit local bus Memory Space 0 Internal Wait States A 0 indicates no wait states required Memory Space 0 Ready I
22. iguration Registers PCI Local CFG Offset PCULocal Register Name Value after Addr Addr Writable Reset Y Range for PCI to Local Address Space 0 OxFFFFF000 Local Base Address Remap for PCI to Local Address Space 0 0x00000000 Unused A ROM and BREQo control Unused 0x18 0x98 Y Local Bus Region Descriptions for PCI Local Accesses 0x00000000 Ox1C 0x9C y Range for Direct Master to PCI Unused 0x00000000 0x20 0xA0 y Local Base Address for Direct Master to PCI Memory Unused 0x00000000 a Local Base Address for Direct Master to PCI Memory IO CFG 0x00000000 Unused PCI Base Address Re map for Direct Master to PCI Unused 0x00000000 0x2C OxAC Y PCI Configuration Address Register for Direct Master to PCI 0x00000000 IO CFG Unused 0x170 Range for PCI to Local Address Space 1 Unused 0x00000000 Unused Accesses Unused 5 2 1 Local Address Space 0 Range Register for PCI to Local Bus PCI 0x00 Reset OxFFFFF000 24 General Standards Corporation Phone 256 880 8787 DO D3 D31 4 DIO24 User Manual Memory Space Indicator A 0 indicates register maps into Memory space Location of register if memory space Location values 00 Locate anywhere in 32 bit memory address space Prefetchable A 0 indicates reads are not prefetchable Specifies which PCI address bits will be used to decode a PCI access to Local Address Space 0 A 1 indicat
23. k output 1 4 1 HOST Interface The PCI interface on the DIO24 is implemented using the PCI9080 from PLX Technology The PCI interface is compliant with the 5V 33 MHz PCI Specification 2 1 Although the PCI9080 supports DMA data transfers DMA is not supported on this product 1 4 2 External UO Interface 1 4 2 1 RS485 422 Interface This interface provides for synchronous bus clock speeds up to 26MHz 104 Mbytes per sec This is the standard interface option 7 General Standards Corporation Phone 256 880 8787 DIO24 User Manual 1 4 2 3 LVDS This interface iS available 1 4 2 4 TTL This interface is planned Contact the sales department for availability 1 5 Ordering Information The DIO24 is designed to fit a variety of high speed digital interface needs and has several options that must be specified when being ordered Please consult our sales department with your application requirements in order to determine the correct ordering options 1 6 Custom Applications Although the DIO24 provides extensive flexibility to accommodate many user applications custom interfaces exist which may not conform to current DIO24 interface options General Standards Corporation has worked with many customers to provide customized versions of the DIO24 and other GSC products Please consult our sales department with your specifications to inquire about a custom application 1 7 Reference Material
24. nput Enable A l indicates Local Ready input enabled Memory Space 0 Bterm Input Enable Unused 25 General Standards Corporation Phone 256 880 8787 DIO24 User Manual D8 Memory Space 0 Prefetch Disable Unused D9 Expansion ROM Space Prefetch Disable Unused D10 Read Prefetch Count Enable Unused D14 11 Prefetch Counter Unused D15 Reserved D17 16 Expansion ROM Space Local Bus Width Unused D21 18 Expansion ROM Space Internal Wait States Unused D22 Expansion ROM Space Ready Input Enable Unused D23 Expansion ROM Space Bterm Input Enable Unused D24 Memory Space 0 Burst Enable D25 Extra Long Load from Serial Enable D26 Expansion ROM Space Burst Enable Unused D27 Direct Slave PCI Write Mode D28 31 PCI Target Retry Delay Clocks 5 3 Runtime Registers The Runtime registers consist of mailbox registers doorbell registers and a general purpose control register The mailbox and doorbell registers are not used on the DIO24 Table 8 Register map of the Runtime Registers PCI Local CFG Offset PCI Local Register Name Value after Addr Addr Writable Reset 0x40 Ont 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 Ox6C 0x70 0x74 0x78 5 3 1 Interrupt Control Status PCI 0x68 Reset 0x00000000 DO Enable Local bus LSERR Unused D1 Enable Local bus LSERR on a PCI parity error Unused D2 Generate PCI Bus SERR D3 Mailbox Interrupt Enable Unused D7 4 Reserved D8 PCI In
25. ontains a PCI based host connection and an RS485 external I O interface A LVDS version is also available Figure 2 An illustration of a PCI DIO24 P1 1 RP 1 1 JRP2 1 RP5 1 RP3 1 RP6 1 RP4 1 RP7 2 1 Identification This subsection gives details on how to identify the different versions of the DIO24 2 1 1 PMC PCI DIO24 The base version of the board no suffix after the DIO24 model number includes RS485 transceivers The transceivers are the 25 small gray outlined squares in Figure 2 running down the center of the board If the transceivers have four unpopulated solder pads to their right then the transceivers are RS485 style This version of the DIO24 has the following identification register values Table 1 Register level identification of the DIO24 Register Value Description PCUDR 0x908010B5 The lower 16 bits is the Vendor ID and identifies PLX Technology The upper 16 bits is the Device ID and identifies the chip is a PCI9080 PCISVID 0x10B5 This identifies the PCISID as being assigned by PLX Technologies PCISID 0x2706 This identifies the board as a member of the DIO24 product series 10 General Standards Corporation Phone 256 880 8787 DIO24 User Manual 2 1 2 PCI DIO24 GD1 This version of the board includes RS485 tr
26. oration assumes no responsibility for any consequences resulting from omissions or errors in this manual or from the use of information contained herein General Standards Corporation reserves the right to make any changes without notice to this product to improve reliability performance function or design ALL RIGHTS RESERVED The information in this document is subject to change without notice This document may be copied or reproduced provided it is in support of products from General Standards Corporation For any other use no part of this document may be copied or reproduced in any form or by any means without prior written consent of General Standards Corporation GSC is a trademark of General Standards Corporation PLX and PLX Technology are trademarks of PLX Technology Inc 3 General Standards Corporation Phone 256 880 8787 DIO24 User Manual Table of Contents 5 O A RRA 11 ene TEE H 1 2 Plug and ME 7 RERA AAA RESQUICOS T I A eege A 7 1 4 ERR H LAT OSA kO En E E EE H 1 42 External 1 0 Interface rana a atada tata let little 7 IS Ordering Information A EE 8 126 Custom Applications ee a E eeh 8 1 7 Reference Material icon Aa ee ee 8 Zz PHYSICAL DESEEUP ASA Y lee se eles E ee Slade oad Laced ease 10 GN N a C LO EE EE 10 Se NEE RE AE 11 PAPE O leede enee Ee A E A ETE A NN 11 2 2 1 External I O Connection PI 11 DIA o te de o de ea a e dis bed 12 2 3 02 Jumper Block ati isa 12 TE 13 DAV EPGA
27. ory provided updates as needed NOTE The DIO24 can be outfitted with custom firmware on an as needed basis Consult the factory for additional information 2 4 2 Termination Resistors RP1 RP7 Resister packs RP1 to RP7 are the termination resistors required for RS485 operation They are located towards the center of the board Pin one is either at the top or the left of the socket according to the socket s orientation For a multi drop environment the termination resistors are removed from all but the two end nodes As necessary the resistors may be also be replaced with alternate values In the factory default configuration all seven resistor packs are installed and all are 150Q 13 General Standards Corporation Phone 256 880 8787 DIO24 User Manual NOTE Consult the factory if additional information is required 2 5 Cables 2 5 1 Loop Back Test Cable The loop back test cable is used for DIO24 testing operations It is used with both the RS485 422 and theLvDs interfaces The cable is used by various test applications that verify the functionality of both the DIO24 and the corresponding device driver On this cable all three ports are wired in parallel such that all Port A pins are wired directly to the same identical pins for both Port B and Port C In addition the Dedicated Input is wired in parallel with the three DO pins This means that the Port A DO pin is connected to the three pins Port B DO Port C DO and Dedicat
28. pose of this document is to briefly describe the DIO24 I O board its features its use and its hardware interface 1 2 Plug and Play The DIO24 is Plug and Play compatible If the host is also Plug and Play compatible then the BIOS will recognize and configure the DIO24 accordingly 1 3 System Resources Through Plug and Play initialization the DIO24 is given three system resources This includes a 256 byte block of memory space for the PLX PCI9080 feature set registers plus an identical block for the same registers that is mapped to I O port space It also includes a 512 byte block of memory for the GSC specific DIO24 registers This board requires neither a DMA channel nor an interrupt request line 1 4 Hardware Overview The DIO24 is a simple 25 bit discrete I O interface board The host side connection is PCI based and the external VO interface is variable see below The external interface includes 24 pins that can be arbitrarily programmed as either input or output and one pin that is input only The 24 programmable pins are divided into three groups of eight pins each Port A Port B and Port C Ports A and B are each programmable as all inputs or all outputs The Port C pins are individually programmable Figure 1 DIO24 simple block diagram Port A 8 bits 24H gt Port B 8 bits PEI gt PEX a Transciever Cable Interface PCI9080 Doki Port C 8 bits SES Interface Dedicated Input 1 bit or cloc
29. s the following three conditions are met 1 PCI9080 asserted PERR itself or observed PERR asserted 2 PCI9080 was bus master for the operation in which the error occurred 3 Parity Error Response bit in the Command Register is set Writing a 1 to this bit clears the bit DEVSEL Timing Indicates timing for DEVSEL assertion A value of 01 indicates a medium decode Note Hardcode to 01 Target Abort A 1 indicates the PCI9080 has signaled a target abort Writing a 1 to this bit clears the bit Received Target Abort A l indicates the PCI9080 has received a target abort Writing a 1 to this bit clears the bit Master Abort A 1 indicates the PCI9080 has generated a master abort signal Writing a 1 to this bit clears the bit Signal System Error A 1 indicates the PCI9080 has reported a system error on the SERR signal Writing a 1 to this bit clears the bit Detected Parity Error A l indicates the PCI9080 has detected a PCI bus parity error even if parity error handling is disabled the Parity Error Response bit in the Command Register is clear One of three conditions can cause this bit to be set 1 PCI9080 detected a parity error during a PCI address phase 2 PCI9080 detected a data parity error when it was the target of a write 3 PCI9080 detected a data parity error when performing a master read Writing a 1 to this bit clears the bit 21 General St
30. t Port C pins Setting a bit to one programs the port pin as an output Setting a bit to zero programs the port pin as an input Bits can be reprogrammed arbitrarily The Dedicated Input pin can be used as a single input or a clock output Speed of the clock depends on the ordering option clock speed is specified in the part number 3 4 I O Reads and Writes Reading from the Discrete Data Input Register DDIR will obtain the data level on all 25 pins both input and output The data level on the output pins is control by the value written to the Discrete Data Output Register DDOR Writes to the DDOR are latched Reads from the DDOR return the current latched value Propagation delays from the external I O connector to the DDIR and from the DDOR to the external I O connector are both less than a single PCI bus access cycle 15 General Standards Corporation Phone 256 880 8787 DIO24 User Manual 4 Registers This section gives a description of the DIO24 register map and all DIO24 registers The GSC specific registers are covered in detail The PLX PCI9080 registers are covered is less detail The full DIO24 register map consists of PCI specific registers internal PLX PCI9080 registers and GSC specific registers In the paragraphs that follow offsets are given in bytes and register sizes are given in bits Register access types are RO for read only RW for read write WO for write only and W1 for write once If the
31. terrupt Enable D9 PCI Doorbell Interrupt Enable Unused D10 PCI Abort Interrupt Enable D11 PCI Local Interrupt Enable 26 General Standards Corporation Phone 256 880 8787 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D31 28 DIO24 User Manual Local Interrupt must be enabled for USC FIFO interrupts Retry Abort Enable Unused PCI Doorbell Interrupt Status PCI Abort Interrupt Status PCI Local Interrupt Status Local Interrupt Output Enable Local Doorbell Interrupt Enable Unused Local DMA Channel 0 Interrupt Enable Local DMA Channel 1 Interrupt Enable Local Doorbell Interrupt Status DMA Channel 0 Interrupt Status DMA Channel 1 Interrupt Status BIST Interrupt Status A 0 indicates a Direct Master was bus master during a Master or Target abort A 0 indicates that DMA CHO was bus master during a Master or Target abort A 0 indicates that DMA CH1 was bus master during a Master or Target abort A 0 indicates that a Target Abort was generated by the PCI9080 after 256 consecutive Master retries to a Target PCI Mailbox 3 0 Write Status 5 3 2 Serial EEPROM Control PCI Command Codes User I O Control Init Control Register PCI 0x6C Reset 0x0x001767E D3 0 D7 4 D11 8 D15 12 D16 D17 D23 18 D24 D25 D26 D27 D28 D29 D30 D31 PCI Read Command Code for DMA PCI Write Command Code for DMA PCI Memory Read Command Code for Direct Master Unused PCI
32. ters Note PCIBARO is Memory Mapped Base Address of PCI9080 Registers 22 General Standards Corporation Phone 256 880 8787 DIO24 User Manual 5 1 10 PCI Base Address Register for UO Access to Local Runtime DMA Registers Offset 0x14 Reset 0x00000001 DO Memory Space Indicator A l indicates the register maps into I O space Note Hardcoded to 1 D1 Reserved D7 2 UO Base Address Default Size 256 bytes Note Hardcoded to 0 D31 8 UO Base Address Base Address for I O access to Local Runtime and DMA Registers Note PCIBAR1 is I O Mapped Base Address of PCI9080 Registers 5 1 11 PCI Base Address Register for Memory Access to Local Address Space 0 Offset 0x18 Reset 0x00000000 DO Memory Space Indicator A 0 indicates register maps into Memory space Specified in Local Address Space 0 Range Register LASORR D2 1 Location of register if memory space Location values 00 Locate anywhere in 32 bit memory address space Specified in Local Address Space 0 Range Register LASORR D3 Prefetchable A 0 indicates reads are not prefetchable Specified in Local Address Space 0 Range Register LASORR D31 4 Memory Base Address Memory base address for access to Local Address Space 0 5 1 12 PCI Subsystem Device Vendor ID Register Offset 0x2C Reset 0x908010B5 D15 0 Subsystem Vendor ID 0x10B5 PLX Technology D31 16 Subsystem Device ID 0x2606 General Standards Corporation DIO24 0x24
33. vision 7 0 FR Firmware Revision This gives the revision number of the FPGA firmware 4 3 2 Board Control Register BCR 0x04 32 RW This register is used to control various board operations Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field CO BR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Field Description 31 1 Reserved 4 co Clock Out Writing a one here enables the clock output on cable signal D24 The D24 bit must also be configured as an output via the IO Control Register see section 4 3 4 Board Reset Writing a one here resets the board The IOCR and DDOR are programmed to zero 0 BR The bit clears itself The operation is completed within a single PCI bus access cycle Writing a zero has no affect 4 3 3 Board Status Register BSR 0x08 32 RO This register reports the status of various board features Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field UJ1 UJO Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Field Description 3
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