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ST10X167 USER`S MANUAL - REV

1. 65 5 4 1 Context Switching tienes tines etnies nee Tete iyaw ien dE 66 5 5 INTERRUPT RESPONSE TIMES 66 5 5 1 PEG Response Times nie e 67 5 6 EXTERNAL INTERRUPTS rennen retine eden o eye 69 5 6 1 Fast External Intermpts iei te ettet rer ne ect Ere Percent re 70 5 7 TRAP FUNCTIONS 2er reete ere ene ean A aee oe dde 71 5 7 1 Software Traps spardar ana was t Pe E Rae E Ee ke 71 5 7 2 Hardware Traps RATER Ad DERE SERRA 71 4 294 ST10X167 5 7 3 External NMI t Zuzana Qua Qa yau aw qupa qaa sas 73 5 7 4 tack Overtlow Traps uid 73 5 7 5 Stack Underflow rapa cct e ori ia t ede be Dh pae a Fe i Dd 73 5 7 6 Undefined Opcode Trap cete e pce een 73 5 4 Protection Irapuato ste mte tette ier RR 73 5 7 8 Illegal Word Operand Access 01 0000 73 5 7 9 Illegal Instruction Access unice et e cette tene tei eene rr iced 73 5 7 10 Illegal External Bus Access 73 6 PARALLEL PORTS 2 saqisaq 74 6 1 INTRODUCTIONS y au LN exe Reseed ee ceeds Moe Re 74 6 1
2. 20 2 4 3 Beg tT 20 2 4 4 Oscillator Watchdog OW D scr u u rideo pon deett 20 2 5 ON CHIP PERIPHERAL 21 2 5 1 PeripheralilBiearfaces tee A ber pe bh Ped 21 2 5 2 Peripheral TIMING Sectarian piede a saan haya kasqaqa renes 21 2 5 8 Programmling Hitts cite Pret aS E ru am dg tas 21 2 5 4 Parallel Porte s ette eate eter eee ter ext eter tane DERE nee Ee ete d 22 2 5 5 Serial Channels as uuu aw eios 22 2 5 6 The on chip CAN Module 22 2 5 7 General Purpose Timer GPT Unit 23 2 5 8 Watchdog TIMET ET 23 2 5 9 Capture Compare CAPCOM Units essen nennen 23 2 5 10 Pulse Width Modulation Unit Qu s u R a Aaa saya 24 2 5 11 AID Converter L usus icd esed 24 2 6 PROTECTED BITS 2 ap Ei ain eal dative eed e pav boc give enti 25 3 MEMORY ORGANIZATION U u u uu uu u 26 3 1 INTERNAL ROM rettet oa Fes od 27 3 2 INTERNAL RAM AND SFR AREA 28 3 2 1 NECI CM Em 29 3 2 2 General Purpose Registers uuu 30 3 2 3 PEC Source and Destination 31 3 2 4 Special Function Registers cocer peccet ee ee Det et v
3. 172 Hardware Reset rire ey 242 17 71 Hold State 125 ky ST10X167 Idle State BUS 123 Idle 292 Incremental Interface Mode 134 151 Input threshold y y 75 Instruction 273 gt 525244 5 0656 36 PIPSIING 35 TIMING 41 unseparable 281 Interface CAN 22 220 serial sync 165 The External Bus Interface 104 Internal RAM iie irr o rrr 28 Interrupt CAPCOM dosi e 198 Enable Disable 64 extemal u ku wass 69 fast exter al 22 eerte rrr sa 70 Handling CAN 225 sss odes ie ue 60 Processing essi denen 55 58 Register 225 Response Times 66 DOULCES T 56 SYSTEM io eer ua eee ee rediere ah 16 55 VECIOMNS cos ET III TID D I 56 ccm wr 46 L Lower Arbitration Reg 230 Lower Global Mask Long 228 Lower Mask of Last Message 228 M Master mod uie eR 124 M 53 MERE
4. 6 The timer resolutions which result from the selected pre scaler option are listed in the Table 27 This table also applies to the Gated Timer Mode of T6 and to the auxiliary timer T5 in timer and gated timer mode Table 27 GPT2 timer resolution Refer to the device datasheet for a table of timer input frequencies resolution and periods for the range of pre scaler options Pre scaler factor Resolution in CPU clock cycles 147 294 ST10X167 Timer 6 in Gated Mode Gated timer mode for the core timer T6 is selected by setting Bit field in register to 010b 011b Bit T6M 0 T6CON 3 selects the active level of the gate input In gated timer mode the same options for the input frequency as for the timer mode are available However the input clock to the timer in this mode is gated by the external input pin T6IN Timer T6 External Input which is an alternate function of P5 12 see Figure 80 If T6M 0 0 the timer is enabled when T6IN shows a low level A high level at this pin stops the timer If 6 0 1 pin T6IN must have a high level in order to enable the timer In addition the timer can be turned on or off by software using Bit T6R The timer will only run if T6R 1 and the gate is active It will stop if either T6R 0 or the gate is inactive Note transition of the gate signal at pin T6IN does not cause an int
5. 253 Protected a A ENRE 4 aaa 43 61 Pulse Width Modulation 24 PREMIER DOLO PROB IE EOD DU S 24 PWM Module 200 208 PWMCONI1 209 286 294 R RAM extension cc Eee 32 internal auqa ever 28 Read Write Delay 114 READY asi CM Ure 115 Register 257 259 265 Reset qataqa aquqa 242 Configuration 246 Output eue 245 Values seg eee IR e DOO 246 Se 282 249 s SOBO cake P 162 SOCON P 157 SORBU Aiwa 161 162 GORIC 163 SOTBIG S0E C 164 SODBUE any esa sabia 160 162 163 Segment Address eer 1 10 251 boundaries 33 Segmentation Enable Disable 43 Serial Interface 27 Asynchronous 158 e ar hund er 22 220 Synchronous 161 165 PM ML 31 259 265 Single Chip Mode 104 Single shot mode PWM 206 Slave mode erri ERI ns 124 Software Reset 242
6. 0008 UUUUh UUUUh UUUUh UUUUh UUUUh UUUUh UUUUh UUUUh The first 8 GPRs R7 R0 may also be accessed Bytewise Other than with SFRs writing to a GPR Byte does not affect the other Byte of the respective GPR The respective halves of the Byte accessible registers receive special names Table 42 General purpose registers GPRs Bit wise addressing wa Y s RL1 RH5 RL6 RH6 RL7 RH7 CP 15 CPU General Purpose Byte Register RH7 258 294 ST10X167 20 3 Special Function Registers Ordered by b in column Name SFRs within the Extended SFR Space ESFRs The following table lists all SFRs which are are marked with the letter E in column Physical implemented in the ST10X167 in alphabetical Address Registers within on chip X Peripherals order CAN are marked with the letter X in column Bit addressable SFRs are marked with the letter Physical Address Table 43 Special function registers ordered by name Physical 8 bit iM Reset ADCIC b FF98h CCh A D Converter End of Conversion Interrupt Control Register 0000h ADCON b FFAOh DOh A D Converter Control Register 0000h ADDAT FEAOh 50h A D Converter Result Register 0000h ADDAT2 FOAOh E 50h A D Converter 2 Result Register 0000h ADDRSEL1 FE18h 0Ch Address Select Register 1 0000h ADDRSEL2 1 0Dh Address Select Register 2 0000h ADDRSEL3 FE1Ch OEh Address Select Register 3 0000h ADDRSEL4 FE1Eh OFh Add
7. 227 Reset Value UUUUh 271 Reset Value 0400h 271 Reset Value UUUUh 272 IDPROG F078h 3Ch Interrupt Register EF02h IP Lower Arbitration Reg EFn4h Lower Global Mask Long EF0Ah Lower Mask of Last Message EF0Eh MDC FF0Eh 87h MDH FE0Ch 06h MDL FE0Eh 07h ESFR XReg XReg XReg XReg SFR SFR SFR Message Configuration Register EFn6h XReg Message Control Register EFn0h ODP2 F1C2h Eth ODP3 F1C6h E3h ODP6 F1CEh E7h ODP7 F1D2h E9h ODP8 F1D6h EBh ONES FF1Eh 8Fh FF02h 81h POL FFOOh 80h FFO6h 83h P1L FF04h 82h P2 FFCOh EOh FFC4h E2h P4 FFC8h E4h P5 FFA2h D1h Pe P7 FFCCh E6h FFDOh E8h P8 FFD4h EAh PECCx FECyh 6zh see Table 8 PICON F1C4h E2h PSW FF10h 88h PSW FF10h 88h PWMCONO FF30h 98h PWMCON1 FF32h 99h PWMIC F17Eh BFh REG NAME A16h A8h REG A16h A8h RPOH F108h 84h RPOH F108h 84h SOCON FFBOh D8h SOEIC FF70h B8 SORIC FF6Eh B7h SOTBIC F19Ch CEh SOTIC FF6Ch B6h SP FE12h 09h SSCCON FFB2h D9h SSCCON FFB2h D9h SSCEIC FF76h BBh SSCRIC FF74h BAh SSCTIC FF72h B9h ky XReg ESFR ESFR ESFR ESFR ESFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR ESFR SFR SFR SFR SFR
8. A m kuna 22 52 ZL mykas 53 Memory irid 17 bit addressable 29 External yn yi eee TCR eee dese 33 dA tense Le Sepa s 28 ROM Mee 27 282 A E 32 Memory Cycle Time 113 Message Configuration Register 231 285 294 ST10X167 Message Control Register 229 Multiplexed Bus 106 Multiplication 52 273 N qaqaqa P 55 73 ODE 82 DPS EE 85 Samana 93 ASEE 96 ODPBS TER than 99 NL RS 54 Open Drain Mode 74 P POL POM E rr 77 FALL 249 82 PO ENERO 85 A o Lb e QUE 88 NRI TOS 90 LONE PRECES 92 95 CEN OD 99 DEG Ossa a 16 17 31 62 Response Times 67 sso MH EU T 62 Peripheral 5 21 PICON TTE 76 um mE 102 in Idle and Power Down mode 256 i n 35 Effects sayu ERIS 37 251 epe 24 input threshold 75 Power Down Mode
9. The virtual stack addresses are transformed to physical stack addresses by concatenating the significant Bit of the stack pointer register SP see table with the complementary most significant Bit of the upper limit of the physical stack area 00 FBFEh This transformation is done via hardware see Figure 151 The reset values STKOV FA00h STKUN FC00h SP FC00h STKSZ 000b map the virtual stack area directly to the physical stack area and allow using the internal system stack without any changes provided that the 256 Word area is not exceeded Figure 151 Physical stack address generation FBFEh 1111 1011 1 111 1110 FB80h 1 111 1011 1000 0000 FB80h 1111 1011 1000 0000 After PUSH 1111 10101 11111110 11111010 0000 0000 1111 1000 0000 0000 After PUSH FBFEh 1111 1011 11111110 FBFEh 1111 1011 1 111 1110 FBFEh 1111 1011 1111 1110 FBFEh 1111 1011 1111 1110 F7FEh 1111 01151 1111 1110 256 Words FB7Eh 31111 1011 01111110 SP 64 Words Stack Size 276 294 ky ST10X167 The following example demonstrates the circular stack mechanism which is also an effect of this virtual stack mapping First register R1 is pushed onto the lowest physical stack location according to the selected maximum stack size With the following instruction register R2 will be pushed onto the highest physical stack location although the SP is decremented by 2 as for the previous push operation MOV SP 0F802h
10. o I Sos q 71 Source cesses 56 p MRNA TP 51 SSC ets han eens 165 Baudrate generation 174 Error Detection 174 Full Duplex 20 0 02 170 Half Duplex 172 ciel ay pa a Qu cass 174 SSCDONI uu 167 SS CEC od E uum tee ui aqasha 176 172 SSOR uuu uum atas 176 SOLID nest oetorten ei SA eat sexs 176 Steele ai pa as 29 51 275 Startup Configuration 246 STIKOV tum EB 5 STUN 52 S bro tine u luu oe e u e penne 278 Synchronous Serial Interface 165 SYSGON hapa bor 42 System Reset Startup Configurations 247 T 186 44 ua ua tices 186 186 TICON yay s A CA ae 137 142 WAGs TAC eoi erae tut qur 142 TAC ON TE 130 TT 142 T4GON D 137 142 MN DU IM 149 154 P ES 145 pom m 154 ST10X167 E 186 78 a aaa a NNN 186 pre ET 186 Threshold 75 2222572220 23 128 143 Auxiliary Timer
11. Feb er nme 10 EMU eo ALE BUSTYP BUSTYP ACTO CTL0 2 To Clock Generator To Port4 Logic To Porte pens Logic Notes 1 Not latched from Porto 2 Bit set if EA pin is 1 Internal Internal 3 248 294 RPOH F108h 84h 15 14 13 12 11 10 ST10X167 Reset Value XXh Write Configuration Control 9 8 7 6 5 4 3 2 1 0 ee SAtSEL csse wrc R R R R 0 Pins WR acts as WRL pin BHE acts as WRH 4 Pins WR and retain their normal function CSSEL Chip Select Line Selection Number of active CS outputs 0 0 3 CS lines CS2 CS0 0 1 2 CS lines CS1 CS0 1 0 No CS lines at all 11 5 CS lines CS4 CS0 Default without pull downs SALSEL Segment Address Line Selection Number of active segment address outputs 0 0 4 Bit segment address A19 A16 0 1 No segment address lines at all 1 0 8 Bit segment address A23 A16 1 1 2 Bit segment address A17 A16 Default without pull downs fopu fxta X F frat x 4 Lx3 2 5 L x 1 5 L x 0 5 L x 2 5 a Notes 1 The Bidirectional Reset functionality has no impact the System Startup Configuration latching If the PLL factor or the input clock frequency is changed when PORTO is transparent then the PLL needs a PLL synchronization lock time typical value is 500 us 2 The maximum depends on the duty cycle of the external clock signal The maximum input frequency is 25
12. acts as WRH System Clock Output Enable CLKOUT 0 CLKOUT disabled pin may be used for general purpose 1 CLKOUT enabled pin outputs the system clock signal ST10X167 1 Pin disabled pin may be used for general purpose I O BYTDIS Disable Enable Control for Pin BHE Set according to data bus width 0 Pin enabled ROMEN Internal Memory Enable Set according to pin EA during reset 0 Internal ROM disabled accesses to the Flash Memory area use the external bus 1 Internal ROM enabled SGTDIS Segmentation Disable Enable Control 0 Segmentation enabled CSP is saved restored during interrupt entry exit 1 Segmentation disabled Only IP is saved restored ROMS1 Internal Memory Mapping 0 Internal ROM area mapped to segment 0 00 0000h 00 7 FFFh 1 Internal ROM area mapped to segment 1 01 0000h 01 7FFFh STKSZ System Stack Size Selects the size of the system stack in the internal RAM from 32 to 1024 Words Note Register SYSCON cannot be changed after execution of the EINIT instruction The function of Bit XPER SHARE VISI BLE WRCFG BYTDIS ROMEN and ROMS is described in more detail in Sec tion 8 4 Controlling the External Bus Controller System Clock Output Enable CLKEN The system clock output function is enabled by setting Bit CLKEN in register SYSCON to 1 If enabled port pin P3 15 takes on its alternate
13. Physical Layer 18 SYSTEM RESET Internal system reset initializes a device into a defined default state System reset is invoked either by asserting a hardware reset signal on pin RSTIN Hardware Reset Input by executing the SRST instruction Software Reset or by an overflow of the Watchdog Timer A bi directional reset can be implemented on the ST10C167 and ST10R167 Synchronous reset can be used for all derivatives of the ST10X167 Asynchronous reset can be used by the ST10C167 and ST10R167 to exit from power down by external interrupt For the ST10C167 and ST10R167 Asynchronous reset is invoked by asserting RSTIN and forcing Vpp low Figure 142 Internal simplified Reset Circuitry EINIT Instruction Reset State Machine Clock ST10X167 Synchronous reset is invoked by asserting RSTIN and forcing Vpp high RSTOUT is activated once the reset conditions are detected and remains active until the execution of EINIT The CPU and peripherals are set in their predefined default state After the internal reset condition is removed the microcontroller starts program execution from memory location 00 0000h in code segment zero This start location typically holds a branch instruction to the start of a software initialization routine for the application specific configuration of peripherals and CPU special function registers The internal reset circuitry is explained in
14. The input frequency to the watchdog timer can be selected via Bit WDTIN in register WDTCON to be either fcpU 2 orfcpu 128 The reload value WDTREL for the high Byte of WDT can be programmed in register WDTCON The period Pwpr between servicing the watchdog timer and the next overflow can therefore be determined by the following formula g 1 WDTIN x6 y 216 WD TREL x 28 Pwpr fopu Refer to the device datasheet for a table of watchdog timer ranges For security you are advised to rewrite WDTCON each time before the watchdog timer is serviced ky 13 BOOTSTRAP LOADER The built in bootstrap loader of the ST10X167 provides a mechanism to load the startup program through the serial interface after reset In this case no external or internal ROM Memory is required for the initialization code starting at location 00 0000h The bootstrap loader moves code data into the internal RAM but can also transfer data via the serial interface into an external RAM using a second level loader routine ROM Memory internal or external is not necessary but it may be used to provide lookup tables or core code like a set of general purpose subroutines for I O operations number crunching system initialization etc see Figure 101 The bootstrap loader can be used to load the complete application software into ROMless systems to load temporary software into complete systems for testing or calibration
15. Q 5 b CC22IC b CC28IC b CC24 FE70h CC24IC b 170 E m ITI m Register 22 0000h m m N N Register 18 0000h 4 C 4 C 4 C 4 C C C 4 4 3 B 3 B 3 B 3 B 3 B 3 B 3 B 3 B 3 B 260 294 ST10X167 Table 43 Special function registers ordered by name continued Ban CAPCOM Register 26interupiGonvel Regier 0000h occ Fin E Cah GAPCOW Register 31 Interrupt Corro Register 0000h _ como b Fr aon GAPCOMMeseConriRegsero ccm b rs Mode Reger ooon come b Fr GAPCOMMoseConriRegser b rs Ach CAPCOM Mode Convo Registers 000 ese reo GPU Code Segment Pointer Register ead ony 0000h om rem E m momceommimeme PH b E PohDredionConRegser om PL b ria E sm PiL Drecion Convoi Regser OPH b rie E PihDiewonConoFegser f o Er E m D l u sm Em Paeon 0m Froen Em Pon Drecion Gontol Regier om rra Eon Direction Convo Regser om um ein reaps a benc Tr a ree OP Gi ae Poor Reps DP3 098 CPU Data Page Pointer 3 Register bit IU o Sie o oj oj o 3 261 294 ST10X167 Table 43 Special function registers ordered by name continued MD b FFOEh F
16. oy oj gt a o gt CCM3 b T2IC b A A T3IC b FF62h Bih GPTI Timer 3 Interrupt Control Register 0000h T4IC b FF64h b GPT1 Timer 4 Interrupt Control Register 0000h T5IC GPT2 Timer 5 Interrupt Control Register 0000h o CRIC FF6Ah Bs GPT2 CAPREL Interrupt Control Register 0000h SOTIC FF Ch Beh Serial Channel 0 Transmit Interrupt Control Register 0000h SORIC FF Eh Serial Channel 0 Receive Interrupt Control Register 0000h E o Q gt GPT2 Timer 6 Interrupt Control Register 0000h m u D gt o CCOIC b b b o N A B B Eh 8Fh 90h 92h 93h 94h 98h 99h AOh A2h A4h A8h 9 Bh Ch BOh B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh Ch Dh BEh BFh COh 3 269 294 ST10X167 Table 44 Registers ordered by address continued Wa ma i EN i m i om 27 ADCIG FF Cch A D Converter End of Conversion Interrupt Control Register 0000h h C o CC111C FF8Eh CAPCOM Register 11 Interrupt Control Register 0000h o cO oj ADEIC FF9Ah A D Converter Overrun Error Interrupt Control Reg 0000h TOIC b FF9Ch CAPCOM Timer 0 Interrupt Control Register 0000h T1IC FF9Eh CF CAPCOM Timer 1 Interrupt Control Register 0000h ADCON FF
17. 137 149 CAPCOM MR 186 Concatenation 139 151 Gore Timet s esee 130 145 58 71 Tri State Time 113 U Unseparable instructions 281 Upper Arbitration Reg 230 Upper Global Mask Long 227 Upper Mask of Last Message 228 Waitstate Memory Cycle 113 Tri State neu 113 Watchdog 23 177 245 WDTCON 177 x KB redire t ente iro tet 18 127 XRAM on chip 32 2 ZEROS 54 287 294 ST10X167 23 INDEX OF REGISTERS ADCIC FF98h CCh ADCON FFAOh D0h ADDAT FEAOh 50h ADDAT 2 F0A0h 50h ADDRSEL1 FE18h OCh ADDRSEL2 FE1Ah ODh ADDRSELS FE1Ch OEh ADDRSEL4 FE1ER OFh ADEIC FF9Ah CDh Bit Timing Register EFO4h BUSCONO FFOCh 86h BUSCON1 FF14h 8Ah BUSCON2 FF16h 8Bh BUSCONS FF18h 8Ch BUSCONA FF1Ah 8Dh CCMO FF52h A9h CCM1 FF54h AAh FF56h ABh CCMS FF58h ACh CCMA FF22h 91h CCMB FF24h 92h CCM6 FF26h 93h CCM7 FF28h 94h CCxIC see Table 32 Control Status Register EFOOh CP FE10h 08h CRIC FF6Ah B5h CSP FEO8h 04h DPOH F102h 81h DPOL F100h 80h DP1H F106h 83h DP1L F104h 82h DP2 FFC2h E1h
18. Buffer Clock M lt lt 1 MUX D 9 Alternate Data Input amp Input Latch 13 11 0 87 294 ST10X167 Pin P3 12 BHE WRH is another pin with an alter used for general purpose I O by disabling the nate output function however its structure is alternate function BYTDIS 1 WRCFG 0 slightly different see Figure 34 After reset the Note Enabling the BHE or WRH function auto BHE or WRH function must be used depending on matically enables the P3 12 output driver the system start up configuration In either of Setting Bit DP3 12 1 is not required ear During bus hold pin P3 12 is switched these cases there is no possibility to program any back to ite standard un etion and i then port latches before Thus the appropriate alter controlled by DP3 12 and P3 12 Keep nate function is selected automatically If BHE DP3 12 0 in this case to ensure floating WRH is not used in the system this pin can be in hold mode Figure 34 Block diagram of pins P3 15 CLKOUT and P3 12 BHE WRH Write DP3 x Direction Latch Read DP3 x Alternate Function e Enable Write P3 x Alternate Data Output P3 12 BHE P3 15 CLKOUT Port Output Latch Read Internal Bus 6 6 Port4 If this 8 Bit port is used for general purpose I O the direction of each line can be configured via the corresponding dire
19. 14 5 2 Compare Mode 1 Compare mode 1 is selected for register CCx by setting Bit field CCMODx of the corresponding mode control register to 101b When a match between the content of the allocated timer and the compare value in register CCx is detected in this mode interrupt request flag CCxIR is set to 1 and in addition the corresponding output pin CCxIO alternate port output function is toggled For this purpose the state of the respective port output latch not the pin is read inverted and then written back to the output latch Compare mode 1 allows several compare events within a single timer period An overflow of the allocated timer has no effect on the output pin nor does it disable or enable further compare events In order to use the respective port pin as compare signal output pin CCxlO for compare register CCx in compare mode 1 this port pin must be configured as output and the corresponding direction control Bit must be set to 1 With this configuration the initial state of the output signal can be programmed or its state can be modified at any time by writing to the port output latch In compare mode 1 the port latch is toggled upon each compare event see Figure 111 Note If the port output latch is written to by software at the same time it would be altered by a compare event the soft ware write will have priority In this case the hardware triggered change will not become effec
20. This instruction 15 1 must not access this memory area Code accesses to the new address area must be made after an absolute branch to this area Note As a rule instructions that change external bus properties must not be executed from the respective external memory area Timing Pipeline architecture drastically reduces the average instruction processing time The mean ratio is about four to one instruction cycle Some peculiar cases of pipeline configuration extend the instruction processing time by half or by one cycle These cases have to be taken in account for the time critical software routines Besides a general execution time description the following section provides some hints on how to optimize time critical program parts with regard to such pipeline caused timing particularities 4 2 Bit handling and Bit protection The ST10X167 provides several mechanisms for Bit manipulation These mechanisms either handle software flags within the internal RAM control on chip peripherals via control Bit in their respective SFRs or control I O functions via port pins The instructions BSET BCLR BAND BOR BXOR BMOV and BMOVN explicitly set or clear specific Bit The instructions BFLDL and BFLDH make it possible to change up to 8 Bit of a specific Byte at a time The instructions JBC and JNBS implicitly clear or set the specified Bit when the jump is taken The 40 294 instructions JB and JNB also conditional
21. three pins are used for bus arbitration after Bit HLDEN was set once ST10X167 8 6 1 Connecting Bus Masters When multiple ST10X167 s or a ST10X167 and another bus master shall share external resources some glue logic is required that defines the currently active bus master and also enables a ST10X167 which has surrendered its bus interface to regain control of it in case it must access the shared external resources This glue logic is required if the other bus master does not automatically remove its hold request after having used the shared resources When two ST10X167 are connected in this way the external glue logic can be left out In this case one of the controllers must be operated in its master mode default after reset DP6 7 0 while the other one must be operated in its slave mode selected with DP6 7 1 In slave mode the ST10X167 inverts the direction of its HLDA pin and uses it as an input while the master s HLDA pin remains an output This approach does not require any additional glue logic for the bus arbitration see Figure 60 When the bus arbitration is enabled HLDEN 1 the three corresponding pins are automatically controlled by the EBC Normally the respective port direction register Bit retain their reset value which is 0 This selects master mode where the device operates compatible with earlier versions slave_mode is enabled by intentionally switching pin BREQ to output D
22. FFC6h E3h DP4 FFCAh E5h DP6 FFCEh E7h care E Em DP7 FFD2h E9h DP8 FFD6h EBh DPP0 FE00h 00h DPP1 FE02h 01h DPP2 FE04h 02h DPP3 FE06h 03h EXICON F1COh E0h EXICON F1COh E0h Global Mask Short EF06h IDCHIP F07Ch 3Eh IDMANUF F07Eh 3Fh IDMEM F07Ah 3Dh 288 294 SFR SFR SFR ESFR SFR SFR SFR SFR SFR XReg SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR ESF XReg SFR SFR SFR ESFR ESFR ESFR ESFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR ESFR ESFR XReg ESFR ESFR ESFR F167 Reset Value 42 Reset Value 00h 219 Reset Value 0000h 212 Reset Value 0000h 213 Reset Value 0000h 213 Reset Value 0000h 120 Reset Value 0000h 120 Reset Value 00008 121 Reset Value 0000h 121 Reset Value 00h 219 Reset Value UUUUh 227 Reset Value OXXON 119 Reset Value 0000h 119 Reset Value 0000h 119 Reset Value 0000h 119 Reset Value 0000h 119 Reset Va
23. The Special Functional Registers are listed both by name hexadecimal address instruction set is covered in full in the ST10 Family Programming Manual and is therefore not discussed in this manual However software programming feature including constructs for August 2002 modularity loops and context switching are described in Chapter 21 System Programming The DC and AC electrical specifications of the device and the pin description for each available package are not covered in this manual but are listed in the specific device Data Sheets Before starting on a new design verify the device characteristics and pinout with an up to date copy of the device Data Sheet The ST10X167 software and hardware develop ment tools include Compilers C FORTH Macro Assemblers Linkers Locators Library Managers Format Converters HLL debuggers Real Time operating systems n Circuit Emulators based on bondout or standard chips Plug In emulators Emulation and Clip Over adapters production Sockets Logic Analyzer disassemblers Evaluation Boards with monitor programs Industrial boards also for CAN FUZZY PROFIBUS FORTH applications Network driver software CAN PROFIBUS 10 294 1 1 Differences Between the ST10R167 ST10C167 amp ST10F167 Apart from the memory arrangement the ST10R167 and ST10C167 are functionally the same as ea
24. The interrupt system of the ST10X167 allows nesting of up to 15 interrupt service routines of different priority levels level 0 cannot be arbitrated Interrupt requests that are programmed to priority levels 15 or 14 ILVL 111Xb will be serviced by the PEC unless the COUNT field of the associated PECC register contains zero In this case the request will instead be serviced by normal interrupt processing Interrupt requests that are programmed to priority levels 13 through 1 will always be serviced by normal interrupt processing Note Priority level 0000b is the default level of the CPU Therefore a request on level 0 will never be serviced because it can never interrupt the CPU However an enabled interrupt request on level 0000b will terminate the ST10X167 s Idle mode and reactivate the CPU For interrupt requests which are to be serviced by the PEC the associated PEC channel number is derived from the respective ILVL LSB and GLVL see Figure 18 So programming a source to priority level 15 ILVL 1111b selects the channel group 7 4 programming a source to priority level 14 ILVL 1110b selects the channel group 3 0 The actual channel number is then determined by the group priority field GLVL see Figure 18 Simultaneous requests for PEC channels are prioritized according to the PEC channel number where channel 0 has lowest and channel 8 has highest priority All sources that request PEC
25. pulse width modulation PWM One of the auxiliary timers is programmed to reload the core timer on a positive transition of T3OTL the other is programmed for a reload on a negative transition of T3OTL With this combination the core timer is alternately reloaded from the two auxiliary timers Figure 75 shows an example for the generation of a PWM signal using the alternate reload mechanism T2 defines the high time of the PWM signal reloaded on positive transitions and T4 defines the low time of the PWM signal reloaded on negative transitions The PWM signal can be output on T3OUT with T3OE 1 P3 3 1 and DP3 3 1 With this method the high and low time of the PWM signal can be varied in a wide range Note The output toggle latch T3OTL is software accessible and may be changed if required to modify the PWM signal How ever this will NOT trigger the reload of T3 Avoid selecting the same reload trigger event for both auxiliary timers as both reload registers will try to load the core timer at the same time If this happens T2 is disregarded and the contents of T4 is reloaded ST10X167 Figure 75 GPT1 timer reload configuration for PWM generation Reload Register T2 T2IR Interrupt Request gt Y Core Timer T3 Up Down gt gt T3OUT P3 3 a O T3OE Interrupt gt Request T3IR T4l Reload Register T4 1 Lines only affected
26. 0 Port line P6 y output driver in push pull mode ODP6 y 1 Port line P6 y output driver in open drain mode 6 8 1 Alternate Functions of Port6 A programmable number of chip select signals CS4 CS0 derived from the bus control registers BUSCON4 BUSCONO can be output on 5 pins of Port6 The other 3 pins may be used for bus arbitra tion to accommodate additional masters in a ST10X167 system The number of chip select signals is selected via PORTO during reset The selected value can be read from Bitfield CSSEL in register RPOH read only in order to check the configuration during run time The Table 15 summarizes the alternate functions of Port6 depending on the number of selected chip select lines coded via Bitfield CSSEL Table 15 Port6 alternate functions A Canon uneton Port6 Pin EL General purpose I O Chip select CSO Chip select CSO Chip select General purpose I O Chip select CS1 Chip select CS1 Chip select CS1 General purpose I O General purpose Chip select CS2 Chip select CS2 General purpose I O General purpose General purpose I O Chip select CS3 General purpose I O General purpose I O General purpose I O Chip select HOLD External hold request input HLDA Hold acknowledge output BREQ Bus request output Figure 39 Port6 I O and alternate functions Alternate Function ky 93 294 ST10X167 The chip select lines of Port6 have an internal
27. 0 v DPP register concatenated with 14 bit 10 bit 14 bit Intra Page Address gives 24 bit address After reset or with segmentation disabled the DPP registers select data pages 3 0 All of the internal memory is accessible in these cases 4 4 6 The Context Pointer CP This non Bit addressable register is used to select the current register context This means that the CP register value determines the address of the first General Purpose Register GPR within the current register bank of up to 16 Wordwide and or Bytewide GPRs CP FE10h 08h SFR ResetValue FCOOh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 u E R R R R RW R Modifiable portion of register CP Specifies the Word base address of the current register bank When writing a value to register CP with Bit CP 11 CP 9 000 Bit CP 11 CP 10 are set to 11 by hardware in all other cases all Bit of Bit field cp receive the written value It is the user s responsibility to ensure that the physical GPR address specified via the CP register plus the short GPR address must always be an internal RAM location If this condition is not met unexpected results may occur Do not set CP below the IRAM start address 00 F600h 2K Byte Do not set CP above 00 FDFEh Be careful using the upper GPRs with CP above 00 FDEOh The register can be updated via any instruction which is capable of modifying an SFR Note Due to the in
28. 16 Bit and even the length of a bus cycle waitstates signal delays can be selected independently This allows access to a variety of memory and peripheral components directly with maximum efficiency If the device does not run in Single Chip Mode where no external memory is required the EBC can control external accesses in one of the following four different external access modes 16 18 20 24 Bit Addresses and 16 Bit data demultiplexed 16 18 20 24 Bit Addresses and 8 Bit data demultiplexed 16 18 20 24 Bit Addresses and 16 Bit data multiplexed 16 18 20 24 Bit Addresses and 8 Bit data multiplexed The demultiplexed bus modes use PORT for addresses and PORTO for data input output The multiplexed bus modes use PORTO for both addresses and data input output All modes use Port 4 for the upper address lines 16 if selected Important timing characteristics of the external bus interface waitstates ALE length and Read Write Delay have been made programmable to 18 294 give the user the choice of a wide range of different types of memories and or peripherals Access to very slow memories or peripherals is supported via a particular Ready function For applications which require less than 64K Byte of address space a non segmented memory model can be selected where all locations can be addressed by 16 Bit Port4 is not needed for the upper address Bit A2
29. All interrupt control registers are bit addressable and all bit can be read or written via software This allows each interrupt source to be programmed or modified with just one instruction When accessing interrupt control registers through instructions which operate on Word data types their upper 8 bit 15 8 will return zeros when read and will discard written data The layout of the Interrupt Control registers shown below applies to each register where stands for the mnemonic for the respective source ResetValue 00h 5 4 3 2 1 0 Group Level 9 8 7 6 ea RW RW RW RW Defines the internal order for simultaneous requests of the same priority 3 Highest group priority 0 Lowest group priority Interrupt Priority Level Defines the priority level for the arbitration of requests Fh Highest priority level Oh Lowest priority level Interrupt Enable Control Bit individually enables disables a specific source 0 Interrupt Request is disabled 1 Interrupt Request is enabled Interrupt Request Flag 0 No request pending 1 This source has raised an interrupt request 59 294 ST10X167 The Interrupt Request Flag is set by hardware whenever a service request from the respective source occurs It is cleared automatically upon entry into the interrupt service routine or upon a PEC service In the case of PEC service the Interrupt Request flag remains set if the COU
30. CEh ST10X167 Reset Value 00h 14 11 T 1 FF9Eh CFh ResetValue 00h 14 11 T T7IC F17Ah BEh 14 13 12 11 10 ESFR ResetValue 00h 4 3 2 1 0 TITI T T 1 T8IC F17Ch ESFR RW RW ResetValue 00h 4 3 2 1 0 14 11 ee 1 Note Refer to the General Interrupt Control Register description for an explanation of the control fields 14 3 Capture Compare Registers The 16 Bit capture compare registers CC0 through CC31 are used as data registers for capture or compare operations with respect to timers T0 T1 and T7 T8 The capture compare registers are not Bitaddressable Each of the registers CC0 CC31 may be individually programmed for capture mode or one of 4 different compare modes except for CC24 CC27 and may be allocated individually to one of the two timers of the respective CAPCOM unit or T1 and 7 or T8 RW RW respectively special combination of compare modes additionally allows the implementation of a double register compare mode When capture or compare operation is disabled for one of the CCx registers it may be used for general purpose variable storage The functions of the 32 capture compare registers are controlled by 8 Bit addressable 16Bit mode control registers named CCM0 CCM7 which are all organized identically see description below Each register contains Bit for m
31. Status Change Interrupt Enable 1 Enables interrupt generation when a message transfer reception or transmision is successfully completed or CAN bus error is detected and registered in LEC is the status partition Disable status change interrupt Error Interrupt Enable 1 Enables interrupt generation on a change of Bit BOFF or EWARN in the status partition 0 Disable error interrupt Configuration Change Enable 1 Allows CPU access to the Bit timing register 0 Disables CPU access to the Bit timing register Test Mode Bit 7 Make sure that Bit 7 is cleared when writing to the Control Register Writing a 1 during normal operation may lead erroneous device behaviour Last Error Code This field holds a code which indicates the type of the last error occurred on the CAN bus If a message has been transferred reception or transmission without error this field will be cleared Code 7 is unused and may be written by the CPU to check for updates 0 No Error 1 Stuff Error More than 5 equal Bit in a sequence have occurred in a part of a received message where this is not allowed Form Error A fixed format part of a received frame has the wrong format AckError The message this CAN controller transmitted was not acknowledged by another node Bit1Error During the transmission of a message with the exception of the arbitration field the device wanted to send a recessive level 1 but the monitored bus value was dominan
32. 2 Mode Control Register 4 7 151 CAPCOM1 Interrupt Control Register 0 15 CC16 31IC CAPCOM2 Interrupt Control Register 16 31 T78CON 2 Timers T7 and T8 Control Register TOIC T1IC CAPCOM Timer 0 1 Interrupt Control Register 2 Timer 7 8 Interrupt Control Register Bitis linked to a function Bit has no function or is not implemented Register is in ESFR internal memory space ST10X167 A CAPCOM unit handles high speed I O tasks such as pulse and waveform generation pulse width modulation or recording of the time at which specific events occur It also allows the implementation of up to 16 software timers The maximum resolution of the CAPCOM units is calculated with the formula in Chapter Section 14 1 CAPCOM Timers and is specified in the device datasheet Each CAPCOM unit consists of two 16 Bit timers TO T1 in CAPCOM1 T7 T8 in CAPCOM2 each with its own reload register TXREL anda bank of sixteen dual purpose 16 Bit capture compare registers through CC15 in CAPCOM1 CC16 through CC31 in 2 The input clock for the CAPCOM timers is programmable to several pre scaled values of the CPU clock or it can be derived from an overflow underflow of timer T6 in block GPT2 TO and T7 may also operate in counter mode from an external input where they can be clocked by external events Figure 106 CAPCOM unit block diagram 2 n 3 10 T
33. 29 b F184h E Register 29 Interrupt Control Register 0000h XPOIC b F186h E C9 CAN Module Interrupt Control Register 0000h b F18Ch E ceh CAPCOM Register 30 Interrupt Control Register 0000h XP11C F18Eh E X Peripheral 1 Interrupt Control Register 0000h CC311C b F194h E Cah CAPCOM Register 31 Interrupt Control Register 0000h 2 196 E X Peripheral 2 Interrupt Control Register 0000h SOTBIC b F19Ch E CEh Serial Channel 0 Transmit Buffer Interrupt Control Register 0000h XP3IC FI9Eh E PLL unlock Interrupt Control Register 0000h 1 E E External Interrupt Control Register 0000h B C C C C EXICON ODP2 B B B B B B B B C C C C b b E i b E i b E i 0 0 0 0 0 0 0 0 0 0 0 fire O K rm 00h DPP1 FEOh om CPU Data Page Pointer 1 Register 10 bit 0001h DPP2 FEo4h 02 CPU Data Page Pointer 2 Register 10 bit 0002h osh 0 Oah Bh och Em Em i NM i Om nm 71 71 7 mj mi m s ss 9 92192 C M M C m m m ER SP DH DL P P FE10h CPU Context Pointer Register s FE12h CPU System Stack Pointer Register STKOV FEt4h CPU Stack Overflow Pointer Register FA00h STKUN FE16h CPU Stack Underflow Pointer Register FC00h ADDRSEL1 FE18h Address Select Register 1 0000h ADDR
34. FA40h Register STKOV FAOCh 0 lt gt Register BUSCONO acc to startup configuration P3 10 TXDO T DP3 10 T Memory Configuration After Reset The configuration and the accessibility of the ST10X167s memory areas after reset in Bootstrap Loader mode differs from the standard case Pin EA is not evaluated when BSL mode is selected and accesses to the internal Flash area are partly redirected while the ST10X167 is in BSL mode see Figure 103 All code fetches are made from the special Boot ROM while data accesses read from the internal user ROM Data accesses will return undefined values on ROMIess devices The code in the Boot ROM is not an invariant feature of the ST10X167 User software should not try to execute code from the internal ROM area while the BSL mode is still active as these fetches will be redirected to the Boot ROM The Boot ROM will also move to segment 1 when the internal ROM area is mapped to segment 1 see Figure 103 External Signal L s 4 Normal 8kQ Circuit 2 74 Figure 103 Memory configuration after reset 16M Byte N access to external bus disabled access to T internal ROM enabled ST10X167 16M Byte 16M Byte access to external Depends on reset bus configuration enabled EA PO access to internal ROM enabled Depends on reset configuration userROM el BSL mode active Yes P0L
35. If either a positive or a negative transition of T3OTL is selected to clock the auxiliary timer this timer is clocked on every second overflow underflow of the core timer This configuration forms a 33 Bit timer 16 Bit core timer T3OTL 16 Bit auxiliary timer The count directions of the two concatenated timers are not required to be the same This offers a wide variety of different configurations T3 can operate in timer gated timer or counter mode in this case see Figure 73 Auxiliary Timer in Reload Mode Reload mode for the auxiliary timers T2 and T4 is selected by setting Bit field TxM in the respective register TxCON to 100b In reload mode the core timer T3 is reloaded with the contents of an auxiliary timer register triggered by one of two different signals The trigger signal is selected the same way as the clock source for counter mode see Table 25 A transition of the auxiliary timer s input or the output toggle latch T3OTL may trigger the reload Note When programmed for reload mode the respective auxiliary timer T2 or T4 stops independent of its run flag T2R or T4R Figure 73 Concatenation of core timer T3 and an auxiliary timer Up Down Core Timer T3 gt Interrupt Request Om Auxiliary Timer Tx Interrupt Request Note 1 Line only affected by over underflows of T3 but NOT by software modifications of T3OTL 139 294 ST10X167 Figure 74 GPT1 auxiliary
36. Jh T Result Lost Read of ADDAT Result of Channel x 3 16 1 3 Wait for ADDAT Read If in default mode of the ADC a previous conversion result has not been read out of register ADDAT by the time a new conversion is complete the previous result in register ADDAT is lost because it is overwritten by the new value and the A D overrun error interrupt request flag ADEIR will be set In order to avoid error interrupts and the loss of conversion results especially when using continuous conversion modes the ADC can be switched to Wait for ADDAT Read Mode by setting Bit ADWR in register ADCON If the value in ADDAT has not been read by the time the current conversion is complete the new result is stored in a temporary buffer and the next Figure 126 Wait for read mode example Conversion of Channel Write ADDAT ADDAT Full Temp Latch Full Generate Interrupt Request 2 1 3 Overrun Error Interrupt Request conversion is suspended ADST and ADBSY will remain set the meantime but no end of conversion interrupt will be generated After reading the previous value from ADDAT the temporary buffer is copied into ADDAT generating an ADCIR interrupt and the suspended conversion is started This mechanism applies to both single and continuous conversion modes While in standard mode continuous conversions are executed at a fixed rate determined by the conversion time in Wait for ADDAT R
37. N 1 N Interrupt Response Time 66 294 The minimum interrupt response time is 5 CPU clock cycles This requires program execution from the internal ROM no external operand read requests and setting the interrupt request flag during the last CPU clock cycle of an instruction When the interrupt request flag is set during the first CPU clock cycle of an instruction the minimum interrupt response time under these conditions is 6 CPU clock cycles The interrupt response time is increased by all delays of the instructions in the pipeline that are executed before entering the service routine including N When internal hold conditions between instruction pairs N 2 N 1 or N 1 N occur or instruction N explicitly writes to the PSW or the SP the minimum interrupt response time may be extended by 1 CPU clock cycle for each of these conditions When instruction N reads an operand from the internal memory or when N is a CALL RETURN TRAP or MOV Rn Rm data16 instruction the minimum interrupt response time may additionally be extended by 2 CPU clock cycles during internal ROM program execution In case instruction reads the PSW and instruction N 1 has an effect on the condition flags the interrupt response time may additionally be extended by 2 CPU clock cycles The worst case interrupt response time during internal ROM program execution adds to 12 CPU clock cycles Any reference to external location
38. Oscillator Watchdog counter On each transition of XTAL1 pin the Oscillator Watchdog is cleared If an external clock failure occurs then the Oscillator Watchdog counter overflows after 16 PLL clock cycles The CPU clock signal will be switched to the PLL clock signal in this case the PLL will run on its basic frequency of 2 5 MHz and the Oscillator Watchdog Interrupt Request XP3INT is flagged The CPU clock will not switch back to the external clock even if a valid external clock exits on XTAL1 pin Only a hardware reset can switch the CPU clock source back to external clock input When the OWD is disabled the CPU clock is always fed from the oscillator input and the PLL is switched off to decrease power supply current ky 2 5 On chip Peripheral Blocks The ST10 family of devices separates peripherals from the core This allows peripherals to be added or deleted without modifications to the core Each functional block processes data independently and communicates information over common buses Peripherals are controlled by data written to the respective Special Function Registers SFRs These SFRs are located either within the standard SFR area 00 FE00h 00 FFFFh or within the extended ESFR area 00 F000h 00 F1FFh The built in peripherals are used for interfacing the CPU to the external world or to provide on chip functions The ST10X167 generic peripherals are Two General Purpose Timer Blo
39. Output Registers Direction Control Registers Threshold Open Drain Control 1514131211109876543210 1514131211109876543210 1514131211109876543210 v v v vy every vv v v opeze Y YOY Y Y Y VOY Y Y Y Y CY OY y Y YYYYYYYYYYYYYY ODP3bE Y YYYYYYYYYYYY ul ote SE YEE YOY Y Yo oc c YYYYYYYY oc YYYYYYYY YYYYYYYY m o YYYYYYYY Bitis linked to a function Bit has no function or is not implemented Register is in ESFR internal memory space c YYYYYYYY m o YYYYYYYY Figure 24 Output drivers in push pull mode and in open drain mode 77 Push Pull Output Driver 6 1 2 Input Threshold Control External Pullup Open Drain Output Driver 77 and feature a defined hysteresis to prevent the The standard inputs of the ST10X167 determine the status of input signals according to TTL levels In order to accept and recognize noisy signals CMOS like input thresholds can be selected instead of the standard TTL thresholds for all pins of Port2 Port3 Port7 and Port8 These special thresholds are defined above the TTL thresholds Gr inputs from toggling while the respective input sig nal level is near the thresholds The Port Input Control register PICON is used to select these thresholds for each Byte of the indi cated ports the 8 Bit ports P7 and P8 are con trolled by one Bit each while ports P2 and P3 are controlled by two Bit each 75 294 ST1
40. Timer Counter x Input Selection Timer Mode TxM 0 Input Frequency fcpu 21 Txl 3 See also table below for examples Counter Mode TxM 1 X00 Overflow Underflow of GPT2 Timer 6 X01 Positive rising edge on pin TxIN 1 X10 Negative falling edge on pin TxIN 1 X11 Any edge rising and falling on pin TxIN 1 Timer Counter x Mode Selection 0 Timer Mode Input derived from internal clock 1 Counter Mode Input from External Input or 6 Timer Counter x Run Control 0 Timer Counter x is disabled Timer Counter x is enabled Note 1 This selection is available for timers TO and T7 Timers T1 and T8 will stop at this selection The run flags TOR T1R T7R and T8R enable or disable the timers The following description of the timer modes and operation always applies to the enabled state of the timers the respective run flag is assumed to be set to 1 In all modes the timers are always counting upward The current timer values are accessible for the CPU in the timer registers Tx which are non Bitaddressable SFRs When the CPU writes to a register Tx in the state immediately before the respective timer increment a reload is to be performed the CPU write operation has priority and the increment or reload is disabled to garantee correct timer operation Timer Mode The Bit TxM in SFRs TO1CON and T78CON selects the timer mode or the counter mode In timer mode TxMz 0 the
41. be turned on or off by software using Bit T3R The timer will only run if T3R 1 and the gate is active It will stop if either T3R 0 or the gate is inactive Note transition of the gate signal at pin does not cause an interrupt request Timer 3 in Counter Mode Counter mode for the core timer T3 is selected by setting Bit field T3M in register T3CON to 001b In counter mode timer T3 is clocked by a transition at the external input pin T3IN which is an alternate function of P3 6 The event causing an increment or decrement of the timer can be a positive a negative or both a positive and a negative transition at this pin Bit field in control register T3CON selects the triggering transition see Table 23 ST10X167 Figure 66 Core timer T3 in gated timer mode 7 Interrupt Core Timer T3 gt Request Up Down Interrupt Request 7 T3OUT P3 3 Table 23 GPT1 core timer T3 counter mode input edge selection Triggering Edge for Counter Increment Decrement 00 None Counter is disabled 001 Positive transition rising edge on T3IN Negative transition falling edge on T3IN Any transition rising or falling edge on T3IN Reserved Do not use this combination 3 133 294 ST10X167 For counter operation pin T3IN P3 6 must be configured as input and direction control Bit DP3 6 must be 0 The maximum input frequency which is allowed in counter
42. complete the boundary pointers are updated to reflect the newly allocated space on the internal stack Thus the user is free to write code without concern for the internal stack limits Only the execution time required by the trap routines affects user programs The following procedure initializes the controller for usage of the circular stack mechanism Specify the size of the physical system stack area within the internal RAM Bitfield STKSZ in register SYSCON Define two pointers which specify the upper and lower boundary of the external stack These values are then tested in the stack underflow and overflow trap routines when moving data Gr F802h Physical stack address FA02h F800h Physical stack address 00 Physical stack address FBFEh Set the stack overflow pointer STKOV to the limit of the defined internal stack area plus six Words for the reserved space to store two interrupt entries The internal stack will now fill until the overflow pointer is reached After entry into the overflow trap procedure the top of the stack will be copied to the external memory The internal pointers will then be modified to reflect the newly allocated space After exiting from the trap procedure the internal stack will wrap around to the top of the internal stack and continue to grow until the new value of the stack overflow pointer is reached When the underflow pointer is reached while the stack
43. onore due 212 Address Arbitration 122 Area Definition 121 33 Segment 1 10 251 ADDRSELX 121 122 ALE length Eee vH 112 44 Analog Digital Converter 24 211 Arbitration Address i eee rtr ree 122 External B s u us re rn 124 ASCO Interrupts 163 Auto Scan conversion 214 B Baudrate BSGO 162 Bootstrap Loader 182 GAN satin MEME E AEE Ei 226 com 174 pem 88 110 Bit addressable memory 29 Handling 40 protected 2 2 exu 40 timing register 22 Bootstrap Loader 179 250 5952 99 rore 33 Burst mode PWM 205 Bus Arbitration 24 GAN Su 22 220 240 Demultiplexed 107 Idle State 123 Mode Configuration 106 250 Multiplexed 106 V 119 284 294 CAN Interface 22 220 CAR COM a aaah tod
44. so their transmit buffers must be loaded with FFFFh prior to any transfer Note A slave with push pull output drivers which is not selected for transmission will Figure 98 SSC error interrupt control Register SSCCON SSCTE Transmit Error SSCTE Receive Error Baudrate Error ky ST10X167 normally have its output drivers switched However in order to avoid possible conflicts misinterpretations it is recommended to always load the slave s transmit buffer prior to any transfer see Figure 98 11 5 SSC Interrupt Control Three interrupt control registers are provided for serial channel SSC Register SSCTIC controls the transmit interrupt SSCRIC controls the receive interrupt and SSCEIC controls the error interrupt of serial channel SSC Each interrupt source also has its own dedicated interrupt vector SCTINT is the transmit interrupt vector SCRINT is the receive interrupt vector and SCEINT is the error interrupt vector The cause of an error interrupt request receive phase Baud rate transmit error can be identified by the error status flags in control register SSCCON Note In contrary to the error interrupt request flag SSCEIR the error status flags 55 are not reset automatically upon entry into the error interrupt service routine but must be cleared by software Register SSCEIR SSCEIE Error gt Interrupt SSCEIR SSCEINT 175 294 ST10X167 SSCTIC F
45. the conversion of the specified channel When the conversion of this channel is complete the result will be placed into the alternate result register ADDAT2 and a Channel Injection Complete Interrupt request will be generated which uses the interrupt request flag ADEIR for this reason the Wait for ADDAT Read Mode is required Channel Injection gt Injected Conversion Request by CC31 of Channel y ADDAT2 Full 777 Interrupt Request 5 ADEINT Read ADDAT2 4 216 294 ky Write ADDAT2 ST10X167 If the temporary data register used in Wait for ADDAT Read Mode is full the respective next conversion standard or injected will be suspended The temporary register can hold data for ADDAT from a standard conversion or for ADDAT2 from an injected conversion Figure 128 Channel injection example with wait for read Conversion of Channel Wait until ADDAT2 is read Write ADDAT x 1 ADDAT Full 1 Read ADDAT 1 Injected Conversion Channel Injection of Channel Request by CC31 Write ADDAT2 ADDAT2 Interrupt Request ADEINT Read ADDAT2 Temp Latch Full Conversion of Channel Write ADDAT 1 ADDAT Full Read ADDAT Temp Latch Full Channel Injection Request by CC31 Wait until ADDAT2 is read ADDAT Full Interrupt Request ADEINT Read ADDAT2 3 217 294 ST10X167 16 2 Conversion Timing Control When a conversion is started first the c
46. timers with the respective auxiliary timers resulting 32 33 Bit timers counters for measuring long time periods with high resolution Various reload or capture functions can be selected to reload timers or capture a timer s contents triggered by an external signal or a selectable transition of toggle latch TxOTL ky ST10X167 2 5 8 Watchdog Timer The Watchdog Timer is a fail safe mechanism It limits the maximum malfunction time of the controller The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in the time interval until the EINIT end of initialization instruction has been executed In this way the chip s start up procedure is always monitored The software must be designed to service the Watchdog Timer before it overflows If due to hardware or software related failures the software fails to do so the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset The Watchdog Timer is a 16 Bit timer clocked with the system clock divided either by 2 or by 128 The high Byte of the Watchdog Timer register can be set to a pre specified reload value stored in WDTREL in order to allow further variation of the monitored time interval Each time itis serviced by the application software the high Byte of the Watchdog Timer is reloaded 2 5 9 Capture Compare CAPCOM Units T
47. 0 R R R R RW R STKUN Modifiable portion of register STKUN Specifies the upper limit of the internal system stack The Stack Underflow Trap entered when SP STKUN may be used in two different ways Fatal error indication treats the stack underflow as a system error through the associated trap service routine Automatic system stack refilling allows to use the system stack as a Stack Cache for a bigger external user stack In this case register STKUN should be initialized to a value which represents the desired highest Bottom of Stack address More details about the stack underflow trap service routine and virtual stack management are given in Chapter 21 System Programming Scope of stack limit control The stack limit control realized by the register pair STKOV and STKUN detects cases where the stack pointer SP is moved outside the defined stack area either by ADD or SUB instructions or by PUSH or POP operations explicit or implicit CALL or RET instructions This control mechanism is not triggered and no stack trap is generated when the stack pointer SP is directly updated via MOV instructions the limits of the stack area STKOV STKUN are changed so that SP is outside of the new limits 4 4 10 The Multiply Divide High Register MDH This register is a part of the 32 Bit multiply divide register which is implicitly used by the CPU when it performs a multiplication or a division After a multi
48. 1 The corresponding Port2 pin is not affected and can be used for general purpose I O However after Figure 112 Compare mode 2 and 3 block diagram ST10X167 the first match has been detected in this mode all further compare events within the same timer period are disabled for compare register CCx until the allocated timer overflows This means that after the first match even when the compare register is reloaded with a value higher than the current timer value no compare event will occur until the next timer period In the example below the compare value in register CCx is modified from cv1 to cv2 after compare event 1 Compare event 2 however will not occur until the next period of timer Ty Capture Register CCx Interrupt COxIR Request gt gt eo Set Port Latch on Mode 3 Reset CCMODx CAPCOM Timer Ty Interrupt TyIR gt Request Note The port latch and pin remain unaffected in compare mode 2 Figure 113 Timing example for compare modes 2 and 3 Contents of Ty FFFFh Compare Value cv2 Compare Value cv1 Interrupt State of Event 1 CCx cv2 t Reload Value lt TyREL gt 0000h Event 2 CCx cv1 Output pin CCxIO only effected in mode 3 No changes in mode 2 195 294 ST10X167 14 5 4 Compare Mode 3 Compare mode 3 is selected for register CCx by setting Bit field CCMODx of the corresponding mode co
49. 11 1 9 8 7 6 2 1 0 0 5 4 3 T T I a RW RW RW RW 6 RW RW RW RW 3 145 294 ST10X167 Timer 6 Input Selection Depends on the Operating Mode see respective sections Timer 6 Mode Control Basic Operating Mode 000 Timer Mode 001 Counter Mode 010 Gated Timer with Gate active low 011 Gated Timer with Gate active high 1 6 Run Bit 0 Timer Counter 6 stops 21 Timer Counter 6 runs Reserved Do not use this combination Timer 6 Up Down Control Timer 6 External Up Down Enable Alternate Output Function Enable T6OE 0 Alternate Output Function Disabled T6OE 1 Alternate Output Function Enabled T6OTL Timer 6 Output Toggle Latch Toggles on each overflow underflow of T6 Can be set or reset by software Timer 6 Reload Mode Enable T6SR 0 Reload from register CAPREL Disabled T6SR 1 Reload from register CAPREL Enabled Note 1 For the effects of Bit TGUD and T6UDE refer to the direction Table 26 Timer 6 run Bit The timer can be started or stopped by software through Bit Timer T6 Run Bit If T6 R 0 the timer stops Setting T6R to 1 will start the timer In gated timer mode the timer will only run if 41 and the gate is active high or low as programmed Count Direction Control The count direction of the core timer can be controlled either by software
50. 130 CAN module address map EFF0h EFEOh EFDOh EFCOh EFBOh EFAOh EF90h EF80h EF70h EF60h EF50h EF40h EF30h EF20h EF10h EFOOh_ Message Object 7 Message Object 6 Message Object 5 Message Object 4 Message Object 3 Message Object 2 Message Object 1 General Registers CAN Address Area Control Status Register EFOOh 14 13 R 15 R Mask of Last Message Global Mask Long Global Mask Short Bit Timing Register Interrupt Register EFO2h Control Status Register EFOOh General Registers ST10X167 Reset Value XX01h 12 A 10 9 8 7 6 5 4 3 2 1 0 w E PPE P RW RW RW RW RW R R RW RW RW RW 223 294 ST10X167 Table 35 CAN Control Status register Function Control Bit Initialization 1 Software initialization of the CAN controller While init is set all message transfers are stopped Setting init does not change the configuration registers and does not stop transmission or reception of a message in progress The init Bit is also set by hardware following a busoff condition the CPU then needs to reset init to start the bus recovery sequence see Figure 139 Disable software initialization of the CAN controller on INI completion the CAN waits for 11 consecutive recessive Bit before taking part in bus activities Interrupt Enable Does not affect status updates 1 Global interrupt enable from CAN module 0 Global interrupt disable from CAN module
51. 16 Bit intra segment address is output on PORTO for multiplexed bus modes or on PORT for demultiplexed bus modes When segmentation is disabled only one 64K Byte segment can be used and accessed Otherwise additional address lines may be output on Port4 and or several chip select lines may be used to select different memory banks or peripherals These functions are selected during reset via Bitfields SALSEL and CSSEL of register RPOH respectively Note Bit SGTDIS of register SYSCON defines if the CSP register is saved during inter rupt entry segmentation active or not segmentation disabled 106 294 8 2 1 Multiplexed Bus Modes In the multiplexed bus modes the 16 Bit intra segment address and data use PORTO The address is time multiplexed with the data and has to be latched externally The width of the required latch depends on the selected data bus width an 8 Bit data bus requires a Byte latch the address Bit A15 A8 on do not change while POL multiplexes address and data a 16 Bit data bus requires a Word latch the least significant address line AO is not relevant for Word accesses The upper address lines An A16 are permanently output on Port4 if segmentation is enabled and do not require latches The EBC initiates an external access by generating the Address Latch Enable signal ALE and then placing an address on the bus The falling edge of ALE triggers an external latch to capture t
52. 19 Power Reduction Modes 3 102 294 ST10X167 Figure 47 Vpp external RC circuit for ST10C167 and ST10R167 ST10C167 200 1 typical ST10R167 Vpp RPD 12 1uF typical Vpp external RC circuit is used for exiting power down mode with external interrupt and for power up asynchronous reset ky 103 294 ST10X167 8 THE EXTERNAL BUS INTERFACE The on chip peripherals and on chip RAM and ROM Flash Memory only cover a small fraction of the ST10X167 address space The external bus interface gives access to external peripherals and additional volatile and non volatile memory It provides a number of configurations and can be tailored to fit perfectly into a given application System see Figure 48 Accesses to external memory or peripherals are executed by the integrated External Bus Controller EBC The function of the EBC is controlled via the SYSCON register and the BUSCONx and ADDRSELx registers The BUSCONx registers specify the external bus cycles in terms of address mux demux data 16 Bit 8 Bit chip selects and length waitstates READY control ALE RW delay These parameters are used for accesses within a specific address area which is defined via the corresponding register ADDRSELx The four pairs BUSCON1 ADDRSEL1 BUSCON4 ADDRSEL4 allow to define four independent address windows while all external accesses outside 104 294 these windows are controlled via BUSCONO registe
53. 4 0 Yes POL 4 0 No POL 4 1 Code fetch from Boot ROM access internal ROM area Data fetch from internal ROM area Loading the Startup Code After sending the identification Byte the BSL enters a loop to receive 32 Byte via ASCO These Byte are stored sequentially into locations 00 FA40h through 00 FA5Fh of the internal RAM So up to 16 instructions may be placed into the RAM area To execute the loaded code the BSL then jumps to location 00 FA40h which is the first loaded instruction The bootstrap loading sequence is now terminated the ST10X167 remains in BSL mode however Most probably the initially loaded routine will load additional code or data as an average application is likely to require substantially more than 16 instructions This second receive loop may directly use the pre initialized interface ASCO to receive data and store it to arbitrary user defined locations This second level of loaded code may be the final application code It may also be another more sophisticated loader routine that adds a transmission protocol to enhance the integrity of the loaded code or data It may also contain a code sequence to change the system configuration and enable the bus interface to store the received data into external memory ky User ROM access User ROM access Boot ROM access User ROM access User ROM access This process may go through several iterations or may directly execute the final a
54. 5 Interrupt Response Times The interrupt response time defines the time from an interrupt request flag of an enabled interrupt source being set until the first instruction 11 being fetched from the interrupt vector location The basic interrupt response time for the ST10X167 is 3 instruction cycles see Figure 21 All instructions in the pipeline including instruction N during which the interrupt request flag is set are completed before entering the service routine The actual execution time for these instructions waitstates therefore influences the interrupt response time In the Figure 21 the respective interrupt request flag is set in cycle 1 fetching of instruction N The indicated source wins the prioritization round during cycle 2 In cycle 3 a TRAP instruction is injected into the decode stage of the pipeline replacing instruction 1 clearing the source s interrupt request flag to 0 Cycle 4 completes the injected TRAP instruction save PSW IP and CSP if segmented mode and fetches the first instruction 11 from the respective vector location All instructions that entered the pipeline after setting of the interrupt request flag N 1 N 2 will be executed after returning from the interrupt service routine Figure 21 Pipeline diagram for interrupt response time Pipeline Stage Cycle 3 Cycle 4 FETCH 2 11 DECODE TRAP 1 TRAP 2 EXECUTE N TRAP WRITEBACK
55. A0 on PORTO or PORT 4 Bit segmented mode 1M Byte with A19 A16 on Port4 and A15 A0 on PORTO or PORT1 8 Bitsegmented mode 16M Byte with A23 A16 on Port4 and A15 A0 on PORTO or PORT1 Each bank can be directly addressed via the address bus while the programmable chip select signals can be used to select various memory banks The ST10X167 also supports four different bus types Multiplexed 16 Bit Bus with address and data on PORTO Default after Reset Multiplexed 8 Bit Bus with address and data on PORTO POL Demultiplexed 16 Bit Bus with address on PORT and data on PORTO Demultiplexed 8 Bit Bus with address on PORT1 and data on POL Memory model and bus mode are selected during reset by pin EA and PORTO pins For further details about the external bus configuration and control See Chapter 8 The External Bus Interface External Word and Byte data can only be accessed via indirect or long 16 Bit addressing modes using one of the four DPP registers There is no short addressing mode for external operands Any Word data access is made to an even Byte address For PEC data transfers the external memory in segment 0 can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers The external memory is not provided for single Bit storage and therefore it is not Bit addressable Gr ST10X167 3 5 Crossing Memory Boundaries The addre
56. Bit 0 Slave Mode Operate on shift clock received via SCLK 15 Master Mode Generate shift clock and output it via SCLK SSCEN SSC Enable Bit 1 Transmission and reception enabled Access to status flags and M S control Note The target of an access to SSCCON control Bit or flags is determined by the state of SSCEN prior to the access Writing C057h to SSCCON in programming mode SSCEN 0 will initialize the SSC SSCEN was 0 and then turn it on SSCEN 1 When writing to SSCCON make sure that reserved locations receive zeros The shift register of the SSC is connected to both the transmit pin and the receive pin via the pin control logic see Figure 94 Transmission and reception of serial data is synchronized and takes place at the same time so the same number of transmitted Bit is also received Transmit data is written into the Transmit Buffer SSCTB It is moved to the shift register as soon as this is empty An SSC master SSCMS 1 immediately begins transmitting while SSC slave SSCMS 0 will wait for an active shift clock When the transfer starts the busy flag SSCBSY is set and a transmit interrupt request SSCTIR will be generated to indicate that SSCTB may be reloaded again When the programmed number of Bit 2 16 has been transferred the contents of ky the shift register are moved to the Receive Buffer SSCRB and a receive interrupt request SSCRIR will be gener
57. Bit Register ADCON input only port The Port5 lines may either be used as analog or digital inputs No special action Its Bit fields specify the analog channel to be is required to configure the Port5 lines as analog acted upon the conversion mode and also reflect inputs the status of the converter ADCON FFA0h DOh SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCTC ADSTC AD AD AD AD ADST ADM ADCH CRQ CIN WR BSY RW RW RW RW RW R RW RW RW 212 294 ky ST10X167 ADC Analog Channel Input Selection ADM ADC Mode Selection 00 Fixed Channel Single Conversion 01 Fixed Channel Continuous Conversion 10 Auto Scan Single Conversion 11 Auto Scan Continuous Conversion ADST ADC Start Bit ADBSY ADC Busy Flag ADBSY 1 a conversion is active ADWR ADC Wait for Read Control ADCIN ADC Channel Injection Enable ADCRQ ADC Channel Injection Request Flag ADSTC ADC Sample Time Control ADC Conversion Time Control Note ADSTC and ADCTC control the con version timing Refer to Section 16 2 Conversion Timing Control Bit field ADCH specifies the analog input channel which is to be converted first channel of a conversion sequence in auto scan modes Bit field ADM selects the operating mode of the A D converter A conversion or a sequence is then started by setting Bit ADST Clearing ADST stops the A D converter after a certain operation which depends on the selected operating mode ADDAT F
58. CLKCFG select the clock generation mode on chip PLL during reset The oscillator clock either directly feeds the CPU and peripherals direct drive or it is fed to the on chip PLL which then provides the CPU clock signal selectable multiple of the oscillator frequency These Bit are latched in register RPOH ST10F167 00 cpu fxraL X F 1 Mss Prescaler morir STIUFTS7 p eee 596 5 ese x O xe ess j 2 50 15 ess j Notes 1 The external clock input range refers to a CPU clock range of 10 to 25 MHz 2 The maximum depends on the duty cycle of the external clock signal 3 Default On chip PLL is active with a factor of 1 4 4 Watch the different requirements for frequency and duty cycle of the oscillator input clock for the possible selections 251 294 ST10X167 19 POWER REDUCTION MODES Two different power reduction modes have been implemented in the ST10X167 Idle mode the CPU is stopped while the peripherals continue their operation Idle mode can be terminated by any reset or interrupt request Power down mode both the CPU and the peripherals are stopped Power Down mode can only be terminated by a hardware reset in protected mode or by an external interrupt Note All external bus actions are completed before Idle or Power Down mode is entered However Idle or Power Down mode i
59. Clock 2n 3 10 GPT1 Timer T4 Interrupt Request T4EUD F N P5 14 K J U D 9 1 1 GPT1 Core Timer T3 The core timer T3 is configured and controlled via its Bitaddressable control register T3CON T3CON FF42h Ath SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTI T 5 RW RW RW RW RW RW RW RW RW RW RW Timer 3 Input Selection Depends on the operating mode see respective sections Timer 3 Mode Control Basic Operating Mode Timer Mode Counter Mode Gated Timer with Gate active low Gated Timer with Gate active high 2 Incremental interface mode not for ST10F 167 Timer Counter runs T3UD Timer 3 Up Down Control T3UDE Timer 3 External Up Down Enable Alternate Output Function Enable 0 Alternate Output Function Disabled T3OE 1 Alternate Output Function Enabled T3OTL Timer 3 Output Toggle Latch Toggles on each overflow underflow of Can be set or reset by software Note 1 For the effects of Bit T3UD and T3UDE refer to the direction Table 21 130 294 Timer 3 Run Bit The timer can be started or stopped by software through Bit T3R Timer Run Bit If T3R 0 the timer stops Setting T3R to 1 will start the timer In gated timer mode the timer will only run if T3R 1 and the gate is active high or low as programmed Count Direction Control The c
60. ESFR SFR SFR SFR SFR SFR ESFR SFR SFR SFR SFR SFR SFR SFR Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value SFR ESFR XReg Reset Value SFR ESFR XReg Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value Reset Value ST10X167 289 294 ST10X167 STKOV FE14h 0Ah STKUN FE16h 0Bh SYSCON FF12h 89h SYSCON FF12h 89h SYSCON FF12h 89h T01CON FF50h A8h TOIC FF9Ch CEh T1IC FF9Eh CFh T2CON FF40h A0h T2IC FF60h BOh T3CON FF42h A1h FF62h B1h T4CON FF44h A2h T4IC FF64h B2h T5CON FF46h A3h T5IC FF66h B3h T6CON FF48h A4h T6IC FF68h B4h T78CON FF20h 90h T7IC F17Ah BEh T8IC F17Ch BFh FFACh D6h Upper Arbitration Reg EFn2h Upper Global Mask Long EF08h Upper Mask of Last Message EF0Ch WDTCON FFAEh D7h yyyyh zzh ZEROS FF1Ch 8Eh 290 2
61. EXTR is not required for this access 2 The scope of the 4 instruction ends here MOV T8REL R1 T8REL uses 16 Bit address R1 is duplicated and does not require switching Gr 31 294 ST10X167 In order to minimize the use of the EXTR instructions the ESFR area mostly holds registers which are required for initialization and mode selection Wherever possible registers that need to be accessed frequently are allocated in the standard SFR area Note The tools are equipped to monitor accesses to the ESFR area and will auto matically insert EXTR instructions or issue a warning in case of missing or excessive EXTR instructions 3 3 The On chip XRAM The XRAM area is located within data page 3 and provides access to 2K Byte of on chip RAM organized as 1K x 16 As the XRAM is connected to the internal XBUS it is accessed like external memory however no external bus cycles are executed for these accesses XRAM accesses are globally enabled or disabled via Bit XPEN in the SYSCON register This Bit is cleared after reset and may be set via software during the initialization to allow accesses to the on chip XRAM When the XRAM is disabled default after reset all accesses to the XRAM area are mapped to external locations The XRAM may be used for both code instructions and data variables user stack tables etc storage Code fetches are always made on even Byte addresses The highest possible code stora
62. Figure 142 SRST instruction Internal watchdog overflow Reset Signal Reset Sequence 512 CPU Clock Cycles Asynchronous Reset UE i Vpp Flash device From to Exit Powerdown Circuit Weak pull down 200uA 241 294 ST10X167 18 1 Types of Reset Whenever one of the reset conditions occurs the microcontroller is reset into its predefined default state through an internal reset procedure When a reset is initiated pending internal hold states are cancelled An external bus cycle is aborted except for a watchdog reset see description After that the bus pin drivers and the I O pin drivers are switched off tristate RSTOUT is activated depending on the reset source The internal reset procedure takes 516 CPU clock cycles 1032 for asynchronous reset to perform a complete reset sequence The reset sequence starts on a watchdog timer overflow an SRST instruction or when the reset input signal RSTIN is sampled low hardware reset The internal reset condition is active Only during the RSTIN input pulse asynchronous mode ensure that the duration meets circuit requirements see Section 18 1 3 Asynchronous Hardware Reset At least for the duration of the reset sequence and then until the RSTIN input is inactive synchronous mode When this internal reset condition is removed the reset configuration is latched from PORTO and pins ALE RD and WR are driven to their ina
63. O lines 22 294 2 5 5 Serial Channels Serial communication with other microcontrollers processors terminals or external peripheral components is provided by two serial interfaces with different functionality an Synchronous Serial Channel ASCO and a High Speed Synchronous Serial Channel SSC They support full duplex asynchronous communication and half duplex synchronous communication The SSC may be configured so it interfaces with serially linked peripheral components Two dedicated Baud rate generators allow to set up all standard Baud rates without oscillator tuning For transmission reception and error handling 3 separate interrupt vectors are provided on channel SSC 4 vectors are provided on channel ASCO In asynchronous mode 8 or 9 Bit data frames are transmitted or received preceded by a start Bit and terminated by one or two stop Bit For multiprocessor communication a mechanism to distinguish address from data Byte has been included 8 Bit data plus wake up Bit mode In synchronous mode the ASCO transmits or receives Byte 8 Bit synchronously to a shift clock which is generated by the ASCO The SSC transmits or receives characters of 2 16 Bit length synchronously to a shift clock which can be generated by the SSC master mode or by an external master slave mode The SSC can start shifting with the LSB or with the MSB while the ASCO always shifts the LSB first A loop ba
64. POUT1 POUT2 POUT3 CC28 I O CC29 I O CC30 I O CC31 I O PWM mode channel 0 output PWM mode channel 1 output PWM mode channel 2 output PWM mode channel 3 output Capture input compare output channel 28 Capture input compare output channel 29 Capture input compare output channel 30 Capture input compare output channel 31 96 294 ST10X167 Figure 42 Port7 I O and alternate functions P7 7 C3110 P7 6 P7 5 CC2910 P7 4 CC28IO P7 3 POUT3 P7 2 POUT2 P741 POUTI P7 0 POUTO General Purpose Input Output Alternate Function The structure of Port7 differ in the way the output latches are connected to the internal bus and to the pin driver see Figure 43 and Figure 44 Pins P7 3 P7 0 POUTS POUTO XOR the alternate data output with the port latch output which allows to use the alternate data directly or inverted at the pin driver Figure 43 Block diagram of Port7 pins P7 3 P7 0 Write 7 Latch Read 0DP7 y Write DP7 y Direction Latch Read DP7 y lt I Alternate Data Internal Bus Output Write P7 y Port Data gt Port Output Output Output Latch Buffer Read P7 y 1 amp lt MUX 0 ky 97 294 ST10X167 Pins P7 7 P7 4 CC311O CC281O combine internal bus data and alternate data output before the port latch input as do the Port2 pins Figure 44 Block diagram
65. RAM 00 FFFFh 00 FEOOh the second register block the Extended SFR ESFR area is located in the 512 Byte below the internal RAM 00 F1FFh 00 F000h Special function registers can be addressed via indirect and long 16 Bit addressing modes Using an 8 Bit offset together with an implicit base address makes it possible to address Word SFRs and their respective low Byte This does not work for the respective high Byte Note Writing to any Byte of an SFR causes the non addressed complementary Byte to be cleared The upper half of each register block is Bit addressable so the respective control status Bit can be directly modified or checked by using Bit addressing When accessing registers in the ESFR area using 8 Bit addresses or direct Bit addressing Extend Register EXTR instruction is required before to switch the short addressing mechanism from the standard SFR area to the Extended SFR area This is not required for 16 Bit and indirect addresses The GPRs R15 RO are duplicated and they are accessible within both register blocks via short 2 4 or 8 Bit addresses without switching Example EXTR 4 Switch to ESFR area for the next 4 instructions MOV ODP2 datal6 ODP2 uses 8 Bit reg addressing BFLDL DP6 datas8 Bit addressing for Bit fields mask BSET DPlh 7 Bit addressing for single Bit MOV T8REL R1 I8REL uses 16 Bit address R1 is duplicated and also accessible via the ESFR mode
66. RO BASE Move table base into RO LOOP CMP R1 RO Compare target to table entry JMPR cc NET LOOP Test whether target is not found AND the end of table P has not been reached Note The last entry in the table must be equal to the lowest signed integer 8000h 21 5 Peripheral Control and Interface All communication between peripherals and the CPU is performed either by PEC transfers to and from internal memory or by explicitly addressing the SFRs associated with the specific peripherals After resetting the ST10X167 all peripherals except the watchdog timer are disabled and initialized to default values A desired configuration of a specific peripheral is programmed using MOV instructions of either constants or memory values to specific SFRs Specific control flags may also be altered via Bit instructions Once in operation the peripheral operates autonomously until an end condition is reached at which time it requests a PEC transfer or requests CPU servicing through an interrupt routine Information may also be polled from peripherals through read accesses to SFRs or Bit operations including branch tests on specific control Bit in SFRs To ensure proper allocation of peripherals among multiple tasks a portion of the internal memory has been made Bit addressable to allow user semaphores Instructions have also been provided to lock out tasks via software by setting or clearing user specific Bit and conditionally branching ba
67. Select Register 1 4 BUSCONx Bus Mode Control Register 0 4 SYSCON System Control Register RPOH Port POH Reset Configuration Register 3 SYSCON BUSCONO BUSCON1 BUSCON2 BUSCONS BUSCON4 PORTO PORT ALE RD Control Registers 15 14 13 1211109876543210 YYYYYYYYYYYYYYYY YYYY Y YYY Mode Registers 1514131211109876543210 WR WRL BHE WRH Y Bit is linked to a function Bit has no function or is not implemented E Register is in ESFR internal memory space 105 294 ST10X167 8 2 External Bus Modes When the external bus interface is enabled Bit BUSACTx 1 and configured Bitfield BTYP the ST10X167 uses a subset of its port lines together with some control lines to build the external bus BTYP External Data Encoding Bus Width External Address Bus Mode 8 Bit Data Demultiplexed Addresses 8 Bit Data Multiplexed Addresses 16 Bit Data Demultiplexed Addresses 16 Bit Data Multiplexed Addresses The bus configuration BTYP for the address windows BUSCONA BUSCON 1 is selected by software usually during the initialization of the system The bus configuration BTYP for the default address range BUSCONO is selected via PORTO during reset provided that pin EA is low during reset Otherwise BUSCONO may be programmed via software just like the other BUSCON registers The 16M Byte address space of the ST10X167 is divided into 256 segments of 64K Byte each The
68. Set SP before last entry of physical stack of 256 Words pe SB PUSH R1 SP PUSH R2 SP F7FEh The effect of the address transformation is that the physical stack addresses wrap around from the end of the defined area to its beginning When flushing and filling the internal stack this circular stack mechanism only requires to move that portion of stack data which is really to be re used the upper part of the defined stack area instead of the whole stack area Stack data that remain in the lower part of the internal stack need not be moved by the distance of the space being flushed or filled as the stack pointer automatically wraps around to the beginning of the freed part of the stack area Note This circular stack technique is applicable for stack sizes of 32 to 512 Words STKSZ 000b to 100b it does not work with option STKSZ 111b which uses the complete internal RAM for system stack In the latter case the address transforma tion mechanism is deactivated When a boundary is reached the stack underflow or overflow trap is entered where the user moves a predetermined portion of the internal stack to or from the external stack The amount of data transferred is determined by the average stack space required by routines and the frequency of calls traps interrupts and returns In most cases this will be approximately one quarter to one tenth the size of the internal stack Once the transfer is
69. When they are accessed they deactivate READY READY until the bus cycle is complete then drive it low again If however the peripheral deactivates READY READY after the first sample point of the ST10X167 the controller samples an active READY READY and terminates the current bus cycle which of course is too early By inserting predefined wait states the first READY READY sample point can be shifted to a time where the peripheral has safely controlled the READY READY line after 2 wait states in the Figure 57 Note For the ST10X167 the active level of the ready pin is set to READY For the ST10C167 and ST10R167 the active level of the ready pin can be set to READY or READY by the RDYPOL Bit in the BUS CON register 8 3 7 Programmable Chip Select Timing Control The position of the CS lines can be changed for the ST10C167 and ST10R167 By default after reset the CS lines change half a CPU clock cycle after the rising edge of ALE With the CSCFG Bit set in the SYSCON register the CS lines change with the rising edge of ALE therefore the CS lines change at the same time that the address lines are changed This feature is not available for the ST10F167 Figure 58 Chip select delay Normal Demultiplexed Address P1 Segment P4 Normal CS cae Read Write gt Delay 8 4 Controlling the External Bus Controller A set of registers controls the functions of the EBC General features like the us
70. Write DP2 y Direction Latch Read DP2 y Internal Bus l 1 Y Y Alternate D gt Output Data 0 Output Write Port P2 y Compare Trigger Read P2 y Alternate data input 4 Fast external interrupt input lt 3 84 294 ST10X167 6 5 Port3 mode by the open drain control register ODP3 If this 15 Bit port is used for general purpose I O pins P3 15 P3 14 and P3 12 do not support open the direction of each line can be configured by the drain mode corresponding direction register DP3 Most port Due to pin limitations register Bit P3 14 is not con lines can be switched into push pull or open drain nected to an output pin P3 FFC4h E2h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW DP3 FFC6h E3h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RW RW RW RW RW Port direction register DP3 Bit y DP3 y 0 Port line P3 y is an input high impedance DP3 y 1 Port line P3 y is an output ODP3 F1C6h ESFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Port3 Open Drain control register Bit y ODP3 y 0 Port line P3 y output driver in push pull mode ODP3 y 1 Port line P3 y output driver in open drain mode 3 85 294 ST10X167 6 5 1 Alternate Functions of Port3 The pins of Port3 are used for various functions which include external timer contro
71. Y Y Y Y YYYYYYYYNY Y Y zo Ta MY Y Yo Y eco T8 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Tb goce s keen NC NOME M T4 Y Y YY YYYYYY YY YY Y X Y Y Control Registers Interrupt Control 15141312111098 76543210 15141312111098 76543210 T2CON Y Y Y Y Y Y YYYYYYYY Y Y h Bees x s CY Y Y Y Y Y Y TSCON YY Y Y Y Y Y YYYYYYYY Y Y n Y Y Y Y Y Y Y Y T4CON Y Y Y Y Y Y YYYYYYYY Y Y a Bye e esc c Y Y Y Y Y Y Y Y T2IN P3 7 T2EUD P5 15 TSIN P3 6 T3EUD P3 4 T4IN P3 5 T4EUD P5 14 T30UT P3 3 ODP3 Port 3 Open Drain Control Register GPT1 Timer 2 Register DP3 Port 3 Direction Control Register GPT1 Timer 3 Register P3 Port 3 Data Register GPT1 Timer 4 Register T2CON GPT1 Timer 2 Control Register GPT1 Timer 2 Interrupt Control Register Timer 3 Control Register GPT1 Timer 3 Interrupt Control Register T4CON GPT1 Timer 4 Control Register GPT1 Timer 4 Interrupt Control Register Y Bit is linked to a function Bit has no function or is not implemented E Register is in ESFR internal memory space 129 294 ST10X167 Figure 64 GPT1 block diagram T2EUD P5 15 y U D GPT1 Timer T2 Interrupt CPU Clock Request 2n n 3 10 T 7 N Mode 1 P37 WA Control Reload CPU Clock 2n 3 10 TS T3OUT Mode T3IN Control GPT1 Timer T3 T3OTL P3 6 m T3EUD e up j P3 4 KA Capture uc Interrupt TAIN ode Request P3 5 Control 11 CPU
72. an internal reset sequences caused by a WDT reset or a SW Reset i e bidirectional reset transforms an internal WDT reset or SW reset into an external hardware reset with a minimum duration of 516 CPU cycles if Vpp is high Consequently during a WDT reset or SW reset the device behaves as if it was in external hardware reset Note the state of the Vpp pin will determin whether the reset is asynchronous or synchronous The hardware implementation is shown in Figure 144 The PORTO sample timing for bidirectional reset is shown in Figure 145 243 294 ST10X167 NOTES 1 After the execution of the EINIT instruction the bidirectional reset configuration can not be changed 2 WDTCON Bit 1 of the WDTR register is cleared after a hardware reset 3 The PORTO0 configuration is transparent and latched as for a power on or PDW Reset 4 The bootstrap loader can be started by a WDT reset or SW Reset if the bidirectional reset is enabled and P0L 4 is low 5 If bidirectional reset is enabled then the RSTIN pin may only be connected to external reset devices with an open drain output driver connection to a push pull output driver can damage the RSTIN input 18 2 Pins After Reset After the reset sequence the different groups of pins of the ST10X167 are activated in different ways depending on their function Bus and control signals are activated immediately after the reset sequence according to the configuration latch
73. applications branch instructions have been optimized to require one extra instruction cycle only when a branch is taken This is implemented by pre calculating the target address while decoding the instruction To decrease loop execution overhead three enhancements have been provided 1 Single cycle branch execution is provided after the first iteration of a loop Therefore only one instruction cycle is lost during the execution of the entire loop In loops which fall through upon completion no instruction cycle is lost when exiting the loop No special instruction is required to perform loops and loops are automatically detected during execution of branch instructions 2 Detection of the end of a table avoids the use of two compare instructions embedded in loops One simply places the lowest negative number at the end of the specific table and specifies branching if neither this value nor the compared value have been found Otherwise the loop is terminated if either condition has been met The terminating condition can then be tested 3 The third loop enhancement provides more flexible solution than the Decrement and Skip on Zero instruction which is found in other microcontrollers Through the use of Com pare and Increment or Decrement instruc tions the user can make comparisons to any value This allows loop counters to cover any range This is particularly powerful in table searching 15 294 ST10X167 Saving of
74. be passed on the system stack without additional software overhead The PCALL push and call instruction first pushes the reg operand and the IP contents onto the system stack and then passes control to the subroutine specified by the caddr operand When exiting from the subroutine the RETP return and pop instruction first pops the IP and then the reg operand from the system stack and returns to the calling program Cross Segment Subroutine Calls Calls to subroutines in different segments require the use of the CALLS call inter segment subroutine instruction This instruction preserves both the CSP code segment pointer and IP on the system stack Upon return from the subroutine a RETS return from inter segment subroutine instruction must be used to restore both the CSP and IP This ensures that the next instruction after the CALLS instruction is fetched from the correct segment Note Itis possible to use CALLS within the same segment but still two Words of the stack are used to store both the IP and CSP Providing Local Registers for Subroutines For subroutines which require local storage the following methods are provided Alternate bank of registers Upon entry into a subroutine it is possible to specify a new set of local registers by executing the SCXT switch context instruction This mechanism does not provide a method to recursively call a subroutine Gr ST10X167 Saving and restoring of regis
75. can be concatenated with the core timer or they may be used as reload or capture registers in conjunction with the core timer The auxiliary timers have no output toggle latch and no alternate output function The individual configuration for timers T2 and T4 is determined by their Bitaddressable control registers T2CON and T4CON which are both organized identically Note that functions which are present in all the 3 timers of block GPT1 are controlled in the same Bit positions and in the same manner in each of the specific control registers Reset Value 0000h 14 11 ae 0 T4CON FF44h A2h 15 14 11 Reset Value 0000h 1 0 DUE Tp pep T NE UE Timer x Input Selection Depends on the Operating Mode see respective sections Timer x Mode Control Basic Operating Mode Timer Mode Counter Mode Gated Timer with Gate active low Gated Timer with Gate active high Reload Mode Capture Mode Incremental interface mode not for ST10F167 Reserved Do not use this combination Timer x Run Bit TxR 0 TxR 1 Timer Counter x stops Timer Counter x runs Timer x Up Down Control Timer x External Up Down Enable Note 1 For the effects of Bit TxUD and TxUDE refer to the direction Table 24 section 137 294 ST10X167 Count Direction Control for Auxiliary Timers The count direction of the auxiliary timers can be
76. can put its data onto the master s receive line Only receiving of data from the master is possible The master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave The selected slave then switches its ky Device 2 MRST line to output until it gets a de selection signal or command The slaves use open drain output on MRST This forms a And wired connection The receive line needs an external pull up in this case Corruption of the data on the receive line sent by the selected slave is avoided when all slaves which are not selected for transmission to the master only send ones 1 Since this high level is not actively driven onto the line but only held through the pull up device the selected slave can pull this line actively to a low level when transmitting a zero Bit The master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave 171 294 ST10X167 After performing all necessary initialization of the SSC the serial interfaces can be enabled For a master device the alternate clock line will now go to its programmed polarity The alternate data line will go to either 0 or 1 until the first transfer will start After a transfer the alternate data line will always remain at the logic level of the last transmitted data Bit When the serial
77. eene enn OUTPUT PIN STATUS REGISTER SET REGISTER DESCRIPTION FORMAT GENERAL PURPOSE REGISTERS GPRS essere SPECIAL FUNCTION REGISTERS ORDERED BY NAME _ REGISTERS ORDERED BY ADDRESS 1 4 sese eren SPECIAL NOTES IDENTIFICATION REGISTERS rne etd tete iiaa ayasa SYSTEM PROGRAMMING STACK OPERATIONS REGISTER BANKING PROCEDURE CALL ENTRY AND EXIT a TABLE SEARCHING PERIPHERAL CONTROL AND INTERFACE essere nns FLOATING POINT SUPPORT 222 225 228 230 239 240 241 242 242 242 243 243 243 244 247 252 252 253 253 253 256 257 257 257 259 265 271 271 273 275 278 278 280 ST10X167 21 7 TRAP INTERRUPT ENTRY AND 281 21 8 INSEPARABLE INSTRUCTION SEQUENCES 1 eene 281 21 9 OVERRIDING THE DPP ADDRESSING _ 281 21 10 HANDLING THE INTERNAL 282 21 11 PITS TRAPS AND MINES ceti inii dere esee as na a ER Eds ha 283 22 KEY WORD 284 23 INDEX OF 8 2 444042 288 24 REVISION HISTORY 2 29
78. etc however will interrupt the atomic sequence since it indicates a severe hardware problem The interrupt inhibit caused by an ATOMIC instruction gets active immediately and no other instruction will enter the pipeline except the one that follows the ATOMIC instruction and no interrupt request will be serviced in between All instructions requiring multiple cycles or hold states are regarded as one instruction in this sense example MUL is one instruction Any instruction type can be used within an inseparable code sequence EXAMPLE ATOMIC 3 The following 3 instructions locked No NOP required OV RO 41234H Instruction 1 no other instr enters the pipeline OV R1 45678H Instruction 2 UL RO R1 Instruction 3 MUL regarded as one instruction OV R2 MDL This instruction is out of the scope of the ATOMIC instruction sequence 21 9 Overriding the DPP Addressing Mechanism The standard mechanism to access data locations uses one of the four data page pointers DPPx which selects a 16K Byte data page and a 14 Bit offset within this data page The four DPPs allow immediate access to up to 64K Byte of data In applications with big data arrays especially in HLL applications using large memory models this may require frequent reloading of the DPPs even for single accesses The EXTP extend page instruction allows switching to an arbitrary data page for 1 4 instructions without havin
79. from the programmed Baud rate by more than 10095 it either is more than double or less than half the expected Baud rate This condition sets the error flag SSCBE and when enabled via SSCBEN the error interrupt request flag SSCEIR Using this error detection capability requires that the slave s Baud rate generator is programmed to the same Baud rate as the master device ky This feature detects false additional or missing pulses on the clock line within a certain frame Note If this error condition occurs and Bit SSCAREN 1 an automatic reset of the SSC will be performed in case of this error This is done to re initialize the SSC if too few or too many clock pulses have been detected A Transmit Error Slave mode is detected when a transfer was initiated by the master shift clock gets active but the transmit buffer SSCTB of the slave was not updated since the last transfer This condition sets the error flag SSCTE and when enabled via SSCTEN the error interrupt request flag SSCEIR If a transfer starts while the transmit buffer is not updated the slave will shift out the old contents of the shift register which normally is the data received during the last transfer This may lead to the corruption of the data on the transmit receive line in half duplex mode open drain configuration if this slave is not selected for transmission This mode requires that slaves not selected for transmission only shift out ones
80. in one instruction cycle For example shift and rotate instructions are processed in instruction cycle independent of the number of Bit to be shifted Multiple cycle instructions have been optimized branches are carried out in 2 CPU clock cycles 16 x 16 Bit multiplication in 5 CPU clock cycles and a 32 16 Bit division in 10 CPU clock cycles The jump cache reduces the execution time of repeatedly performed jumps in a loop from 2 CPU clock cycles to 1 CPU clock cycle The instruction cycle time has been reduced by instruction pipelining This technique allows the core CPU to process in parallel portions of 14 294 multiple sequential instruction stages The following four stage pipeline provides the optimum balancing for the CPU core Fetch In this stage an instruction is fetched from the internal ROM or RAM or from the external memory based on the current IP value Decode In this stage the previously fetched instruction is decoded the required operands are fetched Execute In this stage the specified operation is performed on the previously fetched operands Write back In this stage the result is written to the specified location If this technique is not used each instruction would require four instruction cycles Pipelining offers increased performance ky 2 2 High Function 8 Bit and 16 Bit ALU All standard arithmetic and logical operations are performed in a 16 Bit ALU I
81. inputs This is called the alternate input or output ky ST10X167 function of a port pin in contrast to its function as a general purpose O pin 2 5 2 Peripheral Timing Internal operation of CPU and peripherals is based on the CPU clock The on chip oscillator derives the CPU clock from the crystal or from the external clock signal The clock signal which is gated to the peripherals is independent from the clock signal which feeds the CPU During Idle mode the CPU s clock is stopped while the peripherals continue their operation Peripheral SFRs may be accessed by the CPU once per state When an SFR is written to by software in the same state where it is also to be modified by the peripheral the software write operation has priority Further details on peripheral timing are included in the specific sections about each peripheral 2 5 3 Programming Hints Access to SFRs All SFRs reside in data page 3 of the memory space The following addressing mechanisms are used to access the SFRs Indirect or direct addressing with 16 Bit mem addresses it must be guaranteed that the used data page pointer DPPO DPP3 selects data in memory space page 3 accesses via the Peripheral Event Controller PEC use the SRCPx and DSTPx pointers instead of the data page pointers short 8 Bit reg addresses to the standard SFR area do not use the data page pointers but directly access the registers within
82. into the special register RPOH This read only register holds the selection for the number of chip selects and segment addresses Software can read this register in order to react 78 294 according to the selected configuration if required When the reset is terminated the internal pull up devices are switched off and PORTO will be switched to the appropriate operating mode During external accesses in multiplexed bus modes PORTO first outputs the 16 Bit intra seg ment address as an alternate output function PORTO is then switched to high impedance input mode to read the incoming instruction or data In 8 Bit data bus mode two memory cycles are required for Word accesses the first for the low Byte and the second for the high Byte of the Word During write cycles PORTO outputs the data Byte or Word after outputting the address During exter nal accesses in de multiplexed bus modes PORTO reads the incoming instruction or data Word or out puts the data Byte or Word see Figure 26 When an external bus mode is enabled the direc tion of the port pin and the loading of data into the port output latch are controlled by the bus control ler hardware The input of the port output latch is disconnected from the internal bus and is switched to the line labeled Alternate Data Out put via a multiplexer The alternate data can be the 16 Bit intra segment address or the 8 16 Bit data information The incoming data on PORTO is read on
83. jump instructions that refer to flags evaluate the specified Bit to determine if the jump is to be taken Note Bit operations on undefined Bit locations will always read a Bit value of 0 while the write access will not effect the respective Bit location All instructions that change single Bit or Bit groups internally use a read modify write sequence that accesses the whole Word containing the specified Bit s This method has several consequences Bit can only be modified within the internal specific address areas IRAM SFRs External locations cannot be used with Bit instructions The upper 256 Byte of the SFR area the ESFR area and the internal RAM are Bit addressable see Chapter 3 Memory Organization Those register bits located within the respective sections can be directly manipulated using bit instructions The other SFRs must be accessed Byte or Word wise Note All GPRs are Bit addressable indepen dently of the allocation of the register bank via the context pointer Even GPRs which are allocated in not Bit addressable RAM locations provide this feature The read modify write approach may be critical with hardware effected Bit In these cases the hardware may change specific Bit while the read modify write operation is in progress where the writeback would overwrite the new Bit value generated by the hardware The solution is either the implemented hardware protection see below o
84. latched into register RPOH upon reset the value on the lower Byte POL directly influences the BUSCONO register bus mode or the internal control logic of the ST10X167 247 294 ST10X167 Not all Port0 Bit are latched after the end of an internal reset Depending on the reset type different Bit are latched When RSTIN goes active the PORTO configuration input pins are not transparent for the first 1024 TCL After that time only the pins are transparent and will be latched when internal reset signal becomes inactive see Figures 144 145 and 146 To avoid unexpected behavior the level of the PORTO configuration input pins should not change while PORTO is transparent Table 38 0 Latched Configuration for the Different Resets X Pin is sampled Pin is not sampled Chip Selects gt EE Bus Type Pots o i 8 5 lt v 2 o o0 Sample event Software Reset Watchdog Reset EBEN Short Hardware Reset X x Long Hardware Reset x X x X X X X Power onReset_ x x x x x x Table 39 PortO Bit latched into the different registers after hardware reset 0 Bit nber Porto Bit CLKCFG CLKCFG CLKCFG SALSEL SALSEL CSSEL CSSEL WRC BUSTYP BUSTYP Name gt fel ros ree maa lela eoa esea
85. latches If the alternate output function of a port pin is used by a peripheral the state of the pin is determined by the operation of the peripheral Port pins which are used for bus control functions go into that state which represents the inactive state of the respective function WR or to a defined state which is based on the last bus access BHE Port pins which are used as external address data bus hold the address data which was output during the last external memory access before entry into Idle mode under the following conditions POH outputs the high Byte of the last address if a multiplexed bus mode with 8 Bit data bus is used otherwise POH is floating POL is always floating in Idle mode PORT1 outputs the lower 16 Bit of the last address if a demultiplexed bus mode is used otherwise the output pins of PORT1 represent the port latch data PORT4 outputs the segment address for the last access on those pins that were selected during reset otherwise the output pins of Port4 represent the port latch data During power down mode the oscillator and the clocks to the CPU and to the peripherals are turned off Like in Idle mode all port pins which are configured as general purpose output pins output the last data value which was written to their port output latches When the alternate output function of a port pin is used by a peripheral the state of this pin is determined by the last action of the peripheral before the
86. lt ALE Idle State Multiplexed Bus Cycle lt 109 294 ST10X167 Bus Mode 8 Bit Multiplexed 8 Bit Demultipl 16 Bit Multiplexed High 16 Bit Demultipl 1 5 1 5 3 Very high 1 1 2 Note PORT1 gets available for general purpose I O when none of the BUSCON registers selects a demultiplexed bus mode 8 2 5 Disable Enable Control for Pin BHE BYTDIS Bit BYTDIS is provided for controlling the active low Byte High Enable BHE pin The function of the BHE pin is enabled if the BYTDIS Bit contains a 0 Otherwise it is disabled and the pin can be used as standard I O pin The BHE pin is implicitly used by the External Bus Controller to select one of two Byte organized memory chips which are connected to the ST10X167 via a Word wide external data bus After reset the BHE function is automatically enabled BYTDIS 0 if a 16 Bit data bus is selected during reset otherwise it is disabled BYTDIS 1 It may be disabled if Byte access to 16 Bit memory is not required and the BHE signal is not used 8 2 6 Segment Address Generation During external accesses the EBC generates a programmable number of address lines on Port4 which extend the 16 Bit address output on PORTO or PORT1 and so increase the accessible address space The number of segment address lines is selected during reset and coded in Bit field SALSEL in register RPOH see table below Directly accessible Segment 11 Tw
87. means of communication between CPU and CAN controller Figure 132 Message object address map Each of the 15 message objects uses 15 consecutive Byte see Figure 132 and starts at Object Start Address an address that is a multiple of 16 v Message Control 0 Note All message objects must be initialized by 2 the CPU even those which are not going to Arbitration be used before clearing the INIT Bit 4 Each element of the Message Control Register is Message Config 6 This special mechanism allows the selective 10 setting or resetting of specific elements leaving others unchanged without requiring 12 read modify write cycles None of these elements 14 will be affected by reset Table 37 Functions of complementary Bit of message control register Function on Write Meaning on Read Set element Element is set Leave element unchanged Reserved 228 294 ky ST10X167 Message Control Register EFn0h XReg Reset Value UUUUh 1 14 11 5 13 12 10 9 8 7 6 5 4 3 2 1 0 RMTPND TXRQ MSGLST NEWDAT MSGVAL TXIE RXIE INTPND CPUUPD RW RW RW RW RW RW RW RW INTPND Interrupt Pending Indicates if this message object has generated an interrupt request see TXIE and RXIE since this Bit was last reset by the CPU or not RXIE Receive Interrupt Enable Defines if Bit INTPND is set after successful reception of a frame TXIE Transmit Interrupt Enable Defines if Bit INTPND is set after successful transmission of a fr
88. message object the identifier of this message object is updated If some of the identifier Bit are set to don t care by the corresponding mask register these Bit may be changed in the message object If a remote frame is received the identifier in transmit object remain unchanged except for the last message object which cannot start a transmission Here the identifier Bit corresponding to the don t care Bit of the last message objects mask may be overwritten by the incoming message Upper Arbitration Reg EFn2h XReg Reset Value UUUUh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW Lower Arbitration Reg EFn4h XReg Reset Value UUUUh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 88 j RW R R R RW Identifier 29 Bit Identifier of a standard message ID28 18 or an extended message ID28 0 For standard identifiers Bit ID17 0 are don t care 230 294 ST10X167 Message Configuration and Data extended XTD 1 Data frames only match The following fields hold a description of the with receive objects remote frames only message within this object The data field match with transmit objects occupies the following 8 Byte positions after the When the CAN controller stores a data Message Configuration Register frame it will write all the eight data Byte into Note There is no don t care option for Bit XTD a message object If the data length code and DIR So incoming frames c
89. mode is fcpU 16 To ensure that a transition of the count input signal which is applied to T3IN is correctly recognized its level should be held high or low for at least 8 CPU clock cycles before it changes Timer 3 in Incremental Interface Mode Note This function is not available for ST10F167 Incremental interface mode for the core timer T3 is selected by setting Bit field T3M in register T3CON to 110b In incremental interface mode the two inputs associated with timer T3 T3IN T3EUD are used to interface to an incremental encoder T3 is clocked by each transition on one or both of the external input pins which gives 2 fold or 4 fold resolution to the encoder input see Figure 68 Bitfield in control register T3CON selects the triggering transitions see Table 24 In this mode the sequence of the transitions of the two input signals is evaluated and generates count pulses as well as the direction signal So T3 is modified automatically according to the speed and the direction of the incremental encoder and its contents therefore always represent the encoder s current position The incremental encoder can be connected directly to the MCU without external interface logic In a standard system however comparators will be employed to convert the encoder s differential outputs as A and A to digital signals as A digital signals this greatly increases noise immunity The third encoder output TopO which i
90. modes which are not frequently used This decreases the instruction decode time while also simplifying the development of compilers and assemblers To provide most frequently used instructions with one word instruction formats All other instructions are placed into two word formats This allows all instructions to be placed on Word boundaries which alleviates the need for complex alignment hardware It also has the benefit of increasing the range for relative branching instructions The high performance offered by the hardware implementation of the CPU can efficiently be used by a programmer via the highly functional ST10X167 instruction set Possible operand types are Bit Byte and Words Specific instruction support the conversion extension of Byte to 16 294 Words A variety of direct indirect or immediate addressing modes are provided to specify the required operands 2 2 4 Programmable Multiple Priority Interrupt System The following enhancements have been included to allow processing of a large number of interrupt Sources Peripheral Event Controller PEC This processor is used to off load many interrupt requests from the CPU It avoids the overhead of entering and exiting interrupt or trap routines by performing single cycle interrupt driven Byte or Word data transfers between any two locations segment 0 with an optional increment of either the PEC source or the destination pointer Just one cycle i
91. of Port7 pins P7 7 P7 4 Write ODP7 y Open Drain Latch Read 7 Write DP7 y Direction Latch Read DP7 y Internal Bus Alternate Data Output Write Port P7 y Compare Trigger Read P7 y Output Latch A 98 294 Alternate Latch Data Input Alternate Pin Data Input 4 N P7 y N CCzIO y 4 7 2 28 31 ST10X167 6 10 Port8 If this 8 Bit port is used for general purpose I O the direction of each line can be configured via the corresponding direction register DP8 Each port line can be switched into push pull or open drain mode via the open drain control register ODP8 P8 FFD4h EAh SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Pall Se alee RW R RW RW RW RW RW R 6 0 W W Port data register P8 Bit y DP8 FFD6h EBh SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Port direction register 8 Bit DP8 y 0 Port line P8 y is an input high impedance DP8 y 1 Port line P8 y is an output ODP8 F1D6h EBh ESFR ResetValue 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Port8 Open Drain control register Bit y ODP8 y 0 Port line P8 y output driver in push pull mode ODP8 y 1 Port line P8 y output driver in open drain mode 3 99 294 ST10X167 6 10 1 Alternate Functions of Port8 via software a
92. operands for instructions N 3 through N are in internal memory then the interrupt response time is the time to perform 3 Word bus accesses When the above example has the interrupt vector pointing into the internal ROM the interrupt response time is 1 Word bus access plus 4 CPU clock cycles After an interrupt service routine has been terminated by executing the RETI instruction and if further interrupts are pending the next interrupt service routine will not be entered until at least two instruction cycles have been executed of the program that was interrupted In most cases two instructions will be executed during this time Only one instruction will typically be executed if the first instruction following the RETI instruction is a branch instruction without cache hit or if it reads an operand from internal ROM or if it is executed out of the internal RAM Note A bus access in this context also includes delays caused by an external READY sig nal or by bus arbitration HOLD mode 5 5 1 PEC Response Times The PEC response time defines the time from an interrupt request flag of an enabled interrupt source being set until the data transfer being started The basic PEC response time for the ST10X167 is 2 instruction cycles 67 294 ST10X167 Figure 22 Pipeline diagram for PEC response time Pipeline Stage FETCH DECODE EXECUTE WRITEBACK PEC Response Time
93. overwritten by the status information stacked upon servicing the stack overflow trap Automatic system stack flushing allows to use the system stack as a Stack Cache for a bigger external user stack In this case register STKOV should be initialized to a value which represents the desired lowest Top of Stack address plus 12 according to the selected maximum stack size This considers the worst case that will occur when a stack overflow condition is detected just during entry into an interrupt service routine Then six additional stack Word locations are required to push IP PSW and CSP for both the interrupt service routine and the hardware trap service routine More details about the stack overflow trap service routine and virtual stack management are given in Chapter 21 System Programming ky 51 294 ST10X167 4 4 9 The Stack Underflow Pointer STKUN This non Bit addressable register is compared against the SP register after each operation which pops data from the system stack POP and RET instructions and after each addition to the SP register If the content of the SP register is greater than the content of the STKUN register a stack underflow hardware trap will occur Since the least significant Bit of register STKUN is tied to 0 and Bit 15 through 12 are tied to 1 by hardware the STKUN register can only contain values from 000 to FFFEh STKUN FE16h OBh SFR ResetValue FCOOh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
94. primary use of the timers T0 T1 and T7 T8 is to provide two independent time bases for the capture compare registers of each unit but they may also be used independent of the capture compare registers The basic structure of the four timers is identical while the selection of input signals is different for timers T0 T7 and timers T1 T8 Figure 107 Block diagram of CAPCOM timers T0 and T7 Reload Register TxREL Input Control GPT2 Timer T6 4 Interrupt Over Underflow CAPCOM Timer Tx Request Edge Select TxM Figure 108 Block diagram of CAPCOM timers T1 and T8 CPU e Clock MUX GPT2 Timer 6 x Interrupt Over Underflow X Request Note When an external input signal is connected to the input lines of both TO and T7 these timers count the input signal synchronously Thus the two timers can be regarded as one timer whose contents can be compared with 32 capture registers The functions of the CAPCOM timers are controlled via the Bit addressable 16 Bit control registers TO1CON and T78CON The high Byte of TO1CON controls T1 the low Byte of TO1CON controls TO the high Byte of T78CON controls T8 the low Byte of T78CON controls T7 The control options are identical for all four timers except for external input 186 294 ky T01CON FF50h A8h 15 14 13 12 11 10 ST10X167 ResetValue 0000h 6 4 3 2 1 0 T78CON FF20h 90h 15 14 13 12 11 10 RW ResetValue 0000h 6 4 3 1
95. so all Baud rates between B ow and Bri n are below the deviation limit The maximum standard Baud rate that fulfills this requirement is 19200 Baud Higher Baud rates however may be used as long as the actual deviation does not exceed the limit A certain Baud rate marked l in Figure 104 may violate the deviation limit while an even higher Baud rate marked Figure 104 stays very well below it This depends on the host interface Figure 104 Baud rate deviation between host and ST10X167 182 294 14 THE CAPTURE COMPARE UNITS The ST10X167 provides two almost identical Capture Compare CAPCOM units which differ only in the way they are connected to the I O pins They provide 32 channels which interact with 4timers The CAPCOM units capture the contents of a timer on specific internal or external events or they compare a timer s content with given values and modify output signals in case of ST10X167 a match They support generation and control of timing sequences on up to 16 channels per unit with a minimum of software intervention For programming the term CAPCOM unit refers to a set of SFHs associated to the peripheral including the port pins which may be used for alternate input output functions including their direction control Bit 183 294 v6c v8l Ports amp Direction Control Alternate Functions 15 14 13 1211109 876543210 2 Y CCOIO P2 0 CC151O P2 15 CC1610 P8 0
96. stack is controlled by Bitfield STKSZ in the SYSCON register see Table 3 For all system stack operations the on chip RAM is accessed via the Stack Pointer SP register The stack grows downward from higher towards lower RAM address locations Only Word accesses are supported by the system stack A stack overflow STKOV and a stack underflow STKUN register are provided to control the lower and upper limits of the selected stack area These two stack boundary registers can be used not only for protection against data destruction but also allow to implement a circular stack with hardware supported system stack flushing and filling except for the 2K Byte stack option The technique of implementing this circular stack is described in Section 21 1 Circular virtual Stack mw DEMENS 01 1b 64 32 2 00 FBFEh 00 FBCOh 100b 00 FBFERh 00 F800h 101b REN e Reserved Do not use this combination 110b Reserved Do not use this combination 1024 00 FDFEh 00 F600h Note No circular stack 29 294 ST10X167 3 2 2 General Purpose Registers The general purpose registers GPRs use a block of 16 consecutive Words within the internal RAM The Context Pointer CP register determines the base address of the currently active register bank This register bank may consist of up to 16 Word GPRs R1 R15 and or of up to 16 Byte GPRs RLO RHO RL7 RH7 8 Word regis
97. state as long as no demultiplexed bus is selected via one of the BUSCON registers In demultiplexed bus modes PORT drives the 16 Bit intra segment address while PORTO or POL according to the selected data bus width drives the output data For a 16 Bit data bus BHE is automatically enabled for an 8 Bit data bus BHE is disabled via Bit BYTDIS in register SYSCON Default 16 Bit data bus with multiplexed addresses Note If an internal start is selected via pin EA these two pins are disregarded and Bit field BTYP of register BUSCONO is cleared Write configuration Pin 0 WRC selects the initial operation of the control pins WR and BHE during reset When high this pin selects the standard function which is WR control and BHE When low it selects the alternate configuration WRH and WRL Thus even the first access after a reset can go to a memory controlled via WRH and WRL This Bit is latched in register RPOH and its inverted value is copied into Bit WRCFG in register SYSCON Default Standard function WR control and BHE Gr Chip select lines Pins 2 and POH 1 CSSEL define the number of active chip select signals during reset This allows to select which pins of Port6 drive external CS signals and which used for general purpose I O The two Bit are latched in register RP0H Default All 5 chip select lines active CS4 CS0 Chip Select Lines Note pull downs ore Ferne t
98. system state is automatically performed on the internal system stack avoiding the use of instructions to preserve state upon entry and exit of interrupt or trap routines Call instructions push the value of the IP on the system stack and require the same execution time as branch instructions Instructions have also been provided to support indirect branch and call instructions This supports implementation of multiple CASE statement branching in assembler macros and high level languages 2 2 3 Consistent and Optimized Instruction Formats To obtain optimum performance in a pipeline design an instruction set has been designed using concepts of Reduced Instruction Set Computing RISC These concepts primarily allow fast decoding of the instructions and operands while reducing pipeline holds These concepts however do not preclude the use of complex instructions which are required by microcontroller users The following goals were used to design the instruction set To provide powerful instructions to perform operations which currently require sequences of instructions and which are frequently used To avoid transfer into and out of temporary registers such as accumulators and carry Bit To perform tasks in parallel such as saving state upon entry into interrupt routines or subroutines To avoid complex encoding schemes by placing operands in consistent fields for each instruction Also to avoid complex addressing
99. the DISWDT Disable Watchdog Timer instruction This instruction has been implemented as a protected instruction For further security its execution is only enabled in the time period after a reset until either the SRVWDT Service Watchdog Timer or the EINIT instruction has been executed Thereafter the DISWDT instruction will have no effect 245 294 ST10X167 Reset values for the ST10X167 registers During the reset sequence the registers of the ST10X167 are preset with a default value Most SFRs including system registers and peripheral control and data registers are cleared to zero so all peripherals and the interrupt system are off or idle after reset A few exceptions to this rule provide a first pre initialization which is either fixed or controlled by input pins DPP1 0001h points to data page 1 DPP2 0002h points to data page 2 DPP3 0003h points to data page 3 CP FCOOh STKUN FCOO0h STKOV FAO0h SP FCOOh WDTCON 0002h if reset was triggered by a watchdog timer overflow 0000h otherwise SORBUF XXh undefined SSCRB XXXXh undefined SYSCON OXXOh set according to reset configuration BUSCONO 0XXOh set configuration RPOH XXh reset levels of POH ONES FFFFh fixed value The internal ram after reset The contents of the internal RAM are not affected by a system reset However after a power on reset the contents of the internal RAM are undefined This implies that the GPRs R15 R
100. the SP register is either decremented or incremented as specified For branch instructions the Instruction Pointer and the Code Segment Pointer are updated with the desired branch target address provided that the branch is taken Execute An operation is performed on the previously fetched operands in the ALU ky Additionally the condition flags in the PSW register are updated as specified by the instruction All explicit writes to the SFR memory space and all auto increment or auto decrement writes to GPRs used as indirect address pointers are performed during the execute stage of an instruction too Write back All external operands and the remaining operands within the internal RAM space are written back Injected instructions are generated internally by the machine to provide extra time for instructions that require more than one instruction cycle Instructions are automatically injected into the decode stage of the pipeline they pass through the remaining stages like every standard instruction Program interrupts are performed by the same method of injecting instructions 35 294 ST10X167 Figure 10 Sequential instruction pipelining 4 1 1 Sequential Instruction Processing Each single instruction has to pass through each of the four pipeline stages regardless of whether all possible stage operations are really performed or not Since passing through one pipeline stage takes at least one instruc
101. the line Alternate Data Input While an external bus mode is enabled the user software should not write to the port output latch otherwise unpredictable results may occur When the exter nal bus modes are disabled the contents of the direction register last written by the user becomes active ky Figure 26 PORTO I O and alternate functions Alternate Functions POH 7 POH 6 POH 5 POH 4 POH 3 POH 2 POH 1 AQ P0H 0 A8 POL 7 POL 6 AD6 POL 5 AD5 P0L 4 AD4 POL 3 AD3 POL 2 AD2 POL 1 AD1 POL O ADO General 8 Bit 16 Bit 8 Bit Purpose Demultiplexed Demultiplexed Multiplexed Input Output Bus Bus us The Figure 27 shows the structure of a PORTO pin Figure 27 Block diagram of a PORTO pin Write DPOH y DPOL y Alternate 1 Direction MUX Latch Read DP0H y DP0L y Alternate Function e Enable lt Alternate Data Output Write P0H y POL y u 1 Port Data MUX Port Output Output 0 Latch Read P0H y POL y Internal Bus Input Latch 3 ST10X167 16 Bit Multiplexed Bus 79 294 ST10X167 6 3 Port1 The two 8 Bit ports 1 and P1L represent the higher and lower part of PORT1 respectively Both halves of PORT1 can be written for example via a PEC transfer without effecting the other half If this port is used for general purpose I O the direction of each line can be configured via the corresponding direc
102. the user to define the address area from which the first instructions after reset are fetched When EA is low 0 during reset the internal ROM area is disabled and the first instructions are fetched from external memory When EA is high 1 during reset the internal ROM area is globally enabled and the first instructions are fetched from the internal ROM Note DO NOT select internal ROM access after reset on ROMIess devices 282 294 Mapping the Internal ROM Area After reset the internal ROM area is mapped into segment 0 the system segment 00 0000h 00 7FFFh as a default This is necessary to allow the first instructions to be fetched from locations 00 0000h The ROM area may be mapped to segment 1 01 0000h 01 7FFFh by setting Bit ROMS1 in register SYSCON The internal ROM may now be accessed through the lower half of segment 1 while accesses to segment 0 will now be made to external memory This adds flexibility to the system software The interrupt trap vector table which uses locations 00 0000h through 00 01FFh is now part of the external memory and may therefore be modified so the system software may now change interrupt trap handlers according to the current condition of the system The internal ROM can still be used for fixed software routines like I O drivers math libraries application specific invariant routines tables etc This combines the advantage of an integrated non volatile memo
103. this 512 Byte area short 8 Bit reg addresses to the extended ESFR area require switching to the 512 Byte extended SFR area This is done via the EXTension instructions EXTR EXTP R EXTS R Byte write operations to Word wide SFRs via indirect or direct 16 Bit mem addressing or Byte transfers via the PEC force zeros in the non addressed Byte Byte write operations via short 8 Bit reg addressing can only access the low Byte of an SFR and force zeros in the high Byte It is therefore recommended to use the Bit field instructions BFLDL and BFLDH to write to any number of Bit in either Byte of an SFR without disturbing the non addressed Byte and the unselected Bit 21 294 ST10X167 Reserved Bit Some of the Bit which are contained inthe ST10X167 s SFRs are marked as Reserved User software should never write 1 s to reserved Bit These Bit are currently not implemented and may be used in future products to invoke new functions In this case the active state for these functions will be 1 and the inactive state will be 0 Therefore writing only Os to reserved locations provides portability of the current software to future devices Read accesses to reserved Bit return 0 2 5 4 Parallel Ports The ST10X167 provides to 111 I O lines which are organized into eight input output ports and one input port All port lines are Bit addressable and all input output lines are individually Bit wise progra
104. timer in reload mode Source Edge Select Reload Register Tx Interrupt Ot Up Down Request Interrupt Request T3OUT e lt O Note 1 Line only affected by over underflows of but NOT by software modifications of T3OTL Upon a trigger signal T3 is loaded with the contents of the respective timer register T2 or T4 and the interrupt request flag T2IR or T4IR is set Note When a TS3OTL transition is selected for the trigger signal also the interrupt request flag T3IR will be set upon a trig ger indicating T3 s overflow or underflow Modifications of T3OTL via software will NOT trigger the counter function of T2 T4 The reload mode triggered by T3OTL can be used in a number of different configurations Depending on the selected active transition the following functions can be performed If both a positive and a negative transition of TSOTL is selected to trigger a reload the core timer will be reloaded with the contents of the auxiliary timer each time it overflows or underflows This is the standard reload mode reload on overflow underflow If either a positive or a negative transition of TSOTL is selected to trigger a reload the core timer will be reloaded with the contents of the auxiliary timer on every second overflow or underflow Using this single transition mode for both auxiliary timers allows to perform very flexible 140 294 2 4
105. to perform 7 Word bus accesses When instructions N and N 1 are executed out of external memory but all operands for instructions N 3 through N 1 are in internal memory then the PEC response time is the time to perform 1 Word bus access plus 2 CPU clock cycles ky Once request for service has been acknowledged by the CPU the execution of the next instruction is delayed by 2 CPU clock cycles plus the additional time it might take to fetch the source operand from internal ROM or external memory and to write the destination operand over the external bus in an external program environment Note bus access in this context also includes delays caused by an external READY sig nal or by bus arbitration HOLD mode 5 6 External Interrupts Although the ST10X167 has no dedicated interrupt input pins it provides many possibilities to react on external asynchronous events by using a number of I O lines for interrupt input The interrupt function may either be combined with the pin s main function or may be used instead of it if the main pin function is not required Interrupt signals may be connected to CC311O CCO0IO the capture input compare output lines of the CAPCOM units TAIN T2IN the timer input pins CAPIN the capture input of GPT2 For each of these pins either a positive a negative or both a positive and a negative external transition can be selected to cause an interrupt or
106. transition if the CAN controller itself does not transmit a dominant Bit resynchronization The BTL also provides programmable time segments to compensate for the propagation delay time and for phase shifts and to define the position of the Sample Point in the Bit time The programming of the BTL depends on the Baud rate and on external physical delay times Intelligent Memory The Intelligent Memory CAN RAM Array provides storage for up to 15 message objects of 222 294 maximum 8 data Byte length Each of these objects has a unique identifier and its own set of control and status Bit After the initial configuration the Intelligent Memory can handle the reception and transmission of data without further CPU actions 17 2 Register and Message Object Organization All registers and message objects of the CAN controller are located in the special CAN address area of 256 Byte which is mapped into segment 0 and uses addresses 00 EF00h through 00 EFFFh All registers are organized as 16 Bit registers located on Word addresses However all registers may be accessed Byte wise in order to select special actions without effecting other mechanisms Note The address map shown in Figure 130 lists the registers which are part of the CAN controller There are also ST10X167 specific registers that are associated with the CAN Module These registers however control the access to the CAN Module rather than its function Figure
107. two specified Bit Figure 13 Shift right rounding error evaluation C V Flag Rounding Error Quantity No rounding error i 0 lt 1 0 1 1 Rounding error Rounding error Rounding error Z Flag The Z flag is normally set to 1 if the result of an ALU operation equals zero otherwise it is cleared For the addition and subtraction with carry the Z flag is only set to 1 if the Z flag already contains a 1 and the result of the current ALU operation additionally equals zero This mechanism is provided for the support of multiple precision calculations For Boolean Bit operations with only one operand the Z flag represents the logical negation of the previous state of the specified Bit For Boolean Bit operations with two operands the Z flag represents the logical NORing of the two specified Bit For the prioritize ALU operation the Z flag indicates if the second operand was zero or not ky ST10X167 E Flag The E flag can be altered by instructions which perform ALU or data movement operations The E flag is cleared by those instructions which cannot be reasonably used for table search operations In all other cases the E flag is set depending on the value of the source operand to signify whether the end of a search table is reached or not If the value of the source operand of an instruction equals the lowest negative number which is representable by the data format of the corresponding instruction 8000h
108. weak pull up device This device is switched on under the following conditions Always during reset If the Port6 line is used as a chip select output and the ST10X167 is in Hold mode invoked through HOLD and the respective pin driver is in push pull mode ODP6 x 0 This feature is implemented to drive the chip select lines high during reset in order to avoid mul tiple chip selection and to allow another master to access the external memory via the same chip select lines AND wired while the ST10X167 is in Hold mode With ODP6 x 1 open drain output selected the internal pull up device will not be active during Hold mode external pull up devices must be used in this case When entering Hold mode the CS lines are actively driven high for one clock phase then the output level is controlled by the pull up devices if activated After reset the CS function must be used if selected so In this case there is no possibility to program any port latches before Thus the alter nate function CS is selected automatically in this case Note The open drain output option can only be selected via software earliest during the initialization routine at least signal CSO will be in push pull output driver mode directly after reset see Figure 40 The bus arbitration signals HOLD HLDA and BREQ are selected with Bit HLDEN in register PSW When the bus arbitration signals are enabled via HLDEN also th
109. with a sample rate of 8 CPU clock cycles The upper eight Port2 lines P2 15 P2 8 also support Fast External Interrupt inputs EX7IN EX0IN P2 15 in addition is the input for CAPCOM2 timer T7 T7IN The Table 11 summarizes the alternate functions of Port2 P2Pin Alt Function a Alternate F CCOIO CC1IO CC2IO CC3IO CC4IO CC6lO CC7IO CC8IO CC9IO CC101O CC11IO CC121O 14 CC151O unction b Alternate Function c Fast External Interrupt O Input Fast External Interrupt 1 Input Fast External Interrupt 2 Input Fast External Interrupt 3 Input Fast External Interrupt 4 Input Fast External Interrupt 5 Input Fast External Interrupt 6 Input Fast External Interrupt 7 Input T7IN Timer T7 External Count Input 83 294 ST10X167 Figure 30 Port2 I O and alternate functions Alternate Functions y P2 15 CC15IO P2 14 CC1410 P2 13 P2 12 CC1210 P2 11 CC11IO P2 10 1010 2 9 CC9IO P2 8 ccsio P2 7 cc7lo P2 6 CC6lO P2 5 CC5IO P24 P2 3 2 2 CC2lO P2 1 CC1IO P2 0 CCOIO General Purpose CAPCOM1 Fast External CAPCOM2 Input Output Capture Input Compare Output Interrupt Input Timer T7 Input The pins of Port2 combine internal capture input bus data with compare output alternate data output before the port latch input Figure 31 Block diagram of a Port2 pin Write ODP2 y L Open Drain Latch Read ODP2 y wa
110. within The four register pairs BUSCON4 the address window of the specified size see ADDRSEL4 BUSCON1 ADDRSEL1 allow to 180 19 define 4 separate address areas within the For a given window size only those upper address space of the ST10X167 Within each of address Bit of the start address are used marked these address areas external accesses can be R which are not implicitly used for addresses controlled by one of the four different bus modes inside the window The lower Bit of the start independent of each other and of the bus mode address marked x are disregarded Table 19 Definition of address areas Bit field RGSZ Resulting Window Size Relevant Bit R of Start Address A23 A12 4K Byte 8K Byte 16K Byte 32K Byte 64K Byte 128K Byte 256K Byte 512K Byte 1M Byte 2M Byte 4M Byte 8M Byte Reserved 01 222220220202020 02 2 2220220202020 220220202020 02 x x x x IDDI x x x x x J 20202002 x x x x x x m gt gt gt x x x x x x x IDII x x x x x x x x IDII x x x x x x x x x III x x x x x x x x x x OD x x x Xx x X x x x x x Jg 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 Cy x O OO OoOO ky 121 294 ST10X167 8 4 2 Address Window Arbitration respectively A match with one of these registers This feature does not exist for the ST10F167 directs the access to the res
111. y is an input high impedance DPOX y 1 Port line POX y is an output 6 2 1 Alternate Functions of PORTO When an external bus is enabled PORTO is used as data bus or address data bus Note that an external 8 Bit de multiplexed bus only uses POL while POH is free for I O provided that no other bus mode is enabled PORTO is also used to select the system start up configuration During reset PORTO is configured to input and each line is held high through an internal pull up device Each line can now be individually pulled to a low level see DC level specifications in the respective Data Sheets through an external pull down device A default configuration is selected when the respective PORTO lines are at a high level Through pulling individual lines to a low level this default can be changed according to the needs of the applications The internal pull up devices are designed such that an external pull down resistors see Data Sheet specification can be used to apply a cor rect low level These external pull down resistors can remain connected to the PORTO pins also during normal operation however care has to be taken such that they do not disturb the normal function of PORTO this might be the case for example if the external resistor is too strong With the end of reset the selected bus configura tion will be written to the BUSCONO register The configuration of the high Byte of PORTO will be copied
112. 0 00COh 3 CAPCOM Register 17 CC17IR CC17IE CC17INT 00 00C4h 31h CAPCOM Register 12 Register 25 56 294 12 CC12INT 00 0070h 1Ch h 2 3 4 5 6 0 3 3 3 3 3 37 h h h h h h h ST10X167 Table 6 Interrupt and PEC service request sources continued Source of Interrupt or PEC Trap Service Request Flag Flag Vector Location Number ASCO Transmit Buffer 47h Notes 1 For devices which do not incorporate a CAN module or a PLL the respective interrupt nodes may be used for software triggered interrupts see Section 8 7 The XBUS Interface 2 The currently unused nodes in the table X Peripheral nodes are prepared to accept interrupt requests from integrated XBUS peripherals Nodes where no X Peripherals are connected or when no PLL is implemented may be used to generate software controlled interrupt requests by setting the respective XPnIR bit ky 57 294 ST10X167 Table 7 Vector locations and status for hardware traps 2 Trap Trap Vector Trap Trap Reset Functions Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps Non Maskable Interrupt Stack Overflow Stack Underflow Class B Hardware Traps Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access UNDOPC PRTFLT ILLOPA ILLINA ILLBUS Any 00 0000h ny 00 01FCh 00h 7Fh CPU Priority in s
113. 00 15 waitstates Number of waitstates 15 MCTC 111 1 No waitstates RWDOx Read Write Delay Control for BUSCONx 0 With read write delay the CPU inserts 1 TCL after falling edge of ALE 1 No read write delay RW is activated after falling edge of ALE MTTCx Memory Tristate Time Control 0 1 waitstate 1 No waitstate BTYP External Bus Configuration 0 0 8 Bit Demultiplexed Bus 0 1 8 Bit Multiplexed Bus 1 0 16 Bit Demultiplexed Bus 1 1 16 Bit Multiplexed Bus Note For BUSCONO BTYP is defined via PORTO during reset ALECTLx ALE Lengthening Control 0 Normal ALE signal 417 Lengthened ALE signal BUSACTx Bus Active Control 0 External bus disabled 1 External bus enabled within the respective address window see ADDRSEL RDYENx READY Input Enable 0 External bus cycle is controlled by Bit field MCTC only 1 External bus cycle is controlled by the READY input signal RDYPOLx Ready Active Level Control hot allocated 0 Active level on the READY pin is low bus cycle terminates with a 0 on READY pin in ST10F 167 1 Active level on the READY pin is high bus cycle terminates with a 1 on READY pin CSRENx Read Chip Select Enable 0 The CS signal is independent of the read command RD 1 The CS signal is generated for the duration of the read command CSWENx Write Chip Select Enable 0 The CS signal is independent o
114. 00 0000h which is the first vector in the trap interrupt vector table the reset vector 4 Words locations 00 0000h through 00 0007h are provided in this table to start the initialization after reset As a rule this location holds a branch instruction to the actual initialization routine that may be located anywhere in the address space Note When the Bootstrap Loader Mode is acti vated and sampled during a hardware reset the ST10X167 does not fetch instructions from location 00 0000h but it waits data via serial interface ASCO If single chip mode is selected during reset the first instruction is fetched from the internal ROM Otherwise it is fetched from external memory When internal ROM access is enabled after reset in single chip mode Bit 1 in register SYSCON the software initialization routine may enable and configure the external bus interface before the execution of the EINIT instruction When external access is enabled after reset it may be desirable to reconfigure the external bus characteristics because the SYSCON register is initialized during reset to the slowest possible memory configuration To decrease the number of instructions required to initialize the ST10X167 each peripheral is programmed to a default configuration upon reset but is disabled from operation These default configurations can be found in the descriptions of the individual peripherals During the software design phase portio
115. 000h 15 14 13 12 11 10 7 6 5 4 3 2 1 0 9 8 a SES c R Segment Number Specifies the code segment from where the current instruction is to be fetched SEGNR is ignored when segmentation is disabled 46 294 r Figure 14 Addressing Via the Code Segment Pointer Code Segment CSP Register FF FFFFh 255 254 FE 0000h ST10X167 IP Register Fal 01 0000h EX 24 20 18 Bit Physical Code Address 00 0000h Note When segmentation is disabled the IP value is used directly as the 16 Bit address Code memory addresses are generated by directly extending the 16 Bit contents of the IP register by the contents of the CSP register as shown in the Figure 14 In case of the segmented memory mode the selected number of segment address Bit 7 0 3 0 or 1 0 of register CSP is output on the segment address pins A23 A16 of Port4 for all external code accesses For non segmented memory mode the content of this register is not significant because all code accesses are automatically restricted to segment The CSP register can only be read but not written by data operations It is however modified either directly by means of the JMPS and CALLS instructions or indirectly via the stack by means of the RETS and RETI instructions Upon the acceptance of an interrupt or the execution of a software TRAP instruction the CSP register is automatically set to zero 47 294 ST10X16
116. 01 Bit ROMEN in register SYSCON will be set to 1 Bit BYTDIS in register SYSCON is cleared and BHE is disabled The other Bit of register BUSCONO and the other BUSCON registers are cleared This default initialization selects the slowest possible external accesses using the configured bus type The Ready function is disabled at the end of the internal system reset When the internal reset has completed the configuration of PORTO PORT1 Port4 Port6 and of the BHE signal High Byte Enable alternate function of P3 12 depends on the bus type which was selected during reset When any of the external bus modes was selected during reset PORTO and PORT1 will operate in the selected bus mode Port4 will output the selected number of segment address lines all zero after reset and Port6 will drive the selected number of CS lines CSO will be 0 while the other active CS lines will be 1 When no memory accesses above 64 K are to be performed segmentation may be disabled When the on chip bootstrap loader is activated and sampled during reset pin TxDO alternate function of P3 10 is switched to output mode after the reception of the zero Byte All other pins remain in the high impedance state until they are changed by software or peripheral operation ky Application specific initialization routine After the internal reset condition is removed the ST10X167 fetches the first instruction from location
117. 0X167 PICON F1C4h E2h ResetValue 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Port x Low Byte Input Level Selection Pins Px 7 Px 0 switch on standard TTL input levels Pins Px 7 Px 0 switch on special threshold input levels Port x High Byte Input Level Selection Pins Px 15 Px 8 switch on standard TTL input levels 1 Pins Px 15 Px 8 switch on special threshold input levels All options for individual direction and output mode control are available for each pin independent of the selected input threshold The input hysteresis provides stable inputs from noisy or slowly changing exter nal signals Figure 25 Hysteresis for special input thresholds Bit state 6 1 3 Alternate Port Functions Each port line has one associated programmable alternate input or output function PORTO and PORT1 may be used as the address and data lines when accessing external memory Port4 outputs the additional segment address Bit A23 19 17 A16 in systems where more than 64K Byte of memory are to be accessed directly Port6 provides the optional chip select outputs and the bus arbitration lines Port2 Port7 and Port8 are associated with the capture inputs or compare outputs of the CAP COM units and or with the outputs of the PWM module Port2 is also used for fast external interrupt inputs and for timer 7 input Port3 includes alternate input output functions of timers serial interfaces the optional bus control sig
118. 0X167 An area of 32 1024 Words or all of the internal RAM may be dedicated to the System stack A so called circular stack mechanism allows to use a bigger virtual stack than this dedicated RAM area These techniques as well as the encoding of Bitfield STKSZ are described in more detail in Stack Operations see Section 21 1 Stack Operations 4 4 2 The Processor Status Word PSW This Bit addressable register reflects the current state of the microcontroller Two groups of Bit represent the current ALU status and the current CPU interrupt status A separate Bit USRO within register PSW is provided as a general purpose user flag 43 294 ST10X167 PSW FF10h 88h 15 14 13 12 11 EN RW RW Reset Value 0000h 10 9 8 7 6 5 4 3 2 1 0 ILVL HLD USRO MUL V RW RW RW RW RW RW RW RW Negative Result Set when the result of an ALU operation is negative Overflow Result Set when the result of an ALU operation produces an overflow Carry Flag Set when the result of an ALU operation produces a carry Bit Zero Flag Set when the result of an ALU operation is zero End of Table Flag Set when the source operand of an instruction is 8000h or 80h Multiplication Division In Progress 0 There is no multiplication division in progress 1 A multiplication division has been interrupted USRO User General Purpose Flag May be used by the application software HLDEN
119. 1 Open Drain Mode uu ite ties 74 6 1 2 Input Threshold COntrol 3 dtt ect tere pectine beet ex nu qaq ere Pto Speer tied 75 6 1 3 Alternate Port F nctlohs o icc eet ti tete dert dot eco iater beet AER e Red 76 6 2 PORT O E a 77 6 2 1 Alternate Functions of PORTGO0 78 6 3 80 6 3 1 Alternate Functions of PORT1 80 6 4 esa 82 6 4 1 Alternate Functions of Port2 n 83 6 5 del gc EET 85 6 5 1 Alternate Functions of POrt3 ien tectis ele 86 6 6 PORTA chr up ce 88 6 6 1 Alternate Functions of Port4 89 6 7 POR D5 mula numas Nonnus es 90 6 7 1 Alternate Functions of Portb cccccccccccccceeeeeeseseeeseeeseseseeeeeeeceeeeeeeeeseeseausesaaaaaaaeaeaes 91 6 8 Rie eet etu 92 6 8 1 Alternate Functions of Portl6 a a a 93 6 9 PORT7Z2 u CERE 95 6 9 1 Alternate Functions Of Port7 ccccccccccccccceeee esse seeeseseeseeeeececeeeeeeeeeeeeesesseaeaeausaaaaaeaeaes 96 6 10 PORTS tet d et tet ee Dua 99 6 10 1 Alternate Funct
120. 1 24 1 REVISION OF THE 28TH OF AUGUST 2000 eae eect eet 291 24 2 REVISION OF THE 7TH OF AUGUST 2002 24 292 ky 9 294 SZA ST10X167 USER S MANUAL 1 INTRODUCTION This manual describes the functionality of the ST10X167 group of devices ST10X167 is a generic term covering the ROMIess ST10R167 ROM ST10C167 and flash ST10F167 devices The ST10R167 and ST10C167 are functionally equivalent apart from the memory arrangement The ST10F167 is an older derivative of the device and has different functionality Section 1 1 Differences Between the ST10R167 ST10C167 amp ST10F167 details the functional differences between the ST10X167 derivatives Comments have been made throughout the manual to highlight differences where applicable An architectural overview describes the CPU performance the on chip system resources the on chip clock generator the on chip peripheral blocks and the protected bits The operation of the CPU and the on chip peripherals and the different operating modes such as system reset power reduction modes interrupt handling and system programming are described in individual chapters The explanation of memory configuration has been restricted to that of the internal addressable memory space ST10F167 flash configurations are not discussed in this manual Refer to the ST10F167 datasheet for detailed information
121. 147 Transitions between Idle mode and active mode CPU Interrupt Request IDLE instruction denied accepted Executed PEC Request Note interrupt request which is individually enabled and assigned to priority level 0 will terminate Idle mode The associated interrupt vector will not be accessed however 252 294 ky ST10X167 The watchdog timer may be used to monitor the Idle mode an internal reset will be generated if no interrupt or NMI request occurs before the watchdog timer overflows To prevent the watchdog timer from overflowing during Idle mode it must be programmed to a reasonable duration interval before Idle mode is entered 19 2 Power Down Mode To reduce power consumption the microcontroller can be switched to Power Down mode Clocking of all internal blocks is stopped The contents of the internal RAM are preserved by the voltage supplied by the Vpp pins The watchdog timer is stopped There are two different operating power down modes Protected Power Down Mode ST10F167 can only use protected power down mode Interruptible Power Down Mode not available for ST10F 167 The power down mode is selected by Bit 5 PWDCFG in SYSCON register SYSCON FF12h 89h 15 14 13 12 11 ROM SGT 1 DIS RW RW RW Note 1 Reset value is OXXOh for ST10F 167 PWDCFG not allocated in ST10F167 by asserting the RSTIN pin 10 9 8 7 6 5 4 3 2 1 BYT CLK WR CS PWD OWD BDR XPEN
122. 23 interrupt 198 166 tee ere Ree Ce eee e T 183 Capture mode 191 Capture Mode GPT 141 151 Capture Compare unit 183 CCM1 CCM2 CCM3 190 CCM4 CCM5 CCM6 CCN7 190 Center aligned PWM 204 Chip Select 110 251 Clock Generator 251 Compare modes 192 Concatenation of Timers 139 151 Configuration Addiess 1 10 251 Bus Mode 106 250 Chip Select 110 251 251 ReSet 246 Write Control 250 Context Switching r 66 Control Status Register 223 Conversion analog digital 211 A to SCali seit eder re ir hore yy us 214 timing control es rriat 218 Count direction 131 146 Counter 132 138 148 150 207 o 49 CRU NH 13 ORIG asd sete 154 CSP mios ads paha 46 D Data Page 2 22 2 48 281 boundaries 33 Delay Read Write 114
123. 28 2 212 fopu 2x2 4 2 218 fcpu 64 Model f 5 2x64x2 1 2 64 210 fgg 2x64x2 1 2 64 214 fgg y 2x64x21 207 294 ST10X167 Pulse Width Registers PWx This 16 Bit register holds the actual PWM pulse width value which corresponds to the duty cycle of the PWM signal This register is buffered with a shadow register The CPU accesses the PWx register while the hardware compares the contents of the shadow register with the contents of the associated counter PTx The shadow register is loaded from the respective PWx register at the beginning of every new PWM cycle or upon a write access to PWx while the timer is stopped When the counter value is greater than or equal to the shadow register value the PWM signal is set otherwise it is reset The output of the comparators may be described by the boolean formula PWM output signal PTx gt PWx shadow latch This type of comparison allows a flexible control of the PWM signal For the register locations refer to the Table 34 Table 34 PWM module channel specific register addresses Reg Space FE30n 18h FES2n 19h S Register Address Register Address Reg Space ii ii ii These registers are not Bit addressable PWM Control Register PWMCONO Register controls the function of the timers of the four PWM channels and the channel specific interrupts Having the control Bit organized in functio
124. 3 A19 A17 A16 as is the case when using the segmented memory model The on chip XBUS is an internal representation of the external bus and allows to access integrated application specific peripherals modules in the same as external components It provides a defined interface for these customized peripherals The on chip XRAM and the on chip CAN Module are examples for these X Peripherals 2 4 Clock Generator The on chip clock generator provides the ST10X167 with its basic clock signal that controls the activities of the controller hardware Its oscillator can run with an external crystal and appropriate oscillator circuitry see Chapter 7 Dedicated Pins or can be driven by an external oscillator The oscillator can directly feed the external clock signal to the controller hardware through buffers and divides the external clock frequency by 2 or feeds an on chip phase locked loop PLL which multiplies the input frequency by a selectable factor F The resulting internal clock signal is also referred to as CPU clock Two separated clock signals are generated for the CPU itself and the peripheral part of the chip While the CPU clock is stopped during idle mode the peripheral clock keeps running Both clocks are switched off when the power down mode is entered The on chip PLL circuit allows operation of the ST10X167 on a low frequency external clock while still providing maximum performance The PLL mu
125. 4 4 1 The System Configuration Register SYSCON This Bit addressable register provides general system configuration and control functions The reset value for register SYSCON depends on the state of the PORTO pins during reset see hardware affectable Bit Bit 2 to 6 are not allocated in the ST10F167 device F167 Reset Value 0XX0h SYSCON FF12h 89h 3 STKSZ RW 15 14 XPER SHARE VISIBLE BDRSTEN Not allocated in ST10F167 OWDDIS Not allocated in ST10F167 PWDCFG Not allocated in ST10F167 CSCFG Not allocated in ST10F167 42 294 SFR 10 9 8 7 6 5 4 3 2 1 0 BYT CLK WR CS PWD OWD BDR XPEN VISI XPER DIS EN CFG CFG CFG DIS STEN BLE SHARE RW RW RW RW RW RW RW RW RW RW RW C R167 Reset Value 0X00h 11 SGT DIS RW 12 ROM 51 RW XBUS Peripheral Share Mode Control 0 External accesses to XBUS peripherals are disabled 1 XBUS peripherals are accessible via the external bus during hold mode Visible Mode Control 0 Accesses to XBUS peripherals are done internally 47 XBUS peripheral accesses are made visible on the external pins XBUS Peripheral Enable Bit For ST10C167 ST10R167 This Bit is used to enable XRAM and XCAN For ST10F167 this Bit is used to enable XRAM only as XCAN is always enabled 0 Accesses to the on chip XRAM are disabled external bus cycles instead 1 External bus cycles are executed for accesses to the XRAM area Bidire
126. 7 4 4 5 The Data Page Pointers DPP0 DPP1 DPP2 DPP3 These four non Bit addressable registers select up to four different data pages being active simultaneously at run time The lower 10 Bit of each DPP register select one of the 1024 possible 16K Byte data pages while the upper 6 Bit are reserved for future use The DPP registers make it possible to access the entire memory space in pages of 16K Byte each The DPP registers are implicitly used whenever data accesses to any memory location are made via indirect or direct long 16 Bit addressing modes except for override accesses via EXTended instructions and PEC data transfers After reset the Data Page Pointers are initialized in a way that all indirect or direct long 16 Bit addresses result in identical 18 Bit addresses This allows makes it possible to access data pages 3 0 within segment 0 as shown in the figure below If the user does not want to use any data paging no further action is required DPP0 FE00h 00h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW DPP1 FE02h 01h SFR Reset Value 0001h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F jej a RW DPP2 FE04h 02h SFR Reset Value 0002h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X ES RW DPP3 FE06h 03h SFR ResetValue 0003h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 o RW Data Page Number of DPPx Specifies the data page selected via DPPx Only the 2 least sign
127. 8 Port direction register DP7 Bit y ResetValue 00h DP7 y 0 Port line P7 y is an input high impedance DP7 y 1 Port line P7 y is an output ODP7 F1D2h E9h 15 14 13 12 11 10 9 8 Port Open Drain control register Bit y 6 5 4 3 2 1 ODP7 y 0 Port line P7 y output driver in push pull mode ODPT y 1 Port line P7 y output driver in open drain mode 6 9 1 Alternate Functions of Port7 The upper 4 lines of Port7 P7 7 P7 4 are used as capture inputs or compare outputs CC311O CC281O for the unit How CAPCOM2 unit is connected to Port7 lines and how to handle them by software is similar to the Port2 lines description As all other capture inputs the capture input func tion of pins P7 7 P7 4 can also be used as exter nal interrupt inputs with a sample rate of 8 CPU clock cycles Table 16 Port7 alternate functions The lower 4 lines of Port7 P7 3 P7 0 supports outputs of the PWM module POUTS POUTO At these pins the value of the respective port out put latch is XORed with the value of the PWM out put rather than ANDed as the other pins do This allows to use the alternate output value either as it is port latch holds 0 or invert its level at the pin port latch holds a 1 Note that the PWM outputs must be enabled via the respective PENx Bit in PWMCON1 The Table 16 summarizes the alternate functions of Port7 Port Pin Alternate Function POUTO
128. 94 SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR SFR ESFR ESFR SFR XReg XReg XReg SFR SFR Area SFR Reset Value FAQON 51 Reset Value FCOON 52 C R167 Reset Value 0X00h 42 Reset Value 0X00h 1 118 Reset Value 0X00h 1 253 Reset Value 0000h 187 Reset Value 00h 189 Reset Value 00h 189 Reset Value 0000h 137 Reset Value 00h 142 Reset Value 0000h 130 Reset Value 00h 142 Reset Value 0000h 137 Reset Value 00h 142 Reset Value 0000h 149 Reset Value 00h 154 Reset Value 0000h 145 Reset Value 00h 154 Reset Value 0000h 187 Reset Value 00h 189 Reset Value 00h 189 Reset Value 0000h 72 Reset Value UUUUh 230 Reset Value UUUUh 227 Reset Value UUUUh 228 Reset Value 000Xh 178 Reset Valu
129. BYTDIS 118 294 XBUS Peripheral Share Mode Control 0 External accesses to XBUS peripherals are disabled 1 XBUS peripherals are accessible via the external bus during hold mode Visible Mode Control 0 Accesses to XBUS peripherals are done internally 1 XBUS peripheral accesses are made visible on the external pins XBUS Peripheral Enable Bit For ST10C167 and ST10R167 this Bit is used to enable XRAM and XCAN For ST10F167 this Bit is used to enable XRAM only as XCAN is always enabled 0 Accesses to the on chip XRAM are disabled external bus cycles instead 1 External bus cycles are executed for accesses to the XRAM area Bidirectional Reset Enable 0 RSTIN pin is an input pin only SW Reset or WDT Reset have no effect on this pin 1 RSTIN pin is a bidirectional pin This pin is pulled low during 1024 TCL during reset sequence Oscillator Watchdog Disable Control 0 Oscillator Watchdog OWD is enabled If PLL is bypassed the OWD monitors XTAL1 activity If there is no activity on XTAL1 for at least 1 us the CPU clock is switched automatically to PLLs base frequency around 5MHz 1 OWD is disabled If the PLL is bypassed the CPU clock is always driven by XTAL1 signal The PLL is turned off to reduce power supply current Power Down Mode Configuration Control 0 Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low other
130. CC2310 P8 7 CC2410 P1H 4 CC2710 P1H 7 CC28l0 P7 4 CC3110 P7 7 ODPx DPx Px Port x Data Register T01CON T8E T8REL E CC0 3 CC4 7 CC8 11 CC12 15 CC16 19 CC20 23 CC24 27 CC28 31 Port x Open Drain Control Register Port x Direction Control Register CAPCOM1 Timers TO and T1 Control Register Data Registers 1514131211109876543210 TxREL T01CON Control Registers 1514131211109876543210 VON VEE NS NEY Y OY Wi Y NS Y Y EYA YYYY YYYY W N A ie Gah Y Y SY Y Y x Y NCY YN y ycy y y Y Y y Y NOV Y oN YY Y y YY y OY Voy YON Y OY ONY Yo Y NOV N oco CE PESO NG YY YG NG YY dh Y 37072 Ga h Ca A ah 2 Y Y Me Qh YS YS Yo 84 20 VE Qo Gb YS YS CAPCOM Timer x Reload Register Tx CAPCOM Timer x Register CC0 15 CC16 31 CCM0 3 CAPCOM1 Register 0 15 2 Register 16 31 CCAIC 71C CC8IC 111C CC12 CC16 CC20IC 24 CC28IC C 15 19 Interrupt Control 1514131211109876543210 NCYSY Q b b b 4 YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY eos NY Yo Ye YYYY eos MN YsYo ye YYY Y YEE NY CY Y eos MN Ys Ye Ye NY NYC SHUN WOOdVO pereroosse HOd pue SHAS SOL 29LXOLLS CAPCOM Mode Control Register 0 3 CCM4 7
131. CxIO is configured as output the capture function may be triggered by modifying the corresponding port output latch via software like for testing purposes 191 294 ST10X167 Figure 109 Capture mode block diagram Edge Capture Register CCx Select i CCxIO IN ZZ CCMODx Interrupt COxIR Request Input Interrupt Clock CAPCOM Timer Ty TyIR Request 14 5 Compare Modes The compare modes allow triggering of events interrupts and or output signal transitions with minimum software overhead In all compare modes the 16 Bit value stored in compare register CCx in the following also referred to as compare value is continuously compared with the contents of the allocated timer TO T1 or T7 T8 If the current timer contents match the compare value an appropriate output signal which is based on the selected compare mode can be generated at the corresponding output pin CCxIO except for CC241O CC2710O and the associated interrupt request flag CCxIR is set which can generate an interrupt request if enabled As for capture mode the compare registers are also processed sequentially during compare mode When any two compare registers are programmed to the same compare value their Table 30 Summary of compare modes corresponding interrupt request flags will be set to 1 and the selected output signals will be generated within 8 CPU clock cycles after the allocated timer is incremented t
132. DCFG Power down mode configuration control CSCFG Chip select configuration control System reset Bi directional reset Asynchronous reset function CAN module Optional disabling of the CAN module by the XPEN bit is the SYSCON register Clock generation Optional disabling of the oscillator watchdog by selection of the OWDDIS bit in the SYSCON register Dedicated pins The active level of the READY pin can be selected by software Allocated Allocated Allocated Allocated Not allocated Not allocated Not allocated Not allocated Available Not available Available Not available Available Not available Available Not available Available Not available Vpp used for flash programming voltage for ST10F167 or exit from powerdown for all ST10C167 and ST10R167 devices Identification registers Four identification registers 3 Available Not available 11 294 ST10X167 1 2 Abbreviations The following abbreviations are used in this User s Manual ADG ALE ALU ASG BRG CAN CAPCOM CISC CMOS CPU EBC ESFR Flash GPR 12 294 Analog Digital Converter Address Latch Enable Arithmetic and Logic Unit Asynchronous synchronous Serial Controller Baud Rate Generator Controller Area Network License Bosch CAPture and COMpare unit Complex Instruction Set Computing Complementary Metal Oxide Silicon Central Processing Unit External Bus Controller Ext
133. Demultiplexed Bus 107 Direction EE 131 146 Disable Interrupt as 64 Segmentation 43 Bil 52 273 Double Register compare 196 DP0L DP0H q 78 DP1L DP1H 80 249 EAE 82 DPS 85 Lcd LE 89 BINE c 92 LUE C dee 96 RIEN 99 DPR Tau TREE 48 281 Edge aligned PWM 202 Emulation Mode 250 Enable Interrupt 64 Segmentation 43 Error Detection CAN sas Aaa E 221 ccm E PPS 174 EXIGON aa uyu 71 External BUS qos s 18 Bus Characteristics 111 Bus Idle State 123 B s Modes eir reis 106 110 2 25 2 rrr orn cree 69 F Fast external interrupts 70 Flade 2 CUL 45 Full Duplex 170 G Global Mask Short 224 aci 30 257 GPT esha ante MES 23 uqaqa 128 2 Ga aa 143 H Half
134. EAOh 50h 15 14 13 12 11 10 9 8 The busy flag read only ADBSY is set as long as a conversion is in progress The result of a conversion is stored in the result register ADDAT or in register ADDAT2 for an injected conversion Note Bit field CHNR of register ADDAT is loaded by the ADC to indicate which channel the result refers to Bit field CHNR of register ADDAT2 is loaded by the CPU to select the analog channel which is to be injected Reset Value 0000h 7 6 5 4 3 2 1 0 EN e RW ADDAT2 F0A0h 50h 15 14 13 12 11 10 9 8 ESFR RW ResetValue 0000h 7 6 5 4 3 2 1 0 6 RW RW ADRES Conversion Result 10 Bit CHNR Channel Number 4 Bit identifies the converted analog channel 213 294 ST10X167 A conversion is started by setting Bit ADST 1 The busy flag ADBSY will be set and the converter then selects and samples the input channel which is specified by the channel selection field ADCH in register ADCON The sampled level will then be held internally during the conversion When the conversion of this channel is complete the 10 Bit result together with the number of the converted channel is transferred into the result register ADDAT and the interrupt request flag ADCIR is set If Bit ADST is reset via software while a conversion is in progress the A D converter will stop after the current conversion fixed channel modes or after the
135. EOCh MDL ODP2 ODP3 ODP6 ODP7 ODP8 Eh Fh Dh Ch 7h 06h 07h E3h E7h E9h Bh ONES Fh E6h E8h Ah 60h 62h 63h 64h 65h 66h 67h E2h m m o o o o Constant Value 1 5 Register read only FFFFh Port0 Low Register Lower half of PORT0 00h FiD6h E Port8 Open Drain Control Register 00h 3 8 E 8 8 8 8 0 0 81h 0 High Register Upper half of PORTO 00h 2 P5 Port5 Register read only XXXXh 7 b FFDh Em Port7 Register 8 bit 00h PECC2 FEC4n 79 v U o o TI m m m TI Oo Q N O 5 5 gt m O PEC Channel 2 Control Register 0000h m Q o PECC3 63h PEC Channel 3 Control Register 0000h PECC4 FECBh 64 Channel 4 Control Register 0000h 5 FECAh 65h PEC Channel 5 Control Register 0000h m O gt 79 T 262 294 ST10X167 Table 43 Special function registers ordered by name continued w 3000 U SW b PTO 1 2 3 PT T T U m C2 N b i Co 5 1 W2 W3 U mn T m WO co S 5 gt Xh SOBG FEB4h Serial Channel 0 Baud Rate Generator Reload Register 0000h SOCON FFBOh Serial Channel 0 Control Register 0000h Xh SOEIC b FF70h Serial Channel 0 Error Interrupt Control Register 0000h Serial Channel 0 Receive Buffer Regi
136. External accesses use the slowest possible bus cycle after reset The bus cycle timing may then be optimized by the initialization software 111 294 ST10X167 Figure 52 Programmable external bus cycle ALECTL 8 3 1 ALE Length Control The length of the ALE signal and the address hold time after its falling edge are controlled by the ALECTLx Bit in the BUSCON registers When Bit ALECTL is set to 1 external bus cycles accessing the respective address window will have their ALE signal prolonged by half a CPU clock cycle Also the address hold time after the falling edge of ALE on a multiplexed bus will be Figure 53 ALE length control Normal Multiplexed Bus Cycle 112 294 lt lt 2717777 prolonged by half a CPU clock the data transfer within a bus cycle refers to the same CLKOUT edges as usual the data transfer is delayed by one CPU clock cycle This allows more time for the address to be latched Note ALECTLO is 1 after reset to select the slowest possible bus cycle the other ALECTLx are 0 after reset Lengthened Multiplexed Bus Cycle ST10X167 8 3 2 Programmable Memory Cycle Time The ST10X167 allows the user to adjust the controller s external bus cycles to the access time of the respective memory or peripheral This access time is the total time required to move the data to the destination It represents the period of time during which the controller s signa
137. F167 Ref dsheet IDMEM F07Ah E On chip Memory Identifier Register not in ST10F167 Ref dsheet PTO 1 2 PT3 PP1 PP2 PP3 T7 T8 h h h SSCTB SSCRB SSCBR 8 9 A B D E 0 8 Dr 2 3 4 B B2 B3 B4 B5 TT ADAE 8 8 IDCHIP FO7Ch E Device Identifier Register not in ST10F167 Ref dsheet E DPOH b F102h E 81h POH Direction Control Register DP1L b 104 E P1L Direction Control Register DP1H b 106 E P1H Direction Control Register RPOH b F108h E System Start up Configuration Register Read only x CC16IC b Ft60h E Boh Register 16 Interrupt Control Register 0000h 00h 00h 00h 00h Xh 0 b 162 E CAPCOM Register 17 Interrupt Control Register 0000h CC18IC b F164h E CAPCOM Register 18 Interrupt Control Register 0000h CC19IC b F166h E CAPCOM Register 19 Interrupt Control Register 0000h b 6 CC21IC b F16Ah E CAPCOM Register 21 Interrupt Control Register 0000h h 20 F168h E CAPCOM Register 20 Interrupt Control Register 0000h CC221C b F16Ch E CAPCOM Register 22 Interrupt Control Register 3 265 294 ST10X167 Table 44 Registers ordered by address continued CC28IC CAPCOM Register 28 Interrupt Control Register 0000h F17Ch E CAPCOM Timer 8 Interrupt Control Register 0000h T7IC b b b b PWMIC b F17Eh E BFh PWM Module Interrupt Control Register 0000h
138. F72h B9h SFR ResetValue 00h 15 14 13 5 4 3 2 1 0 12 11 10 9 8 7 6 SSC SSC ILVL GLVL TIR TIE RW RW RW RW SSCRIC FF74h BAh SFR ResetValue 00h 15 14 13 5 4 3 2 1 0 12 11 10 9 8 7 6 SSC SSC ILVL GLVL RIR RIE RW RW RW RW SSCEIC FF76h BBh SFR ResetValue 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 O O T j EIR EIE RW RW RW RW Note Please refer to Section 5 1 3 Interrupt Control Registers for an explanation of the control fields 3 176 294 12 WATCHDOG TIMER The watchdog timer WDT provides recovery from software or hardware failure If the software fails to service this timer before an overflow occurs an internal reset sequence is initiated This internal reset will also pull the RSTOUT pin low this resets the peripheral hardware which might have caused the malfunction When the watchdog timer is enabled and is serviced regularly to prevent overflows the watchdog timer supervises program execution Overflow only occurs if the program does not progress properly The watchdog timer will time out if a software error was due to hardware related failures This prevents the controller from malfunctioning for longer than a user specified time ST10X167 The watchdog timer provides two registers Read only timer register that contains the current count Control register for initialization The watchdog timer is a 16 Bit up counter which can be clocked with the CPU cloc
139. FACE 155 10 1 ASYNCHRONOUS 7 158 10 2 u 5 2 rne Ee e ERR ER Erde 161 10 3 HARDWARE ERROR 162 10 4 ASCO BAUD RATE 162 10 5 ASCO INTERR PT GONTROL tir ts access 163 11 HIGH SPEED SYNCHRONOUS SERIAL INTERFACE 165 11 1 FULL DUPLEX OPERATION eren eae teen 170 11 2 HALF DUPLEX OPERATION nennen nennen nnne 172 11 2 1 Pom Controls ss sehn epp RII IMEEM 173 11 3 BAUD RATE GENERATION u 174 11 4 ERROR DETECTION MECHANISMS 174 6 294 ky 11 5 12 12 1 ST10X167 SSC INTERRUPT 175 WATCHDOG TIMER 177 OPERATION THE WATCHDOG 177 BOOTSTRAP LOADER uu 179 THE CAPTURE COMPARE UNITS u u u 183 res tree dte 186 CAPCOM UNIT TIMER INTERRUPTS L nennen nnne nes 188 CAPTURE COMPARE REGISTERS u uuu u uqta sas s nennen 189 Selection of Capture Modes and Compar
140. FRs to maintain the system state information to supply the ALU with register addressable constants and to control system and bus configuration multiply and divide ALU operations code memory segmentation data memory paging and accesses to the General Purpose Registers and the System Stack The access mechanism for these SFRs in the CPU core is identical to the access mechanism for any other SFR Since all SFRs can be controlled by means of any instruction which is able to address the SFR memory space a lot of flexibility has been gained without creating a set of System specific instructions Note however that there are user access restrictions for some of the CPU core SFRs to ensure proper processor operations The instruction pointer IP and code segment pointer CSP cannot be accessed directly They can only be changed indirectly via branch instructions The PSW SP and MDC registers can be modified not only explicitly by the programmer but also implicitly by the CPU during normal instruction processing Notes 1 Note that any explicit write request via software to an SFR supersedes a simul taneous modification of the same register by hardware 2 Any write operation to a single Byte of an SFR clears the non addressed comple mentary Byte within the specified SFR Non implemented reserved SFR Bit can not be modified and will always supply a read value of O x s s m C 200 300 41 294 ST10X167
141. Idle clock line is high leading clock edge is high to low transition SSCTEN SSC Transmit Error Enable Bit 0 Ignore transmit errors 1 Check transmit errors SSCREN SSC Receive Error Enable Bit 0 Ignore receive errors 1 Check receive errors SSCPEN SSC Phase Error Enable Bit 0 Ignore phase errors 1 Check phase errors SSCBEN SSC Baudrate Error Enable Bit 0 Ignore baudrate errors 1 Check baudrate errors SSCAREN SSC Automatic Reset Enable Bit 0 No additional action upon a baudrate error 1 The SSC is automatically reset upon a baudrate error SSCMS SSC Master Select Bit 0 Slave Mode Operate on shift clock received via SCLK 1 Master Mode Generate shift clock and output it via SCLK SSCEN SSC Enable Bit 0 Transmission and reception disabled Access to control Bits 3 168 294 SSCCON FFB2h D9h 15 14 13 12 55 55 MS BSY RW RW 11 55 RW RW 10 9 8 7 6 5 4 SSC SSC SSC PE RE TE RW RW RW ST10X167 ResetValue 0000h m Shift counter updated with every shifted Bit Do not write to 1 Transfer starts with the slave s transmit buffer not being updated 1 Reception completed before the receive buffer was read Le Received data changes around sampling clock edge SSCBE SSC Baud rate Error Flag 1 More than factor 2 or 0 5 between Slave s actual and expected Baud rate SSCBSY SSC Busy Flag Set while a transfer is in progress Do not write to SSCMS SSC Master Select
142. In the Figure 22 the respective interrupt request flag is set in cycle 1 fetching of instruction N The indicated source wins the prioritization round during cycle 2 In cycle 3 a PEC transfer instruction is injected into the decode stage of the pipeline suspending instruction N 1 and clearing the source s interrupt request flag to 0 Cycle 4 completes the injected PEC transfer and resumes the execution of instruction N 1 All instructions that entered the pipeline after setting of the interrupt request flag N 1 N 2 will be executed after the PEC data transfer Note When instruction N reads any of the PEC control registers PECC7 PECCO while a PEC request wins the current round of pri oritization this round is repeated and the PEC data transfer is started one cycle later The minimum PEC response time is 3 CPU clock cycles This requires program execution from the internal ROM no external operand read requests and setting the interrupt request flag during the last CPU clock cycle of an instruction When the interrupt request flag is set during the first CPU clock cycle of an instruction the minimum PEC response time under these conditions is 4 CPU clock cycles The PEC response time is increased by all delays of the instructions in the pipeline that are executed before starting the data transfer including N When internal hold conditions between instruction pairs N 2 N 1 or N 1 N occur the minimum PEC response t
143. Interrupt and EBC Control Fields ILVL IEN Define the response to interrupt requests and enable external bus Arbitration Described in Chapter 5 Interrupt and Trap Functions ALU Status N C V Z E MULIP The condition flags N C V Z E within the PSW indicate the ALU status due to the last performed ALU operation They are set by most of the instructions due to specific rules which depend on the ALU or data movement operation performed by an instruction After execution of an instruction which explicitly updates the PSW register the condition flags cannot be interpreted as described in the following because any explicit write to the PSW register supersedes the condition flag values which are implicitly generated by the CPU Explicitly reading the PSW register supplies a read value which represents the state of the PSW register after execution of the immediately preceding instruction Note After reset all of the ALU status Bit are cleared N Flag For most of the ALU operations the N flag is set to 1 if the most significant Bit of the result contains 1 otherwise it is cleared In the case of integer operations the N flag can be interpreted as the sign Bit of the result negative N 1 positive N 0 Negative numbers always represented as the 2 s complement of the corresponding positive number The range of signed numbers extends from 8000h to 7FFFh for the Word data type or fr
144. LE INTERRUPTS are required External memory data access does not require special instructions to load data pointers or explicitly load and store external data The ST10X167 provides a Von Neumann memory architecture its on chip hardware ST10X167 automatically detects accesses to internal RAM GPRs and SFRs Multiplication and Division Multiplication and division of Words and double Words is provided through multiple cycle instructions implementing a Booth algorithm Each instruction implicitly uses the 32 Bit register MD MDL lower 16 Bit upper 16 Bit The MDRIU flag Multiply or Divide Register In Use in register MDC is set whenever either half of this register is written to or when a multiply divide instruction is started It is cleared whenever the MDL register is read Because an interrupt can be acknowledged before the contents of register MD are saved this flag is required to alert interrupt routines which require the use of the multiply divide hardware so they can preserve register MD This register however only needs to be saved when an interrupt routine requires use of the MD register and a previous task has not saved the current result This flag is easily tested by the Jump on Bit instructions Multiplication or division is simply performed by specifying the correct signed or unsigned version of the multiply or divide instruction The result is then stored in register MD The ove
145. Latch Shadow Registers Interrupt Request 3 203 294 ST10X167 15 1 2 Mode 1 Symmetrical PWM Generation Center Aligned PWM Mode 1 is selected by setting the respective Bit PMx in register PWMCONT to 1 In this mode the timer PTx of the respective PWM channel is counting up until it reaches the value in the associated period shadow register Upon the next count pulse the count direction is reversed and the timer starts counting down now with subsequent count pulses until it reaches the value 0000 Upon the next count pulse the count direction is reversed again and the count cycle is repeated with the following count pulses The PWM output signal is switched to a high level when the timer contents are equal to or greater than the contents of the pulse width shadow register while the timer is counting up The signal is switched back to a low level when the respective timer has counted down to a value below the contents of the pulse width shadow register So in mode 1 this PWM value controls both edges of the output signal Note that in mode 1 the period of the PWM signal is twice the period of the timer PWM Periodyoge 2 PPx 1 The Figure 119 illustrates the operation and output waveforms of a PWM channel in mode 1 for different values in the pulse width register This mode is referred to as Center Aligned PWM because the value in the pulse width shadow register effects both edges of the output signa
146. MHz when the external crystal oscillator however higher frequencies can be applied with an external clock source Pins controlling the operation of the internal logic and the reserved pins are evaluated only during a hardware triggered reset sequence The pins that influence the configuration of the ST10X167 are evaluated during any reset sequence even during software and watchdog timer triggered resets The configuration via POH is latched in register RPOH for subsequent evaluation by software Register RPOH is described in chapter The External Bus Interface ky ST10C167 ST10R167 ST10F167 fopu X F Ba x 4 Notes Default configuration 4 4 4 ixi Direct drive 1 1 1 CPU clock via prescaler 2 LX 1 Note The reserved pins named R in the row PortO Bit Name of Table 39 must remain high during reset in order to ensure proper operation of the ST10X167 The load on those pins must be small enough for the internal pull up device to keep their level high or external pull up devices must ensure the high level The following describes the different selections that are offered for reset configuration The default modes refer to pins at high level without external pull down devices connected 249 294 ST10X167 Emulation mode When low during reset pin POL O EMU selects the Emulation Mode This mode allows the access to integrated XBus peripherals via the extern
147. MUL V RW RW RW RW RW RW RW RW RW RW N C V ZE CPU status flags Described in section The Central Processing Unit MULIP USR0 Define the current status of the CPU ALU multiplication unit HLDEN HOLD Enable Enables External Bus Arbitration 0 Bus arbitration disabled P6 7 P6 5 may be used for general purpose I O 1 Bus arbitration enabled P6 7 P6 5 serve as BREQ HLDA HOLD respectively ILVL CPU Priority Level Defines the current priority level for the CPU Fh Highest priority level 0h Lowest priority level IEN Interrupt Enable Control Bit globally enables disables interrupt requests 0 Interrupt requests are disabled 1 Interrupt requests are enabled Gr 61 294 ST10X167 CPU Priority ILVL defines the current level for the operation of the CPU This bit field reflects the priority level of the routine that is currently executed Upon the entry into an interrupt service routine this bit field is updated with the priority level of the request that is being serviced The PSW is saved on the system stack before The CPU level determines the minimum interrupt priority level that will be serviced Any request on the same or a lower level will not be acknowledged The current CPU priority level may be adjusted via software to control which interrupt request sources will be acknowledged PEC transfers do not really interrupt the CPU but rather steal a single cycle so PEC
148. MULIP 1 the multiply divide instruction is re read from the location popped from the stack return address and will be completed after the RETI instruction has been executed Note The MULIP flag is part of the context of the interrupted task When the interrupt ing routine does not return to the inter rupted task for example when a scheduler switches to another task the MULIP flag must be set or cleared according to the con text of the task that is switched to BCD Calculations No direct support for BCD calculations is provided inthe ST10X167 BCD calculations are performed by converting BCD data to binary data performing the desired calculations using standard data types and converting the result back to BCD data Due to the enhanced performance of division instructions binary data is quickly converted to BCD data through division by 10d Conversion from BCD data to binary data is enhanced by multiple Bit shift instructions This provides similar performance compared to instructions directly supporting BCD data types while no additional hardware is required 21 1 Stack Operations The ST10X167 supports two types of stacks The system stack is used implicitly by the controller and is located in the internal RAM The user stack provides stack access to the user in either the internal or external memory Both stack types grow from high memory addresses to low memory addresses Internal System Stack A system stack is pr
149. N must be configured as input the respective direction control Bit must be 0 The maximum input frequency which is allowed in counter mode is 8 To ensure that a transition of the count input signal which is applied to TxIN is correctly recognized its level should be held for at least 8 CPU clock cycles before it changes Interrupt Request Table 25 GPT1 auxiliary timer counter mode input edge selection 21 TAI None Counter Tx is disabled Triggering Edge for Counter Increment Decrement Positive transition rising edge on TxIN Negative transition falling edge on TxIN Any transition rising or falling edge on TxIN Positive transition rising edge of output toggle latch T3OTL Negative transition falling edge of output toggle latch T3OTL Any transition rising or falling edge of output toggle latch T3OTL 138 294 ST10X167 Timer Concatenation Using the toggle Bit T3OTL as a clock source for an auxiliary timer in counter mode concatenates the core timer T3 with the respective auxiliary timer Depending on which transition of T3OTL is selected to clock the auxiliary timer this concatenation forms a 32 Bit or a 33 Bit timer counter 32 Bit timer counter If both a positive and a negative transition of T3OTL is used to clock the auxiliary timer this timer is clocked on every overflow underflow of the core timer T3 Thus the two timers form a 32 Bit timer 33 Bit timer counter
150. NT field in register PECCx of the selected PEC channel decrements to zero This allows a normal CPU interrupt to respond to a completed PEC block transfer Note Modifying the Interrupt Request flag via software causes the same effects as if it had been set or cleared by hardware 5 1 4 Interrupt Priority Level and Group Level The four bit of bit field ILVL specify the priority level of a service request for the arbitration of simultaneous requests The priority increases with the numerical value of ILVL so 0000b is the lowest and 1111b is the highest priority level When more than one interrupt request on a specific level gets active at the same time the values in the respective bit fields GLVL are used for second level arbitration to select one request for being serviced Again the group priority increases with the numerical value of GLVL so 006 is the lowest and 11b is the highest group priority Note All interrupt request sources that are enabled and programmed to the same priority level must always be programmed to different group priorities Otherwise an incorrect interrupt vector will be generated Upon entry into the interrupt service routine the priority level of the source that wins the arbitration and who s priority level is higher than the current CPU level is copied into bit field ILVL of register PSW after pushing the old PSW contents on the stack Figure 18 Priority levels and PEC channels 5 4 Interrupt
151. O and the PEC source and destination pointers SRCP7 SRCPO DSTP7 DSTPO which are mapped into the internal RAM also unchanged after a warm reset software reset or watchdog reset but are undefined after a power on reset Ports and external bus configuration during reset During the internal reset sequence all of the ST10X167 s port pins are configured as inputs by clearing the associated direction registers and their pin drivers are switched to the high impedance state This ensures that the ST10X167 and external devices will not try to drive the same pin to different levels Pin ALE is held low through an internal pull down and pins RD and WR are held high through internal pull ups Also the pins selected for CS output will be pulled high according to reset 246 294 The registers SYSCON and BUSCONO are initialized according to the configuration selected via PORTO The reset configurations summarized in Table 38 and Table 39 When an external start is selected pin 0 The Bus Type field BTYP register BUSCONO is initialized according to POL 7 and POL 6 Bit BUSACTO in register BUSCONO is set to 1 Bit ALECTLO in register BUSCONO is set to 1 Bit ROMEN in register SYSCON will be cleared to 0 Bit BYTDIS in register SYSCON is set according to the data bus width When an internal start is selected pin 1 Register BUSCONO is cleared to 000
152. O pon A D Converter Control Register 0000h T gt C2h C3h C4h C4h C5h C6h C7h C8h C9h Ah Bh C D Eh Fh DOh D7h D8h D9h EOh E2h ESh E4h E5h E6h E7h E8h E9h Ah Bh T gt WDTCON FFAEh pn Watchdog Timer Control Register 000xh SOCON FFBOh Ds Serial Channel 0 Control Register 0000h nm UJ F o SSCCON FFB2h SSC Control Register 0000h FFCOh Port2 Register 0000h P ii m O oO 2 ross 5 FR 2 DP2 P3 DP3 4 DP4 DP6 7 P7 8 71 m m a gt ol K a gt u Q Q gt s rom b b Port8 Direction Control Register P P D P 00h 00h 00h 00h 00h 00h Oh i HE I fum ee seme E D Be 3 270 294 ST10X167 20 5 Special Notes PEC Pointer Registers The source and destination pointers for the peripheral event controller are mapped to a special area within the internal RAM Pointers that are not occupied by the PEC may therefore be used like normal RAM During Power Down mode or any short reset the PEC pointers are preserved The PEC and its registers are described in chapter Interrupt and Trap Functions GPR Access in the ESFR Area The locations 00 F000h 00 F01Eh within the ESFR area are reserved and provide access to the current register bank via short register addr
153. P6 7 1 which is neither required for Master Mode nor for earlier devices 8 6 2 Entering the Hold State Access to the 5710 1675 external bus is requested by driving its HOLD input low After synchronizing this signal the ST10X167 will complete a current external bus cycle if any is active release the external bus and grant access to it by driving the HLDA output low During hold state the ST10X167 treats the external bus interface as follows Address and data bus es float to tri state ALE is pulled low by an internal pull down device Command lines are pulled high by internal pull up devices RD WR WRL BHE WRH CSx outputs are pulled high push pull mode or float to tri state open drain mode Should the ST10X167 require access to its external bus during hold mode it activates its bus request output BREQ to notify the arbitration circuitry BREQ is activated only during hold mode It will be inactive during normal operation see Figure 61 Figure 60 Sharing external resources using slave mode HOLD HLDA ST10X167 in Master Mode BREQ HOLD HLDA ST10X167 in Slave Mode BREQ 125 294 ST10X167 Figure 61 External bus arbitration releasing the bus Signals Note The ST10X167 will complete the currently running bus cycle before granting bus access as indicated by the broken lines This may delay hold acknowledge com pared to this figure The figure above show
154. PEC service request The edge selection is performed in the control register of the peripheral device associated with the respective port pin The peripheral must be programmed to a specific operating mode to allow generation of an interrupt by the external signal The priority of the interrupt Table 10 Pins to be used as external interrupt inputs ST10X167 request is determined by the interrupt control register of the respective peripheral interrupt Source and the interrupt vector of this source will be used to service the external interrupt request Note In order to use any of the listed pins as external interrupt input it must be switched to input mode via its direction control bit DPx y in the respective port direction control register DPx see Table 10 When port pins CCxl O are used as external interrupt input pins bit field CCMODx in the control register of the corresponding capture compare register CCx must select capture mode When CCMODx is programmed to 0010 the interrupt request flag COxIR in register CCxIC will be set on a positive external transition at pin CCxI O When CCMODx is programmed to 010b a negative external transition will set the interrupt request flag When CCMODx 011b both a positive and a negative transition will set the request flag In all three cases the contents of the allocated CAPCOM timer will be latched into capture register CCx independent whether the timer is running or not Whe
155. Pin CAPIN differs slightly from the timer input pins as it can be used as external interrupt input pin without affecting peripheral functions When the capture mode enable bit T5SC in register T5CON is cleared to 0 signal transitions on pin CAPIN will only set the interrupt request flag CRIR in register CRIC and the capture function of register CAPREL is not activated So register CAPREL can still be used as reload register for GPT2 timer T5 while pin CAPIN serves as external interrupt input Bit field CI in register T5CON selects the effective transition of the external interrupt input signal When Cl is programmed to 01b a positive external transition will set the interrupt request EXICON F1COh EOh 15 14 11 10 ESFR flag Cl210b selects a negative transition to set the interrupt request flag and with Cl 11b both a positive and a negative transition will set the request flag When the interrupt enable bit CRIE is set an interrupt request for vector CRINT or a PEC request will be generated Note The non maskable interrupt input pin and the reset input RSTIN provide another possibility for the CPU to react on an external input signal NMI and RSTIN are dedicated input pins which cause hard ware traps 5 6 1 Fast External Interrupts The input pins that may be used for external interrupts are sampled every 8 CPU clock cycles this means that the external events are scanned and detected in timeframes o
156. RL reload value from the timer contents The formula below shows the association T6 36 9 CPU 2m c 4 PHost For a correct data transfer from the host to the ST10X167 the maximum deviation between the internal initialized Baud rate for ASCO and the real Baud rate of the host should be below 2 596 The deviation Fp in percent between host Baud rate and ST10X167 Baud rate can be calculated via the formula below SOBRL T6 Boontr PHost Ep B PContr x100 Fp 2 5 96 Note Function Fg does not consider the tolerances of oscillators and other devices supporting the serial communication This Baud rate deviation is a nonlinear function depending on the CPU clock and the Baud rate of the host The maxima of the function increase with the host Baud rate due to the smaller Baud rate pre scaler factors and the implied higher quantization error see Figure 104 The minimum Baud rate B ow in the Figure 104 is determined by the maximum count capacity of timer T6 when measuring the zero Byte and it depends on the CPU clock Using the maximum T6 count 216 in the formula the minimum Baud rate can be calculated The lowest standard Baud rate in this case would be 1200 Baud Baud rates below Bj oy would cause T6 to overflow In this case ASCO cannot be initialized properly The maximum Baud rate ByHigh in the Figure 104 is the highest Baud rate where the deviation still does not exceed the limit
157. Rate Generator Clock Control 8 Master Clock Receive Interrupt Request SSC Control Transmit Interrupt Request Block Error Interrupt Request Status Control Pin Control 16 Bit Shift Register Transmit Buffer Receive Buffer Register SSCTB Register SSCRB Internal Bus The operating mode of the serial channel SSC is controlled by its Bit addressable control register SSCCON This register serves for two purposes During programming SSC disabled by SSCEN 0 it provides access to a set of control Bit During operation SSC enabled by SSCEN 1 it provides access to a set of status flags Register SSCCON is shown below in each of the two modes ky 167 294 ST10X167 SSCCON FFB2h D9h SFR ResetValue 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Tapes MS AREN BEN PEN REN TEN PO PH HB RW RW RW RW RW RW RW RW RW RW RW Function Programming Mode SSCEN 0 SSC Data Width Selection 0 Reserved Do not use this combination 1 15 Transfer Data Width is 2 16 Bit SSCBM 1 SSCHB SSC Heading Control Bit 0 Transmit Receive LSB First 1 Transmit Receive MSB First SSCPH SSC Clock Phase Control Bit 0 Shift transmit data on the leading clock edge latch on trailing edge 1 Latch receive data on leading clock edge shift on trailing edge SSCPO SSC Clock Polarity Control Bit 0 Idle clock line is low leading clock edge is low to high transition 1
158. SEL2 FE1Ah Address Select Register 2 0000h m EN AB 7h 8h 9h Ah Bh Ch Eh Fh Fh 2h 3h 6h 7h Ah Bh Eh Fh Oh 2h 3h 7h 9h Bh Oh 2h 3h 4h 6h 7h 8h 9h h Bh h Dh 266 294 ST10X167 Table 44 Registers ordered by address continued m ELM mm m 0 1 2 3 PW PW PW PW 2 3 4 5 6 0 1 2 2 0 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 Eh Fh Oh 2h 3h 4h 5h 8h 9h Ah Bh Oh 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 40h 42h 43h 4h CO C1 C2 C3 C4 3 267 294 ST10X167 Table 44 Registers ordered by address continued Physical 8 bit Reset FEBAh CAPCOM Register 5 0000h FE8Ch CAPCOM Register 6 0000h FE8Eh CAPCOM Register 7 0000h FE90h FE92h m rm O gt gt CC5 CC6 CC7 CC8 CC9 nij nj mi mji rm cO o v o 5 5 2 BE ND wm w s 22 m gt 5 4 4 4 4 4 4 4 SOTBUF 5 i i Oh 6 6 6 6 8 8 8 8 8 8 8 8A 8 C Bz mei EUM Bead HE I Ea 7 gt 5 PECC6 FECCh PEC Channel 6 Control Regist
159. ST10X167 USER S MANUAL Release 1 1 ST10X167 TABLE OF CONTENTS Page 1 INTRODUCTIONS Sul SSS ss 10 1 1 DIFFERENCES BETWEEN THE ST10R167 ST10C167 amp ST10F167 11 1 2 ABBREVIATIONS ital ee eile e tee eee ad 12 2 ARCHITECTURAL OVERVIEW ua 13 2 1 BASIC CPU CONCEPTS AND OPTIMIZATIONS eene 13 2 1 1 High Instruction Bandwidth Fast 14 2 2 HIGH FUNCTION 8 BIT AND 16 BIT ALU 15 2 2 1 Extended Bit Processing and Peripheral 2 15 2 2 2 High Performance Branch Call and Loop Processing 15 2 2 3 Consistent and Optimized Instruction 2 16 2 2 4 Programmable Multiple Priority Interrupt System 4 16 2 3 ON CHIP SYSTEM RESOURCES uu u 17 2 3 1 Peripheral Event Control and Interrupt 17 2 3 2 Memory Areas 17 2 3 3 External Bus Intetace uuu ee Lee dee idee Ge tre det 18 2 4 CLOCK GENERATOR u tented wide tes loe edi ca det 18 2 4 1 PLL Operations zn lect ne tre teret een Ede m e c e Ex 20 2 4 2 Prescaler
160. Source can be assigned to a specific priority A second level called group priority allows to specify an internal order for simultaneous requests from a group of different sources on the same priority level At the end of each instruction cycle the request with the highest current priority will be determined by the interrupt system The request will be serviced If its priority is higher than the current CPU priority which is stored in the register PSW 5 1 2 Interrupt System Register Description Interrupt processing is globally controlled by register PSW through a general interrupt enable bit IEN and the CPU priority field ILVL Additionally the different interrupt sources are individually controlled by their specific interrupt control registers IC Thus the acceptance of requests by the CPU is determined by both the individual interrupt control registers and the PSW PEC services are controlled by the respective PECCx register and the source and destination pointers which specify the task of the respective PEC service channel 5 1 3 Interrupt Control Registers All interrupt control registers are identically organized The lower 8 bit of an interrupt control xxIC yyyyh zzh 15 14 13 12 11 10 SFR Area ST10X167 register contain the complete interrupt status information of the associated source which is required during one round of prioritization the upper 8 bit of the respective register are reserved
161. T10X167 enters Power Down Mode the XCLK signal will be turned off which will stop the operation of the CAN Module Any message transfer is interrupted In order to ensure that the CAN controller is not stopped while sending a 240 294 dominant level 0 on the CAN bus the CPU should set Bit INIT in the Control Register prior to entering Power Down Mode The CPU can check if a transmission is in progress by reading Bit TXRQ and NEWDAT in the message objects and Bit TXOK in the Control Register After returning from Power Down Mode via hardware reset the CAN Module has to be reconfigured 17 7 CAN Application Interface The on chip CAN Module of the ST10X167 does not incorporate the physical layer connection to the CAN bus This must be provided externally The module s CAN controller is connected to this physical layer the CAN bus via two signals CAN RXD Port4 5 Receive data from the physical layer of the CAN bus CAN TXD Port4 6 Transmit data to the physical layer of the CAN bus A logic low level 0 is interpreted as the dominant CAN bus level a logic high level 1 is interpreted as the recessive CAN bus level Note If CAN module is used Port 4 cannot be programmed to output all the 8 segment address lines Thus only up to 4 segments address lines can be used reducing the external memory space to 5M Byte Figure 141 Connection to the CAN bus CAN TxD CAN ST10X167 Interface
162. TOUT pin generates a reset signal for the system components besides the controller itself RSTOUT is driven active low at the beginning of any reset sequence triggered by hardware the SRST instruction or a watchdog timer overflow RSTOUT stays active low beyond the end of the internal reset sequence until the protected EINIT End of Initialization instruction is executed see Figure 146 This allows the complete configuration of the controller including its on chip peripheral units before releasing the reset signal for the external peripherals of the system Note RSTOUT will float as long as pins POL O and POL 1 select emulation mode or adapt mode Watchdog timer operation after reset The watchdog timer starts running after the internal reset has completed It will be clocked with the internal system clock divided by 2 and its ky default reload value is 00h so a watchdog timer overflow will occur 131072 CPU clock cycles after completion of the internal reset unless it is disabled serviced or reprogrammed meanwhile When the system reset is triggered a watchdog timer overflow the WDTR Watchdog Timer Reset Indication flag in register WDTCON is set to 1 This indicates the cause of the internal reset to the software initialization routine WDTR is reset to 0 by an external hardware reset or by servicing the watchdog timer After the internal reset has completed the operation of the watchdog timer can be disabled by
163. The Stack Pointer SP LE u us usata ir nto e eet e re eet ette bei etel 51 4 4 8 The Stack Overflow Pointer STKOV 51 4 4 9 The Stack Underflow Pointer STKUN 52 4 4 10 The Multiply Divide High Register MDH 52 4 4 11 The Multiply Divide Low Register MDL eem 53 4 4 12 The Multiply Divide Control Register 53 4 4 13 The Constant Zeros Register ZEROS 54 4 4 14 The Constant Ones Register ONES eese eene nnne nnns 54 4 4 15 z cis M 54 5 INTERRUPT AND TRAP FUNCTIONS 55 5 1 INTERRUPT SYSTEM STRUCTURE 55 5 121 Normal Interrupt Processing and PEC Service 2 00 58 5 1 2 Interrupt System Register 59 5 1 3 Interrupt Control Registers Qa sqa nennen nnne nnns 59 5 1 4 Interrupt Priority Level and Group Level eee 60 5 1 5 Interrupt Control Functions in the 2 61 5 2 OPERATION OF THE CHANNELS 62 5 3 PRIORITIZING INTERRUPT amp PEC SERVICE REQUESTS 64 5 3 1 Enabling and Disabling Interrupt Requests a 64 5 3 2 Interrupt Class 64 5 4 SAVING THE STATUS DURING INTERRUPT SERVICE
164. Timer Reset Indication Flag Set by the watchdog timer on an overflow Cleared by a hardware reset or by the SRVWDT instruction Watchdog Timer Reload Value for the high Byte Note The reset value will be 0002h if the reset was triggered by the watchdog timer overflow It will be 0000h otherwise After any software reset external hardware reset see note or watchdog timer reset the watchdog timer is enabled and starts counting up from 0000h with the frequency 2 The input frequency may be switched to 128 by setting Bit WDTIN The watchdog timer can be disabled via the instruction DISWDT Disable Watchdog Timer Instruction DISWDT is a protected 32 Bit instruction which will ONLY be executed during the time between a reset and execution of either the EINIT End of Initialization or the SRVWDT Service Watchdog Timer instruction Either one of these instructions disables the execution of DISWDT When the watchdog timer is not disabled via instruction DISWDT it will continue counting up even during Idle Mode If it is not serviced via the instruction SRVWDT by the time the count reaches FFFFh the watchdog timer will overflow and cause an internal reset This reset will pull the external reset indication pin RSTOUT low It differs from a software or external hardware reset in that Bit WDTR Watchdog Timer Reset Indication Flag of register WDTCON will be set A hardware reset or the SRVWDT instruction will c
165. Timer block GPT2 supports high precision event control with a maximum resolution of 4 CPU clock cycles It includes the two timers T5 and T6 and the 16 Bit capture reload register CAPREL Timer T6 is referred to as the core timer and T5 is referred to as the auxiliary timer of GPT2 Each timer has an alternate associated input pin which serves as the gate control in gated timer mode or as the count input in counter mode The count direction Up Down may be programmed via software or may be dynamically altered by a ST10X167 signal at an external control input pin An overflow underflow of T6 is indicated by the output toggle Bit T6OTL whose state may be output on an alternate function port pin In addition T6 may be reloaded with the contents of CAPREL The toggle Bit also supports the concatenation of T6 with auxiliary timer T5 while concatenation of T6 with the timers of the CAPCOM units is provided through a direct connection Triggered by an external signal the contents of T5 can be captured into register CAPREL and T5 may optionally be cleared Both timer T6 and T5 can count up or down and the current timer value can be read or modified by the CPU in the non Bitaddressable SFRs T5 and T6 143 294 ST10X167 Figure 77 SFRs and port pins associated with timer block GP T2 Ports amp Direction Control Alternate Functions Data Registers 1514131211109876543210 1514131211109876543210 YYYYYYYYYYYYYYYY T6 YYYYYYYY
166. VISI DIS EN CFG cra cra pis STEN BLE RW RW RW RW RW RW RW RW RW RW Reset Value 0X00h 0 RW Power Down Mode Configuration Control 0 Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low otherwise the instruction has no effect To exit Power Down Mode an external reset must occurs 1 Power Down Mode can only be entered during PWRDN instruction execution if all enabled Fast External Interrupt EXxIN pins are in their inactive level Exiting this mode can be done by asserting one enabled pin Note Register SYSCON cannot be changed after execution of the EINIT instruction 19 2 1 Protected Power Down Mode This mode is selected by setting Bit PWDCFG in the SYSCON register to 0 not needed for ST10F167 Entering power down mode can only be achieved if the NMI Non Maskable Interrupt pin is externally pulled low while the PWRDN instruction is executed This feature can be used in conjunction with an external power failure signal which pulls the NMI pin low when a power failure is imminent The microcontroller will enter the NMI trap routine this routine can save the internal state into the RAM After the internal state has been saved the trap routine may set a flag or write a certain Bit pattern into specific RAM locations and then execute the PWRDN instruction If the NMI pin is still low at this time Power Down mode will be entered ot
167. W register is tested to determine whether a higher priority interrupt is currently being serviced When an interrupt is acknowledged the current state of the machine is saved on the internal system stack and the CPU branches to the system specific vector for the peripheral The PEC contains a set of SFRs which store the count value and control Bit for eight data transfer channels In addition the PEC uses a dedicated area of RAM which contains the source and destination addresses The PEC is controlled similarly to any other peripheral through SFRs containing the desired configuration of each channel An individual PEC transfer counter is implicitly decremented for each PEC service except forming in the continuous transfer mode When ky ST10X167 this counter reaches zero a standard interrupt is performed to the vector location related to the corresponding source PEC services are very well suited for example to move register contents to from a memory table The ST10X167 has 8 PEC channels each of which offers such fast interrupt driven data transfer capabilities 2 3 2 Memory Areas The memory space of the ST10X167 is configured in a Von Neumann architecture which means that code memory data memory registers and I O ports are organized within the same linear address space which covers up to 16M Byte The entire memory space can be accessed Byte wise or Word wise Particular portions of the on chip memory have additio
168. Y signal especially asynchro nous READY READY that has been activated by an external device may be deactivated in response to the trailing rising edge of the respective command RD or WR Note When the READY READY function is enabled for a specific address window each bus cycle within this window must be terminated with an active READY READY signal Otherwise the controller hangs until the next reset A time out function is only provided by the watchdog timer Combining the READY function with predefined waitstates is advantageous in two cases Memory components with a fixed access time and peripherals operating with READY READY may be grouped into the same address window The external waitstate control logic in this case would activate READY READY either upon the memory s chip select or with the peripheral s READY READY output After the predefined number of waitstates the ST10X167 will check its READY READY line to determine the end of the bus cycle Fora memory access it will below already see Figure 57 for a peripheral access it may be delayed As memories tend to be faster than peripherals there should be no impact on system performance When using the READY READY function with so called normally ready peripherals it may lead to erroneous bus cycles if the READY READY line is sampled too early These 116 294 peripherals pull their READY READY output low while they are idle
169. YYYYYYYY CAPREL Y Y Y Y Y Y YY YY Y Y Y Y Y Y Control Registers Interrupt Control 15141312111098 76 543210 15 14 13 12111098765 43210 Y Y Y X NYNA YN Y Yo Yo Y Y Sock Whose cu m ees Yo YC Y NY YY YO Y OY Y Y Bor a sama W Y YOY Y YY gt ees veut ene OY TSIN P5 13 T5EUD P5 11 T6IN P5 12 T6EUD P5 10 CAPIN P3 2 T6OUT P3 1 ODP3 Port 3 Open Drain Control Register T5 GPT2 Timer 5 Register DP3 Port 3 Direction Control Register T6 GPT2 Timer 6 Register P3 Port 3 Data Register CAPREL GPT2 Capture Reload Register P5 Port 5 Data Register T5IC GPT2 Timer 5 Interrupt Control Register T5CON GPT2 Timer 5 Control Register T6IC GPT2 Timer 6 Interrupt Control Register T6CON GPT2 Timer 6 Control Register CRIC GPT2 CAPREL Interrupt Control Register Y Bit is linked to a function Bit has no function or is not implemented E Register is in ESFR internal memory space 3 144 294 ST10X167 Figure 78 GPT2 block diagram T5EUD P5 11 CPU Clock 2 2 9 T5 Interrupt T5IN Mode GPT2 Timer T5 Request Clear Capture Interrupt Request Interrupt Request T6IN P5 12 T Mods T6OUT CPU Clock Control P3 1 Up Down to CAPCOM Timers TO T1 T7 8 9 2 1 GPT2 Core Timer T6 The operation of the core timer T6 is controlled by its Bitaddressable control register T6CON FF48h A4h SFR ResetValue 0000h 15 14 13 12
170. a in Bit 0 of these registers The data Bit are rearranged for transfer by the internal shift register logic The unselected Bit of SSCTB are ignored the unselected Bit of SSCRB will be not valid and should be ignored by the receiver service routine The clock control allows the adaptation of transmit and receive behavior of the SSC to a variety of serial interfaces A specific clock edge rising or falling is used to shift out transmit data while the other clock edge is used to latch in receive data Bit SSCPH selects the leading edge or the trailing edge for each function Bit SSCPO selects the level of the clock line in the idle state So for an idle high clock the leading edge is a falling one a 1 to 0 transition The Figure 95 is summary Figure 95 Serial clock phase and polarity options Latch Data Shift Data 170 294 11 1 Full Duplex Operation The different devices are connected through three lines The definition of these lines is always determined by the master The line connected to the master s data output pin MTSR is the transmit line the receive line is connected to its data input line MRST and the clock line is connected to pin SCLK Only the device selected for master operation generates and outputs the serial clock on pin SCLK All slaves receive this clock so their pin SCLK must be switched to input mode DP3 13 2 0 The output of the master s shift register is connected to the extern
171. a standard or extended frame will be accepted The last message object has its own programmable mask for acceptance filtering allowing a large number of infrequent objects to be handled by the system Figure 129 CAN block diagram CAN TxD P4 6 KA BTL Configuration ST10X167 Timing Generator Tx Rx Shift Register Clocks Intelligent Messages Handlers Status Control to XBUS Tx Rx Shift Register The Transmit Receive Shift Register holds the destuffed Bit stream from the bus line to give parallel access to the whole data or remote frame for the acceptance match test and the parallel transfer of the frame to and from the Intelligent Memory Bit Stream Processor The Bit Stream Processor BSP is a sequencer controlling the sequential data stream between the Tx Rx Shift Register the CRC Register and the bus line The BSP also controls the EML and the parallel data stream between the Tx Rx Shift Register and the Intelligent Memory such that the processes of reception arbitration transmission and error signalling are performed according to the CAN protocol Note that the automatic retransmission of messages which have been corrupted by noise or other external error conditions on the bus line is handled by the BSP ky Memory to all Control Cyclic Redundancy Check Register This register generates the Cyclic Redundancy Check CRC code to be transmitted a
172. ad via software 1 Set when register MDL or MDH is written via software or when a multiply or divide instruction is executed Internal Machine Status The multiply divide unit uses these Bit to control internal operations Never modify these Bit without saving and restoring register MDC 3 53 294 ST10X167 When a division or multiplication was interrupted before its completion and the multiply divide unit is required the MDC register must first be saved along with registers MDH and MDL to be able to restart the interrupted operation later and then it must be cleared prepare it for the new calculation After completion of the new division or multiplication the state of the interrupted multiply or divide operation must be restored The MDRIU flag is the only portion of the MDC register which might be of interest for the user The remaining portions of the MDC register are reserved for dedicated use by the hardware and should never be modified by the user in another way than described above Otherwise a correct continuation of an interrupted multiply or divide operation cannot be guaranteed A detailed description of how to use the MDC register for programming multiply and divide algorithms can be found in Chapter 21 System Programming 4 4 13 The Constant Zeros Register ZEROS All Bit of this Bit addressable register are fixed to 0 by hardware This register can be read only Register ZEROS can be used as a register ad
173. age of interface pins WR BHE segmentation internal Memory mapping are controlled by the SYSCON register The properties of a bus cycle like chip select mode usage of READY length of ALE external bus mode read write delay and waitstates are controlled by BUSCONA BUSCONO registers Four of these registers BUSCON4 BUSCON1 have an associated address select register ST10X167 ALE Lengthen Demultiplexed Read Write gt Delay ADDRSEL4 ADDRSEL1 which allows to specify up to four address areas and the individual bus characteristics within these areas All accesses that are not covered by these four areas are then controlled via BUSCONO This allows to memory components or peripherals with different interfaces within the same system while optimizing accesses to each of them Note BUSCON4 BUSCONO Bit SGTDIS con trols the correct stack operation push pop of CSP or not during traps and interrupts 117 294 ST10X167 SYSCON FF12h 89h SFR Reset Value 0X00h 15 14 13 RW 12 11 10 9 8 7 6 5 4 3 2 1 0 ROM SGT BYT CLK WR CS PWD OWD BDR XPEN VISI XPER 51 DIS DIS EN CFG CFG CFG DIS STEN BLE SHARE RW RW RW RW RW RW RW RW RW RW RW RW RW Note 1 Reset value is OXXOh for ST10F 167 XPER SHARE VISIBLE BDRSTEN not allocated in ST10F167 OWDDIS not allocated in ST10F167 PWDCFG not allocated in ST10F167 CSCFG not allocated in ST10F167
174. al bus interface pins in application specific version of the ST10X167 In addition also the RSTOUT pin floats to tristate rather to be driven low When the emulation mode is latched the CLKOUT output is automatically enabled This mode is used for special emulator purposes and is not used in basic ST10X167 devices so in this case P0L 0 should be held high Default Emulation Mode is off Adapt mode Pin POL 1 ADP selects the Adapt Mode when low during reset In this mode the ST10X167 goes into a passive state which is similar to its state during reset The pins of the ST10X167 float to tristate or are deactivated via internal pull up pull down devices as described for the reset state In addition also the RSTOUT pin floats to tristate rather than be driven low and the on chip oscillator is switched off This mode allows switching a ST10X167 that is mounted to a board virtually off so an emulator may control the board s circuitry even though the original ST10X167 remains in its place The original ST10X167 also may resume to control the board after a reset sequence with POL 1 high Default Adapt Mode is off Note When XTAL1 is fed by an external clock generator while XTAL2 is left open this clock signal may also be used to drive the emulator device However if a crystal is used the emulator device s oscillator can use this crystal only if at least XTAL2 of the original device is dis connected from the circuitry th
175. al System Configuration SYSCON RPOH CPU Status Indication and Control PSW Code Access Control IP CSP Data Paging Control DPPO DPP1 DPP2 DPP3 GPRs Access Control CP System Stack Access Control SP STKUN STKOV Multiply and Divide Support MDL MDC ALU Constants Support ZEROS ONES Gr Figure 9 CPU Block Diagram ST10X167 Internal RAM 2K Byte MDL ROM Multiplication Division Hardware or Flash Memory Where Applicable Execution Unit Bit Mask Generator General Purpose Instruction Pointer 4 Stage Pipeline 16 Bit Registers PSW Barrel Shift SYSCON BUSCON 0 BUSCON 1 ADDRSEL 1 BUSCON 2 ADDRSEL 2 BUSCON 3 ADDRSEL 3 BUSCON 4 ADDRSEL 4 Data Page Pointers Code Segment Pointer 4 1 Instruction Pipelines The instruction pipeline breaks down CPU processing into the four following stages Fetch An instruction selected by the Instruction Pointer IP and the Code Segment Pointer CSP is fetched from either the internal memory internal RAM or external memory Decode Instructions are decoded and if required the operand addresses are calculated and the respective operands are fetched For all instructions which implicitly access the system stack
176. al transmit line which in turn is connected to the slaves shift register input The output of the slaves shift register is connected to the external receive line in order to enable the master to receive the data shifted out of the slave The external connections are hard wired the function and direction of these pins is determined by the master or slave operation of the individual device Note The shift direction shown in the Figure 96 applies for MSB first operation as well as for LSB first operation When initializing the devices in this configuration select one device for master operation SSCMS 1 all others must be programmed for slave operation SSCMS 0 Initialization includes the operating mode of the device s SSC and also the function of the respective port lines see Section 11 2 1 Port Control Serial Clock Transmit Data Figure 96 SSC full duplex configuration Device 1 Shift Register I gt ST10X167 Device 2 Shift Register The data output pins MRST of all slave devices are connected together onto the one receive line in this configuration During a transfer each slave shifts out data from its shift register There are two ways to avoid collisions on the receive line due to different slave data Only one slave drives the line it enables the driver of its MRST pin All the other slaves have to program there MRST pins to input So only one slave
177. also be deactivated without the ST10X167 requesting the bus 8 7 The XBUS Interface The ST10X167 provides an on chip interface the XBUS interface which allows to connect integrated costumer application specific peripherals to the standard controller core The XBUS is an internal representation of the external bus interface it works in the same way The current XBUS interface is prepared to support up to 3 X Peripherals ST10X167 For each peripheral on the XBUS X Peripheral there is a separate address window controlled by an XBCON and an XADRS register As an interface to a peripheral in many cases is represented by just a few registers the XADRS registers select smaller address windows than the standard ADDRSEL registers As the register pairs control integrated peripherals rather than externally connected ones they are fixed by mask programming rather than being user programmable X Peripheral accesses provide the same choices as external accesses so these peripherals may be Bytewide or Wordwide with or without a separate address bus Interrupt nodes and configuration pins are provided for X Peripherals to be integrated 127 294 ST10X167 9 THE GENERAL PURPOSE TIMER UNITS The general purpose timer units GPT1 and GPT2 are flexible multifunctional timer structures which may be used for timing event counting pulse width measurement pulse generation frequency multiplication other
178. ame MSGVAL Message Valid Indicates if the corresponding message object is valid or not The CAN controller only operates on valid objects Message objects can be tagged invalid while they are changed or if they are not used at all NEWDAT New Data Indicates if new data has been written into the data portion of this message object by CPU transmit objects or CAN controller receive objects since this Bit was last reset or not 2 MSGLST Message Lost This Bit applies to receive objects only Receive Indicates that the CAN controller has stored a new message into this object while NEWDAT was still set i e the previously stored message is lost CPUUPD CPU Update This Bit applies to transmit objects only Transmit Indicates that the corresponding message object may not be transmitted now The CPU sets this Bit in order to inhibit the transmission of a message that is currently updated or to control the automatic response to remote requests TXRQ Transmit Request Indicates that the transmission of this message object is requested by the CPU or via a remote frame and is not yet done TXRQ can be disabled by CPUUPD 3 RMTPND Remote Pending Used for transmit objects Indicates that the transmission of this message object has been requested by a remote node but the data has not yet been transmitted When RMTPND is set the CAN controller also sets TXRQ RMTPND and TXRQ are cleared when the message object has been successfully
179. an interrupt level 15 has been assigned to the CPU it has the highest possible priority and thus the current CPU operation cannot be interrupted except by hardware traps or external non maskable interrupts For details please refer to Chapter 5 Interrupt and Trap Functions After reset all interrupts are globally disabled and the lowest priority ILVL 0 is assigned to the initial CPU activity 45 294 ST10X167 4 4 3 The Instruction Pointer IP This register determines the 16 Bit intra segment address of the currently fetched instruction within the code segment selected by the CSP register The IP register is not mapped into the MCU address space and thus it is not directly accessible by the programmer The IP can however be modified indirectly via the stack by means of a return instruction The IP register is implicitly updated by the CPU for branch instructions and after instruction fetch operations ResetValue 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GE Specifies the intra segment offset from where the current instruction is to be fetched IP refers to the current segment SEGNR 4 4 4 The Code Segment Pointer CSP This non Bit addressable register selects the code segment being used at run time to access instructions The lower 8 Bit of register CSP select one of up to 256 segments of 64K Byte each while the upper 8 Bit are reserved for future use CSP FEO8h 04h SFR Reset Value 0
180. an only was less than 8 the remaining Byte of the match with corresponding message message object will be overwritten by non objects either standard XTD 0 or specified values Message Configuration Register EFn6h XReg ResetValue UUh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Be Bye 0 3s mee RW RW R R RW RW Extended Identifier Indicates if this message object will use an extended 29 Bit identifier or a standard 11 Bit identifier Message Direction DIR 1 transmit On TXRQ the respective message object is transmitted On reception of a remote frame with matching identifier the TXRQ and RMTPND Bit of this message object are set DIR 0 receive On TXRQ a remote frame with the identifier of this message object is transmitted On reception of a data frame with matching identifier that message is stored in this message object DLC Data Length Code Valid values for the data length are 0 8 Note The first data Byte occupies the upper half of the message configuration register 3 231 294 ST10X167 Data Area The data area of message object n covers locations 00 EFn7h through 00 EFnEh locations 00 EFnFh is reserved Message data for message object15 last message will be written into a two message alternating buffer to avoid the loss of a message if a second message has been received before the CPU has read the first one Handling of Message Objects The following diagrams summar
181. and reset Bit ADBSY 16 1 2 Auto Scan Conversion Modes These modes are selected by programming the mode selection field ADM in register ADCON to 10p single conversion or to 11 continuous conversion Auto Scan modes automatically convert a sequence of analog channels beginning with the channel specified in Bit field ADCH and ending with channel 0 without requiring software to change the channel number After starting the converter through Bit ADST the busy flag ADBSY will be set and the channel specified in Bit field ADCH will be converted After the conversion is complete the interrupt request flag ADCIR will be set and the converter will automatically start a new conversion of the next lower channel ADCIR will be set after each completed conversion After conversion of channel 0 the current sequence is complete In single conversion mode the converter will automatically stop and reset Bit ADBSY and ADST In continuous conversion mode the converter will automatically start a new sequence beginning with the conversion of the channel specified in ADCH When Bit ADST is reset by software while a conversion is in progress the converter will complete the current sequence including conversion of channel 0 and then stop and reset Bit ADBSY Figure 125 Auto scan conversion mode example Conversion of Channel Write ADDAT ADDAT Full Generate Interrupt Request ST10X167 ADDAT Full Channel 0
182. and the disassembly of Words into Byte is ST10X167 handled by the EBC and is transparent to the CPU and the programmer Byte accesses on a 16 Bit data bus require that the upper and lower half of the memory can be accessed individually In this case the upper Byte is selected with the BHE signal while the lower Byte is selected with the AO signal So the two Byte of the memory can be enabled independent from each other or together when accessing Words When writing Byte to an external 16 Bit device which has a single CS input but two WR enable inputs for the two Byte the EBC can directly generate these two write control signals This saves the external combination of the WR signal with or BHE In this case pin WR serves as WRL write low Byte and pin BHE serves as WRH write high Byte Bit WRCFG in register SYSCON selects the operating mode for pins WR and BHE The respective Byte will be written on both data bus halves When reading Byte from an external 16 Bit device whole Words may be read and the ST10X167 automatically selects the Byte to be input and discards the other However care must be taken when reading devices that change state when being read like FIFOs interrupt status registers etc In this case individual Byte should be selected using BHE and AO Figure 51 Switching from demultiplexed to multiplexed bus mode Demultiplexed Bus Cycle Segment P4 Address Address
183. ange the serial channel ASCO provides an error interrupt 162 294 request flag which indicates the presence of an error and three selectable error status flags in register SOCON which indicate which error has been detected during reception Upon completion of a reception the error interrupt request flag SOEIR will be set simultaneously with the receive interrupt request flag SORIR if one or more of the following conditions are met f the framing error detection enable Bit SOFEN is set and any of the expected stop Bit is not high the framing error flag SOFE is set indicating that the error interrupt request is due to a framing error Asynchronous mode only If the parity error detection enable Bit SOPEN is set in parity Bit receive modes and the parity check on the received data Bit proves false the parity error flag SOPE is set indicating that the error interrupt request is due to a parity error Asynchronous mode only f the overrun error detection enable Bit SOOEN is set and the last character received was not read out of the receive buffer by software or PEC transfer at the time the reception of a new frame is complete the overrun error flag SOOE is set indicating that the error interrupt request is due to an overrun error Asynchronous and synchronous mode 10 4 ASCO Baud Rate Generation The serial channel ASCO has its own dedicated 13 Bit Baud rate generator with 13 Bit reload capability allo
184. apacitances of the converter are loaded via the respective analog input pin to the current analog input voltage The time to load the capacitances is referred to as sample time Next the sampled voltage is converted to a digital value in 10 successive steps which correspond to the 10 Bit resolution of the ADC The next 4 steps are used for an internal self calibration of the converter module During these 14 steps the internal capacitances are repeatedly charged and discharged via the Vangr The current that has to be drawn from the sources for sampling and changing charges depends on the time that each respective step takes because the capacitors must reach their final voltage level within the given time at least with a certain approximation The maximum current however that a source can deliver depends on its internal resistance The time that the two different actions during conversion take sampling and converting can be programmed within a certain range in the ST10X167 relative to the CPU clock The absolute time that is consumed by the different conversion steps therefore is independent of the general speed of the controller This allows adjusting the A D converter of the ST10X167 to the properties of the system Fast conversion can be achieved by programming the respective times to their absolute possible minimum This is preferable for scanning high frequency signals The internal resistance of analog source and ana
185. area s 512 Byte reserved Page 1 Page 0 00 0000 00 F000 DPRAM SFR AREA 3 28 294 1 The upper 256 Byte of SFR area ESFR area and internal RAM are Bit addressable 2 Read or write access in reserved locations may cause unexpected behaviour Code accesses are always made on even Byte addresses The highest possible code storage location in the internal RAM is either 00 FDFEh for single Word instructions or 00 FDFCh for double Word instructions The respective location must contain a branch instruction unconditional because sequential boundary crossing from internal RAM to the SFR area is not supported and can causes erroneous results Any Word and Byte data in the internal RAM can be accessed via indirect or long 16Bit addressing modes if the selected DPP register points to data page 3 Any Word data access is made on an even Byte address The highest possible Word data storage location in the internal RAM is 00 FDFEh For PEC data transfers the internal RAM can be accessed independently of the contents of the DPP registers via the PEC source and destination pointers The upper 256 Byte of the internal RAM 00 FDOOh through 00 FDFFh and the GPRs of the current bank are provided for single Bit Table 3 Stack Size ST10X167 storage and therefore they are Bit addressable see Figure 6 3 2 1 System Stack The system stack may be defined within the internal RAM The size of the system
186. articular DPPn n 0 to 3 register is generally not capable of using a new DPPn register value which is to be updated by an immediately preceding instruction Therefore to make sure that the new DPPn register value is used at least one instruction must be inserted between a DPPn changing instruction and a subsequent instruction which implicitly uses DPPn via a long or indirect addressing mode as shown in the example E MOV DPPO 4 select data page 4 via DPPO Tari ip niers must not be an instr using DPPO Tn 2 MOV DPP0O 0000H R1 move contents of R1 to address loc 01 0000h in dp 4 supposed segmentation is enabled Explicit Stack Pointer Updating None of the RET RETI RETS RETP or POP instructions are capable of correctly using a new SP register value which is to be updated by an immediately preceding instruction Therefore in order to use the new SP register value without erroneously performed stack accesses at least one instruction must be inserted between an explicit SP writing and any subsequent of the just mentioned implicitly SP using instructions as shown in the example Tg MOV SP 0FA40H select a new top of stack Ini SE tiie must not be an instruction popping operands from the system stack POP RO pop Word value from new top of stack into RO 38 294 ky ST10X167 External Memory Access Sequences The effect described here will only become noticeable when watching the external memor
187. as WRH 1 Pins WR and retain their normal function CSSEL Chip Select Line Selection Number of active CS outputs 0 0 3 CS lines CS2 CS0 0 1 2 CS lines CS1 CS0 1 0 No CS lines at all 1 1 5 CS lines CS4 CS0 Default without pull downs SALSEL Segment Address Line Selection Number of active segment address outputs 0 0 4 Bit segment address A19 A16 0 1 No segment address lines at all 1 0 8 Bit segment address A23 A16 1 1 2 Bit segment address A17 A16 Default without pull downs CLKCFG CPU Frequency fopu X F baa X 4 Boa x baa X 2 Boa x 5 Boa x 1 Baa x 1 5 faa x 0 5 baa 2 5 Notes 1 In ST10X167 RPOH 7 0 Bit are loaded only during a long hardware reset 2 The maximum depends on the duty cycle of the external clock signal The maximum input frequency is 25MHz when using an external crystal oscillator however higher frequencies can be applied with an external clock source 8 4 3 Precautions and Hints The external bus interface is enabled as long as at least one of the BUSCON registers has its BUSACT Bit set PORT will output the intra segment address as long as at least one of the BUSCON registers selects a demultiplexed external bus even for multiplexed bus cycles Not all address areas defined via registers ADDRSELx may overlap each other The operation of the EBC will be unpredictable in such a case See Section 8 4 2 Address Window Arbit
188. atch Read P4 y 6 7 Port5 This 16 Bit input port can only read data There is no output latch and no direction register Data written to P5 will be lost P5 FFA2h D1h SFR Reset Value XXXXh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Py data register P5 Bit y Read only 90 294 ST10X167 6 7 1 Alternate Functions of Port5 Each line of Port5 is also connected to the input multiplexer of the Analog Digital Converter All port lines P5 15 P5 0 can accept analog signals AN15 AN0 that can be converted by the ADC No special pro gramming is required for pins that shall be used as analog inputs The upper 6 pins of Port5 also serve as external timer control lines for GPT1 and GPT2 The Table 14 summarizes the alternate functions of Port5 Table 14 Port5 alternate functions Ports Pin Alternate Function a Alternate Function b Analog Input ANO Analog Input AN1 Analog Input AN2 Analog Input AN3 Analog Input AN4 Analog Input 5 Analog Input ANG Analog Input AN7 Analog Input AN8 Analog Input AN9 Analog Input AN10 T6EUD Timer 6 external Up Down Input Analog Input AN11 T5EUD Timer 5 external Up Down Input Analog Input AN12 T6IN Timer 6 Count Input Analog Input AN13 Timer 5 Count Input Analog Input AN14 T4EUD Timer 4 external Up Down Input Analog Input AN15 T2EUD Timer 2 external Up Down Input Figure 37 Port5 I O and alternate functions Alternate Func
189. ated If no further transfer is to take place SSCTB is empty SSCBSY will be cleared at the same time Software should not modify SSCBSY as this flag is hardware controlled Only one SSC can be master at a given time The transfer of serial data Bit can be programmed in the following ways The data width can be chosen from 2 Bit to 16 Bit Transfer may start with the LSB or the MSB The shift clock may be idle low or idle high Data Bit may be shifted with the leading or trailing edge of the clock signal The Baud rate may be set for a range of values refer to Section 11 3 Baud Rate Generation for the formula to calculate values or to the device datasheet for specific values The shift clock can be generated master or received slave This allows the adaptation of the SSC to a wide range of applications where serial data transfer is required 169 294 ST10X167 The data width selection supports the transfer of frames of any length from 2 Bit characters up to 16 Bit characters Starting with the LSB SSCHB 0 allows communication with ASC0 devices in synchronous mode like serial interfaces Starting with the MSB 55 1 allows operation compatible with the SPI interface Regardless which data width is selected and whether the MSB or the LSB is transmitted first the transfer data is always right aligned in registers SSCTB and SSCRB with the LSB of the transfer dat
190. be used for general purpose Input Output controlled via software or may be used implicitly by ST10X167 s integrated periph erals or the External Bus Controller All port lines are Bit addressable and all input out put lines are individually Bit wise programmable as inputs or outputs via direction registers except Port5 The I O ports are true bidirectional ports which are switched to high impedance state when configured as inputs The output drivers of five I O ports 2 3 6 7 8 can be configured pin by pin for push pull opera tion or open drain operation via control registers The logic level of a pin is clocked into the input latch once per CPU clock cycle regardless whether the port is configured for input or output A write operation to a port pin configured as an input causes the value to be written into the port output latch while a read operation returns the latched state of the pin itself A read modify write operation reads the value of the pin modifies it and writes it back to the output latch Writing to a pin configured as output DPx y 1 causes the output latch and the pin to have the written value since the output buffer is enabled Reading this pin returns the value of the output latch A read modify write operation reads the value of the output latch modifies it and 74 294 writes it back to the output latch thus also modify ing the level at the pin 6 1 1 Open Drain Mode Some
191. bling instruction Initialization of Port Pins Modifications of the direction of port pins input or output become effective only after the instruction following the modifying instruction As Bit instructions BSET BCLR use internal read modify write sequences accessing the whole port instructions modifying the port direction should be followed by an instruction that does not access the same port WRONG BSET DP3 13 change direction of P3 13 to output BSET P3 5 P3 13 is still input the read modify write reads pin P3 13 RIGHT BSET DP3 13 change direction of P3 13 to output NOP any instruction not accessing Port3 BSET P3 5 P3 13 is now output the read modify write reads the P3 13 output latch 39 294 3 ST10X167 Changing the System Configuration The instruction following an instruction that changes the system configuration via register SYSCON like the mapping of the internal memory like segmentation like stack size cannot use the new resources Memory or stack This instruction must not access the new ressources Code accesses to the new Memory area are only possible after an absolute branch to this area As a rule instructions that change Memory mapping must be executed from internal RAM or external memory BUSCON ADDRSEL The 14 4 instruction following an lp instruction that changes the properties of an external address area cannot access operands within the new area
192. buffer Read P2 y changed to Read P7 y page 120 figure 59 updated page 121 RPOH Bit WRCFG changed to WRC and 0 is normal state is replaced to 1 and vice versa page 134 correction of figure 71 page 148 correction of figure 82 page 150 figure 84 addition of T3IN and T3EUD input pins page 154 figure 87 bit 11 of SOCON register removed page 164 figure 93 bit 7 and 13 of SSCCON register removed page 175 figure 99 bits 2 to 7 of WDTCON removed page 178 figure 102 4 changed to 8 KO maximum page 183 figure 106 x 0 7and y 1 8 added page 188 CC16 CC32 changed to CC16 CC31 page 209 figure 123 data bit 10 and 11 removed from ADDAT and ADDAT2 and bit 6 removed from ADCON page 222 CAN control status register name of bit test changed to TST page 224 table 36 update of notes page 227 message control register bit MSGLST changed to MSGLST CPUUPD page 234 figure 136 INTPNDd changed to INTPND page 240 chapter 18 1 1 18 1 2 and 18 1 3 updated page 246 table 39 redrawn table 40 added page 248 bootstrap loader acknowledge Byte C5h added page 251 SSPEN bit 2 of SYSCON changed to XPEN page 253 figure 148 update of pull down current 200uA page 262 table 44 notes removed page 269 correction of identification registers page 274 table 45 stack size updated for STKSZ 111b page 276 user stack Rb R
193. by over underflows of T3 but NOT by software modifications of T3OTL Note Auxiliary Timer in Capture Mode Capture mode for the auxiliary timers T2 and T4 is selected by setting Bit field TxM in the respective register TXCON to 101b In capture mode the contents of the core timer are latched into an auxiliary timer register in response to a signal transition at the respective auxiliary timer s external input pin TxIN do c Interrupt Request The capture trigger signal can be a positive a negative or both a positive and a negative transition The two least significant Bit of Bit field Txl are used to select the active transition see table in the counter mode section while the most significant Bit Txl 2 is irrelevant for capture mode It is recommended to keep this Bit cleared 2 0 Note When programmed for capture mode the respective auxiliary timer T2 or T4 stops independent of its run flag T2R or T4R 141 294 ST10X167 Figure 76 GPT1 auxiliary timer in capture mode Capture Register Tx Interrupt OQA Input Clock Core Timer T3 Up Down Upon a trigger selected transition at the corresponding input pin TxIN the contents of the core timer are loaded into the auxiliary timer register and the associated interrupt request flag TxIR will be set Request Interrupt Request p 9 1 3 Interrupt Control for GPT1 Time
194. ch other The ST10F167 is an older derivative of the device and has different functionality This section summarizes the ST10X167 functional differences between the ST10R167 ST10C167 devices and the older ST10F167 These differences have been broken into functional groups The differences have been highlighted again in the individual chapters of the user manual where applicable ST10C167 Power Reduction Interruptible power down mode Return from powerdown mode Selected by setting the bit PWDCFG in the Available Not available Available Not available SYSCON register to 1 and uses the VPP RPD pin for C167 R167 For ST10F167 the VPP RPD pin is used for the flash programming voltage External Bus Interface Programmable chip select timing control READY polarity The active level of the READY pin can be selected by software Address window arbitration For each address access the EBC compares the current address with all address select register General Purpose Timers Incremental interface mode Syscon Register Bit allocation XPEN XBUS Peripheral Enable bit enables XRAM and XCAN For ST10F 167 this Available Not available Available Not available Available Not available Available Not available Allocated Allocated bit is used to enable XRAM only as XCAN is always enabled BDRSTEN Bidirectional reset enable OWDDIS Oscillator watchdog disable control PW
195. channel is started via software and is counting up until it reaches the value in the associated period shadow register Upon the next count pulse the timer is cleared to 0000h and stopped via hardware the respective PTRx Bit is cleared The PWM output signal is switched to high level when the timer contents are equal to or greater than the contents of the pulse width shadow register The signal is switched back to low level when the respective timer is cleared because it is below the pulse width shadow register Thus starting a PWM timer in single shot mode produces one single pulse on the respective port pin provided that the pulse width value is between 0000h and the period value In order to generate a further pulse the timer has to be started again via software by setting Bit PTRx see Figure 121 Figure 121 Operation and output waveform in single shot mode PPx Period 7 PTx Count Value PWx Pulse Width 4 Set PTRx by Software PTRx Reset by Hardware Set PTRx by Software for Next Pulse PTx stopped PPx Period 7 PTx Count Value PWx Pulse Width 4 Retrigger after Pulse has started Write PWx value to P Tx 206 294 Trigger before Pulse has started Write PWx value to PTx Shortens Delay Time tp After starting the timer with PTRx 1 the output pulse may be modified via software Writing to timer PTx changes the positive and or negative edge of the output signal depending on wh
196. ck option is available for testing purposes A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers A parity Bit can automatically be generated on transmission or be checked on reception Framing error detection allows to recognize data frames with missing stop Bit An overrun error will be generated if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete 2 5 6 The on chip CAN Module The integrated Module handles the completely autonomous transmission reception of CAN frames in accordance with the CAN specification V2 0 part B active The on chip CAN Module can receive and transmit standard frames with 11 Bit identifiers as well as extended frames with 29 Bit identifiers The module provides Full CAN functionality on up to 15 message objects Message object 15 may be configured for Basic CAN functionality ky Both modes provide separate masks for acceptance filtering which allows to accept a number of identifiers in Full CAN mode and also allows to disregard a number of identifiers in Basic CAN mode All message objects can be updated independent from the other objects and are equipped for the maximum message length of 8 Byte The Bit timing is derived from the XCLK and is programmable up to a data rate of 1M Baud The CAN Module uses two pins to interface t
197. cks GPT1 and GPT2 Two Serial Interfaces ASCO and SSC A Watchdog Timer Two 16 channel Capture Compare units 1 CAPCOM2 4 channel Pulse Width Modulation unit 10 Bit Analog Digital Converter Nine I O ports with a total of 111 I O lines Each peripheral also contains a set of Special Function Registers SFRs which control the functionality of the peripheral and temporarily store intermediate data results Each peripheral has an associated set of status flags Individually selected clock signals are generated for each peripheral from binary multiples of the CPU clock 2 5 1 Peripheral Interfaces The on chip peripherals generally have two different types of interfaces an interface to the CPU and an interface to external hardware Communication between CPU and peripherals is performed through Special Function Registers SFRs and interrupts The SFRs serve as control status and data registers for the peripherals Interrupt requests are generated by the peripherals based on specific events which occur during their operation like end of task new event error Specific pins of the parallel ports are used for interfacing with external hardware when an input or output function has been selected for a peripheral During this time the port pins are controlled by the peripheral when used as outputs or by the external hardware which controls the peripheral when used as
198. clocks were switched off The Table 40 summarizes the state of all ST10X167 output pins during Idle and Power Down mode Table 40 Output pin state during idle and powerdown modes ST10X167 Idle Mode Power Down Mode Output Pin s No External bus No External bus external bus enabled external bus enabled ALE Low Low Low Low PORT Port Latch Data Last Address 3 Port Latch Data Last Address 3 Port Latch Data Port Latch Data Port 4 Port Latch Data Port Latch Data Last Port Latch Data Port Latch Data Last segment segment Other Port Port Latch Data Port Latch Data Port Latch Data Port Latch Data Output Pins Alternate Function Alternate Function Alternate Function Alternate Function Notes 1 High if EINIT was executed before entering Idle or Power Down mode Low otherwise 2 For multiplexed buses with 8 Bit data bus 3 For demultiplexed buses 4 The CS signal that corresponds to the last address remains active low all other enabled CS signals remain inactive high By accessing an on chip X Periperal prior to entering a power save mode all external CS signals can be deactivated 256 294 ky ST10X167 20 REGISTER SET This section summarizes all registers implemented in the ST10X167 and explains the description format used in the chapters describing the function and layout of the SFRs For easy reference the registers except for GPRs are ordered in two ways Ordered by address to check which re
199. control fields Using the ASC0 Interrupts For normal operation besides the error interrupt the ASC0 provides three interrupt requests to control data exchange via this serial channel S0TBIR is activated when data is moved from SOTBUF to the transmit shift register is activated before the last Bit of an asynchronous frame is transmitted or after the last Bit of a synchronous frame has been transmitted is activated when the received frame is moved to SORBUF While the task of the receive interrupt handler is quite clear the transmitter is serviced by two interrupt handlers This provides advantages for the servicing software For single transfers is sufficient to use the transmitter interrupt SOTIR which indicates that SOTIR SORIR Figure 92 ASCO interrupt generation Synchronous Mode 164 294 RW RW the previously loaded data has been transmitted except for the last Bit of an asynchronous frame For multiple back to back transfers it is necessary to load the following piece of data at last until the time the last Bit of the previous frame has been transmitted In asynchronous mode this leaves just one Bit time for the handler to respond to the transmitter interrupt request synchronous mode it is impossible at all Using the transmit buffer interrupt SOTBIR to reload transmit data gives the time to transmit a complete frame for the service routine as SOTBUF may be reloaded while the
200. controlled in the same way as for the core timer The description and the table apply accordingly Timers T2 and T4 in Timer Mode or Gated Timer Mode When the auxiliary timers T2 and T4 are programmed to timer mode or gated timer mode their operation is the same as described for the core timer T3 The descriptions figures and tables apply accordingly with one exception There is no output toggle latch and no alternate output pin for T2 and T4 Timers T2 and T4 in Counter Mode Counter mode for the auxiliary timers T2 and T4 is selected by setting Bit field TxM in the respective register TxCON to 001b In counter mode timers 2 and 4 can be clocked either by transition at the respective external input pin TxIN or by a Figure 72 Auxiliary timer in counter mode Auxiliary Timer Tx Up Down transition of timer T3 s output toggle latch T3OTL see Figure 72 The event causing an increment or decrement of a timer can be a positive a negative or both a positive and a negative transition at either the respective input pin or at the toggle latch T3OTL Bit field Txl in the respective control register TxCON selects the triggering transition see Table 25 Note Only transitions of T3OTL which are caused by the overflows underflows of T3 will trigger the counter function of T2 T4 Modifications of T3OTL via software will NOT trigger the counter function of T2 T4 For counter operation pin Txl
201. corresponds to the rotation direction of the connected sensor The table below summarizes the possible combinations T3EUD Input Level on respective other input 135 294 ST10X167 The Figure 70 gives examples of T3 s operation visualizing count signal generation and direction control It also shows how input jitter is compensated This might occur if the sensor stays near to one of the switching points Figure 70 Evaluation of the incremental encoder signals Contents of T3 Note This example shows the timer behavior assuming that T3 counts upon any transition on any input T3I2 011b Contents of T3 Note This example shows the timer behavior assuming that T3 counts upon any transition on T3IN input T3I2 001b 136 294 ky Note Timer 3 operating in incremental interface mode automatically provides information on the sensor s current position Dynamic information speed acceleration deceler ation may be obtained by measuring the incoming signal periods This is facilitated by an additional special capture mode for timer T5 9 1 2 GPT1 Auxiliary Timers T2 and T4 Both auxiliary timers T2 and T4 have exactly the same functionality They can be configured like timer gated timer or counter mode with the same options for the timer frequencies and the count signal as the core timer T3 In addition to these T2CON FF40h AOh ST10X167 3 counting modes the auxiliary timers
202. ction register DP4 P4 FFC8h E4h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PR a rss s RW RW RW RW RW RW RW RW 88 294 ky DP4 FFCAh 5 15 14 13 12 11 10 9 8 7 Port direction register DP4 Bit y DP4 y 0 Port line P4 y is an input high SFR ST10X167 Reset Value 00h 6 5 4 3 2 1 0 impedance DP4 y 1 Port line P4 y is an output 6 6 1 Alternate Functions of Port4 During external bus cycles that use segmentation for address space above 64K Byte a number of Port4 pins may output the segment address lines The number of pins that is used for segment address output determines the external address space which is directly accessible The other pins of Port4 if any may be used for general purpose I O If segment address lines are selected the alternate function of Port4 may be necessary to access for external memory directly after reset For this reason Port4 will be switched to this alter nate function automatically Table 13 Port4 Alternate Functions The number of segment address lines is selected via PORTO during reset The selected value can be read from Bitfield SALSEL in register RPOH read only in order to check the configuration during run time Devices with a CAN interface use 2 pins of Port4 to interface the CAN module to an external CAN transceiver In this case the number of possible segment addr
203. ctional Reset Enable 0 RSTIN pin is an input pin only SW Reset or WDT Reset have no effect on this pin 1 RSTIN pin is a bidirectional pin This pin is pulled low during 1024 TCL during reset sequence Oscillator Watchdog Disable Control 0 Oscillator Watchdog OWD is enabled If PLL is bypassed the OWD monitors XTAL1 activity If there is no activity on XTAL1 for at least 1 us the CPU clock is switched automatically to PLUs base frequency around 2 to 10MHz 1 OWD is disabled If the PLL is bypassed the CPU clock is always driven by XTAL1 signal The PLL is turned off to reduce power supply current Power Down Mode Configuration Control 0 Power Down Mode only be entered during PWRDN instruction execution if NMI is low otherwise the instruction has no effect To exit Power Down Mode an external reset must occurs by asserting the RSTIN pin 1 Power Down Mode can only be entered during PWRDN instruction execution if all enabled fast external interrupt EXxIN pins are in their inactive level Exiting this mode can be done by asserting one enabled EXxIN pin Chip Select Configuration Control 0 Latched Chip Select lines CSx change 1 TCL after rising edge of ALE 1 Unlatched Chip Select lines CSx change with rising edge of ALE Write Configuration Control Inverted copy of WRC bit of RPOH 0 Pins WR and BHE retain their normal function 1 Pin WR acts as WRL
204. ctions of these pins instead of the general purpose I O operation the respective port latches have to be set to 1 since the port latch outputs and the alternate output lines are ANDed When an alternate data output line is not used function disabled it is held at a high level allowing I O operations via the port latch The direction of the port lines depends on the operating mode The SSC will automatically use the correct alternate input or output line of the ports when switching modes The direction of the pins however must be programmed by the user as shown in the tables 173 294 ST10X167 Using the open drain output feature helps to avoid bus contention problems and reduces the need for hardwired hand shaking or slave select lines In this case it is not always necessary to switch the direction of a port pin The table below summarizes the required values for the different modes and pins EE Slave Mode mam mes ron P3 13 SCLK Serial Clock Output P3 13 1 DP3 13 1 Serial Clock Input P3 13 x DP3 13 0 P3 9 MTSR Serial Data Output P3 9 1 DP3 9 Serial Data Input P39 x DP3 9 0 P3 8 MRST Serial Data Input P38 x DP3 8 o Serial Data Output P3 8 1 DP3 8 t Note In the table above an x means that the actual value is irrelevant in the respective mode however it is recommended to set these Bit to 1 so they are already in the correct state whe
205. ctive levels Bit ADP which selects the Adapt mode is latched with the rising edge of RSTIN Figure 143 External reset circuitry ST10X167 RSTOUT External Hardware Vpp External amp Reset ES Sources Reset 4 T V a Generated Warm reset 7 b Automatic Power on reset 18 1 1 ST10F167 Synchronous Hardware Reset This synchronous hardware reset is only applicable to ST10F167 Synchronous hardware reset is triggered when the reset input signal RSTIN is sampled low AND the Vpp pin sampled high When a synchronous reset is initiated all pending internal hold states are cancelled and the current internal access 242 294 cycle if any is completed Except in the case of a watchdog reset external bus cycles are aborted Following this the internal reset sequence starts the bus pin drivers and the I O pin drivers are switched off tristate and the PORTO pins are internally pulled high The RSTIN pin is driven low for the duration of the reset sequence which is 516 CPU clock cycles To ensure the recognition of the RSTIN signal latching it must be held low for at least 2 CPU clock cycles Also shorter RSTIN pulses may trigger a hardware reset if they coincide with the latch s sample point However it is recommended to keep RSTIN low for at least 1 ms After the reset sequence has been completed the RSTIN input is sampled When the reset i
206. current conversion sequence auto scan modes Setting Bit ADST while a conversion is running will abort this conversion and start a new conversion with the parameters specified in ADCON Note Stop and restart see above are triggered by Bit ADST changing from 0 to 1 ADST must be 0 before being set While a conversion is in progress the mode selection field ADM and the channel selection field ADCH may be changed ADM will be evaluated after the current conversion ADCH will be evaluated after the current conversion fixed channel modes or after the current conversion sequence auto scan modes 16 1 1 Fixed Channel Conversion Modes These modes are selected by programming the mode selection field ADM in register ADCON to 00b single conversion or to 01b continuous conversion After starting the converter through Bit ADST the busy flag ADBSY will be set and the channel specified in Bit field ADCH will be converted After the conversion is complete the interrupt request flag ADCIR will be set 214 294 In single conversion mode the converter will automatically stop and reset Bit ADBSY and ADST In continuous conversion mode the converter will automatically start a new conversion of the channel specified in ADCH ADCIR will be set after each completed conversion When Bit ADST is reset by software while a conversion is in progress the converter will complete the current conversion and then stop
207. d Baud rate generator enabled 3 157 294 ST10X167 A transmission is started by writing to the Transmit Buffer register SOTBUF via an instruction or a PEC data transfer Only the number of data Bit which is determined by the selected operating mode will actually be transmitted Bit written to positions 9 through 15 of register SOTBUF are always insignificant After a transmission has been completed the transmit buffer register is cleared to 0000h Data transmission is double buffered so a new character may be written to the transmit buffer register before the transmission of the previous character is complete This allows the transmission of characters back to back without gaps Data reception is enabled by the Receiver Enable Bit SOREN After reception of a character has been completed the received data and if provided by the selected operating mode the received parity Bit can be read from the read only Receive Buffer register SORBUF Bit in the upper half of SORBUF which are not valid in the selected operating mode will be read as zeros Data reception is double buffered so that reception of a second character may already begin before the previously received character has been read out of the receive buffer register In all modes receive buffer overrun error detection can be selected through Bit SOOEN 158 294 When enabled the overrun error status flag SOOE and the error interrupt request flag SOEIR w
208. d Only IP is saved restored ROMS1 Internal Memory Mapping 0 Internal ROM memory area mapped to segment 0 00 0000h 00 7FFFh 1 Internal ROM memory area mapped to segment 1 01 0000h 01 7FFFh STKSZ System Stack Size Selects the size of the system stack in the internal RAM from 32 to 1024 Words The layout of the five BUSCON registers is identical Registers BUSCON4 BUSCON1 which control the selected address windows are completely under software control while register BUSCONO which is also used for the very first code access after reset is partly controlled by BUSCONO FFOCh 86h 15 14 11 10 hardware and it is initialized via PORTO during the reset sequence This hardware control allows to define an appropriate external bus for systems where no internal program memory is provided Bit 13 is not available to the ST10F167 Reset Value 0OXXOh 4 3 2 1 0 caer Sees pape me RW BUSCON1 FF14h 8Ah RW ResetValue 0000h 11 coe oven Fosse ores e BUSCON FF16h 8Bh SFR Reset Value 0000h 14 11 10 4 2 1 ces e pe em 1 BUSCONS FF18h 8Ch SFR Reset Value 0000h 11 Eee r meses T ww em BUSCON4 FF1Ah 8Dh SFR Reset Value 0000h 14 11 10 4 2 1 ky 119 294 ST10X167 Memory Cycle Time Control Number of memory cycle time waitstates 00
209. d with a Port3 pin is configured to use the alternate output function its Alternate Data Output line is ANDed with the port output latch line When using these alternate functions the user must set the direction of the port line to output DP3 y 1 and must set the port output latch P3 y 1 Otherwise the pin is in its high impedance state when configured as input or the pin is stuck at 0 when the port out put latch is cleared When the alternate output functions are not used the Alternate Data Out put line is in its inactive state which is a high level 17 Port3 pins with alternate output functions are T6OUT TxD0 and CLKOUT When the on chip peripheral associated with a Port3 pin is configured to use both the alternate input and output function the descriptions above apply to the respective current operating mode The direction must be set accordingly Port3 pins with alternate input output functions are MTSR MRST RxD0 and SCLK Note Enabling the CLKOUT function automati cally enables the P3 15 output driver Set ting Bit DP3 15 1 is not required Figure 33 Block diagram of Port3 pin with alternate input or alternate output function Write ODP3 y Open Drain Latch Read ODP3 y Write Internal Bus Direction Latch Read DP3 y lt lt I Write P3 y Alternate Data Input Port Data Output f Port Output Latch Read P3 y gt
210. diagram Compare Register CCx Interrupt CCxIR gt Request Comparator Interrupt CAPCOM Timer Ty Request Comparator Compare Register CCz CCMODz Interrupt CCzIR Request X 2 23 16 7 0 y 0 1 7 8 z 31 24 15 8 In this configuration example the same timer allocation was chosen for both compare registers but each register may also be individually allocated to one of the two timers of the respective CAPCOM unit In the timing example for this compare mode below the compare values in registers CCx and CCz are not modified ky 197 294 ST10X167 The pins CCzlO which are not selected for double register compare mode may be used for general purpose Figure 115 Timing example for double register compare mode Contents of Ty FFFFh Compare Value cv2 Compare Value cv1 Reload Value lt TyREL gt 0000h Interrupt Requests CCxIR CCxIR TyIR CCxIR CCxIR TyIR State of CCxIO t x 23 16 7 0 0 1 7 8 z 31 24 15 8 14 6 Capture Compare Interrupts Note Each of the 32 capture compare Upon a capture or compare event the interrupt registers CCO CC31 has its own request flag CCxIR for the respective capture Bitaddressable interrupt control register compare register CCx is set to 1 This flag can be CCOIC CC311C and its own interrupt used to generate an interrupt or trigger a PEC vector CCOINT CC31INT Th
211. dressable constant of all zeros for Bit manipulation or mask generation It can be accessed via any instruction which is capable of addressing an SFR ZEROS FF1Ch 8Eh SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ae R R R R R R R R R R R R R R R R 4 4 14 The Constant Ones Register ONES All Bit of this Bit addressable register are fixed to 1 by hardware This register can be read only Register ONES can be used as a register addressable constant of all ones for Bit manipulation or mask generation It can be accessed via any instruction which is capable of addressing an SFR ONES FF1Eh 8Fh SFR Reset Value FFFFh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PR EA ER pem rem eem pem cupere peres R R R R R R R R R R R R R R R R 4 4 15 Example Mask for FFFFh values use to increment or decrement memory sub mem ones mem mem 1 increments the memory location in one instruction instead of three as described below mov R13 mem mem gt 13 add R13 1 R13 1 mov mem R13 R13 gt mem 54 294 ky 5 INTERRUPT AND TRAP FUNCTIONS The architecture of the ST10X167 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller These mechanisms include Normal interrupt processing The CPU temporarily suspends the current pro
212. dule The CAN Module is implemented as an X Peripheral and is therefore accessed like an external memory or peripheral so the registers of the CAN Module can be read and written using 16 Bit or 8 Bit direct or indirect MEM addressing modes Since the XBUS to which the CAN Module is connected also represents the external bus CAN accesses follow the same rules and procedures as accesses to the external bus CAN accesses cannot be executed in parallel to external instruction fetches or data read writes but are arbitrated and inserted into the external bus access stream Accesses to the CAN Module use de multiplexed addresses and a 16 Bit data bus Byte accesses possible Two wait states give an access time of 8TCL 4 CPU clock cycles No tristate waitstate is used The CAN address area starts at 00 EFOOh and covers 256 Byte A dedicated hardwired XADRS XBCON register pair selects the respective address window so none of the programmable register pairs must be sacrificed in order to access the on chip CAN Module Locating the CAN address area to address OO EFOOh in segment 0 has the advantage that the CAN Module is accessible via data page 3 which is the system data page accessed usually through the system data page pointer DPP3 In this way the internal addresses such like SFRs internal RAM and the CAN registers are all located within the same data page and form a contiguous address space Power Down Mode If the S
213. duplex communication Data is transmitted or received on pins MTSR P3 9 Master Transmit Slave Receive and MRST P3 8 Master Receive Slave Transmit The clock signal is output or input on pin SCLK P3 13 These pins are alternate functions of Port3 pins 165 294 ST10X167 Figure 93 SFRs and port pins associated with the SSC Ports amp Direction Control Alternate Functions 15141312111098 76543210 Control Registers 1514131211109876543210 SSCCON Y Y YY YYY YYYYYYY SCLK P3 13 MTSR P3 9 MRST P3 8 ODP3 DP3 SSCBR SSCTB SSCTIC Port3 Open Drain Control Register Port3 Direction Control Register SSC Baud Rate Generator Reload Register SSC Transmit Buffer Register write only SSC Transmit Interrupt Control Register Y Bit is linked a function Bit has no function or is not implemented E Register is in ESFR internal memory space 166 294 Data Registers 1514131211109876543210 YYYYYYYYYYYYYYYY YYYYYYYYYYYYYYYY SSCRBE Y Y Y Y Y YYYYYYYYYYY Interrupt Control SSCBRE SSCTBE 15141312111098 76543210 YYYYYYYY SSCTIC SSCRIC c YYYY Y Y Y Y c YYYNYY Y Y Y SSCEIC P3 Port3 Data Register SSCCON SSC Control Register SSCRB SSC Receive Buffer Register read only SSCRIC SSC Receive Interrupt Control Register SSCEIC SSC Error Interrupt Control Register 3 ST10X167 Figure 94 Synchronous serial channel SSC block diagram Slave Clock Baud
214. e 00h 59 Reset Value 0000h 54 ST10X167 24 REVISION HISTORY 24 1 Revision of the 28th of August 2000 This is revision 1 1 of this document released on 28th of August 2000 The differences between previous revisions and revision 1 1 are page 6 Table of content chap18 Previous revision 18 1 to 18 5 New revision 18 1 to 18 6 reflects the modifications of the text page 10 Abbreviations IRAM on chip Internal RAM added page 11 figure 1 XTAL1 XTAL2 RxD TxD added page 12 figure 2 up date block diagram with XRAM page 17 figure 3 updated with POH 7 POH 6 POH 5 pins table 1 addition of footnote page 18 chapter 2 4 1 Vdd all Vcc changed to Vdd page 24 chapter 3 figure 4 updated page 26 figure 6 updated page 30 figure 8 RAM SFR area changed from 00 F000h to 00 F600h page 40 chapter 4 4 1 Syscon bit OWDDIS PLL base frequency 2 to 10 MHz WRCFG bit text updated page 47 figure 15 updated CP register text Do not set CP below IRAM start address 00 F600h 2K Byte page 50 chapter 4 4 12 MDC register bit MS added page 55 chapter 5 1 order of comments and note of table6 are inverted page 82 figure 31 updated page 83 chapter 6 5 text ODP2 changed to ODP3 page 84 figure 32 pin WRH changed to WRH page 91 chapter 6 8 1 figure 39 updated page 96 figure 44 read
215. e Modes 191 GAPTURE MODBE 2 ttti pire tee eet rebote hides det eee Pera 191 COMPARE MODES ub E E ut 192 Mode Urrainn cde e LH ERE 193 Compare Mode Tau ede erede Dee EU tee ee 194 Compare MOC 2 u u nm eui ed Peg Ei UE ED e BRE ined 195 Compare Mode 3 cinere HR ee nn 196 Double Register Compare Mode sese 196 CAPTURE COMPARE INTERRUPTS 02 198 PULSE WIDTH MODULATION MODULE u u u 200 OPERATING MODES sie Sula a ayasa 202 Mode 0 Standard PWM Generation Edge Aligned 202 Mode 1 Symmetrical PWM Generation Center Aligned PWM 204 Burst rete 205 Single Shot Mode au asua Deni pne Le cese nee 206 PWM MODULE REGISTERS sai huan Y ariaa 207 INTERRUPT REQUEST 209 PWM OUTPUT SIGNALS n g D er eii qe P upaya sayis nan 210 ANALOG DIGITAL CONVERTER u 211 MODE SELECTION AND 2 104042 02 00000000 00030000000 00 212 Fixed Channel Conversion 214 Auto Scan Conversion 214 Wait for ADDAT Read M
216. e T8 respectively Counter Mode The Bit TxM in SFRs TO1CON and T78CON select between timer or counter mode for the respective timer In Counter mode 17 the input clock for a timer can be derived from the overflows underflows of timer T6 in block GPT2 In addition timers TO and T7 can be clocked by external events Either a positive a negative or both a positive and a negative transition at pin TOIN alternate input function of port pin P3 0 or T7IN alternate input function of port pin P2 15 respectively can be selected to cause an increment of TO T7 When T1 or T8 is programmed to run in counter mode Bit field Txl is used to enable the overflows underflows of timer T6 as the count source This is the only option for T1 and T8 and itis selected by the combination Txl X00b When Bit field Txl is programmed to any other combination the respective timer T1 or T8 will stop When TO or T7 is programmed to run in counter mode Bit field Txl is used to select the count source and transition if the source is the input pin which should cause a count trigger see description of TxyCON for the possible selections Note In order to use pin TOIN or T7IN as exter nal count input pin the respective port pin 188 294 must be configured as input and the cor responding direction control Bit DP3 0 or DP2 15 must be cleared 0 If the respective port pin is configured as output the associated timer may be c
217. e function of the external output pin T6OUT P3 1 For that purpose a 1 must be written into port data latch P3 1 and pin P3 1 must be configured as output by setting direction control Bit DP3 1 to 1 If TEOE 1 pin T6OUT then outputs the state of T6OTL If T6OE 0 pin T6OUT can be used as general purpose I O pin In addition T6OTL can be used in conjunction with the timer over underflows as an input for the counter function of the auxiliary timer T5 For this purpose the state of TGOTL does not have to be cPU ft __ 4 x 2 16 rte Hs available at pin T6OUT because an internal connection is provided for this option An overflow or underflow of timer T6 can also be used to clock the timers in the CAPCOM units For this purpose there is a direct internal connection between timer T6 and the CAPCOM timers Timer 6 in Timer Mode Timer mode for the core timer T6 is selected by setting Bit field T6M in register to 000b In this mode T6 is clocked with the internal System clock divided by a programmable pre scaler which is selected by Bit field T6l The input frequency frg for timer T6 and its resolution are scaled linearly with lower clock frequencies fcpy as can be seen from the following formula 4 x 2 16 fceu MHz Figure 79 Block diagram of core timer T6 in timer mode Edge Select Core Timer T6 Up Down Interrupt Request T6OUT Os
218. e master to another device in the network In this case the previous master and the future master previous slave will have to toggle their operating mode SSCMS and the direction of their port pins see description above 11 2 Half Duplex Operation In a half duplex configuration only one data line is necessary for both receiving and transmitting of data The data exchange line is connected to both pins MTSR and MRST of each device the clock line is connected to the SCLK pin The master device controls the data transfer by generating the shift clock while the slave devices receive it Due to the fact that all transmit and receive pins are connected to the one data exchange line serial data may be moved between arbitrary stations Similar to full duplex mode there are two ways to avoid collisions on the data exchange line Only the transmitting device may enable its transmit pin driver The non transmitting devices use open drain output and only send ones Since the data inputs and outputs are connected together a transmitting device will clock in its own data at the input pin MRST for a master device MTSR for slave By these means any corruptions on the common data exchange line are detected where the received data is not equal to the transmitted data ky Figure 97 SSC half duplex configuration Device 1 Shift Register Continuous Transfers When the transmit interrupt request f
219. e output XTAL2 will still be active in Adapt Mode Bootstrap loader mode Pin POL 4 BSL activates the on chip bootstrap loader when low during hardware reset The bootstrap loader allows moving the start code into the internal RAM of the ST10X167 via the serial interface ASCO The MCU will remain in bootstrap loader mode until a hardware reset with POL 4 high or a software reset The bootstrap loader acknowledge Byte is C5h Default The ST10X167 starts fetching code from location 00 0000h the bootstrap loader is off External bus type Pins POL 7 and POL 6 BUSTYP select the external bus type during reset if an external start 250 294 is selected via pin EA This allows the configuration of the external bus interface of the ST10X167 even for the first code fetch after reset The two Bit are copied into Bit field BTYP of register BUSCONO POL 7 controls the data bus width while POL 6 controls the address output multiplexed or demultiplexed This Bit field may be changed via software after reset if required BTYP External Data External Address Encoding Bus Width Bus Mode 8 Bit Data Demultiplexed Addresses 01 8 Bit Data Multiplexed Addresses 10 16 Bit Data Demultiplexed Addresses 16 Bit Data Multiplexed Addresses PORTO and PORT1 are automatically switched to the selected bus mode In multiplexed bus modes PORTO drives both the 16 Bit intra segment address and the output data while PORT remains in high impedance
220. e respective PEC channel remains idle and the associated interrupt service routine is activated instead This allows to choose if a level 15 or 14 request is to be serviced by the PEC or by the interrupt service routine Note transfers are only executed if their priority level is higher than the CPU level for example only PEC channels 7 4 are processed while the CPU executes on level 14 All interrupt request sources that are enabled and programmed for PEC service should use different channels Otherwise only one transfer will be per formed for all simultaneous requests When COUNT is decremented to 00 and the CPU is to be interrupted an incor rect interrupt vector will be generated The source and destination pointers specify the locations between which the data is to be moved A pair of pointers SRCPx and DSTPx is associated with each of the 8 PEC channels These pointers do not reside in specific SFRs but are mapped into the internal RAM of the ST10X167 just below the bit addressable area see Figure 19 Figure 19 Mapping of PEC pointers into the internal RAM 00 FCFEh 00 FCFCh 00 FCFAh 00 FCF8h 00 FCEEh 00 FCECh 00 FCEAh 00 FCE8h 00 FCE6h 00 FCE4h 00 FCE2h 00 FCE0h 00 FCF6h 00 FCF4h 00 FCF2h 00 FCF0h 63 294 ST10X167 PEC data transfers do not use the data page pointers DPP3 DPP0 The source and destination pointers are used as 16 bit intra segment addresses wi
221. e the respective port see Partic put latches check how the alternate data output is ular Pipeline Effects in chapter The Cen combined with the respective port latch output tral Processing Unit SINGLE_Bit BSE P4 7 Initial output level is high BSE DP4 7 Switch on the output driver Bit_GROUP BFLDH P4 24H 24 Initial output level is high BFLDH DP4 24H 24H Switch on the output drivers 6 2 PortO The two 8 Bit ports POH and POL represent the higher and lower part of PORTO respectively Both halves of PORTO can be written for example via a PEC transfer without effecting the other half If this port is used for general purpose I O the direction of each line can be configured via the correspond ing direction registers DPOH and DPOL POL FFOOh 80h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T T T T T Ter Tr Tre RW RW RW RW RW RW RW RW FF02h 81h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C br l br d eon pons pora eon Po RW RW RW RW RW RW RW RW POX y Port data register POH or POL Bit y ky 77 294 ST10X167 DP0L F100h 80h 15 14 13 12 11 10 9 8 7 ESFR Reset Value 00h 6 5 4 3 2 1 0 RW DP0H F102h 81h 15 14 13 12 11 10 9 8 7 ESFR 6 5 4 3 2 1 0 RW RW RW RW RW RW RW Port direction register DPOH or DPOL Bit y DPOX y 0 Port line POX
222. ead Mode there may be delays due to suspended conversions However this only affects the conversions if the CPU or PEC cannot keep track with the conversion rate Hold Result in Temp Latch Read of ADDAT i m Result of Channel 3 2 1 0 215 294 ST10X167 16 1 4 Channel Injection Mode Channel Injection Mode allows the conversion of a specific analog channel also while the ADC is running in a continuous or auto scan mode without changing the current operating mode After the conversion of this specific channel the ADC continues with the original operating mode Channel Injection mode is enabled by setting Bit ADCIN in register ADCON and requires the Wait for ADDAT Read Mode ADWR 1 The channel to be converted in this mode is specified in Bit field CHNR of register ADDAT2 These 4 Bit in ADDAT2 are not modified by the A D converter but only the ADRES Bit field Since the channel number for an injected conversion is not buffered Bitfield CHNR of ADDAT2 must never be modified during the sample phase of an injected conversion otherwise the input multiplexer will switch to the new channel It is recommended to only change the channel number with no injected conversion running see Figure 127 A channel injection can be triggered in two ways Setting the Channel Injection Request Bit ADCRQ via software a compare or a capture event of Capture Compare register CC31 of the CAPCOM2 Un
223. ed from PORTO so either external accesses can take place or the external control signals are inactive The general purpose I O pins remain in input mode high impedance until reprogrammed via software see Figure 146 The RSTOUT pin remains active low until the end of the initialization routine see description Figure 144 Bi directional reset hardware implementation Reset node ST10C167 ST10R167 RSTIN S gt Figure 145 PORTO sample timing BiDirRes Software reset and watchdog timer reset bidirectional reset enabled 1024 TCL RSTIN BiDirRes SW or WDT reset 244 294 10 TCL o motansperent _ Figure 146 Synchronous reset RSTOUT ST10X167 Initialization Internal Reset Condition Initialization When the internal reset condition is prolonged by RSTIN the activation of the output signals is delayed until the end of the internal reset condition 1 Current bus cycle is completed or aborted 2 Switches asynchronously with RSTIN synchronously upon software or watchdog reset The reset condition ends here The ST10 starts program execution 3 4 Activation of the I O pins is controlled by software 5 Execution of the EINIT instruction 6 10 This duration designates the internal reset sequence which starts after a low level is sampled on RSTIN Internal reset duration is 24 TCL Reset output pin The RS
224. eee re dene 115 8 3 6 READY READY Controlled Bus Cycles 115 8 3 7 Programmable Chip Select Timing Control a 116 8 4 CONTROLLING THE EXTERNAL BUS CONTROLLER 117 8 4 1 Definition of Address 121 8 4 2 Address Window Arbitration 2 122 8 4 3 Precautions and Hints uuu ee ee de eee Da eta 123 8 5 EBC IDLE STATE m 123 8 6 EXTERNAL BUS 124 8 6 1 Connecting Bus Masters 125 8 6 2 Entering the Hold State u Ausia sas taunted Hasa saka was rasa 125 8 6 3 Exiting the Hold State aa uwa nece erect eec 126 8 7 THE XBUS INTEREAGE a 127 9 THE GENERAL PURPOSE TIMER UNITS eren nnne 128 9 1 TIMER BLOCK GP11 ii i in ni ieee 128 9 1 1 GPT Gore Timer 130 9 1 2 Auxiliary Timers T2 and 137 9 1 3 Interrupt Control for 142 9 2 TIMER BLOCK GPT 2 nei 143 9 2 1 GPT2 Core Timer 6 aiii eee deoa pere Leere 145 9 2 2 Interrupt Control for GPT2 Timers and CAPREL sse 154 10 ASYNCHRONOUS SYNCHRONOUS SERIAL INTER
225. een selected for capture mode the current contents of the allocated timer will be latched captured into the capture compare register in response to an external event at the port pin which is associated with this register In addition a specific interrupt request for this capture compare register is generated Either a positive a negative or both a positive and a negative external signal transition at the pin can be selected as the triggering event The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers When a match occurs between the timer value and the value in a capture compare register specific actions will be taken based on the selected compare mode 2 5 10 Pulse Width Modulation Unit The Pulse Width Modulation Module can generate up to four PWM output signals using edge aligned or centre aligned PWM In addition the PWM module can generate PWM burst signals and single shot outputs In Burst Mode two channels can be combined with their output signals ANDed where one channel gates the output signal of the other channel In Single Shot Mode a single output pulse is generated retriggerable under software control Each PWM channel is controlled by an up down counter with associated reload and compare registers The polarity of the PWM output signals may be controlled via the respective port output latch combinat
226. efore the division is started After any division register MDL represents the 16 Bit quotient MDL FEOEh 07h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MDL RW MDL Specifies the low order 16 Bit of the 32 Bit multiply and divide register MD Whenever this register is updated via software the Multiply Divide Register In Use MDRIU flag in the Multiply Divide Control register MDC is set to 1 The MDRIU flag is cleared whenever the MDL register is read via software When a multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed within the interrupt service routine register MDL must be saved along with registers MDH and MDC to avoid erroneous results A detailed description of how to use the MDL register for programming multiply and divide algorithms can be found in Chapter 21 System Programming 4 4 12 The Multiply Divide Control Register MDC This Bit addressable 16 Bit register is implicitly used by the CPU when it performs a multiplication or a division It is used to store the required control information for the corresponding multiply or divide operation Register MDC is updated by hardware during each single cycle of a multiply or divide instruction MDC FFOEh 87h SFR ResetValue 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW Multiply Divide Register In Use 0 Cleared when register MDL is re
227. egister It will not wait for the next clock from the Baud rate generator as the master does The reason for this is that depending on the selected clock phase the first clock edge generated by the master may be already used to clock in the first data Bit So the slave s first data Bit must already be valid at this time Note A transmission and a reception takes place at the same time regardless whether valid data has been transmitted or received This is different from asynchronous reception on ASCO The initialization of the SCLK pin on the master requires some attention in order to avoid 172 294 undesired clock transitions which may disturb the other receivers The state of the internal alternate output lines is 1 as long as the SSC is disabled This alternate output signal is ANDed with the respective port line output latch Enabling the SSC with an idle low clock 55 07 will drive the alternate data output and via the AND the port pin SCLK immediately low To avoid this use the following sequence Select the clock idle level SSCPO x Load the port output latch with the desired clock idle level P3 13 x Switch the pin to output DP3 13 1 Enable the SSC SSCEN 1 f SSCPO 0 enable alternate data output P3 13 1 The same mechanism as for selecting a slave for transmission separate select lines or special commands may also be used to move the role of th
228. egisters the address area 00 E000 to 00 E7FFy is reserved for XRAM accesses 3 3 1 XRAM Access Via External Masters When Bit XPER SHARE in register SYSCON is set the on chip XRAM of the ST10X167 can be accessed by an external master during hold mode via the ST10X167 s bus interface These external accesses must use the same configuration as the internally programmed demultiplexed bus 100 ns minimum access cycle time No waitstates are required The configuration in register SYSCON cannot be changed after the execution of the EINIT instruction Figure 8 On chip XRAM area Internal RAM SFR Area 00 F600h CAN Module OO EFOOh Reserved E7FFh On chip un XRAM 00 E000h Data Page 3 16K Byte External Access Note 1 The address area 00 E800h to 00 EEFFh is mapped external memory but should be reserved for reasons of upward compatibility ky 3 4 External Memory Space The ST10X167 is capable of using an address space of up to 16M Byte Only parts of this address space are occupied by internal memory areas All addresses which are not used for on chip memory Flash ROM or RAM or for registers may refer to external memory locations This external memory is accessed via the ST10X167 s external bus interface Four memory bank sizes are supported Non segmented mode 64K Byte with A15 A0 on PORTO or PORT1 2 Bit segmented mode 256K Byte with 17 16 on Port4 and A15
229. els CC8 CC15 so the capture compare function cannot be used on the respective Port2 pins with EXIxES z 00b However general purpose I O is possible in all cases Note fast external interrupt inputs are sam pled every 8 CPU clock cycle The inter rupt request arbitration and processing is executed every 4 CPU clock cycles 5 7 Trap Functions Traps interrupt the current execution like standard interrupts do However trap functions offer the possibility to bypass the interrupt system prioritization process in cases where immediate System reaction is required Trap functions are not maskable and always have priority over interrupt requests on any priority level The ST10X167 provides two different kinds of trap mechanisms Hardware traps are triggered by events that occur during program execution like illegal access or undefined opcode software traps are initiated via an instruction within the current execution flow 5 7 1 Software Traps The TRAP instruction is used to cause a software call to an interrupt service routine The trap number that is specified in the operand field of the trap instruction determines which vector location in the address range from 00 0000h through 00 01FCh will be branched to Executing a TRAP instruction causes the same effect as servicing the interrupt at the same vector PSW CSP in segmentation mode and IP are pushed on the internal system stack and a jump is taken to the specif
230. en accessing external devices like latches or drivers that only provide a single enable input Note CSO provides an address chip select directly after reset except for single chip mode when the first instruction is fetched Internal pull up devices hold all CS lines high during reset After the end of a reset sequence the pull up devices are switched off and the pin drivers control the pin levels on the selected CS lines Not selected CS lines will enter the high impedance state and are available for general purpose The pull up devices also active during bus hold on the selected CS lines while HLDA is active and the respective pin is switched to push pull mode Open drain outputs will float during bus hold In this case external pull up devices are required or the new bus master is responsible for driving appropriate levels on the CS lines 8 2 8 Segment Address Versus Chip Select Note This feature is not available for the ST10F167 The external bus interface supports many configurations for the external memory By increasing the number of segment address lines a linear address space of 256K Byte 1M Byte or 16M Byte can be addressed It is possible to implement a large memory area and to access a great number of external devices using an external decoder By increasing the number of CS line accesses can be made to Gr ST10X167 memory banks or peripherals without external glue logic These t
231. en the last stop Bit has been received the content of the receive shift register is transferred to the receive data buffer register SORBUF Simultaneously the receive interrupt request flag SORIR is set after the 9th sample in the last stop Bit time slot as programmed regardless whether valid stop Bit have been received or not The receive circuit then waits for the next start Bit 1 to 0 transition at the receive data input pin The receiver input pin RXDO P3 11 must be configured for input using direction control register DP3 11 0 Asynchronous reception is stopped by clearing Bit SOREN A currently received frame is completed including the generation of the receive interrupt request and an error interrupt request if appropriate Start Bit that follow this frame will not be recognized Note In wake up mode received frames are only transferred to the receive buffer register if the 9th Bit the wake up Bit is 1 If this Bit is 0 no receive interrupt request will be activated and no data will be transferred 10 2 Synchronous Operation Synchronous mode supports X half duplex communication basically for simple I O expansion via shift registers Data is transmitted and received via pin RXDO P3 11 while pin TXDO P3 10 outputs the shift clock These signals are alternate functions of Port3 pins Synchronous mode is selected with SOM 000b 8 data Bit are transmitted or received synchronous to a shift clock
232. ency see Figure 86 This combined mode can be used to detect consecutive external events which may occur periodically but where a finer resolution that means more ticks within the time between two external events is required For this purpose the time between the external events is measured using timer T5 and the CAPREL register For example Timer T5 runs in timer mode counting up with a frequency of fcpu 32 The external events are applied to pin CAPIN When an external event occurs the timer T5 contents are latched into register CAPREL and timer T5 is cleared T5CLR 1 ST10X167 Thus register CAPREL always contains the correct time between two events measured in timer 5 increments Timer T6 which runs in timer mode counting down with a frequency of fcpy 4 uses the value in register CAPREL to perform a reload on underflow This means the value in register CAPREL represents the time between two underflows of timer T6 now measured in timer T6 increments Since timer T6 runs 8 times faster than timer T5 it will underflow 8 times within the time between two external events Thus the underflow signal of timer T6 generates 8 ticks Upon each underflow the interrupt request flag T6IR will be set and Bit T6OTL will be toggled The state of TEOTL may be output on T6OUT This signal has 8 times more transitions than the signal which is applied to pin CAPIN The underflow signal of timer T6 can furthe
233. ended Special Function Register Non volatile memory that may be electrically erased General Purpose Register GPT HLL IRAM PLL PWM RAM RISC ROM SFR SSC XBUS XRAM General Purpose Timer unit High Level Language On chip Internal RAM Input Output Peripheral Event Controller Programmable Logic Array Phase Locked Loop Pulse Width Modulation Random Access Memory Reduced Instruction Set Computing Read Only Memory Special Function Register Synchronous Serial Controller Internal representation of the External Bus On chip extension RAM 2 ARCHITECTURAL OVERVIEW ST10X167 architecture combines the advantages of both RISC and CISC processors with an advanced peripheral subsystem The following block diagram gives an overview of the different on chip components and of the advanced high bandwidth internal bus structure of the ST10X167 see Figure 1 2 1 Basic CPU Concepts and Optimizations The main core of the CPU includes a 4 stage instruction pipeline a 16 Bit arithmetic and logic unit ALU and dedicated SFRs Additional hardware is provided for a separate multiply and divide unit a Bit mask generator and a barrel shifter See Figure 2 Several areas of the processor core have been optimized for performance and flexibility Figure 1 ST10X167 functional block diagram 128K Byte Flash 32K Byte ROM ST10X167 Functional blocks in the CPU core are controlled by signals f
234. ent is again subdivided into four data pages of 16K Byte each see Figure 4 Most of the internal memory areas are mapped into segment 0 named system segment The upper Figure 4 Memory areas and address space Segment 254 Segment 255 02 0000 07 06 Segment 64K Byte 05 Segment 1 04 03 02 Segment 0 01 Page 16K Byte 00 Data Page Number Absolut Memory Address 26 294 Address space 16M Byte Byte of segment 0 00 F000h 00 FFFFh hold the Internal RAM and Special Function Register Areas SFR and ESFR The lower 32K Byte of segment 0 00 0000h 00 7FFFh can be occupied by a part of the on chip ROM or Flash Memory and is called the internal ROM area This ROM area can be remapped to segment 1 01 0000h 01 7FFFh to enable external memory access in the lower half of segment 0 or the internal ROM may be disabled Code and data may be stored in any part of the internal memory areas except for the SFR blocks which may be used for control data but not for instructions Note Accesses to the internal ROM areas on ROMless devices will produce unpredict able results IRAM SFR Area O0 FSFF CAN 00 EF00 00 E7FF XRAM 00 E000 External 00 C000 S Memory Internal ROM or Flash Area depending 004000 on device External Memory for Romless device System segment 0 64K Byte stored at even odd addresses Words are st
235. er gated timer or counter mode with the same options for the timer frequencies and the count signal as the core timer T6 In addition to these 3 counting modes the auxiliary timer can be concatenated with the core timer The auxiliary timer has no output toggle latch and no alternate output function The individual configuration for timer T5 is determined by its Bitaddressable control register T5CON Note that functions which are present in both timers of block GPT2 are controlled in the same Bit positions and in the same manner in each of the specific control registers Reset Value 0000h 7 6 1 sepe a 39 T m T5I Timer 5 Input Selection Depends on the Operating Mode see respective sections Timer 5 Mode Control Basic Operating Mode 0 0 Timer Mode 0 1 Counter Mode 1 0 Gated Timer with Gate active low 11 Gated Timer with Gate active high Timer 5 Run Bit T5R 0 Timer Counter 5 stops 1 Timer Counter 5 runs Timer 5 Up Down Control TSUDE Timer 5 External Up Down Enable Capture Trigger 3 0 Capture triggered from CAPIN pin 1 Capture triggered from T3 input pin Register CAPREL Input Selection 0 0 Capture disabled 0 1 Positive transition rising edge on CAPIN 1 0 Negative transition falling edge on CAPIN a Any transition rising or falling edge on CAPIN Timer 5 Clear Bit T5CLR 0 Timer 5 not cleared on a capture T5CLR 1 Timer 5 i
236. er 0000h PECC7 FECEh PEC Channel 7 Control Register 0000h L FFOOh Low Register Lower half of PORTO H FFObh Port High Register Upper half of PORTO PECC3 FEC6h PEC Channel 3 Control Register 0000h m o gt o gt PO PO gt 0 0 0 gt i Serial Channel 0 Transmit Buffer Register write only 0 i i Port1 Low Register Lower half of PORT1 Oh Oh Oh E LE NM 40 O Zz c n 1 9 c TITT 9m ECM EM o O 5 5 5h 6h 7h 8h 9h h Bh h Dh Eh Fh Oh 7h 8h 9h h Oh 2h 3h 4h 5h 6h 7h Oh 2h 3h 6h 7h 8h 9h h Bh h Dh 3 268 294 ST10X167 Table 44 Registers ordered by address continued Physical 8 bit Reset ZEROS b FF1Ch Constant Value 0 s Register read only 0000h ONES FFiEh 8Fh_ Constant Value 1 s Register read only FFFFh m EN m 5 b CAPCOM Mode Control Register 5 0000h 7 28 CAPCOM Mode Control Register 7 0000h N lt Q z c 1 U z O U z lt 9 o 5 n n S ELM A9 NM 71 Aj A gt Timer 4 Control Register 0000h GPT2 Timer 5 Control Register 0000h
237. er Clear Control Clock 2 Run Match 5 Pour Shadow Register Write Control User readable amp writeable register PWx Pulse Width Register 15 1 Operating Modes The PWM module provides four different operating modes Mode 0 standard PWM generation edge aligned PWM available on 4 channels Mode 1 Symmetrical PWM generation center aligned PWM available on all four channels Burst mode combines channels 0 and 1 Single shot mode available on channels 2 and 3 Note The output signals of the PWM module are XORed with the outputs of the respective port output latches After reset these latches are cleared so the PWM signals are directly driven to the port pins By set ting the respective port output latch to 1 the PWM signal may be inverted XORed with 1 before being driven to the port pin The descriptions below refer to the stan dard case after reset which is direct drive 15 1 1 Mode 0 Standard PWM Generation Edge Aligned PWM Mode 0 is selected by clearing the respective Bit PMx in register PWMCONT to 0 In this mode the timer PTx of the respective PWM channel is always counting up until it reaches the value in the associated period shadow register Upon the next count pulse the timer is reset to 0000h and continues counting up with subsequent count pulses The PWM output signal is switched to high level when the timer contents are equal
238. er T3 in timer mode Interrupt Request T3OUT P3 3 The timer resolutions which result from the selected pre scaler option are listed in the Table 22 This table also applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 and T4 in timer and gated timer mode Table 22 GPT1 timer resolutions Pre scaler factor Resolution in CPU clock cycles Refer to the device datasheet for a table of timer input frequencies resolution and periods for the range of pre scaler options Timer 3 in Gated Timer Mode Gated timer mode for the core timer T3 is selected by setting Bit field T3M in register to 010b or 011b Bit T3M 0 T3CON 3 selects the active level of the gate input In gated timer mode the same options for the input frequency as for the timer mode are available However the input clock to the timer in this mode is gated by the external input pin T3IN Timer T3 External Input which is an alternate function of P3 6 To enable this operation pin T3IN P3 6 must be configured as input and direction control Bit DP3 6 must contain 0 see Figure 66 If T3M 0 0 the timer is enabled when T3IN shows a low level A high level at this pin stops the timer If T3M 0 1 pin T3IN must have a high level in order to enable the timer In addition the timer can 132 294 8 te 3 1 2 s2 1024 e 6 t 256 512 1024
239. er teat decere read 31 3 3 THE ON CHIPXRAM ttn tene dene ee Dune cea a 32 3 8 1 XRAM Access Via External Masters 32 3 4 EXTERNAL MEMORY SPACE bic e bottes ie e EH Rie tee ee 33 ST10X167 3 5 CROSSING MEMORY BOUNDARIES esee 33 4 THE CENTRAL PROCESSING UNIT CPU 34 4 1 INSTRUCTION PIPELINESu u eter ito terere Pte Pete ern 35 4 1 1 Sequential Instruction Processing a U u uu 36 4 1 2 Standard Branch Instruction Processing 2 0010 36 4 1 3 Cache Jump Instruction Processing 1 u eene 36 4 1 4 Particular Pipeline 37 4 2 BIT HANDLING AND BIT PROTECTION seen eene en nnn 40 4 3 INSTRUCTION EXECUTION TIMES 02 8 41 4 4 CPU SPECIAL FUNCTION REGISTERS 2 au asa 41 4 4 1 The System Configuration Register SYSCON 42 4 4 2 The Processor Status Word PSW 43 4 4 3 The Instruction 46 4 4 4 The Code Segment Pointer CSP 11 nenne nennen enne 46 4 4 5 The Data Page Pointers DPPO DPP1 DPP2 DPP3 48 4 4 6 The Context Pointer CP a aaa auqa eed e dde 49 4 4 7
240. errupt request Timer 6 in Counter Mode Counter mode for the core timer T6 is selected by setting Bit field T6M in register T6CON to 001b In counter mode timer T6 is clocked by a transition at the external input pin T6IN which is an alternate function of P5 12 The event causing an increment or decrement of the timer can be a positive a negative or both a positive and a negative transition at this pin Bit field T6l in control register T6CON selects the triggering transition see Table 28 Figure 80 Block diagram of core timer T6 in gated timer mode Control 148 294 Interrupt Request TeoUT P3 1 gt tom gt tom Oi T6OUT Table 28 GPT2 core timer T6 counter mode input edge selection Tel Triggering Edge for Counter Increment Decrement None Counter T6 is disabled 001 Positive transition rising edge on T6IN 010 Negative transition falling edge on T6IN 011 Any transition rising or falling edge on T6IN 1X xX Reserved Do not use this combination The maximum input frequency which is allowed in counter mode is fopy 8 To ensure that transition of the count input signal which is applied to T6IN is correctly recognized its level should be held high or low for at least 4 CPU clock cycles before it changes T5CON FF46h A3h 15 14 13 12 11 10 9 8 ST10X167 GPT2 Auxiliary Timer T5 The auxiliary timer T5 can be configured for tim
241. es and to define the identifier of outgoing messages A received message is stored into the valid message object with a matching identifier and DIR 0 data frame or DIR 1 remote frame Extended frames can be stored only in message objects with XTD 1 standard frames only in message objects with XTD 0 For matching the corresponding global mask has to be considered in case of message object 15 also the Mask of Last Message If a received message data frame or remote frame matches with more than one valid message object it is stored into that with the lowest message number When the CAN controller stores a data frame not only the data Byte but the whole identifier and the data length code are stored into the corresponding message object standard identifiers have Bit ID17 0 filled with 0 This is implemented to keep the data Byte connected with the identifier even if arbitration mask registers are used When the CAN controller stores a remote frame only the data length code is stored into the corresponding message object The identifier and the data Byte remain unchanged There must not be more than one valid message object with a particular identifier at any time If Bit are masked by the Global Mask Registers don t care then the identifiers of the valid message objects must differ in the remaining Bit which are used for acceptance filtering If a received data frame is stored into a
242. ese service request when enabled by the interrupt ist 46 dth enable Bit CCxIE registers are organized the same way as Capture interrupts can be regarded as external all other interrupt control registers The interrupt requests with the additional feature of figure below shows the basic register recording the time at which the triggering event layout and the table lists the associated occurred see also section External Interrupts addresses CCxIC see Table 32 SFR ESF ResetValue 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I I I I T Tdew ew Car T ex RW RW RW RW Note Refer to Interrupt control registers chapter for more details of the control fields 198 294 ky ST10X167 Table 32 CAPCOM unit interrupt control register addresses CAPCOM1 Unit 2 Unit FR ky 199 294 ST10X167 15 PULSE WIDTH MODULATION MODULE The Pulse Width Modulation PWM Module of the ST10X167 generates up to 4 independent PWM signals The minimum PWM signal frequency depends on the width 16 Bit and the resolution CLK 1 or CLK 64 of the PWM timers The maximum PWM signal frequency assumes that the PWM output signal changes with every cycle of the respective timer In a real application the maximum PWM frequency will depend on the required resolution of the PWM output signal see Figure 116 The pulse width modulation module has 4 independent PWM channels Each channel has a 16 Bit up down counter PTx a 16 B
243. ese pins are switched automatically to the appropriate direction Note that the pin drivers for HLDA and BREQ are auto matically enabled while the pin driver for HOLD is automatically disabled see Figure 41 Figure 40 Block diagram of Port6 Pins with an alternate output function X Write ODP6 y Open Drain Latch Read ODP6 y Write DP6 y Direction Latch Read DP6 y r4 Write P6 y Alternate Data Port Output Latch Output Read P6 y E 0 o 2 m v 2 Alternate Enable Function 1 MUX 0 P6 Output Buffer Clock 94 294 Input Latch y 0 4 6 7 ST10X167 Figure 41 Block diagram of Pin P6 5 HOLD WrteoDP6 5 Open Drain Latch Read 0DP6 5 Write DP6 5 Direction Latch Read DP6 5 Internal Bus Write P6 5 Port Output gt Latch Output Buffer Read P6 5 Clock Alternate Data Input 6 9 Port7 If this 8 Bit port is used for general purpose I O the direction of each line can be configured via the corresponding direction register DP7 Each port line can be switched into push pull or open drain mode via the open drain control register ODP7 P7 FFDOh E8h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ky 95 294 ST10X167 DP7 FFD2h E9h SFR 15 14 13 12 11 10 9
244. ess lines is reduced The Table 13 summarizes the alternate functions of Port4 depending on the number of selected segment address lines coded via Bitfield SALSEL Standard Function SALSEL 01 64K Byte General purpose I O General purpose I O General purpose I O General purpose I O General purpose I O General purpose I O General purpose I O General purpose I O Alternate Function SALSEL 11 256K Byte Segment address A16 Segment address A17 General purpose I O General purpose General purpose General purpose General purpose General purpose Alternate Function SALSEL 00 1M Byte Segment address A16 Segment address A17 Segment address A18 Segment address A19 General purpose General purpose General purpose General purpose Alternate Function SALSEL 10 16M Byte Segment address A16 Segment address A17 Segment address A18 Segment address A19 Segment address A20 Segment address A21 Segment address A22 Segment address A23 Figure 35 Port4 I O and alternate functions Alternate Functions P4 7 P4 6 P4 5 P4 4 P4 3 P4 2 4 0 General Purpose Input Output 3 P4 7 CAN_TxD CAN_RxD P4 4 A19 A18 A17 A16 89 294 ST10X167 Figure 36 Block diagram of a Port4 pin Write DP4 y Direction Latch Read DP4 y Alternate Function e Enable Write P4 y Alternate Data Output Internal Bus Port Output L
245. essing modes The GPRs are mirrored to the ESFR area which allows access to the current register bank even after switching register spaces see example below MOV R5 DP3 GPR access via SFR area EXTR 1 MOV R5 ODP3 GPR access via ESFR area Writing Byte to SFRs All special function registers may be accessed Word wise or Bytewise some of them even Bit wise Reading Byte from Word SFRs is a non critical operation However when writing Byte to Word SFRs the complementary Byte of the respective SFR is cleared with the write operation 20 6 Identification Registers The ST10F167 does not have identification registers The ST10C167 and ST10R167 have four Identification registers mapped in ESFR space These registers contain A manufacturer identifier A chip identifier with its revision A internal ROM Flash and size identifier Programming voltage description IDMANUF F07Eh 3Fh ESFR Reset Value 0400h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ee eed R MANUF Manufacturer Identifier 0400h STMicroelectronics manufacturer JTAG worldwide normalization IDCHIP F07Ch 3Eh ESFR Reset Value UUUUh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R IDCHIP Device Identifier Refer to datasheet for values 271 294 3 ST10X167 IDMEM F07Ah 3Dh ESFR Reset Value UUUUh 15 14 11 10 9 8 7 6 5 4 3 2 1 0 13 12 R R MEMSIZE Internal Memory Size Refer to datasheet for values Internal Memory si
246. et during reset according to the level on pin EA or may be altered via software If enabled the internal ROM area occupies the lower 32 KByte of either segment 0 or segment 1 This ROM mapping is controlled by Bit ROMS1 in register SYSCON Note size of the internal ROM area is inde pendent of the size of the actual imple mented ROM Also devices with less than 32 KByte of ROM or with no ROM at all will have this 32 KByte area occupied if the ROM is enabled Devices with larger ROMs provide the mapping option only for the ROM area Devices with a ROM size above 32 KByte expand the ROM area from the middle of segment 1 i e starting at address 01 8000 The internal ROM Flash can be used for both code instructions and data constants tables etc storage Code fetches are always made on even byte addresses The highest possible code storage location in the internal ROM is either xx xxFEy for single word instructions or xx xxFCg for double word instructions The respective location must contain a branch instruction unconditional because sequential boundary crossing from internal ROM to external memory is not supported and causes erroneous results Any word and byte data read accesses may use the indirect or long 16Bit addressing modes There is no short addressing mode for internal ROM operands Any word data access is made to an even byte address The highest possible word data storage location in the in
247. ether the pulse has already started the output is high or not the output is still low This multiple re triggering is always possible while the timer is running after the pulse has started and before the timer is stopped Loading counter PTx directly with the value in the respective PPx shadow register will abort the current PWM pulse upon the next clock pulse counter is cleared and stopped by hardware By setting the period PPx the timer start value PTx and the pulse width value PWx appropriately the pulse width tw and the optional pulse delay td may be varied in a wide range see Figure 121 15 2 PWM Module Registers The PWM module is controlled via two sets of registers The waveforms are selected by the channel specific registers PTx timer PPx period and PWx pulse width Three common registers control the operating modes and the general functions PWMCONO and PWMCON 1 of the PWM module as well as the interrupt behavior PWMIC Up down Counters PTx Each counter PTx of a PWM channel is clocked either directly by the CPU clock or by the CPU clock divided by 64 Bit PTlx in register PWMCONO selects the respective clock source A Table 33 Input Clock and Mode Counter resolution 8 Bit PWM resolution 10 Bit PWM resolution ST10X167 PWM counter counts up or down controlled by hardware while its respective run control Bit PTRx is set A timer is started PTRx 1 via softwa
248. evel Traps are entered regardless of the current CPU priority When either a trap or interrupt routine is entered the state of the machine is preserved on the system stack and a branch to the appropriate trap interrupt vector is made All trap and interrupt routines require the use of the RETI return from interrupt instruction to exit from the called routine This instruction restores the system state from the system stack and then branches back to the location where the trap or interrupt occurred 21 8 Inseparable Instruction Sequences The instructions of the ST10X167 are very efficient most instructions execute in one instruction cycle and even the multiplication and division are interruptible in order to minimize the response latency to interrupt requests internal and external In many microcontroller applications this is vital Some special occasions however require certain code sequences like semaphore handling to be non interruptible to function properly This can be provided by inhibiting interrupts during the respective code sequence by disabling and enabling them before and after the sequence The necessary overhead may be reduced by means of the ATOMIC instruction which allows locking 1 4 instructions to an inseparable code sequence during which the interrupt system standard interrupts and PEC requests and Class A Traps NMI stack overflow underflow are disabled A Class B Trap illegal opcode illegal bus access
249. ever specific status flags which identify the type of error are implemented in the serial channels control registers The ST10X167 provides a vectored interrupt System In this system specific vector locations in the memory space are reserved for the reset trap and interrupt service functions Whenever a request occurs the CPU branches to the location that is associated with the respective interrupt source This allows direct identification of the source that caused the request The only exceptions are the class B hardware traps which all share the same interrupt vector The status flags in the Trap Flag Register TFR can then be used to determine which exception caused the trap For the special software TRAP instruction the vector address is specified by the operand field of the instruction which is a seven bit trap number The reserved vector locations build a jump table in the low end of the ST10X167 s address space segment 0 The jump table is made up of the appropriate jump instructions that transfer control to the interrupt or trap service routines which may be located anywhere within the address space 55 294 ST10X167 The entries of the jump table are located at the lowest addresses in code segment 0 of the address space Each entry occupies 2 Words except for the reset vector and the hardware trap vectors which occupy 4 or 8 Words The Table 6 lists all sources that are capable of requesting interrup
250. f 8 CPU clock cycles The ST10X167 provides 8 interrupt inputs that are sampled every CPU clock cycle so external events are captured faster than with standard interrupt inputs The upper 8 pins of Port2 CC8 15 I O on P2 8 P2 15 can individually be programmed to this fast interrupt mode In this mode the trigger transition rising falling or both can also be selected The External Interrupt Control register EXICON controls this feature for all 8 pins The EXxIN pins can also be used to exit power down mode if bit PWDCFG in the SYSCON register is set Power reduction modes are detailled in Chapter 19 Power Reduction Modes Reset Value 0000h 13 12 9 8 7 6 5 4 3 2 1 0 EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES EXI2ES EXI1ES EXIOES RW RW RW RW RW RW RW RW EXIxES 7 0 External Interrupt x Edge Selection Field x 3 0 0 0 Fast external interrupts disabled standard mode EXxIN pin not taken in account for entering exiting Power Down mode 0 1 Interrupt on positive edge rising Enter Power Down mode if EXilN 0 exit if EXxIN 1 ref as high active level 1 0 Interrupt on negative edge falling Enter Power Down mode if EXilN 1 exit if EXxIN 0 ref as low active level 1 1 Interrupt on any edge rising or falling Always enter Power Down mode exit if EXxIN level changed 70 294 These fast external interrupts use the interrupt nodes and vectors of the CAPCOM chann
251. f the write command WR WRL WRH 1 The CS signal is generated for the duration of the write command Note BUSCONO is initialized with 0000h if pin EA is high during reset If pin EA is low during reset Bit BUSACTO and ALECTLO are set 1 and Bit field BTYP is loaded with the bus configuration selected via PORTO ADDRSEL1 FE18h OCh SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW ADDRSEL2 FE1Ah 0Dh SFR ResetValue 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW 120 294 ky ST10X167 ADDRSELS3 FE1Ch 0Eh SFR ResetValue 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RGSAD RGSZ RW RW ADDRSEL4 FE1Eh 0Fh SFR ResetValue 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Range Size Selection Defines the size of the address area controlled by the respective BUSCONx ADDRSELx register pair See Table 19 RGSAD Range Start Address Defines the upper Bit of the start address A23 of the respective address area See Table 19 Note Register BUSCONO controls the complete specified in register BUSCONO Each ADDRSELx external address space except for the 4 register in a way cuts out an address window windows supported by BUSCON1 to within which the parameters in register BUSCONx BUSCON4 So there is no need of are used to control external accesses ADDRSELO register The range start address of such a window defines 8 4 1 Definition of Address Areas the upper address Bit which are not used
252. for the Word data type or 80h for the Byte data type the E flag is set to 1 otherwise it is cleared MULIP Flag The MULIP flag will be set to 1 by hardware upon the entrance into an interrupt service routine when a multiply or divide ALU operation was interrupted before completion Depending on the state of the MULIP Bit the hardware decides whether a multiplication or division must be continued or not after the end of an interrupt service The MULIP Bit is overwritten with the contents of the stacked MULIP flag when the return from interrupt instruction RETI is executed This normally means that the MULIP flag is cleared again after that Note The MULIP flag is a part of the task environ ment When the interrupting service routine does not return to the interrupted multiply divide instruction for example in case of a task scheduler that switches between inde pendent tasks the MULIP flag must be saved as part of the task environment and must be updated accordingly for the new task before this task is entered CPU Interrupt Status IEN ILVL The Interrupt Enable Bit allows to globally enable IEN 1 or disable IEN 0 interrupts The four Bit Interrupt Level field ILVL specifies the priority of the current CPU activity The interrupt level is updated by hardware upon entry into an interrupt service routine but it can also be modified via software to prevent other interrupts from being acknowledged In case
253. fter the data Byte and checks the CRC code of incoming messages This is done by dividing the data stream by the code generator polynomial Error Management Logic The Error Management Logic is responsible for the fault confinement of the CAN device Its counters the Receive Error Counter and the Transmit Error Counter are incremented and decremented by commands from the Bit Stream Processor According to the values of the error counters the CAN controller is set into the states error active error passive and busoff The CAN controller is error active if both error counters are below the error passive limit of 128 It is error passive if at least one of the error counters equals or exceeds 128 221 294 ST10X167 It goes busoff if the Transmit Error Counter equals or exceeds the busoff limit of 256 The device remains in this state until the busoff recovery sequence is finished Additionally there is the Bit EWRN in the Status Register which is set if at least one of the error counters equals or exceeds the error warning limit of 96 EWRN is reset if both error counters are less than the error warning limit Bit Timing Logic This block BTL monitors the busline input CAN_RxD and handles the busline related Bit timing according to the CAN protocol The BTL synchronizes on a recessive to dominant busline transition at Start of Frame hard synchronization and on any further recessive to dominant busline
254. function as CLKOUT output pin The clock output is a 50 96 duty cycle clock whose frequency equals the CPU operating frequency four fcpu Note The output driver of port pin P3 15 is switched on automatically when the CLK OUT function is enabled The port direc tion Bit is disregarded After reset the clock output function is dis abled CLKEN 907 Segmentation Disable enable Control SGTDIS Bit SGTDIS allows to select either the segmented or non segmented memory mode In non segmented memory mode SGTDIS 1 it is assumed that the code address space is restricted to 64K Byte segment 0 and thus 16 Bit are sufficient to represent all code addresses For implicit stack operations CALL or RET the CSP register is totally ignored and only the IP is saved to and restored from the stack In segmented memory mode SGTDIS 0 it is assumed that the whole address space is available for instructions For implicit stack operations CALL or RET the CSP register and the IP are saved to and restored from the stack After reset the segmented memory mode is selected Note Bit SGTDIS controls if the CSP register is pushed onto the system stack in addition to the IP register before an interrupt ser vice routine is entered and it is repopped when the interrupt service routine is left again System Stack Size STKSZ This Bitfield defines the size of the physical System stack which is located in the internal RAM of the ST1
255. g PWMIR in register PWMIC is set provided that it is enabled via the common interrupt enable Bit PWMIE Note The channel interrupt request flags PIRx in register PWMCONO are not automatically cleared by hardware upon entry into the interrupt service routine so they must be cleared via software The module interrupt request flag PWMIR is cleared by hardware upon entry into the service routine regardless of how many channel interrupts were active However it will be set again if during execution of the service routine a new channel interrupt request is generated Reset Value 00h 5 4 3 2 1 0 9 8 7 6 PWM IE RW RW RW RW Note Refer to the general Interrupt Control Register description for an explanation of the control fields Gr 209 294 ST10X167 15 4 PWM Output Signals The output signals of the four PWM channels POUTS POUTO are alternate output functions on Port7 P7 3 P7 0 The output signal of each PWM channel is individually enabled by control Bit PENx in register PWMCON1 The PWM signals are XORed with the respective port latch outputs before being driven to the port pins This allows driving the PWM signal directly to the port pin P7 x 0 or drive the inverted PWM signal 7 1 see Figure 122 Note Using the open drain mode on Port 7 allows the combination of two or more PWM outputs through a Wired AND configuration using an external pull up device This provides sort of a bu
256. g to change the current DPPs EXAMPLE EXTP R15 41 The override page number is stored in R15 MOV RO R14 The 14 Bit page offset is stored in R14 MOV R1 R13 This instruction uses the standard DPP scheme ky 281 294 ST10X167 The EXTS extend segment instruction allows switching to a 64K Byte segment oriented data access scheme for 1 4 instructions without having to change the current DPPs In this case all 16 Bit of the operand address are used as segment offset with the segment taken from the EXTS instruction This greatly simplifies address calculation with continuous data like huge arrays in EXAMPLE EXTS 15 1 The override seg is 15 OF 0000h 0F FFFFh MOV RO R14 The 16 Bit segment offset is stored in R14 MOV R1 R13 This instruction uses the standard DPP scheme Note Instructions EXTP and EXTS inhibit interrupts the same way as ATOMIC Short Addressing in the Extended SFR ESFR Space The short addressing modes of the ST10X167 REG or BitOFF implicitly access the SFR space The additional ESFR space would have to be accessed via long addressing modes MEM or Rw The EXTR extend register instruction redirects accesses in short addressing modes to the ESFR space for 1 4 instructions so the additional registers can be accessed this way too The EXTPR and EXTSR instructions combine the DPP override mechanism with the redirection to the ESFR space usi
257. ge location in the XRAM is either 00 E7FEh for single Word instructions or 00 E7FCh for double Word instructions The respective location must contain a branch instruction unconditional because sequential boundary crossing from XRAM to external memory is not supported and causes erroneous results Any Word and Byte data read accesses may use the indirect or long 16Bit addressing modes There is no short addressing mode for XRAM operands Any Word data access is made to an even Byte address The highest possible Word data storage location in the XRAM is 00 E7FEh For PEC data transfers the XRAM can be accessed independently of the contents of the DPP registers via the PEC source and destination pointers Note For the ST10C167 ST10R167 the XPEN Bit in the SYSCON register is used to enable or disable the CAN For the ST10F167 the CAN is always enabled As the XRAM appears like external mem ory it cannot be used for the ST10X167 s System stack or register banks The 32 294 XRAM is not provided for single Bit stor age and therefore is not Bit addressable The on chip XRAM is accessed without any waitstates using 16 Bit demultiplexed bus cycles which takes one instruction cycle Even if the XRAM is used as external memory it does not occupy BUSCONx ADDRSELx registers but is selected via additional dedicated XBCON XADHRS registers These registers mask programmed and are not user accessible With these r
258. ge into Buffer 1 MSGLST is set Allocated Released NEWDAT 1 OR NEWDAT 0 AND Store received Message into Buffer 1 Buffer 1 allocated Buffer 2 released CPU access to Buffer 1 Store received Message into Buffer 2 Buffer 1 allocated Buffer 2 allocated CPU access to Buffer 1 CPU releases Buffer 1 Store received message into Buffer 2 MSGLST is set RMTPND 1 RMTPND 0 237 294 ST10X167 Figure 139 CAN controller handling of bus recovery sequence 1 sequence of 11 recessive Bit Bit0 error 1 128 occurence of 238 294 ky Figure 140 CPU handling of bus recovery 17 6 Initialization and Reset The on chip CAN Module is connected to the XBUS Reset signal XRESET This signal is activated when the ST10X167 s reset input is activated when a software reset is executed and in case of a watchdog reset Activating the CAN Module s reset line triggers a hardware reset This hardware reset Sets the CAN_TxD output to 1 recessive Clears the error counters Resets the busoff state Switches the Control Register s low Byte to Oth Leaves the Control Register s high Byte and the Interrupt Register undefined Does not change the other registers including the message objects notified as UUUU Note The first hardware reset after power on leaves the unchanged registers in an undefined state The value 01h in the Control Registe
259. generated by the internal Baud rate generator The shift clock is only active as long as data Bit are transmitted or received Figure 91 Synchronous mode of serial channel ASCO Reload Register SOM 000b Clock Serial Port Control Shift Clock Receive Receive Interrupt Request Transmit Interrupt Request Error Interrupt Request Receive Shift Register Transmit Shift Register Transmit Receive Buffer Register SORBUF Transmit Buffer Register SOTBUF Internal Bus 161 294 ST10X167 Synchronous transmission begins within 4 CPU clock cycles after data has been loaded into SOTBUF provided that SOR is set and SOREN O half duplex no reception Data transmission is double buffered When the transmitter is idle the transmit data loaded into SOTBUF is immediately moved to the transmit shift register thus freeing SOTBUF for the next data to be sent This is indicated by the transmit buffer interrupt request flag SOTBIR being set SOTBUF may now be loaded with the next data while transmission of the previous one is still going on The data Bit are transmitted synchronous with the shift clock After the Bit time for the 8th data Bit both pins TXD0 and RXDO will go high the transmit interrupt request flag SOTIR is set and serial data transmission stops Pin TXDO P3 10 must be configured for alternate data output P3 10 1 and DP3 10 1 in order to provide the shift cl
260. gister a given address references Ordered by register name to find the location of a specific register 20 1 Register Description Format In the following chapters the function and the layout of the SFRs is described in a specific format The example below explains this format A Word register looks like this REG_NAME A16h A8h SFR ESFR XReg Reset Value h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 only only bit RW R RW RW RW RW bit field name Explanation of bit field name Description of the functions controlled by this bit field A Byte register looks like this REG_NAME A16h A8h SFR ESFR XReg Reset Value h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Oe TemImem RW RW RW RW Elements REG_NAME Name of this register A16h A8h Long 16 bit address Short 8 bit address SFR ESFR XReg Register space SFR ESFR or External XBUS Register fter Register contents after reset 0 1 defined X undefined undefined X after power up U unchanged hwbit bit that are set cleared by hardware are written in bold 20 2 General Purpose Registers GPRs The GPRs form the register bank that the CPU works with This register bank may be located anywhere within the internal RAM via the Context Pointer CP Due to the addressing mechanism GPR banks can only reside within the internal RAM All GPRs are bit addressable ky 257 294 ST10X167 Table 41 General purpose registers GPRs
261. gram execution and branches to an interrupt service routine in order to service an interrupt requesting device The current program status IP PSW in segmentation mode also CSP is saved on the internal system stack A prioritization scheme with 16 priority levels allows the user to specify the order in which multiple interrupt requests are to be handled Interrupt processing via the peripheral event controller PEC A faster alternative to normal software controlled interrupt processing is servicing an interrupt requesting device with the ST10X167 s integrated Peripheral Event Controller PEC Triggered by an interrupt request the PEC performs a single Word or Byte data transfer between any two locations in segment 0 data pages 0 through 3 through one of eight programmable PEC Service Channels During a PEC transfer the normal program execution of the CPU is halted for just 1 instruction cycle No internal program status information needs to be saved The same prioritization scheme is used for PEC service as for normal interrupt processing PEC transfers share the 2 highest priority levels Trap functions Trap functions are activated in response to special conditions that occur during the execution of instructions A trap can also be caused externally by the Non Maskable Interrupt pin NMI Several hardware trap functions are provided for handling erroneous conditions and exceptions that arise during the execution of an in
262. h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 aa RW RW RW RW CRIC FF6Ah B5h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ee o RW RW RW RW Note Please refer to Interrupt Control Registers for explanation of the control fields 3 154 294 ST10X167 10 ASYNCHRONOUS SYNCHRONOUS SERIAL INTERFACE The Asynchronous Synchronous Serial Interface ASCO provides serial communication between the ST10X167 and other microcontrollers micropro cessors or external peripherals In synchronous mode data are transmitted or received synchronously to a shift clock which is generated by the ST10X167 In asynchronous mode 8 or 9Bit data transfer parity generation and the number of stop Bit can be selected Parity framing and overrun error detection is provided to increase the reliability of data transfers Transmission and reception of data is double buffered For multiprocessor communication a mechanism to distinguish address from data Byte is included Testing is supported by a loop back option A 13 Bit Baud rate generator provides the ASCO with a separate serial clock signal 155 294 ST10X167 Figure 87 SFRs and port pins associated with ASC0 Ports amp Direction Control Alternate Functions Data Registers 1514131211109876543210 1514131211109876543210 SOBG sce oum SS Y YS Y UY YY Y Y OY YY SOTBUF Y Y Y Y Y Y YY Y Y Y Y Y Y Y Y SORBUF Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Control Regis
263. h CAPCOM Register 8 Interrupt Control Register 0000h CC9 FE92h CAPCOM Register 9 0000h CC9IG b FF8Ah CAPCOM Register 9 Interrupt Control Register 0000h CC10 FE94h CAPCOM Register 10 0000h CC10IC b FF8Ch CAPCOM Register 10 Interrupt Control Register 0000h CC11 FE96h CAPCOM Register 11 0000h m ITI m m m 71 rm j co m 2 NONO jx T una 2 2 CIL QD _ 77 pon ae M E m NC META gt b FF92h CC14IC b m gt m ITI co y m N CAPCOM Register 13 Interrupt Control Register 0000h m Q CAPCOM Register 14 0000h CC15 FE9Eh CAPCOM Register 14 Interrupt Control Register 0000h CAPCOM Register 15 0000h 8h 4h 9h 5h Ah 6h Bh 7h 4Ch 8h 4Dh 9h Eh CAh Fh 18 2 b 2h 3h 3h 4h 4h 5h 5h 6h 6h 7h 7h 8h 8h 9h 9h Ah CC18IC F164h E CC19 FE66h CAPCOM Register 18 Interrupt Control Register 0000h CAPCOM Register 19 0000h 1 b F166h E Register 19 Interrupt Control Register 0000h CC20 FE68h Register 20 0000h CC20lC b F168h E CAPCOM Register 20 Interrupt Control Register 0000h 21 FE6Ah 5 Register 21 0000h CC21IC F16Ah E CAPCOM Register 21 Interrupt Control Register 0000h
264. h bank pointer is then assigned Thus upon entry into a new task the appropriate bank pointer is used as the operand for the SCXT switch context instruction Upon exit from a task a simple POP instruction to the context pointer CP restores the previous task s register bank 21 3 Procedure Call Entry and Exit To support modular programming a procedure mechanism is provided to allow coding of frequently used portions of code into subroutines The CALL and RET instructions store and restore the value of the instruction pointer IP on the System stack before and after a subroutine is executed 278 294 Procedures may be called conditionally with instructions or CALLI or be called unconditionally using instructions or CALLS Note Any data pushed onto the system stack dur ing execution of the subroutine must be popped before the RET instruction is exe cuted Passing Parameters on the System Stack Parameters may be passed via the system stack through PUSH instructions before the subroutine is called and POP instructions during execution of the subroutine Base plus offset indirect addressing also permits access to parameters without popping these parameters from the stack during execution of the subroutine Indirect addressing provides a mechanism of accessing data referenced by data pointers which are passed to the subroutine In addition two instructions have been implemented to allow one parameter to
265. h of 8 Byte The Bit timing is derived from the XCLK and is programmable up to a data rate of 1M Baud at 25 MHz CPU clock The CAN Module uses two pins of Port 4 to interface to a bus transceiver 17 1 The CAN Controller The CAN module combines several functional blocks that work in parallel These units and the functions they provide are described below 220 294 Each of the message objects has a unique identifier and its own set of control and status Bit Each object can be configured for transmit or receive direction except the last message which is a double receive buffer with a special mask register An object with its direction set as transmit can be configured to be automatically sent whenever a remote frame with a matching identifier taking into account the respective global mask register is received over the CAN bus By requesting the transmission of a message with the direction set as receive a remote frame can be sent to request that the appropriate object be sent by some other node Each object has separate transmit and receive interrupts and status Bit giving the CPU full flexibility in detecting when a remote data frame has been sent or received Two acceptance filtering masks be programmed for general purpose one for identifiers of 11 Bit and one for identifiers of 29 Bit However the CPU must configure Bit XTD Normal or Extended Frame Identifier for each valid message to determine whether
266. he address After a period of time during which the address must have been latched externally the address is removed from the bus The EBC now activates the respective command signal RD WR WRL WRH Data is driven onto the bus either by the EBC for write cycles or by the external memory peripheral for read cycles After a period of time which is determined by the access time of the memory peripheral data become valid Read cycles Input data is latched and the command signal is now deactivated This causes the accessed device to remove its data from the bus which is then tri stated again Write cycles The command signal is now deactivated The data remain valid on the bus until the next external bus cycle is started Figure 49 Multiplexed bus cycle ST10X167 Bus Cycle 8 2 2 Demultiplexed Bus Modes In the demultiplexed bus modes the 16 Bit intra segment address is permanently output on PORT1 while the data uses PORTO 16 Bit data or POL 8 Bit data The upper address lines are permanently output on Port4 if selected via SALSEL during reset No address latches are required The EBC initiates an external access by placing an address on the address bus After a programmable period of time the EBC activates the respective command signal RD WR WRL WRH Data is driven onto the data bus either by the EBC for write cycles or by the external memory peripheral for read cycles After a peri
267. he corresponding Error Enable Bit is set also an error interrupt request will be generated by setting SSCEIR see figure below The error interrupt handler may then check the error flags to determine the cause of the error interrupt The error flags are not reset automatically like SSCEIR but rather must be cleared by software after servicing This allows servicing of some error conditions via interrupt while the others may be polled by software Note error interrupt handler must clear the associated enabled error flag s to prevent repeated interrupt requests A Receive Error Master or Slave mode is detected when a new data frame is completely received but the previous data was not read out of the receive buffer register SSCRB This condition sets the error flag SSCRE and when enabled via SSCREN the error interrupt request flag SSCEIR The old data in the receive buffer SSCRB will be overwritten with the new value and is irretrievably lost A Phase Error Master or Slave mode is detected when the incoming data at pin MRST master mode or MTSR slave mode sampled with the same frequency as the CPU clock changes between one sample before and two samples after the latching edge of the clock signal see Clock Control This condition sets the error flag SSCPE and when enabled via SSCPEN the error interrupt request flag SSCEIR A Baud Rate Error Slave mode is detected when the incoming clock signal deviates
268. he count input in counter mode The count direction Up Down can be programmed by software or can be dynamically altered by a signal at an external control input pin Each overflow underflow of core timer T3 can be indicated on an alternate output function pin The auxiliary timers T2 and T4 can additionally be concatenated with the core timer or used as capture or reload registers for the core timer In incremental interface mode the GPT1 timers T2 T3 T4 can be directly connected to the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD Direction and count signals are internally derived from these two input signals so the contents of the respective timer Tx corresponds to the sensor position The third position sensor signal TOPO can be connected to an interrupt input The current contents of each timer can be read or modified by the CPU by accessing the corresponding timer registers T2 T3 or T4 located in the non Bitaddressable SFR space When any of the timer registers is written to by the CPU in the state immediately before a timer increment decrement reload or capture the CPU write operation has priority This is to guarantee correct results ST10X167 Figure 63 SFRs and port pins associated with timer block GPT1 3 Ports amp Direction Control Alternate Functions Data Registers 15 14 13 12111098765 43210 15 14 13 1211109 876543210 cw MY Y Yo Y T2 Y
269. he location where the execution of the interrupted task is to be resumed after returning from the service routine This return location is specified through the Instruction Pointer IP and in case of a segmented memory model the Code Segment Pointer CSP Bit SGTDIS in register SYSCON control how the return location is stored The system stack receives the PSW first followed by the IP unsegmented or followed by CSP and then IP segmented mode This optimizes the usage of the system stack if segmentation is disabled The CPU priority field ILVL in PSW is updated with the priority of the interrupt request that is to be serviced so the CPU now executes on the new level If a multiplication or division was in progress at the time the interrupt request was acknowledged bit MULIP in register PSW is set to 1 In this case the return location that is saved on the stack is not the next instruction in the instruction flow but rather the multiply or divide instruction itself as this instruction has been interrupted and will be completed after returning from the service routine Status of Interrupted b System stack after Interrupt Entry segmented 65 294 ST10X167 The interrupt request flag of the source that is being serviced is cleared The IP is loaded with the vector associated with the requesting source the CSP is cleared in case of segmentation and the first instruction of the service routine is fetched f
270. he two CAPCOM units support generation and control of timing sequences on up to 32 channels The CAPCOM units are typically used to handle high speed I O tasks such as pulse and waveform generation pulse width modulation PMW Digital to Analog D A conversion software timing or time recording relative to external events Four 16 Bit timers TO T1 T7 T8 with reload registers provide two independent time bases for the capture compare register array The input clock for the timers is programmable to several pre scaled values of the internal system clock or may be derived from an overflow underflow of timer T6 in module GPT2 This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements In addition external count inputs for CAPCOM timers TO and 7 allow event scheduling for the capture compare registers relative to external events 23 294 ST10X167 Both of the two capture compare register arrays contain 16 dual purpose capture compare registers each of which be individually allocated to either CAPCOM timer or T1 T7 or T8 respectively and programmed for capture or compare function Each register has one port pin associated with it which is an input pin for triggering the capture function or is output pin except for CC24 CC27 to indicate the occurrence of a compare event When a capture compare register has b
271. he underflow register whenever the SP is INCREMENTED either by a RET POP or ADD instruction An underflow trap will be entered when the SP value is greater than the value in the stack underflow register Note When a value is MOVED into the stack pointer NO check against the overflow underflow registers is performed In many cases the user will place a software reset instruction SRST into the stack underflow and overflow trap service routines This is an easy approach which does not require special programming However this approach assumes that the defined internal stack is sufficient for the current software and that exceeding its upper or lower boundary represents a fatal error It is also possible to use the stack underflow and stack overflow traps to cache portions of a larger external stack Only the portion of the system stack currently being used is placed into the internal memory thus allowing a greater portion of the internal RAM to be used for program data or register banking This approach assumes no error but requires a set of control routines see below Circular Virtual Stack This basic technique allows pushing until the overflow boundary of the internal stack is reached At this point a portion of the stacked data must be saved into external memory to create space for further stack pushes 275 294 ST10X167 This is called stack flushing When executing a number of return or pop instructions
272. herwise program execution continues During ky power down the voltage at the Vpp pins can be lowered to 2 5 V while preserving the contents of the internal RAM Exiting power down mode can only be achieved by external hardware reset The initialization routine executed upon reset checks the identification flag or Bit pattern within the RAM to determine whether the controller was initially switched on or whether it was properly restarted from power down mode 19 3 Interruptible Power Down Mode This mode is selected by setting the Bit PWDCFG in register SYSCON to 1 This mode is not available for ST10F167 Entering power down mode can only be achieved if enabled Fast External Interrupt pins 0 to 3 EXxIN pins alternate functions of Port2 pins with x 7 0 are in their inactive level This inactive level is configured with the EXIxES Bit field in the EXICON register as follows 253 294 ST10X167 EXICON F1C0h E0h 15 14 11 10 ESFR ResetValue 0000h 13 12 9 8 7 6 5 4 3 2 1 0 EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES EXI2ES EXI1ES EXIOES RW RW RW RW RW RW RW RW External Interrupt x Edge Selection Field x 7 0 0 0 Fast external interrupts disabled standard mode EXxIN pin not taken in account for entering exiting Power Down mode 0 1 Interrupt on positive edge rising Enter Power Down mode if EXiIN 0 exit if EXxIN 1 ref as high active level 1 0 Interrupt on negati
273. his time The duration of the calibration sequence is then extended by the time consumed by the conversions Note After a power on reset the total unadjusted error TUE of the ADC might be worse than 2 LSB max 4 LSB During the full calibration sequence the TUE is constantly improved until at the end of the calibration TUE is within the specified limits of 2 LSB One calibration cycle is performed after each conversion Each calibration cycle takes 4 ADC clock cycles These operation cycles ensure constant updating of the ADC s accuracy compensating for changing operating conditions A complete conversion cycle takes 16 ADC clock cycles 2 ADC clocks sample phase 10 ADC clocks conversion phase 4 ADC clocks calibration phase 16 4 A D Converter Interrupt Control At the end of each conversion interrupt request flag ADCIR in interrupt control register ADCIC is set This end of conversion interrupt request may cause an interrupt to vector ADCINT or it may trigger a PEC data transfer which reads the conversion result from register ADDAT it can be stored it into a table in the internal RAM for later evaluation ky ST10X167 The interrupt request flag ADEIR in register ADEIC will be set either if a conversion result overwrites a previous value in register ADDAT error interrupt in standard mode or if the result of an injected conversion has been stored into ADDAT2 end of injected conversion interrupt This interrup
274. host 3 Identification Byte sent by ST10X167 5 Caution TxDO is only driven a certain time after reception of the zero Byte 4 32 Byte of code data sent by host 6 Internal Boot ROM 179 294 ST10X167 When the ST10X167 has entered BSL mode the following configuration is automatically set values that deviate from the normal reset values are marked Watchdog Timer Disabled Context Pointer CP FA00h Stack Pointer SP FA40h Register SOCON 8011h Register S0BG acc to 00 Byte In this case the watchdog timer is disabled so the bootstrap loading sequence is not time limited Pin TXDO is configured as output so the ST10X167 can return the identification Byte Even if the internal Flash is enabled no code can be executed out of it The hardware that activates the BSL during reset may be a simple pull down resistor on POL 4 for Systems that use this feature upon every hardware reset A switchable solution via jumper or an external signal can be used for systems that only temporarily use the bootstrap loader see Figure 102 After sending the identification Byte the ASCO receiver is enabled and is ready to receive the initial 32 Byte from the host A half duplex connection is therefore sufficient to feed the BSL Figure 102 Hardware provisions to activate the BSL Rpoia 8kQ max tet 77 Circuit 1 180 294 Register SYSCON OE00h Register STKUN
275. ied vector location When segmentation is enabled and a trap is executed the CSP for the trap service routine is set to code segment 0 No Interrupt Request flags are affected by the TRAP instruction The interrupt service routine called by a TRAP instruction must be terminated with a RETI return from interrupt instruction to ensure correct operation Note The CPU level in register PSW is not modi fied by the TRAP instruction so the service routine is executed on the same priority level from which it was invoked Therefore the service routine entered by the TRAP instruction can be interrupted by other traps or higher priority interrupts other than when triggered by a hardware trap ST10X167 5 7 2 Hardware Traps Hardware traps are issued by faults or specific System states that occur during the runtime of a program not identified at assembly time hardware trap may also be triggered intentionally for example to emulate additional instructions by generating an Illegal Opcode trap The ST10X167 distinguishes eight different hardware trap functions When a hardware trap condition has been detected the CPU branches to the trap vector location for the respective trap condition Depending on the trap condition the instruction which caused the trap is either completed or cancelled it has no effect on the system state before the trap handling routine is entered Hardware traps are non maskable and always have prio
276. ifi cant Bit of DPPx are used when segmentation is disabled Data paging is performed by concatenating the lower 14 Bit of an indirect or direct long 16 Bit address with the contents of the DDP register selected by the upper two Bit of the 16 Bit address The content of the selected DPP register specifies one of the 1024 possible data pages This data page base address together with the 14 Bit page offset forms the physical 24 20 18 Bit address In case of non segmented memory mode only the two least significant Bit of the implicitly selected DPP register are used to generate the physical address Thus extreme care should be taken when changing the content of a DPP register if a non segmented memory model is selected because otherwise unexpected results could occur In case of the segmented memory mode the selected number of segment address Bit 9 2 5 2 or 3 2 of the respective DPP register is output on the segment address pins A23 A19 A17 A16 of Port4 for all external data accesses A DPP register can be updated via any instruction which is capable of modifying an SFR Due to the internal instruction pipeline a new DPP value is not yet usable for the operand address calculation of the instruction immediately following the instruction updating the DPP register 48 294 ST10X167 Figure 15 Addressing via the data page pointers Data Pages 16 Bit Data Address 15 14 13 DPP Registers DPP3 11 DPP1 01 DPPO0 00 9
277. ific conditions Support for both signed and unsigned arithmetic is provided through user specifiable branch tests These flags are also preserved automatically by the CPU upon entry into an interrupt or trap routine All targets for branch calculations are also computed in the central ALU A 16 Bit barrel shifter provides multiple Bit shifts in a single instruction cycle Rotate and arithmetic shifts are also supported 2 2 1 Extended Bit Processing and Peripheral Control A large number of instructions are dedicated to Bit processing These instructions provide efficient control and testing of peripherals and they enhance data manipulation Unlike other microcontrollers these instructions provide direct access to two operands in the Bit addressable ky ST10X167 space without the need to move them into temporary flags The same logical instructions available for Words and Byte are also supported for Bit This allows the user to compare and modify a control Bit for a peripheral in one instruction Multiple Bit shift instructions have been included to avoid long instruction streams of single Bit shift operations These are also performed in a single instruction cycle In addition Bit field instructions have been provided to allow the modification of multiple Bit from one operand in a single instruction 2 2 2 High Performance Branch Call and Loop Processing Due to the high percentage of branching in controller
278. iguration of POL 5 POL 0 and sets Bit BSL inactive 18 1 5 Watchdog Timer Reset When the watchdog timer is not disabled during the initialization or serviced regularly during pro gram execution it will overflow and trigger the reset sequence Other than hardware and soft ware reset the watchdog reset completes a run ning external bus cycle if this bus cycle either does not use READY at all or if READY is sam pled active low after the programmed waitstates When READY is sampled inactive high after the programmed waitstates the running external bus cycle is aborted Then the internal reset sequence is started Note A watchdog reset disregards the configura tion of POL 5 POL 0 and sets Bit BSL inac tive The watchdog reset cannot occur while the ST10X167 is in bootstrap loader mode 18 1 6 Bi Directional Reset Note This feature does not exist for the ST10F167 device Bi directional reset converts SW or WDT resets to hardware reset Circuit behaviour is the same as for hardware reset reset sequence system start up configuration from POH and POL Reset sequence is visible at the RSTIN pin Bi directional reset is disabled during and after hardware reset and is enabled by setting BDRSTEN Bit 3 of the SYSCON register In bi directional reset mode the RSTIN pin is pulled low for the duration of the internal reset sequence Bidirectional reset activates the RSTIN pin for the duration of
279. igure 136 CPU handling of the last message object Power Up Initialisation Process Start Process Process End all Bit undefined RXIE application specific 0 reset INTPND 0 1 set RMTPND 0 MSGLST 0 Identifier application specific NEWDAT 0 Direction receive DLC value of DLC in transmitter MSGVAL 1 XTD application specific process message contents NEWDAT 0 Restart Process 235 294 ST10X167 Figure 137 CPU handling of message objects in receive direction Power Up all Bit undefined TXIE application specific RXIE application specific INTPND 0 RMTPND 0 TXRQ 0 MSGLST 0 Identifier application specific NEWDAT 0 Direction receive DLC value of DLC in transmitter MSGVAL 1 XTD application specific Initialisation NEWDAT 0 Process Start process message contents Process Process End Restart Process request update 236 294 ST10X167 Figure 138 Handling of the last message object s alternating buffer CPU releases Buffer 2 CPU releases Buffer 1 Buffer 1 released Buffer 2 released CPU access to Buffer 2 CPU allocates Buffer 2 Buffer 1 released Buffer 2 allocated CPU access to Buffer 2 Store received Message into Buffer 1 Buffer 1 allocated Buffer 2 allocated CPU access to Buffer 2 CPU releases Buffer 2 Store received messa
280. ill be acknowledged disclosing all other requests The priority level of the source that wins the arbitration is compared against the CPU s 64 294 current level and only this source is serviced If its level is higher than the current CPU level Changing the CPU level to a specific value via software blocks all requests on the same or a lower level An interrupt source that is assigned to level 0 will be disabled and never be serviced The ATOMIC and EXTend instructions automatically disable all interrupt requests for the duration of the following 1 4 instructions This is useful for semaphore handling and does not require to re enable the interrupt system after the inseparable instruction sequence see Chapter 21 System Programming 5 3 2 Interrupt Class Management An interrupt class covers a set of interrupt sources with the same priority from the system s viewpoint Interrupts of the same class must not interrupt each other The ST10X167 supports this function with two features Classes with up to 4 members can be established by using the same interrupt priority ILVL and assigning a dedicated group level GLVL to each member This functionality is built in and handled automatically by the interrupt controller Classes with more than 4 members can be established by using a number of adjacent interrupt priorities ILVL and the respective group levels 4 per ILVL Each interrupt service routine within this cla
281. ill be set when the receive buffer register has not been read by the time reception of a second character is complete The previously received character in the receive buffer is overwritten The Loop Back option selected by Bit SOLB allows the data currently being transmitted to be received simultaneously in the receive buffer This may be used to test serial communication routines at an early stage without having to provide an external network In loop back mode the alternate input output functions of the Port3 pins are not necessary Note Serial data transmission or reception is only possible when the Baud rate Gen erator Run Bit SOR is set to 1 Other wise the serial interface is idle Do not program the mode control field SOM in register SOCON to one of the reserved combinations to avoid unpre dictable behavior of the serial interface 10 1 Asynchronous Operation Asynchronous mode supports full duplex commu nication where both transmitter and receiver use the same data frame format and the same Baud rate Data is transmitted on pin TXDO P3 10 and received on pin RXDO P3 11 These signals are alternate functions of Port 3 pins Figure 88 Reload Register ST10X167 Asynchronous mode of serial channel ASCO SOM SOSTP Serial Port Control 5 SOPE SOOE Receive Interrupt Request Clock gt Transmit Interrupt Request Error Interrupt Request Shift Clock Tra
282. ime may be extended by 1 CPU clock cycle for each of these conditions When instruction N reads an operand from the internal ROM or when N is a CALL RETURN TRAP or MOV Rn Rm data16 instruction 68 294 the minimum PEC response time may additionally be extended by 2 CPU clock cycles during internal ROM program execution n case instruction N reads the PSW and instruction N 1 has an effect on the condition flags the PEC response time may additionally be extended by 2 CPU clock cycles The worst case PEC response time during internal ROM program execution adds to 9 CPU clock cycles Any reference to external locations increases the PEC response time due to pipeline related access priorities The following conditions have to be considered Instruction fetch from an external location Operand read from an external location Result write back to an external location Depending on where the instructions source and destination operands are located there are a number of combinations Note however that only access conflicts contribute to the delay A few examples illustrate these delays The worst case interrupt response time including external accesses will occur when instructions N and N 1 are executed out of external memory instructions N 1 and N require external operand read accesses and instructions N 3 N 2 and N 1 write back external operands In this case the PEC response time is the time
283. input clock of a timer is derived from the internal CPU clock divided by a programmable pre scaler The different options of the pre scaler of each timer are selected separately by the Bit fields Txl The input frequencies fr for Tx are determined as a function of the CPU clock as follows where represents the contents of the Bit field Txl 3 When timer overflows from FFFFh to 0000h it is reloaded with the value stored in its respective reload register TxREL The reload value determines the period between two consecutive overflows of Tx as follows rx 216 TxREL x 2179931 i fopu 187 294 ST10X167 The timer resolutions against pre scaler option in are listed in the table below Pre scaler for CPU Timer Input Selection RE SE 128 512 1024 Resolution EH E EIE CPU clock cycles Refer to the device datasheet for a table of timer input frequencies resolution and periods for each pre scaler option in Txl After a timer has been started by setting its run flag TxR to 1 the first increment will occur within the time interval which is defined by the selected timer resolution All further increments occur exactly after the time defined by the timer resolution When both timers of a CAPCOM unit are to be incremented or reloaded at the same time TO is always serviced one CPU clock before T1 T7 befor
284. input or output function of a pin only an alternate output function however have different structures due to the way the direction of This is done by setting or clearing the direction the pin is switched and depending on whether the control Bit DPx y of the pin before enabling the in is accessible by the user software or not in the alternate function alternate function mode There are port lines however where the direction usss All port lines that are not used for these alternate of the port line is switched automatically functions may be used as general purpose lines When using port pins for general purpose output the initial output value should be written to the port latch prior to enabling the output drivers in order to avoid undesired transitions on the out put pins This applies to single pins as well as to For instance in the multiplexed external bus modes of PORTO the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data Obviously this cannot be done through instruc pin groups see examples below tions In these cases the direction of the port line is switched automatically by hardware if the alter Note When using several BSET pairs to control nate function of such a pin is enabled more pins of one port these pairs must be separated by instructions which do not To determine the appropriate level of the port out referenc
285. interfaces are enabled the master device can initiate the first data transfer by writing the transmit data into register SSCTB This value is copied into the shift register which is assumed to be empty at this time and the selected first Bit of the transmit data will be placed onto the MTSR line on the next clock from the Baud rate generator transmission only starts if SSCEN 1 Depending on the selected clock phase also a clock pulse will be generated on the SCLK line With the opposite clock edge the master at the same time latches and shifts in the data detected at its input line MRST This exchanges the transmit data with the receive data Since the clock line is connected to all slaves their shift registers will be shifted synchronously with the master s shift register shifting out the data contained in the registers and shifting in the data detected at the input line After the pre programmed number of clock pulses via the data width selection the data transmitted by the master is contained in all slaves shift registers while the master s shift register holds the data of the selected slave In the master and all slaves the content of the shift register is copied into the receive buffer SSCRB and the receive interrupt flag SSCRIR is set A slave device will immediately output the selected first Bit MSB or LSB of the transfer data at pin MRST when the content of the transmit buffer is copied into the slave s shift r
286. ion via EXOR 24 294 2 5 11 A D Converter A 10 Bit A D converter with 16 multiplexed input channels and a sample and hold circuit has been integrated on chip for analog signal measure ment It uses a successive approximation method The sample time for loading the capacitors and conversion time is programmable and can be modified for the external circuitry Overrun error detection protection is provided for the conversion result register ADDAT When the result of a previous conversion has not been read from the result register at the time the next conversion is complete either an interrupt request is generated or the next conversion is suspended until the previous result has been read For applications which require less than 16 analog input channels the remaining channel inputs can be used as digital input port pins The A D converter of the ST10X167 supports four different conversion modes Standard Single Channel conversion mode the analog level on a specified channel is sampled once and converted to a digital result Single Channel Continuous mode the analog level on a specified channel is repeatedly sampled and converted without software intervention For the Auto Scan mode the analog levels on a pre specified number of channels sequentially sampled and converted Inthe Auto Scan Continuous mode the number of pre specified channels is repeatedly sampled and converted I
287. ions below The SP register can be updated via any instruction which is capable of modifying an SFR Note Due to the internal instruction pipeline a POP or RETURN instruction must not immediately follow an instruction updating the SP register SP FE12h 09h SFR ResetValue FC00h 11 10 9 8 7 6 5 4 3 2 1 0 14 RE ee c z wasa Modifiable portion of register SP Specifies the top of the internal system stack 4 4 8 The Stack Overflow Pointer STKOV This non Bit addressable register is compared against the SP register after each operation which pushes data onto the system stack PUSH and CALL instructions or interrupts and after each subtraction from the SP register If the content of the SP register is less than the content of the STKOV register a stack overflow hardware trap will occur Since the least significant Bit of register STKOV is tied to 0 and Bit 15 through 12 are tied to 1 by hardware the STKOV register can only contain values from F000h to FFFEh STKOV FE14h 0Ah SFR ResetValue FA00h 11 10 9 8 7 6 5 4 3 2 1 0 14 j s qun STKOV Modifiable portion of register STKOV Specifies the lower limit of the internal system stack The Stack Overflow Trap entered when SP lt STKOV may be used in two different ways Fatal error indication treats the stack overflow as a system error through the associated trap service routine Under these circumstances data in the bottom of the stack may have been
288. ions of Portl8 a enne 100 7 DEDICATED PINS lu uu uuu us never Siecle ens 102 8 THE EXTERNAL BUS INTERFACE 104 8 1 SINGLE GHIP MODE uuu ticles Su eye 104 8 2 EXTERNAL BUS MODES 106 8 2 1 Multiplexed Bus Modes te re Ge n Fa E Re 106 8 2 2 Demultiplexed Bus Modes nnne 107 8 2 3 Switching Between the Bus Modes 1 eene 108 8 2 4 External Data Bus Width nennen nennen nennen 109 8 2 5 Disable Enable Control for Pin BYTDIS 110 8 2 6 Segment Address Generation nnne nnne 110 ky 5 294 ST10X167 8 2 7 CS Signal Generation 0 2 000040 iq wau wa nnne enin 110 8 2 8 Segment Address Versus Chip 111 8 3 PROGRAMMABLE BUS CHARACTERISTICS 111 8 3 1 ALE Length Control 112 8 3 2 Programmable Memory Cycle Time 113 8 3 3 Programmable Memory Tri State Time 113 8 3 4 Read Write Signal Delay 114 8 3 5 READY Polarity cosine osia eere tree ene enne deer
289. is emptied the bottom of stack is reloaded from the external memory and the internal pointers are adjusted accordingly Linear Stack The ST10X167 also offers a linear stack option STKSZ 111b where the system stack may use the complete internal RAM area This provides a large system stack without requiring procedures to handle data transfers for a circular stack However this method also leaves less RAM space for variables or code The RAM area that may effectively be consumed by the system stack is defined via the STKUN and STKOV pointers The underflow and overflow traps in this case serve for fatal error detection only For the linear stack option all modifiable Bit of register SP are used to access the physical stack Although the stack pointer may cover addresses from 00 F000h up to 00 FFFEh the physical system stack must be located within the internal RAM and therefore may only use the address range 00 F600h to 00 FDFER It is the user s responsibility to restrict the system stack to the internal RAM range Note Avoid stack accesses below the IRAM area ESFR space and reserved area and within address range OO FEOOh and SFR space Otherwise unpredictable results will occur 277 294 ST10X167 User Stacks User stacks provide the ability to create task specific data stacks and to off load data from the system stack The user may push both Byte and Words onto a user stack but is responsible for usi
290. is possible that a previous routine s Multiply or Divide instruction was interrupted while in progress In this case the information about how to restart the instruction is contained in this register Register MDC must be cleared to be correctly initialized for a subsequent multiplication or division The old MDC contents must be popped from the stack before the RETI instruction is executed For a division the user must first move the dividend into the MD register If a 16 16Bit division is specified only the low portion of register MD must be loaded The result is also stored into register MD The low portion MDL contains the integer result of the division while the high portion MDH contains the remainder The following instruction sequence performs a 32 by 16Bit division MOV MDH R1 Move dividend to MD register Sets MDRIU MOV MDL R2 Move low portion to MD DIV R3 Divide 32 16 signed R3 holds the divisor JMPR cc V ERROR Test for divide overflow MOV R3 MDH Move remainder to R3 MOV R4 MDL Move integer result to R4 Clears MDRIU 274 294 Whenever a multiply or divide instruction is interrupted while in progress the address of the interrupted instruction is pushed onto the stack and the MULIP flag in the PSW of the interrupting routine is set When the interrupt routine is exited with the RETI instruction this Bit is implicitly tested before the old PSW is popped from the stack If
291. it which also sets Bit ADCRQ Triggering a channel injection at a specific time on the occurrence of a predefined count value of the CAPCOM timers or on a capture event of register CC31 This can be either the positive negative or both the positive and the negative edge of an external signal In addition this Figure 127 Channel injection example Conversion Y Y Y Write ADDAT x 1 fix 77 PEE uM Read ADDAT option allows recording the time of occurrence of this signal Note The channel injection request Bit ADCRQ will be set on any interrupt request of CAPCOM2 channel CC31 regardless whether the channel injec tion mode is enabled or not It is recom mended to always clear Bit ADCRQ before enabling the channel injection mode While an injected conversion is in progress no further channel injection request can be triggered The Channel Injection Request flag ADCRQ remains set until the result of the injected conver sion is written to the ADDAT2 register If the converter was idle before the channel injection and during the injected conversion the converter is started by software for normal conver sions the channel injection is aborted and the converter starts in the selected mode as described above This can be avoided by checking the busy Bit ADBSY before starting a new operation After the completion of the current conversion if any is in progress the converter will start inject
292. it period register PPx with a shadow latch a 16 Bit pulse width register PWx with a shadow latch two comparators and the necessary control logic The operation of all four channels is controlled by two common control registers PWMCONO and PWMCON1 and the interrupt control and status is handled by one interrupt control register PWMIC which is also common for all channels see Figure 117 200 294 ST10X167 Figure 116 SFRs and port pins associated with the PWM module Ports amp Direction Control Alternate Functions Data Registers 15141312111098 76543210 1514131211109876543210 Control Registers Interrupt Control 1514131211109876543210 15141312111098 76543210 PTOEJ Y Y Y Y Y YYYYYYYYYYY PWMCONO Y YY Y Y YYYYYYYYYY Y PWMCON1 Y Y Y Y Y YYYYYYYYYYY PTIEIY Y Y Y Y Y YYYYYYYYYY 2 Y Y Y Y YYYYYYYYY YY PWMICE c oc o Y Y Y Y Y Y Y Y PISEJY Y Y Y Y YYYYYYYYYYY POUTO P7 0 POUT1 P7 1 POUT2 P7 2 POUT3 P7 3 ODP7 Port7 Open Drain Control Register PPx PWM Period Register x DP7 Port7 Direction Control Register PWx PWM Pulse Width Register x P7 Port7 Data Register PTx PWM Counter Register x PWMIC PWM Interrupt Control Register PWMCONxPWM Control Register 0 1 Y Bit is linked to a function Bithas no function or is not implemented E Register is in ESFR internal memory space 3 201 294 ST10X167 Figure 117 PWM channel block diagram PPx Period Register Control 16 Bit Up Down Count
293. ive following segment to prevent the prefetcher from trying to leave the current segment Data Pages are contiguous blocks of 16K Byte each They are referenced via the data page pointers DPP3 0 and via an explicit data page number for data accesses overriding the standard DPP scheme Each DPP register can select one of the possible 1024 data pages The DPP register that is used for the current access is selected via the two upper Bit of the 16 Bit data address Subsequent 16 Bit data addresses that cross the 16K Byte data page boundaries therefore will use different data page pointers while the physical locations need not be subsequent within memory 33 294 ST10X167 4 THE CENTRAL PROCESSING UNIT CPU The CPU is used to fetch and decode instructions to supply operands for the arithmetic and logic unit ALU to perform operations on these operands in the ALU and to store the previously calculated results A four stage pipeline is implemented where up to four instructions can be processed in parallel Most instructions of the ST10X167 are executed in one instruction cycle due to this parallelism This chapter describes how the pipeline works for sequential and branch instructions in general and which hardware provisions have been made to speed the execution of jump instructions in particular The general instruction timing is described including standard and exceptional timing While internal memory accesses n
294. ize the necessary actions to transmit and receive data over the CAN bus The CAN and CPU activities are described including the servicing program Figure 133 CAN controller handling of message objects in transmit direction NEWDAT 0 load message into buffer Transmission successful yes INTPND 1 232 294 Received remote frame with same identifier as this message object TXRQ 1 RMTPND 1 INTPND 1 TXRQ 0 RMTPND 0 0 reset 1 set ST10X167 Figure 134 CPU handling of message objects in transmit direction Power Up all Bit undefined TXIE application specific 0 reset RXIE application specific 1 set INTPND 0 RMTPND 0 TXRQ 0 CPUUPD 1 Identifier application specific NEWDAT 0 Direction transmit DLC application specific MSGVAL 1 XTD application specific Initialisation CPUUPD 1 Update Start NEWDAT 1 write calculate message contents Update End CPUUPD 0 update message ky 233 294 ST10X167 Figure 135 CAN controller handling of message objects in receive direction Bus idle Received frame with same identifier as this message object load identifier and control into buffer yes MSGLST 1 Store message 4 NEWDAT 1 successful TXRQ 0 RMTPND 0 TXRQ 0 RMTPND 0 yes yes INTPND 1 INTPND 1 0 reset 1 set 234 294 3 ST10X167 F
295. k fcpy either divided by 2 or divided by 128 This 16 Bit timer is realized as two concatenated 8 Bit timers see Figure 100 The upper 8 Bit of the watchdog timer can be preset to user programmable value by a watchdog service access in order to program the watchdog expire time The lower 8 Bit are reset on each service access Figure 99 SFRs and port pins associated with the watchdog timer Reset Indication Pin 1514131211109876543210 Y Bit is linked to a function Bit has no function or is not implemented E Register is in ESFR internal memory space Data Registers Control Registers 1514131211109876543210 WDTR 2 N 7 RSTOUT WDT Control 12 1 Operation of the Watchdog Timer WDTREL The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT which is a Bitaddressable read only register The operation of the Watchdog Timer is controlled by its Bitaddressable Watchdog Timer Control Register WDTCON This register specifies the reload value for the high Byte of the timer selects the input clock prescaling factor and provides a flag that indicates a watchdog timer overflow ky 177 294 ST10X167 WDTCON FFAEh D7h SFR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x Wm 1 wr wem RW RW RW ResetValue 000Xh Watchdog Timer Input Frequency Selection 0 Input frequency is fcpu 2 1 Input frequency is fopy 128 Watchdog
296. l symmetrically Figure 119 Operation and output waveform in mode 1 PPx Period 7 PTx Count Value PWx Pulse Width 0 PWx 1 PWx 2 PWx 4 PWx 6 PWx 7 PWx 8 Duty Cycle 100 87 5 75 50 25 12 5 0 LSR Change Count Latch Shadow Registers Interrupt Reques 204 294 Direction 15 1 3 Burst Mode Note Burst mode is selected by setting Bit PB01 in register PWMCONI1 to 1 This mode combines the signals from PWM channels 0 and 1 onto the port pin of channel 0 The output of channel O is replaced with the logical AND of channels 0 and 1 The output of channel 1 can still be used at its associated output pin if enabled Each of the two channels can either operate in mode 0 or 1 Figure 120 Operation and output waveform in burst mode Channel 0 PP1 PT1 Channel 1 Resulting Output POUTO ST10X167 It is guaranteed by design that no spurious spikes will occur at the output pin of channel 0 in this mode The output of the AND gate will be transferred to the output pin synchronously to internal clocks XORing of the PWM signal and the port output latch value is done after the ANDing of channel O and 1 see Figure 120 205 294 ST10X167 15 1 4 Single Shot Mode Single shot mode is selected by setting the respective Bit PSx in register PWMCONI1 to 1 This mode is available for PWM channels 2 and 3 In this mode the timer PTx of the respective PWM
297. l ANDing of the two specified Bit ky V Flag For addition subtraction and 2 s complementation the V flag is always set to 1 if the result overflows the maximum range of signed numbers which are representable by either 16 Bit for Word operations 8000h to 7FFFh or by 8 Bit for Byte operations 80h to 7Fh otherwise the V flag is cleared The result of an integer addition integer subtraction or 2 s complement is not valid if the V flag indicates an arithmetic overflow For multiplication and division the V flag is set to 1 if the result cannot be represented in a Word data type otherwise it is cleared A division by zero will always cause an overflow In contrast to the result of a division the result of a multiplication is valid regardless of whether the V flag is set to 1 or not Since logical ALU operations cannot produce an invalid result the V flag is cleared by these operations The V flag is also used as Sticky Bit for rotate right and shift right operations With only using the C flag a rounding error caused by a shift right operation can be estimated up to a quantity of one half of the LSB of the result In conjunction with the V flag the C flag allows evaluating the rounding error with a finer resolution see Figure 13 For Boolean Bit operations with only one operand the V flag is always cleared For Boolean Bit operations with two operands the V flag represents the logical ORing of the
298. l FI ILLINA Illegal Instruction Access Flag BN n 13 12 9 8 7 6 5 4 3 2 1 0 STK UND PRT ILL ILL ILL UF OPC FLT OPA INA BUS RW RW RW RW RW RW ResetValue 0000h PRTFLT Protection Fault Flag ccc RN UNDOPC Undefined Opcode Flag O ILLOPA Illegal Word Operand Access Flag A Word operand access read or write to an odd address has been attempted STKUF Stack Underflow Flag Bl o VEI STKOF Stack Overflow Flag Non Maskable Interrupt Flag Lo A negative transition falling edge has been detected on pin NMI Note The trap service routine must clear the respective trap flag otherwise a new trap will be requested after exiting the service routine Setting a trap request flag by soft ware causes the same effects as if it had been set by hardware The reset functions hardware software watchdog may be regarded as a type of trap Reset functions have the highest system priority trap priority III Class A traps have the second highest priority trap priority II on the 3rd rank are class B traps So a class A trap can interrupt a class B trap If more than one class A trap occur at a time they are prioritized internally with the NMI trap on the highest and the stack underflow trap on the lowest priority All class B traps have the same trap priority trap priority 1 When several class B traps get active at a time the corresponding flags in the register are set and the trap
299. l lines the two serial interfaces and the control lines BHE WRH and CLKOUT Table 12 Port3 alternative functions Ports Pin Alternate Function TOIN CAPCOM1 Timer 0 Count Input T6OUT Timer 6 Toggle Output CAPIN GPT2 Capture Input T30UT Timer 3 Toggle Output TSEUD Timer 3 External Up Down Input TAIN Timer 4 Count Input 3 Count Input T2IN Timer 2 Count Input MRST SSC Master Receive Slave Transmit MTSR SSC Master Transmit Slave Receive TxD0 ASCO Transmit Data Output RxD0 ASC0 Receive Data Input BHE WRH Byte High Enable Write High Output SCLK SSC Shift Clock Input Output CLKOUT System Clock Output Figure 32 Port3 I O and alternate functions Alternate Functions P3 15 CLKOUT No Pin P3 13 SCLK P3 12 BHE P3 11 RxD0 P3 10 P3 9 MTSR P3 8 MRST P3 7 T2IN P3 6 T3IN 5 TAIN P3 4 T3EUD P3 3 T30UT P3 2 CAPIN P3 1 T6OUT P3 0 TOIN General Purpose Input Output 86 294 ST10X167 The port structure of the Port3 pins depends on their alternate function see Figure 33 When the on chip peripheral associated with a Port3 pin is configured to use the alternate input function it reads the input latch which represents the state of the pin via the line labeled Alternate Data Input Port3 pins with alternate input func tions are TOIN T2IN T3IN TAIN T3EUD and CAPIN When the on chip peripheral associate
300. lag is set it indicates that the transmit buffer SSCTB is empty and ready to be loaded with the next transmit data If SSCTB has been reloaded by the time the current transmission is finished the data is immediately transferred to the shift register and the next transmission will start without any additional delay On the data line there is no gap between the two successive frames so two Byte transfers would look the same as one Word transfer This feature can be used to interface with devices which can operate with or require more than 16 data Bit per transfer It is just a matter of software how long a total data frame length can be This option can also be used to interface to Byte wide and Word wide devices on the same serial bus Note Of course this can only happen in multiples of the selected basic data width since it would require disabling enabling of the SSC to reprogram the basic data width on the fly ky ST10X167 Device 2 Shift Register Common Transmit I Receive Device 3 Line 11 2 1 Port Control The SSC uses three pins of Port3 to communicate with the external world Pin P3 13 SCLK serves as the clock line while pins P3 8 MRST Master Receive Slave Transmit and P3 9 MTSR Master Transmit Slave Receive serve as the serial data input output lines The operation of these pins depends on the selected operating mode master or slave In order to enable the alternate output fun
301. lear this Bit Bit WDTR can be examined by software in order to determine the cause of the reset A watchdog reset will also complete a running external bus cycle before starting the internal reset sequence if this bus cycle does not use READY or samples READY active low after the programmed waitstates Otherwise the external bus cycle will be aborted After a hardware reset that activates the Bootstrap Loader the watchdog timer will be disabled 178 294 To prevent the watchdog timer from overflowing it must be serviced periodically by the user software The watchdog timer is serviced with the instruction SRVWDT which is a protected 32 Bit instruction Servicing the watchdog timer clears the low Byte and reloads the high Byte of the watchdog time register WDT with the preset value in Bit field WDTREL which is the high Byte of register WDTCON Servicing the watchdog timer will also reset Bit WDTR After being serviced the watchdog timer continues counting up from the value WDTREL x 28 Instruction SRVWDT has been encoded in such a way that the chance of unintentionally servicing the watchdog timer eg by fetching and executing a Bit pattern from a wrong location is minimized When instruction SRVWDT does not match the format for protected instructions the Protection Fault Trap will be entered rather than the instruction be executed The time period for an overflow of the watchdog timer is programmable in two ways
302. lected the delimiter 1 or 2 stop Bit Data transmission is double buffered When the transmitter is idle the transmit data loaded into SOTBUF is immediately moved to the transmit shift register thus freeing SOTBUF for the next data to be sent This is indicated by the transmit buffer interrupt request flag SOTBIR being set SOTBUF may now be loaded with the next data while transmission of the previous one is still going on The transmit interrupt request flag SOTIR will be set before the last Bit of a frame is transmitted that means before the first or the second stop Bit is shifted out of the transmit shift register The transmitter output pin TXDO P3 10 must be configured for alternate data output P3 10 1 and DP3 10 1 Asynchronous reception is initiated by a falling edge 1 to 0 transition on pin RXDO provided that Bit SOR and SOREN are set The receive data input pin RXDO is sampled at 16 times the rate of the selected Baud rate A majority decision of the 7th 8th and 9th sample determines the effective Bit value This avoids erroneous results that may be caused by noise If the detected value is not a 0 when the start Bit is sampled the receive circuit is reset and waits for the next 1 to O transition at pin RXDO If the start Bit proves valid the receive circuit continues sampling and shifts the incoming data frame into the receive shift register Data Bit D8 Parity Wake up Bit ST10X167 Wh
303. locked by modifying the port output latches P3 0 or P2 15 via software for example for testing purposes The maximum external input frequency to TO or T7 in counter mode is fcpy 16 To ensure that a signal transition is properly recognized at the timer input an external count input signal should be held for at least 8 CPU clock cycles before it changes its level again The incremented count value appears in SFR TO T7 within 8 CPU clock cycles after the signal transition at pin TxIN Reload A reload of a timer with the 16 Bit value stored in its associated reload register in both modes is performed each time a timer would overflow from FFFFh to 0000h In this case the timer does not wrap around to 0000h but rather is reloaded with the contents of the respective reload register TxREL The timer then resumes incrementing starting from the reloaded value The reload TxREL are not Bit addressable registers 14 2 CAPCOM Unit Timer Interrupts Upon a timer overflow the corresponding timer interrupt request flag TxIR for the respective timer will be set This flag can be used to generate an interrupt or trigger a PEC service request when enabled by the respective interrupt enable Bit TxIE Each timer has its own Bitaddressable interrupt control register TxIC and its own interrupt vector TxINT The organization of the interrupt control registers TxIC is identical with the other interrupt control registers T0IC FF9Ch
304. log supply must be sufficiently low however High internal resistance can be achieved by programming the respective times to a higher value or the possible maximum This is preferable when using analog sources and supply with a high internal resistance in order to keep the current as low as possible The conversion rate in this case may be considerably lower however The conversion times are programmed via the upper four Bit of register ADCON Bit field ADCTC conversion time control selects the basic conversion clock used for the 14 steps of converting The sample time is a multiple of this conversion time and is selected by Bit field ADSTC sample time control The table below 218 294 lists the possible combinations The timings refer to the unit TCL where fcpy 1 2TCL Conversion Sample C T Mm Reserved do not use ot tec x2 mem reo A complete conversion will take 14 2tsc 4TCL This time includes the conversion itself the sample time and the time required to transfer the digital value to the result register Note The decoding of Bit field ADCTC provides compatibility with ST10F166 designs for the default value 00 at after reset 16 3 Calibration A full calibration sequence is performed after a reset This full calibration lasts 40 000 CPU clock cycles During this time the busy flag ADBSY is set to indicate the operation Normal conversion may be performed during t
305. ls do not change The external bus cycles of the ST10X167 can be extended for a memory or a peripheral which cannot keep pace with the controllers maximum speed some waitstates are introduced during the access see Figure During these memory cycle time waitstates the CPU is idle if this access is required for the execution of the current instruction The memory cycle time waitstates can be programmed in increments of one CPU clock within a range from 0 to 15 default after reset via the MCTC fields of the BUSCON registers 15 MCTC waitstates will be inserted Figure 54 Memory cycle time a Bus Cycle Segment X Address MCTC Wait States 1 8 3 3 Programmable Memory Tri state Time The ST10X167 allows the user to adjust the time between two subsequent external accesses to address slow external device The tri state time MTTC starts when the external device has released the bus after deactivation of the read command RD The output of the next address on the external bus can be delayed for a memory or peripheral which needs more time to switch off its bus drivers by introducing a waitstate after the previous bus cycle see Figure 55 During this memory tri state time waitstate the CPU is not idle so CPU operations will only be slowed down if a subsequent external instruction or data fetch operation is required during the next instruction cycle The memory tri state time waitsta
306. lternate Data Latch Read P1H y P1L y ST10X167 15 2 14 CC26lO CC25IO A12 240 11 9 8 A7 A6 A5 A4 A3 A2 A1 A0 8 16 Bit CAPCOM2 Capture Inputs While an external bus mode is enabled the user software should not write to the port output latch otherwise unpredictable results may occur When the external bus modes are disabled the contents of the direction register last written by the user becomes active The Figure 29 shows the structure of a PORT1 pin MUX 5 Output Buffer Input Latch 81 294 ST10X167 6 4 Port2 If this 16 Bit port is used for general purpose I O the direction of each line can be configured via the cor responding direction register DP2 Each port line can be switched into push pull or open drain mode via the open drain control register ODP2 P2 FFC0h E0h SFR ResetValue 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RW RW RW RW RW RW RW RW Port data register P2 Bit y DP2 FFC2h E1h SFR ResetValue 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW RW Port direction register DP2 Bit y DP2 y 0 Port line P2 y is an input high impedance DP2 y 1 Port line P2 y is an output ODP2 F1C2h Eth ESFR Reset Value 0000h 15 14 11 0 41 10 RW RW RW RW RW RW RW RW RW Port2 Open Drain control register Bit y ODP2 y 0 Port line P2 y output driver in pu
307. ltiplies the external clock frequency by a selectable factor of 1 F and generates a CPU clock signal with 50 duty cycle The PLL also provides fail safe mechanisms which allows the detection of frequency deviations and the execution of emergency actions in case of an external clock failure even when PLL is by passed see Chapter 12 Watchdog Timer ky ST10X167 Figure 3 PLL block diagram POH 7 6 5 Prescaler Oscillator Circuit PLL Circuit fpi F x fin B Factor reset sleep Unlock XP3INT Oscillator Watchdog The Table 1 lists all the possible selections for the on chip clock generator Table 1 On chip clock generator selections Ea on 7 5 CPU Frequency fcpy fxrTAL X F CPU Frequency fcpy fxTAL X F om NA f Baa x 1 x i Note 1 The maximum depends on the duty cycle of the external clock signal The maximum input frequency is 25 MHz when using an external crystal oscillator however higher frequencies can be applied with an external clock source qom 3 19 294 ST10X167 2 4 1 PLL Operation The PLL is enabled except when 7 5 011 or 001 during reset On power up the PLL provides a stable clock signal within 1ms after Vpp has reached 5V 10 even if there is no external clock signal in this case the PLL will run on its basic frequency of 2 5 MHz The PLL sta
308. lue 0000h 190 Reset Value 0000h 190 Reset Value 0000h 190 Reset Value 0000h 190 Reset Value 0000h 190 Reset Value 0000h 190 Reset Value 0000h 190 Reset Value 0000h 190 Reset Value 00h 198 Reset Value XXO1h 223 Reset Value FCOOh 49 Reset Value 00h 154 Reset Value 0000h 46 Reset 00h 78 Reset Value 00h 78 Reset 00h 80 Reset Value 00h 80 Reset Value 0000h 82 Reset Value 0000h 85 Reset Value 00h 89 Reset Value 00h 92 Reset Value 00h 96 Reset 00h 99 Reset Value 0000h 48 Reset Value 0001h 48 Reset Value 0002h 48 Reset Value 0003h 48 Reset Value 0000h 70 Reset Value 0000h 254 Reset Value UFUUh
309. me the request is activated selects the action COUNT may allow a specified number of PEC transfers unlimited transfers or no PEC service at all The table below summarizes how the COUNT field itself the interrupt requests flag IR and the PEC channel action depend on the previous content of COUNT Action of PEC Channel and Comments I Previous Modified PEC service Move a Byte Word Continuous transfer mode COUNT is not modified FEh 02h FDh 01h Move a Byte Word and decrement COUNT Move a Byte Word Leave request flag set which triggers another request No action Activate interrupt service routine rather than PEC channel The PEC transfer counter allows to service a specified number of requests by the respective PEC channel and then when COUNT reaches 00h activate the interrupt service routine which is associated with the priority level After each PEC ky ST10X167 transfer the COUNT field is decremented and the request flag is cleared to indicate that the request has been serviced Continuous transfers are selected by the value FFh in bit field COUNT In this case COUNT is not modified and the respective channel services any request until it is disabled again When COUNT is decremented from 01h to 00h after a transfer the request flag is not cleared which generates another request from the same source When COUNT already contains the value 00h th
310. mm om CAPCOM Timer T ana 8 ConvelRegiier ooon enc o E WemuerConifegser Umm b rise E ce XPerhesziemuiConiRegeer Desc b rsen E CFn PLL unockhierupkConrelRegiter zeros p rris vaue 0s Regter tedon 3 264 294 ST10X167 20 4 Registers Ordered by Address SFRs within the Extended SFR Space ESFRs The following table lists all SFRs which are are marked with the letter E in column Physical implemented in the ST10X167 ordered by their Address Registers within on chip X Peripherals physical address Bit addressable SFRs are CAN are marked with the letter X in column marked with the letter b in column Physical Address Table 44 Registers ordered by address Physical 8 bit Reset Fo30h E PWM Module Up Down Counter 0 0000h F032h E 19Hh PWM Module Up Down Counter 1 0000h F034h E PWM Module Up Down Counter 2 0000h F036h E PWM Module Up Down Counter 3 0000h F038h E PWM Module Period Register 0 0000h FO3Ah E PWM Module Period Register 1 0000h FO3Ch E PWM Module Period Register 2 0000h FO3Eh E PWM Module Period Register 3 0000h FO50h E h CAPCOM Timer 7 Register 0000h F052h E h CAPCOM Timer 8 Register 0000h T7REL F054h E h CAPCOM Timer 7 Reload Register 0000h T8REL FO56h E h CAPCOM Timer 8 Reload Register 0000h IDPROG F078h E Programming Voltage Identifier Register not in ST10
311. mmable as inputs or outputs via direction registers The I O ports are true bidirectional ports which are switched to high impedance state when configured as inputs The output drivers of three I O ports can be configured pin by pin for push pull operation or open drain operation via control registers During the internal reset all port pins are configured as inputs All pins of I O ports also support an alternate pro grammable function PORTO and PORT1 may be used as data and address lines respectively when accessing external memory Port2 accepts the fast external interrupt inputs and provides inputs outputs for CAPCOM unit Port3 includes the alternate functions of timers serial interfaces the optional bus control signal BHE and the system clock output CLKOUT Port4 outputs the additional segment address bit A16 to A23 in systems where segmentation is enabled to access more than 64K Byte of memory Port5 is used as analog input channels of the A D converter or as timer control signals Port6 provides optional bus arbitration signals BREQ HLDA HOLD and chip select signals Port provides the output signals from the PWM unit and inputs outputs for the CPACOM2 unit Port8 provides inputs outputs for the CAPCOM2 unit Four pins of PORT1 may also be used as inputs only for the CAPCOM2 unit All port lines that are not used for alternate func tions may be used as general purpose I
312. n When the SP is incremented by an add instruction the pushed IP value represents the address of the instruction after the instruction following the add instruction 5 7 6 Undefined Opcode Trap When the instruction currently decoded by the CPU does not contain a valid ST10X167 opcode the UNDOPC flag is set in register TFR and the ky ST10X167 CPU enters the undefined opcode trap routine The IP value pushed onto the system stack is the address of the instruction that caused the trap This can be used to emulate non implemented instructions The trap service routine can examine the faulting instruction to decode operands for non implemented opcodes based on the stacked IP In order to resume processing the stacked IP value must be incremented by the size of the undefined instruction which is determined by the user before a RETI instruction is executed 5 7 7 Protection Fault Trap The format of the protected instructions is 4 Byte wide Byte 1 and 2 are complementary values Byte 3 and 4 are identical to Byte 1 For example the format of SRST instruction is B7h 48h B7h B7h If the format of a protected instruction going to be executed does not fulfill this coding the PRTFLT flag in register is set and the CPU enters the protection fault trap routine The protected instructions include DISWDT EINIT IDLE PWRDN SRST and SRVWDT When the protection fault trap occurs the IP value pushed onto the system stack i
313. n P7 1 Latch P7 0 Pin P7 0 16 ANALOG DIGITAL CONVERTER The ST10X167 provides an Analog Digital Converter with 10 Bit resolution and a sample amp hold circuit on chip A multiplexer selects between up to 16 analog input channels alternate functions of Port5 either via software fixed channel modes or automatically auto scan modes An automatic self calibration adjusts the ADC module to changing temperatures or process variations The ADC supports the following conversion modes Fixed channel single conversion produces just one result from the selected channel Fixed channel continuous conversion repeatedly converts the selected channel ST10X167 Auto scan single conversion produces one result from each of a selected group of channels Auto scan continuous conversion repeatedly converts the selected group of channels Wait for ADDAT read mode start a conversion automatically when the previous result was read Channel injection mode insert the conversion of a specific channel into a group conversion auto scan A set of SFRs and port pins provide access to control functions and results of the ADC Figure 123 SFRs and port pins associated with the A D converter Ports amp Direction Control Alternate Functions 1514131211109876543210 P Y YYYYYYYYYYYYYYY ANO P5 0 AN15 P5 15 Control Registers 1514131211109876543210 ADCON YYYYYYYYY YYYYYY P5 ADDAT ADDAT2 ADCON Por
314. n addition the condition flags for Byte operations are provided from Bit six and seven of the ALU result Multiple precision arithmetic is provided through a CARRY IN signal to the ALU from previously calculated portions of the desired operation Most of the internal execution blocks have been optimized to perform operations on either 8 Bit or 16 Bit data Once the pipeline has been filled one instruction is completed per instruction cycle except for multiply and divide An advanced Booth algorithm has been incorporated to allow four Bit to be multiplied and two Bit to be divided per instruction cycle Thus these operations use two coupled 16 Bit registers MDL and and require four and nine instruction cycles respectively to perform a 16 Bit by 16 Bit or 32 Bit by 16 Bit calculation plus one instruction cycle to setup and adjust the operands and the result Even these longer multiply and divide instructions can be interrupted during their execution to allow very fast interrupt response Instructions have also been provided to allow Byte packing in memory while providing sign extension of Byte for Word wide arithmetic operations The internal bus structure also allows transfers of Byte or Words to or from peripherals based on the peripheral requirements A set of consistent flags is automatically updated in the PSW after each arithmetic logical shift or movement operation These flags allow branching spec
315. n addition the conversion of a specific channel can be inserted injected into a running sequence without disturbing this sequence This is called Channel Injection Mode The Peripheral Event Controller PEC may be used to automatically store the conversion results into a table in memory for later evaluation without the overhead of interrupt routines for each data transfer ST10X167 2 6 Protected Bits The ST10X167 MCU provide 106 protected Bit These Bit are modified by the on chip hardware during special events like power on reset power failure application hardware etc These bit cannot be modified by some wrong software accesses Table 2 Protected Bit pwc y 3 0 X Peripheral y interrupt request flag Note 106 protected Bit 3 25 294 ST10X167 3 MEMORY ORGANIZATION The memory space of the ST10X167 is configured in a Von Neumann architecture Code memory data memory registers and I O ports organized within the same linear address space All of the physically separated memory areas including internal ROM Flash internal RAM the internal Special Function Register Areas SFRs and ESFRs the address areas for integrated XBUS peripherals like XRAM or CAN module and external memory are mapped into one common address space The ST10X167 provides a total addressable memory space of 16M Byte This address space is arranged as 256 segments of 64K Byte each and each segm
316. n is complete The software initialization routine should be terminated with the EINIT instruction This instruction has been implemented as a protected instruction Execution of the EINIT instruction disables the action of the DISWDT instruction disables write accesses to register SYSCON see note and causes the RSTOUT pin to go high This signal can be used to indicate the end of the initialization routine and the proper operation of the microcontroller to external hardware Note All configurations regarding register SYSCON enable CLKOUT stacksize etc must be selected before the execution of EINIT 18 2 1 System Start up Configuration Although most programmable features are either selected during the initialization phase or repeatedly during program execution there are some features that must be selected earlier because they are used for the first access of the program execution for example internal or external start selected via EA These selections are made during reset by the pins of PORTO which are read at the end of the internal reset sequence During reset internal pull up devices are active on the PORTO lines so their input level is high if the respective pin is left open or is low or if the respective pin is connected to an external pull down device With the coding of the selections as shown below in many cases the default option high level can be used The value on the upper Byte of PORTO POH is
317. n switching between master and slave mode 11 3 Baud Rate Generation The serial channel SSC has its own dedicated 16 Bit Baud rate generator with 16 Bit reload capability allowing Baud rate generation independent from the timers The Baud rate generator is clocked by fcpu 2 The timer is counting downwards and can be started or stopped through the global enable Bit SSCEN in register SSCCON Register SSCBR is the dual function Baud Rate Generator Reload register Reading SSCBR while the SSC is enabled returns the content of the timer Reading SSCBR while the SSC is disabled returns the programmed reload value In this mode the desired reload value can be written to SSCBR Note Never write to SSCBR while the SSC is enabled The formulas below calculate the resulting Baud rate for a given reload value and the required reload value for a given Baud rate sa fcpu aud rate SSC 2x SSCBR 1 cPU SSCBR _ 1 2 x Baud ratessc SSCBR represents the content of the reload register taken as unsigned 16 Bit integer Refer to the device datasheet for a table of Baud rates reload values and resulting Bit times 11 4 Error Detection Mechanisms The SSC is able to detect four different error conditions Receive Error and Phase Error are detected in all modes while Transmit Error and Baud rate Error only apply to slave mode When 174 294 an error is detected the respective error flag is set When t
318. n the interrupt enable bit CCxIE is set a PEC request or an interrupt request for vector CCxINT will be generated see Table 10 Pins T2IN or T4IN can be used as external interrupt input pins when the associated auxiliary timer T2 or T4 in block GPT1 is configured for capture mode This mode is selected by programming the mode control fields T2M or T4M in control registers T2CON or T4CON to 101b Control Register 2 0 15 0 1 Register 0 15 Capture Input CC0 CC15 P8 0 7 CC16 231 0 CAPCOM Register 16 23 Capture Input CC16 CC23 P1H 4 7 CC24 271 0 CAPCOM Register 24 27 Capture Input CC24 CC27 3 69 294 ST10X167 The active edge of the external input signal is determined by bit fields 21 41 When these fields are programmed to X01b interrupt request flags T2IR or T4IR in registers T2IC or T4IC will be set on a positive external transition at pins T2IN or TAIN respectively When 21 or 4 are programmed to X10b then a negative external transition will set the corresponding request flag When 21 or are programmed to X11b both a positive and a negative transition will set the request flag In all three cases the contents of the core timer T3 will be captured into the auxiliary timer registers T2 or T4 based on the transition at pins T2IN or T4IN When the interrupt enable bit T2IE or T4IE are set PEC request or an interrupt request for vector T2INT or T4INT will be generated
319. nal BHE WRH and the system clock output CLKOUT Port5 is used for the analog input channels to the A D converter or timer control sig nals 76 294 If an alternate output function of a pin is to be used the direction of this pin must be pro grammed for output DPx y 1 except for some signals that are used directly after reset and are configured automatically Otherwise the pin remains in the high impedance state and is not effected by the alternate output function The respective port latch should hold a 1 because its output is ANDed with the alternate output data except for PWM output signals If an alternate input function of a pin is used the direction of the pin must be programmed for input DPx y 0 if an external device is driving the pin The input direction is the default after reset If no external device is connected to the pin however one can also set the direction for this pin to output In this case the pin reflects the state of the port output latch Thus the alternate input function reads the value stored in the port output latch This can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch ky ST10X167 On most of the port lines the user software is There is one basic structure for all port lines with responsible for setting the proper direction when only an alternate input function Port lines with using an alternate
320. nal groups allows to start or to stop all the 4 PWM timers simultaneously with one Bitfield instruction PWMCONDO FF30h 98h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW RW RW RW RW R RW RW RW PWM Timer x Run Control Bit 0 Timer PTx is disconnected from its input clock 1 Timer PTx is running PWM Timer x Input Clock Selection 0 Timer clocked with CLKcpu 1 Timer PTx clocked with CLKcpu 64 PWM Channel x Interrupt Enable Flag 0 Interrupt from channel x disabled 1 Interrupt from channel x enabled PWM Channel x Interrupt Request Flag 0 No interrupt request from channel x 1 Channel x interrupt pending must be reset via software 208 294 ky ST10X167 PWM Control Register PWMCON1 Register PWMCON1 controls the operating modes and the outputs of the four PWM channels The basic operating mode for each channel standard edge aligned or symmetrical center aligned PWM mode is selected by the mode Bit PMx Burst mode channels 0 and 1 and single shot mode channel 2 or 3 are selected by separate control Bit The output signal of each PWM channel is individually enabled by Bit PENx If the output is not enabled the respective pin can be used for general purpose I O and the PWM channel can only be used to generate an interrupt request PWMCON 1 FF32h 99h SFR ResetValue 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM Channel x O
321. nally been made directly Bit addressable A 2K Byte 16 Bit wide internal RAM provides fast access to General Purpose Registers GPRs user data variables and system stack The internal RAM may also be used for code A unique decoding scheme provides flexible user register banks in the internal memory while optimizing the remaining RAM for user data The CPU contains an actual register context consisting of up to 16 Word wide and or Byte wide GPRs which are physically located within the on chip RAM area A Context Pointer CP register determines the base address of the active register bank to be accessed by the CPU at a time The number of register banks is only restricted by the available internal RAM space For easy parameter passing one register bank may overlap others A system stack of up to 1024 Words is provided as a storage for temporary data The system stack is also located within the on chip RAM area and it is accessed by the CPU via the stack pointer SP register Two separate SFRs STKOV and STKUN are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow Hardware detection of the selected memory space is placed at the internal memory decoders and allows the user to specify any address directly or indirectly and obtain the desired data without using temporary registers or special instructions A 2K Byte 16 Bit wide on chip XRAM provides fas
322. nate Data Output Write Port P8 y Compare Trigger Read P8 y Y Y Buffer 3 Alternate Latch Data Input Alternate Pin Data Input pp 8 Output N 4 CCzIO 101 294 ST10X167 7 DEDICATED PINS Most of the input output or control signals of the including the oscillator special control signals and ST10X167 are realized as alternate functions of the power supply pins of the parallel ports There is however a The Table 18 summarizes the dedicated pins of number of signals that use separate pins the ST10X167 Table 18 Summary of dedicated pins Address Latch Enable controls external address latches that provide a stable address in multi plexed bus modes ALE is activated for every external bus cycle independent of the selected bus mode It is also activated for bus cycles with a de multiplexed address bus When an external bus is enabled if one or more of the BUSACT Bit is set also X Peripheral accesses will generate an active ALE signal ALE is not activated for internal accesses like accesses to ROM to Flash to the internal RAM and to the special function registers In single chip mode when no external bus is enabled no BUSACT Bit set ALE will also remain inactive for X Peripheral accesses External Read Strobe controls the output drivers of external memory or peripherals when the ST10X167 reads data from these external devices During reset and during Hold mode an in
323. ncident SIE must be set like reception or transmission of a message RXOK or TXOK is set or the occurrence of a CAN bus error LEC is updated The CPU may clear RXOK TXOK and LEC however writing to the status partition of the Control Register can never generate or reset an interrupt To update the INTID value the status partition of the Control Register must be read The last message object has the highest interrupt priority of all message objects 1 01 02 Message 15 Interrupt Bit INTPND in the Message Control Register of message object 15 last message has been set 2 N Message N Interrupt Bit INTPND in the Message Control Register of message object N has been set 1 14 02 Notes 1 Bit INTPND of the corresponding message object has to be cleared to give messages with a lower priority the possibility to update INTID or to reset INTID to 00h idle state 2 A message interrupt code is only displayed if there is no other interrupt request with a higher priority Bit Timing Configuration According to the CAN protocol specification a Bit time is subdivided into four segments Sync segment propagation time segment phase buffer segment 1 and phase buffer segment 2 Figure 131 Bit timing definition 1 Bit time TSeg1 Each segment is a multiple of the time quantum tg with t 1 x2xixCLK The Synchronization Segment Sync seg is always 1 t long The Propagation Time Segmen
324. nd the precautions are the same as I described for the 2 lines All Port8 lines P8 7 P8 0 support capture inputs As all other capture inputs the capture input func or compare outputs CC23lO CC161O for the tion of pins 8 7 8 0 can also be used as exter CAPCOM unit see Table 17 The use of the nal interrupt inputs with a sample rate of 8 CPU port lines by the CAPCOM unit its accessibility clock cycles Table 17 Port8 alternate functions Port8 Pin Alternate Function CC16lO Capture input compare output channel 16 CC171O Capture input compare output channel 17 CC18lO Capture input compare output channel 18 CC19IO Capture input compare output channel 19 CC201O Capture input compare output channel 20 CC211O Capture input compare output channel 21 CC221O Capture input compare output channel 22 CC23IO Capture input compare output channel 23 Figure 45 Port8 I O and alternate functions Alternate Function P8 7 CC2310 P8 6 2210 8 5 cc2110 P8 4 2010 P8 3 C1910 P8 2 CC18lO P8 1 1710 8 0 CC16lO General Purpose Input Output 100 294 5 ST10X167 The pins of Port8 combine internal bus data and alternate data output before the port latch input as do the Port2 pins Figure 46 Block diagram of Port8 pins LS Internal Bus Write ODP8 y Open Drain Latch Read ODP8 y Write DP8 y Direction Latch Read DP8 y Alter
325. ndicates the mechanical zero position may be connected to an external interrupt input and trigger a reset timer T3 for example via PEC transfer from ZEROS see Figure 69 Figure 68 Core timer T3 in incremental interface mode e T3OUT aA P3 3 Table 24 GPT1 core timer T3 incremental interface mode input edge selection T3I Triggering Edge for Counter Increment Decrement None Counter stops 001 Any transition rising or falling edge on T3IN Any transition rising or falling edge on T3EUD Any transition rising or falling edge T3 input T3IN or T3EUD Reserved Do not use this combination 134 294 ST10X167 Figure 69 Connection of the encoder to the ST10X167 tc 2 For incremental interface operation the following conditions must be met Bitfield T3M must be 110b Both pins T3IN and T3EUD must be configured as input at the respective direction control Bit with 0 Bit TSEUD must be 1 to enable automatic direction control The maximum allowed input frequency in incremental interface mode is fcpu 16 To ensure T3input TSinput ST10X167 Interrupt Signal Conditioning correct recognition of the transition of any input signal its level should be held high or low for at least 8 CPU clock cycles In incremental interface mode the count direction is automatically derived from the sequence in which the input signals change This
326. ng a single instruction Note Instructions EXTR EXTPR and EXTSR inhibit interrupts the same way as ATOMIC The switching to the ESFR area and data page overriding is checked by the development tools or handled automatically Nested Locked Sequences Each of the described extension instruction and the ATOMIC instruction starts an internal extension counter counting the effected instructions When another extension or ATOMIC instruction is contained in the current locked sequence this counter is restarted with the value of the new instruction This allows the construction of locked sequences longer than 4 instructions Note Interrupt latencies may be increased when using locked code sequences PEC requests are not serviced during idle mode if the IDLE instruction is part of a locked sequence 21 10 Handling the Internal ROM The mask ROM or Flash Memory versions of the ST10X167 may provide and control a 32K Byte internal ROM area that may store code as well as data Access to this internal ROM area is controlled during the reset configuration and via software The ROM area may be mapped to segment 0 to segment 1 or may be disabled at all Note The internal ROM area always occupies an address area of 32KByte even if the implemented mask ROM or Flash memory is smaller than that e g 8KByte Of course the total implemented memory may exceed 32KBytes ROM Configuration During Reset The control input pin EA External Access enables
327. ng the appropriate instructions when popping data from the specific user stack No hardware detection of overflow or underflow of a user stack is provided The following addressing modes allow implementation of user stacks Rw Rb or Rw Rw Pre decrement Indirect Addressing Used to push one Byte or Word onto a user stack This mode is only available for MOV instructions and can specify any GPR as the user stack pointer Rb Rw or Rw Rw Post increment Index Register Indirect Addressing Used to pop one Byte or Word from user stack This mode is available to most instructions with some restrictions For MOV instructions any word GPR can be used as user stack pointer For arithmetic logical and compare instructions only GPRs RO R3 can be used Rb Rw or Rw Rw Post increment Indirect Addressing Used to pop one Byte or Word from a user stack This mode is only available for MOV instructions and can specify any GPR as the user stack pointer 21 2 Register Banking Register banking provides the user with an extremely fast method to switch user context A single instruction cycle instruction saves the old bank and enters a new register bank Each register bank may assign up to 16 registers Each register bank should be allocated during coding based on the needs of each task Once the internal memory has been partitioned into a register bank space internal stack space and a global internal memory area eac
328. nput signal is active at that time the internal reset condition is extended until RSTIN gets inactive During a synchronous hardware reset the PORTO inputs for the reset configuration need some time to settle on the required levels especially if the hardware reset aborts a read operation form an external peripheral During this settling time the configuration may intermittently be wrong In such a case also the PLL clock selection may be wrong It is therefore strongly recommended to provide an external reset pulse of at least 1 ms in order to allow the PLL to settle on the desired CPU clock frequency The input RSTIN provides an internal pullup device equalling a resistor of 50 KQ to 150 KQ the minimum reset time must be determined by the lowest value Simply connecting an external capacitor is sufficient for an automatic power on reset see b in Figure 143 RSTIN may also be connected to the output of other logic gates see a in Figure 143 Note A power on reset requires an active time of two reset sequences 1036 CPU clock cycles after a stable clock signal is available plus about 10 50 ms to allow the on chip oscillator to stabilize 18 1 2 ST10C167 ST10R167 Synchronous Hardware Reset This synchronous hardware reset applicable to ST10C167 ST10R167 Synchronous hardware reset is triggered when the reset input signal RSTIN is sampled low AND the Vpp pin sampled high To ensure the recognition of the RSTIN
329. ns of the internal memory space must be assigned to register banks and system stack When initializing the stack pointer SP and the context pointer CP it must be ensured that these registers are initialized before any GPR or stack operation is performed This includes interrupt processing which is disabled upon completion of the internal reset and should remain disabled until the SP is initialized Note Traps NMI may occur even though the interrupt system is still disabled In addition the stack overflow STKOV and the stack underflow STKUN registers should be initialized After reset the CP SP and STKUN registers all contain the same reset value 00 FCOOh while the STKOV register contains 00 FAOOh With the default reset initialization 256 Words of system stack are available where the system stack selected by the SP grows ky ST10X167 downwards from OO FBFEh while the register bank selected by the CP grows upwards from 00 FCOOh Based on the application the user may wish to initialize portions of the internal memory before normal program operation Once the register bank has been selected by programming the CP register the desired portions of the internal memory can easily be initialized via indirect addressing At the end of the initialization the interrupt system may be globally enabled by setting Bit IEN in register PSW Care must be taken not to enable the interrupt system before the initializatio
330. nsmit Buffer Register SOTBUF Asynchronous Data Frames 8 Bit data frames either consist of 8 data Bit D7 D0 S0M 001b or of 7 data Bit D6 D0 plus an automatically generated parity Bit SOM 011b Parity may be odd or even depending on Bit SOODD in register SOCON An even parity Bit will be set if the modulo 2 sum of Figure 89 Asynchronous 8 Bit data frames Internal Bus the 7 data Bit is 1 An odd parity Bit will be cleared in this case Parity checking is enabled via Bit SOPEN always OFF in 8 Bit data mode The parity error flag SOPE will be set along with the error interrupt request flag if a wrong parity Bit is received The parity Bit itself will be stored in Bit SORBUF 7 159 294 ST10X167 9 Bit data frames either consist of 9 data Bit D8 D0 S0M 100b of 8 data Bit D7 D0 plus an automatically generated parity Bit 50 1110 or of 8 data Bit D7 DO plus wake up Bit SOM 101b Parity may be odd or even depending on Bit 50000 register SOCON An even parity Bit will be set if the modulo 2 sum of the 8 data Bit is 1 An odd parity Bit will be cleared in this case Parity checking is enabled via Bit SOPEN always OFF in 9 Bit data and wake up mode The parity error flag SOPE will be set along with the error interrupt request flag if a wrong parity Bit is received The parity Bit itself will be stored in Bit 8 of SORBUF In wake up mode received frames are onl
331. nterrupt B gt Request Note 1 Line only affected by over underflows of T6 but NOT by software modifications of T6OTL ky 151 294 ST10X167 Figure 84 GPT2 register CAPREL in capture mode Up Down Interrupt Request Edge Select Interrupt GPT2 Capture Reload Register CAPREL in Reload Mode This 16 Bit register can be used as a reload register for the core timer T6 This mode is selected by setting Bit T6SR 1 in register T6CON The event causing a reload in this mode is an overflow or underflow of the core timer T6 Figure 85 GPT2 register CAPREL in reload mode CAPREL Register CRIR Request CAPREL Register Core Timer T6 Up Down 152 294 When timer T6 overflows from FFFFh to 0000h or when it underflows from 0000h to FFFFh the value stored in register CAPREL is loaded into timer T6 This will not set the interrupt request flag CRIR associated with the CAPREL register However interrupt request flag T6IR will be set indicating the overflow underflow of T6 19 p Interrupt Request To CAPCOM Timers GPT2 Capture Reload Register CAPREL Capture and Reload Mode Since the reload function and the capture function of register CAPREL can be enabled individually by Bit T5SC and T6SR the two functions can be enabled simultaneously by setting both Bit This feature can be used to generate an output frequency that is a multiple of the input frequ
332. ntrol register to 111b In compare mode 3 only one compare event will be generated per timer period When the first match within the timer period is detected the interrupt request flag CCxIR is set to 1 and also the output pin alternate port function will be set to 1 The pin will be reset to 0 when the allocated timer overflows If a match was found for register CCx in this mode all further compare events during the current timer period are disabled for CCx until the corresponding timer overflows If after a match was detected the compare register is reloaded with a new value this value will not become effective until the next timer period In order to use the respective port pin as compare signal output pin CCxlO for compare register CCx in compare mode3 this port pin must be configured as output and the corresponding direction control Bit must be set to 1 With this configuration the initial state of the output signal can be programmed or its state can be modified at any time by writing to the port output latch In compare mode 3 the port latch is set upon a compare event and cleared upon a timer overflow see Figure 113 However when compare value and reload value for a channel are equal the respective interrupt requests will be generated only the output signal is not changed set and clear would coincide in this case Note If the port output latch is written to by software a
333. o A17 A16 256K Byte Default without pull downs Eight A23 A16 16M Byte Maximum 00 Four A19 A16 1M Byte Note total accessible address space may be increased by accessing several banks which are distinguished by individual chip select signals 8 2 7 CS Signal Generation During external accesses the EBC can generate a programmable number of CS lines on Port6 which allows to directly select external peripherals 110 294 Transfer Rate i i Speed factor for Byte Word DWord access System Requirements Free I O Lines Very low 1 5 3 6 Low 8 Bit latch Byte bus P1H P1L Low 1 2 4 Very low no latch Byte bus High 16 Bit latch Word bus P1H P1L or memory banks without requiring an external decoder The number of CS lines is selected during reset and coded in Bit field CSSEL in register RP0H see table below E NAM Low latch Word bus Five CS4 CS0 Default without pull downs Port6 pins free for VO 01 The CS outputs are associated with the BUSCONXx registers and are driven active low for any access within the address area defined for the respective BUSCON register C For any access outside this defined address area the respective CS signal will go inactive high At the beginning of each external bus cycle the corresponding valid CS signal is determined and activated All other CS lines are deactivated driven high at the same time Note The CS
334. o a bus transceiver 2 5 7 General Purpose Timer GPT Unit The GPT unit is a flexible multifunctional timer counter structure which may be used for time related tasks such as event timing and counting pulse width and duty cycle measurements pulse generation or pulse multiplication The five 16 Bit timers are organized into two separate modules GPT1 and GPT2 Each timer in each module may operate independently in a number of different modes or may be concatenated with another timer of the same module Each timer can be configured individually for one of three basic modes of operation which are Timer Gated Timer and Counter Mode In Timer Mode the input clock for a timer is derived from the internal CPU clock divided by a programmable prescaler while Counter Mode allows a timer to be clocked in reference to external events via TXIN Pulse width duty cycle measurement is supported in Gated Timer Mode where the operation of a timer is controlled by the gate level on its external input pin TxIN The count direction up down for each timer is programmable by software or may additionally be altered dynamically by an external signal TxEUD to facilitate for example position tracking The core timers T3 and T6 have output toggle latches TxOTL which change their state on each timer overflow underflow The state of these latches may be output on port pins TxOUT or may be used internally to concatenate the core
335. o the compare value Further compare events on the same compare value are disabled until the timer is incremented again or written to by software After a reset compare events for register CCx will only become enabled if the allocated timer has been incremented or written to by software and one of the compare modes described in the following has been selected for this register The different compare modes which can be programmed for a given compare register CCx are selected by the mode control field CCMODx in the associated capture compare mode control register In the following each of the compare modes including the special double register mode is discussed in detail Mode 0 Interrupt only compare mode several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match several compare events per timer period are possible Mode 2 Interrupt only compare mode only one compare interrupt per timer period is generated Mode 3 Pin set 1 on match pin reset 0 on compare time overflow only one compare event per timer period is generated Double Two registers operate on one pin pin toggles on each compare match Register Mode several compare events per timer period are possible 192 294 3 14 5 1 Compare Mode 0 This is an interrupt only mode which can be used for software timing purposes Compare mode 0 is selected for a given compare register CCx by setting Bit field CCMODx
336. ock Pin RXDO P3 11 must also be configured for output P3 11 1 DP3 11 1 during transmission Synchronous reception is initiated by setting Bit SOREN 1 If Bit SOR 1 the data applied at pin RXDO are clocked into the receive shift register synchronous to the clock which is output at pin TXDO After the 8th Bit has been shifted in the content of the receive shift register is transferred to the receive data buffer SORBUF the receive interrupt request flag SORIR is set the receiver enable Bit SOREN is reset and serial data reception stops Pin TXDO P3 10 must be configured for alternate data output P3 10 1 and DP3 10 1 in order to provide the shift clock Pin RXDO P3 11 must be configured as alternate data input DP3 11 0 Synchronous reception is stopped by clearing Bit SOREN A currently received Byte is completed including the generation of the receive interrupt request and an error interrupt request if appropriate Writing to the transmit buffer register while a reception is in progress has no effect on reception and will not start a transmission If a previously received Byte has not been read out of the receive buffer register at the time the reception of the next Byte is complete both the error interrupt request flag SOEIR and the overrun error status flag SOOE will be set if the overrun check has been enabled by SOOEN 10 3 Hardware Error Detection To improve the safety of serial data exch
337. od of time which is determined by the access time of the memory peripheral data become valid Read cycles Input data is latched and the command signal is now deactivated This causes the accessed device to remove its data from the data bus which is then tri stated again Write cycles The command signal is now deactivated If a subsequent external bus cycle is required the EBC places the respective address on the address bus The data remain valid on the bus until the next external bus cycle is started 107 294 ST10X167 Figure 50 Demultiplexed bus cycle Bus Cycle Segment 1 Segment P4 8 2 3 Switching Between the Bus Modes The EBC allows dynamic switching between different bus modes this means that subsequent external bus cycles may be executed in different ways Certain address areas may use multiplexed or demultiplexed buses or use READY control or predefined waitstates A change of the external bus characteristics can be initiated in two different ways Reprogramming the BUSCON and or ADDRSEL registers allows to either change the bus mode for a given address window or change the size of an address window that uses a certain bus mode Reprogramming allows to use a great number of different address windows more than BUSCONS are available on the expense of the overhead for changing the registers and keeping appropriate tables Switching between predefined address windows automatically selec
338. ode 215 Channel Injection M66222 aa 216 CONVERSION TIMING CONTROL 218 CALIBRATION eee acies 218 A D CONVERTER INTERRUPT CONTRQOL enne nennen 218 CAN INTERFACE a ste un uui sss ss 220 THE CAN CONTROLLER natu quqman aou u unu 220 7 294 ST10X167 17 2 17 3 17 4 17 5 17 6 17 7 18 18 1 18 1 1 18 1 2 18 1 3 18 1 4 REGISTER AND MESSAGE OBJECT CAN INTERRUPT HANDLING THE MESSAGE OBJECT ARBITRATION REGISTERS INITIALIZATION AND RESET CAN APPLICATION INTERFACE SYSTEM RESET TYPES OF RESET ST10F167 Synchronous Hardware Reset sss ST10C167 ST10R167 Synch ronous Hardware Reset Asynchronous Hardware Reset T Software Reset Watchdog Timer Reset Bi Directional Reset PINS AFTER RESET System Start up Configuration POWER REDUCTION MODES IDLE MODE POWER DOWN MODE Protected Power Down Mode INTERRUPTIBLE POWER DOWN MODE
339. ode selection and timer allocation of four capture compare registers 189 294 ST10X167 Capture compare mode registers for the CAPCOM1 unit CC0 CC15 CCM0 FF52h A9h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW CCM1 FF54h AAh SFR Reset Value 0000h 14 1 12 10 9 8 15 3 11 7 6 5 4 3 2 1 0 ACC7 CCMOD7 ACC6 CCMOD6 5 5 ACC4 CCMOD4 RW RW RW RW RW RW RW RW CCM2 FF56h ABh SFR Reset Value 0000h 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW FF58h ACh SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW Capture compare mode registers for the CAPCOM2 unit CC16 CC31 FF22h 91h SFR Reset Value 0000h 15 14 1 2 3 1 11 10 9 8 7 6 5 4 3 2 1 0 ACC19 CCMOD19 ACC18 CCMOD18 ACC17 CCMOD17 ACC16 CCMOD16 RW RW RW RW RW RW RW RW CCM5 FF24h 92h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW CCM6 FF26h 93h SFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW CCM7 FF28h 94h SFR Reset Value 0000h 15 14 1 2 3 1 11 10 9 8 7 6 5 4 3 2 1 0 ACC31 CCMOD31 ACC30 CCMOD30 ACC29 CCMOD29 ACC28 CCMOD28 RW RW RW RW RW RW RW RW 3 190 294 CCMODx Mode Selection for 122 222 1 Compare Register available capture compare modes listed the table below ST10X167 ACCx Allocation Bit f
340. of I O Ports of ST10X167 provide Open Drain Control It is used to switch the output driver of a port pin from a push pull configuration to an open drain configuration In push pull mode a port output driver has an upper and a lower transistor thus it can actively drive the line either to a high or a low level In open drain mode the upper transis tor is always switched off and the output driver can only actively drive the line to a low level When writing a 1 to the port latch the lower tran sistor is switched off and the output enters a high impedance state The high level must then be provided by an exter nal pull up device With this feature it is possible to connect several port pins together to a AND wired configuration saving external glue logic and or additional software overhead for enabling disabling output signals This feature is implemented for ports P2 P3 P6 P7 and P8 see respective sections and is con trolled through the respective Open Drain Control Registers ODPx These registers allow the individual Bitwise selec tion of the open drain mode for each port line If the respective control Bit ODPx y is 0 default after reset the output driver is in the push pull mode If ODPx y is 1 the open drain configura tion is selected Note that all ODPx registers are located in the ESFR space see Figure 24 ST10X167 Figure 23 SFRs and pins associated with the parallel ports Data Input
341. of the corresponding mode control register to 100b In this mode the interrupt request flag CCxIR is set each time a match is detected between the content of compare register CCx and the allocated timer Several of these compare events are possible within a single timer period when the compare Figure 110 Compare mode 0 and 1 block diagram ST10X167 value in register CCx is updated during the timer period The corresponding port pin CCxIO is not affected by compare events in this mode and can be used as general purpose pin If compare mode 0 is programmed for one of the registers CC8 CC15 or CC24 CC31 the double register compare mode becomes enabled for this register if the corresponding bank 1 register is programmed to compare mode 1 see section Double Register Compare Mode Capture Register CCx Interrupt COxIR Request CCMODx V lt Port Latch CCxlO Toggle NA Mode 1 CAPCOM Timer Ty Interrupt Request x 31 0 y 0 1 7 8 Note The port latch and pin remain unaffected in compare mode 0 193 294 ST10X167 In the example below the compare value in register CCx is modified from cvl to cv2 after compare events 1 and 3 and from cv2 to cv1 after events 2 and 4 etc This results in periodic interrupt requests from timer Ty and in interrupt requests from register CCx which occur at the time specified by the user through cv1 and cv2 see Figure 111
342. olled via the RWDCx Bit in the BUSCON registers The command s will be delayed if Bit RWDCx is 0 default after reset Read Write Delay M 1 data drivers from the previous bus cycle should be disabled when the RD signal becomes active 114 294 8 3 5 READY Polarity For the ST10C167 and ST10R167 the active level of the ready pin can be set to READY or READY by the RDYPOL Bit 13 in the BUSCON register For the ST10F 167 the active level is fixed on READY 8 3 6 READY READY Controlled Bus Cycles For ST10C167 and ST10R167 the active level of the ready pin can be set to READY or READY by the RDYPOL Bit in the BUSCON register For situations where the programmable waitstates are not enough or where the response access time of a peripheral is not constant the ST10X167 provides external bus cycles that are terminated by a READY or READY input signal synchronous or asynchronous In this case the ST10X167 first inserts a programmable number of waitstates 0 7 and then monitors the READY or READY line to determine the actual end of the current bus cycle The external device drives READY or READY low in order to indicate that data has been latched write cycle or are available read cycle For the ST10C167 and ST10R167 when the READY or READY function is enabled for specific address window each bus cycle in this window must be terminated wi
343. om 80h to 7Fh for the Byte data type For Boolean Bit 44 294 operations with only one operand the N flag represents the previous state of the specified Bit For Boolean Bit operations with two operands the N flag represents the logical XOR of the two specified Bit C Flag After an addition the C flag indicates that a carry from the most significant Bit of the specified Word or Byte data type has been generated After a subtraction or a comparison the C flag indicates a borrow which represents the logical negation of a carry for the addition This means that the C flag is set to 1 if no carry from the most significant Bit of the specified Word or Byte data type has been generated during a subtraction which is performed internally by the ALU as a 2 s complement addition and the C flag is cleared when this complement addition caused a carry The C flag is always cleared for logical multiply and divide ALU operations because these operations cannot cause a carry anyhow For shift and rotate operations the C flag represents the value of the Bit shifted out last If a shift count of zero is specified the C flag will be cleared The C flag is also cleared for a prioritize ALU operation because a 1 is never shifted out of the MSB during the normalization of an operand For Boolean Bit operations with only one operand the C flag is always cleared For Boolean Bit operations with two operands the C flag represents the logica
344. or Capture Compare Register CCx 0 allocated to Timer TO 1 Timer T7 2 1 CCx allocated to Timer T1 1 Timer T8 2 14 3 1 Selection of Capture Modes and Compare Modes CCMODx Selected Operating Mode Disable Capture and Compare Modes The respective CAPCOM register may be used for general variable storage Capture on Positive Transition Rising Edge at Pin CCxlO Capture on Negative Transition Falling Edge at Pin Capture on Positive and Negative Transition Both Edges at Pin CCxlO 100 Compare Mode 0 Interrupt Only Several interrupts per timer period Enables double register compare mode for registers CC8 CC15 and CC24 CC31 101 Compare Mode 1 Toggle Output Pin on each Match Several compare events per timer period This mode is required for double register compare mode for registers CCO CC7 and CC16 CC23 110 Compare Mode 2 Interrupt Only moms porao _____ 111 Compare Mode 3 Set Output Pin on each Match EH cR The detailed discussion of the capture and compare modes is valid for all the capture compare channels so registers Bit and pins are only referenced by the place holder x Note Capture compare channels 24 27 generate an interrupt request but do not provide an output signal The resulting exceptions are indicated in the following subsections A capture or compare event on channel 31 may be used
345. or by the external input pin T6EUD Timer T6 External Up Down Control Input which is the alternate input function of port pin P5 10 These options are selected by Bit T6UD and T6UDE in control register T6CON When the up down control is done by software Bit T6UDE 0 the count direction can be altered by setting or clearing Bit T6UD When T6UDE 1 pin T6EUD is selected to be the controlling source of the count direction However Bit T6UD can still be used to reverse the actual count direction as shown in the Table 26 If T6UD 0 and pin T6EUD shows a low level the timer is counting up With a high level at T6 EUD the timer is counting down If T6UD 1 a high level at pin T6EUD specifies counting up and a low level specifies counting down The count direction can be changed regardless of whether the timer is running or not Table 26 GPT2 core timer T6 count direction control Pin TXEUD Bit TXUDE Bit TxUD Count Direction X o x j 0 Jj 1 jo bn 9 Note The direction control works the same for core timer T6 and for auxiliary timer T5 Therefore the pins and Bit are named Tx 146 294 r ST10X167 Timer 6 Output Toggle Latch An overflow or underflow of timer T6 will clock the toggle Bit T6OTL in control register T6CON T6OTL can also be set or reset by software Bit T6OE Alternate Output Function Enable in register T6CON enables the state of T6OTL to be an alternat
346. or to load a programming routine for Flash devices The BSL mechanism can be used for standard system startup as well as for special occasions Figure 101 Bootstrap loader sequence RSTIN POL 4 RxDO TxDO CSP IP 1 BSL initialization time ST10X167 like system maintenance firmer update or end of line programming or testing Entering the bootstrap loader The ST10X167 enters BSL mode when pin POL 4 is sampled low at the end of a hardware reset In this case the built in bootstrap loader is activated independent of the selected bus mode The bootstrap loader code is stored in a special Boot ROM No part of the standard mask Memory or Flash Memory area is required for this After entering BSL mode and the respective initialization the ST10X167 scans the RXDO line to receive a zero Byte one start Bit eight 0 data Bits and one stop Bit From the duration of this zero Byte it calculates the corresponding Baud rate factor with respect to the current CPU clock initializes the serial interface ASCO accordingly and switches pin TxDO to output Using this Baud rate an identification Byte is returned to the host that provides the loaded data This identification Byte identifies the device to be booted Refer to the datasheet for specific device information O Internal Memory BSL routine 32 Byte user software 2 Zero Byte 1 start Bit eight 0 data Bits 1 stop Bit sent by
347. ored in ascending memory locations with the low Byte at an even Byte address being followed by the high Byte at the next odd Byte address Double Words code only are stored in ascending memory locations as two subsequent Words Single Bit are always stored in the specified Bit position at a Word address Bit position 0 is the least significant Bit of the Byte at an even Byte address and Bit position 15 is the most significant Bit of the Byte at the next odd Byte address Bit addressing is supported for a part of the Special Function Registers a part of the internal RAM and for the General Purpose Registers Figure 5 Storage of Words Byte and Bit in a Byte organized memory xxxx6h Bit 8 xxxx5h Bit xxxx4h Byte xxxx3h Byte xxxx2h Word high Byte Word low Byte xxxx1h xxxx0h xxxxFh Note Byte units forming a single Word dou ble Word must always be stored within the same physical internal external ROM RAM and organizational page segment memory area 3 1 Internal ROM The ST10X167 reserves an address area of variable size depending on the version for on chip mask programmable ROM organized as X 32 or Flash memory The lower 32 KByte of the on chip ROM Flash are referred to as Internal ROM Area Internal ROM accesses are globally enabled or disabled via Bit ky ST10X167 ROMEN in register SYSCON This Bit is s
348. ormally performed by the CPU itself external peripheral or memory accesses are performed by a particular on chip External Bus Controller EBC which is automatically invoked by the CPU whenever a code or data address refers to the external address space If possible the CPU continues to operate while an external memory access is in progress If external data are required but are not yet available or if a new external memory access is requested by the CPU before a previous access has been completed the CPU will be held by the EBC until the request can be satisfied The EBC is described in The External Bus Interface see Chapter 8 The External Bus Interface The on chip peripheral units of the ST10X167 are almost independent of the CPU with a separate clock generator Data and control information is interchanged between the CPU and these peripherals via Special Function Registers SFRs Whenever peripherals need a non deterministic CPU action an on chip Interrupt Controller compares all pending peripheral interrupt requests and prioritizes one of them If the priority of the current CPU operation is lower than the priority of the selected peripheral request an interrupt service will occur There are two types of interrupt processing 1 Standard interrupt processing forces the CPU to save the current program status and return address on the stack before branching to the interrupt vector jump table 2 interrup
349. oscillator input clock signal by a 2 1 prescaler The frequency of fcpu is half the frequency of xTAL The PLL is still running on its basic frequency of 2 5 MHz and delivers the clock signal for the Oscillator Watchdog except for ST10C167 or ST10R167 where if Bit OWDDIS is set the PLL is switched 20 294 2 4 3 Direct Drive When pins P0H 7 5 011 during reset the CPU clock is directly driven from the internal oscillator with the input clock signal this means fopu fosc The maximum input clock frequency depends on the clock signal s duty cycle because the minimum values for the clock phases TCLs must be reselected The PLL runs on its basic frequency of 2 5 MHz and delivers the clock signal for the Oscillator Watchdog except for ST10C167 or ST10R167 where if Bit OWDDIS is set the PLL is switched off 2 4 4 Oscillator Watchdog OWD In order to provide a fail safe mechanism for the instance of a loss of the external clock an oscillator watchdog is implemented when the selected clock option is direct drive or direct drive with prescaler The oscillator watchdog operates as follows For the ST10F167 the oscillator watchdog is always enabled For the ST10C167 and ST10R167 the oscillator watchdog is enabled by default after reset To disable the OWD set bit OWDDIS of the SYSCON register When the OWD is enabled the PLL runs on its free running frequency and increments the
350. ount direction of the core timer can be controlled either by software or by the external input pin T3EUD Timer T3 External Up Down Control Input which is the alternate input function of port pin P3 4 These options are selected by Bit T3UD and T3UDE in control register T3CON When the up down control is done by software Bit T3UDE 0 the count direction can be altered by setting or clearing Bit T3UD When T3UDE 1 pin T3EUD is selected to be the controlling source of the count direction However Bit T3UD can still be used to reverse the actual count direction as shown in the Table 21 If T3UD 0 and pin TSEUD is at low level the timer is counting up With a high level at T3EUD the timer is counting down If T3UD 1 a high level at pin T3EUD specifies counting up and a low level specifies counting down The count direction can be changed regardless of whether the timer is running or not When pin T3EUD P3 4 is used as external count direction control input it must be configured as input its corresponding direction control Bit DP3 4 must be set to 0 Table 21 GPT1 core timer T3 count direction control Count TxEUD TxUDE TxUD Direction Count Down Count Up Count Down Count Down Count Up ST10X167 Note The direction control works the same for core timer T3 and for auxiliary timers T2 and T4 Therefore the pins and Bit are named Tx Timer 3 Output Toggle Latch An
351. overflow or underflow of timer T3 will clock the toggle Bit T3OTL in control register T3CON can also be set or reset by software Bit T3OE Alternate Output Function Enable in register T3CON enables the state of T3OTL to be an alternate function of the external output pin T30UT P3 3 For that purpose a 1 must be written into port data latch P3 3 and T3OUT P3 3 must be configured as output by setting direction control Bit DP3 3 to 1 If TSOE 1 pin T30UT then outputs the state of T3OTL If T30E 0 pin T3OUT can be used as general purpose I O pin In addition TSOTL can be used in conjunction with the timer over underflows as an input for the counter function or as a trigger source for the reload function of the auxiliary timers T2 and 4 For this purpose the state of T3OTL does not have to be available at pin because an internal connection is provided for this option Timer 3 in Timer Mode Timer mode for the core timer is selected by setting Bit field T3M in register T3CON to 000b In this mode T3 is clocked with the internal system clock CPU clock divided by a programmable pre scaler which is selected by Bit field T3l The input frequency f 3 for timer and its resolution rr4 are scaled linearly with lower clock frequencies fcpy as can be seen from the following formula hse EL 8 x 203 g x 2 T3 fopu MHZ 131 294 ST10X167 Figure 65 Core tim
352. ovided to store return vectors segment pointers and processor status for procedures and interrupt routines A system register SP points to the top of the stack This pointer is decremented when data is pushed onto the stack and incremented when data is popped The internal system stack can also be used to temporarily store data or pass it between subroutines or tasks Instructions are provided to push or pop registers on from the system stack However in most cases the register banking ky ST10X167 scheme provides the best performance for passing data between multiple tasks Note The system stack allows the storage of Words only Byte must either be converted to Word or the respective other Byte must be disregarded Register SP can only be loaded with even Byte addresses The LSB of SP is always 0 Detection of stack overflow underflow is supported by two registers STKOV Stack Overflow Pointer and STKUN Stack Underflow Pointer Specific system traps Stack Overflow trap Stack Underflow trap will be entered whenever the SP reaches either boundary specified in these registers The contents of the stack pointer are compared to the contents of the overflow register whenever the SP is DECREMENTED either by a CALL PUSH or SUB instruction An overflow trap will be entered when the SP value is less than the value in the stack overflow register The contents of the stack pointer are compared to the contents of t
353. p or external events like a hardware failure or manual reset The input voltage threshold of the RSTIN pin is raised compared to the standard pins in order to minimize the noise sensitivity of the reset input Reset Output provides a special reset signal for external circuitry RSTOUT is activated at the beginning of the reset sequence triggered via RSTIN a watchdog timer overflow or by the SRST instruction RSTOUT remains active low until the EINIT instruction is executed This allows to ini tialize the controller before the external circuitry is activated XTAL1 XTAL2 Oscillator Input Output connect the internal clock oscillator to the external crystal An external clock signal may be fed to the input XTAL1 leaving XTAL2 open Vpp Vss Digital Power Supply and Ground 6 pins each provides the power supply for the digital logic of the ST10X167 All Vpp pins and all Vss pins must be connected to the power supply and ground respectively Vpp Flash Programming Voltage for ST10F167 or Exit from powerdown for ST10C167 and ST10R167 devices If a Fast External Interrupt pin EX3IN EXOIN is used to exit from Power Down mode external RC circuit should be connected to the Vpp pin The discharging of the external capacitor causes a delay that allows the oscillator and PLL circuits to stabilize before the clock signal is deliv ered to the CPU and peripherals see Figure 47 For more information on exiting power down mode refer to Chapter
354. pective external For each access the EBC compares the current Me un uuu address with all address select registers register and ignoring registers ADDRSEL1 3 programmable ADDRSELx and hardwired Gee Figure 59 XADRSx This comparison is done in four levels A match with registers ADDRSEL1 or The hardwired XADRSx registers are evaluated ADDRSEL3 directs the access to the respective first A match with one of these registers directs external area using the corresponding XBCONx the access to the respective X Peripheral using register the corresponding XBCONx register and ignoring all other ADDRSELx registers f there is no match with any XADRSx or Registers ADDRSEL2 and ADDRSEL4 are ADDRSELx register the access to the external evaluated before ADDRSEL1 and ADDRSEL3 bus uses register BUSCONO Figure 59 Address window arbitration XBCONO Active L Window BUSCON2 BUSCON4 Inactive BUSCON1 BUSCON3 Window BUSCONO Note Only the indicated overlaps are defined All other overlaps lead to erroneous bus cycles ADDRSEL4 may not overlap ADDRSEL2 or ADDRSEL1 The hardwired XADRSx registers are defined non overlapping RPOH F108h 84h SFR Reset Value XXh 15 14 13 12 11 10 9 8 7 6 5 3 1 4 2 0 T T e sasa R R R K R 122 294 ky ST10X167 WRC Write Configuration Control Set according to pin 0 during reset 0 Pins WR acts as WRL pin BHE acts
355. peed 10 5 ASCO Interrupt Control Four Bit addressable interrupt control registers are provided for serial channel ASCO Register SOTIC controls the transmit interrupt SOTBIC controls the transmit buffer interrupt SORIC controls the receive interrupt and SOEIC controls the error interrupt of serial channel ASCO Each interrupt source also has its own dedicated interrupt vector SOTINT is the transmit interrupt vector SOTBINT is the transmit interrupt vector SORINT is the receive interrupt vector and SOEINT is the error interrupt vector The cause of an error interrupt request framing parity overrun error can be identified by the error status flags in control register SOCON Note In contrary to the error interrupt request flag SOEIR the error status flags SOFE SOPE SOOE are not reset automatically upon entry into the error interrupt ser vice routine but must be cleared by soft ware Reset Value 00h 7 5 4 3 2 1 0 SORIC FF6Eh B7h 15 14 13 12 11 10 9 8 RW RW Reset Value 00h 7 5 4 3 2 1 0 T m j RW RW 163 294 ST10X167 SOEIC FF70h B8 15 14 13 12 11 10 9 8 Reset Value 00h 7 5 4 3 2 1 0 T TI T L T Em J SOTBIC F19Ch CEh 15 14 13 12 11 10 9 8 ESFR RW RW Reset Value 00h 7 5 4 3 2 1 0 TL T Note Please refer to Section 5 1 3 Interrupt Control Registers for an explanation of the
356. peripheral clocks the device resumes code execution If the Interrupt was enabled Bit CCxIE 1 in the respective CCxIC register before entering Power Down mode the device executes the interrupt service routine and then resumes execution after the PWRDN instruction see note below If the interrupt was disabled the device executes the instruction following PWRDN instruction and the Interrupt Request Flag Bit CCxIR in the respective CCxIC register remains set until it is cleared by software Note Due to internal pipeline the instruction that follows the PWRDN instruction is executed before the CPU performs a call of the interrupt service routine Figure 148 Delay with RC on Vpp pin ST10C167 R1 220 k 1MQ Typ ST10R167 Figure 149 Simplified powerdown exit circuitry enter powerdown external XTAL1 CPU clk internal Po 18 signal External Interrupt Vpp ExitPwrd internal Not applicable to ST10F167 ST10X167 Not applicable to ST10F167 stop pll stop oscillator exit weak pull down 200 LA CPU and Peripherals clocks delay for oscillator pll stabilization 255 294 ST10X167 19 4 Output Pin Status During Idle mode the CPU clocks are turned off while all peripherals continue their operation in the normal way Therefore all ports pins which are configured as general purpose output pins output the last data value which was written to their port output
357. plication this non Bit addressable register represents the high order 16 Bit of the 32 Bit result For long divisions the MDH register must be loaded with the high order 16 Bit of the 32 Bit dividend before the division is started After any division register MDH represents the 16 Bit remainder MDH FEOCh 06h SFR ResetValue 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW Specifies the high order 16 Bit of the 32 Bit multiply and divide register MD 52 294 ky ST10X167 Whenever this register is updated via software the Multiply Divide Register In Use MDRIU flag in the Multiply Divide Control register is set to 1 When a multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed within the interrupt service routine register MDH must be saved along with registers MDL and MDC to avoid erroneous results A detailed description of how to use the MDH register for programming multiply and divide algorithms can be found in Chapter 21 System Programming 4 4 11 The Multiply Divide Low Register MDL This register is a part of the 32 Bit multiply divide register which is implicitly used by the CPU when it performs a multiplication or a division After a multiplication this non Bit addressable register represents the low order 16 Bit of the 32 Bit result For long divisions the MDL register must be loaded with the low order 16 Bit of the 32 Bit dividend b
358. pplication In all cases the ST10X167 will still run in BSL mode that means with the watchdog timer disabled and limited access to the internal ROM area All code fetches from the internal ROM area 00 0000h 00 7FFFh or 01 0000h 01 7FFFh if mapped to segment 1 are redirected to the special Boot ROM Data fetches access will access the internal Boot ROM of the ST10X167 if any is available but will return undefined data on ROMIess devices Exiting Bootstrap Loader Mode In order to execute a program in normal mode the BSL mode must be terminated first The ST10X167 exits BSL mode upon a software reset ignores the level on POL 4 or a hardware reset POL 4 must be high After a reset the ST10X167 will start executing from location 00 0000h of the internal ROM the external memory as programmed via pin EA 181 294 ST10X167 Choosing the Baud rate for the BSL The calculation of the serial Baud rate for ASC0 from the length of the first zero Byte that is received allows the operation of the bootstrap loader of the ST10X167 with a wide range of Baud rates However the upper and lower limits have to be kept in order to insure proper data transfer cPU BsT10X167 32 x SOBRL 1 The ST10X167 uses timer T6 to measure the length of the initial zero Byte The quantization uncertainty of this measurement implies the first deviation from the real Baud rate the next deviation is implied by the computation of the SOB
359. previous data is still being transmitted As shown in the Figure 92 SOTBIR is an early trigger for the reload routine while SOTIR indicates the completed transmission Software using handshake therefore should rely on SOTIR at the end of a data block to make sure that all data has really been transmitted ST10X167 11 HIGH SPEED SYNCHRONOUS SERIAL INTERFACE The High Speed Synchronous Serial Interface SSC provides flexible high speed serial communication between the ST10X167 and other microcontrollers microprocessors or external peripherals The SSC supports full duplex and half duplex synchronous communication The serial clock signal can be generated by the SSC itself master mode or be received from an external master slave mode Data width shift direction clock polarity and phase are programmable This allows communication with SPl compatible devices Transmission reception of data is double buffered A 16 Bit Baud rate generator provides the SSC with a separate serial clock signal The high speed synchronous serial interface can be configured in three ways it can be used with other synchronous serial interfaces the ASCO insynchronous mode or configured in like master slave or multimaster interconnections or operate like the popular SPI interface It can communicate with shift registers I O expansion peripherals EEPROMs etc or other controllers networking The SSC supports half duplex and full
360. purposes They incorporate five 16 Bit timers that are grouped into the two timer blocks GPT1 and GPT2 Block GPT1 contains 3 timers counters with a maximum resolution of 8 CPU clock cycles while block GPT2 contains 2 timers counters with a maximum resolution of 4 CPU clock cycles and a 16 Bit Capture Reload register CAPREL Each timer in each block may operate independently in a number of different modes such as gated timer or counter mode or may be concatenated with another timer of the same block The auxiliary timers of GPT1 may optionally be configured as reload or as capture registers for the core timer In the GPT2 block the additional CAPREL register supports capture and reload operation with extended functionality and its core timer T6 may be concatenated with timers of the CAPCOM units T0 T1 T7 and T8 Each block has alternate input output functions and specific interrupts associated with it 9 1 Timer Block GPT1 From a programmer s point of view the GPT1 block is composed of a set of SFRs Those portions of port and direction registers which are used for alternate functions by the GPT1 block are named by Y in Figure 63 All three timers of block GPT1 T2 T3 T4 can run in 3 basic modes timer gated timer and counter mode and all timers can count either up 128 294 or down Each timer has an associated alternate input function pin on Port3 which serves as the gate control in gated timer mode or as t
361. r 8 1 Single Chip Mode Single chip mode is entered when pin EA is high during reset In this case register BUSCONO is initialized with 0000h which also resets Bit BUSACTO so no external bus is enabled In single chip mode the ST10X167 operates only with and out of internal resources No external bus is configured and no external peripherals and or memory can be accessed Also no port lines are occupied for the bus interface When running in single chip mode however external access may be enabled by configuring an external bus under software control Single chip mode allows the ST10X167 to start execution out of the internal program memory Masked ROM Flash Memory Any attempt to access a location in the external memory space in single chip mode results in the hardware trap ILLBUS ST10X167 Figure 48 SFRs and port pins associated with the external bus interface Ports amp Direction Control Alternate Functions 15141312111098 76543210 Y Y Y Y YYYYYYYYYYY PIL PIH Y Y YYYYYYYYYYYYY Y Y P3 S uM anis P4 YYYYYYYYYYYYYYYY ODP6E V YY YY YYYYYYYYYYY DP6 YYYYYYYYYYYYYYYY YYYYYYYYYYYYYYYY Address Registers 15141312111098 76543210 POL POH PORTO Data Registers P1L P1H PORT1 Data Registers DP3 Port3 Direction Control Register P3 Port3 Data Register P4 Port4 Data Register Port6 Open Drain Control Register Port6 Direction Control Register P6 Port 6 Data Register ADDRSELx Address Range
362. r bank is growing upwards Figure 152 Local registers Newly Allocated Register Bank Old CP Contents im The software to provide the local register bank for the example above Figure 152 is very compact After entering the subroutine SUB SP 10D Free 5 Words in the current system stack SCXT CP SP Set th Before exiting the subroutine POP CP ADD SP 10D new register bank pointer Restore the old register bank Release the 5 Word of the current system stack 279 294 ST10X167 21 4 Table Searching A number of features have been included to decrease the execution time required to search tables First branch delays are eliminated by the branch target cache after the first iteration of the loop Second in non sequentially searched tables the enhanced performance of the ALU allows more complicated hash algorithms to be processed to obtain better table distribution For sequentially searched tables the auto increment indirect addressing mode and the E end of table flag stored in the PSW decrease the number of overhead instructions executed in the loop The two examples below illustrate searching ordered tables and non ordered tables respectively OV RO BASE Move table base into RO LOOP CMP R1 RO Compare target to table entry JMPR SGT LOOP Test whether target has not been found The last entry in the table must be greater than the largest possible target OV
363. r realized through special programming see Section 4 1 4 Particular Pipeline Effects Protected Bit As mentioned in Section 2 6 Protected Bits hardware set are not modified during a read modify write sequence even if an interrupt request rises between read and write time The hardware protection logic guarantees that only the intended Bit s is are effected by the write back operation Note If a conflict occurs between a Bit manipu lation generated by hardware and an intended software access the software access has priority and determines the final value of the respective Bit See Sec tion 2 6 Protected Bits ky 4 3 Instruction Execution Times Instruction execution time depends on where the instruction is fetched from and where operands are read from or written to When a program is fetched from internal memory most of the instructions can be processed in one instruction cycle All external memory accesses are performed by the on chip External Bus Controller EBC which works in parallel with the CPU This section summarizes the execution times A detailed description of the execution times for the various instructions and the specific exceptions can be found in the ST10 Family Programming Manual Table 5 shows the minimum execution times required to process a ST10X167 instruction fetched from the internal ROM the internal RAM or from external memory The values are in CPU clock cycles and assume no wait
364. r s low Byte prepares for software initialization ST10X167 busoff 1 and init 1 Bit0 error 1 wait end of recovery Software Initialization The Software Initialization is enabled by setting Bit INIT in the Control Register This can be done by the CPU via software or automatically by the CAN controller on a hardware reset or if the EML switches to busoff state While INIT is set All message transfer from and to the CAN bus is stopped The CAN bus output recessive The control Bit NEWDAT and RMTPND of the last message object are reset The counters of the EML are left unchanged Setting Bit CCE in addition allows changing the configuration in the Bit Timing Register To initialize the CAN Controller the following actions are required CAN TxD is 1 Configure the Bit Timing Register CCE required Set the Global Mask Registers nitialize each message object 239 294 ST10X167 If a message object is not needed it is sufficient to clear its message valid Bit MSGVAL so it is defined as not valid Otherwise the whole message object has to be initialized After the initialization sequence has been completed the CPU clears the INIT Bit To change the configuration of a message object during normal operation the CPU first clears Bit MSGVAL which defines it as not valid When the configuration is completed MSGVAL is set again Accessing the On chip CAN Mo
365. ration The address areas defined via registers ADDRSELx may overlap internal address areas Internal accesses will be executed in this case ky Notes 4 Default configuration LX4 LX4 LX4 Direct drive 1 1 CPU clock via prescaler 2 1 For any access to an internal address area the EBC will remain inactive see EBC Idle State 8 5 EBC Idle State When the external bus interface is enabled but no external access is currently executed the EBC is idle As long as only internal resources from an architecture point of view like IRAM GPRs or SFRs etc are used the external bus interface does not change see Table 20 Accesses to on chip X Peripherals are also controlled by the EBC However even though an X Peripheral appears like an external peripheral to the controller the respective accesses do not generate valid external bus cycles Due to timing constraints address and write data of an XBUS cycle are reflected on the external bus interface see Table 20 The address mentioned above includes Port1 Port 4 BHE and ALE which also pulses for an XBUS cycle The external CS signals on Port 6 are driven inactive high because the EBC switches to an internal XCS signal 123 294 ST10X167 The external control signals RD and WR or WRLANRH if enabled remain inactive high see Table 20 Table 20 Status of the external bus interface during EBC idle state Pin
366. re 143 18 1 3 Asynchronous Hardware Reset Note This feature does not exist for the ST10F167 device Asynchronous hardware reset must be used for power on reset of ST10C167 and ST10R167 Asynchronous reset is invoked by asserting RSTIN and forcing Vpp low While the RSTIN pin is asserted a weak internal pull down is turned on the Vpp pin When an asynchronous reset is initiated the microcontrol ler is immediately asynchronously reset into its predefined default state and therefore does not require a stabilized clock signal on XTAL1 pin When this asynchronous reset condition is removed the microcontroller starts program exe cution from memory location 00 0000h in code segment zero RSTIN pin must be held low for the whole duration of the circuit internal reset sequence once the input clock is stabilised and once the PLL synchronised For application using exit from power down by external interrupt this mode is detected by the ST10 during power up Constraints on reset duration on the RSTIN pin are the same as for synchronous reset 1ms for PLL 10 to 50 ms for on chip oscillator ky ST10X167 18 1 4 Software Reset The reset sequence can be triggered at any time by the protected instruction SRST Software Reset This instruction can be executed deliberately within a program e g to leave bootstrap loader mode or upon a hardware trap that reveals a system failure Note A software reset disregards the conf
367. re and is stopped PTRx 0 either via hardware or software depending on its operating mode Control Bit PTRx enables or disables the clock input of counter PTx rather than controlling the PWM output signal Note For the register locations please refer to Table 33 This table summarizes the PWM frequencies that result from various combinations of operating mode counter resolution input clock and pulse width resolution Period Registers PPx The 16 Bit period register PPx of a PWM channel determines the period of a PWM cycle and the frequency of the PWM signal This register is buffered with a shadow register The shadow register is loaded from the respective PPx register at the beginning of every new PWM cycle or upon a write access to PPx while the timer is stopped The CPU accesses the PPx register while the hardware compares the contents of the shadow register with the contents of the associated counter PTx When a match is found between counter and PPx shadow register the counter is either reset to 0000h or the count direction is switched from counting up to counting down depending on the selected operating mode of that PWM channel For the register locations refer to the Table 34 12 Bit PWM resolution 14 Bit PWM resolution 16 Bit PWM resolution fopu Mode 0 28 fopu 2 fopu 2 fopu 2 4 fopu 2 8 fopu 64 0 J 64x28 fopu 64x2 0 fopu 64x2 fopu 64x2 4 fopu 64x2 6 fopu Model u2x
368. res ervo CS1 CS0 mestre Three CS2 CS0 Note The selected number of CS signals cannot be changed via software after reset Segment address lines Pins POH 4 and POH 3 SALSEL define the number of active segment address lines during reset This determines which pins of Port4 are used as address line or as I O line The two Bit are latched in register RPOH Depending on the system architecture the required address space is chosen and accessible right from the start so the initialization routine can directly access all locations without prior programming P0 15 13 P0H 7 5 ST10C167 ST10R167 fopu X F ST10X167 The required pins of Port4 are automatically switched to address output mode Segment Address Lines Directly accessible SALSEL Address Space 11 Two A17 A16 256K Byte Default without pull downs Eight A23 A16 16M Byte Maximum Byie Ninimum 00 19 16 1M Byte Even if not all segment address lines are enabled on Port4 the ST10X167 internally uses its complete 24 Bit addressing mechanism This allows the restriction of the width of the effective address bus while still deriving CS signals from the complete addresses Default 2 Bit segment address A17 A16 allowing access to 256K Byte Note The selected number of segment address lines cannot be changed via software after reset Clock generation control Pins POH 7 POH 6 and POH 5
369. ress Select Register 4 0000h ADEIC b FF9Ah CDh A D Converter Overrun Error Interrupt Control Reg 0000h BUSCONO b FFOCh 86h Bus Configuration Register 0 OXXOh BUSCON1 b FF14h 8Ah Bus Configuration Register 1 0000h BUSCON2 b FF16h 8Bh Bus Configuration Register 2 0000h BUSCONS b FF18h 8Ch Bus Configuration Register 3 0000h BUSCONA b FF1Ah 8Dh Bus Configuration Register 4 0000h CAPREL FE4Ah GPT2 Capture Reload Register 0000h CC8IC b FF88h C4h EXOIN Interrupt Control Register 0000h CC0 FE80h CAPCOM Register 0 0000h CCOIC b FF78h CAPCOM Register 0 Interrupt Control Register 0000h CC1 FE82h CAPCOM Register 1 0000h CC1IC b FF7Ah CAPCOM Register 1 Interrupt Control Register 0000h CC2 FE84h CAPCOM Register 2 0000h CC2IC b FF7Ch CAPCOM Register 2 Interrupt Control Register 0000h CC3 FE86h CAPCOM Register 3 0000h CC3IC b FF7Eh CAPCOM Register 3 Interrupt Control Register 0000h CC4 FE88h CAPCOM Register 4 0000h CC4IC b FF80h CAPCOM Register 4 Interrupt Control Register 0000h CC5 FE8Ah CAPCOM Register 5 0000h CC5IC b FF82h CAPCOM Register 5 Interrupt Control Register 0000h CC6 FE8Ch CAPCOM Register 6 0000h CC6IC b FF84h CAPCOM Register 6 Interrupt Control Register 0000h 7 FE8Eh CAPCOM Register 7 0000h CC7IC b FF86h CAPCOM Register 7 Interrupt Control Register 0000h 3 259 294 ST10X167 Table 43 Special function registers ordered by name continued Physical 8 bit inti Reset CC8 FE90h CAPCOM Register 8 0000h CC8IC b FF88
370. ress calculation is identical to that for the short 4 Bit GPR addresses For single Bit accesses on a GPR the GPR s Word address is calculated as just register CP described but the position of the Bit within the Word is specified by a separate additional 4 Bit value Figure 16 Register bank selection via register CP Internal RAM CP 30 CP 28 Context Pointer Figure 17 Implicit CP use by short GPR addressing modes Specified by register or Bitoff Context Pointer Control For Byte GPR accesses 50 294 1111 4 Bit GPR Address Internal Must be within the internal RAM area For Word GPR accesses ST10X167 4 4 7 The Stack Pointer SP This non Bit addressable register is used to point to the top of the internal system stack TOS The SP register is pre decremented whenever data is to be pushed onto the stack and it is post incremented whenever data is to be popped from the stack Thus the system stack grows from higher toward lower memory locations Since the least significant Bit of register SP is tied to 0 and Bit 15 through 12 are tied to 1 by hardware the SP register can only contain values from F000h to FFFEh This allows to access a physical stack within the internal RAM of the MCU A virtual stack usually bigger can be realized via software This mechanism is supported by registers STKOV and STKUN see respective descript
371. rflow flag V is set if the result from a multiply or divide instruction is greater than 16 Bit This flag can be used to determine whether both Word halves must be transferred from register MD The high portion of register MD MDH must be moved into the register file or memory first in order to ensure that the MDRIU flag reflects the correct state 273 294 ST10X167 The following instruction sequence performs an unsigned 16 by 16 Bit multiplication SAVE JNB MDRIU START Test if MD was in use SCXT MDC 0010H Save and clear control register leaving MDRIU set only req for interrupted multiply divide instructions 5 SAVED Indicate the save operation PUSH MDH Save previous MD contents PUSH MDL system stack START MULU R1 R2 Multiply 16 16 unsigned Sets MDRIU JMPR cc NV COPYL Test for only 16 Bit result MOV R3 MDH Move high portion of MD COPYL MOV R4 DL Move low portion of MD Clears MDRIU RESTORE JNB SAVED DONE Test if MD registers were saved POP MDL Restore registers POP MDH POP MDC BCLR SAVED Multiplication is completed program continues DONE The above save sequence and the restore sequence after COPYL are only required if the current routine could have interrupted a previous routine which contained a MUL or DIV instruction Register MDC is also saved because it
372. rise during run time so called Hardware Traps Hardware traps cause an immediate non maskable system reaction which is similar to a standard interrupt service branching to a dedicated vector table location The occurrence of a hardware trap is additionally signified by an individual Bit in the trap flag register TFR Except for another higher prioritized trap service being in progress a hardware trap will interrupt any current program execution In turn hardware trap services can normally not be interrupted by standard or PEC interrupts Software interrupts are supported by means of the TRAP instruction in combination with an individual trap interrupt number 2 3 On chip System Resources The ST10X167 controllers provide a number of powerful system resources designed around the CPU The combination of CPU and these resources results in the high performance of the members of this controller family 2 3 1 Peripheral Event Control and Interrupt Control The Peripheral Event Controller makes it possible to respond to an interrupt request with a single data transfer Word or Byte which only consumes one instruction cycle and does not require a save and restore of the machine status Each interrupt source is prioritized in every instruction cycle in the interrupt control block If a PEC service is selected a PEC transfer is started If CPU interrupt service is requested the current CPU priority level stored in the PS
373. rity over every other CPU activity If several hardware trap conditions are detected within the same instruction cycle the highest priority trap is serviced see Section 5 1 Interrupt System Structure PSW CSP in segmentation mode and IP are pushed on the internal system stack and the CPU level in register PSW is set to the highest possible priority level level 15 disabling all interrupts The CSP is set to code segment zero if segmentation is enabled A trap service routine must be terminated with the RETI instruction The eight hardware trap functions of the ST10X167 are divided into two classes Class A traps These traps share the same trap priority but have an individual vector address External Non Maskable Interrupt NMI Stack Overflow Stack Underflow trap Class B traps These traps share the same trap priority and the same vector address Undefined Opcode Protection Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Trap The bit addressable Trap Flag Register TFR allows a trap service routine to identify the kind of trap which caused the exception Each trap function is indicated by a separate request flag When a hardware trap occurs the corresponding request flag in register TFR is set to 1 71 294 ST10X167 TFR FFACh D6h 14 STK OF RW 11 10 15 RW ILLBUS External Bus Access Flag B
374. rmine the cause of the interrupt request The Interrupt Identifier INTID a number in the Interrupt Register indicates the cause of an interrupt When no interrupt is pending the identifier will have the value 00h If the value in INTID is not 00h then there is an interrupt pending If Bit IE in the Control Register is set also the interrupt line to the CPU is activated The interrupt line remains active until either INTID gets OOh after the interrupt requester has been serviced or until IE is reset if interrupts are disabled The interrupt with the lowest number has the highest priority If a higher priority interrupt lower number occurs before the current interrupt is processed INTID is updated and the new interrupt overrides the last one The Table 36 lists the valid values for INTID and their corresponding interrupt sources Reset Value XXh 7 6 5 4 3 2 1 0 RESERVED INTID Interrupt Identifier This number indicates the cause of the interrupt When no interrupt is pending the value will be 00 225 294 ST10X167 Table 36 INTID values and Corresponding Interrupt Sources INTID Cause of the Interrupt o Interrupt Idle There is interrupt request pending Status Change Interrupt The CAN controller has updated not necessarily changed the status in the Control Register This can refer to a change of the error status of the CAN controller EIE is set and BOFF or EWRN change or to a CAN transfer i
375. rmore be used to clock one or more of the timers of the CAPCOM units which gives the user the possibility to set compare events based on a finer resolution than that of the external events Figure 86 GPT2 register CAPREL in capture and reload mode Up Down Input Edge Select CAPIN P3 2 Clock Auxiliary Timer T5 T5IR A Interrupt Request Interrupt Request T6OUT Up Down T6OE P3 1 Interrupt Request To CAPCOM Timers TO T1 T7 153 294 ST10X167 9 2 2 Interrupt Control for GPT2 Timers and CAPREL When a timer overflows from FFFFh to 0000h when counting up or when it underflows from 0000h to FFFFh when counting down its interrupt request flag T5IR or T6IR in register TxIC will be set Whenever a transition according to the selection in Bit field Cl is detected at pin CAPIN interrupt request flag CRIR in register CRIC is set Setting any request flag will cause an interrupt to the respective timer or CAPREL interrupt vector T5INT T6INT or CRINT or trigger a PEC service if the respective interrupt enable Bit T5IE or T6IE in register TxIC CRIE in register CRIC is set There is an interrupt control register for each of the two timers and for the CAPREL register T5IC FF66h B3h SFR Reset Value 00h 15 14 13 12 11 10 9 5 4 3 2 1 0 8 7 6 w T ex RW RW RW RW T6IC FF68h B4h SFR Reset Value 00
376. rogrammed to compare mode 1 and the corresponding bank 2 register see Table 31 must be programmed to compare mode 0 If the respective bank 1 compare register is disabled or programmed for a mode other than mode 1 the corresponding bank 2 register will operate in compare mode 0 interrupt only mode In the following a bank 2 register programmed to compare mode 0 will be referred to as CCz while the corresponding bank 1 register programmed to compare mode 1 will be referred to as CCx When a match is detected for one of the two registers in a register pair CCx or CCz the associated interrupt request flag CCxIR or ST10X167 CCzIR is set to 1 and pin CCxIO corresponding to bank 1 register CCx is toggled The generated interrupt always corresponds to the register that caused the match Note If match occurs simultaneously for both register CCx and register CCz of the register pair pin CCxIO will be tog gled only once but two separate com pare interrupt requests will be generated one for vector CCxINT and one for vector CCzINT In order to use the respective port pin as compare signal output pin for compare register CCx in double register compare mode this port pin must be configured as output and the corresponding direction control Bit must be set to 1 With this configuration the output pin has the same characteristics as in compare mode 1 Figure 114 Double register compare mode block
377. rom the instruction decode logic The core improvements are summarized below and described in detail in the following sections 1 High instruction bandwidth fast execution 2 High function 8 Bit and 16 Bit arithmetic and logic unit 3 Extended Bit processing and peripheral control 4 High performance branch call processing and loop Consistent and optimized instruction formats Programmable structure multiple priority interrupt 2K Byte Internal RAM Oscillator PLL Oscillator Watchdog External Bus 16 Bc el Controller C SO Port4 DS lt 16 Jac i p 13 294 ST10X167 Figure 2 CPU Block Diagram Internal RAM MDH 2K Byte MDL 128K Byte Flash 32K Byte Multiplication Division Hardware ROM C Bit Mask where Generator Execution Unit General Purpose applicable Instruction Pointer 4 Stage Pipeline 16 Bit Registers PSW Barrel Shift SYSCON BUSCON 0 BUSCON 1 ADDRSEL 1 BUSCON 2 ADDRSEL 2 BUSCON 3 ADDRSEL 3 BUSCON 4 ADDRSEL 4 Data Page Pointers Code Segment Pointer 2 1 1 High Instruction Bandwidth Fast Execution Most of the ST10X167 s instructions are executed
378. rom the respective vector location which is expected to branch to the service routine itself The data page pointers and the context pointer are not affected When the interrupt service routine is left RETI is executed the status information is popped from the system stack in the reverse order taking into account the value of bit SGTDIS 5 4 1 Context Switching An interrupt service routine usually saves all the registers it uses on the stack and restores them before returning The more registers a routine uses the more time is wasted with saving and restoring The ST10X167 allows to switch the complete bank of CPU registers GPRs with a single instruction so the service routine executes within its own separate context The instruction SCXT CP New_Bank pushes the content of the context pointer CP on the system stack and loads CP with the immediate value New Bank which selects a new register bank The service routine may now use its own registers This register bank is preserved when the service routine terminates its contents are available on the next call Before returning RETI the previous CP is simply POPped from the system stack which returns the registers to the original bank Note The first instruction following the SCXT instruction must not use a GPR Resources that are used by the interrupting program must eventually be saved and restored the DPPs and the registers of the MUL DIV unit 5
379. rrupt Handling The on chip CAN Module has one interrupt output which is connected through a synchronization stage to a standard interrupt node in the ST10X167 in the same manner as all other interrupts of the standard on chip peripherals The control register for this interrupt is XPOIC located at address F186h C3h in the ESFR range The associated interrupt vector is called XPOINT at location 100h trap number 40h With this configuration the user has all control options available for this interrupt such as enabling disabling level and group priority and interrupt or PEC service see note below As for all other interrupts the interrupt request flag XPOIR in register XPOIC is cleared automatically by hardware when this interrupt is serviced either by standard interrupt or PEC service Note As a rule CAN interrupt requests can be serviced by a PEC channel However because PEC channels only can execute single predefined data transfers there are no conditional PEC transfers PEC service Interrupt Register EFO2h 15 14 13 12 11 10 9 8 XReg can only be used if the respective request is known to be generated by one specific source and that no other interrupt request will be generated in between In practice this seems to be a rare case Since an interrupt request of the CAN Module can be generated due to different conditions the appropriate CAN interrupt status register must be read in the service routine to dete
380. rs When a timer overflows from FFFFh to 0000h when counting up or when it underflows from 0000h to FFFFh when counting down its interrupt request flag T2IR T3IR or T4IR in register TxIC will be set This will cause interrupt to the respective timer interrupt vector T2INT T3INT or T4INT or trigger PEC service if the respective interrupt enable Bit T2IE or T4IE in register TxIC is set There is an interrupt control register for each of the three timers Reset Value 00h 15 14 13 12 11 10 9 5 4 3 2 1 0 8 7 6 TIT T T T To enr RW RW RW RW Note The direction control Bit DP3 7 for T2IN and DP3 5 for T4IN must be set to 0 and the level of the capture trigger signal should be held high or low for at least 8 CPU clock cycles before it changes to ensure correct edge detection T2IC FF60h B0h SFR T3IC FF62h B1h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW TAIC FF64h B2h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 is RW RW RW RW Note Please refer to the general Interrupt Control Register description for an explanation of the control fields 142 294 ky 9 2 Timer Block GPT2 From a programmer s point of view the GPT2 block is represented by a set of SFRs The I O of port and direction registers which are used for alternate functions by the GPT2 block are noted Y in Figure 77
381. rs for data transfers on the eight PEC channels Each channel uses a pair of pointers stored in two subsequent Word locations with the source pointer SRCPx on the lower and the destination pointer DSTPx on the higher Word address x 7 0 see Figure 7 Whenever a PEC data transfer is performed the pair of source and destination pointers selected by the specified PEC channel number is accessed independently of the current DPP register contents The locations referred to by these pointers are accessed independently of the current DPP register contents If a PEC channel is not used the corresponding pointer locates the area available and can be used for Word or Byte data storage For more details about the use of the source and destination pointers for PEC data transfers see Chapter 21 System Programming Figure 7 Location of the PEC pointers 00 FDOOh 00 FCFEh DSTP7 00 FCFEh 00 FCFCh SRCP7 00 FCEOh Internal PEC RAM source amp destination pointers 00 FCE2h 00 FCE0h 00 F600h 00 F5FEh 3 2 4 Special Function Registers The functions of the CPU the bus interface the I O ports and the on chip peripherals of the ST10X167 are controlled via a number of so called Special Function Registers SFRs These SFRs are arranged within two areas each of 512 Byte size The first register block is called the SFR area and is located in the 512 Byte above the internal
382. rst mode for any PWM channel Software Control of the PWM Outputs In an application the PWM output signals are generally controlled by the PWM module However it may be necessary to influence the level of the PWM output pins via software either to initialize the system or to react on some Figure 122 PWM output signal generation L PENxPBo1 J 210 294 extraordinary condition like a system fault or an emergency Clearing the timer run Bit PTRx stops the associated counter and leaves the respective output at its current level The individual PWM channel outputs controlled by comparators according to the formula PWM output signal PTx gt PWx shadow latch So whenever software changes registers PTx the respective output will reflect the condition after the change Loading timer PTx with a value greater than or equal to the value in PWx immediately sets the respective output a PTx value below the PWXx value clears the respective output By clearing or setting the respective Port7 output latch the PWM channel signal is driven directly or inverted to the port pin Clearing the enable Bit PENx disconnects the PWM channel and switches the respective port pin to the value in the port output latch Note To prevent further PWM pulses from occurring after such a software interven tion the respective counter must be stopped first Latch P7 3 Pin P7 3 Latch P7 2 Pin P7 2 Latch P7 1 Pi
383. rt 06 15 14 13 12 11 10 9 ud compare the message s identifier in the respective Bit position The last message object 15 has an additional individually programmable acceptance mask Mask of Last Message for the complete arbitration field This allows classes of messages to be received in this object by masking some Bit of the identifier Note The Mask of Last Message is ANDed with the Global Mask that corresponds to the incoming message Reset Value UFUUh 3 1 O ID28 18 Identifier 11 Bit Mask to filter incoming messages with standard identifier Upper Global Mask Long EF08h XReg Reset Value UUUUh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW ky 227 294 ST10X167 Lower Global Mask Long EF0Ah XReg Reset Value UUUUh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 o o o o ma 1 RW R R R RW Identifier 29 Bit Mask to filter incoming messages with extended identifier Upper Mask of Last Message EFOCh XReg Reset Value UUUUh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID20 18 ID28 21 RW RW RW Lower Mask of Last Message EFOEh XReg Reset Value UUUUh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID4 0 1012 5 RW R R R RW Identifier 29 Bit Mask to filter the last incoming message Nr 15 with standard or extended identifier as configured 17 4 The Message Object The Table 37 shows how to use and to interpret these 2 Bit fields The message object is the primary
384. rts synchronizing with the external clock signal as soon as it is available Within 1ms after stable oscillations of the external clock within the specified frequency range the PLL will be synchronous with this clock at a frequency of F x fxrAL and the PLL locks to the external clock Note Ifthe ST10X167 is required to operate on the desired CPU clock directly after reset make sure that RSTIN remains active until the PLL has locked approx 1ms The PLL constantly synchronizes to the external clock signal Due to the fact that the external frequency is 1 F th of the PLL output frequency the output frequency may be slightly higher or lower than the desired frequency This jitter is irrelevant for longer time periods For short periods 1 4 CPU clock cycles it remains below 4 When the PLL detects that it is no longer locked no longer stable it generates an interrupt request PLL Unlock interrupt node This occurs when the input clock is unstable and especially when the input clock fails completely for example due to a broken crystal In this case the synchronization mechanism will reduce the PLL output frequency down to the PLLs basic frequency 2 5 MHz The basic frequency is still generated and allows the CPU to execute emergency actions in case of a loss of the external clock 2 4 2 Prescaler Operation When pins POH 7 5 001 during reset the CPU clock is derived from the internal
385. ruction passes through the decode stage of the pipeline for the first time provided that the jump condition is met the jump target instruction is fetched as usual causing a time delay of one instruction cycle If the instruction is repeated in a loop the target instruction JMPA JMPR JB JBC JNB JNBS is additionally stored in the cache For execution of the repeated cache jump instruction the jump target instruction is not fetched from program memory but taken from the cache and immediately injected into the decode stage of the pipeline see Figure 12 A time saving jump on cache is always taken after the second and any further occurrence of the same cache jump instruction unless instruction which has the fundamental capability of changing the CSP register contents JMPS CALLS RETS TRAP RETI or any standard interrupt has been processed during the period of time between two following occurrences of the same cache jump instruction Injection cycle Y BRANCH ITARGET 1 2 TARGET 3 DECODE BRANCH insect 1 TARGET 2 36 294 Figure 12 Cache jump instruction pipelining gt 1 instruction cycle Injection DECODE EXECUTE WRITEBACK 1st loop iteration 4 1 4 Particular Pipeline Effects Since up to four different instructions are processed simultaneously additional hardware has been included in the ST10X167 to take in
386. ry with the advantage of a flexible adaptable software system Enabling and Disabling the Internal ROM Area After Reset If the internal ROM does not contain an appropriate start up code the system may be booted from external memory while the internal ROM is enabled afterwards to provide access to library routines tables etc If the internal ROM only contains the start up code and or test software the system may be booted from internal ROM which may then be disabled after the software has switched to executing from external memory in order to free the address space occupied by the internal ROM area which is now unnecessary 21 11 Pits Traps and Mines Although handling the internal ROM or Flash provides powerful means to enhance the overall performance and flexibility of a system extreme ST10X167 care must be taken in order to avoid a system crash Instruction memory is the most crucial resource for the ST10X167 and it must be made sure that it never runs out of it The following precautions help to take advantage of the methods mentioned above without jeopardizing system security Internal ROM access after reset When the first instructions are to be fetched from internal ROM EA 1 the memory must contain a valid reset vector and valid code at its destination Mapping the internal ROM to segment 1 Due to instruction pipelining any new ROM mapping will at the earliest become valid for the second instruc
387. s Internal accesses only XBUS accesses PORTO Tristate floating Tristate floating for read accesses PORT1 Last used external address Last used XBUS address if used for the bus interface if used for the bus interface Port4 Last used external segment address Last used XBUS segment address on selected pins on selected pins Port6 Active external CS signal corresponding to last Inactive high for selected CS signals used address Rb maneno 1700 8 6 External Bus arbitration In high performance systems it may be efficient to share external resources like memory banks or peripheral devices among more than controller The ST10X167 supports this approach with the possibility to arBitrate the access to its external bus and to the external devices This bus arbitration allows an external master to request the ST10X167 s bus via the HOLD input The ST10X167 acknowledges this request via the HLDA output and will float its bus lines in this case The CS outputs provide internal pull up devices The new master may now access the peripheral devices or memory banks via the same interface lines as the ST10X167 During this time the ST10X167 can keep on executing as long as it does not need access to the external bus All actions that just require internal resources like instruction or data memory and on chip peripherals may be executed in parallel When the ST10X167 needs access to its external bus while it i
388. s stolen from the current CPU activity to perform a PEC service Multiple Priority Interrupt Controller This controller allows all interrupts to be placed at any specified priority Interrupts may also be grouped which provides the user with the ability to prevent similar priority tasks from interrupting each other For each of the possible interrupt sources there is a separate control register which contains an interrupt request flag an interrupt enable flag and an interrupt priority Bitfield Once having been accepted by the CPU an interrupt service can only be interrupted by a higher prioritized service request For standard interrupt processing each of the possible interrupt sources has a dedicated vector location Multiple Register Banks This feature allows the user to specify up to sixteen general purpose registers located anywhere in the internal RAM A single one instruction cycle instruction is used to switch register banks from one task to another Interruptible Multiple Cycle Instructions Reduced interrupt latency is provided by allowing multiple cycle instructions multiply divide to be interruptible With an interrupt response time within a range from just 250ns to 500ns in case of internal program execution the ST10X167 is capable of fast reaction to non deterministic events ky The ST10X167 also provides an excellent mechanism to identify and to process exceptions or error conditions that a
389. s the value 1 is written to the port output latch via the line Alternate Data Output When an overflow of the corresponding timer occurs a 0 is written to the port output latch In both cases the output latch is clocked by the signal Compare Trigger The Table 11 Port2 alternate functions ST10X167 direction of the pin should be set to output by the user otherwise the pin will be the high impedance state and will not reflect the state of the output latch As can be seen from the port structure Figure 31 the user software always has free access to the port pin even when it is used as a compare output This is useful for setting up the initial level of the pin when using compare mode 1 or the double register mode In these modes unlike in compare mode 3 the pin is not set to a specific value when a compare match occurs but is toggled instead When the user wants to write to the port pin at the same time a compare trigger tries to clock the out put latch the write operation of the user software has priority Each time a CPU write access to the port output latch occurs the input multiplexer of the port output latch is switched to the line con nected to the internal bus The port output latch will receive the value from the internal bus and the hardware triggered change will be lost As all other capture inputs the capture input func tion of pins P2 15 P2 0 can also be used as external interrupt inputs
390. s cleared on a capture Timer 5 Capture Mode Enable T5SC 0 Capture into register CAPREL Disabled T5SC 1 Capture into register CAPREL Enabled Note 1 For the effects of Bit TXUD and TxUDE refer to the direction Table 26 ky 149 294 ST10X167 Count Direction Control for Auxiliary Timer The count direction of the auxiliary timer can be controlled in the same way as for the core timer T6 The description and the table apply accordingly Timer T5 in Timer Mode or Gated Timer Mode When the auxiliary timer T5 is programmed to timer mode or gated timer mode its operation is the same as described for the core timer T6 The descriptions figures and tables apply accordingly with one exception There is no output toggle latch and no alternate output pin for T5 Timer T5 in Counter Mode Counter mode for the auxiliary timer T5 is selected by setting Bit field T5M in register T5CON to 001b In counter mode timer 5 can be clocked either by a transition at the external input pin T5IN or by a transition of timer T6 s output toggle latch T6OTL The event causing an increment or decrement of the timer can be a positive a negative or both a positive and a negative transition at either the input pin or at the toggle latch T6OTL see Figure 82 Bit field in control register T5CON selects the triggering transition see Table 29 Note Only state transitions of TGOTL which are caused by the overflow
391. s increases the interrupt response time due to pipeline related access priorities The following conditions have to be considered Instruction fetch from an external location Operand read from an external location Result write back to an external location Depending on where the instructions source and destination operands are located there are a number of combinations Note however that only access conflicts contribute to the delay A few examples illustrate these delays The worst case interrupt response time including external accesses occurs when instructions N 1 and N 2 are executed from external memory instructions N 1 and N require external ST10X167 operand read accesses instructions N 3 to N write back external operands and the interrupt vector also points to an external location In this case the interrupt response time is the time to perform 9 Word bus accesses because instruction 11 cannot be fetched via the external bus until all write fetch and read requests of preceding instructions in the pipeline are terminated When the above example has the interrupt vector pointing into the internal ROM the interrupt response time is 7 Word bus accesses plus 2 CPU clock cycles because fetching of instruction 11 from internal ROM start earlier When instructions N 1 and N 2 are executed out of external memory and the interrupt vector also points to an external location but all
392. s not entered if READY is enabled but has not been activated driven low during the last bus access 19 1 Idle Mode The power consumption of the ST10X167 microcontroller can be decreased by entering Idle mode In this mode all peripherals including the watchdog timer continue to operate normally only the CPU operation is halted Idle mode is entered after the IDLE instruction has been executed and the instruction before the IDLE instruction has been completed To prevent unintentional entry into Idle mode the IDLE instruction has been implemented as a protected 32 Bit instruction Idle mode is terminated by interrupt request from any enabled interrupt source whose individual Interrupt Enable flag has been set before the Idle mode was entered regardless of Bit IEN For a request selected for CPU interrupt service the associated interrupt service routine is entered if the priority level of the requesting source is higher than the current CPU priority and the interrupt system is globally enabled After the RETI Return from Interrupt instruction of the interrupt service routine is executed the CPU continues executing the program with the instruction following the IDLE instruction Otherwise if the interrupt request cannot be serviced because of a too low priority or a globally disabled interrupt system the CPU immediately resumes normal program execution with the instruction following the IDLE instruction For a reque
393. s occupied by another bus master it demands it via the BREQ output The external bus arbitration is enabled by setting Bit HLDEN in register PSW to 1 In this case the three bus arbitration pins HOLD HLDA and BREQ are automatically controlled by the EBC independent of their I O configuration Bit HLDEN may be cleared during the execution of program 124 294 sequences where the external resources are required but cannot be shared with other bus masters In this case the ST10X167 will not answer to HOLD requests from other external masters If HLDEN is cleared while the ST10X167 is in hold state code execution from internal RAM ROM this hold state is left only after HOLD has been deactivated again In this case the current hold state continues and only the next HOLD request is not answered Connecting two ST10X167 s in this way would require additional logic to combine the respective output signals HLDA and BREQ This can be avoided by switching one of the controllers into slave mode where pin HLDA is switched to input This allows to directly connect the slave controller to another master controller without glue logic The slave mode is selected by setting Bit DP6 7 to 1 DP6 7 0 default after reset selects the Master Mode Note The pins HOLD HLDA and BREQ keep their alternate function bus arbitration even after the arbitration mechanism has been switched off by clearing HLDEN
394. s the address of the faulty instruction 5 7 8 Illegal Word Operand Access Trap Whenever a Word operand read or write access is attempted to an odd Byte address the ILLOPA flag in register TFR is set and the CPU enters the illegal Word operand access trap routine The IP value pushed onto the system stack is the address of the instruction following the one which caused the trap 5 7 9 Illegal Instruction Access Trap Whenever a branch is made to an odd Byte address the ILLINA flag in register TFR is set and the CPU enters the illegal instruction access trap routine The IP value pushed onto the system stack is the illegal odd target address of the branch instruction 5 7 10 Illegal External Bus Access Trap Whenever the CPU requests an external instruction fetch data read or data write and no external bus configuration has been specified the ILLBUS flag in register TFR is set and the CPU enters the illegal bus access trap routine The IP value pushed onto the system stack is the address of the instruction following the one which caused the trap 73 294 ST10X167 6 PARALLEL PORTS 6 1 Introduction ST10X167 has to 111 parallel I O lines organized into Eight 8 Bit I O ports PORTO made of and POL PORT1 made of and P1L Port4 Port 6 Port 7 Port8 One 15 Bit I O port Port3 One 16 Bit input port Port5 One 16 Bit I O port Port2 These port lines may
395. s the first possibility for BREQ to get active During bus hold pin P3 12 is switched back to its standard function and is then controlled by DP3 12 and P3 12 Keep DP3 12 0 in this case to ensure floating in hold mode 8 6 3 Exiting the Hold State The external bus master returns the access rights to the ST10X167 by driving the HOLD input high After synchronizing this signal the ST10X167 will drive the HLDA output high actively drive the control signals and resume executing external bus cycles if required Depending on the arbitration logic the external bus can be returned to the ST10X167 under two circumstances The external master does no more require access to the shared resources and gives up its own access rights The ST10X167 needs access to the shared resources and demands this by activating its BREQ output The arbitration logic may then deactivate the other master s HLDA and so free the external bus for the ST10X167 depending on the priority of the different masters Note The Hold State is not terminated by clear ing Bit HLDEN Figure 62 External bus arbitration regaining the bus Signals 126 294 Note The falling BREQ edge shows the last chance for BREQ to trigger the indicated regain sequence Even if BREQ is activated earlier the regain sequence is initiated by HOLD going high BREQ and HOLD are connected via an external arbitration circuitry Please note that HOLD may
396. s underflows of 6 will trigger the counter function of T5 Modifications of T6OTL via software will NOT trigger the counter function of T5 The maximum input frequency allowed in counter mode is fcpu 4 To ensure that a transition of the count input signal which is applied to T5IN is correctly recognized its level should be held high or low for at least 4 CPU clock cycles before it changes Figure 82 Block diagram of auxiliary timer T5 in counter mode Interrupt Auxiliary Timer T5 T5IR gt Request Up Down Table 29 GPT2 auxiliary timer counter mode input edge selection Triggering Edge for Counter Increment Decrement None Counter T5 is disabled Positive transition rising edge on T5IN Negative transition falling edge on T5IN Any transition rising or falling edge on T5IN Positive transition rising edge of output toggle latch T6OTL Negative transition falling edge of output toggle latch T6OTL Any transition rising or falling edge of output toggle latch T6OTL 150 294 Timer Concatenation Using the toggle Bit T6OTL as a clock source for the auxiliary timer in counter mode concatenates the core timer T6 with the auxiliary timer Depending on which transition of T6OTL is selected to clock the auxiliary timer this concatenation forms a 32 Bit or a 33 Bit timer counter 32 Bit Timer Counter If both a positive and a negative transition of T6OTL is used to clock the au
397. se lines can also be used in the address bus mode Hereby changes of the upper address lines could be detected and trigger an interrupt request in order to perform some special service routines External capture signals can only be applied if no address output is selected for PORT1 During external accesses in de multiplexed bus modes PORT1 outputs the 16 Bit intra segment address as an alternate output function During external accesses in multiplexed bus modes when no BUSCON register selects a de multiplexed bus mode PORT1 is not used and is available for general purpose I O ky Figure 28 PORT1 I O and alternate functions Alternate Functions gt P1H 7 P1H 6 P1H 5 P1H 4 P1H 3 P1H 2 P1H 1 P1H 0 P1L 7 P1L 6 P1L 5 P1L 4 P1L 3 P1L 2 P1L 1 P1L 0 General Purpose Input Output When an external bus mode is enabled the direc tion of the port pin and the loading of data into the port output latch are controlled by the bus control ler hardware The input of the port output latch is disconnected from the internal bus and is switched to the line labeled Alternate Data Out put via a multiplexer The alternate data is the 16 Bit intra segment address Figure 29 Block diagram of a PORT1 pin Write DP1H y DP1L y 2 Direction Demultiplexed Bus Latch Read DP1H y DP1L y Output Write P1H y P1L y Internal Bus Port Data Port Output Output Alternate Function Enable A
398. sed on these specific Bit It is recommended that Bit fields in control SFRs are updated using the BFLDH and BFLDL instructions or a MOV instruction to avoid undesired intermediate modes of operation which can occur when BCLR BSET or AND OR instruction sequences are used 21 6 Floating Point Support All floating point operations are performed using software Standard multiple precision instructions are used to perform calculations on data types that exceed the size of the ALU Multiple Bit rotate and logic instructions allow easy masking and extracting of portions of floating point numbers To decrease the time required to perform floating point operations two hardware features have been implemented in the CPU core First the PRIOR instruction aids in normalizing floating point numbers by indicating the position of the first set Bit in a GPR This result can the be used to rotate the floating point result accordingly The second feature aids in properly rounding the result of normalized floating point numbers through the overflow V flag in the PSW This flag is set when a one is shifted out of the carry Bit during shift right operations The overflow flag and the carry flag are then used to round the floating point result based on the desired rounding algorithm 280 294 ky ST10X167 21 7 Trap Interrupt Entry and Exit Interrupt routines are entered when a requesting interrupt has a priority higher than the current CPU priority l
399. service must be programmed to different channels Otherwise an incorrect PEC channel may be activated 3 2 1 0 Control Register ILVL GLVL Control 2 1 0 Channel 60 294 ST10X167 The table below shows in a few examples which action is executed with a given programming of an interrupt control register Priority Level Type of Service ILVL GLVL COUNT 00h COUNT z 00h 1111 CPU interrupt level 15 group priority 3 PEC service channel 7 1111 CPU interrupt level 15 group priority 2 PEC service channel 6 99 GPUmterupt ve T group priority o CPU interrupt eve T group priory 0 Note All requests on levels 13 1 cannot initiate PEC transfers They are always serviced by an interrupt service routine No PECC register is associated and no COUNT field is checked 5 1 5 Interrupt Control Functions in the PSW The Processor Status Word PSW is functionally divided into 2 parts the lower Byte of the PSW basically represents the arithmetic status of the CPU the upper Byte of the PSW controls the interrupt system of the ST10X167 and the arbitration mechanism for the external bus interface Note Pipeline effects have to be considered when enabling disabling interrupt requests via modifications of register PSW see Chapter 4 The Central Processing Unit CPU PSW FF10h 88h SFR ResetValue 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ILVL IEN HLD USRO
400. service routine is entered Since all class B traps have the same vector the priority to service simultaneous class B traps is 72 294 determined by the software in the trap service routine If a class A trap occurs during the execution of a class B trap service routine class A trap will be serviced immediately During the execution of a class A trap service routine no class B trap will be serviced until the class A trap service routine is exited with a RETI instruction In this case the occurrence of the class B trap condition is stored in the TFR register but the IP value of the instruction which caused this trap is lost If an Undefined Opcode trap class B occurs simultaneously with an NMI trap class A both the NMI and the UNDOPC flag is set the IP of the instruction with the undefined opcode is pushed onto the system stack but the NMI trap is executed After return from the NMI service routine the IP is popped from the stack and immediately pushed again because of the pending UNDOPC trap ky 5 7 3 External NMI Trap Whenever a high to low transition on the dedicated external NMI pin Non Maskable Interrupt is detected the NMI flag in register TFR is set and the CPU will enter the NMI trap routine The IP value pushed on the system stack is the address of the instruction following the one after which normal processing was interrupted by the NMI trap Note The NMI pin is sampled with every CPU clock cycle
401. services do not influence the ILVL field in the PSW Hardware traps switch the CPU level to maximum priority 15 so no interrupt or PEC requests will be acknowledged while an exception trap service routine is executed Note The TRAP instruction does not change the CPU level so software invoked trap service routines may be interrupted by higher requests PECCx FECyh 6zh see Table 8 15 14 13 12 11 10 9 8 Interrupt Enable bit IEN globally enables or disables PEC operation and the acceptance of interrupts by the CPU When IEN is cleared no interrupt requests are accepted by the CPU When IEN is set to 1 all interrupt sources which have been individually enabled by the interrupt enable bit in their associated control registers are globally enabled Note Traps are non maskable and are therefore not affected by the IEN bit 5 2 Operation of the PEC Channels The Peripheral Event Controller PEC of the MCU provides 8 PEC service channels which move a single Byte or Word between two locations in segment 0 data pages 3 0 This is the fastest possible interrupt response and in many cases is sufficient to service the respective peripheral request from serial channels A D converter etc Each channel is controlled by a dedicated PEC Channel Counter Control register PECCx and a pair of pointers for source SRCPx and destination DSTPx of the data transfer The PECC registers control the action that is performed by
402. sh pull mode ODP2 y 1 Port line P2 y output driver in open drain mode 82 294 6 4 1 Alternate Functions of Port2 All Port2 lines P2 15 P2 0 can be configured capture inputs or compare outputs CC151O CCO0IO for the CAPCOM1 unit When a Port2 line is used as a capture input the state of the input latch which represents the state of the port pin is directed to the CAPCOM unit via the line Alternate Pin Data Input If an external capture trigger signal is used the direction of the respective pin must be set to input If the direction is set to output the state of the port output latch will be read since the pin represents the state of the output latch This can be used to trigger a capture event through software by setting or clearing the port latch Note that in the output configuration no external device may drive the pin otherwise conflicts would occur When a Port2 line is used as a compare output compare modes 1 and 3 the compare event or the timer overflow in compare mode 3 directly effects the port output latch In compare mode 1 when a valid compare match occurs the state of the port output latch is read by the CAPCOM control hardware via the line Alternate Latch Data Input inverted and written back to the latch via the line Alternate Data Output The port output latch is clocked by the signal Compare Trigger which is generated by the CAPCOM unit In compare mode 3 when a match occur
403. signal latching it must be held low for at least 2 CPU clock cycles Also shorter RSTIN pulses may trigger a hardware reset if they coincide with the latch s sample point is only ky When synchronous reset is initiated all pending internal hold states are cancelled and the current internal access cycle if any is completed Except in the case of a watchdog reset external bus cycles are aborted Following this the internal reset sequence starts the bus pin drivers and the I O pin drivers are switched off tristate and the PORTO pins are internally pulled high After such a reset the configuration on PortO pins is relatched The configuration needs some time to settle to the required levels especially if the hardware reset aborts a read operation from an external peripheral During this settling time the configuration may intermittently be wrong In such a case also the PLL clock selection may be wrong It is therefore strongly recommended to provide an external reset pulse of at least 1 ms in order to allow the PLL to settle on the desired CPU clock frequency The input RSTIN provides an internal pullup device equalling a resistor of 50 KO to 150 KQ the minimum reset time must be determined by the lowest value Simply connecting an external capacitor is sufficient for an automatic power on reset see b in Figure 143 RSTIN may also be connected to the output of other logic gates see in Figu
404. signals will not be updated for an access to any internal address area for example when no external bus cycle is started even if this area is covered by the respective ADDRSELx register An access to an on chip X Peripheral deactivates all external CS signals Upon accesses to address windows without a selected CS line all selected CS lines are deactivated The chip select signals allow to operate in four different modes which are selected via Bit CSWENx and CSRENx in the BUSCONx register CSWENx CSRENx Chip Select Mode Address Chip Select Default after Reset mode for CSO ee RAS respective Write Chip Select Read Write Chip Select Address chip select signals remain active until an access to another address window An address chip select becomes active with the falling edge of ALE and becomes inactive with the falling edge of ALE of an external bus cycle that accesses a diferent address area No spikes will be generated on the chip select lines Read or write chip select signals remain active only as long as the associated control signal RD or WR is active This also includes the programmable read write delay Read chip select is only activated for read cycles write chip select is only activated for write cycles read write chip select is activated for both read and write cycles write cycles are assumed ifany of the signals WRH or WRL becomes active These modes save external glue logic wh
405. ss sets the CPU level to the highest interrupt priority within the class All requests from the same or any lower level are blocked now and no request of this class will be accepted The example below establishes 3 interrupt classes which cover 2 or 3 interrupt priorities depending on the number of members in a class A level 6 interrupt disables all other sources in class 2 by changing the current CPU level to 8 which is the highest priority ILVL in class 2 Class 1 requests or PEC requests are still serviced in this case ST10X167 The 24 interrupt sources excluding requests are so assigned to 3 classes of priority rather than to 7 different levels as the hardware support would do Table 9 Example Software controlled interrupt classes ILVL Priority Interpretation 38 to 8 hames ul US 32 DX Gass 11 1 8 sources on 7 Zia sssi pio Interrupt Class 2 10 sources on 3 levels E Interrupt Class 3 6 sources on 2 levels Low Addresses a System stack before Interrupt Entry b System stack after Interrupt Entry unsegmented 5 4 Saving the Status During Interrupt Service Before an interrupt request that has been arbitrated is actually serviced the status of the current task is automatically saved on the system stack The CPU status PSW is saved along with t
406. ss space of the ST10X167 is implicitly divided into equally sized blocks of different granularity and into logical memory areas Crossing the boundaries between these blocks code or data or areas requires special attention to ensure that the controller executes the desired operations Memory Areas are partitions of the address space that represent different kinds of memory if provided at all These memory areas are the internal RAM SFR area the internal ROM Flash Memory if available the on chip X Peripherals if integrated and the external memory Accessing subsequent data locations that belong to different memory areas is no problem However when executing code the different memory areas must be switched explicitly via branch instructions Sequential boundary crossing is not supported and leads to erroneous results Note Changing from the external memory area to the internal RAM SFR area takes place within segment O Segments are contiguous blocks of 64K Byte each They are referenced via the code segment pointer CSP for code fetches and via an explicit segment number for data accesses overriding the standard DPP scheme During code fetching segments are not changed automatically but rather must be switched explicitly The instructions JMPS CALLS and RETS will do this In larger sequential programs make sure that the highest used code location of a segment contains an unconditional branch instruction to the respect
407. st 4 CPU clock cycles before it changes When the timer capture trigger is enabled CT3 1 the CAPREL register captures the contents of T5 upon transitions of the selected input s These values can be used to measure T3 s input signals This is useful when operates in incremental interface mode in order to derive dynamic information speed acceleration deceleration from the input signals When a selected transition at the external input pin T3EUD is detected the contents of the auxiliary timer T5 is latched into register CAPREL and interrupt request flag CRIR is set With the same event timer T5 can be cleared to 0000h This option is controlled by Bit T5CLR in register T5CON If TECLR O the contents of timer 5 are not affected by a capture If T5CLR 1 timer T5 is cleared after the current timer value has been latched into register CAPREL Note Bit T5SC only controls whether a capture is performed or not If T5SC 0 the input pin CAPIN can still be used to clear timer T5 or as an external interrupt input This interrupt is controlled by the CAPREL interrupt control register CRIC see Figure 84 Figure 83 Concatenation of core timer T6 and auxiliary timer T5 T l CPU Soa gt Core Timer T6 Up Down p p T6OTL Interrupt gt Request gt T6OUT KA P3 1 Edge Select p Auxiliary Timer T5 6 I
408. st which was programmed for PEC service a PEC data transfer is performed if the priority level of this request is higher than the current CPU priority and if the interrupt system is globally enabled After the PEC data transfer has been completed the CPU remains in Idle mode Otherwise if the PEC request cannot be serviced because of a too low priority or a globally disabled interrupt system the CPU does not remain in Idle mode but continues program execution with the instruction following the IDLE instruction see Figure 147 Idle mode can also be terminated by a Non Maskable Interrupt with a high to low transition on the NMI pin After Idle mode has been terminated by an interrupt or NMI request the interrupt system performs round of prioritization to determine the highest priority request In the case of an NMI request the NMI trap will always be entered Any interrupt request whose individual Interrupt Enable flag was set before Idle mode was entered will terminate Idle mode regardless of the current CPU priority The CPU will not go back into Idle mode when a CPU interrupt request is detected even when the interrupt was not serviced because of a higher CPU priority or a globally disabled interrupt system IEN 0 The CPU will only go back into Idle mode when the interrupt system is globally enabled IEN 1 and PEC service on a priority level higher than the current CPU level is requested and executed Figure
409. states Two CPU clock cycles are equal to one instruction cycle These execution times apply to most of the ST10X167 instructions except some of the branches the multiplication the division and a special move instruction In case of internal Memory program execution there is no execution time dependency on the instruction length except for some special branch situations Because of the short execution time execution from internal RAM is flexible for loadable and modifiable code Execution from external memory depends on the selected bus mode and the programming of the bus cycles waitstates The operand and instruction accesses listed below can extend the execution time of an instruction Internal ROM Flash Memory operand reads same for Byte and Word operand reads Internal RAM operand reads via indirect addressing modes Internal SFR operand reads immediately after writing External operand reads External operand writes Table 5 Minimum execution times A Memory Area Word Instruction Doubleword Instruction Read trom CPU clock cycles CPU clock cycles Internal RAM 16 Bit Demux Bus 16 Bit Mux Bus 8 Bit Demux Bus 8 Bit Mux Bus 3 ST10X167 Jumps to non aligned double Word instructions in the internal ROM Flash Memory space Testing Branch Conditions immediately after PSW writes 4 4 CPU Special Function Registers The CPU requires a set of Special Function Registers S
410. ster read only X SORBUF SORIC b SOTBIC b SOTBUF SOTIC P SSCBR SSCCON SSCEIC b SSCRB SSCRIC b FF74h SSCTB SSCTIC b FF72h STKOV FE STKUN FEt6h SYSCON b TO1CON b Serial Channel 0 Receive Interrupt Control Register 0000h Serial Channel 0 Transmit Buffer Interrupt Control Register 0000h Serial Channel 0 Transmit Interrupt Control Register 0000h i CPU System Stack Pointer Register b b SSC Control Register 0000h SSC Receive Buffer read only XXXXh SSC Receive Interrupt Control Register 0000h SSC Transmit Buffer write only 0000h i N Serial Channel 0 Transmit Buffer Reg write only 00h E N TOREL FE54h h CAPCOM Timer 0 Reload Register 0000h 1 FE52h CAPCOM Timer 1 Register 0000h m ant A SSC Error Interrupt Control Register 0000h m EF gt 98h 99h BF 84h 5A D8 B8 59h B7 CE 58h B6 09h 5A D9 BB 59h BA 58h B9 0A 0B 89h 28h A8 CE 2A FOB4h E SSC Baud rate Register 0000h 3 263 294 ST10X167 Table 43 Special function registers ordered by name continued De mmpm o e EE TC s res 0 Timer nerupi Conroe CON rem Am GPTiTmerzCowoRedse son tno econ e Am e rm 86 __ GPTa Tiers erupt Comor Reger ooon tamam wam m U Gas Trason re
411. struction Hardware traps always have highest priority and cause immediate system reaction The software trap function is invoked by the TRAP instruction which generates a software interrupt for a specified interrupt vector For all types of traps the current program status is saved on the System stack External interrupt processing Although the ST10X167 does not provide dedicated interrupt pins it allows to connect external interrupt sources and provides several mechanisms to react on external events including standard inputs non maskable interrupts and fast ky ST10X167 external interrupts These interrupt functions are alternate port functions except for the non maskable interrupt and the reset input 5 1 Interrupt System Structure The ST10X167 provides 56 separate interrupt nodes that may be assigned to 16 priority levels In order to support modular and consistent software design techniques each source of an interrupt or PEC request is supplied with a separate interrupt control register and interrupt vector The control register contains the interrupt request flag the interrupt enable bit and the interrupt priority of the associated source Each source request is activated by one specific event depending on the selected operating mode of the respective device The only exceptions are the two serial channels of the ST10X167 where an error interrupt request can be generated by different kinds of error How
412. t BitOError During the transmission of a message or acknowledge Bit active error flag or overload flag the device wanted to send a dominant level 0 but the monitored bus value was recessive During busoff recovery this status is set each time a sequence of 11 recessive Bit has been monitored This enables the CPU to monitor the proceeding of the busoff recovery sequence indicating the bus is not stuck at dominant or continuously disturbed CRCError The CRC check sum was incorrect in the message received Transmitted Message Successfully Indicates that a message has been transmitted successfully error free and acknowledged by at least one other node since this Bit was last reset by the CPU the CAN controller does not reset this Bit 3 224 294 ST10X167 Bit Function Control Bit RXOK Received Message Successfully Indicates that a message has been received successfully since this Bit was last reset by the CPU the CAN controller does not reset this Bit EWRN Error Warning Status Indicates that at least one of the error counters in the EML has reached the error warning limit of 96 BOFF Busoff Status Indicates when the CAN controller is in busoff state see EML Note Reading the upper half of the Control Register status partition will clear the Status Change Interrupt value in the Interrupt Register if it is pending Use Byte accesses to the lower half to avoid this 17 3 CAN Inte
413. t and the Phase Buffer Segment1 combined to Tseg1 defines the time before the sample point while Phase Buffer Segment2 Tseg2 defines the time after the sample point The length of these segments is programmable except Sync Seg Note For exact definition of these segments please refer to the CAN Specification o cM 1 time quantum 226 294 sample point transmit point 3 Bit EF04h 14 11 PUE ST10X167 ResetValue UUUUh CRT Ge mm Tem 1 R BRP Baud Rate Prescaler For generating the Bit time quanta the CPU frequency is divided by 2 x BRP 1 SJW Re Synchronization Jump Width Adjust the Bit time by maximum SJW 1 time quanta for re synchronization TSEG1 Time Segment before sample point There are TSEG1 1 time quanta before the sample point Valid values for TSEG1 are 2 15 Time Segment after sample point There are TSEG2 1 time quanta after the sample point Valid values for TSEG2 are 1 7 Note This register can only be written if the configuration change enable Bit CCE is set Mask Registers Messages can use standard or extended identifiers Incoming frames are masked with their appropriate global masks Bit IDE of the incoming message determines whether the standard 11 Bit mask in Global Mask Short or the 29 Bit extended mask in Global Mask Long is to be used Bit holding a 0 mean don t care so do not Global Mask Sho
414. t access to user data variables user stacks and code The on chip XRAM is an X Peripheral and appears to the software as an external RAM Therefore it cannot store register banks and is not Bit addressable The XRAM allows 16 Bit accesses with maximum speed 17 294 ST10X167 An optional internal ROM provides for both code and constant data storage This memory area is connected to the CPU via a 32 bit wide bus Thus an entire double word instruction can be fetched in just one instruction cycle Program execution from the on chip ROM is the fastest of all possible alternatives For Special Function Registers 1024 Byte ofthe address space are reserved The standard Special Function Register area SFR uses 512 Byte while the Extended Special Function Register area ESFR uses the other 512 Byte E SFRs are Word wide registers which are used for controlling and monitoring functions of the different on chip units Unused ESFR addresses are reserved for future members of the ST10X167 family 2 3 3 External Bus Interface In order to meet the needs of designs where more memory is required than is provided on chip up to 16M Byte of external memory can be connected to the microcontroller via its external bus interface The integrated External Bus Controller EBC allows flexible access to external memory and or peripheral resources For up to five address areas the bus mode multiplexed demultiplexed the data bus width 8 Bit
415. t is sampled at the 7th 8th and 9th cycle of this clock The Baud rate for asynchronous operation of serial channel ASCO and the required reload value for a given Baud rate can be determined by the following formulas cPU B sr STD as uv qas sS Async 46 x 2 SOBRS x SOBRL 1 fopu SOBRL 1 16 x 2 SOBRS x Bagync SOBRL represents the content of the reload register taken as unsigned 13 Bit integer SOBRS represents the value of Bit SOBRS 0 or 1 taken as integer Using the above equation the maximum Baud rate can be calculated for any given clock speed The device datasheet gives a table of values for Baud rate vs reload register value for SOBRS 0 and SOBRS 1 Synchronous Mode Baud Rates For synchronous operation the Baud rate generator provides a clock with 4 times the rate of the established Baud rate The Baud rate for SOTIC FF6Ch B6h 15 14 13 12 11 10 9 8 ST10X167 synchronous operation of serial channel ASC0 can be determined by the following formula fopu Syne 4x 2 SOBRS x SOBRL 1 fopu SOBRL Mp 1 4 x 2 SOBRS x SOBRL represents the content of the reload register taken as unsigned 13 Bit integers SOBRS represents the value of Bit SOBRS 0 or 1 taken as integer Using the above equation the maximum Baud rate can be calculated for any given clock s
416. t or PEC service in the ST10X167 the associated interrupt vectors their locations and the associated trap numbers It also lists the mnemonics of the affected Interrupt Table 6 Interrupt and PEC service request sources Enable Interrupt Vector Trap Flag Vector Location Number Source of Interrupt or PEC Request Service Request Flag Request flags and their corresponding Interrupt Enable flags The mnemonics are composed of a part that specifies the respective source followed by a part that specifies their function IR Interrupt Request flag IE Interrupt Enable flag Each entry of the interrupt vector table provides room for two Word instructions or one doubleword instruction The respective vector location results from multiplying the trap number by 4 4 Byte per entry CAPCOM Register 4 CAPCOM Register 5 CAPCOM Register 6 CCAIR CC6IR CC4IE CC5IE CC6IE CC6INT 00 0058h 16h CCAINT 00 0050h 14h CC5INT 00 0054h 15h CAPCOM Register 7 CC7IR CC7IE CC7INT 00 005Ch 17h CAPCOM Register 8 CC8IR CC8IE CC8INT 00 0060h 18h CAPCOM Register 9 CC9IR CC9IE CC9INT 00 0064h 19h CAPCOM Register 10 CC10IR CC10IE CC10INT 00 0068h 1Ah CAPCOM Register 11 CC11IR CC11IE CC11INT 00 006Ch 1Bh CC12IR CAPCOM Register 13 00 0074h 1Dh CAPCOM Register 14 CC14IR CC14IE CC14INT 00 0078h 1Eh CAPCOM Register 15 CC15IR CC15IE CC15INT 00 007Ch 1Fh CAPCOM Register 16 CC16IR CC16IE CC16INT 0
417. t processing steals just one instruction cycle from the current CPU activity 34 294 to perform a single data transfer via the on chip PEC System errors detected during program execution so called hardware traps or an external non maskable interrupt are also processed as high priority standard interrupts There is a close conjunction between the watchdog timer and the CPU If enabled the watchdog timer expects to be serviced by the CPU within a programmable period of time otherwise it will reset the chip Therefore the watchdog timer is able to prevent the CPU from going totally astray when executing erroneous code After reset the watchdog timer starts counting automatically but if necessary it can be disabled via software Beside its normal operation there are the following particular CPU states Reset state Any reset hardware software watchdog forces the CPU into a predefined active state IDLE state The clock signal to the CPU itself is switched off while the clocks for the on chip peripherals keep running POWER DOWN state All of the on chip clocks are switched off A transition into an active CPU state is forced by an interrupt if being IDLE or by a reset if being in POWER DOWN mode The IDLE POWER DOWN and RESET states can be entered by particular ST10X167 system control instructions A set of Special Function Registers is dedicated to the functions of the CPU core Gener
418. t request may be used to cause an interrupt to vector ADEINT or it may trigger a PEC data transfer ADCIC FF98h CCh SFR ResetValue 00h 15 14 13 12 11 10 5 4 3 2 1 0 9 8 7 6 ADC ADC ILVL GLVL IR IE RW RW RW RW ADEIC FF9Ah CDh SFR ResetValue 00h 15 14 13 12 11 10 5 4 3 2 1 0 9 8 7 6 ADE ILVL GLVL IE RW RW RW RW Note Refer to Section 5 1 3 Interrupt Control Registers for explanation of the control fields ky 219 294 ST10X167 17 ON CHIP CAN INTERFACE The CAN module is always enabled on the ST10F167 The CAN module may be enabled or disabled with ST10C167 or ST10R167 by programming the XPEN Bit in the SYSCON register The integrated Module handles the autonomous transmission and reception of CAN frames in accordance with the CAN specification V2 0 part B active the on chip CAN Module can receive and transmit standard frames with 11 Bit identifiers and extended frames with 29 Bit identifiers The CAN provides Full CAN functionality on up to 15 full sized message objects 8 data Byte each Message object15 may be configured for Basic CAN functionality with a double buffered receive object Full CAN and Basic CAN modes both provide separate masks for acceptance filtering accepting identifiers in Full CAN mode and disregarding identifiers in Basic CAN mode Al message objects can be updated independently from the other objects and are equipped with buffers for the maximum message lengt
419. t the same time it would be altered by a compare event the soft ware write will have priority In this case the hardware triggered change will not become effective On channels 24 27 compare mode 1 will generate interrupt requests but no output function is provided 14 5 5 Double Register Compare Mode In double register compare mode two compare registers work together to control one output pin This mode is selected by a special combination of modes for these two registers For double register mode the 16 capture compare registers of each CAPCOM unit are regarded as two banks of 8 registers each Registers CC0 CC7 and CC16 CC23 form bank1 while registers CC8 CC15 and CC24 CC31 form bank2 respectively For double register mode a bank 1 register and a bank 2 register form a register pair Both registers of this register pair operate on the pin associated with the bank 1 register pins CCOIO CC7IO and CC161O CC2310 The relationship between the bank 1 and bank 2 register of a pair and the effected output pins for double register compare mode is listed in the Table 31 Table 31 Register pairs for double register compare mode CAPCOM Unit CAPCOM Unit Register Pair Pin Register Pair 9 Associated Output 196 294 The double register compare mode be programmed individually for each register pair In order to enable double register mode the respective bank 1 register see Table 31 must be p
420. t5 Data Register A D Converter Result Register A D Converter Control Register Y Bit is linked to a function Bit has no function or is not implemented E Register is in ESFR internal memory space 3 2E A D Converter Channel Injection Result Register Data Registers 1514131211109876543210 YU YEON YOY NOE YON Y YYYY YYYYYYYYYY Interrupt Control 1514131211109876543210 02 0c ee Y Y Y Y Y Y Y Y o 0 0 co co c c o Y Y Y Y Y Y Y Y ADCIC A D Converter Interrupt Control Register End of Conversion A D Converter Interrupt Control Register Overrun Error Channel Injection ADEIC 211 294 ST10X167 The external analog reference voltages Varner VAGNp are fixed The separate supply for the ADC reduces the interference with other digital signals The sample time as well as the conversion time is programmable so the ADC can be adjusted to the internal resistances of the analog sources and or the analog reference voltage supply Figure 124 Analog digital converter block diagram RoR Conversion Interrupt Control Request ADEIR gt 16 Result Register ADDA T Analog 10 Bit Result Register ADDAT2 Input Channels Converter AN15 P5 15 Varer VAGND 16 1 Mode Selection and Operation The functions of the A D converter are controlled The analog input channels ANO AN15 are by the Bit addressable A D Converter Control alternate functions of Port5 which is a 16
421. te requires one CPU clock and is controlled via the MTTCx Bit of the BUSCON registers A waitstate will be inserted if Bit is 0 default after reset External bus cycles in multiplexed bus modes implicitly add one tri state time waitstate in addition to the programmable MTTC waitstate Any MTTC waitstates are applicable to both read and write cycles ky 113 294 ST10X167 Figure 55 Memory tri state time 8 3 4 Read Write Signal Delay The ST10X167 allows the user to adjust the timing of the read and write commands to account for timing requirements of external peripherals The read write delay controls the time between the falling edge of ALE and the falling edge of the command Without read write delay the falling edges of ALE and command s are coincident except for propagation delays With the delay enabled the command s become active half a CPU clock cycle after the falling edge of ALE Figure 56 Read write delay Bus Cycle Segment ALE Bus Cycle MTTC Wait State The read write delay does not extend the memory cycle time and does not slow down the controller in general In multiplexed bus modes however the data drivers of an external device may conflict with the ST10X167 s address when the early RD signal is used Therefore multiplexed bus cycles should always be programmed with read write delay The read write delay is contr
422. teps of 4h Software Traps TRAP Instruction The Table 7 lists the vector locations for hardware traps and the corresponding status flags in register TFR It also lists the priorities of trap service for cases where more than one trap condition might be detected within the same instruction After any reset hardware reset software reset instruction SRST or reset by watchdog timer overflow program execution starts at the reset vector at location 00 0000h Reset conditions have priority over every other System activity and therefore have the highest priority trap priority III Software traps may be initiated to any vector location between 00 0000h and 0001 service routine entered via a software TRAP instruction is always executed on the current CPU priority level which is indicated in bit field ILVL in register PSW 58 294 NMITRAP STOTRAP STUTRAP 00 0000h 00 0000h 00 0000h 00 0008h 00 0010h 00 0018h 00 0028h 00 0028h 00 0028h 00 0028h 00 0028h Current This means that routines entered via the software TRAP instruction can be interrupted by all hardware traps or higher level interrupt requests 5 1 1 Normal Interrupt Processing and PEC Service At each instruction cycle among all the sources which require a PEC or an interrupt processing only the one with the highest priority is selected The priority of interrupts and PEC requests is programmable in two levels Each requesting
423. ternal pull up ensures an inactive high level on the RD output External Write Write Low Strobe controls the data transfer from the ST10X167 to an external mem ory or peripheral device This pin may either provide an general WR signal activated for both Byte and Word write accesses or specifically control the low Byte of an external 16 Bit device WRL together with the signal WRH alternate function of P3 12 BHE During reset and during Hold mode an internal pull up ensures an inactive high level on the WR WRL output READY READY Ready Input receives a control signal from an external memory or peripheral device that is used to terminate an external bus cycle provided that this function is enabled for the current bus cycle READY READY may be used as synchronous READY READY or may be evaluated asynchro nously For the ST10F167 the polarity is always READY For the ST10C167 and ST10R167 the polarity can be set to READY or READY by setting Bit 13 in the BUSCON register A External Access Enable determines if the ST10X167 after reset starts fetching code from the inter nal Memory area EA 1 or via the external bus interface EA 0 Non Maskable Interrupt Input allows to trigger a high priority trap via an external signal It can be used as power fail input or to validate the PWRDN instruction that switches the ST10X167 into power down mode Reset Input puts the ST10X167 into the reset default configuration either at power u
424. ternal ROM is xx xxFEy For PEC data transfers the internal ROM can be accessed independently of the contents of the DPP registers via the PEC source and destination pointers The internal ROM is not provided for single Bit storage and therefore it is not Bit addressable Note The x in the locations above depends on the available ROM Flash memory and on the mapping The internal ROM may be enabled disabled or mapped into segment 0 or segment 1 under software control Handling the internal ROM Section 21 10 describes the mapping procedures and precautions 27 294 ST10X167 3 2 Internal RAM and SFR Area System Stack programmable size The RAM SFR area is located within data page 3 General Purpose Register Banks GPRs and provides access to 2K Byte Internal RAM X Source and destination pointers for the organized as 1K x 16 and to two 512 Byte blocks Peripheral Event Controller PEC of Special Function Registers SFRs The Variable and other data storage or Code internal RAM is used as storage Figure 6 Internal RAM and SFR ESFR areas 00 FFFF Bit addressable area 256 Byte SFR area 0 00 __ __ 512 Byte reserved 00 FE00 00 FFFF 00 FDFF Bit addressable area 256 Byte 00 FD00 00 C000 External Memory 00 F600 Page 2 Area 00 8000 Reserved Segment 0 00 F200 O0 F1FF Bit addressable area Internal 00 4000 ROM for 256 Byte ST10C167 00 F100 ESFR
425. ternal instruction pipeline a new CP value is not yet usable for GPR address calcu lations of the instruction immediately following the instruction updating the CP register ky 49 294 ST10X167 The Switch Context instruction SCXT makes it possible to save the content of register CP on the stack and updating it with a new value in just one instruction cycle Several addressing modes use implicitly for address calculations Short 4 Bit GPR addresses mnemonic Rw or Rb specify an address relative to the memory location specified by the contents of the CP register which is the base of the current register bank Depending on whether a relative Word Rw or Byte Rb GPR address is specified the short 4 Bit GPR address is either multiplied by two or not before it is added to the content of register CP see Figure 17 Thus both Byte and Word GPR accesses are possible in this way GPRs used as indirect address pointers are always accessed Word wise For some instructions only the first four GPRs can be used as indirect address pointers These GPRs are specified via short 2 Bit GPR addresses The respective physical address calculation is identical to that for the short 4 Bit GPR addresses Short 8 Bit register addresses mnemonic reg or Bitoff within a range from F0h to FFh interpret the four least significant Bit as short 4 Bit GPR address while the four most significant Bit are ignored The respective physical GPR add
426. ters To provide local registers the contents of the registers which are required for use by the subroutine can be pushed onto the stack and the previous values be popped before returning to the calling routine This is the most common technique used today and it does provide a mechanism to support recursive procedures This method however requires two instruction cycles per register stored on the system stack one cycle to PUSH the register and one to POP the register Use of the system stack for local registers It is possible to use the SP and CP to set up local subroutine register frames This enables subroutines to dynamically allocate local variables as needed within two instruction cycles A local frame is allocated by simply subtracting the number of required local registers from the SP and then moving the value of the new SP to the CP This operation is supported through the SCXT switch context instruction with the addressing mode reg mem Using this instruction saves the old contents of the CP on the system stack and moves the value of the SP into CP see example below Each local register is then accessed as if it was a normal register Upon exit from the subroutine first the old CP must be restored by popping it from the stack and then the number of used local registers must be added to the SP to restore the allocated local space back to the system stack The system stack is growing downwards while the registe
427. ters Interrupt Control 15141312111098 76543210 15 14 13 12111098765 43210 SOCON Y Y Y Y Y YY Y Y Y Y Y Y Y Y SOTIC So ee er Se are NON SORIC Y YON SOEIC Ss Sh Woo YE Yo Y SOTBICE YYYYYYYY RXDO P3 11 TXDO P3 10 ODP3 Port3 Open Drain Control Register DP3 Port3 Direction Control Register Port3 Data Register SOBG ASCO Baud rate Generator Reload Register SOCON ASCO Control Register SOTBUF ASCO Transmit Buffer Register SORBUF ASCO Receive Buffer Register read only SOTIC ASCO Transmit Interrupt Control Register SORIC ASCO Receive Interrupt Control Register SOTBIC ASCO Transmit Buffer Interrupt Control Register SOEIC ASCO Error Interrupt Control Register Y Bit is linked to a function Bit has no function or is not implemented E Register is in ESFR internal memory space The operating mode of the serial channel ASCO is controlled by its Bit addressable control register SOCON This register contains control Bit for mode and error check selection and status flags for error identification 156 294 ST10X167 SOCON FFB0h D8h SFR ResetValue 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 son se eene sooc soo sere sope sooen soren soren sonen sosre RW RW RW RW RW RW RW RW RW RW RW RW RW 8 Bit data synchronous operation 8 Bit data asynchronous operation Reserved Do not use this combination 7 Bit data parity asynchronous opera
428. ters R8 R15 The sixteen Byte GPRs are mapped onto the first eight Word GPRs see Table 4 In contrast to the system stack a register bank grows from lower towards higher address locations and occupies a maximum space of 32 Byte The GPRs are accessed via short 2 4 or 8 Bit addressing modes using the context pointer CP register as base address independent of the current DPP register contents Additionally each Bit in the currently active register bank can be accessed individually The ST10X167 supports fast register bank context switching Multiple register banks can physically exist within the internal RAM at the same time Only the register bank selected by the Context Pointer register CP is active at a given time Selecting a new active register bank is simply done by updating the CP register A particular Switch Context SCXT instruction performs register bank switching and an automatic saving of the previous context The number of implemented register banks arbitrary sizes is only limited by the size of the available internal RAM Details on using switching and overlapping register banks are described in Register Banking Section 21 2 Table 4 Mapping of general purpose registers to RAM addresses CP 30 294 ST10X167 3 2 3 PEC Source and Destination Pointers The 16 Word locations in the internal RAM from 00 FCEOh to 00 FCFEh are provided as source and destination address pointe
429. th the active level defined by the RDYPOL Bit in the associated BUSCON register see Figure 57 Figure 57 READY READY controlled bus cycles Bus Cycle with active READY or READY A Evaluation sampling of the READY READY input Note 1 Not available for ST10F167 ST10X167 The READY READY function is enabled by the RDYENx Bit in the BUSCON registers When this function is selected RDYENx 1 only the lower 3 Bit of the respective MCTC Bit field define the number of inserted waitstates 0 7 while the MSB of Bit field MCTC selects the READY operation MCTO 3 0 Synchronous READY READY the READY READY signal must meet setup and hold times MCTC 3 1 Asynchronous READY READY the READY READY signal is synchronized internally The synchronous READY READY SREADY SREADY provides the fastest bus cycles but requires setup and hold times to be met The CLKOUT signal should be enabled and may be used by the peripheral logic to control the READY READY timing in this case The asynchronous READY READY AREADY AREADY is less restrictive but requires additional waitstates caused by the internal synchronization As the asynchronous READY READY is sampled earlier see Figure 57 programmed waitstates may be necessary to provide proper bus cycles see also notes on normally ready peripherals below Bus Cycle Extended via READY or READY 115 294 ST10X167 A READY READ
430. the respective PEC channel ResetValue 0000h 7 6 5 4 3 2 1 0 COUNT PEC Transfer Count Counts PEC transfers and influences the channel s action see table below BWT Byte Word Transfer Selection 0 Transfer a Word 1 Transfer a Byte Increment Control Modification of SRCPx or DSTPx 0 0 Pointers are not modified 0 1 Increment DSTPx by 1 or 2 BWT 1 0 Increment SRCPx by 1 or 2 BWT 1 1 Reserved Do not use this combination changed to 10 by hardware Table 8 PEC Control Register Addresses PECCO FECOh 60h SER PECC1 FEC2h 61h S S S PECC4 FEC8h 64h PECC2 FEC4n 62h SFR PECC6 FECCh 66h FR FR FR FR PECC3 FEC6h 63h PECC7 FECEh 67h 62 294 3 Byte Word Transfer bit BWT controls if Byte or a Word is moved during a PEC service cycle This selection controls the transferred data size and the increment step for the modified pointer Increment Control Field INC controls if one of the pointers is incremented after the transfer It is not possible to increment both pointers however If the pointers are not modified 00 the respective channel will always move data from the same source to the same destination Note The reserved combination 11 is changed to 10 by hardware Do not to use this combination The PEC Transfer Count Field COUNT controls the action of a respective PEC channel where the content of bit field COUNT at the ti
431. the upper boundary since the stack empties upward to higher memory locations is reached The entries that have been previously saved in external memory must now be restored This is called stack filling Because procedure The basic mechanism is the transformation of the addresses of a virtual stack area controlled via registers SP STKOV and STKUN to a defined physical stack area within the internal RAM via hardware This virtual stack area covers all possible locations that SP can point to from 00 F000h through 00 FFFEh STKOV and STKUN call instructions do not continue to nest infinitely accept the same 4K Byte address range and call and return instructions alternate flushing and filling normally occurs very infrequently If this is not true for a given program environment this technique should not be used because of the overhead of flushing and filling The size of the physical stack area within the internal RAM that effectively is used for standard stack operations is defined via Bitfield STKSZ in register SYSCON see below Table 45 Stack Size Selection Stack Size Words Internal RAM Addresses Words of Physical Stack Significant Bit of STKSZ Stack Pointer SP 000b 00 FBFEh 00 FA00h Default after Reset SP8 SP 0 001b 00 FBFEh 00 FB00h SP7 SP 0 010b 00 FBFEh 00 FB80h 5 6 5 0 31518 ReemedDonotusetiscombmaon 110p Reserved Do not use this combination
432. thin segment 0 so data can be transferred between any two locations within the first four data pages 3 0 The pointer locations for inactive PEC channels may be used for general data storage Only the required pointers occupy RAM locations Note If Word data transfer is selected for a specific PEC channel BWT 0 the respective source and destination pointers must both contain a valid Word address which points to an even Byte boundary Otherwise the Illegal Word Access trap will be invoked when this channel is used 5 3 Prioritizing Interrupt amp PEC Service Requests Interrupt and PEC service requests from all sources can be enabled so they are arbitrated and serviced if they win or they may be disabled so their requests are disregarded and not serviced 5 3 1 Enabling and Disabling Interrupt Requests This may be done in three ways Control bit allow to switch each individual source ON or OFF so it may generate a request or not The control bit xxIE are located in the respective interrupt control registers All interrupt requests may be enabled or disabled generally via bit IEN in register PSW This control bit is the main switch that selects if requests from any source are accepted or not In order to be arbitrated both dedicated and global enable bit of the interrupt source must be set The Priority Level automatically selects a certain group of interrupt requests that w
433. tically by interpreting the physical address No additional switching or selecting is necessary during run time except when more than the four address windows plus the default is to be used ky Switching from demultiplexed to multiplexed bus mode represents a special case The bus cycle is started by activating ALE and driving the address to Port4 and PORT1 as usual if another BUSCON register selects a demultiplexed bus However in the multiplexed bus modes the address is also required on PORTO In this special case the address on PORTO is delayed by one CPU clock cycle which delays the complete multiplexed bus cycle and extends the corresponding ALE signal see Figure 51 This extra time is required to allow the previously selected device via demultiplexed bus to release the data bus which would be available in a demultiplexed bus cycle 8 2 4 External Data Bus Width The EBC can operate on 8 Bit or 16 Bit wide external memory peripherals A 16 Bit data bus uses PORTO while an 8 Bit data bus only uses POL the lower Byte of PORTO This saves on address latches bus transceivers bus routing and memory cost on the expense of transfer time The EBC can control Word accesses on an 8 Bit data bus as well as Byte accesses on a 16 Bit data bus Word accesses on an 8 Bit data bus are automatically split into two subsequent Byte accesses where the low Byte is accessed first then the high Byte The assembly of Byte to Words
434. tion 9 Bit data asynchronous operation 8 Bit data wake up Bit asynchronous operation Reserved Do not use this combination 8 Bit data parity asynchronous operation Number of Stop Bit Selection asynchronous operation 0 One stop Bit 1 Two stop Bit SOREN Receiver Enable Bit 0 Receiver disabled Receiver enabled Reset by hardware after reception of Byte in synchronous mode SOPEN Parity Check Enable Bit asynchronous operation 0 Ignore parity 1 Check parity SOFEN Framing Check Enable Bit asynchronous operation 0 Ignore framing errors 1 Check framing errors SOOEN Overrun Check Enable Bit Bd 0 Ignore overrun errors 1 Check overrun errors SOPE Parity Error Flag Set by hardware on a parity error SOPEN 1 Must be reset by software SOFE Framing Error Flag NON Set by hardware on a framing error SOFEN 1 Must be reset by software SOOE Overrun Error Flag E E Set by hardware on an overrun error SOOEN 1 Must be reset by software SOODD Parity Selection Bit 0 Even parity parity Bit set on odd number of 1 s in data E Odd parity parity Bit set on even number of 1 s in data SOBRS Baud rate Selection Bit 0 Divide clock by reload value constant depending on mode T Additionally reduce serial clock to 2 3rd SOLB Loopback Mode Enable Bit 0 Standard transmit receive mode 1 Loopback mode enabled SOR Baud rate Generator Run Bit 0 Baud rate generator disabled ASCO inactive
435. tion registers DP1H and DP1L P1L FFO4h 82h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T CC peee RW RW RW RW RW RW RW RW FFO6h 83h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L L Bz pie pitts ena Prhe pres Pato RW RW RW RW RW RW RW RW P1X y Port data register P1H or P1L Bit y DP1L F104h 82h ESFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH RW RW RW RW RW RW RW RW DP1H F106h 83h ESFR ResetValue 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T T Eeepesspesspesa penis pene peso RW RW RW RW RW RW RW RW Port direction register DP1H or DP1L Bit y DP1X y 0 Port line P1X y is an input high impedance DP1X y 1 Port line P1X y is an output 6 3 1 Alternate Functions of PORT1 When a de multiplexed external bus is enabled PORT is used as address bus Note that de multiplexed bus modes use PORT1 as a 16 Bit port Otherwise all 16 port lines can be used for general purpose I O The upper four pins of PORT1 P1H 7 P1H 4 also are capture input lines for the CAPCOM unit CC27 24 I O As all other capture inputs the capture input func tion of pins P1H 7 P1H 4 can also be used as external interrupt inputs with a sample rate of 8 CPU clock cycles 80 294 As a side effect the capture input capability of the
436. tion after the instruction which has changed the ROM mapping To enable accesses to the ROM after mapping a branch to the newly selected ROM area JMPS and reloading of all data page pointers is required This also applies to re mapping the internal ROM to segment 0 Enabling the internal ROM after reset When enabling the internal ROM after having booted the System from external memory note that the ST10X167 will then access the internal ROM using the current segment offset rather than accessing external memory Disabling the internal ROM after reset When disabling the internal ROM after having booted the system from there note that the ST10X167 will not access external memory before a jump to segment 0 in this case is executed General Rules When mapping the ROM no instruction or data accesses should be made to the internal ROM otherwise unpredictable results may occur To avoid these problems the instructions that configure the internal ROM should be executed from external memory or from the internal RAM Whenever the internal ROM is disabled enabled or re mapped the DPPs must be explicitly re loaded to enable correct data accesses to the internal ROM and or external memory 283 294 ST10X167 22 KEY WORD INDEX Symbols a 249 A AcronymS eeeeeeeeee eene 12 Adapt Mode 250 p esas sya 24 211 AD GON
437. tion cycle any isolated instruction takes at least four instruction cycles to be completed Pipelining however allows parallel simultaneous processing of up to four instructions Therefore as soon as the pipeline has been filled most instructions appear to be processed during one instruction cycle see Figure 10 Specification of instruction execution time always refers to the average execution time for pipelined parallel instruction processing see Figure 10 4 1 2 Standard Branch Instruction Processing When branch is taken it is necessary to perform the branched target instruction before the current instruction in the pipeline Therefore at least one additional instruction cycle is required to fetch the branch target instruction This extra instruction cycle is provided by means of an injected instruction see Figure 11 If a conditional branch is not taken there is no deviation from the sequential program flow and thus no extra time is required In this case the instruction after the branch instruction will enter the decode stage of the pipeline at the beginning Figure 11 Standard branch instruction pipelining 1 instruction of the next instruction cycle after decode of the conditional branch instruction 4 1 3 Cache Jump Instruction Processing The ST10X167 incorporates a jump cache This minimizes the time taken for conditional jumps which are repeatedly processed in a loop Whenever a cache jump inst
438. tions P5 15 P5 14 P5 13 P5 12 P5 11 P5 10 P5 9 AN9 P5 8 AN8 P5 7 AN7 P5 6 6 5 5 5 5 4 4 P5 3 AN3 52 2 P5 1 AN1 P5 0 AN0 General Purpose Input A D Converter Input 3 91 294 ST10X167 Port5 pins have a special port structure see Figure 38 first because it is an input only port and second because the analog input channels are directly connected to the pins rather than to the input latches Figure 38 Block diagram of a Port5 pin Channel Select Analog to Sample Hold Switch Circuit P5 y ANy Read Port P5 y Clock Input Latch Read Buffer o 2 m c 2 6 8 Port6 If this 8 Bit port is used for general purpose I O the direction of each line can be configured via the corresponding direction register DP6 Each port line can be switched into push pull or open drain mode via the open drain control register ODP6 P6 FFCCh E6h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP6 FFCEh E7h SFR Reset Value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Port direction register DP6 Bit y DP6 y 0 Port line P6 y is an input high impedance DP6 y 1 Port line P6 y is an output 92 294 ky ST10X167 ODP6 F1CEh E7h ESFR ResetValue 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C por ove bores foors oor oeos RW RW RW RW RW RW RW RW Port6 Open Drain control register Bit y ODP6 y
439. tive If compare mode 1 is programmed for one of the registers 7 or 16 23 the double register compare mode becomes enabled for this register if the corresponding bank 1 register is programmed to compare mode 0 see section Double Register Compare Mode Note If the port output latch is written to by software at the same time it would be altered by a compare event the soft ware write will have priority In this case the hardware triggered change will not become effective On channels 24 27 compare mode 1 will generate interrupt requests but no output function is provided Figure 111 Timing example for compare modes 0 and 1 Contents of Ty FFFFh Compare Value cv2 Compare Value cv1 Reload Value lt TyREL gt 0000h Interrupt Requests TyIR CCxIR CCxIR TyIR CCxIR CCxIR TyIR Event 3 CCx cv2 Event 4 gt Event 1 Event 2 CCx cv1 CCx cv2 CCx cv1 Output pin CCxIO only effected in mode 1 No changes in mode 0 194 294 5 14 5 3 2 Compare mode 2 is an interrupt only mode similar to compare mode 0 but only one interrupt request per timer period will be generated Compare mode 2 is selected for register CCx by setting Bit field CCMODx of the corresponding mode control register to 110b When a match is detected in compare mode 2 for the first time within a timer period the interrupt request flag CCxIR is set to
440. to account dependencies between instructions in different stages of the pipeline This extra hardware like a forwarding operand read and write values resolves most of the possible conflicts like multiple usage of buses ST10X167 Injection of cached Target Instruction In 2 ITARGET 1 12 rangers ITARGET 2 insect ITARGET ITARGET 1 Repeated loop iteration _ gt This prevents delays that would cause the pipeline to become noticeable to the user However there are some cases where allowances must be made by the programmer for the pipeline architecture of the ST10X167 In these cases the delays caused by pipeline conflicts can be used for other instructions in order to optimize performance 37 294 ST10X167 Context Pointer Updating An instruction which calculates a physical GPR operand address via the CP register is generally not capable of using a new CP value which is to be updated by an immediately preceding instruction Therefore to make sure that the new CP value is used at least one instruction must be inserted between a CP changing and a subsequent GPR using instruction as shown in the example T SCXT CP 0FCOOh select a new context must not be an instruction using a GPR Taga MOV RO dataX write to GPR 0 in the new context Data Page Pointer Updating An instruction which calculates a physical operand address via a p
441. to detect transitions 5 7 4 Stack Overflow Trap Whenever the stack pointer is decremented to a value which is less than the value in the stack overflow register STKOV the STKOF flag in register TFR is set and the CPU will enter the stack overflow trap routine Which IP value will be pushed onto the system stack depends on which operation caused the decrement of the SP When an implicit decrement of the SP is made through a PUSH or CALL instruction or upon interrupt or trap entry the IP value pushed is the address of the following instruction When the SP is decremented by a subtract instruction the IP value pushed represents the address of the instruction after the instruction following the subtract instruction For recovery from stack overflow it must be ensured that there is enough excess space on the stack for saving the current system state PSW IP in segmented mode also CSP twice Otherwise a system reset should be generated 5 7 5 Stack Underflow Trap Whenever the stack pointer is incremented to a value which is greater than the value in the stack underflow register STKUN the STKUF flag is set in register TFR and the CPU will enter the stack underflow trap routine Again the IP value pushed onto the system stack depends on which operation caused the increment of the SP When an implicit increment of the SP is made through a POP or return instruction the IP value pushed is the address of the following instructio
442. to or greater 202 294 Enable than the contents of the pulse width shadow register The signal is switched back to low level when the respective timer is reset to 0000h that means below the pulse width shadow register The period of the resulting PWM signal is determined by the value of the respective PPx shadow register plus 1 counted in units of the timer resolution PWM_Periodmodeo PPx 1 The duty cycle of the PWM output signal is controlled by the value in the respective pulse width shadow register This mechanism allows the selection of duty cycles from 096 to 10096 including the boundaries For a value of 0000h the output will remain at a high level representing a duty cycle of 10095 For a value higher than the value in the period register the output will remain at a low level which corresponds to a duty cycle of 096 The Figure 118 illustrates the operation and output waveforms of a PWM channel in mode 0 for different values in the pulse width register This mode is referred to as Edge Aligned PWM because the value in the pulse width shadow register only effects the positive edge of the output signal The negative edge is always fixed and related to the clearing of the timer ky ST10X167 Figure 118 Operation and output waveform in mode 0 PPx Period 7 PTx Count Value Duty Cycle PWx Pulse Width 0 100 PWx 1 87 5 PWx 2 75 PWx 4 50 PWx 6 25 PWx 7 12 5 PWx 8 0 LSR
443. to trigger a channel injection on the ST10X167 s A D con verter if enabled 14 4 Capture Mode In response to an external event the content of the associated timer TO T1 or T7 T8 depending on the used CAPCOM unit and the state of the allocation control Bit ACCx is latched into the respective capture register CCx The external event causing a capture can be programmed to be either a positive a negative or both a positive or a negative transition at the respective external input pin CCxIO ky The triggering transition is selected by the mode Bit CCMODx in the respective CAPCOM mode control register In any case the event causing a capture will also set the respective interrupt request flag CCxIR which can cause an interrupt or a PEC service request when enabled see Figure 109 In order to use the respective port pin as external capture input pin CCxIO for capture register CCx this port pin must be configured as input the corresponding direction control Bit by setting to 0 To ensure that a signal transition is properly recognized an external capture input signal should be held for at least 8 CPU clock cycles before it changes its level During these 8 CPU clock cycles the capture input signals are scanned sequentially When a timer is modified or incremented during this process the new timer contents will already be captured for the remaining capture registers within the current scanning sequence If pin C
444. transmitted Notes 1 In message object 15 last message these Bit are hardwired to 0 inactive in order to prevent transmission of message 15 2 When the CAN controller writes new data into the message object unused message Byte will be overwritten by non specified values Usually the CPU will clear this Bit before working on the data and verify that the Bit is still cleared once it has finished working to ensure that it has worked on a consistent set of data and not part of an old message and part of the new message For transmit objects the CPU will set this Bit along with clearing Bit CPUUPD This will ensure that if the message is actually being transmitted during the time the message was being updated by the CPU the CAN controller will not reset Bit TXRQ In this way Bit TXRQ is only reset once the actual data has been transferred 3 When the CPU requests the transmission of a receive object a remote frame will be sent instead of a data frame to request a remote node to send the corresponding data frame This Bit will be cleared by the CAN controller along with Bit RMTPND when the message has been successtully transmitted if Bit NEWDAT has not been set If there are several valid message objects with pending transmission request the message with the lowest message number is transmitted first 3 229 294 ST10X167 17 5 Arbitration Registers The arbitration Registers are used for acceptance filtering of incoming messag
445. ts the bus mode that is associated with the respective window Predefined address windows allow to use different bus modes without any overhead but restrict their number to the number of BUSCONS However as BUSCONO controls all address areas which are not covered by the other BUSCONSs this allows to have gaps between these windows which use the bus mode of BUSCONO 108 294 PORT will output the intra segment address when any of the BUSCON registers selects a demultiplexed bus mode even if the current bus cycle uses a multiplexed bus mode This means that an external address decoder can be connected to PORT1 only while using it for all kinds of bus cycles Note Never change the configuration for an address area that currently supplies the instruction stream Due to the internal pipe lines it is very difficult to determine the first instruction fetch that will use the new con figuration Only change the configuration for address areas that are not currently accessed This applies to BUSCON regis ters as well as to ADDRSEL registers The use of the BUSCON ADDRSEL registers is controlled via the issued addresses When an access code fetch or data is initiated the respective generated physical address defines if the access is made internally uses one of the address windows defined by ADDRSELA 1 or uses the default configuration in BUSCONO After initializing the active registers they are selected and evaluated automa
446. utput Enable Bit 0 Channel x output signal disabled generate interrupt only 1 Channel x output signal enabled PWM Channel x Mode Control Bit 0 Channel x operates in mode 0 i e edge aligned PWM 1 Channel x operates in mode 1 i e center aligned PWM PWM Channel 0 1 Burst Mode Control Bit 0 Channels 0 and 1 work independently in respective standard mode 1 Outputs of channels 0 and 1 are ANDed to POUTO in burst mode PWM Channel x Single Shot Mode Control Bit 0 Channel x works in respective standard mode 1 Channel x operates in single shot mode 15 3 Interrupt Request Generation Each of the four channels of the PWM module can generate an individual interrupt request Each of these channel interrupts can activate the common module interrupt which actually interrupts the CPU This common module interrupt is controlled by the PWM Module Interrupt Control register PWMIC The interrupt service routine can determine the active channel interrupt s from the channel specific interrupt request flags PIRx in register PWMCONO The interrupt request flag PIRx of a channel is set at the beginning of a new PWM cycle when loading the shadow registers This indicates that registers PPx and PWx are now ready to receive a new value If a channel interrupt is enabled via its PWMIC F17Eh BFh 15 14 13 12 11 10 ESFR respective PIEx Bit also the common interrupt request fla
447. ve edge falling Enter Power Down mode if EXiIN 1 exit if EXxIN 0 ref as low active level 1 1 Interrupt on any edge rising or falling Always enter Power Down mode exit if EXxIN level changed Exiting Power Down Mode During power down mode the CPU the peripheral clocks and the oscillator and PLL clock are stopped Power down mode can be exited by asserting either RSTIN or one of the enabled EXxIN pins Fast External Interrupt RSTIN must be held low until the oscillator and PLL have stabilized EXxIN inputs are normally sampled interrupt inputs However the power down mode circuitry uses them as level sensitive inputs An EXxIN x 3 0 Interrupt Enable Bit Bit CCxIE in respective CCxIC register need not to be set to bring the device out of power down mode An external RC circuit must be connected as shown Figure 148 To exit Power Down mode with external interrupt an EXxIN pin has to be asserted for at least 40 ns x 7 0 This signal enables the internal oscillator PLL circuitry and also turns on the weak pull down see Figure 149 The discharging of the external capacitor provides a delay that allows the oscillator and PLL circuits to stabilize before the internal CPU and peripheral clocks are enabled When the Vpp voltage drops below the threshold voltage about 2 5 V the Schmitt trigger clears Q2 flip flop therefore enabling the CPU and 254 294
448. ved STMicroelectronics GROUP OF COMPANIES Australia Brazil Canada China Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States http www st com 3 294 294
449. w or Rw Rw text changed pages 282 to 285 update of KEY WORD INDEX ky 291 294 ST10X167 page 289 update revision history 24 2 Revision of the 7th of August 2002 pages 1 2 and 294 cover and last page have been inserted in the document numbering leading to a total of 294 pages instead of 290 page 130 bits T3M of T3CON register combination 1XX Reserved Do not use this combination has been changed to 111 page 149 bit CT3 of T5CON register is bit 10 instead of bit 9 and its functionality when 0 is Capture triggered from CAPIN pin End of file 7th of August 2002 292 294 171 ST10X167 293 294 ST10X167 Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics 2002 STMicroelectronics All Rights Reser
450. wing Baud rate generation independent of the GPT timers The Baud rate generator is clocked by 2 The timer is counting downwards and can be started or stopped through the Baud rate Generator Run Bit SOR in register SOCON Each underflow of the timer provides one clock pulse to the serial channel The timer is reloaded with the value stored in its 13 Bit reload register each time it underflows The resulting clock is again divided according to the operating mode and controlled by the Baud rate Selection Bit SOBRS If SOBRS 1 the clock signal is additionally divided to 2 3rd of its frequency see formulas and table So the Baud rate of ASCO is determined by the CPU clock the reload value the value of SOBRS andthe operating mode asynchronous or synchronous Register SOBG is the dual function Baud rate Generator Reload register Reading SOBG returns the content of the timer Bit 15 13 return zero while writing to SOBG always updates the reload register Bit 15 13 are insignificant ky auto reload of the timer with the content of the reload register is performed each time S0BG is written to However if SOR 0 at the time the write operation to S0BG is performed the timer will not be reloaded until the first instruction cycle after SOR Asynchronous Mode Baud rates For asynchronous operation the Baud rate generator provides a clock with 16 times the rate of the established Baud rate Every received Bi
451. wise the instruction has no effect To exit Power Down Mode an external reset must occurs by asserting the RSTIN pin 1 Power Down Mode can only be entered during PWRDN instruction execution if all enabled fast external interrupt EXxIN pins are in their inactive level Exiting this mode can be done by asserting one enabled pin Chip Select Configuration Control 0 Latched Chip Select lines CSx change 1 TCL after rising edge of ALE 1 Unlatched Chip Select lines CSx change with rising edge of ALE Write Configuration Control Inverted copy of WRC bit of RPOH 0 Pins WR and BHE retain their normal function 1 Pin WR acts as WRL acts as WRH System Clock Output Enable CLKOUT 0 CLKOUT disabled pin may be used for general purpose 1 CLKOUT enabled pin outputs the system clock signal Disable Enable Control for Pin BHE Set according to data bus width 0 Pin BHE enabled 1 Pin disabled pin may be used for general purpose I O 3 ST10X167 Internal Memory Enable Set according to pin EA during reset 0 Internal ROM memory disabled accesses to the ROM memory area use the external bus 1 Internal ROM memory enabled access to the internal ROM memory see Table 45 on page 276 SGTDIS Segmentation Disable Enable Control 0 Segmentation enabled CSP is saved restored during interrupt entry exit 1 Segmentation disable
452. wo features may be combined to optimize the overall system performance Enabling 4 segment address lines and 5 chip select lines to give access to five memory banks of 1M Byte each so the available address space is 5M Byte without glue logic Note Bit SGTDIS of register SYSCON defines whether the CSP register is saved during interrupt entry segmentation active or not segmentation disabled 8 3 Programmable Bus Characteristics Important timing characteristics of the external bus interface have been made user programmable to allow to adapt it to a wide range of different external bus and memory configurations with different types of memories and or peripherals The following parameters of an external bus cycle are programmable ALE control defines the ALE signal length and the address hold time after its falling edge Memory cycle time extendable with 1 15 waitstates defines the allowable access time Memory tri state time extendable with 1 waitstate defines the time for a data driver to float Read write delay time defines when a command is activated after the falling edge of ALE READY polarity is programmable for ST10C167 and ST10R167 only READY control defines if a bus cycle is terminated internally or externally Programmable chip select timing control for ST10C167 and ST10R167 only Note Internal accesses are executed with maxi mum speed and therefore are not pro grammable
453. x Input Control GPT2 Timer T6 Over Underflow Mode 16 Control Capture inputs Capture Compare outputs or Compare Ty Input Control GPT2 Timer T6 Over Underflow Each capture compare register may be programmed individually for capture or compare function and each register may be allocated to either timer of the associated unit Each capture compare register has one port pin associated with it which serves as an input pin for the capture function or as an output pin for the compare function except for CC27 CC24 P1H 7 P1H 4 which only provide the capture function The capture function causes the current timer contents to be latched into the respective capture compare register triggered by an event transition on its associated port pin The compare function may cause an output signal transition on that port pin whose associated capture compare register matches the current timer contents Specific interrupt requests are generated upon each capture compare event or upon timer overflow Figure 106 shows the basic structure of the two CAPCOM units Reload Register TxREL CAPCOM Timer Tx Interrupt Request Sixteen 16 bit 16 Capture Compare Capture Compare Registers Interrupt Requests Interrupt Request CAPCOM Timer Ty Reload Register TyREL Note The CAPCOM2 unit provides 16 capture inputs but only 12 compare outputs 185 294 ST10X167 14 1 CAPCOM Timers The
454. xiliary timer this timer is clocked on every overflow underflow of the core timer T6 Thus the two timers form a 32 Bit timer 33 Bit Timer Counter If either a positive or a negative transition of T6OTL is selected to clock the auxiliary timer this timer is clocked on every second overflow underflow of the core timer T6 This configuration forms a 33 Bit timer 16 Bit core timer T6OTL 16 Bit auxiliary timer The count directions of the two concatenated timers are not required to be the same This offers a wide variety of different configurations T6 can operate in timer gated timer or counter mode in this case see Figure 83 GPT2 Capture Reload Register CAPREL in Capture Mode This 16 Bit register can be used as a capture register for the auxiliary timer T5 This mode is selected by setting Bit T5SC 1 in control register T5CON Bit CT3 selects the external input pin CAPIN or the input pins of timer T3 as the source for a capture trigger Either a positive a negative or both a positive and a negative transition at this pin can be selected to trigger the capture function ST10X167 or transitions on input T3IN or input T3EUD or both inputs T3IN and T3EUD The active edge is controlled by Bit field Cl in register The maximum input frequency for the capture trigger signal at CAPIN is fopy 4 To ensure that transition of the capture trigger signal is correctly recognized its level should be held for at lea
455. y transferred to the receive buffer register if the 9th Bit the wake up Bit is 1 If this Bit is 0 no receive interrupt request will be activated and no data will be transferred This feature may be used to control communication in multi processor system when the master processor wants to transmit a block of data to one of several slaves it first sends out an address Byte which identifies the target slave An address Byte differs from a data Byte in that the additional 9th Bit is 1 for an address Byte and a 0 for a data Byte so no slave will be interrupted by a data Byte An address Byte will interrupt all slaves operating in 8 Bit data wake up Bit mode so each slave can examine the 8 LSBs of the received character the address The addressed slave will switch to 9 Bit data mode by clearing Bit 50 0 which enables it to also receive the data Byte that will be coming having the wake up Bit cleared The slaves that were not being addressed remain 8 Bit data wake up Bit mode ignoring the following data Byte see Figure 90 Figure 90 Asynchronous 9 Bit data frames 160 294 Asynchronous transmission begins at the next overflow of the divide by 16 counter see Figure 90 provided that SOR is set and data has been loaded into SOTBUF The transmitted data frame consists of three basic elements the start Bit the data field 8 or 9 Bit LSB first including a parity Bit if se
456. y access sequences on the external bus by means of a Logic Analyzer Different pipeline stages can simultaneously put a request on the External Bus Controller EBC The sequence of instructions processed by the CPU may diverge from the sequence of the corresponding external memory accesses performed by the EBC due to the predefined priority of external memory accesses lst Write Data 2nd Fetch Code 3rd Read Data Controlling Interrupts Software modifications implicit or explicit of the PSW are done in the execute phase of the respective instructions In order to maintain fast interrupt responses however the current interrupt prioritization round does not consider these changes For example an interrupt request may be acknowledged after the instruction that disables interrupts via IEN or ILVL or after the following instructions Time critical instruction sequences therefore should not begin directly after the instruction disabling interrupts as shown in the example INT_OFF BCLR IEN globally disable interrupts 1 non critical instruction CRIT 1ST Iy start of non interruptible critical Sequence CRIT LAST end of non interruptible critical Sequence INT ON BSET IEN globally r nable interrupts Note The described delay of 1 instruction also applies for enabling the interrupts system that means interrupt requests are acknowledged until the instruction following the ena
457. ze is 4 x MEMSIZE in K Byte MEMTYP Internal Memory Type Refer to datasheet for values IDPROG F078h 3Ch ESFR Reset Value UUUUh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R PROGVDD Programming Vdd Voltage 00h for ST10C167 and ST10R167 PROGVPP Programming Vpp Voltage 00h for ST10C167 and ST10R167 1 Note 1 Not implemented for ST10F167 3 272 294 21 SYSTEM PROGRAMMING Constructs for modularity loops and context switching have been built into the ST10X167 instruction set Many commonly used instruction sequences have been simplified The following programming features are available to the programmer Instructions Provided as Subsets of Instructions In many cases instructions found in other microcontrollers are provided as subsets of more powerful instructions in the ST10X167 This provides the same functionality while decreasing the hardware requirement decreasing decode complexity These instructions can be built in macros to aid assembly programming Directly substitutable instructions are known instructions from other microcontrollers that can be replaced by the following instructions of the ST10X167 NN Instruction Instruction SWAPB Rn ROR Rn 8h Swap Byte within Word Modification of system flags is performed by using Bit set or Bit clear instructions BSET BCLR All Bit and Word instructions can access the PSW register so no instructions like CLEAR CARRY or ENAB

ST10X167 USER`S MANUAL - REV

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