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1. Signal Name FPGA B Pin Clock Refdes and Pin ACLK1 U28 AU22 U62 91 BCLK1 U28 AN22 U63 91 USER BCLKp U28 K21 U1 5 USER BCLKn U28J21 01 6 SYS BCLKp U28 AP21 65 3 SYS BCLKn U28 AN21 U65 6 RCKTIO OSCT Bp U28 F21 U38 14 RCKTIO OSCT Bn U28 G21 U38 15 RCKTIO OSCB Bp U28 AT21 U38 11 RCKTIO_OSCB_Bn U28 AU21 U38 12 Signal Name FPGA C Pin Clock Refdes and Pin ACLK2 029 722 062 94 BCLK2 U29 G22 063 94 USER CCLKp U29 AP21 U1 10 USER CCLKn U29 AN21 U1 9 SYS_CCLKp U29 K21 U65 10 SYS_CCLKn 029 721 U65 9 RCKTIO_OSCT_Cp U29 F21 U37 14 RCKTIO OSCT Cn U29 G21 U37 15 RCKTIO OSCB Cp U29 AT21 03711 RCKTIO OSCB Cn U29 AU21 1137 12 DDR CCLKp U29 AU22 018 5 DDR CCLKn 29 22 018 6 Signal Name FPGA D Pin Clock Refdes and Pin ACLK3 U53 K21 U62 96 BCLK3 U53 F21 U63 96 USER_DCLKp U53 AN22 U1 20 USER_DCLKn U53 AP22 111 29 SYS DCLKp U53 22 U65 20 DN6000K 10 User Guide www dinigroup com 74 BOARD HARDWARE SYS DCLKn AUS53 K22 U65 19 RCKTIO OSCT Dp 053 622 060 14 RCKTIO OSCT Dn U53 F22 060 15 RCKTIO OSCB Dp U53 AU22 060 11 RCKTIO OSCB Dn U53 AT22 U60 12 DDR_DCLKp U53 AT21 U36 5 DDR_DCLKn U53 AU22 036 6 Signal Name FPGA E Pin Clock Refdes and Pin ACLK4 U52 AU022 U62 66 BCLK4 U52 AN22 U63 66 USER_ECLKp U52 K21 11 22 USER ECLKn 052 721 11 23 SYS ECLKp U52 AP21 116
2. dee bMS euet 8 2 2 Combined CPU Trace Debug Connection to FPGA s 9 EEE 131 9 1 Status Indicators oco a v p Fe RR RH 131 9 2 FPGA A GPIO LED s 133 10 POWER SYSTEM H 134 10 1 Stand Alone Oper atin 134 10 1 1 External Power Connector 135 10 1 2 Power Monitors 136 10 1 3 Power Indicators 136 10 1 4 Bront Panel Indicator S rer Ere He ATA IS EOD er ee s EARN 136 11 TEST HEADER amp DAUGHTER CARD CONNECTIONS eee er GRE E S AE E EES a ES SEEE 137 11 1 Test Header 137 11 1 1 Test Header Connector erse 139 11 1 2 Test Header Pin Numberin sch ent tet edet te e N E TEE 139 140 142 11 2 DN3000K10SD Daughter Card 11 2 1 Daughter Card LED s 11 2 2 Power Supply 143 11 2 3 Unbuffered 144 11 2 4 luci M 144 11 2 5 LVDS IO 144 11 2 6 Connection between FPGA and the Daughter Card 145 12 MECHANICAL 12 1 1 Case 12 1 2 PWB DimensionThe DN6000K10 PWB conforms to
3. Daughter Card Connections DN26000K10 IO Connections Test Header C Test Signal Name Connector Test Signal Name FPGA Pin Header Header 1 184 GND 2 36 11 184 GND 1 185 P4N14 VAs P11 185 TST HDRC146 U79 H3 1 186 P4N9 P11 186 TST HDRC147 U79J2 J1 187 P4N8 719 P11 187 TST HDRC148 U79 K2 1 188 P4N5 7 21 P11 188 HDRC149 07911 1 189 1 23 PILIS ISE HDRCIOO 17913 1 190 1 25 P11 190 TST HDRC151 U79 M3 11 191 1 21 P11 191 151 HDRC152 UT79 N2 1 192 13 17 29 11 192 HDRC153 1979 21 11193 P4NX12 11 31 P11 193 TST HDRC154 U79 P3 J1 194 P4NX9 J7 33 11 194 TST HDRC155 U79 R2 11195 No Connect P11 195 GND J1 196 P4NX8 J7 35 P11 196 TST HDRC156 7912 1 197 P4NX3 1737 11 197 HDRCI57 1179411 1 198 P4NX2 1539 P11 198 HDRC158 U79 U3 1 199 4 1 J74 11 199 TST_HDRC159 U79 V1 J1 200 J7 43 P11 200 TST HDRC160 U79 W1 12 Mechanical Two bus bars MP1 and MP2 are installed to prevent flexing of the PWB are connected to the ground plane and can be used to ground test equipment The user must not short any power rails or signals to these metal bars they can conduct a lot of current Mounting holes are provided to allow the PCB to be mounted in a case 12 1 1 Case The Amaquest PM7200 Server case holds the DN6000K10 board as well as a PC pla
4. Signal Name FPGA Pin FLASH FLASHC ADDR18 U29 AK38 U17 16 FLASHC ADDR19 U29 AK39 011715 FLASHC_ADDR20 U29 AH38 U17 10 FLASHC_ADDR21 U29 AH40 U17 9 FLASHC DATAO U29 AR39 U17 29 FLASHC DATA1 U29 AT42 017 31 FLASHC DATA2 U29 A T40 1717 33 FLASHC DATA3 U29 AT38 U17 35 FLASHC 4 U29 AU41 U17 38 FLASHC DATA5 U29 AU39 U17 40 FLASHC_DATAG U29 AV41 U17 42 FLASHC_DATA7 U29 AW42 U17 44 FLASHC_DATA8 U29 AR38 017 30 FLASHC DATA9 U29 AT41 U17 32 FLASHC DATA10 U29 AT39 U17 34 FLASHC U29 AU42 U17 36 FLASHC DATA12 U29 AU40 U17 39 FLASHC DATA13 U29 AV42 017 41 FLASHC DATA14 U29 AV40 U17 43 FLASHC DATA15 U29 AWA1 U17 45 FLASHC CEN U29 AP38 U17 26 FLASHC OEN U29 AR40 U17 28 FLASHC WEN U29 A 40 U17 11 FLASHC WPN U29 AK40 U17 14 FLASHG ADDRO U80 M3 U88 25 FLASHG ADDR1 U80 M2 U88 24 FLASHG ADDR2 U80 L3 U88 23 FLASHG ADDR3 U80 L2 U88 22 FLASHG ADDR4 U80 L1 U88 21 DN6000K 10 User Guide www dinigroup com 100 BOARD HARDWARE Signal Name FPGA Pin FLASHG ADDR5 U80 K3 FLASHG ADDR6 U80 K2 FLASHG ADDR7 U80 K1 FLASHG ADDR8 U80 F2 FLASHG ADDR9 U80 F1 FLASHG ADDR10 U80 E3 FLASHG ADDR11 080 52 FLASHG ADDR12 U80 E1 FLASHG ADDR13 U80 D3 FLASHG ADDR14 U80 D2 FLASHG ADDR15 U80 D1 FLASHG ADDR16 U80 W3 FLASHG ADDR17 U80 J2 FLASHG ADDR18 U80 1 FLASHG ADDR19 U80 H3 FLASHG ADDR20 U80 G1 FLASHG ADDR 21 U80 F3 FLASHG DATAO U80 N3 FLASHG_DATA1 U80 P2 FLASHG DATA2 U80 R1 FLASHG
5. AE E 68 3 3 es t E TENER UTRUM RORIS QR NT 3 3 1 SmartMedia Connector 5 3 3 2 SmartMedia connection to Spartan Configuration 70 3 4 Boundary Sc n JTAG IEEE 1532 Mode etie ien e ii HA EE PRESTA ERATES 71 3 4 1 FPGA JTAG Connector m 3 4 2 FPGA JTAG connection to 71 4 CLOCK GENERATION ER RETE Mk ERE TER TRE RR eH XL LU I Eee d rra e 72 4 1 Clock Methodology 72 42 Clock Source Jumpers 577 4 2 1 Clock Source Jumper Header 78 4 3 78 4 3 1 RoboClock PLL Clock Buffers UE 4 3 2 RoboClock Configuration Jumpers 4 3 3 Roboclock Configuration Headets ett een 84 4 3 4 Useful Notes and Hints 84 4 3 5 Customizing the Oscillators 85 4 3 6 Common Clock Source Selections 2 85 4 4 External Clocks sess 4 4 1 External SMA Clock 4 4 2 Connections between FPGA s and External SMA Clock 86 45 DDR Clocking 4 5 1 Clocking Methodology 4 5 2 Connections between FPGA s and DDR PLL Clock Buffer 88 4 6 Power PC PPC Clock Sytem Clock s 4 6 1 Clocking Methodology 4 6 2 Connections between FPGA s and System Clock
6. 89 47 Rocket IO Programmable Clock irise aci t a ptt e s iei t DR ECL HEU IA WEE 90 4 7 1 Clocking Methodology MP 91 4 7 2 ICS8442 Programmable LVDS Clock Synthesizer 4291 4 7 3 Connections between FPGA s and RocketIO Clock Synthesizers 91 5 RESET LOPOLOG Vis 93 REEL GIN I M 93 32 PPG Reset eee Ree REOR EE eee PP PU PE et ee E Ie 95 6 MEMORY 01 6 1 1 FLASH Connection to the FPGA s 62 eee 6 2 1 LR quaDBIeich m M 6 2 2 DDR SDRAM Configuration 6 2 3 DDR SDRAM Clocking 6 2 4 DDR SDRAM Termination 6 2 5 DDR SDRAM Power Supply 6 2 6 DDR SDRAM Connection tothe n Pe PEE 107 7 ROCKET IO TRANSCEIVERS ERR PETI 7 1 SMA Connectors 7 1 1 FPGA to SMA Connector ead 8 CPU DEBUG AND CPU FRAGE 8 1 CPU Debug sss 8 1 1 CPU Debug Connectors 8 1 2 CPU Debug Connection to FPGA s 8 2 UTE 8 2 1 CPU Trace Connectors
7. CC ck CK CK CC CC CCS S E E DN6000K10 ASIC DEVELOPMENT PLATFORM REFERENCE DESIGN SOFTWARE KC CC _ Waiting for External Host Commands Press Any Key To Enter Local User Menu 8 At this point tests may be run from the MCU menu Text will appear on the PPC RS232 pott as tests from the MCU menu are run on the associated FPGA At this point the PPC port is connected to FPGA 9 Press a key on the PPC RS232 port to display the PPC test menu See the section Using the Reference Design in Chapter 4 Introduction to the Reference Design for more information Congratulations You have now programmed the DN6000K10 and successfully executed out utility to exercise various features of the board All of the source code for the embedded PowerPC utility is included on the CD for reference The FPGA design written in Verilog can also be found on the CD and used as a basis for new design DN6000K 10 User Guide ww w dinigroup com 13 INTRODUCTION VIRTEX II PRO ISE Chapter Introduction to USB Controller Software 1 Exploring the Software Tools 1 1 USBController USBController application is used to communicate with the DN6000
8. 12 5 PLAYING WITH YOUR DN6000K IO VIA THE PPC 12 INTRODUCTION TO USB CONTROLLER SOFTWARE vsssssscsssassassasesesessossosvossosenssesssesssesesencscseassasocvsnssassasensesssestsseassaseateceseescssosssesetesdssssbesasdeseadessees 14 1 EXPLORING THE SOFTWARE TOOLS ur etea GRE EE EIE 14 1 1 USBController 1 1 1 Getting Started with USBController 112 Basic Menu Operations UO 15 1 1 3 File Menu 1 1 4 Edit Menu 1 1 5 FPGA Configuration Men oeste Pe tee eee o 16 1 1 6 Memory MED 5 17 1 1 7 18 INTRODUCTION 1 PRO AND 20 2 PRO 241 Summary of Virtex II Pro Features 22 405 2 3 3 125 Gbps Transceiver aie e WERE 21 2 4 Virtex II FPGA Fabric P 3 FOUNDATION SE 6 NEM 3 1 Foundation
9. DN6000K 10 User Guide www dinigroup com 86 BOARD HARDWARE Signal Name FPGA Pin External SMA Clock Buffer USER_ICLKn UT ATA U1 30 4 5 DDR Clocking The DDR Clock is generated in the FPGA by using the Digital Clock Managers DCM Clocking for DDR SDRAM requires the transmission of two clocks the positive clock and the negative clock SSTL 2 differential These two clocks are 180 out of phase from each other and their phase alignment must be tightly controlled In order to prevent signal integrity problems and timing differences from becoming an issue it is preferable for each device whether memory or register to have its own clock While it is possible for each device to have a positive and negative clock generated by the FPGA this unnecessarily consumes pins that could be used elsewhere To save these pins an externally DDR SDRAM clock driver is used The clock is routed to the DDR PLL Clock Driver that distributes the individual clocks to the separate DDR devices 4 5 1 Clocking Methodology This section describes the DDR clocking methodology implemented in the reference design refer to Figure 27 The first DCM generates and CLK90 directly follows the user supplied input clock one of the clock sources ACLK BCLK etc This DCM also supplies the CLKDV output which is the input clock divided by 16 used for the AUTO REFRESH counter The second DCM in the controller block DCM2_RECAPT
10. UG DN6000K 10 User Guide www dinigroup com 118 BOARD HARDWARE Signal Name FPGA Pin DDR F2 WEN U51 L12 DDR G1 DATAO U80 M18 DDR G1 DATA1 U80 M17 DDR G1 DATA2 U80 L17 DDR G1 DATA3 U80 K17 DDR G1 DATA4 U80 H17 DDR G1 DATAS U80J17 DDR G1 DATAG 080 17 DDR G1 U80 G17 DDR G1 DATAS U80 K18 DDR G1 DATA9 080 118 DDR G1 DATA10 U80 G18 DDR G1 DATA11 U80 H18 DDR G1 DATA12 U80 E17 DDR G1 DATA13 U80 E18 DDR G1 DATA14 08019 DDR G1 DATA15 U80 K19 DDR_FPGA_G1_ADD0 U80 C14 DDR_FPGA_G1_ADD1 U80 C15 DDR_FPGA_G1_ADD2 080116 DDR ADD3 U80 M16 DDR ADD4 U80J16 DDR_FPGA_G1_ADD5 U80 K16 DDR_FPGA_G1_ADD6 U80 H16 DDR ADD7 U80 G16 DDR ADD8 U80 G19 U U U DDR FPGA G1 ADD9 80 H19 DDR FPGA G1 ADD10 80 E19 80 F19 DDR FPGA G1 ADD11 DN6000K 10 User Guide www dinigroup com 119 BOARD HARDWARE Signal Name FPGA Pin DDR FPGA G1 ADD12 U80 D19 DDR FPGA ADD13 U80 C19 DDR FPGA G1 UDQS 80 M19 DDR 1005 80 D17 DDR 1 80 C18 DDR LDM 80 D16 DDR G1 BAO 80 C20 DDR G1 80 D20 DDR FPGA G1 CASN 80 K20 DDR 80 21 DDR FPGA G1 CSN U80 20 DDR FPGA G1 RASN U80 L20 DDR FPGA G1 WEN U80 H20 DDR
11. C389 4 20 20 PGND1 0 001uF AGND DDR2 VREF Lid 8 benD PkaGND DDR2 VREF R518 ML6554 PSOP16 1K Figure 35 DDR Termination Regulator 6 2 6 DDR SDRAM Connection to the FPGA The connections between the FPGA and the DDR SDRAM are not homogeneous as control and address are handled differently from the data and differently from the clocks However all of these signals are controlled impedance and are SSTL2 terminated The termination of these signals is covered in DDR SDRAM Termination The Data signals DQ the Data Strobe DQS and the Data Mask DM signals are point to point signals going from the FPGA to the DDR SDRAM components As mentioned above these signals are controlled impedance and terminated according to the DDR SDRAM specification The data data strobe and data mask signals all serve different purposes The data signals are self evident carrying the raw data between the chips and are bi directional The data strobe signals are responsible for actual clocking in the data on rising and falling edges of the clock Finally the data mask signals can be used to enable or disable the reading and writing of some of the bytes in a 16 bit word transaction The interface signals between the FPGA and the DDR SDRAM components in covered in Table 18 Table 18 Connection between FPGA s and DDR SDRAM s Signal Name FPGA Pin
12. 2 JTAG DN6000K10 User Guide www dinigroup com 4 60 TEST HEADER 200PIN Pit FLASH XILINX XC2VP70 100 FF1704 MB BUS 256 BC 202 191 138 FLASH MB BUS 1 32 202 191 E XILINX FPGAA DDRSDRAM 44 XC2VP70 100 N fj FF1704 DDR SDRAM FPGA STATUS LED S wae z S m 2 5 s o 8 Vy mictor 5 amp PPO E DEBUG 2 ROCKETIO 10 DDRSDRAM 4 XILINX 4 32MX16 FPGAF 4 T DDRSDRAM 2 70 100 32MX16 FF1704 99 k TT A v x 2 8 5 V n N DDR SDRAM 32MX16 41 XILINX DDRSDRAM 4 32MX16 XC2VP70 100 FF1704 GH 180 169 EON qup M ROCKETIO 10 SMA1 SMA2 0 0 FLASH 45 0 i Y TEST HEADER 200PIN XILINX FPGA E U48 XC2VP70 100 FF1704 5 FD 96 96 XILINX FPGAH XC2VP70 100 FF1704 ED 103 90 TEST HEADER 200PIN GH131 Bus vp100 lines
13. 27 H32 DDR A2 CSN 27 K31 27 C33 27131 c c 5 c c c em ci c c DDR FPGA A2 RASN DDR FPGA A2 WEN DDR C1 DATAO U29 AW33 c c DDR C1 DATA1 DDR C1 DATA2 DDR C1 DATA3 DDR C1 DATA4 DDR C1 5 DDR C1 DATAG DDR C1 29 AN31 DDR_C1_DATA8 29 AU31 DDR_C1_DATA9 U29 AT31 DDR_C1_DATA10 U29 AN30 DDR_C1_DATA11 U29 AP30 DDR_C1_DATA12 U29 AL30 29 AV33 29 AY32 20 AY35 29 AU32 29 AV32 29 AM31 DN6000K 10 User Guide www dinigroup com 110 BOARD HARDWARE Signal Name FPGA Pin DDR C1 DATA13 U29 AM30 c DDR C1 DATA14 U29 AR30 DDR C1 15 U29 AT30 DDR FPGA C1 ADDO U29 AY30 DDR FPGA C1 1 U29 AW30 DDR FPGA C1 ADD2 U29 AU30 DDR FPGA C1 ADD3 U29 AV30 DDR FPGA C1 ADD4 U29 AU28 DDR FPGA C1 ADD5 U29 AV28 DDR FPGA C1 ADD6 U29 AL27 DDR FPGA C1 ADD7 U29 AM27 DDR FPGA C1 ADDS U29 AT27 DDR_FPGA_C1_ADD9 U29 AR27 DDR_FPGA_C1_ADD10 U29 AN27 DDR_FPGA_C1_ADD11 U29 AP27 DDR_FPGA_C1_ADD12 U29 AN26 DDR_FPGA_C1_ADD13 U29 AM26 DDR FPGA C1 UDQS U29 AP31 DDR FPGA C1 LDOS 29 AN32
14. DDR_FPGA_G2_CKE U80 K11 DDR_FPGA_G2_CSN U80 K12 DDR_FPGA_G2_RASN U80J12 DDR_FPGA_G2_WEN U80 L12 cr S DDR I1 DATAO U79 AN20 DDR U79 AM20 DDR I1 DATA2 U79 AP20 DDR_I1_DATA3 DN6000K10 User Guide U79 AR20 Www dinigroup com 121 BOARD HARDWARE Signal Name FPGA Pin DDR I1 DATA4 UT9 AV19 DDR I1 DATA5 U79 AU19 DDR DATAG U79 AW19 DDR T9 A Y19 DDR I1 DATAS T9 ATTB DDR I1 DATA9 79 AR18 DDR I1 DATA10 79 AV17 DDR DATA11 79 AV18 DDR DATA12 79 AN18 DDR DATA13 79 AM18 DDR_I1_DATA14 79 AU17 DDR DATA15 79 AT17 DDR FPGA I1 ADDO 79 AT19 DDR_FPGA_I1_ADD1 79 19 DDR FPGA I1 ADD2 U79 AM19 DDR FPGA ADD3 U79 AL19 DDR FPGA I1 ADD4 U79 AP19 DDR_FPGA_I1_ADD5 U79 AN19 DDR FPGA I1 ADD6 U79 AR17 DDR_FPGA_I1_ADD7 U79 AP17 DDR_FPGA_I1_ADD8 U79 AL18 DDR_FPGA_I1_ADD9 U79 AL17 DDR_FPGA_I1_ADD10 U79 AM17 DDR FPGA ADD11 LUT9 ANTT DDR FPGA I1 ADD12 U79 AP16 DDR FPGA I1 ADD13 U79 AN16 DDR_FPGA_I1_UDQS U79 AY18 DDR_FPGA_I1_LDQS U79 AV20 DDR_FPGA_I1_UDM
15. 1 if FPGA is 2vp100 0 if 2vp70 Bit 11 1 if FPGA C is 2vp100 0 if 2vp70 Bit 12 1 if FPGA D is 2vp100 0 if 2vp70 Bit 13 1 if FPGA E is 2vp100 0 if 2vp70 Bit 14 1 if FPGA F is 2vp100 0 if 2vp70 Bit 15 1 if FPGA is 2vp100 0 if 2vp70 Bit 16 1 if FPGA H is 2vp100 0 if 2vp70 Bit 17 1 if FPGA 115 2vp100 0 if 2vp70 178 FPGAE Start End Address Read Description Address Write External Host 0x4C00_0004 0x4C00_0004 R W Write Read register for MCU to issue the following commands Commands Regter 0x1 test all functionality 0x2 test registers 0x5 test FPGA interconnect issue a command the MCU must write one of the above values to this register The MCU can then poll this register to check if the test is done register will return all zeros when finished Status Register 0 4 00 0008 0 4 00 0008 R Read only register Status of commands and bus control Bits 16 18 must all be zero for MCU to issue any commands to External Host Command Register Status results can be read after command register is cleared decode for the test results is as follows Bit 0 overall pass fail pass 1 fail 0 Bit 1 register test pass fail Bit 4 interconnect test pass fail Existing FPGA 0 4 00 0018 Ox4COO 0018 R W Contains information what FPGAs are stuffed on the Register DN6000k10 as well as what type of FPGAs they are The register has the following
16. Communication via Rocket I O Transceivers Instantiation of Daughter Card Test Headers DN6000K10 User Guide www dinigroup com 28 INTRODUCTION THE SOFTWARE TOOLS source code for the reference design is included on the CD and may be used freely in customer development Precompiled bit files for the most common stuffing options are also included and should be used to vetify board functionality before beginning development A build utility described in the section Compiling The Reference Design can be used to generate new bit files or to generate bit files for less common configurations of the DN6000K10 1 2 Using the Reference Design For information on preparing the board for running the reference design see Chapter 5 Programming Configuring the Hardware This section assumes that board has been set up with appropriate jumper settings and oscillators code has been loaded for the Configuration FPGA and the MCU and that the Reference Design has been loaded into at least FPGA A Note that when the board is shipped all of these steps have already been completed no modification to jumper settings oscillators Config FPGA code or MCU code is required to use the Reference Design The primary interface to the DN6000K10 Reference Design is through RS232 Serial Port connected to one of the four PPC RS232 headers P3 P4 P6 and P7 For more information see the section PPC RS232 Port Setup in Chapter 2 Gettin
17. 3 2 1 Configuration PROM FPGA Programming The Configuration FPGA U13 is programmed using an in system programmable configuration PROM U12 The JTAG chain from the PROM is in a serial daisy chain with the Configuration FPGA allowing simultaneous JTAG programming option of both devices The Configuration FPGA is set to Master Serial Mode using dipswitch 54 At power up the Configuration FPGA provides a configuration clock CFPGA_CCLK that drives the PROM short access time after CEn CFPGA_DONE and OE CFPGA_INITh are enabled data is available on the PROM data 0 pin that is connected to the Configuration FPGA The programming header J7 as shown in Figure 18 is used to download the files to the Configuration PROM FPGA via a Xilinx Parallel IV cable 43 3V 3 3 R137 R150 R160 1K 1K 1K 1 2 3 4 JTAG_PROM_TMS 5 6 7 8 1 9 10 PROM 11 12 H3 y 87832 1420 145 1K Figure 18 Configuration PROM FPGA Programming Header 3 2 2 Design Notes on the Configuration FPGA Oscillator X1 is 48 MHz oscillator used to clock the Configuration FPGA This part is soldered down to the PWB and is not intended to be user configurable The 48 MHz is divided down to 24 MHz in the Configuration FPGA to provide the clock for the micro controller U7 The clock signal is labeled MCU_CLK on the schematic The 48 MHz
18. 4 17 P9 59 TST HDRA43 U27 V36 1 060 BP3N28 P3N28 J4 19 9 60 TST HDRA44 U27 V42 1 061 BP3N27 P3N27 14 21 9 61 TST HDRA45 027 032 1 062 BP3N26 P3N26 14 23 P9 62 TST 46 027 033 11 063 P3N23 12 21 9 63 TST HDRA47 027 035 1 064 P3N22 12 22 9 64 TST HDRA48 027 037 1 065 BP3N19 P3N19 14 25 9 65 TST HDRA49 27 42 11 066 No Connect P9 66 GND 1 067 BP3N18 P3N18 4 27 P9 67 TST HDRA50 927 133 1 068 BP3N15 P3N15 4 29 9 68 TST HDRA51 U27 T36 1 069 BP3N14 P3N14 4 31 P9 69 151 52 1027 831 11 070 P3N9 2 23 P9 70 1517 HDRA53 1027 633 11 071 P3N8 J2 24 9 71 TST HDRA54 U27 R35 1 072 BP3N7 P3N7 14 33 9 72 TST 55 U27 R42 11 073 BP3N6 P3N6 14 35 9 73 TST HDRA56 U27 P31 DN6000K 10 User Guide www dinigroup com 147 BOARD HARDWARE Daughter Card Connections DN6000K10 IO Connections Test Header A Test Signal Name Connector Test Signal Name FPGA Pin Header Header J1 074 BP3N3 P3N3 14 37 P9 74 TST HDRA57 U27 P33 J1 075 BP3N2 P3N2 4 39 P9 75 58 U27 P35 J1 076 BP4N27 P4N27 14 41 P9 76 TST HDRA59 U27 P41 11 077 No Connect P9 77 GND J1 078 BP4N26 P4N26 J4 43 P9 78 TST_HDRA60 U27 N32 J1 079 BP4N21 P4N21 14 45 P9 79 TST HDRAG61 U27 N34 11 080 BPAN20 P4N20 14 47 P9 80
19. 5 2 TxN 29 889 25 FPGAC 5 2 RxP 29 BB7 24 FPGAC SMA2 RxN 29 BB6 J26 SMA1 TxP 80 A8 38 FPGAG_SMA1_TxN 80 A9 J37 FPGAG_SMA1_RxP 80 A7 J46 FPGAG_SMA1_RxN 80 A6 J45 FPGAG_SMA2_TxP 80 4 140 SMA2 TxN 80 A5 39 SMA2 RxP 80 A3 148 SMA2 RxN 80 A2 147 FPGAI 5 1 TxP U U U U U U U U 079 36 142 FPGAI SMA1 TxN 079 37 jai FPGAI SMA1 RxP 079 35 50 FPGAI SMA1 RxN U79 BB34 j49 U U U FPGAI SMA2 79 BB40 44 FPGAI SMA2 TxN 79 BB41 SMA2 RxP 79 BB39 152 DN6000K 10 User Guide www dinigroup com 126 BOARD HARDWARE Signal Name FPGA Pin Connector FPGAI SMA2 RxN U79 BB38 J51 Please note the RocketIO Transceiver performance in Table 20 Table 20 RocketIO Performance Item Speed Grade RocketIO Transceiver FF 3 125 3 125 2 0 PowerPC Processor Block 400 350 300 8 CPU Debug and CPU Trace The DN6000K10 board includes two CPU debugging interfaces for FPGA A C the CPU Debug vertical headers i e JP1 JP2 and the Combined CPU Trace and Debug vertical mictor connector i e 18 and J19 These connectors can be used in conjunction with third party tools or in some cases the Xilinx Parallel Cable IV to debug softwate as it runs on the processor T
20. NK SMARTMEDIA D 0 7 amp CONTROL FPGAA 16 32 64 124 V y XC2VP70 100 FPGA CONFIG BIT FF1704 PLES le 5 4 DDRVIT x SWITCHING 1 25V REGULATOR eis Y FPGAB _ 0 7 XC2VP70 100 EEPROM 8 FF1704 DDRVIT 2 le 5 SWITCHING 1 25 i rj 4 REGULATOR i USB MICRO A 0 15 SERUUM CONTROLLER Aen FPGAC H 12V 20 CYPRESS XC2VPT70 100 SWITCHING a0 FF1704 oue CY7068013 PSU U4 Ue ONOFF switch 7 FPGA 020 7 MODULE gt 120K X6 CONFIGURATION Psuz uss 2 M gt FPGA le 6 us EN 25 VOLTAGE 3 monitor PWARSTn E FPGAE 101524 GI mas SPARTA 4 d reser SWITCH VOLTAGE SOURCES 15 S d 2 1704 CONFIG B PROGRAMMABLE CLOCK source JUMPERS CLOCK SOURCE Y 2 FPGAG JUMPER GRID rere XC2VP70 100 RS232 PORTS x4 5 42 FF1704 1 _ 5 2 FPGAH Y 2 70 100 1704 ROBOCLOCK 6 eoon m 2 062 L FPGAI ATES Lock 5232 MONITOR z xc2vP70 100 INDICATORS PORTS x4 FF1704 1 le JUMPERS 58 FPGA SERIAL
21. THE SOFTWARE TOOLS KKKKKKKKKKKKKKKKKKK FPGA_A MAIN MENU KKKKKKKKKKKKKKKKKKK a b c d e q Run Full Test Suite Test Registers Test Flash Test DDR Test Interconnect Write Memory Location Read Memory Location Display Memory in 8 DWORDS per Line Format Fill Memory with specified DWORD pattern Toggle Mem Owner INTERNAL User Interconnect Test Menu Quit Now tests can be run directly from the embedded PPC processor The menu options are as follows moon Run Full Test Suite Runs options b c d and e Test Registers Runs read write tests on local FPGA registers Test Flash Runs a full set of tests on the Flash takes 4 minutes Test DDR Runs read write tests on the DDR memoties Test Interconnect Runs an inter FPGA test on the physical interconnect Write Memory Location Allows writing to any PPC memory location DDR_BASE 0x80000000 FLASH BASE 0x90000000 REGISTER BASE 0x98000000 Read Memory Location Allows reading any PPC memory location Display Memory Starting from any PPC address lists DWORDs Fill Memory with specified DWORD pattern Allows large chunks of memoty to be filled with a known value Toggle Mem Owner Sets the Memory Arbiter to User PPC or Host Interconnect Test Menu For interconnect debug under construction Note that the full test suite takes about 5 minutes to run abort any test operation u
22. 0x28FF_FFFF Address maps directly to FLASH DDR Phase Shift 0 2 00 0000 0 2 00 0000 R W DDR phase shift value upper WORD is read only and contains Register the current phase shift value lower WORD is write only External Host 0 2 00 0004 0x2C00_0004 R W Write Read register for MCU to issue the following commands Commands Register 0x1 test all functionality 0x2 test registers 0x3 test FLASH 0x4 test DDR s 0 5 test FPGA interconnect To issue a command MCU must write one of the above values to this register The MCU can then poll this register to check if the test 15 done register will return all zeros when finished Status Register 0x2C00 0008 0 2 00 0008 Read only register Status of commands and bus control Bits 16 18 must all be zero for MCU to issue any commands to External Host Command Register Status results can be read after command register is cleared decode for the test results is as follows Bit 0 overall pass fail pass 1 fail 0 Bit 1 register test pass fail Bit 2 flash test pass fail Bit 3 ddr test pass fail Bit 4 interconnect test pass fail Existing 0 2 00 0018 0 2 00 0018 Contains information on what FPGAs are stuffed on the Register DN6000k10 as well as what type of FPGAs they are The register has the following format Bit 0 1 if FPGA A is stuffed 0 otherwise Bit 1 1 if FPGA B is stuf
23. 2 Exit Closes the USBController application 1 1 5 Edit Menu The Edit Menu performs the basic edit commands on the command log in the bottom half of the USBController window The Find option is not currently supported 1 1 6 FPGA Configuration Menu The FPGA Configuration Menu has the following options 1 Refresh Configuration Status Queries to see which FPGA s configured and update the GREEN LEDS in DN6000k10 picture 2 Configure via USB individually After selecting this option a window will pop and ask which FPGA you want to configure and then what bitfile you want to configure the selected FPGA with The status of the FPGA configuration will detailed in the log window and the DN6000k10 will be updated after the bitfile has been transferred 3 Configure via USB using file This option allows the user to configure more than one FPGA over USB at a time To use this option you must DN6000K10 User Guide www dinigroup com 16 INTRODUCTION VIRTEX II AAND 15 create a setup file that contains information on which FPGA s should be configured and what bitfiles should be used for each FPGA file should be in the following format the first character of each line represents which FPGA you want configured a i A D this letter should be followed by a colon and then the path to the bitfile to use for this FPGA The path to the bitfile is realative to the directory where this setup file is
24. DN6000K10 User Guide U79 AW17 www dinigroup com G eG C 122 BOARD HARDWARE Signal Name FPGA Pin DDR FPGA I1 LDM U79 AL21 DDR FPGA BAO U79 AW20 DDR FPGA BA1 U79 AY20 DDR FPGA CASN U79 AT16 DDR FPGA U79 AW16 DDR FPGA CSN U79 AV16 DDR RASN U79 AR16 DDR FPGA WEN U79 AL15 DDR 12 DATAO U79 AW14 DDR I2 DATA1 79 AV14 DDR I2 DATA2 79 15 DDR 12 DATA3 79 AN15 DDR I2 DATA4 79 AU14 e t DDR 12 DATA5 79 AT14 DDR 12 79 AN14 DDR 12 DATA7 79 AM14 DDR 12 DATAS U U U U U U U U 79 13 DDR 12 DATA9 U79 AL13 DDR I2 DATA10 U79 AP13 DDR I2 DATA11 U79 AN13 DDR I2 DATA12 LI 79 AR12 DDR I2 DATA13 U79 AP12 DDR I2 DATA14 79 AT12 DDR_I2_DATA15 79 012 DDR FPGA I2 ADDO 79 AV15 DDR FPGA I2 ADD1 DDR FPGA I2 ADD2 79 AY14 DDR FPGA I2 ADD3 TO AY T5 DDR FPGA I2 ADD4 DN6000K 10 User Guide U U U U79 AU15 U U U79 A V13 Www dinigroup com GS C ec eb Ee e 123 BOARD HARDWARE Signal Name
25. GND 24LC64 TSSOPB no R142 10K Address 00000001 0x01 RAM Space 0x0000 to OxlFFF Figure 12 MCU EEPROM Interface 3 1 2 SRAM External Memory expansion for the MCU is provided as 128k x 8 SRAM U8 Writing to the device is accomplished by taking Chip Enable and Write Enable MEM_WRn inputs low Reading from the device is accomplished by taking the Chip Enable SRAM_CSn and the Output Enable MEM_OEn low while forcing Write Enable high The contents of the memory location specified by the address pins will appear on the IO pins Address space above 2000H is banked through the Configuration FPGA The SRAM interface is shown in Figure 13 MCU 2 0 5 2141 01 10 MCUTD2 MCUAS 1 2 02 11 mum ____13 03 722 MCU_D4_ MOUAS aM mune 15 5 8 05 26 MCUD6 mUa 7716 46 06 257 MCUD7 7147 9 mun BAe 9 gA 7 MCUAT ____20 10 MCU org At E CFPGA 29 12 A13 CFPGA Ai4 30 9 5 31 6 32 w 32 A16 vec A 3 3V MEM_WRn 12 n VCC 1 28 WE 9 5 GND 725 SSS GND CY7C1018CV33 TSOP32 Figure 13 MCU SRAM 3 1 3 MCU FLASH Program mem
26. RCKTIO OSCT Hn U67 15 U78 G21 RCKTIO OSCB Hp U67 11 U78 AT21 RCKTIO_OSCB_Hn U U78 AU21 RCKTIO_OSCT_Ip U U78 G22 U RCKTIO_OSCT_In 68 15 U78 F22 068 11 078 22 RCKTIO In U68 12 U78 AT22 5 Reset Topology 5 1 DN6000K10 Reset The voltage monitor device from Linear Technology P N L TC2900 U5 allows push button reset function that is used to reset the DN6000K10 Figure 30 shows the distribution of the reset signal SYS_RSTn In addition to controlling the reset the power supplies rails 1 5V 2 5V 3 3V and 5V are monitored for under voltage conditions that will cause the assertion of the SYS_RSTn signal LED 1052 2 when lit means that reset is asserted refer the section describing the GPIO LED s DN6000K10 User Guide www dinigroup com 93 BOARD HARDWARE FPGAA 9 XC2VP70 100 U27 FPGAB 2 70 100 U28 1 5V 25 Reset Circuit MCU 43V LTC2900 gt CY7C68013 aN 05 U7 xc2vP70 100 U29 SYS RST FPGAD L gt 2 70 100 U53 FPGA GRSTn FPGAE 2 70 100 052 FPGAF FPGA 2 70 100 XC95288XV ge U13 FPGAG PPC RST gt 2 70 100 U80 FPGAH XC2VP70 100 067 FPGAI XC2VP70 100 U68 Figure 30 Reset Topology Block Diagram Depressing the
27. Status Register 0 8 00 0008 0 8 00 0008 Read only register Status of commands and bus control Bits 16 18 must all be zero for MCU to issue any commands to External Host Command Register Status results can be read after command register is cleared decode for the test results is as follows Bit 0 overall pass fail pass 1 fail 0 Bit 1 register test pass fail Bit 2 flash test pass fail Bit 3 ddr test pass fail Bit 4 interconnect test pass fail t FPGA 0 8 00 0018 0 8 00 0018 Contains information on what FPGAs are stuffed on the egister DN6000k10 as well as what type of FPGAs they The register has the following format Bit 0 1 if FPGA A is stuffed 0 otherwise Bit 1 1 if FPGA B is stuffed 0 otherwise Bit 2 1 if FPGA C is stuffed 0 otherwise Bit 2 1 if FPGA D is stuffed 0 otherwise Bit 2 1 if FPGA E is stuffed 0 otherwise Bit 2 1 if FPGA F is stuffed 0 otherwise Bit 2 1 if FPGA is stuffed 0 otherwise Bit 7 1 if FPGA H is stuffed 0 otherwise Bit 8 1 if FPGA I is stuffed 0 otherwise Bit 9 1 if FPGA is 2vp100 0 if 2vp70 Bit 10 1 if FPGA 2vp100 0 if 2vp70 Bit 11 1 if FPGA is 2vp100 0 if 2vp70 Bit 12 1 if FPGA D is 2vp100 0 if 2vp70 Bit 13 1 if FPGA E is 2vp100 0 if 2vp70 Bit 14 1 if FPGA F is 2vp100 0 if 2vp70 Bit 15 1 if FPGA is 2vp100 0 if 2vp70 Bit 16 1 if
28. Value able Readback and E Property Create ReadBack Data Files Allow SelectMAP Pins to Persist Create Logic Allocation File Create Mask File TN The user can now generate the bit file In the Process for Source window the user must right click on the Generate Programming File process and select Run The bit file will be generated and may be found in the project directory 4 2 Creating Configuration File main txt To control which bit file on the Smart Media card is used to configure which FPGA in SelectMAP mode a file named main txt must be created and copied to the root directory of the Smart Media The configuration process cannot be performed without this file Below is a description of the options that can be set in the file a description of the format this file needs to follow and an example of a main txt file 4 2 1 Verbose Level During the configuration process there are three different verbose levels that can be selected for the serial port messages e Level 0 Fatal error messages file errors e g bit file was created for the wrong part bit file was created with wrong version of Xilinx tools or bitgen options are set incorrectly Initializing message will appear before configuration single message will appear once the FPGA is configured level All messages that Level 0 displays
29. 1 134 P3N78 J24 P11 134 TST HDRC100 U78 D1 11 195 P3N73 2 6 11 135 HDRC101 078 03 J1 136 P3N72 J27 P11 136 TST_HDRC102 U78 E2 J1 137 P3N71 2 33 11 137 HDRC103 UT78F1 1 138 P3N70 12 34 11 138 TST HDRC104 U78 F3 1139 P3N65 5 43 P11 139 HDRC105 U78 G2 1 140 11 140 GND 1 141 P3N64 J5 45 P11 141 TST HDRC106 U78 H2 1 142 P3N61 5 47 11 142 TST HDRC107 1078 11 1 143 P3N60 J5 49 P11 143 TST HDRC108 U78 K1 1 144 P3N59 164 11 144 TST HDRC109 U78 K3 1 145 P3N58 6 3 11 145 HDRC110 07812 J1 146 P3N53 6 5 11 146 TST HDRC111 U78 M2 1 147 P3N52 6 7 11 147 HDRC112 U78N1 1 148 P3N51 2 17 P11 148 TST HDRC113 U78 N3 1 149 P3N50 J218 11 149 TST HDRC114 U78 P2 11 450 P3N45 6 9 11 150 TST HDRC115 1078 82 11 151 11 151 GND 1 152 P3N44 6 11 11 152 IST HDRC116 107801 1 153 P3N41 6 13 P11 153 HDRC117 UT78 V1 1 154 P3N40 16 15 11 154 TST HDRC118 U78 W1 11155 P3N37 J6 17 11 155 TST HDRC119 U78 W2 J1 156 P3N36 J6 19 11 156 TST HDRC120 U78 Y9 1 157 P3N33 J6 21 P11 157 TST HDRC121 U78 AD2 DN6000K 10 User Guide www dinigroup com 169 BOARD HARDWARE Daughter Card Connections DN6000K10 IO Connections Test Header C Test Signal Name Connect
30. 186 ST HDRAT47 ST HDRA69 87 ST HDRAT48 GND 88 188 TST HDHAT49 _ 89 189 ST_HDRATSO TST_HDRA71 90 7190 TST E 91 191 HDRAT52 TST 92 7192 TST HDHA153 93 193 TST 54 TST HDRA74 94 194 75 95 195 GND TST_HDRA76 96 1196 TST 156 ST HDRA77 97 197 TST 157 5 78 98 198 TST 158 GND 99 199 59 12 100 200 TST HDRAT6O 2 203 201 204 58 202 22 205 200 Figure 43 Test Header DN6000K 10 User Guide www dinigroup com 138 BOARD HARDWARE 11 1 1 Test Header Connector Micropax connector 200 pin 15 used as a standard interface to all the Dini Group logic emulation boards This connector has a specified current rating of 0 5 amps contact See datasheet for more information P N 91294 003 11 1 2 Test Header Pin Numbering Figure 44 indicates the pin numbering scheme used on the test headers pt Mounting Holes Figure 44 Test Header Pin Numbering DN6000K 10 User Guide www dinigroup com 139 BOARD HARDWARE 11 2 DN3000K 10SD Daughter Card The Dini Group manufactures a daughter DN3000K10SD card that allows the user connection to the FPGA IO pins The daughter card has the following features Buffered I O Passive and Active Bus Drivers Unbuffered I
31. 2 0 100 125 25150 0456 PUZENG gt REFS xi uis Synthesizer DDR SDRAM FPGA 1058442 DDR ICLK2n BAM x 16 LVDS u83 FPGA_DCLK FPGA DOLKA FPGATOKA FPGA_DCLK FPGA DOLK 8 gt FPGA TCK FPGATCKB FPGA DOLK FPGA T a xd ee FPGA 0 D FPGA TCK D CLK Buffer E CLK Buffer FPGA Y TEM 49 20 07 TOK F m m M Test Test FPGA DOUG eio e 809 Header 80010 H Header B gt Header FPGA DOLK FPGA TCK H p P10 FPGA gt FPGATOKH 7 Figure 21 Clocking Block Diagram The clocking structures for the DN6000K10 include the following features Two user selectable socketed oscillators X2 X3 e One 48 MHz oscillator for the Configuration FPGA X1 DN6000K 10 User Guide www dinigroup com 72 BOARD HARDWARE Two RoboclockIITM CY7B994V Multi Phase PLL Clock Buffers External Differential User Clock Input Connectors J1 J4 System Oscillator X4 Dedicated Oscillators The clock source selection grid formed by JP5 distributes clock signals CLOCKA and CLOCKB to two Roboclock PLL clock buffers 062 063 The clock outputs from the buffers are dispersed throughout the board An external differential clock input
32. BP3N27 P3N27 4 21 P11 61 IST HDRC45 U78 AK2 71 062 BP3N26 P3N26 4 23 P11 62 HDRCA46 U78 AL2 1 063 P3N23 2 21 P11 63 TST_HDRC47 U78 AM1 1 064 P3N22 2 22 P11 64 IST HDRC48 U78 AM3 1 065 BP3N19 P3N19 14 25 P11 65 5 49 U78 AN2 1 066 No Connect P11 66 GND 1 067 BP3N18 P3NI18 4 27 P11 67 IST HDRC50 U78 AP1 11 068 BP3N15 P3N15 4 29 P11 68 5 HDRC51 U78 AR2 11 069 BP3N14 P3N14 4 31 P11 69 HDRC52 U78 AT1 11 070 P3N9 12 23 P11 70 TST HDRC53 U78 AT3 J1 071 P3N8 J2 24 P11 71 54 U78 AU2 10072 BP3N7 P3N7 14 33 P11 72 IST HDRC55 U78AV1 J1 073 BP3N6 P3N6 14 35 P11 73 IST HDRC56 U78 AV3 1 074 BP3N3 P3N3 14 37 P11 74 IST HDRC57 U78 AW2 1 075 BP3N2 P3N2 14 39 P11 75 IST HDRC58 U79 D1 J1 076 BP4N27 P4N27 4 41 P11 76 IST HDRC59 U79 D3 J1 077 No Connect P11 77 GND J1 078 BP4N26 P4N26 4 43 P11 78 IST HDRC60 79 2 DN6000K 10 User Guide www dinigroup com 166 BOARD HARDWARE Daughter Card Connections DN6000K10 IO Connections Test Header C Test Signal Name Connector Test Signal Name FPGA Pin Header Header J1 079 BPAN21 P4N21 14 45 P11 79 TST_HDRC61 U79 F1 J1 080 BP4N20P4N20 14 47 P11 80 TST HDRC62 U79 F3 J1 081 No Co
33. Connection between FPGA s and DDR PLL Clock Drivers Signal Name FPGA Pin DDR PLL Clock Driver DDR ACLKp U27 J22 U36 5 DDR ACLKn U27 K22 U36 6 DDR_CCLKp U29 AU22 018 5 DDR 1129 22 018 6 DDR DCLKp U53 AU22 U61 5 DN6000K 10 User Guide www dinigroup com 88 BOARD HARDWARE DDR DCLKn U53 AT22 DDR FCLKp 05122 DDR U51 K22 DDR GCLKp 080 22 DDR 080 622 DDR ICLKp U79 AU22 DDR ICLKn U79 A 122 4 6 Power PC PPC Clock Sytem Clock A 3 3 V half can oscillator X4 and the signal SYS CLK provide an external clock source for the PPC The oscillator is socketed and the DN6000K10 is shipped with a 100MHz oscillator refer to Figure 28 43 3V R537 2 2R C1784 0 047uF R536 3 RSYS CLK A SYS CLK 33 Figure 28 External Clock 4 6 1 Clocking Methodology Refer to the Xilinx application notes for more information on this subject 4 6 2 Connections between FPGA s and System Clock Buffer The connection between the FPGA s and the external oscillator buffer are shown in Table 14 Table 14 Connection between FPGA and External PPC Oscillator Signal Name FPGA Pin DDR PLL Clock Driver SYS ACLKp U27 AT21 U65 3 SYS ACLKn U27 AU21 U65 2 SYS_BCLKp U28 AT21 965 5 SYS BCLKn U28 AU21 U65 6 SYS CCLKp U29 K21 U65 10 DN6000K 10 User Guide www dinigroup
34. DDR_A1_DATAO U27 H24 DDR A1 DATA1 U27 G24 DDR A1 DATA2 U27 K24 DDR A1 DATA3 U27 24 DDR A1 DATA4 U27 M24 DDR A1 DATAS5 U27 L24 DDR A1 UZT H25 DDR 1 DATAT7 U27 G25 DN6000K 10 User Guide Www dinigroup com 107 BOARD HARDWARE Signal Name FPGA Pin DDR A1 DATAS U27 G26 DDR A1 DATA9 U27 F26 DDR A1 DATA10 U27 26 DDR A1 DATA11 U27 H26 DDR A1 DATA12 U27 K26 DDR A1 DATA13 U27 L26 DDR A1 DATA14 U27 M26 DDR A1 DATA15 U27 M25 DDR FPGA A1 ADDO U27 F24 DDR 1 ADD1 U27 E24 DDR FPGA A1 ADD2 U27 L25 DDR FPGA A1 ADD3 U27 K25 DDR FPGA A1 ADD4 U27 G27 DDR FPGA A1 ADD5 U27 H27 DDR_FPGA_A1_ADD6 U27 K27 DDR_FPGA_A1_ADD7 U27J27 DDR_FPGA_A1_ADD8 U27 M27 DDR_FPGA_A1_ADD9 27 127 DDR FPGA A1 ADD10 27 28 DDR A1 ADD11 21 29 DDR FPGA A1 ADD12 27 F28 DDR FPGA A1 ADD13 27 28 DDR A1 0008 27 27 DDR FPGA A1 1005 27 226 DDR FPGA A1 UDM U U U U U U U U 27 D27 DDR FPGA A1 LDM U27 C25 DDR FPGA A1 BAO U27 H23 DDR FPGA A1 U27J23 DDR FPGA A1 CASN DN6000K 10 User Guide U27 C24 www dinigroup com ct Le pee Gea e 108 BO
35. GPIO Header P1 as shown in Figure 15 allows for connection to the unused MCU IO pins The user can utilize this IO as required e g external interrupts external IO expansion etc Note The interface is LVTTL33 and the device is not 5V tolerant refer to the Cypress datasheet for CY7C68013 for more information Pi MCU_GPIOO 2 1 JE 4 3 GPIO5 GPIO2 6 5 E MCU GPIO3 8 7 E GPIO4 10 9 Figure 15 MCU General Purpose IO Connector 3 15 MCU USB 2 0 Interface Communication with the system is via the USB connector JJ which interfaces directly with the MCU The USB interface connector is a type B receptacle as shown in Figure 16 The CM1213 03 04 provides ESD protection on the USB ports R4 VBUS VBUS PWR VALID R3 62K GND SHIELD GND SHIELD 6 4 Figure 16 USB Connector DN6000K10 User Guide www dinigroup com 65 BOARD HARDWARE 3 1 6 RS232 Interface An RS232 serial port P2 is provided for low speed communication with the MCU The RS 232 standard specifies output voltage levels between 5V to 15V for logical 1 and 5V to 15V for logical 0 Input must be compatible with voltages in the range of 3V to 15V for logical 1 and 3V to 15V for logical 0 This ensures data bits are read correctly even at maximum cable lengths between DTE and DCE specified as 50 feet The RS 232 standard has two primary modes of operation Data Terminal Equipment and Data Com
36. PPCC_JTAG_TCK U29 AD33 2 7 JTAG 5 U29 AD34 2 7 DBG U29 AC36 2 7 8 2 The CPU Trace port accesses the real time trace debug capabilities built into the PowerPC 405 CPU core Real time trace debug mode supports real time tracing of the instruction stream executed by the processor In this mode debug events are used to cause external trigger events An external trace tool uses the trigger events to control the collection of trace information The broadcast of trace information occuts independently of external trigger events trace information is always supplied by the processor Real time trace debug does not affect processor performance Real time trace debug mode is always enabled However the trigger events occur only when both internal debug mode and external debug mode are disabled Most trigger events are blocked when either of those two debug modes is enabled Information on the trace debug capabilities how trace debug works and how to connect an external trace tool is available in the RISCWatch Debugger User s Guide DN6000K 10 User Guide www dinigroup com 129 BOARD HARDWARE 8 2 1 CPU Trace Connectors Figure 38 shows J18 the vertical header used to trace the operation of software in the PPC of FPGA there is another connector on FPGA C Agilent Windriver has defined a Trace Port Analyzer TPA port for the PowerPC 4xx line of CPU cores that
37. ROBOT FBFO ROBOTFBDSO __ 83 28051 ROBO FBDIS 5 ROBOLFO 86 ROBOT Fi B7 ROBOT 050 B8 ROBOT DST 9 JP7B ROBO2 REFSEL al ROBO2 FS Bi 2 B2 3 ROBO2 FBDSO B3 A4 FBDS1 B4 P ROBO2_FBDIS B6 RoBo F ____ 87 50802 B8 A9 B9 A10 Figure 25 RoboClock Configuration Jumpers 4 3 4 Useful Notes and Hints The RoboClock consistently outputs 32 5MHz signals in cases of improper settings or unacceptable clock inputs This was observed when the CY7B994V part was operating at a nominal frequency of 36 4MHz with FS set LOW Identical clocks were sent to PLL2B and PLL2BN For the CY7B994V part the operating frequency can reach up to 200 MHz Howevet the maximum output frequency is 185MHz This means when 185 MHz lt lt 200MHz the output divider must be set to at least 2 Otherwise the RoboClocks will output garbage DN6000K 10 User Guide www dinigroup com 84 BOARD HARDWARE 4 3 5 Customizing the Oscillators The user can customize the frequency of the clock networks by stuffing different oscillators in X2 and X3 DN6000K10 is shipped with a 14 318MHz oscillator in location and 33 333 oscillator in X2 The RoboClocks are not 5V tolerant so 3 3V oscillators are necessary The Dini Group suggests Digi Key http www digikey com as a possible source for the o
38. Repetitive material that has allow block block_name been omitted loct loc2 locn Prefix or suffix Indicates hexadecimal notation Read from address 0x00110373 returned 4552494h 22 Letter P or n Signal is active low INTZ is active low inta is active low 3 2 Online Document The following conventions are used in this document Convention Meaning or Use Example DN6000K 10 User Guide ww w dinigroup com 3 ABOUT THIS MANUAL Blue Text Cross refetence link to a See the section Additional location in the cuttent file Resoutces for details another file in the current Refer to Title Formats in document Chapter 1 for details Red Text Cross reference link to a See Figure 2 5 in the location in another document Virtex IT Handbook Blue underlined text Hyperlink to a website URL Go to http www xilinx com for the latest datasheets 4 Relevant Information Information about PCI can be obtained from the following sources Reference the PCI Special Interest Group for the latest in PCI PCI X Specifications PCI Special Interest Group http www pcisig com 2575 NE Kathryn St 17 Hillsboro OR 97124 FAX 603 693 8344 Other recommended specifications include PCI Industrial Computer Manufacturers Group PICMG http picmg org 401 Edgewater Place Suite 500 Wakefield MA 01880 USA TEL 781 224 1
39. TST HDRAO dac L112 TST TST HDHAT 19 TST_HDRA81 TST 14 114 cal 5 HDRA3 15 715 TST TST_HDRAG 16 116 TST 5 171 117 E 18 118 GND ST 19 7119 TST 6 TST HDRAB 20 120 ST 7 TST HDRAS 7121 5 GND 22 122 9 ST 2317 123 ST_HDRASO ST HDRATT 24 7 124 ST ST HDRAT2 25 gt 125 ST HDRA92 TST_HDRATS 26 126 HDHA93 TST 27 127 TST HDRA94 5 28 128 95 ST HDRAT6 29 ST HDRAT7 30 130 7 HDRAS6 ST Si TST HADRATI 32 132 TST HDRAJS GND 33 433 TST HDHASS TST HDRA20 34 134 TST ST 3537 135 HDRA101 ST HDRAZ2 36 136 ST 2 87 187 ST TST HDHA24 38 7138 5 HDRA104 TST HDRA25 39 139 TST HDRA105 TST HDRA26 40 740 GND TST 27 4 41 TST_HDRATO6 TST HDRA28 42 142 jl 43 7 143 __ 5 8 _ GND 44 7 144 9 TST 45 145 __151_ 110 TST 46 7146 __ 2 47 7147 TST HDRA112 TST HDRA33 48 7 148 TST HDRATI3 TST_HDRA34 49 7 449 _TST_HD
40. combines the CPU Trace and the CPU Debug interfaces onto a single 38 pin Mictor connector This provides for high speed controlled impedance signaling x 4 xs PPCA_DBG_HALTH 7 5 9 PPCA JTAG TDOX 11 PPCA TRC VSENSE 13 PPCA JTAG TCKX 15 13 TMS 17 15 16 TD 19 17 18 PPCA JTAG 21 19 20 2 2 510 23 23 24 520 25 26 Som 27 28 Som 29 30 Siem 31 32 at 33 34 Sem 35 36 TRO x 37 38 CONN MICTOR38 Figure 38 Combined Trace Debug Connector Pinout 8 2 2 Combined CPU Trace Debug Connection to FPGA s The connection between the Combined CPU Trace and Debug Port connectors is shown in Table 22 The connections to the FPGA ate shared with the CPU Trace and CPU Debug interfaces discussed in previous sections Table 22 Combined CPU Trace Debug connection to FPGA Signal Name FPGA Pin Connector PPCA U27 137 J18 6 PPCA_DBG_HALTn U27 F36 J18 7 PPCA_TRC_VSENSE N A 18 12 PPCA U27 E36 JA711 TAG 057 118 15 JTAG TMS U27 E37 J18 17 PPCA JTAG TDI U27 D36 J18 19 PPCA_JTAG_TRSTn GND 18 21 TS1O 027 837 18 24 PPCA TRC 1520 U27 P37 J18 26 TS1E U27 N37 J18 28 DN6000K10 User Guide Www dinigroup com
41. gi 3 CONFIGURING HYPERTERMINALET 255 06 toe rer ERE EVEN EXER ERAN ACER RENTUR XX 4 CONFIGURING THE FPGA USING SELECTMA D tenente TEE A tenete 4 1 Bit File Generation for Select MAP Configuration i 4 2 Creating Configuration File RR HE 4 2 1 Verbose 4 2 2 Sanity Check 42 3 Foimatof 3 Starting SelectMAP COnfi guration 4 3 1 Description of Main Menu Options 4 4 BOARD 60 1 INTRODUCTION TO THE BOARD Rt dp Ee ede cad a PME 60 DN6000K1I0 RR RR UE ERR ERR RR ette Re 61 2 eR 62 24 FPGA 2VP70 Facts 62 3 FPGA CONFIGURATION 63 3 1 Micro Controller Unit MCU 63 3 1 1 EEPROM Interface 64 3 1 2 MCU SRAM 64 3 1 3 MCU FLASH 23 3 1 4 RR 65 3 1 5 MCU USB 2 0 Intetface ee tec rot ee bee OR CHI ROPA eet i ae en 65 3 1 6 RS232 Interface 66 3 2 Configuration FPGA 66 3 2 1 Configuration PROM FPGA Programming 68 3 22 Design Notes on the Configuration FPGA
42. m A err u x 5 ey 9 N 8 N 2 EN Y P 4 XILINX XILINX N _ _FPGACN y k XC2VP70 100 XC2VP70 100 XC2VP70 100 4 FF1704 FF1704 TENIS SMA 1 SMA 2 1 Figure 36 RocketIO Block Diagram 7 1 SMA Connectors The SMA connectots allow fot direct connection the FPGA MGT interfaces 711 FPGA to SMA Connector The DN6000K10 board provides two discrete MGT channels for A C G I The connection between the FPGA and the SMA connectors is fairly simple involving only one wire per connector as well as a few capacitors and resistors to AC couple the signals These connections are also shown in Table 19 Table 19 Connections between FPGA and SMA Connectors Signal Name FPGA Pin Connector FPGAA_SMA1_TxP U27 A40 9 SMA1 TxN U27 A41 18 DN6000K 10 User Guide www dinigroup com 125 BOARD HARDWARE Signal Name FPGA Pin Connector FPGAA SMA1 RxP U27 A39 J13 FPGAA SMA1 RxN U27 A38 J12 FPGAA SMA2 TxP U27 A36 SMA2 TxN 127 437 10 SMA2 RxP U27 A35 J15 FPGAA SMA2 RxN U27 A34 14 FPGAC 5 1 TxP U29 BB4 J27 FPGAC SMA1 TxN 29 BB5 30 FPGAC_SMA1_RxP 29 BB3 28 FPGAC_SMA1_RxN 29 882 31 FPGAC SMA2 TxP 29 BB8 23
43. uset s purpose 5 The file main txt is NOT case sensitive 6 Example of main txt statt of file main txt Verbose level 2 Sanity check y FPGA fpgaF bit the line above configures FPGA with the bit file fpgaF bit end of main txt Given the above example file Verbose level is set to 2 a sanity check on the bit files will be performed and FPGA will be configured with file fpgaF NOTE All configuration file names have a maximum length of eight 8 characters with an additional three for the extension Do not name your configuration bit files with long file names In addition all file names should be located in the root directory of the Smart Media card no subdirectories or folders are allowed Since the main txt file controls which bit file is used to configure the FPGA the Smart Media card can contain other bit files DN6000K10 User Guide www dinigroup com 54 PROGRAMMING CONFIGURING THE HARDWARE 4 3 Starting SelectMAP Configuration If using the reference design SmartMedia card that came with the DN6000K10 then no files need to be copied to the card Otherwise copy your bit files and main txt to the root directory of the SmartMedia card using the FlashPath floppy adapter some other means Make sure the dipswitch 52 is set for SeleccMAP as shown in Table 2 Table 2 52 Dipswitch Configuration Settings Signal Name Pins Status FPGA MSELO Pins1 amp 8 Close
44. 0 if 2vp70 Bit 11 1 if FPGA C is 2vp100 0 if 2vp70 Bit 12 1 if FPGA D is 2vp100 0 if 2vp70 Bit 13 1 if FPGA E is 2vp100 0 if 2vp70 Bit 14 1 if FPGA F is 2vp100 0 if 2vp70 Bit 15 1 if FPGA is 2vp100 0 if 2vp70 Bit 16 1 if FPGA H is 2vp100 0 if 2vp70 Bit 17 1 if FPGA Lis 2vp100 0 if 2vp70 180 Start End Address Read Description Address Write DDR 1 U78 0x6000_0000 0 60 _ R W Address maps directly to DDR 1 DDR 2 U85 0x6100 0000 Ox61FF_FFFF Address maps directly to DDR 2 085 only avail if 2vp100 FLASH U88 0 6800 0000 0 6 FFFF R W Address maps directly to FLASH DDR Phase Shift 0x6C00_0000 0x6COO 0000 R W DDR phase shift value upper WORD is read only and contains Register the current phase shift value lower WORD is write only External Host 0 6 00 0004 0x6C00_0004 R W Write Read register for MCU to issue the following commands Corimands Register 0x1 test all functionality 0x2 test registers 0x3 test FLASH 0x4 test DDR s 0 5 test FPGA interconnect To issue a command the MCU must write one of the above values to this register The MCU can then poll this register to check if the test is done register will return all zeros when finished Status Register 0 6 00 0008 0 6 00 0008 R Read only register Status of commands and bus control Bits 16 18 must all be zero for MCU to i
45. 130 BOARD HARDWARE Signal Name FPGA Pin Connector TS2B 027 137 18 30 153 U27 K37 18 32 PPCA 154 027 37 18 34 155 U27 H37 J18 36 PPCA_TRC_TS6 U27 G37 J18 38 PPCC_TRC_TCK U29 AN37 J19 6 PPCC_DBG_HALTn U29 AC36 J19 7 PPCC TRC VSENSE 19 12 PPCC_JTAG_TDO U29 AC34 1811 PPCC_JTAG_TCK U29 AD33 119 15 PPCC_JTAG_TMS U29 AD34 19 17 PPCC TDI U29 AC33 11919 PPCC JTAG TRSTn GND 1921 TRG 1510 U29 AM37 19 24 1520 U29 AK37 19 26 PPCC TRC U29 AJ37 J19 28 152 U29 AH37 19 30 153 U29 AG37 19 32 1984 U29 AF37 J19 34 PPCC_TRC_TS5 U29 AD37 719 96 156 U29 AC37 19 38 9 GPIOLED s 9 1 Status Indicators The DN6000K10 uses DS1 052 to visually indicate the status of the board 051 is controller by 07 and the Configuration 013 controls DS2 DN6000K 10 User Guide www dinigroup com 131 BOARD HARDWARE Az DA ma i 6007 5556 coop coe 4 Table 23 lists the function of the CPLD The LED s is number from left to right CPLD LEDOn CPLD_LED3n Table 23 CPLD LED s Signal Name Description CFPGA_LEDn0 Blinks when configuring over USB CFPGA_LEDn1 Blinks when reading data from the SmartMedia card CFPGA_LEDn2 B
46. DDR_FPGA_C1_UDM 29 AW31 DDR_FPGA_C1_LDM DDR FPGA C1 BAO 29 23 DDR FPGA 1 U U U29 AU33 U U 29 AN23 DDR_FPGA_C1_CASN U29 AP23 DDR_FPGA_C1_CKE U29 AR32 DDR_FPGA_C1_CSN U29 AL28 DDR_FPGA_C1_RASN 29 AR23 DDR FPGA C1 WEN 29 27 e EE DDR C2 DATAO DN6000K 10 User Guide 29 AT29 www dinigroup com 111 BOARD HARDWARE Signal Name FPGA Pin DDR C2 DATA1 U29 AU29 DDR C2 DATA2 U29 AN28 DDR C2 DATA3 U29 AM28 DDR C2 DATA4 U29 A V29 DDR C2 DATA5 U29 AW29 DDR C2 DATAG U29 AY28 DDR C2 7 U29 AY29 DDR C2 DATAS 29 25 DDR C2 DATA9 29 AN25 DDR C2 DATA10 29 AV25 DDR C2 DATA11 29 AV26 DDR C2 DATA12 29 AR25 DDR C2 DATA13 U U U U U U 29 25 DDR 2 14 U29 AN24 DDR C2 15 U29 AP24 DDR FPGA C2 ADDO U29 AL26 DDR FPGA C2 ADD1 U29 AL25 DDR FPGA C2 ADD2 U29 AP26 DDR FPGA C2 ADD3 U29 AR26 DDR FPGA C2 ADD4 U29 AT26 DDR_FPGA_C2_ADD5 U29 AU26 DDR_FPGA_C2_ADD6 U29 AL24 DDR FPGA C2 ADD7 U29 AM24 DDR FPGA C2 ADDS8 U29 AR24 DDR FPGA C2 ADD9 U29 AT24 DDR_FPGA_C
47. Displays configuration type should be DN6000K 10 User Guide ww w dinigroup com 52 PROGRAMMING CONFIGURING THE HARDWARE Displays current FPGA being configured if the configuration type is set to SeleccMAP Displays a message at the completion of configuration for each FPGA configured e Level 2 All messages that Level 1 displays Options that are found in main txt file names for each FPGA as entered in main txt Maker ID device ID and size of Smart Media card All files found on Smart Media card If sanity check is chosen the bit file attributes will be displayed part package date and time of the bit file During configuration will be printed out after each block 16 KB has successfully been transferred from the Smart Media to the current FPGA 4 2 2 Sanity Check The Sanity Check if enabled verifies that the bit file was created for the right part the right version of Xilinx was used and the bitgen options were set correctly If any of the settings found in the bit file are not compatible with the FPGA a message will appear from the serial port and the user will be asked whether or not they want to continue with the bit file Please see the section Bit File Generation for SeleccMAP Configuration for details on which bitgen options need to be changed from the default settings 4 2 3 Format of main txt The format of main txt file is as
48. FLASHI_DATAO U79 AN3 FLASHI U79 AP2 FLASHI DATA2 U79 AR3 FLASHI DATA3 U79 AT2 FLASHI_DATA4 U79 AU1 U U FLASHI DATA5 A13 FLASHI DATAG 79 AV2 FLASHI DATA7 U79 AW1 FLASHI_DATA8 U79 AP1 FLASHI DATA9 U79 AR2 FLASHI DATA10 U79 AT1 FLASHI DATA11 U79 AT3 FLASHI_DATA12 79 AU2 FLASHI_DATA13 79 AV1 FLASHI_DATA14 79 AV3 FLASHI DATA15 79 AW2 FLASHI CEN 79 AN1 FLASHI OEN 79 AN2 FLASHI WEN U79 AH1 FLASHI WPN U79 AH3 U U U U U U ere CL GGG 6 2 DDR SDRAM Double Data Rate DDR SDRAM represents enhancement to the traditional SDRAM Instead of data and control signals operating at the same frequency data operates at twice the clock frequency while address and control operate at the base clock frequency In other words the data is written or read from the device on every clock transition or twice per clock cycle This effectively doubles the throughput of the memoty device The trade off for such an improvement in throughput is increased complexity in interface logic to the DDR memoty as well as increased complexity in routing the DN6000K 10 User Guide www dinigroup com 103 BOARD HARDWARE DDR signals on the printed circuit board Additionally this memory has the same latencies as standatd SDRAM so that while the data transfers are twice as fas
49. Guide www dinigroup com 78 BOARD HARDWARE with two feedback output clocks Two sets of eight output clocks are jumper selectable fot each chip The feedback clocks are controlled separately Eighteen configurable outputs each drive terminated transmission lines with impedances as low as 50 while delivering minimal and specified output skews at LVTTL levels refer to Figure 24 The outputs are arranged in five banks Banks 1 to 4 of four outputs allow a divide function of 1 to 12 while simultaneously allowing phase adjustments in 625 ps 1300 ps increments up to 10 4 ns One of the output banks also includes an independent clock invert function The feedback bank consists of two outputs which allows divide by functionality from 1 to 12 and limited phase adjustments Any one of these eighteen outputs can be connected to the feedback input as well as driving other inputs Selectable reference input is a fault tolerance feature which allows smooth change over to secondary clock source when the primary clock source is not in operation The reference inputs and feedback inputs are configurable to accommodate either LVTTL ot Differential LVPECL inputs The completely integrated PLL reduces jitter Please refer to the datasheet for more detailed information DN6000K10 User Guide www dinigroup com 79 BOARD HARDWARE Ms 2 D LOCK Phase Control Logic FBSEL VCO REFA Detector FSB Divide
50. J7 47 P10 96 FD90 and 051 3 U53 AV2 1 097 No Connect P10 97 U53 AW1 1 098 No Connect P10 98 POST land Usi Di DN6000K 10 User Guide www dinigroup com 157 BOARD HARDWARE Daughter Card Connections DN6000K10 IO Connections Test Header B Test Signal Name Connector Test Signal Name FPGA Pin Header Header 112099 No Connect 10 99 GND J1 100 No Connect P10 100 12V J1 101 No Connect P10 101 GND J1 102 MBCK1 J2 27 P10 102 m es U51 AN22 1 103 No Connect P10 103 T1 5V 1 104 12 28 10 104 GND 1 105 No Connect P10 105 3 3V 11 407 No Connect P10 107 GND 11 108 ECLK1 5 7 10 108 GND J1 109 No Connect P10 109 GND J1 110 No Connect P10 110 GND U53 D1 and 11111 P2N5 J5 15 P10 111 FD1 USLAWA U53 D3 and 11 112 P2N4 J5 17 P10 112 FD3 USLAW3 U53 E2 and J1 113 P2NX11 12 2 10 113 FD5 051 U53 F1 and J1 114 P2NX10 2 1 10 114 FD7 051 U53 F3 and J1 115 P2NX9 5 19 210 115 FD9 U51 AU3 U53 G2 and J1 116 P2NX8 15 21 10 116 2011 051 2 U53 H2 and J1 117 P2NX3 J5 23 P10 117 FD13 U51 AR2 11 118 No Connect P10 118 GND 053 1 J1 119 P2NX2 J5 25 P10 119 FD15 51 DN6000K 10 User Guide www dinigroup com 158 BOARD HARDWARE Daughter Card Connections DN6000K10 IO Connections Test Header B
51. MCU CLK High Speed USB SM D 0 7 GPIF_RDYn GPIF Interface to the SmartMedia Data Bus SM 0 7 Control Signals SM REn SM WEn SM ALE SM CLE SM CEn SM RDYBUSYn e Banked Address to the SRAM FLASH Upper Address Signals CFPGA_A 13 19 e FPGA Configuration Serial SelectMap Data Bus for FPGA _100 7 Data Bus for FPGA _20 0 7 Data Bus for FPGA G H I FPGA_3D 0 7 Control Signals FPGA_PROGn_A FPGA_RD WRn_A FPGA_CSn_A FPGA_BUSY_A these signals are reproduced for FPGA A to FPGA I Clock FPGA DCLK FPGA Configuration JTAG JTAG Signals TDI FPGA DONE TDO FPGA 5 ABC FPGA 5 DEF FPGA 5 GHI SRAM Chip Select Generation Signal SRAM_CSn e FLASH Chip Select Generation Signal FLASH CSn e FPGA Configuration MODE Select DipSwitch Signals FRGA_MSEL 0 3 Interface to the UART Connectors RS232Signals from the FPGA s PPCA RXD PPCI TXD PPCI RXD for FPGA A to I DN6000K 10 User Guide www dinigroup com 67 BOARD HARDWARE RS232Signals to the Connectors TXD1 PPC_TXD2 TXDA PPC_RXD1 PPC RXD2 RXD3 PPC_RXD4 PPC MONI PPC MONA e LED Indicators Signals CFPGA_LEDn 0 3 GPIO between Configuration FPGA and FPGA s 9 Signals MB 1 40
52. TST HDRAG62 U27 N36 11 081 No Connect P9 81 5 HDRAG3 U27 N42 11 082 No Connect P9 82 TST 4 U27 M32 11 083 No Connect 9 83 TST HDRA65 U27 M34 11 084 No Connect P9 84 TST HDRA66 U27 M35 11 085 No Connect P9 85 5 HDRAG7 U27 M41 11 086 No Connect P9 86 HDRA68 027 134 11 087 No Connect P9 87 5 HDRAG69 027 136 J1 088 No Connect 9 88 GND 11 089 No Connect P9 89 TST HDRA70 U27 K34 11 090 No Connect P9 90 TST HDRAT71 U27 K36 1 091 No Connect P9 91 TST HDRAT72 U27 K42 11 092 No Connect P9 92 TST_HDRA73 027 36 112093 No Connect 9 93 TL5V 11 094 No Connect P9 94 TST HDRA74 U27 H41 11 095 7 17 45 P9 95 TST HDRAT5 U27 G42 11 096 P4NX6 J7 47 P9 96 TST HDRA76 U27 F42 11 097 No Connect p9 97 HDRAT77 027 42 11 098 No Connect P9 98 5 HDRATS8 U27 D42 11 099 No Connect 9 99 GND DN6000K 10 User Guide www dinigroup com 148 BOARD HARDWARE Daughter Card Connections DN6000K10 IO Connections Test Header A Test Signal Name Connector Test Signal Name FPGA Pin Header Header 1 100 No Connect P9 100 12V J1 101 No Connect P9 101 GND TST_HDRA_CL J1 102 MBCK1 J2 27 P9 102 KIN U27 AT22 11 103 No Connect P9 103 1 5V J1 104 MBCKO 12 28 9 104 GND 11 105 No Connect P9 105 3 3V J1 107 No Conn
53. Test Signal Name Connector Test Signal Name FPGA Pin Header Header J1 120 P3NX11 J229 Pio120 PN and J1421 P3NX10 2 30 P10 121 1 122 P3NX7 J231 P10 122 ER 1 123 P3NX6 232 10123 Oe J1 124 P3NX3 3527 Pi0124 rp2s and J1 125 P3NX2 529 P10 125 gt 11 126 P3NX1 1531 P10 126 Fp29 DAR 1 127 P3NXO J5 33 P10 127 puc ecce J1 128 P3N85 J5 35 P10 128 ED33 ad 1 129 No Connect 10 129 GND 11 130 P3N84 1537 P10 130 Fb36 71 131 P3N81 539 P10 131 05202 1 132 P3N80 1541 P10 132 055 24 1 133 P3N79 J23 10 133 1 134 P3N78 10 134 1 135 P3N73 J26 10 135 ma tat ane DN6000K10 User Guide Www dinigroup com 159 BOARD HARDWARE Daughter Card Connections DN6000K10 IO Connections Test Header B Test Signal Name Connector Test Signal Name FPGA Pin Header Header U53 AA3 J1 136 P3N72 J2 7 P10 136 21047 and U51 AB3 U53 AB3 J1 137 P3N71 J2 33 P10 137 FD49 and U51 AA3 11 138 P3N70 12 34 10 138 TST HDRB104 U52 D1 1 139 P3N65 J5 43 10 139 TST_HDRB105 U52 E1 J1 140 No Connect P10 140 GND 11 141 P3N64 J5 45 10 141 TST HDRB106 U52 F1 1 142 P3N61 J5 47 10 142 TST_HDRB107 U52 G1 J1 143 P3N60 J5 49 10 143 TST_HDRB108 U52 H2 11 144 P3N59 J6 1 P10 1
54. U27 W36 11 156 P3N36 16 19 P9 156 IST 120 U27 W37 11 157 P3N33 J6 21 P9 157 TST_HDRA121 U27 W42 J1 158 P3N32 J6 23 P9 158 TST_HDRA122 U27 V32 14 159 P3N31 J2 44 9 159 TST_HDRA123 U27 V35 J1 160 P3N30 J2 45 P9 160 TST_HDRA124 U27 V41 J1 161 P3N25 J6 25 P9 161 TST_HDRA125 027 031 J1 162 No Connect P9 162 GND 11 163 P3N24 16 27 P9 165 TST_HDRA126 U27 U34 11 164 P3N21 J6 29 P9 164 TST_HDRA127 027 036 1 165 P3N20 16 31 P9 165 128 027 041 11 166 P3N17 J6 33 29 166 151 29 927 181 11 167 P3N16 16 35 P9 167 TST_HDRA130 027 132 J1 168 P3N13 J6 37 9 168 TST_HDRA131 U27 135 1 169 P3N12 J6 39 P9 169 TST_HDRA132 U27 T41 J1 170 P3N11 12 47 P9 170 TST_HDRA133 U27 R32 P3N10 J2 48 P9 171 TST_HDRA134 U27 R34 1172 P3N5 J6 41 P9 172 15 135 U27 R41 1473 No Connect P9 173 GND J1 174 P3N4 16 43 9 174 TST_HDRA136 U27 P32 11 175 P3N1 16 45 9 175 HDRA137 U27 P34 11 176 J6 47 9 176 TST_HDRA138 U27 P36 P4N25 17 9 177 TST_HDRA139 U27 P42 11 178 P4N24 7 3 P9 178 TST_HDRA140 027 331 DN6000K10 User Guide Www dinigroup com 151 BOARD HARDWARE Daughter Card Connections DN6000K10 IO Connections Test Header A Test Signal Name Connector Test Signal Name FPGA Pin Header Head
55. USB J3 the Cypress MCU RS232 port P2 The USB PC application be found product Source Code USBController USBController exe This application allows the user to read write to different FPGA addresses and also perform tests on the DDR FLASH internal registers and interconnect between the FPGA s Description of Main Menu Options The following 9 tables are the address maps for each FPGA when communicating through USB or via the RS232 port on the MCU P2 Please note these address maps are not the same for communication through the PPC RS232 port menus please see Using the Reference Design for a description Also note that The Dini Group reference design provided with the DN6000k10 must be loaded in each of the existing FPGA s for the following address maps to be valid www dinigroup com 12 174 FPGAA Start End Address Read Description Address Write DDR 1 U32 0 0000 0000 FFFF Address maps directly to DDR 1 DDR 2 U22 0 0100 0000 FFFF Address maps directly to DDR 2 022 only avail if 2vp100 FLASH 015 0 0800 0000 FFFF Address maps directly to FLASH DDR Phase Shift 0 0 00 0000 0x0COO 0000 R W DDR phase shift value upper WORD is read only and contains Register the current phase shift value lower WORD is write only External Host 0x0C00_0004 0 0 00 0004 R W Write
56. VIRTEX II AAND ISE Internal 3 state busing e High performance clock management circuitry Up to eight Digital Clock Manager DCM modules Precise clock de skew Flexible frequency synthesis High resolution phase shifting o 16 global clock multiplexer buffers in all parts e Active Interconnect technology Fourth generation segmented routing structure Fast predictable routing delay independent of fanout o Deep sub micron noise immunity benefits Select I O Ultra technology Up to 852 user I Os o Twenty two single ended standards and five differential standards Programmable LVTTL and LVCMOS sink source current 2 mA to 24 mA per I O o Digitally Controlled Impedance I O on chip termination resistors for single ended I O standards PCI support 1 o Differential signaling 840 Mb s Low Voltage Differential Signaling I O LVDS with current mode drivers Bus LVDS I O HyperTransport LDT I O with current driver buffers Built in DDR input and output registers Proprietary high performance SelectLink technology for communications between Xilinx devices High bandwidth data path Double Data Rate DDR link Web based HDL generation methodology SRAM based in system configuration Fast SelectMAP configuration DN6000K10 User Guide www dinigroup com 23 INTRODUCTION VIRTEX II AAND ISE o Triple Data Encryption Standard DES security option bitst
57. and Phase REFA sr 8 Rocca OUTPUT MODE IT Divide and gt Le QFAO Phase d Feedback Bank Select 9 FBDIS Matrix 2 gt nis Divide ant LK 4 1 Bank4 82 Phase SU Select E 4080 B Matrix 4081 SER SL Divide and 3QA1 Bank3 gt s 30B0 gt aan de Matrix gt 3QB1 INV3 2 gt 20 0 Divide and lt 20A1 Bank2 p 2050 2080 5 T Matrix P 2QB1 1QA0 pivide and 1 1 E Phase Bank 1 1050 E Select D 1080 Matrix L2 1081 Figure 24 RoboClock Functional Block Diagram 4 3 2 RoboClock Configuration J umpers Header JP4 JP6 and JP7 enable the user to configure the RoboClocks as required These 3 way headers and allow the signal to float MID or be pulled to GND LOW 3 3 HIGH A brief description of each pin 15 given in Table 11 Table 11 RoboClock Configuration Signals Signal Name Desctiption Connector ROBO1_REFSEL1 ROBOCLOCK 1 Reference Select Input JP4 B1 The REFSEL input controls how the reference input is configured When LOW it will use the REFA pair PLL1A as the reference input When HIGH it will use the REFB pair PLL1BC PLL1BNC as the DN6000K 10 User Guide www dinigroup com 80 BOARD HARDW
58. be made through the build utility described below through the synplicity GUI or by hand At the bottom of each file is a list of defined compiler constants that dictate what code is included and what code is excluded The recognized constants are as follows EXTERNAL DEFINES Tells fpga v not to define it s own set of constants but to use the ones defined externally by synplicity FPGA X Tells fpga v which FPGA is being compiled X must be replaced with A B C D E F G H or I Used to define the FPGA s ID number and name for communication with the host VP70 VP100 Tells fpga v which fpga is being targeted Used by the intetconnect test to disable bus lines that ate no connect in the VP70 part INTERCON MASTER This must be defined for one and only one FPGA in the system It includes the control code for the interconnect test all other FPGA s are passive in the interconnect test Any FPGA can be the master but only INCLUDE_FLASH Includes Excludes the flash controller code EXCLUDE_FLASH INCLUDE DDR1 Includes Excludes the ddr1 controller code EXCLUDE DDR1 INCLUDE DDR2 Includes Excludes the ddt2 controller code EXCLUDE DDR2 DDR 32 MEG Defines the size of the DDR s for address mapping DDR 64 MEG DDR 128 MEG The above parameters may be modified by hand or by using the build utility with the following options make VP70 makes changes to synplicity and EDK proj
59. be posted on the Dini Group website The user is required to purchase the Xilinx Development Tools if in house development is required The tools are available from Xilinx http www xilinx com The Configuration 013 is programmed using an in system programmable configuration PROM U12 The JTAG chain from the PROM is in a serial daisy chain with the Configuration FPGA allowing simultaneous JTAG programming option of both devices The Configuration FPGA 15 set to Master Serial Mode using dipswitch 54 power up the Configuration FPGA provides a configuration clock that drives the PROM short access time after CEn and OE CFPGA_INITnh are enabled data is available on the PROM DO pin that is connected to the Configuration FPGA The programming header J7 as shown in Figure 18 is used to download the files to the Configuration PROM FPGA via a Xilinx Parallel IV cable DN6000K10 User Guide www dinigroup com 40 PROGRAMMING CONFIGURING THE HARDWARE 3 3 3 3 R150 R160 1K 1K J7 1 3 JTAG_PROM_TMS 5 7 8 PROM 10 JTAG PROM TDI 12 HX 14 x 87332 1420 Figure 4 Configuration PROM FPGA Programming Header This section lists detailed instructions for programming the Configuration FPGA PROM using the Xilinx ISE 6 11 tools Note This user guide will not be updated for every re
60. com 89 BOARD HARDWARE Signal Name FPGA Pin DDR PLL Clock Driver SYS_CCLKn U29 21 0659 SYS DCLKp U53 22 65 20 SYS_DCLKn 1153 24 65 19 SYS ECLKp 52 A 121 65 22 SYS ECLKn 52 AU21 65 23 65 46 SYS_FCLKn 51 AT22 65 47 U U SYS_FCLKp U51 AU22 U U SYS_GCLKp 80 AU22 65 44 SYS_GCLKn U80 AT22 65 43 SYS_HCLKp U78 AT21 65 39 SYS_HCLKn U78 AU21 65 40 SYS ICLKp 79 702 65 29 SYS U79 K22 65 30 4 7 Rocket IO Programmable Clocks The DN6000K10 provides one crystal oscillator to differential LVDS frequency syntheszer per FPGA These frequency syntheszer are serially programmable The use of this variable clock source allows designers to prototype vatious interconnect technologies with different clock source requirements The dual output LVDS clocks are routed to the top and bottom RocketIO reference clock inputs The PLL architecture for the RocketIO transceivers uses the reference clock as the interpolation source to clock the serial data Removing the reference clock will stop the RX and TX PLLs from working Therefore a reference clock must be provided at all times The serial transceiver input is locked to the input data stream through Clock and Data Recovery CDR a built in feature of the RodketIO transceiver There are eight clock inputs into each RocketIO transceiver instantiation REFCLK and BREFCLK are reference clock
61. emulator is required to monitor MCU transactions and to interact with the embedded PowerPC processors in the Reference Design The Dini Group suggests using the Windows based program HyperTerminal Hypertrm exe The configuration files for HyperTerminal mcu_rs232 ht and ppc rs232 ht are supplied on the CD ROM or can be downloaded from the Dini Group website The RS232 ports are configured with the following parameters e Bits per second 19200 Data bits 8 e Parity None Stop Bits 1 e Flow control None Terminal Emulation VT100 Two cables converting the 5 x 2 header to a DB9 are shipped with the DN6000K10 The 5 x 2 headers connect to the MCU RS232 header P2 and any of the four PPC RS232 headers P3 P4 P6 and P7 These headers are not keyed ensure correct pin otientation as noted below Note MCU RS232 Header P2 is not keyed Ensure correct pin orientation Pin 1 is indicated with a letter 1 on the board silkscreen as well as a dot Pin 1 on the 5 X 2 cable header 15 indicated with a triangular shape printed on the connector and by a coloted wire on the cable DN6000K10 User Guide www dinigroup com 46 PROGRAMMING CONFIGURING THE HARDWARE Two female to female RS232 cables are provided with the DN6000K10 These cables will attach directly to the RS232 ports of a PC The Dini Group suggests Jameco as a possible supplier http www jameco com The part number is 132345 Male to female extension cab
62. follows 1 The first nonempty uncommented line in main txt should be Verbose level X where X can be 0 1 or 2 If this line is missing or X is an invalid level then the default verbose level will be 2 2 The second nonempty uncommented line in main txt tells whether or not to perform a sanity check on the bit files before configuring Sanity check y ec 22 where stands for yes n for no If the line is missing or the character after 292 22 2 is not y n then the sanity check will be enabled DN6000K 10 User Guide ww w dinigroup com 53 PROGRAMMING CONFIGURING THE HARDWARE 3 For each FPGA that the user wants to configure there should be exactly one entty in the main txt file with the following format FPGA F example bit In the above format the F following FPGA is to signal that this entry is for FPGA F and FPGA F would then be configured with the bit file example bit The DN6000K10 only has one FPGA which is FPGA There can be any number of spaces between and the configuration file name but they need to be on the same line 4 Comments are allowed with the following rules All comments must start at the beginning of the line e All comments must begin with Ifacomment spans multiple lines then each line should start with Commented lines will be ignored during configuration and are only for the
63. or you can use the full path Below 15 an example of an accepted setup file A fpga_a bit B fpga_b bit fpga_c it 4 Configure via SmartMedia Card This option allows the user to use a SmartMedia card to configure the FPGAs Please section Creating Configuration File main txt for information on what files should be the SmartMedia card to use this option 5 Clear All FPGAs This option will clear all FPGAs of configuration 6 Reset This options sends an active low reset active for approx 20ns to all FPGAs on the signal called FRGA_GRSTn which is connect to the following I O pins FPGA A M28 FPGA B M22 FPGA C M22 FPGA D M21 FPGA E M16 FPGA F E20 FPGA G E20 FPGA H M28 FPGA I A26 1 1 7 FPGA Memory Menu The FPGA Memory Menu has the following options DN6000K 10 User Guide ww w dinigroup com 17 INTRODUCTION VIRTEX II AAND ISE 1 Write DWORD s Writes DWORD s to memory with a specified starting address and number of DWORDY Ss to write Also the user can specify what to write address value inverse of address or a user inputted value Additionally enabling verbose mode will allow the user to see what has been written to what address Please note that all addresses must be entered as 8 digit hexadecimals 2 Read DWORD s Reads DWORD s from memory with a specified starting address and number of DWORD s to read The Values used to test memory options are
64. parts required for vatious RocketIO Power operating speeds refer to Xilinx datasheet 32MB SmartMedia Card with reference design and main txt V 32MB SmartMedia Card for customer use blank DN6000K 10 User Guide Www w dinigroup com 6 GETTING STARTED FlashPath Adapter to copy bit files to the SmartMedia Card s 8232 Serial cable female to female 6ft IDC 10 pin to DB 9 pin adaptor cable Jumpers 0 1 x10 Y Documentation Reference CD Optional items that support development efforts not provided Xilinx ISE software cable Daughter Card 3 Installation Instructions 3 1 J umper Setup Figure 2 indicates the factory jumper configuration of the DN6000K10 DN6000K 10 User Guide ww w dinigroup com GETTING STARTED JP4 ROBO DS1 o ROBO1 050 ROBO1_F1 ROBO ROBO FBDIS ROBO FBDS1 o ROBO1_FBDSO 1 ROBO FS ROBO1_REFSEL C1 1 A1 C1 9 1 9 6 453 B1 C1 JP5 C1 B1 Figure 2 Default Jumper Setup 3 2 J umper Description Table 1 describes the functionality Table 1 Jumper Desctiption Jumper Signal Name Installed of t
65. pass fail Bit 2 flash test pass fail Bit 4 interconnect test pass fail 0 1 00 0018 Ox1COO 0018 R W Contains information what FPGAs are stuffed on egister DN6000k10 as well as what type of FPGAs they are The register has the following format Bit 0 1 if FPGA A is stuffed 0 otherwise Bit 1 1 if FPGA B is stuffed 0 otherwise Bit 2 1 if FPGA is stuffed 0 otherwise Bit 2 1 if FPGA D is stuffed 0 otherwise Bit 2 1 if FPGA E is stuffed 0 otherwise Bit 2 1 if FPGA F is stuffed 0 otherwise Bit 2 1 if FPGA is stuffed 0 otherwise Bit 7 1 if FPGA H is stuffed 0 otherwise Bit 8 1 if FPGA I is stuffed 0 otherwise Bit 9 1 if FPGA is 2vp100 0 if 2vp70 Bit 10 1 if FPGA 2vp100 0 if 2vp70 Bit 11 1 if FPGA is 2vp100 0 if 2vp70 Bit 12 1 if FPGA D is 2vp100 0 if 2vp70 Bit 13 1 if FPGA E is 2vp100 0 if 2vp70 Bit 14 1 if FPGA F is 2vp100 0 if 2vp70 Bit 15 1 if FPGA is 2vp100 0 if 2vp70 Bit 16 1 if FPGA H is 2vp100 0 if 2vp70 Bit 17 1 if FPGA I is 2vp100 0 if 2vp70 176 Start End Address Read Description Address Write DDR 1 U23 0 2000 0000 0x20FF_FFFF Address maps directly to DDR 1 DDR 2 U34 0 2100 0000 Ox21FF_FFFF Address maps directly to DDR 2 034 only avail if 2vp100 FLASH 017 0 2800 0000
66. specifically for high speed LVDS signaling The connector mates with a standard off the shelf 3M cable assembly P N 14150 EZBB XXX 0LC where XXX is 050 0 5 m 150 1 5m 300 3 0 m 500 5 0 m Please contact for further details www 3m com DN6000K 10 User Guide www dinigroup com 144 BOARD HARDWARE 11 2 6 Connection between FPGA and the Daughter Card Headers Table 28 shows the IO connections between the DN3000K10SD headers and the FPGA IO pins The VCCO of the IO banks are connected to 2 5V Table 28 Connection between FPGA and the Daughter Card Headers Daughter Card Connections DN6000K10 IO Connections Test Header A Test Signal Name Connector Test Signal Name FPGA Pin Header Header j1 001 No Connect P9 1 12V J1 002 No Connect 9 2 GND 11 003 ACLK1 P9 3 2 5V J1 004 No Connect P9 4 T5V 11 005 BCLK1 5 3 9 5 2 5 11 006 No Connect P9 6 T5V 11 007 CCLK1 J5 5 P9 7 ACLK9 J1 008 No Connect 9 8 GND J1 009 No Connect 292 3 3V J1 010 BP2N3 P2N3 J3 1 P9 10 BCLK9 J1 011 No Connect P9 11 GND J1 012 BP2N2 P2N2 133 P9 12 TST HDRAO U28 AF41 11 013 P2N1 J2 8 P9 13 TST_HDRA1 U28 AE41 J1 014 P2NO J2 9 9 14 TST_HDRA2 U28 AD41 1 015 BP2NX7 P2NX7 155 P9 15 TST_HDRA3 U28 AC31 J1 016 BP2NX6 P2NX6 J3 7 P9 16 TST_HDRA4 U28 AC33 J1 017 BP2NX5 P2NX5 13 9 P9 17 TST_HDRA5 U2
67. to twenty four RocketIO embedded multi gigabit transceiver blocks based on Mindspeed s SkyRail technology DN6000K10 User Guide www dinigroup com 20 INTRODUCTION VIRTEX II AAND ISE o Up to four IBM PowerPC RISC processor blocks Based Virtex IT FPGA technology Flexible logic resources up to 125 136 Logic Cells SRAM based in system configuration Active Interconnect technology SelectRAM memory hierarchy Up to 556 Dedicated 18 bit x 18 bit multiplier blocks o High performance clock management circuitry SelectIOTM Ultra technology o Digitally Controlled Impedance I O 2 2 PowerPC 405 Core Embedded 300 MHz Harvard architecture core Low power consumption 0 9 mW MHz Five stage data path pipeline Hardware multiply divide unit Thirty two 32 bit general purpose registers 16 KB two way set associative instruction cache 16 KB two way set associative data cache Memory Management Unit MMU 64entry unified Translation Look aside Buffers TLB Variable page sizes 1 to 16 MB Dedicated on chip memory OCM interface Supports IBM CoreConnect bus architecture Debug and trace support Timer facilities 2 3 RocketlO 3 125 Gbps Transceivers Full duplex serial transceiver SERDES capable of baud rates from 622 Mb s to 3 125 Gb s please reference the Xilinx datasheet for speed grade limitations 80 Gb s duplex data rate 16 channels DN6000K10 User Gui
68. various clock frequencies VCO range 220MHz to 700MHZ e Output Frequency range 31 25MHz to 700MHz RMS period jitter 2 7ps typical Cycle to cycle jitter 18ps typical Please tefer to the manufacturers datasheet for more information http www icst com 4 7 3 Connections between FPGA s and RocketlO Clock Synthesizers The connection between the FPGA s and the RocketIO clock synthesizers are shown in Table 15 DN6000K10 User Guide www dinigroup com 91 BOARD HARDWARE Table 15 Connections between FPGA s and Rocket IO Clock Synthesizers RCKTIO_OSCB_An U27 AU21 RCKTIO_OSCT_Bp U28 P21 RCKTIO OSCT Bn U38 15 U28 G21 RCKTIO OSCB Bp U38 11 U28 AT21 RCKTIO_OSCB_Bn U28 AU21 RCKTIO_OSCT_Cp 929 821 RCKTIO OSCT Cn 37 15 U29 G21 RCKTIO OSCB Cp 37 11 U29 AT21 RCKTIO_OSCB_Cn U29 AU21 RCKTIO_OSCT_Dp U53 G22 RCKTIO_OSCT_Dn 60 15 U53 F22 RCKTIO_OSCB_Dp 60 11 U53 AU22 RCKTIO OSCB Dn U53 AT22 RCKTIO_OSCT_Ep U52 F21 RCKTIO OSCT En 59 15 U52 G21 RCKTIO OSCB Ep 159 11 AT2 RCKTIO OSCB En U52 AU21 RCKTIO OSCT U51 G22 RCKTIO OSCT Fn 50 15 U51 F22 RCKTIO_OSCB_Fp U50 11 U51 AT21 RCKTIO_OSCB_Fn U U51 AU21 RCKTIO_OSCT_Gp U U80 G22 U RCKTIO_OSCT_Gn 70 15 U80 F22 RCKTIO_OSCB_Gp U70 11 U80 AT21 DN6000K10 User Guide www dinigroup com 92 BOARD HARDWARE Signal Name FPGA Pin OSCILLATOR RCKTIO OSCB Gn U80 AU21 RCKTIO OSCT Hp U U78 F21
69. vp70 lines ET IO 10 HI 180 169 ROCKETIO 10 Figure 11 DN6000K10 Block Diagram 1 1 DN6000K10 Functionality The components and interfaces featured on the DN6000K10 includes DN6000K10 User Guide USB2 0 Interface FLASH 4M x 16 x 3 200 Pin Test Header x 3 SmartMedia Configuration 2VP70 100 Pro FPGA Options x 9 DDR SDRAM 16M x 16 2 per FPGA www dinigroup com One User Clock SMA Interface differential SMB 5 2 FLASH 4 16 exei AC 5 EIBDES 41 5 DDR SDRAM 32MX16 XC2VP70 100 FF1704 aj s POR SORAM x 2 22 8 2465 MICTOR 8 5 DEBUG e 2 XILINX 41 gt DDR SDRAM FPGAD 32MX16 XC2VP70 100 le 41 DDR SDRAM FF1704 32MX16 ol 3 2 5 a o g a ov DDR SDRAM ddl 32MX16 XILINX DDR SDRAM FPGAI FO XC2VP70 100 FF1704 L gt x x S olloh FLASH aMXIG Flexible and Configurable Clocking Scheme RoboClocklT Two Multi Gigabit Transceiver MGT channels SMB FPGA A C 1 61 BOARD HARDWARE CPU Debug and Trace Interfaces in Berg and Mictor con
70. working order by following the steps below 2 The DN6000K 10 LOGIC Emulation Kit The DN6000K10 LOGIC Emulation Kit provides a complete development platform for designing and verifying applications based on the Xilinx Virtex II Pro FPGA family The DN6000k10 is stand alone hosted a USB interface The DN6000K10 enables designers to implement embedded processor based applications with extreme flexibility using IP cores and customized modules The Virtex II Pro DN6000K10 User Guide www dinigroup com 5 GETTING STARTED FPGA with its integrated PowerPC processor and powerful Rocket I O Multi Gigabit Transceivers MGT make it possible to develop highly flexible and high speed serial transceiver applications The DN6000K10 in its standard configuration includes a high speed USB interface a SmartMedia interface for configuration 16M x 16 DDR SDRAM x8 4M x 16 FLASH x5 RS232 ports x4 multiplexed and RS232 monitor port There are 9 low skew clock sources that are distributed to the FPGAs and the test header A 200 pin test header allows for connection to individual FPGA s IO banks using a custom daughter card Figure 1 shows the DN6000K10 Logic Emulation Board a i 24 io Figure 1 DN6000K10 LOGIC Emulation Board The DN6000K10 LOGIC Emulation Kit includes the following DN6000K10 development board 2VP70 or 2VP100 in the FF1704 package Note Specific speed grade
71. 0 is first powered up RocketlO CLK inputs to the FPGAs are inactive The RocketlO CLK Inputs are connected to the following FPGA Differential CLK inputs on all FPGAs F21 G21 and AT21 AU21 This menu option allows the user to specify what frequency the RocketlO CLKs should be set at for each FPGA The supported frequency range is 31 22MHz 700MHz After selecting this option a pop up window will ask which FPGA s Frequency you want to set or you can choose to set all to the same frequency and then what frequency you want Check the log window to verify what frequency the CLKs were actually set at Change Text Editor This options allows the user to select a text editor to use the default editor is notepad FPGA Stuffing Information This option will display the type of FPGAs that are stuffed on the DN6000k10 Turn FPGA Fans On Off This option will either turn the FPGA fans on or off MCU Firmware Version This option will display the MCU Firmware version in the log window BOARD SPARTAN Version This option will display the Board Version along with the Spartan Config Fpga Version DN6000K10 User Guide www dinigroup com 19 INTRODUCTION VIRTEX II PRO AAND ISE Chapter Introduction to Virtex l Pro and ISE 2 Virtex4l Pro The Virtex II Pro FPGA solution is the most technically sophisticated silicon and softwate product development in the history of the programmable logic industry
72. 000K10 User Guide www dinigroup com 96 BOARD HARDWARE Signal Name FPGA Pin FLASHA ADDR15 U27 D40 FLASHA ADDR16 U27 AA37 FLASHA ADDR17 U27 L39 FLASHA ADDR18 027 140 FLASHA_ADDR19 U27 K38 FLASHA_ADDR20 U27 H38 FLASHA_ADDR21 U27 H39 FLASHA DATAO U27 R38 FLASHA_DATA1 U27 139 FLASHA DATA2 U27 U40 U U FLASHA DATA3 27 U38 FLASHA DATA4 27 V38 FLASHA_DATA5 U27 W39 FLASHA_DATA6 U27 Y40 FLASHA_DATA7 U27 AA40 FLASHA_DATA8 U27 T40 FLASHA_DATA9 U27 138 FLASHA_DATA10 927 39 FLASHA DATA11 127 039 DATA12 U27 W40 FLASHA DATA13 U27 W38 FLASHA DATA14 127 39 FLASHA DATA15 U27 AA39 FLASHA CEN U27 P38 _ 027 840 FLASHA WEN U27 J39 FLASHA_WPN 27 40 FLASHB ADDRO 28 U42 FLASHB ADDR1 28 141 nC c c emm DN6000K 10 User Guide www dinigroup com 97 BOARD HARDWARE Signal Name FPGA Pin FLASHB ADDR2 U28 R41 FLASHB ADDR3 U28 R42 FLASHB_ADDR4 U28 P41 FLASHB ADDR5 U28 P42 FLASHB ADDR6 U28 N41 FLASHB ADDR7 U28 N42 FLASHB ADDRS8 U28 G41 FLASHB ADDR9 U28 G42 FLASHB ADDR10 U28 F41 FLASHB ADDR11 U28 F42 FLASHB ADDR12 U28 E41 FLASHB ADDR13 U28 E42 FLASHB ADDR14 U28 D41 FLASHB ADDR15 U28 D42 FLASHB ADDR16 U28 AA33 FLASHB ADDR17 U28 M41 FLASHB_ADDR18 U28 L41 FLASHB ADDR19 028 142 FLASHB ADDR20 U28 42 FLASHB ADDR 1 U28 H
73. 0k10 via the USB interface At this point the DN6000k10 should be powered All present FPGAs should be programmed with the reference design bit files provided by The Dini Group 1 2 Hook up the USB cable to your DN6000k10 and your When you plug in the board and start windows the first time windows should detect the board and ask for a driver Select install from a list gt select search for the best driver in these locations Select include the location in the search and browse to where the INF file is located on the product CD in Source CodeNAETEST USB driver Nwin wdm V select finish If the driver was installed successfully you should see the following device in the USB section of the device mananger DiniGroup DN6000k10 FLASH boot You can now run the USB application found on the product CD in Source CodeNUSBConttollerNUSBConttroller exe Please see 5 Playing with your DN6000K 10 via the PPC s At this point the DN6000K10 should be powered All present FPGA s should be programmed with the reference design bit files supplied by The Dini Group 6 Hook up the PPC RS232 port 1 P3 All PPC RS232 ports run at 19200 bps DN6000K 10 User Guide ww w dinigroup com 12 GETTING STARTED 7 Press 1 on the MCU menu to reconfigure all FPGA s When configuration is complete the following text will be displayed on the PPC RS232 port CK CCS CCS CS S E E KG Kk
74. 1 U53 T2 and J1 029 BP3N86 P3N86 13 23 P10 29 FD34 U51 AG2 U53 T3 J1 030 BP3N83 P3N83 13 25 10 30 2135 051 053 02 and 1 031 BP3N82 P3N82 3 27 10 31 2137 0751 U53 V1 11 032 BP3N77 P3N77 13 29 P10 32 FD39 U51 AE1 J1 033 No Connect P10 33 GND U53 W2 and J1 034 BP3N76 P3N76 10 34 2142 U51 AD2 U53 W4 and J1 035 BP3N75 P3N75 13293 10 35 2144 0751 U53 Y4 and 11 036 BP3N74 P3N74 J3 35 P10 36 FD46 U51 AC4 J1 037 P3N69 J2 42 P10 37 FD48 U53 AA4 DN6000K10 User Guide Www dinigroup com 154 BOARD HARDWARE Daughter Card Connections DN26000K10 IO Connections Test Header B Signal Name Connector Test Signal Name FPGA Pin Header and U51 AB4 J1 038 P3N68 2 43 P10 38 TST HDRB24 052 02 1 039 BP3N67 P3N67 3 37 P10 39 TST HDRB25 U52 E2 11 040 BP3N66 P3N66 13 29 10 40 TST HDRB26 U52 F2 1 041 BP3N63 P3N63 3 41 10 41 TST HDRB27 U52 G2 1 042 BP3N62 P3N62 J3 43 P10 42 TST_HDRB28 052 1 1 043 BP3N57 P3N57 J3 45 P10 43 TST HDRB29 U52 K1 J1 044 No Connect P10 44 GND 1 045 BP3N56 P3N56 J3 47 P10 45 TST HDRB30 05211 J1 046 No Connect P10 46 TST HDRB31 U52 M2 1 047 No Connect P10 47 TST HDRB32 U52 N2 J1 048 BP3N49 P3N49 P10 48 TST HDRB33 1152 P2 1 049 BP3N48 P3N48 4 3 P10 49 TST HDRB34 U52 R2 1 050 P3N47 12 1
75. 1 J1 169 P3N12 J6 39 P10 169 TST HDRB132 U52 AR2 J1 170 P3N11 12 47 10 170 TST HDRB133 U52 AT2 P3N10 12 48 10 171 TST HDRB134 U52 AU2 J1 172 P3N5 J6 41 10 172 TST HDRB135 U52 AV2 1 173 No Connect 10 173 GND J1 174 P3N4 16 43 10 174 TST_HDRB136 U52 AW2 U53 AD2 J1 175 P3N1 10 45 10 175 21054 and 051 472 U53 AD4 J1 176 16 47 P10 176 FD56 and 051 WA U53 AE1 J1 177 P4N25 7 1 10 177 FD57 and U51 V1 U53 AF1 J1 178 PAN24 17 3 10 178 FD59 and 05111 U53 AF3 J1 179 PAN23 J7 5 P10 179 FD61 and 051 03 U53 AG3 11 180 P4N22 J7 7 P10 180 FD63 and 05173 U53 AH2 P4N17 J7 9 P10 181 FD65 and US1 R2 DN6000K 10 User Guide www dinigroup com 161 BOARD HARDWARE Daughter Card Connections DN6000K10 IO Connections Test Header B Signal Name Connector Test Signal Name FPGA Pin Header U53 AJ1 J1 182 P4N16 7 11 P10 182 FD67 USi P1 U53 AJ3 J1 183 4 15 J743 P10 183 FD69 U51 P3 1 184 GND 2 36 10 184 GND U53 AK3 J1 185 P4N14 17 15 P10 185 FD72 and U51 N3 U53 AL3 J1 186 P4N9 7 17 10 186 FD74 and U51 M3 U53 AM2 1 187 P4N8 17 19 10 187 FD76 and U51 L2 U53 AM3 J1 188 P4N5 T6521 P10 188 2077 and 05113 U53 AN2 J1 189 17 23 P10 189 FD79 and U51 K2 U53 AP1 1 190 P4N1 11 25 10 190 FD81 and 051 1 U53 AR2 11 191 P4NO 7 27 10 191 FD83 and U51 H2 U53 AT1 11
76. 1 Output Divider Function Select Controls the divider function of all banks ACLKx of outputs Refer to Table 4 in the datasheet JP7 A1 B1 ROBO2 REFSEL RoboClock 2 057 ROBOCLOCK 2 Reference Select Input The REFSEL input controls how the reference input is configured When LOW it will use the REFA pair PLL1A as the reference input When HIGH it wil use the REFB pair PLL1BC PLLIBNC as the reference input This input has an internal pull down JP7 A4 B4 ROBO2 FBDSO ROBOCLOCK 2 Feedback Divider Function Select These inputs determine the function of the QFAO and QFA1 outputs Refer to Table 4 in the datasheet JP7 A5 B5 ROBO2 FBDS1 ROBOCLOCK 2 Feedback Divider Function Select These inputs determine the function of the QFA1 outputs Refer to Table 4 in the datasheet JP7 A9 B9 ROBO2 1050 ROBOCLOCK Z2 Output Divider Function DN6000K 10 User Guide ww w dinigroup com 9 GETTING STARTED Jumper Desctiption Installed Select Controls the divider function of all banks BCLKx of outputs Refer to Table 4 in the datasheet JP7 A10 B10 ROBO2_DS1 ROBOCLOCK 2 Output Divider Function Select Controls the divider function of all banks BCLKx of outputs Refer to Table 4 in the datasheet JP6 B1 C1 OSCA Enable for Oscillator A X9 JP6 B2 BC2 OSCB Enable for Oscillator B X8 JP6 B7 C7 ROBO1 MODE ROBOCLOCK 1 Output Mode Thi
77. 1 P10 3 2 5V J1 004 No Connect P10 4 5V J1 005 BCLK1 15 3 P10 5 2 5 1 006 No Connect 10 6 5V J1 007 CCLK1 J5 5 P10 7 ACLK10 J1 008 No Connect P10 8 GND J1 009 No Connect P10 9 3 3V J1 010 BP2N3 P2N3 J3 1 P10 10 BCLK10 J1 011 No Connect P10 11 GND U53 D2 and J1 012 BPZN2 P2N2 3 3 P10 12 FD2 U51 U53 E1 and J1 013 P2N1 J2 8 P10 13 FD4 USLAVI U53 E3 and J1 014 P2NO 12 9 10 14 FD6 USLAV3 U53 F2 and 11 015 BP2NX7 P2NX7 13 5 P10 15 FD8 1051 02 U53 G1 and J1 016 BP2NX6 P2NX6 10 16 FD10 051 ATI U53 G3 and J1 017 BP2NX5 P2NX5 J3 9 P10 17 FD12 051 53 11 018 BP2NX4 P2NX4 10 18 2014 151 053 2 and 11 019 P2NX1 12 10 10 19 2016 051 U53 K2 and 11 020 P2NXO0 2 11 10 20 2018 051 DN6000K 10 User Guide www dinigroup com 153 BOARD HARDWARE Daughter Card Connections DN6000K10 IO Connections Test Header B Signal Name Connector Test Signal Name FPGA Pin Header U53 L1 and 1 021 P3NX9 12 40 10 21 21020 0751 1 1 022 No Connect P10 22 GND U53 L3 and 1 023 P3NX8 2 41 10 23 21022 10751 53 11 024 BP3NX5 P3NX5 13 19 10 24 2124 USLAL3 U53 N2 and 11 025 BP3NX4 P3NX4 J3 15 P10 25 FD26 051 2 U53 P1 and J1 026 BP3N89 P3N89 J3 17 P10 26 FD28 U51 AJ1 U53 P3 and J1 027 BP3N88 P3N88 13 49 10 27 2130 U51 AJ U53 R2 and 11 028 BP3N87 P3N87 13 21 P10 28 FD32 05
78. 10 User Guide www dinigroup com 62 BOARD HARDWARE 3 FPGA Configuration The Dini Group developed the SmartMedia Configuration Environment to address the need for a space efficient pre engineered high density configuration solution for systems with single or multiple FPGA s The technology is a groundbreaking in system programmable configuration solution that provides substantial savings in development effort and cost per bit over traditional PROM and embedded solutions for high capacity FPGA systems Virtex II Pro devices are configured by loading application specific configuration data into internal memory Configuration is carried out using a subset of the device pins some of which are dedicated while others can be reused as general purpose inputs and outputs after configuration is complete SmartMedia is the primary means of configuring the FPGA s on the DN6000K10 board Configuration of FPGA s is accomplished using either Serial SelectMAP or the JTAG interface The remainder of this section describes the functional blocks that entail the FPGA configuration environment 3 1 Micro Controller Unit MCU The Cypress CY7C68013 U7 micro controller is used to control the configuration process The MCU contains an enhanced 8051 core USB 2 0 transceiver and Serial Interface Engine SIE The CY7C68013 provides the following features 256 bytes of register RAM three flexible Timers 2 USARTs and an integrated compatible co
79. 100 FAX 781 224 1239 Suggested reference books available from Amazon Samir Palnitkar HDI Guide fo Digital Design and Synthesis ISBN 0 13 451675 3 Sundar Rajan Essential VHDL RTL Synthesis Done Right Edwin Breecher The Booster Improve Your Performance Dramatically DN6000K10 User Guide www dinigroup com GETTING STARTED Chapter Getting Started Congratulations your purchase of the DN6000K10 LOGIC Emulation Board You can begin by installing the software or by powering on your DN6000K10 If you wish to begin installation please follow the installation instructions The remainder of this chapter describes the contents of the box and how to start using the DN6000K10 LOGIC Emulation Board 1 Precaution The DN6000K10 is sensitive to static electricity so treat the PCB accordingly The target markets for this product are engineers that are familiar with FPGA s and circuit boards so a lecture in ESD really isn t appropriate and wouldn t be read anyway However the following web page has an excellent tutorial on the Fundamentals of ESD for those of you who are new to ESD sensitive products http www esda org basics part1 cfm The DN6000K10 has been factory tested and pre programmed to ensure correct operation You do not need to alter any jumpers or program anything to see the board work A reference design is included on the enclosed CD Please verify that the board is in
80. 11 110 GND 1 111 P2N5 5 15 11 111 TST HDRC79 U80 AD2 P2N4 5 17 11 112 TST_HDRC80 U80 AE2 J1 113 P2NX11 2 2 11 113 TST HDRCS81 2 1 114 P2NX10 123 11 114 TST_HDRC82 U80 AG3 1 145 P2NX9 15 19 11 115 TST HDRC83 U80 AH2 J1 116 P2NX8 J5 21 P11 116 TST HDRC84 U80 AJ1 J1 117 P2NX3 J5 23 P11 117 TST HDRC85 U80 AJ3 J1 118 No Connect P11 118 GND J1 119 P2NX2 J5 25 P11 119 TST HDRC86 U80 AK2 J1 120 P3NX11 J2 29 P11 120 TST_HDRC87 U80 AL2 J1 121 P3NX10 J2 30 P11 121 TST_HDRC88 U80 AM1 J1 122 P3NX7 J2 31 P11 122 TST_HDRC89 U80 AM3 J1 123 P3NX6 J2 32 11 123 TST_HDRC90 U80 AN2 1 124 P3NX3 5 27 11 124 TST HDRC 1 U80 AP1 11 425 P3NX2 5 29 11 125 TST HDRC92 U80 AR2 11 126 P3NX1 J5 31 P11 126 TST HDRC93 U80 AT1 1 127 J5 33 11 127 TST HDRC 4 U80 AT3 1 128 P3N85 15 35 P11 128 TST_HDRC95 U80 AU2 11 129 No Connect P11 129 GND 11 130 P3N84 J5 37 P11 130 TST HDRC96 U80 AV1 1 131 P3N81 5 39 11 131 TST HDRC 7 U80 AV3 DN6000K 10 User Guide www dinigroup com 168 BOARD HARDWARE Daughter Card Connections DN26000K10 IO Connections Test Header C Test Signal Name Connector Test Signal Name FPGA Pin Header Header 1 132 P3N80 5 41 11 132 TST HDRC98 U80 AW2 14 433 P3N79 11 133 TST HDRC99 U80 AW3
81. 12 x 20 1 C615 C632 C18 gt 100 0 1uF 4 100 16 16V 20 20 39 29 9202 gt ELEC ELEC Figure 40 External Power Connection Note Header J17 is not hot plug able Do not attach power while power supply is ON DN6000K10 User Guide www dinigroup com 135 BOARD HARDWARE Since the DN6000K10 is populated with up to 9 Virtex II Pro FPGA s depending on the RTL design significant power demands may be placed on the on board 1 5V 2 5V switching power supplies Optional PWR connectorS allows for connection to a high power external PSU s These connectors would need to be used in place of the 1 5V 2 5V switching supplies PSU1 PSU2 A Molex connector P N 42819 4212 is used and is rated at 600V 48A refer to Figure 41 1 5 Figure 41 Optional PWR Connector 10 1 2 Power Monitors Power supply monitor U5 is used to monitor the 1 5V 2 5V 3 3V and 5V supplies for more information on these devices please refer to the datasheet for the L T2900 from Linear Technology The power supply monitor also provides a push button reset input that is utilized to reset the various sub circuits of the DN6000K10 After power up 5 5 RSTn remains asserted for approximately 10ms 10 1 3 Power Indicators There are LED s on the DN6000K10 used to indicates the presence of the following voltage sources refer to Table 26 Table 26 Voltage Indicators Volta
82. 192 P4NX13 7 29 10 192 21085 and U51 G1 U53 AT2 J1 193 P4NX12 TEM P10 193 FD86 and U51 G2 U53 AU1 J1 194 P4NX9 J7 33 P10 194 FD88 and U51 F1 11195 No Connect P10 195 GND U53 AV1 J1 196 P4NX8 17 35 P10 196 FD91 and UST U53 AV3 J1 197 P4NX3 TS P10 197 FD93 and U51 E3 J1 198 P4NX2 7 39 10 198 2195 U53 AW2 DN6000K 10 User Guide www dinigroup com 162 BOARD HARDWARE Daughter Card Connections DN6000K10 IO Connections Test Header B Signal Name Connector Test Signal Name FPGA Pin Header and U51 D2 U53 AW3 11 199 P4NX1 J7 41 10 199 FD96 and U51 D3 DN6000K 10 User Guide www dinigroup com 163 BOARD HARDWARE Daughter Card Connections DN6000K10 IO Connections Test Header C Test Signal Name Connector Test Signal Name FPGA Pin Header Header j1 001 No Connect P11 1 12V J1 002 No Connect P11 2 GND J1 003 ACLK1 5 P11 3 2 5V J1 004 No Connect P11 4 5V J1 005 BCLK1 J5 3 P11 5 2 5 1 006 No Connect P11 6 5V J1 007 CCLK1 155 P11 7 ACLK11 J1 008 No Connect P11 8 GND J1 009 No Connect P11 9 T33V 1 010 BP2N3 P2N3 J34 P11 10 BCLK11 1 011 No Connect P11 11 GND 1 012 BP2N2 P2N2 J3 3 P1112 TST HDRCO U80 AD1 J1 013 P2N1 J2 8 P11 13 TST HDRC1 U80 AE1 J1 014 2 0 12 9 P1114 TST HDRC2 U80 AF1 1 015 BPZNX7 P2NX7T J3 5 P11 15 TST HDRC3 U80 AF3 J1 016
83. 23 U78 E3 J1 038 P3N68 J2 43 11 38 TST HDRC24 U78 F2 J1 039 BP3N67 P3N67 3 57 11 39 TST HDRC25 U78 G1 1 040 BP3N66 P3N66 J3 39 P11 40 TST_HDRC26 U78 G3 1 041 BP3N63 P3N63 J3 41 P11 41 TST_HDRC27 U78 H3 1 042 BP3N62 P3N62 J3 43 P11 42 TST_HDRC28 U78J2 1 043 BP3N57 P3N57 J3 45 P11 43 TST_HDRC29 U78 K2 J1 044 No Connect P11 44 GND 1 045 BP3N56 P3N56 J3 47 P11 45 TST HDRC30 07811 11 046 No Connect P11 46 TST HDRC31 U78 L3 J1 047 No Connect P11 47 TST_HDRC32 U78 M3 1 048 BP3N49 P3N49 J41 P11 48 TST_HDRC33 U78 N2 J1 049 BP3N48 P3N48 J43 P11 49 TST HDRC34 U78 P1 J1 050 P3N47 J219 P11 50 TST_HDRC35 U78 R1 J1 051 P3N46 2 20 11 51 TST HDRC36 078 72 1 052 BP3N43 P3N43 145 P11 52 TST HDRC37 U78 U2 DN6000K 10 User Guide www dinigroup com 165 BOARD HARDWARE Daughter Card Connections DN26000K10 IO Connections Test Header C Test Signal Name Connector Test Signal Name FPGA Pin Header Header 1 053 BP3N42 P3N42 J4 7 11 53 TST HDRC38 U78 V2 1 054 BP3N39 P3N39 49 P11 54 5 HDRC39 U78 AD1 1 055 No Connect P11 55 GND J1 056 BP3N38 P3N38 J4 11 P11 56 TSI_HDRC40 U78 AE1 J1 057 BP3N35 P3N35 413 P11 57 TST_HDRC41 U78 AF1 J1 058 BP3N34 P3N34 14 15 P11 58 TST_HDRC42 U78 AG2 J1 059 BP3N29 P3N29 14 17 P11 59 IST HDRC43 U78 AH2 1 060 BP3N28 P3N28 4 19 P11 60 TST HDRC44 U78 AJ2 J1 061
84. 2_ADD10 U29 AY24 DDR FPGA C2 ADD11 U29 AW24 DDR FPGA C2 ADD12 U29 AU24 DDR FPGA C2 ADD13 DN6000K 10 User Guide U29 AV24 www dinigroup com c ee ELE Se e 112 BOARD HARDWARE Signal Name FPGA Pin DDR C2 0008 U29 AW26 DDR FPGA C2 LDOS U29 AR29 DDR FPGA C2 UDM 1729 A Y 25 c DDR FPGA C2 LDM U29 AR28 DDR FPGA C2 BAO U29 AN29 DDR FPGA C2 U29 AM29 DDR FPGA C2 CASN U29 AY23 DDR FPGA C2 U29 AW27 DDR FPGA 2 U29 AL22 DDR C2 RASN U29 AW23 DDR_FPGA_C2_WEN U29 A V23 DDR D1 DATAO U53 AN20 DDR D1 DATA U53 AM20 DDR D1 DATA2 U53 AP20 DDR_D1_DATA3 U53 AR20 DDR_D1_DATA4 U53 AV19 U U U U U DDR_D1_DATA5 U53 AU19 DDR D1 6 U53 AW19 DDR D1 DATAT7 1753 AY 19 DDR D1 DATAS U53 AT18 DDR D1 DATA9 U53 AR18 DDR D1 10 53 A VTT DDR D1 DATA 11 89 AM TB DDR D1 DATA12 DDR D1 DATA13 53 AM18 DDR D1 DATA14 U U U53 AN18 U U 53 AU17 DDR_D1_DATA15 U53 AT17 DDR FPGA D1 ADDO U53 AT19 DDR FPGA D1 1 DN6000K 10 User Guide U53 AR19 www dinigroup c
85. 3 61 USER ICLKp U79 AN22 111 29 USER ICLKn U79 AP22 01 30 DN6000K 10 User Guide www dinigroup com 76 BOARD HARDWARE SYS ICLKp 1719422 065 29 SYS ICLKn U79 K22 U65 30 RCKTIO OSCT Ip U79 G22 U68 14 RCKTIO OSCT In U79 F22 U68 15 RCKTIO_OSCB_Ip U79 AU22 U68 11 U79 AT22 U68 12 DDR_ICLKp U79 AT21 066 5 DDR 12 U79 AU21 U66 6 4 2 Clock Source J umpers The clock source grid JP5 gives the user the ability to select the clock input source to the RoboClock PLL buffers A brief description of each pin is given in Table 10 Table 10 Clock Source Signals Signal Name Description Connector CFPGA_CLKOUT Clock signal from the Configuration JP5 A3 FPGA CLOCKA Clock signal from oscillator JP5 A1 CLOCKB Clock signal from oscillator X2 JP5 A5 PLLIB Secondary clock input to RoboClock JP5 B4 differential pair with PLL1BN Secondary clock input to RoboClock JP5 B5 differential pair withl PLL1B PLL2B Secondary clock input to RoboClock JP5 B1 differential pair with PLL2BN Secondary clock input to RoboClock JP5 B2 differential pair with 2 Provides a ground reference for signals JP5 C1 C5 in the ribbon cable The PLL clock buffers can accept either LVTTL33 or Differential LVPECL reference inputs refer to Figure 22 DN6000K 10 User Guide www dinigroup com 77 BOARD H
86. 41 9 132 TST HDRA98 U27 AL41 1 133 P3N79 J2 3 9 133 TST HDRA99 U27 AK42 J1 134 P3N78 J24 9 134 TST HDRA100 27 41 11 195 P3N73 J2 6 P9 135 TST_HDRA101 U27 AH41 J1 136 P3N72 J2 7 P9 136 TST_HDRA102 U27 AG41 11 137 P3N71 J2 33 P9 137 TST_HDRA103 U27 AF42 J1 138 P3N70 J2 34 P9 138 TST_HDRA104 U27 AE42 1 139 P3N65 5 43 P9 139 TST_HDRA105 U27 AD42 J1 140 No Connect P9 140 GND 11 141 P3N64 J5 45 P9 141 TST_HDRA106 U27 AC36 11 142 P3N61 15 47 P9 142 TST_HDRA107 U27 AC39 J1 143 P3N60 J5 49 P9 143 TST_HDRA108 U27 AB33 1 144 P3N59 J6 1 P9 144 TST HDRA109 U27 AB36 J1 145 P3N58 6 3 P9 145 TST_HDRA110 U27 AB37 11 146 P3N53 165 9 146 TST HDRA111 U27 AB40 J1 147 P3N52 J6 7 P9 147 IST HDRA112 U27 AA31 11 148 P3N51 J247 P9 148 TST_HDRA113 U27 AA34 11 149 P3N50 12 18 9 149 TST HDRA114 U27 Y31 11 150 P3N45 16 9 P9 150 IST HDRA115 U27 Y33 J1 151 No Connect P9 151 GND 1 152 P3N44 J6 11 P9 152 IST HDRA116 U27 Y37 DN6000K 10 User Guide www dinigroup com 150 BOARD HARDWARE Daughter Card Connections DN6000K10 IO Connections Test Header A Test Signal Name Connector Test Signal Name FPGA Pin Header Header 1 155 P3N41 16 13 P9 153 TST_HDRA117 U27 W32 J1 154 P3N40 16 15 P9 154 TST 18 U27 W34 11 155 P3N37 J6 17 P9 155 IST HDRA119
87. 41 FLASHB DATAO U28 V41 FLASHB DATA1 U28 W41 FLASHB DATA2 U28 Y39 FLASHB DATA3 U28 Y36 FLASHB DATA4 U28 Y33 FLASHB DATA5 028 131 FLASHB DATAG U28 AA39 FLASHB DATA7 U28 AA36 FLASHB DATAS U28 W42 DN6000K 10 User Guide www dinigroup com 98 BOARD HARDWARE Signal Name FPGA Pin FLASHB DATA9 U28 Y40 FLASHB DATA10 U28 Y37 FLASHB DATA11 U28 Y34 FLASHB DATA12 U28 Y32 FLASHB DATA13 U28 AA40 FLASHB DATA14 U28 AA37 FLASHB DATA15 U28 AA34 FLASHB CEN 028 041 FLASHB OEN U28 V42 FLASHB WEN 02841 FLASHB WPN U28 K41 FLASHC ADDRO U29 AP39 FLASHC ADDR1 U29 AN38 FLASHC ADDR2 U29 AN40 FLASHC ADDR3 U29 AM38 FLASHC ADDR4 U29 AM39 FLASHC ADDR5 U29 AM40 FLASHC ADDR6 U29 AL38 FLASHC ADDR7 1729 1 39 FLASHC ADDRS8 U29 AG38 FLASHC ADDR9 U29 AG39 FLASHC ADDR10 U29 AG40 FLASHC ADDR11 U29 AF39 FLASHC ADDR12 U29 AF40 FLASHC ADDR13 029 AES9 FLASHC ADDR14 U29 AD39 FLASHC ADDR15 U29 AD40 FLASHC ADDR16 029 40 FLASHC ADDR17 DN6000K 10 User Guide U29 AL40 Www dinigroup com BOARD HARDWARE
88. 44 TST HDRB109 U52 2 J1 145 P3N58 16 3 10 145 TST_HDRB110 U52 K2 J1 146 P3N53 J6 5 P10 146 TST_HDRB111 05212 1 147 P3N52 16 7 P10 147 TST_HDRB112 U52 N1 1 148 P3N51 J247 P10 148 TST HDRB113 U52 P1 J1 149 P3N50 J2 18 P10 149 TST_HDRB114 U52 R1 J1 150 P3N45 16 9 10 150 TST_HDRB115 U52 T2 1 151 No Connect PI0 151 GND J1 152 P3N44 J6 11 P10 152 TST HDRB116 U52 U2 1 153 P3N41 16 13 10 153 15 HDRB117 U52 V2 11 154 P3N40 16 15 10 154 TST HDRB118 U52 W2 11 155 P3N37 J6 17 P10 155 TST HDRB119 U52 Y3 J1 156 P3N36 16 19 P10 156 TST HDRB120 U52 AB3 11 57 P3N33 16 21 P10 157 TST HDRB121 U52 AD3 11 158 P3N32 J6 23 P10 158 TST_HDRB122 U52 AD1 1159 P3N31 J2 44 10 159 TST_HDRB123 U52 AE1 DN6000K10 User Guide Www dinigroup com 160 BOARD HARDWARE Daughter Card Connections DN6000K10 IO Connections Test Header B Signal Name Connector Test Signal Name FPGA Pin Header J1 160 P3N30 J2 45 P10 160 TST HDRB124 U52 AF1 1 161 P3N25 J6 25 P10 161 TST HDRB125 U52 AG2 11 162 No Connect 10 162 GND 1163 P3N24 J6 27 P10 163 TST HDRB126 U52 AH2 11 164 P3N21 J6 29 P10 164 TST_HDRB127 U52 AJ2 1 165 P3N20 16 31 P10 165 TST HDRB128 U52 AK2 11 166 P3N17 J6 33 P10 166 TST HDRB129 U52 AM1 J1 167 P3N16 16 35 10 167 TST HDRB130 U52 AN1 11 168 P3N13 J6 37 P10 168 TST HDRB131 U52 AP
89. 5 22 SYS_ECLKn U52 AN21 U65 23 RCKTIO_OSCT_Ep U52 F21 059 14 RCKTIO OSCT En U52 G21 1359 15 RCKTIO OSCB Ep U52 AT21 U59 11 RCKTIO_OSCB_En U52 AU21 U59 12 Signal Name FPGA F Pin Clock Refdes and Pin ACLK5 U51 AP21 U62 64 BCLK5 U51 AN21 063 64 USER FCLKp U51J22 U1 46 USER_FCLKn U51 K22 U1 47 SYS_FCLKp U51 AU22 065 46 SYS FCLKn U51 AT22 U65 47 RCKTIO_OSCT_Fp U51 G22 U50 14 RCKTIO OSCT Fn U51 F22 U50 15 RCKTIO OSCB Fp U51 AT21 050 11 RCKTIO OSCB Fn U51 AU21 U50 12 DDR FCLKp U51 K21 041 5 DN6000K 10 User Guide www dinigroup com 75 BOARD HARDWARE DDR FCLKn U51J21 U41 6 Signal Name FPGA G Pin Clock Refdes and Pin ACLK6 U80 AP21 062 61 BCLK6 U80 AN21 U63 61 USER_GCLKp 080 722 01 44 USER GCLKn U80 K22 U1 43 SYS_GCLKp U80 AU22 065 44 SYS U80 AT22 U65 43 RCKTIO_OSCT_Gp U80 G22 U70 14 RCKTIO_OSCT_Gn U80 F22 U70 15 RCKTIO_OSCB_Gp U80 AT21 U70 11 RCKTIO_OSCB_Gn U80 AU21 U70 12 DDR_GCLKp U80 K21 U87 5 DDR_GCLKn U80J21 U87 6 Signal Name FPGA H Pin Clock Refdes and Pin ACLK7 U78 AU22 U62 59 BCLK7 U78 AN22 U63 59 USER_HCLKp U78 K21 11 39 USER U78 J21 U1 40 SYS HCLKp U78 AP21 U65 39 SYS_HCLKn U78 AN21 U65 40 RCKTIO_OSCT_Hp U78 G21 067 14 RCKTIO OSCT U78 F21 U67 15 RCKTIO OSCB Hp U78 AT21 U67 11 RCKTIO_OSCB_Hn U78 AU21 067 12 Signal Name FPGA I Pin Clock Refdes and Pin ACLK8 U79 K21 U62 61 BCLK8 U79 F21 U6
90. 8 AC36 J1 018 BP2NX4 P2NX4 13 11 P9 18 TST_HDRA6 U28 AC37 J1 019 P2NX1 12 10 9 19 TST_HDRA7 U28 AC40 J1 020 P2NX0 J241 P9 20 TST HDRAS U28 AB33 J1 021 P3NX9 12 40 9 21 TST_HDRA9Y U28 AB36 DN6000K 10 User Guide www dinigroup com 145 BOARD HARDWARE Daughter Card Connections DN6000K10 IO Connections Test Header A Test Signal Name Connector Test Signal Name FPGA Pin Header Header 1 022 No Connect 9 22 GND J1 023 P3NX8 2 41 9 23 TST HDRA10 U28 AB40 1 024 BP3NX5 P3NX5 1913 P924 TST HDRA11 U27 AW42 1 025 BP3NX4 P3NX4 1815 9 25 TST HDRA12 027 42 1 026 BP3N89 P3N89 13 17 P9 26 TST HDRA13 U27 AU42 1 027 BP3N88 P3N88 13 19 9 27 TST HDRA14 U27 AT42 1 028 BP3N87 P3N87 3 21 P9 28 TST HDRA15 U27 AP41 1 029 BP3N86 P3N86 J3 23 P9 29 TST HDRA16 U27 AP42 1 030 BP3N83 P3N83 18 25 9 30 TST HDRA17 027 42 1 031 BP3N82 P3N82 13 27 9 31 TST HDRA18 27 42 1 032 BP3N77 P3N77 13 29 9 32 TST HDRA19 U27 AK41 11 033 No Connect P9 33 GND J1 034 BP3N76 P3N76 13 31 9 34 TST 20 27 42 1 035 BP3N75 P3N75 J3 33 P9 35 TST HDRA21 U27 AH42 J1 036 BP3N74 P3N74 18 35 9 36 TST HDRA22 27 41 1 037 P3N69 12 42 9 37 TST HDRA23 U27 AE41 11 038 P3N68 2 43 9 38 TST HDRA24 U27
91. 9 10 50 TST HDRB35 052 01 1 051 P3N46 J2 20 10 51 TST HDRB36 U52 V1 1 052 BP3N43 P3N43 14 5 10 52 TST HDRB37 U52 W1 J1 053 BP3N42 P3N42 14 7 10 53 TST HDRB38 U52 W3 1 054 BP3N39 P3N39 4 9 P10 54 TST HDRB39 U52 AA3 11 055 No Connect P10 55 GND J1 056 BP3N38 P3N38 J4 11 P10 56 TST_HDRB40 U52 AC3 11 057 BP3N35 P3N35 14 13 P10 57 TST HDRBA1 U52 AD2 1 058 BP3N34 P3N34 14 15 P10 58 TST_HDRB42 U52 AE2 J1 059 BP3N29 P3N29 4 17 P10 59 TST HDRB43 U52 AF2 11 060 BP3N28 P3N28 14 19 P10 60 TST_HDRB44 U52 AH1 11 061 BP3N27 P3N27 421 P10 61 TST HDRB45 U52 AJ1 1 062 BP3N26 P3N26 J4 23 P10 62 TST_HDRB46 U52 AK1 DN6000K10 User Guide Www dinigroup com 155 BOARD HARDWARE Daughter Card Connections DN6000K10 IO Connections Test Header B Test Signal Name Connector Test Signal Name FPGA Pin Header Header J1 063 P3N23 2 21 210 63 TST HDRB47 U52 AL2 11 064 P3N22 2 22 P10 64 TST 48 U52 AM2 11 065 BP3N19 P3N19 14 25 P10 65 TST HDRB49 U52 AN2 11 066 No Connect P10 66 GND 11 067 BP3N18 P3N18 14 27 10 67 TST HDRB50 U52 AP2 11 068 BP3N15 P3N15 4 29 210 68 TST HDRB51 U52 AT1 11 069 BP3N14 P3N14 4 31 210 69 TST HDRB52 U52 AU1 1 070 P3N9 J2 23 P10 70 TST HDRB53 U52 AV1 1 071 P3N8 J2 24 P10 71 TST HDRB54 U52 AW1 U53 AB4 J1 072 BP3N7 P3N7 4 33 P10 72 FD50 and U51 A
92. A4 U53 AC3 J1 073 BP3N6 P3N6 14 35 10 73 21051 and 051 U53 AC4 J1 074 BP3N3 P3N3 4 37 P10 74 FD52 and U51 Y4 U53 AD1 J1 075 BP3N2 P3N2 14 39 10 75 21153 and 051 41 U53 AD3 J1 076 BP4N27 P4N27 J4 41 P10 76 FD55 and U51 W3 J1 077 No Connect P10 77 GND U53 AE2 J1 078 BP4N26 P4N26 14 43 P10 78 FD58 and U51 V2 U53 AF2 11 079 BP4N21 P4N21 14 45 10 79 FD60 and U51 U2 U53 AG2 11 080 BP4N20 P4N20 14 47 P10 80 FD62 and US1 T2 U53 AH1 1 081 No Connect P10 81 FD64 and 05181 11 082 No Connect 10 82 266 1753 DN6000K 10 User Guide www dinigroup com 156 BOARD HARDWARE Daughter Card Connections DN6000K10 IO Connections Test Header B Test Signal Name Connector Signal Name FPGA Pin Header Header and U51 R3 U53 AJ2 J1 083 No Connect P10 83 FD68 U51 P2 U53 AK1 11 084 No Connect P10 84 FD70 and U51 N1 U53 AK2 J1 085 No Connect P10 85 FD71 and U51 N2 U53 AL2 1 086 No Connect P10 86 FD73 and U51 M2 U53 AM1 J1 087 No Connect P10 87 FD75 and 05111 J1 088 No Connect P10 88 GND U53 AN1 11 089 No Connect RU and U51 K1 U53 AN3 11 090 No Connect Bie 599 and U51 K3 U53 AP2 11 091 No Connect P10 91 FD82 and U51 J2 U53 AR3 J1 092 No Connect P10 92 FD84 and U51 H3 J1 093 No Connect P10 93 1 5V U53 AT3 J1 094 No Connect P10 94 FD87 and U51 G3 U53 AU2 1 095 PANX7 17 45 10 95 FD89 and U51 E2 U53 AU3 1 096 P4NX6
93. AD41 1 039 BP3N67 P3N67 19 37 9 39 TST HDRA25 U27 AC33 1 040 BP3N66 P3N66 13 39 9 40 TST HDRA26 U27 AC34 1 041 BP3N63 P3N63 J3 41 P9 41 TST HDRAZ7 U27 AC37 1 042 BP3N62 P3N62 J3 43 9 42 TST HDRA28 U27 AC40 1 043 BP3N57 P3N57 J3 45 P9 43 TST HDRA29 U27 AB34 J1 044 No Connect P9 44 GND 1 045 BP3N56 P3N56 J3 47 P9 45 TST U27 AB39 11 046 No Connect P9 46 TST_HDRA31 U27 AB31 1 047 No Connect P9 47 TST_HDRA32 U27 AA33 DN6000K 10 User Guide www dinigroup com 146 BOARD HARDWARE Daughter Card Connections DN6000K10 IO Connections Test Header A Test Signal Name Connector Test Signal Name FPGA Pin Header Header J1 048 BP3N49 P3N49 141 P9 48 TST_HDRA33 U27 AA36 1 049 BP3N48 P3N48 143 P9 49 TST 4 U27 Y32 1 050 P3N47 12 19 9 50 TST HDRA35 U27 Y34 1 051 P3N46 12 20 9 51 TST HDRA36 U27 Y36 1 052 BP3N43 P3N43 5 P9 52 TST HDRA37 027 731 1 053 BP3N42 P3N42 4 7 P9 53 TST U27 W33 1 054 BP3N39 P3N39 14 9 P9 54 TST HDRA39 U27 W35 11 055 No Connect 9 55 GND J1 056 BP3N38 P3N38 1411 9 56 TST HDRA40 U27 W41 1 057 BP3N35 P3N35 14 13 P9 57 41 U27 V31 1 058 BP3N34 P3N34 14 15 9 58 TST HDRA42 U27 V33 1 059 BP3N29 P3N29
94. ARD HARDWARE Signal Name FPGA Pin DDR 1 CKE U27 D26 DDR FPGA A1 CSN U27 L23 DDR FPGA A1 RASN U27 D24 DDR FPGA A1 WEN U27 K23 DDR A2 DATAO U27 H30 DDR A2 1 U27 G30 DDR A2 DATA2 U27 K30 DDR A2 DATA3 U27 30 DDR A2 DATA4 U27 M30 DDR A2 DATA5 U27 L30 DDR A2 027 731 DDR 2 DATAT7 027 931 DDR 2 DATAS8 U27 F32 DDR A2 9 U27 E32 DDR A2 DATA10 U27 D33 DDR A2 DATA11 027 33 DDR A2 DATA12 U27 G33 DDR A2 DATA13 U27 F33 DDR_A2_DATA14 02733 DDR A2 DATA15 U27 H33 DDR FPGA A2 ADDO U27 H28 DDR FPGA A2 ADD1 U27 K28 DDR FPGA A2 ADD2 U27 L28 DDR FPGA A2 ADD3 U27 B29 DDR FPGA A2 ADD4 U27 D29 DDR FPGA A2 ADD5 U27 G29 DDR FPGA A2 ADD6 U27 F29 DDR FPGA A2 ADD7 U27 H29 DDR FPGA A2 ADDS8 DN6000K 10 User Guide U27 L29 www dinigroup com 109 BOARD HARDWARE Signal Name FPGA Pin DDR FPGA A2 ADD9 U27 K29 DDR A2 ADD10 U27 C30 DDR 2 ADD11 U27 D30 DDR 2 ADD12 27 30 DDR FPGA 2 ADD13 27 30 DDR 2 0008 27 34 DDR 2 108 27 631 DDR 2 UDM 27 K32 DDR A2 LDM 27 031 DDR FPGA 2 27 E34 DDR FPGA 2 BA1 27 34 DDR 2 CASN 27 32 DDR FPGA 2
95. ARDWARE 3 3 43 3V 3 3 3 3 0 1uF PLL2BN eve 0 1uF PLL1B C1745 0 1UF PLL1BN C1746 0 1uF R525 82 5 Figure 22 LVPECL Clock Input and Termination Note The schematic shows capacitors in locations C1747 C1748 C1745 C1746 These are actually populated with 0 ohm resistors for direct connection to the RoboClock reference inputs The terminating resistors to GDN and 3 3V are not stuffed When using LVPECL make the required hardware changes 4 2 1 Clock Source J umper Header Figure 23 shows JP5 the clock source header connector used to select between different clock soutces CLOCKA CLOCKB Clock Source Jumpers Figure 23 Clock Source Jumper 4 3 Roboclocks Two 3 3V half can oscillator sockets X2 and the signal CFPGA_CLKOUT from the Configuration FPGA provide on board input clock solutions The DN6000K10 is shipped with both 14 318MHz X3 and 33 33MHz X2 oscillator Neither X2 nor X3 are used by the configuration circuitry so the user is free to stuff any standard 3 3 V half can oscillators in the X2 and X3 positions The oscillators interface to two high speed multi phase RoboClock buffers 431 RoboClock PLL Clock Buffers The CY7B994V U62 U63 High Speed Multi Phase PLL Clock Buffers offer user selectable control over system clock functions Each chip has 16 output clocks along DN6000K10 User
96. ARE Signal Name Desctiption Connector reference input This input has an internal pull down 1 FS ROBOCLOCK 1 Frequency Select This JP4 B2 input must be set according to the nominal frequency Refer to Table 1 in the datasheet ROBO ROBOCLOCK 1 Feedback Output Phase Function Select Controls the phase function of bank 3 amp 4 CCLK of outputs refer to Table 3 in the datasheet ROBO FBDSO ROBOCLOCK 1 Feedback Divider Function Select These inputs determine the function of the QFAO and QFA1 outputs Refer to Table 4 in the datasheet ROBO1_FBDS1 ROBOCLOCK 1 Feedback Divider Function Select These inputs determine the function of the QFAO and QFA1 outputs Refer to Table 4 in the datasheet ROBO1_FBDIS ROBOCLOCK 1 Feedback Disable This input controls the state of QFA 0 1 When HIGH QFA 0 1 is disabled to the HOLD OFF or HI Z state the disable state is determined OUTPUT MODE When LOW the QFA 0 1 is enabled Refer to Table 5 in the datasheet This input has an internal pull down ROBO F0 ROBOCLOCK 7H Output Phase Function Select Controls the phase function of bank 1 2 5 amp 4 ACLK of outputs Refer to Table 3 in the datasheet ROBO1_F1 ROBOCLOCK 1 Output Phase Function Select Controls the phase function of bank 1 2 3 amp 4 DCLK of outputs Refer to Table 3 in the datasheet 080 ROBOCLOCK 1 Output Divider Function Select Contro
97. BPZNX6 P2NX6 J3 7 P1116 TST HDRC4 U80 AG2 1 017 BPZNX5 P2NX5 3 9 P1117 TST HDRC5 U80 AH1 1 018 BP2NX4 P2NX4 311 P11 18 TST HDRC6 U80 AH3 1 019 P2NX1 J2 10 P11 19 TST HDRC7 U80 AJ2 J1 020 P2NX0 P11 20 TST HDRC8 U80 AK1 1 021 P3NX9 J2 40 P11 21 TST HDRC9 U80 AK3 1 022 No Connect P11 22 GND 11 023 P3NX8 J241 P1123 IST U80 AL3 J1 024 BP3NX5 P3NX5 3 13 P1124 IST HDRC11 U80 AM2 J1 025 4 J3 15 P1125 TST_HDRC12 U80 AN1 J1 026 BP3N89 P3N89 3 17 P11 26 IST HDRC13 U80 AN3 DN6000K 10 User Guide www dinigroup com 164 BOARD HARDWARE Daughter Card Connections DN6000K10 IO Connections Test Header C Test Signal Name Connector Test Signal Name FPGA Pin Header Header J1 027 BP3N88 P3N88 3 19 P11 27 TST 14 U80 AP2 1 028 BP3N87 P3N87 J3 21 P11 28 TST HDRC15 U80 AR3 1 029 BP3N86 P3N86 12 23 P11 29 TST HDRC16 U80 AT2 1 030 BP3N83 P3N83 18 25 P11 30 TST_HDRC17 U80 AU1 1 031 BP3N82 P3N82 18 27 P11 31 TST HDRC18 U80 AU3 1 032 BP3N77 P3N77 13 29 P11 32 TST HDRC19 U80 AV2 1 033 No Connect P11 33 GND J1 034 BP3N76 P3N76 3 31 11 34 TST HDRC20 U80 AW1 1 035 BP3N75 P3N75 J3 33 11 35 TST HDRC21 078 02 J1 036 BP3N74 P3N74 13 35 11 36 TST HDRC22 U78 E1 1 037 P3N69 J242 P11 37 TST HDRC
98. CLUDE_FLASH Includes menu options associated with the FLASH device INCLUDE_DDR1 Includes menu options associated with DDR memory EXCLUDE DDR1 INCLUDE DDR2 Expands the DDR test range to twice the size EXCLUDE DDR2 DDR 32 MEG Defines DDR test range per DDR chip define one or DDR 64 MEG the other or none if neither DDR is included These files may be editted by hand or modified with the build utility as follows make INCLUDE DDR2 makes changes to synplicity projects EDK source code and UCF files to include DDR2 make EXCLUDE DDR2 makes changes to synplicity projects EDK source code and UCF files to exclude DDR2 make 32 makes changes to synplicity projects and EDK source code to set DDR size make 64 makes changes to synplicity projects and EDK source code to set DDR size make DDR 128 MEG makes changes to synplicity projects and EDK source code to set DDR size DN6000K 10 User Guide ww w dinigroup com 37 INTRODUCTION THE SOFTWARE TOOLS V Setting up the build utility make bat The following tools must be installed on the system to use make bat Xilinx ISE Xilinx EDK Synplicity Pro In the section below VoXILIN should be replaced with your Xilinx install directory By default this is C Xilinx XILINX_EDK should be replaced with your Xilinx EDK install directory This is commonly C Xilinx EDK SYNPLICITY should be replaced
99. Clock Driver 14 Connection between FPGA and External PPC Oscillator e 15 Connections between FPGA s and Rocket IO Clock Synthesizers e 16 PPC Reset 17 Connection between FPGA and FLASH 18 Connection between FPGA s and DDR SDRAM s e 19 Connections between FPGA and SMA Connector e 20 RocketIO Performance e 21 CPU Debug connection to e 22 Combined CPU Trace Debug connection to FPG e23 GPDED EBEDY S e 24 MCU 1 5 e 25 GPIO LED s e 26 Voltage Indicators e 27 External Power Connections e 28 Connection between FPGA and the Daughter Card Headers ABOUT THIS MANUAL Chapter About This Manual This User Guide accompanies the DN6000K10 LOGIC Emulation Board For specific information regarding the Virtex II Pro parts please reference the datasheet 1 Manual Contents This manual contains the following chapters Chapter 1 Getting Started contains information on the contents of the LOGIC Emulation Kit Chapter 2 Introduction to the Virtex II and ISE an overview of the Vitex II platform and the software features Chapter 3 Introduction to the Software Tools information regarding the reference design and test software Chapter 4 Programming Configuring the Hardware step by step information on programming and configuring the h
100. Connection Figure 32 DDR SDRAM Connection Figure 33 SSTL2 Class 1 Termination Figure 34 SSTL2 Class 2 Termination Figure 35 DDR VTT Termination Regulator Figure 36 RocketIO Block Diagram Figure 37 CPU Debug Connector Figure 38 Combined Trace Debug Connector Pinout Figure 39 ATX Power Supply Figure 40 External Power Connection Figure 41 Optional PWR Connector Figure 42 Front Panel Indicator Switch Figure 43 Test Header Figure 44 Test Header Pin Numbering Figure 45 DN3000K10SD Daughter Card Block Diagram Figure 46 DN3000K10S Daughter Card Figure 47 Assembly drawing for the DN3000K10SD Figure 48 PM7200 Server Case List of Tables Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab Tab e 1 Jumper Description e 2 S2 Dipswitch Configuration Settings 3 HyperTerminal Main Menu Options e 4 HyperTerminal Interactive Configuration Menu Options e 5 FPGA Configuration Modes e 6 FPGA configuration file sizes 7 Connection between Configuration FPGA MCU 8 FPGA JTAG connection to Configuration FPGA e 9 Clocking inputs to the FPGA s e 10 Clock Source Signals e 11 RoboClock Configuration Signals e 12 Connection between FPGA and External PPC Oscillator 13 Connection between FPGA s and DDR PLL
101. DATA3 U80 R3 FLASHG DATA4 U80 13 FLASHG DATA5 080 02 _ U80 V1 FLASHG U80 W1 FLASHG DATAS U80 P1 FLASHG DATA9 U80 P3 FLASHG DATA10 U80 R2 FLASHG DATA11 080 72 eS DN6000K 10 User Guide www dinigroup com 101 BOARD HARDWARE Signal Name FPGA Pin FLASHG DATA12 U80 U1 FLASHG DATA13 U80 U3 FLASHG DATA14 U80 V2 FLASHG DATA15 c c U80 W2 FLASHG CEN U80 N1 FLASHG OEN U80 N2 U U c FLASHG WEN 80 G2 FLASHG WPN 80 H2 FLASHI ADDRO U79 AM3 FLASHI ADDR1 U79 AM2 FLASHI ADDR2 U79 AM1 FLASHI ADDR3 U79 AL3 FLASHI ADDR4 U79 AL2 FLASHI ADDR5 U79 AK3 FLASHI ADDR6 U79 AK2 FLASHI ADDR7 U79 AK1 FLASHI ADDRS8 U79 AF3 FLASHI ADDR9 U79 AF2 FLASHI_ADDR10 U79 AF1 FLASHI ADDR11 U79 AE2 FLASHI ADDR12 U79 AE1 FLASHI ADDR13 U79 AD3 FLASHI ADDR14 U79 AD2 FLASHI_ADDR15 U79 AD1 FLASHI_ADDR16 U79 AW3 FLASHI ADDR17 U79 AJ3 FLASHI ADDR18 U79 A 2 FLASHI ADDR19 U79 AJ1 FLASHI ADDR20 U79 AG3 c cC c c CH CIO C DN6000K 10 User Guide www dinigroup com 102 BOARD HARDWARE Signal Name FPGA Pin FLASHI_ADDR21 U79 AG2
102. Encryption Standard DES operation Xilinx software tools offer an optional encryption of the configuration data bitstream with a triple key DES determined by the designer The keys are stored in the FPGA by JTAG instruction and retained by a battery connected to the VBATT pin when the device is not powered Virtex II Pro devices can be configured with the corresponding encrypted bitstream using any of the configuration modes described previously A detailed description of how to use bitstream encryption is provided in the Pro Platform FPGA User Guide DN6000K10 User Guide www dinigroup com 59 BOARD HARDWARE Chapter Board Hardware l Introduction to the Board DN6000K10 Logic Emulation board provides for a comprehensive collection of peripherals to use in creating a system around the Virtex II Pro Figure 11 is a block diagram of the DN6000K10 Logic Emulation board FIXME below diagram DN6000K10 BLOCK DIAGRAM VOLTAGE INDICATORS FPGA CONFIGURATION USING SMARTMEDIA BUS 1 32 255550 HI Ge DDRVIT SMARTMEDIA _ SWITCHING 1 25V
103. F1 DATAS 05117 DDR_F1_DATAG 051 17 DDR F1 U51 G17 DDR F1 DATAS8 U51 K18 DDR F1 DATA9 U51 L18 DDR DATA10 U51 G18 DDR DATA11 U51 H18 DDR DATA12 051 817 DDR F1 DATA13 051 818 DDR F1 DATA14 05119 DDR F1 DATA15 U51 K19 DDR F1 ADDO U51 C14 DDR FPGA 1 ADD1 U51 C15 DDR F1 ADD2 051146 DDR FPGA F1 ADD3 U51 M16 DDR FPGA F1 ADD4 151 16 DDR 1 ADD5 U51 K16 DDR FPGA F1 ADD6 U51 H16 G ci Cb LE See ere EGG aye DN6000K 10 User Guide www dinigroup com 116 BOARD HARDWARE Signal Name FPGA Pin DDR SDRAM DDR FPGA F1 ADD7 U51 G16 U45 38 DDR FPGA F1 ADDS8 U51 G19 U45 39 DDR FPGA F1 ADD9 U51 H19 U45 40 DDR FPGA F1 ADD10 U51 E19 U45 28 DDR FPGA F1 ADD11 E19 U45 41 DDR FPGA F1 ADD12 U51 D19 U45 42 DDR FPGA F1 ADD13 U51 C19 U45 17 DDR_FPGA_F1_UDQS U51 M19 U45 51 DDR_FPGA_F1_LDQS U51 D17 045 16 DDR FPGA F1 UDM U51 C18 U45 47 DDR FPGA F1 LDM U51 D16 U45 20 DDR FPGA F1 U51 C20 U45 26 DDR FPGA F1 BA1 U51 D20 U45 27 DDR FPGA F1 CASN U51 K20 U45 22 DDR FPGA F1 U51 M21 U45 44 DDR FPGA F1 CSN U51 20 U45 24 DDR FPGA F1 RASN U51 L20 U45 23 DDR FPGA F1 WEN
104. FPGA H is 2vp100 0 if 2vp70 Bit 17 1 if FPGA Lis 2vp100 0 if 2vp70 183 184
105. FPGA Pin DDR SDRAM DDR_FPGA_I2_ADD5 UP U 83 36 DDR FPGA I2 ADD6 U79 AW13 83 37 DDR FPGA I2 ADD7 U79 AY13 83 38 DDR FPGA I2 ADD8 79 12 83 39 DDR FPGA I2 ADD9 79 12 83 40 DDR FPGA I2 ADD10 79 AV11 83 28 DDR FPGA I2 ADD11 T9 ALTI 83 41 DDR FPGA I2 ADD12 79 AY10 83 42 DDR FPGA I2 ADD13 U U U U U U 79 AYTI 83 17 DDR_FPGA_I2_UDQS U79 AT13 83 51 DDR FPGA I2 LDQS U79 AR15 83 16 DDR_FPGA_I2_UDM U79 AW12 83 47 DDR FPGA I2 LDM U79 AR14 83 20 DDR I2 BAO U79 AL16 83 26 DDR FPGA I2 BA1 U79 AM16 83 27 DDR FPGA I2 CASN U79 AV10 83 22 DDR FPGA I2 CKE U79 AN11 83 44 DDR FPGA I2 CSN U79 AR11 83 24 DDR_FPGA_I2_RASN U79 AW10 83 23 DDR FPGA I2 WEN U79 AU10 U U U U U U U U U U U U U U U U U U U 83 21 7 0 Transceivers The multigigabit transceivers can transmit data at speeds from 622 Mb s up to 3 125 Gb s determined be the speed grade of the part please refer to the Xilinx datasheet are capable of various high speed serial standards such as Gigabit Ethernet FiberChannel InfiniBand and XAUI In addition the channel bonding feature ageregates multiple channels allowing for even higher data transfer rates For additional information on RocketIO
106. Features cei 24 3 1 1 Design Entry 24 3 1 2 Synthesis eerie 5225 3 1 3 Implementation and Configuration 1 25 3 1 4 Board Level Integration nnas 26 4 VIRTEX II PRO DEVELOPER S 26 INTRODUCTION TO THE REFERENCE DESIGN eese eese estate tatnen ense tata tasses essa tatnen 28 1 EXPLORING THE REFERENCE DESIGN QUU 28 1 1 What is the Reference Design 5 1 2 Using the Reference Design uiu ee rere ta p OD REO OH 1 3 Compiling The Reference Design 31 1 3 1 The Xilinx Embedded Development Kit 31 132 Synplicity 31 1 3 3 Xilinx ISE 231 1 3 4 The Build Utility Make bat 2 31 2 GETTING MORE INFORMATION 39 2 1 Printed 39 222 39 2 3 Online DOCUMENTATION wii 39 PROGRAMMING CONFIGURING THE HARDWARE cssscsssssssssssscsssssecsssessssessesessssscssssssecsssessssessscessssecsssessesesesesesessessssessssecsscessesessesecsesesseseeses 40 1 PROGRAMMING THE CONFIGURATION FPGA 2 MCU DETAILS PROGRAMMING THE MCU
107. Figure 3 Figure 3 DN6000k10 Not Found DN6000k10 USB Controller Edit FF figuration A Memor fx The DN6000k10 was not found Clear Log 1 1 2 Basic Menu Operations If the USBController finds the DN6000k10 and the USB cable was plugged into the PC before power was turned on to the DN6000k10 you will see the following screen If the USB Cable was plugged into the DN6000k10 after it powered on you will see the following screen DN6000K 10 User Guide www dinigroup com 15 INTRODUCTION VIRTEX II AAND ISE 1 1 3 Enable Disable USB to FPGA Communication Disable USB gt FPGA Com This button allows you to disable the USB to FPGA communication via the Spartan II When the USB interface 1s used the Spartan II will drive main bus MB pins 0 39 in order to provide USB communication to the FPGAs This makes main bus pins 0 39 unusable for any other purpose If your design requires the use of these pins it is necessaty to disable USB to FPGA communication which will cause the Spartan II to cease driving these pins and release them for other purposes Note USB to FPGA communication is disabled by default Note In order to run our reference design USB to FPGA communication must be enabled 1 1 4 File Menu The File Menu has the following 2 options 1 Open opens a file with the selected text editor notepad by default To change the text editor see Settings Info Menu section
108. G2 DATAO U80 H10 DDR G2 DATA1 U80J10 DDR_G2_DATA2 U80 F10 DDR_G2_DATA3 80 G10 DDR G2 DATA4 80 E10 DDR G2 DATAS 80 D10 DDR G2 DATAG 80 C10 DDR G2 80 C11 DDR G2 DATAS 80 K14 DDR G2 DATA9 080 114 DDR G2 DATA10 080 14 DDR G2 DATA11 U80 G14 DDR 62 DATA12 U80 D14 DDR G2 DATA13 U80 E14 DDR G2 DATA14 U80 L15 DDR G2 DATA15 U80 K15 c U U U U U U U U U U U U U U DN6000K 10 User Guide www dinigroup com 120 BOARD HARDWARE Signal Name FPGA Pin DDR FPGA G2 ADDO U80 G12 c DDR FPGA G2 ADD1 U80 F12 DDR_FPGA_G2_ADD2 U80 D12 DDR_FPGA_G2_ADD3 U80 L13 DDR_FPGA_G2_ADD4 U80 M13 DDR_FPGA_G2_ADD5 U80J13 DDR_FPGA_G2_ADD6 U80 K13 DDR FPGA G2 ADD7 U80 G13 DDR FPGA G2 ADDS8 U80 H13 DDR FPGA G2 ADD9 U80 E13 DDR FPGA G2 ADD10 U80 F13 DDR G2 ADD11 U80 D13 DDR FPGA G2 ADD12 U80 C13 DDR FPGA G2 ADD13 U80 M15 DDR FPGA G2 UDQS U80 F15 DDR FPGA G2 LDQS U80 F11 DDR FPGA G2 UDM U80 H15 DDR G2 U80 H11 DDR FPGA G2 BAO U80 F9 DDR FPGA G2 U80 E9 DDR_FPGA_G2_CASN U80 H12
109. GH QFA 0 1 is disabled to the HOLD OFF or HI Z state the disable state is determined OUTPUT MODE When LOW the QFA 0 1 is enabled Refer to Table 5 in the datasheet This input has an internal pull down ROBO2 F0 ROBOCLOCK Z2 Output Phase Function Select Controls the phase function of bank 1 2 5 amp 4 ACLK of outputs Refer to Table 3 in the datasheet DN6000K 10 User Guide www dinigroup com 82 BOARD HARDWARE Signal Name Desctiption Connector ROBO2 F1 ROBOCLOCK Z2 Output Phase Function Select Controls the phase function of bank 1 2 3 amp 4 DCLK of outputs Refer to Table 3 in the datasheet JP7 B8 2 1050 ROBOCLOCK Z2 Output Divider Function Select Controls the divider function of bank 1 2 3 amp 4 ACLK of outputs Refer to Table 4 in the datasheet 2 DS1 ROBOCLOCK Z2 Output Divider Function Select Controls the divider function of bank 1 2 3 amp 4 ACLK of outputs Refer to Table 4 in the datasheet JP7 B10 Enable for Oscillator A X9 ROBO DIS Enable for Oscillator B X8 ROBOCLOCK 1 Output Disable Each input controls the state of the respective output bank When HIGH the output bank is disabled to the HOLD OFF or HI Z state the disable state is determined by OUTPUT MODE When LOW the 4 0 0 1 is enabled See Datasheet These inputs each have
110. N6000K10 User Guide Www dinigroup com 142 BOARD HARDWARE 11 2 2 Power Supply A linear power supply U4 is present to provide level shift translation functions when the board is populated with passive bus switches Resistors R10 and R11 can be used to select alternate voltage sources 5V or 3 3V respectively When used U4 must be removed in order to prevent contention The power supplies is rated as follows 5 V power supply is rated for 1 A 3 3 V power supply is rated for 1 A 1 5 V power supply is rated for 1 A 12 V power supply is rated for 0 5 e 12V power supply is rated for 0 5 NOTE Never populate R10 R11 simultaneously this will result in a shorting the 3 3V and 5V power supplies Header J8 allows external connection to the Power Sources refer to Table 27 for connection details Table 27 External Power Connections Pin Function Pin Function J8 1 GND J8 11 GND J8 2 5V 18 12 1 5V J8 3 GND J8 13 GND 18 4 5V J8 14 12V J8 5 GND 8 15 J8 6 T3 9V 8 16 12V J8 7 GND J8 17 GND J8 8 3 3V 8 18 12V DN6000K 10 User Guide www dinigroup com 143 BOARD HARDWARE 11 2 3 Unbuffered 10 The DN3000k10SD Daughter Card provides 66 unbuffered 1 O signals including 5 single ended clock signals available on headers J5 J6 and J7 The function of these signals is position dependent 11 2 4 Buffered 10 The DN3000k10SD Daughter Card pro
111. O Differential LVDS pairs Note Not available on DN6000K10 Logic Emulation board Headers for Test Points The daughter card contains headers that may be useful with certain types of oscilloscope probes or when wiring pins to prototype areas Figure 45 is a block diagram of the daughter card DIFFERENTIAL js ECLK1 4 MBCK6 j DIFF CLOCK J3 J4 J5 J6 J7 50 PIN IDC HEADER UNBUFFERED 0 17 J2 A N DIFF PAIR 0 15 J6 UNBUFFERED 10 0 23 50 PIN MINI D RIBBON CABLE p CONNECTOR 7 UNBUFFERED 10 0 23 LINEAR REGULATOR 12VDC TO 3 3 3 9VDC J POWER INDICATORS A N C3 CC NUR BUFFERED I O 0 15 Ut UNBUFFERED l O 0 15 A 3 3 5 0 12 0 93 BUFFERED 10 0 7 POWER 02 ees VO 0 15 HEADER BUFFERED 10 0 7 41 5V I 3 3V J4 5 0 12 0v 98 BUFFERED 1 0 0 15 03 UNBUFFERED 0 15 12 0 N N y GND 20 PIN IDC 74LVC16245APA 200 PIN MICROPAX HEADER 74FST163245PA BOTTOM OF PWB Ut 02 03 BUFFERS OR LEVEL TRANSLATORS Figure 45 DN3000K10SD Daughter Card Block Diagram The DN3000K10SD Daughter Card provides 16 differential pairs 48 buffered passive active L O a
112. OM MCS file in the window prompting the file name and click OK Select Bypass for the second device in the chain XC28150 The following window would be displayed DN6000K 10 User Guide www dinigroup com 43 PROGRAMMING CONFIGURING THE HARDWARE untitled Configuration Mode iMPACT File Edit View Mode Operations Output Help Da Pe SSB 55 2 Boundary Scan Slave Serial SelectMAP Desktop Configuration TDI Assign New Configuration File 3 18 01 File 2 i File Look in C3 ISE MCS File Size 357 KB File name prom mcs Open 501 1 1 Files of type mcs Files mes Cancel ES SUE Bypass 2 Device 1 selected pti or Help press F1 Configuration Mode 5 Parallel Note Two devices should be detected XC18V01 and 25150 10 Select the XC18VO01 right click and select Program option The XC2S150 is not programmed 11 Select the Erase before programming and the Erase option before clicking the OK button DN6000K 10 User Guide www dinigroup com 44 PROGRAMMING CONFIGURING THE HARDWARE Program Options 2i xj Program Load FPGA Secure Mode 7 Parallel Mode Program Key Use DA for CE Use
113. RATI4 TST 5 50 150 5 TST_HDRA36 51 M6 151 GND TST HDRA37 52 7152 LL TST HDRATIS 5 8 53 153 IST HDRATI7 ST 9 54 154 ST HDRATTS GND 55 155 9 ISI ___56 7 156 HDRA41 57 7 7157 _ TST 121 TST HDHA4Z 58 7158 TST_HDRAT22 TST HDRA43 59 7 159 TST HDHA123 TST HDRA44 60 17160 TST_HDRAT24 TST HDRA45 61 161 TST HDRA125 HDHA46 62 162 GND TST_HDRA47 63 163 TST 26 TISI HDHAMS ___64 m64 TST HDRA127 7 ST HDHA4S 65 165 ST 2 GND 66 166 TST 129 ST_HDRASO 67 7167 _ TST 68 168 TST 52 69 169 ST 2 ST 70 2 170 ST ST HDHA54 is 171 ST HDRAT34 TST HDHA55 72 172 ST 5 HDRA56 73 173 TST 57 74 174 __151_ 136 TST 58 75 7 TST 137 TST HDHA59 76 176 ST 8 GND 7 Dp ST 9 TST_HDRAGO 178 _ 5 0 _ TST HDRA61 79 7179 __151 TST 2 80 180 ST HDHAT42 ST_HDRAGS 81 7181 5 _ 43 TST HDRA64 82 182 5 HDRAT44 TST HDHA65 ___83 183 5 _ ST HDRA66 84 184 GND ST HDRA67 85 185 ST HDHAT46 TST_HDRAGS 86
114. R_D2_DATA9 U53 AL13 DDR_D2_DATA10 U53 AP13 DDR 02 DATA11 U53 AN13 DDR D2 DATA12 U53 AR12 DDR D2 DATA13 U53 AP12 DDR_D2_DATA14 53 AT12 DDR D2 DATA15 53 AU12 DDR FPGA D2 ADDO 53 AV15 DDR_FPGA_D2_ADD1 53 AU15 DDR_FPGA_D2_ADD2 53 AY14 DDR_FPGA_D2_ADD3 53 AY15 DDR_FPGA_D2_ADD4 53 AV13 DDR_FPGA_D2_ADD5 U U U U U U U U 53 AU13 DDR FPGA D2 ADD6 U53 AW13 DDR D2 53 AY15 DDR D2 ADDS8 53 AN12 DDR FPGA 02 ADD9 53 12 DDR FPGA D2 ADD10 53 AV11 DDR D2 ADD11 53 AU11 DDR FPGA D2 ADD12 53 A Y 10 DDR D2 ADD13 53 AY11 DDR FPGA D2 UDOS 53 AT13 DDR_FPGA_D2_LDQS 53 AR15 DDR FPGA D2 UDM U53 AW12 DDR FPGA D2 LDM U53 AR14 DDR FPGA D2 BAO DN6000K 10 User Guide U53 AL16 www dinigroup com Seb e ee e 115 BOARD HARDWARE Signal Name FPGA Pin DDR D2 U53 AM16 DDR FPGA D2 CASN U53 AW10 DDR D2 CKE U53 AN11 DDR FPGA D2 CSN U53 AR11 DDR FPGA D2 RASN U53 AV10 DDR D2 WEN U53 AU10 DDR F1 DATAO U51 M18 DDR F1 U51 M17 DDR F1 DATA2 U51 L17 DDR F1 DATA3 U51 K17 DDR F1 DATA4 U51 H17 DDR
115. Read register for MCU to issue the following commands Commands Register 0x1 test all functionality 0x2 test registers 0x3 test FLASH 0x4 test DDR s 0 5 test FPGA interconnect To issue a command MCU must write one of the above values to this register The MCU can then poll this register to check if the test 15 done register will return all zeros when finished Status Register 0 0 00 0008 0 0 00 0008 Read only register Status of commands and bus control Bits 16 18 must all be zero for MCU to issue any commands to External Host Command Register Status results can be read after command register is cleared decode for the test results is as follows Bit 0 overall pass fail pass 1 fail 0 Bit 1 register test pass fail Bit 2 flash test pass fail Bit 3 ddr test pass fail Bit 4 interconnect test pass fail Existing 0 0 00 0018 0 0 00 0018 Contains information on what FPGAs are stuffed on the Register DN6000k10 as well as what type of FPGAs they are The register has the following format Bit 0 1 if FPGA A is stuffed 0 otherwise Bit 1 1 if FPGA B is stuffed 0 otherwise Bit 2 1 if FPGA C is stuffed 0 otherwise Bit 2 1 if FPGA D is stuffed 0 otherwise Bit 2 1 if FPGA E is stuffed 0 otherwise Bit 2 1 if FPGA F is stuffed 0 otherwise Bit 2 1 if FPGA is stuffed 0 otherwise Bit 7 1 if FPGA is stuffed 0 oth
116. Select bit files to configure FPGA s 2 Set verbose level current level 2 3 Disable sanity check for bit files M Main menu ENTER SELECTION Connected 1 13 25 Auto detect _ 6008 N 1 SCROLL caes Capture Print echo Figure 10 Interactive Configuration Option Menu DN6000K 10 User Guide www dinigroup com 58 PROGRAMMING CONFIGURING THE HARDWARE Table 4 desctibes the Interactive Configuration Menu options Table 4 HyperTerminal Interactive Configuration Menu Options Function Description Select a bit file to The user is able to select a bit file from a list of bit files found on configure FPGA s the SmartMedia card for configuring the FPGA Set verbose level The user can change the verbose level from the current setting current level 2 NOTE If the user goes back to the main menu and configures the FPGA s using main txt the verbose level will be set to whatever setting is specified in main txt Disable Enable The user can disable or enable the sanity check depending on what sanity check for bit the current setting is files NOTE If the user goes back to the main menu and configures the FPGA s using main txt the sanity check will be set to whatever setting is specified in main txt Main menu Returns the user to the Main Menu 4 4 Bitstream Encryption Virtex II Pro devices have an on chip decryptor using one or two sets of three keys for triple key Data
117. THE DINI GROUP User Guide DNO6000K10 LOGIC EMULATION SOURCE DN6000K 10 User Manual Version 1 1 The Dini Group 1010 Peatl Street Suite 6 La Jolla CA92037 Phone 858 454 3419 Fax 858 454 1279 support dinigroup com www dinigroup com Table of Contents ABOUT THIS MANUAL Pr 1 1 MANUAL CONTENTS 1 2 ADDITIONAL RESOURCES 41 2 CONVENTIONS 55 3 1 m Ce 22 Online Document 3 4 RELEVANT INFORMATION i sic i Are ret Fen EXER axes EFE a Fa LER ra ead 4 GETTING STAR PED E 5 1 PRECAUTION 5 2 THE DN6000K10 LOGIC EMULATION KIT Rer 5 3 INSTALLATION INSTRUCTIONS teivas 7 3 1 Jumper Setup 3 2 Jumper Description 3 3 Switch Setup and Description 2 citar e M Foe OR en E E 10 3 4 Oscillator Setup d 3 5 PPC RS232 Port Setup 211 3 6 Powering ON 6000 10 0 211 4 PLAYING WITH YOUR DN6000K10 VIA THE 1 2 2 2
118. TWARE TOOLS step in to place and route or implement the design with the Xilinx ISE tools The fourth and final step is to compile the PowerPC code and embed it in the bitfile This fourth step is referred to by Xilinx as updating the bitfile Hence this fourth step will be referred to as the update step The build script creates a directory called out and places its output files there After the script completes you will find 3 files for each FPGA that was built Fpga bit is the file to be downloaded to the FPGA The fpga ui bit and the fpga_ bmm files are used by the Xilinx EDK in the update process to embed the PowerPC source code into the bitfile creating the final bitfile All of the steps mentioned above can be performed with the build script The following command line options are supported All Synthesizes implements and updates for all 9 fpga s Doesn t generate the PowerPC netlist Replace with A B C D E F G H or I Synthesizes implements and updates for the specified FPGA synthesize_ Replace with or all Synthesizes the specified FPGA or all FPGA s implement_ Replace with a b c d e f h 1 or Implements the specified FPGA or all FPGA s update_ Replace with or all Updates the specified FPGA or all FPGA s Clean Deletes all intermediate tool generated files Leaves out dir
119. The goal was to revolutionize system architecture from the ground up To achieve that objective the best circuit engineers and system architects from IBM Mindspeed and Xilinx co developed the world s most advanced FPGA silicon product Leading teams from top embedded systems companies worked together with Xilinx software teams to develop the systems software and IP solutions that enabled new system architecture paradigm The result is the first FPGA solution capable of implementing high performance system on a chip designs previously the exclusive domain of custom ASICs yet with the flexibility and low development cost of programmable logic The Virtex II Pro family marks the first paradigm change from programmable logic to programmable systems with profound implications for leading edge system architectures in networking applications deeply embedded systems and digital signal processing systems It allows custom user defined system architectures to be synthesized next generation connectivity standards to be seamlessly bridged and complex hardware and software systems to be co developed rapidly with in system debug at system speeds Together these capabilities usher in the next programmable logic revolution 2 1 Summary of Virtex4l Pro Features The Virtex II Pro has an impressive collection of both programmable logic and hard IP that has historically been the domain of the ASICs High performance FPGA solution including o Up
120. These are provided on the DN6000K10 using a combination of switching and linear power regulators 10 1 Stand Alone Operation An external ATX power supply is used to supply power to the DN6000K10 refer to Figure 39 The external power supply connects to header P16 Molex type header P N 39 29 9202 The DN6000K10 has the following power supplies 1 25V 1 5V 2 5V 3 3V 5V 12V The 1 5V 2 5V power supplies are generated from the 5V supply on the External ATX power supply while 3 3V comes directly from the ATX power supply DN6000K 10 User Guide www dinigroup com 134 BOARD HARDWARE Figure 39 ATX Power Supply Any ATX type power supply is adequate The Dini Group recommends a power supply rated for 250W Note The switching regulators in the Power Supply may requite and external load to operate within specifications the DN6000K10 may not meet the minimum load requirements The Dini Group recommends attaching an old disk drive to one of the spare connectors 10 1 1 External Power Connector Figure 40 indicates the connections to the external power connector This header is fully polarized to prevent reverse connection and is rated for 1500VAC at 6A per contact J17 43 3V TP5 43 3V 1 11 I pa 3 3V 2 12 3 18 C35 C672 5 4 4 14 PS 100uF 0 tuF al 5 15 16V 6 16 20 1 7 17 45V ELEC gt 12V PWR OK 8 18 35VSB 9 19 45V
121. U51 H20 U45 21 DDR F2 DATAO U51 H10 57 2 DDR F2 DATA1 051 10 57 4 DDR F2 DATA2 U51 F10 057 5 DDR F2 DATA3 U51 G10 U57 7 DDR_F2_DATA4 U51 E10 U57 8 DDR_F2_DATA5 U51 D10 057 10 DDR F2 6 U51 C10 U57 11 DDR_F2_DATA7 U51 C11 U57 13 DDR_F2_DATA8 U51 K14 U57 54 DDR_F2_DATA9 051 114 157 56 DDR F2 DATA10 U51 F14 057 57 DN6000K 10 User Guide www dinigroup com BOARD HARDWARE Signal Name FPGA Pin DDR 2 DATA11 U51 G14 DDR F2 DATA12 U51 D14 DDR F2 DATA13 051 814 DDR F2 DATA14 051115 DDR F2 DATA15 051 15 DDR FPGA F2 ADDO U51 G12 DDR F2 ADD1 U51 F12 DDR F2 ADD2 U51 D12 DDR FPGA F2 ADD3 U51 L13 DDR F2 ADD4 U51 M13 DDR FPGA F2 ADD5 51 13 DDR FPGA 2 ADD6 U51 K13 DDR F2 ADD7 U51 G13 DDR FPGA F2 ADDS U51 H13 DDR F2 ADD9 051 813 DDR FPGA F2 ADD10 051 13 DDR F2 ADD11 U51 D13 DDR FPGA F2 ADD12 U51 C13 DDR F2 ADD13 U51 M15 DDR F2 0008 051 15 DDR F2 1005 U51 F11 DDR F2 UDM U51 H15 DDR F2 LDM U51 H11 DDR FPGA F2 BAO U51 F9 DDR F2 U51 E9 DDR F2 CASN U51 H12 DDR F2 CKE U51 K11 DDR FPGA F2 CSN U51 K12 DDR FPGA F2 RASN 051 12 c cbe b eee me
122. URE generates phase shifted version of the user input clock It is used to recapture data from the DOS clock domain during a memory Read Data recaptured in the rclk domain is then transferred to the system clock domain The phase shift value is specific to the system and must be programmed accordingly When adequate DCM resources ate available third DCM can be used for better timing margins This DCM is used to generate WCLK a phase shifted version of the system clock WCLK is used to clock data at the DDR IOB registers during a Write DN6000K10 User Guide www dinigroup com 87 BOARD HARDWARE DCM1 BUFG CLKO clk IBUFG SSTL2 I user clk gt CLKIN Brien gt dk90 CLK270 1 user_rst CLKDV CLK2X LOCKED ddr clk OBUF SSTL2 ddr clkb DCM CLK OBUF SSTL2 DCM2 RECAPTURE BUFG clkdv 16 I CLKIN CLK90 CLKFB CLK180 CLK270 CLKDV CLK2X LOCKED locked DCM RCLK PHASE SHIFT optional CLKO welk CLKIN CLK90 CLKFB CLK180 CLK270 CLKDV CLK2X LOCKED RST DCM WCLK PHASE SHIFT Figure 27 DDR DCM Implementation 4 5 2 Connections between FPGA s and DDR PLL Clock Buffer The connection between FPGA s and the DDR PLL Clock Drivers consists of SSTL 2 differential pairs A feedback reference clock input is provided from the PLL clock driver to each FPGA The connections for all the FPGA s are shown in Table 13 Table 13
123. an internal pull down 2 DIS ROBOCLOCK Z2 Output Disable Each input controls the state of the respective output bank When HIGH the output bank 15 disabled to the HOLD OFF or HI Z state the disable state is determined by OUTPUT MODE When LOW the 1 4 O A B 0 1 is enabled See Table 27 Datasheet These inputs each have an internal pull down ROBO1_MODE ROBOCLOCK 1 Output Mode This pin determines the clock outputs disable state When this input is HIGH the clock outputs will disable to high impedance HI Z When this input is LOW the clock outputs will disable to HOLD OFF mode When in MID the device will enter factory test mode DN6000K10 User Guide www dinigroup com 83 BOARD HARDWARE Signal Name Desctiption Connector ROBO2 MODE ROBOCLOCK 2 Output Mode This pin JP6 B8 determines the clock outputs disable state When this input is HIGH the clock outputs will disable to high impedance HI Z When this input is LOW the clock outputs will disable to HOLD OFF mode When in MID the device will enter factory test mode 4 3 3 Roboclock Configuration Headers Figure 25 shows JP4 JP6 and JP7 the RoboClock configuration headers RoboClock Configuration Jumpers 3 3V OSCA OSCB ROBO DIS DIS ROBO1 MODE MODE ROBO REFSEL FS
124. and files can be deleted from the card when they are no longer needed If the SmartMedia card requires formatting format the media with the program supplied by the FlashPath SmartMedia floppy adapter software Table 6 FPGA configuration file sizes Pro Bitstream Device Length bits XC2VP70 25 604 096 XC2VP100 33 645 312 DN6000K 10 User Guide www dinigroup com 69 BOARD HARDWARE SmartMedia Cards are available from www computers4sure com 331 SmartMedia Connector Figure 19 shows 2 the SmartMedia connector used to download the configuration files to the FPGA gt ET mm WE we 27 58 WP CARD WP CARD SM RDYBUSYn SmartMedia Figure 19 SmartMedia Connector Note Do not press down on the top of the SmartMedia connector J2 if a SmartMedia card is not installed The metal case shorts 3 3V to GND 3 3 2 SmartMedia connection to Spartan Configuration FPGA MCU Table 7 shows the connection between the SmartMedia connector and the Configuration FPPGA MCU Table 7 Connection between Configuration FRGA MCU Configuration Connector FPGA MCU U13 K21 2 6 U13 K22 jn U13J21 2 8 01320 J29 U1318 j243 U U 1322 72 14 1319 12 15 U13 H19 j246 U13 L20 p2 DN6000K10 User Guide www dinigroup com 70 BOARD HARDWARE Configuration Connector FPGA MCU 013147 J23 013118 j24 SM RDYBUSY
125. ardware Chapter 5 Board Hardware detailed description of board hardware 2 Additional Resources For additional information go to http www dinigroup com The following table lists some of the resources you can access from this website You can also directly access these resources using the provided URLs Resource Description URL User Manual This is the main source of technical information The manual DN6000K10 User Guide www dinigroup com 1 ABOUT THIS MANUAL Resource Description URL should contain most of the answers to your questions Dini Group Web Site Data Book The web page will contain the latest manual application notes FAQ articles and any device errata and manual addenda Please visit and bookmark http www dinigroup com Pages from The Programmable Logic Data Book which contains device specific information on Xilinx device characteristics including readback boundary scan configuration length count and debugging http suppotrt xilinx com pattinfo databook htm E Mail You may direct questions and feedback to the Dini Group using this e mail address support dinigroup com Phone Support Call us at 858 454 3419 during the hours of 8 00am to 5 00pm Pacific Time FAQ The download section of the web page contains a document called DN6000K10 Frequently Asked Questions FAQ This document is periodically updated with information that may not be in t
126. asheet PN MT46V64M106 DDR FPGA 1 ADDO _ 29 2 DDR A1 DQO FPGA ADDT 30 0 DDRTPGA M ADD2 31 5 Li ADDS 32 2 r7 DDR FPCA 4_ 35 003 8 FPGA ADDS 36 4 004 10 DDR FPGA ADD6 37 5 005 11 DDR FPGA ADD7 38 46 096 ADDS 39 7 007 54 DDR FPCA M ADDI __40 8 56 DDR FPGA ADDIO 28 009 DDR FPGA N ADDIT 48 55 DDR FPGA AT ADDT2 42 11 60 DDR DDR FPGA ADDI3 17 12 0012 65 DDR Ai DQ AB 0013 3 DDR FPGA A1 26 0014 65 _ DDR 1 0015 FPGA 27 0015 es 47 DDR A1 DDR ACLKip 45 UDM 55 48 LDM 251 DDR 1 1006 DDR FPGA 1 CKE FPGA 44 Lbas H DDR FPGA 1 23 __ 14 FPGA 5 22 BAS NC 25 DDR FPGA AI WEn 21 E Ws 43 AT WE DDR FPGA Ai 24 CS NC 53 DDR VREF 2 5V Figure 32 DDR SDRAM Connection DN6000K10 User Guide www dinigroup com 104 BOARD HARDWARE 6 2 3 DDR SDRAM Clocking Refer to the DDR Clocking Section 6 2 4 DDR SDRAM Termination DDR SDRAM is based on the 55112 Standard Stub Series Terminated Logic for 2 5V signaling standard The SSTL2 termination mod
127. ces refer to Figure 31 as an example of a FLASH interface shown is the FLASH device FPGA In addition to programming the and storing bitstreams the FLASH may be used for non volatile storage FLASHA ADDRO 25 29 FLASHA FLASHA ADDRT 24 10 000 731 FLASHA DATAT FLASHA ADDR2 23 Al 091 33 FLASHA FASHA ADDR ______ 2 2 e 002 35 FLASHA DATAS FLASHA ADDR4 21 3 FLASHA DATAT FLASHA_ADDR5 20 4 DQ4 40 FLASHA DATAS FLASHA ADDR6 19 5 005 42 FLASHA DATAG 18 T 006 744 FLASHA FASHA ADDR g 7 007 390 FLASHA DATAS FLASHA ADDRS 7 DQ8 32 FLASHA DATAS FLASHA ADDRiO 6 9 009 34 FLASHA DATATO FLASHA ADDRi1 5 10 0010 36 FLASHA DATATI FLASHA ADDRI2 4 11 d 39 FLASHA DATAi2 gj 12 0912 733 ___ _ 5__ FLASHA 2 A13 fa 0013 43 FLASHA FLASHA 414 0014 45 FLASHA 5 FLASHA ADDRi6 48 15 5 moe FLASHA ADDRI7 17 16 FLASHA ADDRi8 16 17 i FLASHA ADDRIS 15 18 m FLASHA_ADDR2O 1021245 id 3 3V FLASHA_ADDR21 9 us 9 13 FLASHA CE m 3 3V FLASHA OER m E vec 27 2 5V FLASHA 1t we 9 FPGA DONE S 27 HAWER 80 WP GND 28F640B3 TSOP48 Figure 31 FLASH Connect
128. commended for the user also Consequently edif files are used in the design flow described here Selecting the edif file in the Module View window the user s Project Navigator box should resemble Figure 8 DN6000K 10 User Guide www dinigroup com 49 PROGRAMMING CONFIGURING THE HARDWARE 16 DN5000106 npl Window meme aaao Creete New Source Design Entry User Constraints Implement Design Generate Programming File Figure 8 Project Navigator In the Process for Source window a process is signified by the icon In the Process for Source window the user must right click on the Generate Programming File process and select properties The default settings are correct The user should verify a couple important options right click and selecting properties options Configuration Options Tab Configuration Pin Powerdown Pull Up DN6000K 10 User Guide www dinigroup com 50 PROGRAMMING CONFIGURING THE HARDWARE Process Properties EU a Default 4 Default 5 Default 5 Default NoWait Default NoWait Readback Options Tab Security Enable Readback and Reconfiguration Www w dinigroup com 51 DN6000K 10 User Guide PROGRAMMING CONFIGURING THE HARDWARE Process Properties x General Options Configuration Options Startup Options Readback Options Encryption Options
129. d FPGA_MSEL1 Pins 2 amp 7 Open FPGA_MSEL2 Pins 3 amp 6 Open DIP_SW3 Pins 4 amp 5 X Set up the serial port connection as desctibed above in Configuring HyperTerminal Next place the SmartMedia card in the SmartMedia socket on the DN6000K10 and turn on the power NOTE the catd can only go in one way The SmartMedia catd is hot swappable and can be taken out or put into the socket even when the power is on Once the power has been turned on the configuration process will begin as long as there is a valid SmartMedia card inserted properly in the socket SmartMedia is determined to be invalid if either the format of the card does not follow the SSFDC specifications or if it does not contain a file named main txt in the root directory If the configuration was successful a message stating so will appear and the Main Menu will come up Otherwise an error message will appear The LED s on 051 and 052 give feedback during and after the configuration process see Table 23 for GPIO LED s for further details After the FPGA has been configured the following Main Menu will appear via the serial port refer to Figure 9 DN6000K10 User Guide www dinigroup com 55 PROGRAMMING CONFIGURING THE HARDWARE List files on Smart Set FPGA Address DOD M b c d e f ENTER SELECTION Turn FRNS on Configure FPGAs in SelectMAP mode Interactive configu
130. de www dinigroup com 21 INTRODUCTION VIRTEX II PRO AAND 15 Monolithic clock synthesis and clock recovery CDR Fibre Channel Gigabit Ethernet 10 Gb Attachment Unit Interface and Infiniband compliant transceivers 8 16 or 32 bit selectable internal FPGA interface 10B encoder and decoder e 50 75 on chip selectable transmit and receive terminations e Programmable comma detection e Channel bonding support two to sixteen channels Rate matching via insertion deletion characters e Four levels of selectable pre emphasis e Five levels of output differential voltage Per channel internal loopback modes 2 5 transceiver supply voltage 2 4 Virtex ll FPGA Fabric Description of the Virtex II Family fabric follows SeleccRAM memory hierarchy o Up to 10 Mb of True Dual Port RAM in 18 Kb block resources Upto 1 7 Mb of distributed SelectRAM resources o High performance interfaces to external memory e Arithmetic functions Dedicated 18 bit x 18 bit multiplier blocks Fast look ahead carry logic chains e Flexible logic resources Up to 111 232 internal registers latches with Clock Enable o Up to 111 232 look up tables LUTs or cascadable variable 1 to 16 bits shift registers Wide multiplexers and wide input function support o Horizontal cascade chain and Sum of Products support DN6000K10 User Guide www dinigroup com 22 INTRODUCTION
131. e flexibility The user can bring a single 3 3V TTL input It can be attached to either input However the other input must be left open The user can provide a differential clock input to the pair to the RoboClocks DN6000K10 User Guide www dinigroup com 85 BOARD HARDWARE 441 External SMA Clock 1 ate SMA connectors to allow an external differential clock USER CLKp n input to all the FPGA s via a PLL clock driver U1 Resistors R100 R116 allows for AC coupling if required Refer Figure 26 J4 R116 5 RCLK USER USER CLK IG ESL 3 4 0 CONN SMB J1 R100 RCLK_USERp USER_CLKn 4 CONN SMB Figure 26 External SMA Clock 4 4 2 Connections between FPGA s and External SMA Clock Buffer The connection between the FPGA s and the external SMA clock buffer are shown in Table 12 Table 12 Connection between FPGA and External PPC Oscillator Signal Name FPGA Pin External SMA Clock Buffer SER_ACLKp U27 K21 11 3 SER ACLKn U27J21 U1 2 SER_BCLKp U28 K21 01 5 SER BCLKn 028 721 01 6 SER CCLKp U29 AT21 U1 10 SER U29 AU21 U1 9 SER_DCLKp U53 AU22 1 20 SER_DCLKn U53 AT22 1 19 SER_ECLKp U52 K21 1 22 SER ECLKn U52J21 1 23 SER FCLKp 051 722 1 46 SER FCLKn 151 822 1 47 SER GCLKp 080 722 144 SER GCLKn U80 K22 1 43 SER HCLKp U78 K21 1 39 SER HCLKn U78J21 1 40 SER_ICLKp U79 AU22 1 29 a
132. ect P9 107 GND J1 108 ECLK1 J5 7 P9 108 GND 11 109 No Connect P9 109 GND 1 110 No Connect P9 110 GND 11111 P2N5 J5 15 P9111 TST HDRA79 U28 AH42 J1 112 P2N4 J5 17 P9 112 TST_HDRA80 U28 AG41 J1 113 P2NX11 2 2 9 113 TST HDRAS1 U28 AF42 11 114 P2NX10 2 1 9 114 TST HDRAS82 U28 AE42 11 115 P2NX9 J5 19 P9 115 TST HDRAS3 U28 AD42 J1 116 P2NX8 5 21 9 116 TST 4 U28 AC32 J1 117 P2NX3 5 23 9 117 TST HDRAS85 U28 AC34 1 118 No Connect P9 118 GND J1 119 P2NX2 15 25 9 119 TST HDRAS6 U28 AC39 J1 120 P3NX11 J2 29 P9 120 TST_HDRA87 U28 AB31 T1321 P3NX10 12 30 9 121 TST 8 U28 AB34 1 22 P3NX7 12 31 9 122 TST_HDRA89 U28 AB37 11123 P3NX6 2 32 9 123 TST HDRA90 U28 AB39 1 124 P3NX3 5 27 9 124 TST_HDRA91 U27 AWA1 1 125 P3NX2 J5 29 9 125 TST_HDRA92 U27 AV41 J1 126 P3NX1 15 31 9 126 TST HDRA93 U27 AU41 DN6000K 10 User Guide www dinigroup com 149 BOARD HARDWARE Daughter Card Connections DN6000K10 IO Connections Test Header A Test Signal Name Connector Test Signal Name FPGA Pin Header Header J1 127 J5 33 P9 127 TST_HDRA94 U27 AT41 J1 128 P3N85 J5 35 9 128 TST HDRA95 U27 AR41 1 129 No Connect P9 129 GND 11 130 P3N84 J5 37 P9 130 TST_HDRA96 U27 AN41 J1 131 P3N81 J5 39 P9 131 TST_HDRA97 U27 AM41 J1 132 P3N80 15
133. ect files and UCF files to compile for VP70 DN6000K 10 User Guide ww w dinigroup com 34 INTRODUCTION THE SOFTWARE TOOLS make VP100 makes changes to synplicity and EDK project files and UCF files to compile for VP100 make INCLUDE DDR2 makes changes to synplicity projects EDK source code and UCF files to include DDR2 make EXCLUDE DDR2 makes changes to synplicity projects EDK source code and UCF files to exclude DDR2 make 32 makes changes to synplicity projects and EDK source code to set DDR size make 64 makes changes to synplicity projects and EDK source code to set DDR size make DDR 128 MEG makes changes to synplicity projects and EDK source code to set DDR size II UCF FILES In soutce ucf ate 9 files one for each FPGA The files must be modified to exclude any unused memory device DDR1 DDR2 or FLASH If any DDR or FLASH chip is to be excluded simply comment out all associated lines in the UCF file by putting a in front of the line If DDR2 is to be excluded it should always be excluded for the VP70 then the build utility may be used as shown below Use make VP70 or make VP100 to include exclude bus interconnect lines that ate appropriate to that device Please note that the bus numbering in the files under source ucf does not match the schematic We have included a set of UCF files that do match the schematic under t
134. ectory intact clean_all Deletes all generated files accept those from the EDK clean ppc Deletes all EDK netlist files ppc netlist Rebuilds the EDK netlist The netlist MUST previously have been build from the EDK user interface before it can be built from the command line make VP70 makes changes to synplicity and EDK project files and UCF files to compile for VP70 make VP100 makes changes to synplicity and EDK project files and UCF files to compile for VP100 DN6000K10 User Guide www dinigroup com 32 INTRODUCTION THE SOFTWARE TOOLS make INCLUDE DDR2 makes changes to synplicity projects EDK source code and UCF files to include DDR2 make EXCLUDE DDR2 makes changes to synplicity projects EDK source code and UCF files to exclude DDR2 make 32 makes changes to synplicity projects and EDK source code to set DDR size make DDR_64_MEG makes changes to synplicity projects and EDK source code to set DDR size make DDR_128_MEG makes changes to synplicity projects and EDK soutce code to set DDR size The reference design must support any number of FPGA s in both VP70 and VP100 sizes Compiler constants ate used to include exclude code as well as to set appropriate parameters for the configuration being compiled for Specifically the user may want to include exclude any memory device DDR1 DDR2 FLASH or may want to switch between the VP70 and VP100 part There are four
135. egisters 0x3 test FLASH 0x4 test DDR s 0 5 test FPGA interconnect To issue a command the MCU must write one of the above values to this register The MCU can then poll this register to check if the test is done register will return all zeros when finished Status Register 0 5 00 0008 0 3 00 0008 Read only register Status of commands and bus control Bits 16 18 must all be zero for MCU to issue any commands to External Host Command Register Status results can be read after command register is cleared decode for test results is as follows Bit 0 overall pass fail pass 1 fail 0 Bit 1 register test pass fail Bit 2 flash test pass fail Bit 3 ddr test pass fail Bit 4 interconnect test pass fail 0 5 00 0018 0 3 00 0018 Contains information on what are stuffed on the egister DN6000k10 as well as what type of FPGAs they are The register has the following format Bit 0 1 if FPGA A is stuffed 0 otherwise Bit 1 1 if FPGA B is stuffed 0 otherwise Bit 2 1 if FPGA C is stuffed 0 otherwise Bit 2 1 if FPGA D is stuffed 0 otherwise Bit 2 1 if FPGA E is stuffed 0 otherwise Bit 2 1 if FPGA F is stuffed 0 otherwise Bit 2 1 if FPGA G is stuffed 0 otherwise Bit 7 1 if FPGA H is stuffed 0 otherwise Bit 8 1 if FPGA I is stuffed 0 otherwise Bit 9 1 if FPGA is 2vp100 0 if 2vp70 Bit 10
136. el used for DDR SDRAM has two types of termination e Class 1 Also called 55112 I Used for unidirectional signaling Control signals e Class 2 Also called SSTL2_II O Used for bi directional signaling Data signals Both Class 1 and Class 2 are based on a 50Q controlled impedance environment and termination to VTT a 1 25V power supply SSTL2 Class 1 termination is used for unidirectional signaling such as control signals It is based on a 500 controlled impedance driver a 500 controlled impedance transmission line and 500 parallel termination to VTT at the receiver Figure 33 shows a basic SSTL2 Class 1 circuit The driver is brought to 500 by the addition of a 25 series resistor immediately adjacent to the driver implemented using DCI thus no need for an external component 0 6 X Figure 33 SSTL2 Class 1 Termination SSTL2 Class 2 termination is used for bi directional signaling such as data signals It is based on a 500 controlled impedance driver and 50 2 parallel termination to for the receiver at both ends connected through a 50 controlled impedance DN6000K 10 User Guide www dinigroup com 105 BOARD HARDWARE transmission line Figure 34 shows a basic SSTL2 Class 2 circuit The driver is brought to 500 by the addition of a 25 series resistor immediately adjacent to the driver DDQ Figure 34 SSTL2 Class 2 Termination Note DCI termination must be im
137. er 1 179 P4N23 7 5 9 179 TST_HDRA141 U27 N33 J1 180 P4N22 Jr P9 180 TST_HDRA142 U27 N35 1 181 P4N17 17 9 9 181 IST HDRA143 027 341 1 182 P4N16 7 11 P9 182 TST HDRA144 027 31 J1 183 P4N15 17 13 9 183 TST HDRA145 U27 M33 1 184 GND 12 36 9 184 GND 1 185 P4N14 J7 15 P9 185 TST_HDRA146 U27 M36 J1 186 P4N9 17 17 P9 186 TST HDRA147 U27 L33 1 187 P4N8 J7 19 9 187 TST_HDRA148 U27 L35 J1 188 P4N5 17 21 P9 188 TST HDRA149 027 141 1 189 17 23 P9 189 TST HDRA150 U27 142 1 190 P4N1 17 25 9 190 HDRA151 U27 K35 112191 17 27 P9 191 TST 152 U27 K41 11 192 13 J7 29 9 192 151 HDRAI155 027 735 14 193 P4NX12 17 31 9 193 5 154 27 41 11 194 P4NX9 J7 33 P9 194 TST HDRA155 U27J 42 11 195 No Connect P9 195 GND 11 196 P4NX8 J7 35 P9 196 TST_HDRA156 U27 H36 11 197 P4NX3 1727 P9 197 IST 157 027 641 1 198 P4NX2 J7 39 P9 198 TST_HDRA158 U27 F41 11 199 P4NX1 J7 41 9 199 HDRA159 U27 E41 11 200 17 43 9 200 TST_HDRA160 027 041 DN6000K10 User Guide Www dinigroup com 152 BOARD HARDWARE Daughter Card Connections DN6000K10 IO Connections Test Header B Test Signal Name Connector Test Signal Name FPGA Pin Header Header J1 001 No Connect P10 1 12V J1 002 No Connect P10 2 GND J1 003 ACLK1 5
138. erwise Bit 8 1 if FPGA I is stuffed 0 otherwise Bit 9 1 if FPGA is 2vp100 0 if 2vp70 Bit 10 1 if FPGA is 2vp100 0 if 2vp70 Bit 11 1 if FPGA C is 2vp100 0 if 2vp70 Bit 12 1 if FPGA D is 2vp100 0 if 2vp70 Bit 13 1 if FPGA E is 2vp100 0 if 2vp70 Bit 14 1 if FPGA F is 2vp100 0 if 2vp70 Bit 15 1 if FPGA is 2vp100 0 if 2vp70 Bit 16 1 if FPGA H is 2vp100 0 if 2vp70 Bit 17 1 if FPGA Iis 2vp100 0 if Zvp70 175 Start End Address Read Description Address Write FLASH U16 0 1800 0000 OXISFF FFFF Address maps directly to FLASH External Host 0 1 00 0004 0004 R W Write Read register for MCU to issue the following commands Register Ox1 test all functionality 0 2 test registers 0 3 test FLASH 0 5 test FPGA interconnect issue a command the MCU must wtite one of the above values to this register The MCU can then poll this register to check if the test 15 done register will return all zeros when finished Status Register 0x1C00 0008 0 1 00 0008 R Read only register Status of commands and bus control Bits 16 18 must all be zero for MCU to issue any commands to External Host Command Register Status results can be read after command register is cleared decode for the test results is as follows Bit 0 overall pass fail pass 1 fail 0 Bit 1 register test
139. fed 0 otherwise Bit 2 1 if FPGA C is stuffed 0 otherwise Bit 2 1 if FPGA D is stuffed 0 otherwise Bit 2 1 if FPGA E is stuffed 0 otherwise Bit 2 1 if FPGA F is stuffed 0 otherwise Bit 2 1 if FPGA G is stuffed 0 otherwise Bit 7 1 if FPGA is stuffed 0 otherwise Bit 8 1 if FPGA I is stuffed 0 otherwise Bit 9 1 if FPGA is 2vp100 0 if 2vp70 Bit 10 1 if FPGA is 2vp100 0 if 2vp70 Bit 11 1 if FPGA C is 2vp100 0 if 2vp70 Bit 12 1 if FPGA D is 2vp100 0 if 2vp70 Bit 13 1 if FPGA E is 2vp100 0 if 2vp70 Bit 14 1 if FPGA F is 2vp100 0 if 2vp70 Bit 15 1 if FPGA is 2vp100 0 if 2vp70 Bit 16 1 if FPGA H is 2vp100 0 if 2vp70 Bit 17 1 if FPGA Iis 2vp100 0 if Zvp70 177 FPGAD Start End Address Read Description Address Write DDR 1 U46 0 5000 0000 0x30FF_FFFF Address maps directly to DDR 1 DDR 2 U58 0x3100 0000 Ox31FF_FFFF Address maps directly to DDR 2 058 only avail if 2vp100 FLASH 015 0 5800 0000 0x38FF_FFFF Address maps directly to FLASH FIXME DDR Phase Shift 0 3 00 0000 0x3CO0 0000 R W DDR phase shift value upper WORD is read only and contains Register the current phase shift value lower WORD is write only External Host 0x3C00_0004 0x3C00_0004 R W Write Read register for MCU to issue the following commands Commands Register 0x1 test all functionality 0x2 test r
140. format Bit 0 1 if FPGA is stuffed 0 otherwise Bit 1 1 if FPGA B is stuffed 0 otherwise Bit 2 1 if FPGA is stuffed 0 otherwise Bit 2 1 if FPGA D is stuffed 0 otherwise Bit 2 1 if FPGA E 15 stuffed 0 otherwise Bit 2 1 if FPGA F is stuffed 0 otherwise Bit 2 1 if FPGA G is stuffed 0 otherwise Bit 7 1 if FPGA is stuffed 0 otherwise Bit 8 1 if FPGA I is stuffed 0 otherwise Bit 9 1 if FPGA is 2vp100 0 if 2vp70 Bit 10 1 if FPGA is 2vp100 0 if 2vp70 Bit 11 1 if FPGA C is 2vp100 0 if 2vp70 Bit 12 1 if FPGA D is 2vp100 0 if 2vp70 Bit 13 1 if FPGA E is 2vp100 0 if 2vp70 Bit 14 1 if FPGA F is 2vp100 0 if 2vp70 Bit 15 1 if FPGA is 2vp100 0 if 2vp70 Bit 16 1 if FPGA H is 2vp100 0 if 2vp70 Bit 17 1 if 115 2vp100 0 if 2vp70 179 Existing Register 0 5 00 0018 0 5 00 0018 R W Start End Address Read Description Address Write DDR 1 U45 0 5000 0000 0 50 _ R W Address maps directly to DDR 1 DDR 2 U57 0x5100 0000 Ox51FF_FFFF Address maps directly to DDR 2 057 only avail if 2vp100 DDR Phase Shift 0 5 00 0000 Ox5COO 0000 R W DDR phase shift value upper WORD is read only and contains Register the current phase shift value lower WORD is write only External Host 0x5C00_0004 0x5C00_0004 R W Write Read re
141. g Started and the section Configuring HyperTerminal in Chapter 5 Programming Configuring the Hardware It is assumed at this point that a terminal emulator is connected to PPC Header running at 19200 bps Powering up the board will display the following text on the terminal Cc ck KK KKK KK KK ko ko DN6000K10 ASIC DEVELOPMENT PLATFORM REFERENCE DESIGN SOFTWARE CC CS A ko ko x _ Waiting for External Host Commands Press Any Key To Enter Local User Menu The vatious functions of the Reference Design may be controlled both from the MCU menu desctibed in the section Description of Main Menu Options in Chapter 5 from the PowerPC menu In this example we will be using the PowerPC menu to exercise the functions of the Reference Design When presented with the above text the Reference Design is waiting for commands to be sent from the MCU Press any key to stop waiting for MCU commands and get the following menu DN6000K 10 User Guide ww w dinigroup com 29 INTRODUCTION
142. ge Source PWR OK 25 3 3V 5V 12V 12V 10 1 4 Front Panel Indicator Switch In order to power the board from the ATX Power Supply 5 ONn needs to be pulled to GND There is also a LED signal to indicate the power has been turned on refer to Figure 42 DN6000K10 User Guide Www dinigroup com 136 BOARD HARDWARE 5VSB 5VSB R674 10K PS_ONn PWR ON LEDA 8672 ANA 553 5 22 28 4050 lt oc soma Figure 42 Front Panel Indicator Switch llTest Header Daughter Card Connections 11 1 Test Header The DN6000K10 offers three 200 pin test headers P9 P10 P11 that allow the user connection to discrete FPGA pins refer to Figure 43 Test Header A is shown Note Use of a Duaghter card requires the FPGA fan to be removed leaving the heatsink in place DN6000K10 User Guide Www dinigroup com 137 BOARD HARDWARE P9 412V 1 101 E CIR e e 188 lt CLKIN 5V 41 104 GND 2 5V 5 7105 3 35V 6 106 ACLK9 Tt E107 GND __ 3 3V 109 GND BCLK9 10 m10 GND GND 79
143. gister for MCU to issue the following commands Ox1 test all functionality 0 2 test registers 0 4 test DDR s 0 5 test FPGA interconnect To issue a command MCU must write one of the above values to this register The MCU can then poll this register to check if the test 15 done register will return all zeros when finished Status Register 0 5 0008 0 5 00 0008 R Read only register Status of commands and bus control Bits 16 18 must all be zero for MCU to issue any commands to External Host Command Register Status results can be read after command register is cleared decode for the test results is as follows Bit 0 overall pass fail pass 1 fail 0 Bit 1 register test pass fail Bit 3 ddr test pass fail Bit 4 interconnect test pass fail Contains information on what FPGAs are stuffed on the DN6000k10 as well as what type of FPGAs they are The register has the following format Bit 0 1 if FPGA A is stuffed 0 otherwise Bit 1 1 if FPGA B is stuffed 0 otherwise Bit 2 1 if FPGA C is stuffed 0 otherwise Bit 2 1 if FPGA D is stuffed 0 otherwise Bit 2 1 if FPGA E is stuffed 0 otherwise Bit 2 1 if FPGA F is stuffed 0 otherwise Bit 2 1 if FPGA G is stuffed 0 otherwise Bit 7 1 if FPGA H is stuffed 0 otherwise Bit 8 1 if FPGA I is stuffed 0 otherwise Bit 9 1 if FPGA is 2vp100 0 if 2vp70 Bit 10 1 if FPGA is 2vp100
144. guration i e VP70 vs VP100 DDR2 stuffed ot not stuffed etc and to invoke all of the above tools from the command line Instructions for invoking the batch file can be found by viewing the batch file with a text editor Additional information about using the batch file to build the reference design is found below Taking the reference design through all of the vatious tools for several FPGA s can be very tedious and time consuming this batch file can do it all in one command The command line utility Make bat is an MS DOS batch file compatible with Windows 2000 and later operating systems Make bat should be run from the command line with command line parameters It should not be double clicked from the windows environment A command prompt shortcut is provided in the same directory as Make bat and can be double clicked to open a command prompt window with the proper working directory Four main steps are involved in building the reference design First the PowerPC netlist must be built using the EDK The first time this is done it must be done from the EDK GUI not from the command line Open the EDK project in PPC system xmp and select Tools gt make netlist Once this has been done once the Make bat script can be used to build the netlist with the command Make ppc_netlist The second step is to synthesize the design with Synplicity s Synplify Pro The third DN6000K10 User Guide www dinigroup com 31 INTRODUCTION THE SOF
145. h push button ease e Incremental Design DN6000K10 User Guide www dinigroup com 25 INTRODUCTION VIRTEX II AAND 15 e Macro Builder 3 1 4 Board Level Integration Xilinx understands the critical issues such as complex board layout signal integrity high speed bus interface high performance I O bandwidth and electromagnetic interference for system level designers To ease the system level designers challenge ISE provides support to all Xilinx leading FPGA technologies e System IO XCITE e Digital clock management for system timing control management for electromagnetic interference To really help you ensure your programmable logic design works in context of your entire system Xilinx provides complete pin configurations packaging information tips on signal integration and various simulation models for your board level verification including e IBIS models HSPICE models e STAMP models 4 Virtex4l Pro Developer s Kit V2PDK is the Virtex II Pro Developer s Kit and is included to provide an existing framework of hardware and software code to explore the capabilities of the Pro as well as a basis to build new systems wide variety of software and hardware tools used to build a ProTM design V2PDK The design flow is a tool chain methodology that exists to simplify the entire design process by providing integration between the tools and automating task
146. have the ability to proactively meet the design timing requirements by driving the placement in the physical device In addition cross probing between the physical design report and the HDL design code will further enhance the turnaround time Xilinx ISE provides the seamless integration with the leading synthesis engines from Mentor Graphics Synopsys and Synplicity You can use the synthesis engine of your choice In addition ISE includes Xilinx proptietary synthesis technology XST You have options to use multiple synthesis engines to obtain the best optimized result of your programmable logic design 3 1 3 Implementation and Configuration Programmable logic design implementation assigns the logic created during design entry and synthesis into specific physical resources of the target device The term place and route has historically been used to describe the implementation process for FPGA devices and fitting has been used for CPLDs Implementation is followed by device configuration where a bitstream is generated from the physical place and route information and downloaded into the target programmable logic device To ensure designers get their product to market quickly Xilinx ISE software provides several key technologies required for design implementation e Ultra fast runtimes enable multiple turns per day ProActive Timing Closure drives high performance results Timing driven place and route combined wit
147. he directory soutce ucf busnum 1toN The files under that directory however will not work with the reference design You may use them for your own design if you wish The difference between the two versions is that the standard UCF files source ucf have busses with numbering starting from 0 while the UCF files matching the schematic source ucf busnum 1toN have busses with numbering starting at 1 make INCLUDE_DDR2 makes changes to synplicity projects EDK source code and UCF files to include DDR2 DN6000K10 User Guide www dinigroup com 35 INTRODUCTION THE SOFTWARE TOOLS make EXCLUDE DDR2 makes changes to synplicity projects EDK source code and UCF files to exclude DDR2 make VP70 comments out bus interconnect lines that Connect in the VP70 make VP100 uncomments bus interconnect lines that are Connect in the VP70 but exist in VP100 If excluding FLASH or DDR1 all changes must be made by hand be sure to also make changes to the synplicity project file and the PPC source file PPC code fpga patrams h III XILINX EDK PROJECT FILE The Xilinx EDK Project file is found at PPC system xmp After making any changes to this file be sure to select the clean all option in the Xilinx EDK so that all generated files will be remade with the new project settings The only setting that should be changed in this file is the target device This can be changed thro
148. he PowerPCTM 405 CPU core includes dedicated debug resources that support a vatiety of debug modes for debugging duting hardware and software development These debug resources include e Internal debug mode for use by ROM monitors and software debuggers e External debug mode for use JTAG debuggers Debug wait mode which allows the servicing of interrupts while the processor appears to be stopped Real time trace mode which supports event triggering for real time tracing Debug modes and events are controlled using debug registers in the processor The debug registers are accessed either through software running on the processor or through the JTAG port The debug modes events controls and interfaces provide a powerful combination of debug resources for hardware and software development tools The port interface supports the attachment of external debug tools such as the ChipScope Integrated Logic Analyzer a powerful tool providing logic analyzer capabilities for signals inside FPGA without the need for expensive external DN6000K 10 User Guide www dinigroup com 127 BOARD HARDWARE instrumentation Using the JTAG test access port a debug tool can single step the processor and examine the internal processor state to facilitate software debugging This capability complies with the IEEE 1149 1 specification for vendor specific extensions and is therefore compatible with standard JTAG hardware for boundar
149. he User s Manual 3 Conventions This document uses the following conventions An example illustrates each convention 3 1 Typographical The following typographical conventions are used in this document Convention Meaning or Use Example Courier font Messages prompts and Speed grade program files that the system 100 displays Courier bold Literal commands that you ngdbuild enter in a syntactical statement design name Garamond bold DN6000K 10 User Guide Commands that you select File gt Open from a menu Keyboatd shortcuts Ctrl C www dinigroup com 2 ABOUT THIS MANUAL Convention Meaning or Use Example Variables in a syntax statement ngdbuild fot which you must supply values References to other manuals See the Development System Reference Guide for more information Italic font ar 7 Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected An optional entry or ngdbuild opton_name parameter However in bus design name specifications such as bus 7 0 they are required Braces A list of items from which you lowpwr off must choose one ot more Vertical bar Separates items in a list of lowpwr on off choices Vertical ellipsis Repetitive material that has 1 Name IOB 2 Name CLKIN Horizontal ellipsis
150. he installed jumpers on the DN6000K10 Description JP5 A4 A3 PLL2BNC JP5 A5 B5 CLOCKB CFPGA_CLKOUT connected to RoboClock 2 057 CFPGA CLKOUT is an output clock from the Configuration FPGA This connection causes 48MHz to output on all BCLK signals which is used in the reference design for communication between Configuration FPGA and Pro FPGAs Oscillator 8 33 33MHz connected to RoboClock 1 056 JP4 A1 C1 ROBO1_REFSEL ROBOCLOCK 1 Reference Select Input The REFSEL input controls how the reference input DN6000K10 User Guide www dinigroup com 8 GETTING STARTED Jumper Installed Signal Name Desctiption is configured When LOW it will use the REFA pair PLL1A as the reference input When HIGH it wil use the REFB pair PLL1BC PLL1BNO as the reference input This input has an internal pull down JP4 A2 C2 FS ROBOCLOCK 1 Frequency Select This input must be set according to the nominal frequency fNOM Refer to Table 1 in the datasheet JP4 A4 B4 ROBO FBDSO ROBOCLOCK 1 Feedback Divider Function Select These inputs determine the function of the QFAO and QFA1 outputs Refer to Table 4 in the datasheet JP4 A9 B9 ROBO 050 ROBOCLOCK 1 Output Divider Function Select Controls the divider function of all banks ACLKx of outputs Refer to Table 4 in the datasheet JP4 A10 B10 ROBO1_DS1 ROBOCLOCK
151. igator software package Go to the File menu and select New Project A New Project dialog box will pop up shown in Figure 7 DN6000K10 User Guide www dinigroup com 47 PROGRAMMING CONFIGURING THE HARDWARE New Project E Enter a Name and Location for the Project Project Name Project Location 10 50001 06 r Selectthe type of Top Level module for the Project Top Level Module Type EDIF Y Cancel Figure 5 New Project Screen Shot Select the input files for the project refer to Figure 6 Selectthe Input File for the Project Input Design rce fpgacode FPGA_SYNTH rev_1 50001 06 edf Copy Input Design to the Project directory Select the Constraint File for the Project Constraint File Budice Jack DiniGroup 50001 06 Source fpgacc Copy Constraint file to the Project directory lt Back Next gt Figure 6 Input File Select the device and the design flow for the project user must specify a project name and location The correct property values must be selected refer to Figure 7 DN6000K 10 User Guide ww w dinigroup com 48 PROGRAMMING CONFIGURING THE HARDWARE Figure 7 New Project Dialog Box The Project Navigator will create a new project with the required files The DINI Group prefers to use Synplicitys Synplify for synthesis which is re
152. iguration process However a user can put several files that follow the format for main txt on the SmartMedia card that contain different options for the configuration process By selecting the main menu option 4 the user can select a file from a list of files that can be used in place of main txt If the power is turned off or the reset button S1 is pressed the configuration file is changed back to the default main txt www dinigroup com 56 PROGRAMMING CONFIG URING THE HARDWARE Function Description List files on This option prints out a list of all the files found on the SmartMedia SmartMedia card Display Contents of a TXT File This option allows the user to list the contents of any text file on the Smart Media card Change RS232 PPC Ports This options allows the user to select what FPGA PPCs should be connected to which PPC PORTS P3 P4 P6 amp P7 This option will also print out the current port settings allowing you to quit without changing them The next 7 options are only available if the FPGAs ate configured with The Dini Group reference design Please see Appendix A for FPGA Address Maps Set FPGA Address Set the fpga address for the next read write to the fpga Write to FPGA at current address a Read from FPGA at current address Performs a DWORD write to the current fpga address You will see the current address at the top of the Main Menu and also the wri
153. ion The Intel Advanced Boot Block Flash Memory C3 device supports read array mode operations at various IO voltages 1 8V and 3V and erase and program operations at 3V or 12V VPP On the DN6000K10C VPP is 3 3V The DN6000K10C interfaces to the FLASH at 2 5V levels DN6000K10 User Guide www dinigroup com 95 BOARD HARDWARE This family of devices is capable of fast programming at 12V not utilized on the DN6000K10C The C3 device features the following e Enhanced blocking for easy segmentation of code and data or additional design flexibility e Program Suspend to Read command e VCCQ input of 1 65V 2 5V or 2 7V 3 6V on all I Os e Maximum program and erase time specification for improved data storage For more information on this part please refer to the Intel P N TE28F640C3TC80 datasheet 6 1 1 FLASH Connection to the FPGA s The FLASH memory components are connected as listed in Table 17 The VCCO of the IO banks are connected to 2 5V Table 17 Connection between FPGA and FLASH Signal Name FPGA Pin FLASHA_ADDRO U27 P40 FLASHA_ADDR1 U27 N38 FLASHA_ADDR2 U27 N39 FLASHA_ADDR3 U27 N40 FLASHA_ADDR4 U27 M38 PLASHA_ADDR5 U27 M39 FLASHA_ADDR6 U27 M40 FLASHA_ADDR7 U27 L38 FLASHA_ADDR8 U27 H40 FLASHA_ADDR9 U27 G38 FLASHA_ADDR10 027 639 FLASHA_ADDR11 U27 G40 FLASHA_ADDR12 27529 FLASHA ADDR13 U27 F40 FLASHA ADDR14 U27 E40 DN6
154. ion Address Write External Host 0 7 00 0004 0x7CO0 0004 Write Read register for MCU to issue the following commands Commands Register Ox1 test all functionality 0 2 test registers 0 5 test FPGA interconnect To issue a command the MCU must wtite one of the above values to this register The MCU can then poll this register to check if the test 15 done register will return all zeros when finished Status Register 0 7 00 0008 0 7 00 0008 Read only register Status of commands and bus control Bits 16 18 must all be zero for MCU to issue any commands to External Host Command Register Status results can be read after command register is cleared decode for the test results is as follows Bit 0 overall pass fail pass 1 fail 0 Bit 1 register test pass fail Bit 4 interconnect test pass fail Existing FPGA 0 7 00 0018 Ox7COO 0018 R W Contains information what FPGAs are stuffed on the DN6000k10 as well as what type of FPGAs they are The register has the following format Bit 0 1 if FPGA A is stuffed 0 otherwise Bit 1 1 if FPGA B is stuffed 0 otherwise Bit 2 1 if FPGA C is stuffed 0 otherwise Bit 2 1 if FPGA D 55 stuffed 0 otherwise Bit 2 1 if FPGA E is stuffed 0 otherwise Bit 2 1 if FPGA F is stuffed 0 otherwise Bit 2 1 if FPGA G is stuffed 0 otherwise Bit 7 1 if FPGA H is stuffed 0 otherwise Bit 8 1 if FPGA I is s
155. is used directly for the state machines in the Configuration FPGA for controlling the interface to the SmartMedia card The maximum frequency for SelectMap configuration is 50 MHz without wait states DN6000K 10 User Guide www dinigroup com 68 BOARD HARDWARE Serial and JTAG configuration of the Virtex II Pro FPGA s are back off positions only The 48 MHz clock can be divided down in the Configuration FPGA and used as a clock source to the PWB clock network CFPGA The signals 40 connects to the MB bus that links all the FPGA s CFPGA_MSEL 0 2 selects the configuration mode of the Configuration FPGA refer to Table 5 using dipswitch S4 Table 5 FPGA Configuration Modes Configuration Mode CLK Direction Master Serial Out Slave Serial In Master Select MAP Slave SelectMAP Boundary Scan Note Grayed options not supported by this design 3 3 SmartMedia The configuration bit file for the FPGA is copied to a SmartMedia card using the SmartDisk FlashPath Floppy Disk Adapter The approximate file size for each possible FPGA option is shown below in Table 6 Note that several BIT files can be put on a 32MB card The DN6000K10 is shipped with two 32 megabyte 3 3V SmartMedia cards The DN6000K10 support card densities up to 128MB Note Do NOT format the SmartMedia card using the default Windows file format program Smart Media cards come pre formatted from the factory
156. k10 All USBController source code is included on the CD ROM shipped with the DN6000k10 USBController can be installed on Windows 98 ME 2000 XP There is a command line version called USB that can be installed on Linux and Solaris Detailed installation instructions for each version may be found in README on the CD There ate 2 versions of the USBController USBControllerUpdate exe Allows user to update the Flash USBController exe Does not allow the user to update the MCU Flash The USBController Application contains the following functionality DN6000K 10 User Guide Configure FPGA s over USB Verify Configuration Status Configure FPGAs via Smartmedia card Clear FPGA s Reset FPGA s Set CLK Frequency www dinigroup com 14 INTRODUCTION VIRTEX II AAND 15 o Tum FPGA Fan s Off On o Retrieve MCU Spartan version The following features are available when The Dini Group Reference design bit files are loaded o Read Write to FPGA s see Appendix for address maps o Test DDRs FLASH Reigstets Interconnect 1 1 1 Getting Started with USBController Once USBController is installed and the DN6000k10 is powered on and the USB cable is plugged in the user can open USBController USBController application should immediately find the DN6000k10 If USBController does not find the DN6000k10 the user will get the following alert see
157. les are part number 25700 4 Configuring the FPGA using SelectMAP The simplest mode of configuration for the DN6000K10 Virtex II PRO FPGA involves the SelectMAP configuration method using a SmartMedia card The DN6000K10 ships with two 32 MB SmartMedia cards One of these SmartMedia cards contains reference design bit files produced for SelectMAP configuration and a file named main txt that sets the configuration options see Creating Configuration File main txt other SmartMedia card is empty and available for user applications To configure FPGA s with the reference design please skip to Starting SelecMAP Configuration Status messages are reported by the MCU via the RS232 serial port during FPGA configuration It is INOT necessary to have the serial port connection in order to configure the FPGA s in SelectMAP mode However if an error occurs during the configuration the user would be able to identify possible problems by viewing the configuration status messages See Configuring HyperTerminal on how to setup the serial port 4 1 Bit File Generation for SelectMAP Configuration Configuring the DN6000K10 Virtex H PRO FPGA requires the generation of bit files by the Xilinx ISE tools NOTE This user guide will not be updated for every revision of the Xilinx tools so please be aware of minor differences The Xilinx ISE 6 11 revision is used here First a project must be created Open the Xilinx ISE Project Nav
158. links when MCU is reading writing data to from the FPGA s CFPGA_LEDn3 Blinks when the MCU is read writing data to from the FPGA s via the USB interface MCU_LED s are used to show which FPGA is currently being configured either by SmartMedia or over USB and also give the user overall configuration status Table 24 MCU LED s MCU_LED0n LED1n MCU_LED3n On Off off Off Off Off DN6000K10 User Guide www dinigroup com 132 BOARD HARDWARE MCU_LED0n MCU LEDin MCU LED2n MCU LED3n On Off On Off On On Off Successful Configuration Error during Configuration No FPGAs configured 9 2 FPGA A GPIOLED s The DN6000K10 provides 10 GPIO directly connected to FPGA A IO Bank 2 pins Table 25 lists the FPGA GPIO on the DN6000K10 and is available to the user The signals are active LOW Table 25 FPGA A GPIO LED s FPGA U29 P11 U27 P12 U27 R11 U27 R12 U27 T12 U27 U12 27 V11 DN6000K10 User Guide U U27 U11 U27 V12 www dinigroup com 133 BOARD HARDWARE 10 Power System The DN6000K10 supports a wide range of technologies from legacy devices like serial ports to DDR SDRAM and RocketIO multi gigabit transceivers This wide range of technologies requires a wide range of power supplies
159. ls the divider function of bank 1 2 3 amp 4 ACLK of outputs Refer to Table 4 in the datasheet ROBO1_DS1 ROBOCLOCK 1 Output Divider Function JP4 B10 DN6000K10 User Guide www dinigroup com 81 BOARD HARDWARE Desctiption Connector Select Controls the divider function of bank 1 2 3 amp 4 ACLK of outputs Refer to Table 4 in the datasheet ROBO2_REFSEL1 ROBOCLOCK 2 Reference Select Input The REFSEL input controls how the reference input is configured When LOW it will use the REFA pair PLL1A as the reference input When HIGH it will use the pair PLL1BC PLLIBNC as the reference input This input has an internal pull down 2 FS ROBOCLOCK 2 Frequency Select This input must be set according to the nominal frequency Refer to Table 1 in the datasheet 2 ROBOCLOCK 2 Feedback Output Phase Function Select Controls the phase function of bank 3 amp 4 CCLK of outputs refer to Table 3 in the datasheet ROBO2 FBDSO ROBOCLOCK Z2 Feedback Dividet Function Select These inputs determine the function of the QFAO and QFA1 outputs Refer to Table 4 in the datasheet ROBO2_FBDS1 ROBOCLOCK 12 Feedback Divider Function Select These inputs determine the function of the QFAO and QFA1 outputs Refer to Table 4 in the datasheet ROBO2_FBDIS ROBOCLOCK 2 Feedback Disable This input controls the state of QFA 0 1 When HI
160. munication Equipment DCE These can be thought of as host PC for DTE and as peripheral for DCE The DN6000K10 operates in the DCE mode only Figure 17 shows the implementation of the serial port on the DN6000K10 MCU TXD U2 V C1 J x 2 RIOUT 3 tx 85232 Rios 100 85232 _ 1 pu ciu E FORCEON INVALID Hex 2 4 5 C592 590 0 147 0 1uF C2 vec ps one 1613221 Figure 17 Serial Port There two signals attached to the MCU e Transmit Data e Receive Data TXD and RXD provide bi directional transmission of transmit and receive data No hardware handshaking is supported 3 2 Configuration FPGA The Xilinx Spartan II 25150 013 is needed to handle the counters and state machines associated with the high speed USB interface and the SmartMedia card The FPGA contains 150K logic gates 48K of BlockRAM and 260 user I O s The Verilog source code for the Configuration FPGA ConfigFPGA v is provided on the CD ROM The Configuration FPGA performs the following functions e Interface to the Micro Controller DN6000K 10 User Guide www dinigroup com 66 BOARD HARDWARE Data Bus MCU DYJO 7 Address Signals A 0 15 Control Signals WRn MCU_OEn MCU PSENn Clock
161. n U13 H18 12 19 SM CEn 113 121 12 21 SM 013 122 2 20 pti 12 27 3 4 Boundary Scan TAG IEEE 1532 Mode In boundary scan mode dedicated pins are used for configuring the Virtex II Pro devices The configuration is done entirely through the IEEE 1149 1 Test Access Port The JTAG interfaces to IO on the Configuration FPGA This allows manipulation of the data as required by the application and allows the JTAG chain to become an address on the existing bus The processor can then read from or write to the address representing JTAG chain FPGA s that are not populated requires feed through resistor to maintain the daisy chain connection between FPGA s 3 4 1 FPGA JTAG Connector Figure 20 shows J16 the connector used to download the configuration files to the FPGA s 3 3V 43 3V R182 R193 1K 1K FPGA_PROGn TMS FPGA DIN TDI J16 FPGA INITn Figure 20 FPGA JTAG Connector 3 4 3 FPGA JTAG connection to Configuration FPGA Table 8 shows the connection between the FPGA JTAG connector and the Configuration FPGA DN6000K 10 User Guide www dinigroup com 71 BOARD HARDWARE Table 8 FPGA JTAG connection to Configuration FPGA Signal Name Configuration FPGA Connector FPGA U13 N21 J16 6 FPGA PROGn TMS U13 M20 16 4 FPGA DONE TDO U13 M19 j16 8 DIN TDI U13 M18 J16 10 FPGA INIT
162. n U13 M22 j16 14 4 Clock Generation 4 1 Clock Methodology The DN6000K10 Logic Emulation board has a flexible and configurable clocking scheme Figure 21 is a block diagram showing the clocking resources and connections FIXME DDR ACLK P DDR SDRAM DDR ACLKin 64M x 16 u32 FPGA A XC2VP70100 125 027 RocketlO PLLIA User CLK USER AGL Synthesizer DDR 2 DDR SDRAM neris USER BCLKpin 158442 DDR ACLK2n 64M x 16 rera RoboClock LVDS USER_CCLKp b LVDS ACLK O 15 gt PLLIBC CYB944V CLK PLL osc cLocka Us2 plecvas7 USER_ECLKpin gt USER_FCLKpin gt USER USER HCLKp n USER ICLKp n BCLK 1 osc gt FPGA B T 2 7 100 125 System gt FT 28 SUA Synthesizer c SYS_DGLKpin 4 CLKPLL sys gt 57 gt 1 uss SYS gt 55 HCLKpin CFPGA CLKOUT gt 575 ICLKpin 2 JUMPER d DDR ACLKGJ Licukip_ DDR SDRAM DDR_ICLKIn 64M x 16 BCLK 8 ura 15 PLL2BC FPGA
163. nd 66 unbuffered I O signals The DN3000K10SD Daughter Catd is pictured in Figure 46 DN6000K 10 User Guide www dinigroup com 140 BOARD HARDWARE TEE E Lab 444444 44 4 Be Ie Tos jn Do ot 7 P N ONSKIODL Figure 46 DN3000K10S Daughter Card Figure 47 show the assembly drawing of the DN3000K10SD Daughter Card IDT74FST163245 devices U1 U2 U3 are used as bus switches in the passive mode 141 www dinigroup com DN6000K10 User Guide BOARD HARDWARE and the IDT74LVC16245A U1 U2 U3 devices are used as bus transceivers in the active mode The DN3000K10SD has separate enable direction signals for each driver P TI cc E TE aC LIL IL 1 UUL LI omn Rent hn 621 _ mr a D 5 sz x QE 85 5 s STI Nnm POUPU LPLILI o LJ e D nit nn L Figure 47 Assembly drawing for the DN3000K10SD NOTE Signals 7 and P4NX6 are also used for direction select and output enable on U2 and respectively 11 2 1 Daughter Card LED s The LED s act as visual indicators representing the presence of active power sources D1 LED indicating 3 3 V present D2 LED indicating 5 0 V present D3 LED indicating 12 V present Under normal operating conditions all LED s should be ON D
164. nectors ATX Power Supply Connection NOTE RocketIO interface speed is directly affected by speed grade of the FPGA Please refer to the Xilinx datasheet 2 Virtex4l Pro FPGA The Virtex II Pro FPGA s are situated on the topside of the board For a detailed description of the capabilities of the Pro FPGA s refer to the datasheet on the Xilinx website 2 1 FPGA 2VP70 Facts The Virtex II Pro Platform FPGA a on board the DN6000K10 is in the FF1704 package The capabilities of the 2VP70 base model include 2PowerPC M 405 processor 160r 20 Multi Gigabit Transceivers 996 SelectI O e 8 Digital Clock Managers DCMs 33000 logic slices 5900 of BlockRAM BRAM 328 18 x 18 bit multiplier blocks The FF1704 package on the DN6000K10 is a 1 0mm 42 5 x 42 5mm fully populated with four corner balls removed flip chip BGA The PowerPC 405 is capable of operation at 300 MHz and is capable of 420 Dhrystone MIPs dependent on the speed grade of the part Each of are capable of 3 125 Gigabits per second in both directions for an aggregate bandwidth of 50 Gigabits per second from the MGTs 25 Gbps transmit and 25 Gbps receive The SelectIO are capable of supporting multiple high speed I O standards from LVDS to SSTL2 to PCI The DCMs are capable of 24 MHz to 420 MHz operation and provide fot clock deskew frequency synthesis and fine phase shifting DN6000K
165. nnect P11 81 TST_HDRC63 U79 G2 J1 082 No Connect P11 82 TST_HDRC64 U79 H2 J1 083 No Connect P11 83 TST_HDRC65 U79J1 11 084 No Connect P11 84 TST_HDRC66 U79 K1 J1 085 No Connect P11 85 TST_HDRC67 U79 K3 J1 086 No Connect P11 86 TST_HDRC68 17912 11 087 No Connect P11 87 TST HDRCO69 U79 M2 J1 088 No Connect P11 88 GND J1 089 No Connect P11 89 TST_HDRC70 U79 N1 11 090 No Connect P1190 TST HDRC71 U79 N3 1 091 No Connect P1191 TST_HDRC72 U79 P2 1 092 No Connect P11 92 5 HDRC73 U79 R1 J1 093 No Connect P11 93 1 5V J1 094 No Connect P11 94 TST HDRC74 U79 R3 1 095 P4NX7 17 45 P1195 IST HDRC75 U79 T3 J1 096 P4NX6 17 47 P11 96 5 HDRC76 079 02 1 097 No Connect P1197 IST HDRC77 U79 V2 11 098 No Connect P1198 IST HDRC78 U79 W2 1 099 No Connect P11 99 GND J1 100 No Connect P11 100 12V J1 101 No Connect P11 101 GND TST HDRC CL 1 102 MBCK1 J2 27 P11 102 KIN U80 AN22 J1 103 No Connect P11 103 1 5V J1 104 MBCKO J2 28 P11 104 GND DN6000K 10 User Guide www dinigroup com 167 BOARD HARDWARE Daughter Card Connections DN6000K10 IO Connections Test Header C Test Signal Name Connector Test Signal Name FPGA Pin Header Header 1 105 No Connect P11 105 3 3V 11 107 11 107 GND 11 108 ECLK1 J5 7 P11 108 GND J1 109 No Connect 11 109 GND J1 110 No Connect P
166. non functional for this dialog Verbose mode will print what is read from what address 3 Write and Read DWORD s this combines the previous two items It first writes the DWORD to a given address range and then reads back those addresses The values used to test memory will determine what 15 wtitten to each address 4 Test Address Space this will write the specified value to a given address range read it back and check the results for errors Note some memory addresses cannot be written to and will return errors Please check the FPGA memory maps in Appendix A for clarification 5 Display Address Space coming soon 6 Test DDR through PPC s tests an FPGA s DDR by using the PPC built into each FPGA 7 Test FLASH through PPC s tests an FPGA s flash by using the PPC built into each FPGA 8 Test SRAM through PPC s tests an FPGA s SRAM by using the PPC built into each FPGA 9 Test Internal Registers coming soon 10 Test Interconnect coming soon 11 Test ALL through PPC s tests an FPGA s DDR flash and SRAM by using the PPC built into each FPGA 12 Display Memory Map coming soon 1 1 8 Settings Info Menu The Settings Info Menu has the following options DN6000K10 User Guide www dinigroup com 18 INTRODUCTION VIRTEX II AAND 15 1 2 3 4 5 6 Set FPGA CLK Frequency When the DNN6000k1
167. ntroller The MCU interfaces to the Configuration FPGA 013 via an 8 bit bus and the SmartMedia interfaces to the Configuration FPGA via an 8 bit bus The FPGA s x9 on the board interfaces to the Configuration FPGA via the JTAG interface and an 8 bit bus used during Serial and SelectMap programming of the FPGA s The amount of internal SRAM is not large enough to hold the FAT needed for SmartMedia so an external 128Kb x 8 SRAM U8 was added In addition a 1Mb x 8 FLASH U6 was added to store the downloaded program code An external EEPROM U9 configures the MCU during power up The micro controller has the following responsibilities e Reading the SmartMedia card via the Configuration FPGA e Communicate to the system via the USB Interface Configuring the Virtex II Pro FPGA s 9 e Executing DN6000K10 self tests e Drive status LED s DN6000K10 User Guide www dinigroup com 63 BOARD HARDWARE 311 MCU EEPROM Interface During the power up sequence internal logic checks the l C compatible port for the connection of an EEPROM U9 whose first byte is either OxCO or 2 If found the MCU uses the VID PID DID values in the EEPROM in place of the internally stored values of it boot loads the EEPROM contents into internal 0 2 The EEPROM interface is shown in Figure 12 3 3 3 3 3 3V R128 5 129 5 ug 22K lt 2 2K 3 R155 10K R156 10K 0 SCL U R157 10K t 56 1 C SUA
168. oclock jumpers are set to their default locations then ACLKx will be 133 33MHz and BCLKx will be 48MHz 3 5 PPCRS232 Port Setup There are 4 RS232 ports that are shared with the 9 VirtexII FPGAs These ports are multiplexed by the Configuration and can be changed the MCU Main Menu see Configuring HyperTerminal The default setup is P3 FPGA P4 FPGA Port P6 FPGA Port4 P7 FPGA C 3 6 Powering ON the DN6000K 10 This section describes what is necessary to power up the DN6000K10 1 Install the SmartMedia card containing reference design into the DN6000K10 2 If switch position 4 on S2 is OFF then the MCU will automatically boot from the flash and try to configure the FPGAs via the SmartMedia card please see Creating Configuration File for information on setting up the files DN6000K10 User Guide www dinigroup com 11 GETTING STARTED on the SmartMedia card If switch position 4 on S2 is ON then the MCU will wait for USB commands and will not be able to configure the FPGAs until the USB application on the product CD in Source CodeNUSBControllerNUSBController exe is opened You can hook up the RS232 port P2 to see messages during FPGA configuration see Configuring HyperTerminal for more details Plug ATX power supply into J17 and turn on the power The power will not turn on unless a jumper is installed in J53 1 2 4 Playing with your DN600
169. om 2 SIE He BOARD HARDWARE Signal Name FPGA Pin DDR FPGA D1 ADD2 U53 AM19 DDR_FPGA_D1_ADD3 U53 AL19 DDR_FPGA_D1_ADD4 U53 AP19 DDR FPGA D1 ADD5 U53 AN19 DDR FPGA D1 ADD6 U53 AR17 DDR_FPGA_D1_ADD7 U53 AP17 DDR FPGA D1 ADDS8 U53 AL18 DDR FPGA D1 9 U53 AL17 DDR FPGA D1 ADD10 U53 AM17 ci DDR D1 1 U53 AN17 DDR FPGA D1 ADD12 U53 AP16 c DDR D1 ADD13 U53 AN16 DDR FPGA D1 0005 U53 AY18 c DDR FPGA D1 LDQS U53 AV20 DDR FPGA D1 UDM U53 AW17 DDR FPGA D1 LDM U53 AL21 c DDR FPGA D1 U53 AW20 c DDR D1 BA1 53 A Y20 DDR FPGA D1 CASN 53 AT16 G DDR FPGA D1 CKE DDR FPGA D1 CSN 53 AV16 DDR FPGA D1 RASN 53 AR16 c DDR FPGA D1 WEN U U U53 AW16 U U U 53 AL15 G DDR 02 DATAO U53 AW14 DDR 02 DATA1 U53 AV14 DDR D2 DATA2 U53 AM15 DDR D2 DATA3 U53 AN15 DDR D2 DATA4 U53 AU14 ct ce ci DDR D2 DATA5 DN6000K 10 User Guide U53 AT14 www dinigroup com BOARD HARDWARE Signal Name FPGA Pin DDR D2 DATA6 U53 AN14 c DDR D2 DATAT7 U53 AM14 DDR_D2_DATA8 U53 AM13 DD
170. option is available through the SMA connectors J1 J4 which is the buffered and distributed throughout the board A system oscillator X4 is buffered and distributed throughout the board This oscillator can be used to clock the Power PC s on each FPGA if required Each FPGA has a dedicated RocketIO clock synthesizer driven by a 25MHz crystal DDR clocks DDR CLKA Ip n are generated by each individual FPGA A dedicated 48MHz oscillator X1 clocks the Configuration FPGA 013 which in turn buffers the JTAG clock signal as well as the setial parallel clock signal DCLK required for FPGA configuration The connections between the FPGA s and various clocking resources are documented in Table 9 covering the clocking inputs and outputs respectively Table 9 Clocking inputs to the FPGA s Signal Name FPGA A Pin Clock Refdes and Pin ACLKO 27 AU22 62 89 BCLKO 27 22 63 89 27 621 13 USER ACLKp USER ACLKn 27 21 12 27 21 05 3 578 ACLKp 27 AN21 65 2 SYS ACLKn 27 121 27 021 RCKTIO OSCT Ap 39 14 RCKTIO OSCT An RCKTIO OSCB Ap 27 AT21 RCKTIO_OSCB_An 27 AU21 DDR_ACLKp 27 22 E HU DDR 21 22 Cr Hee HDRA CLKIN 27 AT22 DN6000K10 User Guide www dinigroup com 73 BOARD HARDWARE
171. or Test Signal Name FPGA Pin Header Header 11 158 P3N32 J6 23 P11 158 TST_HDRC122 U78 AE2 11 159 P3N31 J2 44 P11 159 TST_HDRC123 U78 AP2 J1 160 P3N30 J2 45 11 160 TST HDRC124 U78 AH1 J1 161 P3N25 J6 25 11 161 TST HDRC125 U78 AJ1 J1 162 No Connect P11 162 GND J1 163 P3N24 J6 27 P11 163 TST_HDRC126 U78 AK1 1 164 P3N21 16 29 11 164 HDRC127 U78 AK3 11 165 P3N20 16 31 11 165 TST HDRC128 U78 AL3 11 166 P3N17 16 33 11 166 TST HDRC129 U78 AM2 1 167 P3N16 16 35 11 167 HDRC130 U78 AN1 11 168 P3N13 J6 37 11 168 TST HDRC131 U78 AN3 11 169 P3N12 16 39 11 169 HDRC132 U78 AP2 J1 170 P3N11 J247 P11 170 HDRC133 U78 AR3 LET P3N10 J2 48 P11 171 TST HDRC134 U78 AT2 1 172 P3N5 16 41 P11 172 151 HDRCIS5 U78 AUI 11 173 11 173 GND 1 174 16 43 11 174 TST_HDRC136 U78 AU3 1 175 16 45 11 175 HDRC137 U78 AV2 11 176 J6 47 P11 176 HDRC138 U78 AW1 1 177 P4N25 17 1 11 177 HDRC139 U78 AW3 1 178 P4N24 17 3 11 178 140 1979 02 J1 179 P4N23 17 5 11 179 14 U79 E1 J1 180 P4N22 17 7 11 180 TST HDRC142 U79 E3 1 181 P4N17 17 9 11 181 HDRC143 UT79 2 1 82 P4N16 7 11 11 182 TST HDRC144 U79 G1 1 183 P4N15 1 15 11 183 TST HDRC145 U79 G3 DN6000K 10 User Guide www dinigroup com 170 BOARD HARDWARE
172. ore information on the JTAG debug port signals Information on JTAG is found in the IEEE standard 1149 1 1990 8 1 1 CPU Debug Connectors Figure 37 shows JP1 the vertical header used to debug the operation of software in the PPC of FPGA A there is another connector on FPGA C This is done using debug tools such as Parallel Cable IV or third party tools This connector cannot be used when the Mictor connector is in use JTAG TRSTn DBUGA VSEN Pin 14 must 1 be removed HEADER 8X2 Figure 37 CPU Debug Connector DN6000K 10 User Guide www dinigroup com 128 BOARD HARDWARE 8 12 CPU Debug Connection to FPGA s The connection between the PPC debug connectors and the FPGA s are shown in Table 21 These signals are attached to the PowerPCTM 405 JTAG debug resources using normal FPGA routing resources The JTAG debug resources are not hard wired to particular pins and are available for attachment in the fabric making it 15 possible to route these signals to whichever pins the user would prefer to use Table 21 CPU Debug connection to FPGA Signal Name FPGA Pin Connector PPCA JTAG TDO U27 E36 JTAG TDI U27 D36 1 3 PPCA TRSTn GND 14 PPCA_JTAG_TCK U27 D37 JP17 PPCA_JTAG_TMS U27 E37 17 DBG HALIn U27 F36 JP1 7 PPCC_JTAG_TDO U29 AC34 2 1 PPCC_JTAG_TDI U29 AC33 JP2 3 PPCC_JTAG_TRSTn GND JP2 4
173. ory is provided by the 1Mb x 8 FLASH 06 To eliminate bus contention the device has separate Chip Enable FLASH_CSn Write Enable MEM_WRn and Output Enable MEM_OEn controls Device programming occurs by executing the program command sequence Address space above 2000H is banked through the Configuration FPGA The FLASH interface is shown in Figure 14 DN6000K 10 User Guide www dinigroup com 64 BOARD HARDWARE M A1 M D CU 25 lo oa 29 DO mumn ____23 001 33 MCU DZ E 23 33 8 MCUAM ____22 2 35 MCU A5 21 003 38 MCU D4 MCU AG ____20 A4 004 MCUA7 19 5 005 42 __ MCU AB 18 X DQ6 14 WCU D7 MCUAS 8 7 Dar o 78 a Px ____6 9 009 4 5 410 0010 36 A9 4 0011 12 0012 r CROAT 16 1 14 0914 45 48 18 ap um 18 17 17 17 sc 18 m NC 9 FLASH CS 38 E 4 I X MEM WHn 1i PP 14 FLASH ee 8 NOWP FLASH RY BYi SLASH 15 voc 4 ms 27 YS RSTI GND SYS_RSTn 12 AM29LV800B TSOP48 Figure 14 FLASH 3 14 MCU General Purpose IO
174. places where changes must be made to get the desired configuration 1 Synplicity synthesis project file II files in source ucf Xilinx EDK project file IV Xilinx EDK processor source code files PPC code fpga_params h V Setting up the build utility make bat Note that the build utility runs the xilinx tools from the command line so there are no Xilinx Project Navigator files to edit If you choose to use the Project Navigator GUI be very careful to have all the appropriate settings 2vp70 vs 2vp100 The following sections explain what to change and what options the user has to accomplish these changes Most are automated some are not It is highly recommended that everything be recompiled after making any of these changes including the PPC netlist the synplicity project the Xilinx project and the EDK source code If everything is not updated unpredictable behavior will result If you aren t sure delete all tool generated files and start fresh For information on the usage of the build tool make bat see the top of the make bat file I SYNPLICITY SYNTHESIS PROJECT FILE DN6000K 10 User Guide ww w dinigroup com 33 INTRODUCTION THE SOFTWARE TOOLS In the synthesis folder there are nine project files one for each FPGA The line option part XC2VP70 must be modified appropriately for the VP70 or VP100 This change as well as changes to the parameters described below may
175. plemented in the DDR SDRAM controller design 6 2 5 DDR SDRAM Power Supply The DATEL 2 5V module 014 U64 U89 is used to supply power to the 2 5V plane that supplies the VDDQ pins of the DDR SDRAM devices Due to the power requirements three separate PSU s are used to supply the power to the DRR devices on FPGA A C FPGA D F and FPGA G I According to Specification Double Data Rate DDR SDRAM termination voltage VTT must track 50 of VDDQ over voltage temperature and noise The ML6554 014 is used as a voltage source for DDR termination Connecting the Vger pin to the 2 5V supply allows the regulator to track the VDDQ supply refer to Figure 35 A dedicated VREF output supplies the VREF pins on the FPGA as well as on the DDR SDRAM devices and maintains a less that 40mV offset from VTT DN6000K 10 User Guide www dinigroup com 106 BOARD HARDWARE 43 3V 505 _ y 190 C1743 C382 C1732 1733 C381 33pF 100uF 100 100uF EL 100uF U64 10V 10V 10V 10V 42 5V 16 1 10 10 10 10 1 c1744 VoD 15 PVDD1 5 PVDD2 14 VTT2 1 254 3 3 R58 10K 12 3 ro 2 1 25V Mv SHDN L C380 635 61729 10 ep 3 3uH 4 150uF 150 6 3V
176. ration menu Check configuration status Change MAIN configuration file Media Display Smart Media text file Change RS232 PPC Ports Write to FPGA at current address Read from FPGA at current address Test FLASH chip through PPC s Test DDR chip through PPC s FULL MEMORV TEST through 5 Interconnect Test will test all configured FPGAs Figure 9 Main Menu The HyperTerminal interface gives the user an easy method for handling and monitoring the DN6000K10 FPGA configuration 4 3 1 Description of Main Menu Options Table 3 describes the Menu options found on HyperTerminal intetface Table 3 HyperTerminal Main Menu Options Function 1 Configure FPGA s Using main txt Description The FPGA will configure in SeleccMAP mode 2 Interactive This option takes you to a menu titled Interactive configuration menu Configuration Menu and allows the to be configured through a set of menu options instead of using the main txt file menu options are described below 3 Check Configuration This option checks the status of the DONE pin and prints out Status whether or not the FPGA s have been configured along with the file name that was used for configuration 4 Change MAIN By default the processor uses the file main txt to get the name configuration file of the bit file to be used for configuration as well as options for DN6000K10 User Guide the conf
177. rcode 8 Hex Digits Enter upto characters 12 The Configuration FPGA is now programmed You must power cycle the board before the Configuration FPGA will be configured with the new PROM data 2 MCU Details Programming the MCU Switch 4 on S2 tells MCU how to boot Ifthe 4 switch position 15 ON then the MCU boot sequence will behave in the following manner 1 If the USB cable is plugged in when the DN6000k10 is powered on reset the MCU boots from the EEPROM U8 and waits for USBController applicatin to send commands In this case the MCU FLASH firmware stored in U6 can be updated In this state the MCU has limited USB functionality and cannot configure the FPGAs via USB SmartMedia or perform many of the other USB GUI functions 2 If the USB cable is NOT plugged in when the DN6000k10 is powered on reset the MCU first boots from the EEPROM DN6000K10 User Guide www dinigroup com 45 PROGRAMMING CONFIGURING THE HARDWARE U8 and then automatically boots from the MCU FLASH U6 In this case the MCU FLASH can NOT be updated o Ifthe 4 switch position is OFF then the MCU will always boot from the MCU FLASH 06 regardless of whether the USB cable is plugged in or not When the MCU has booted from the FLASH it has full USB and FPGA configuration functionality This is the default factory setup as of 1 1 05 Please note you can NOT update the MCU FLASH in the switch position 3 Configuring HyperTerminal terminal
178. ream encryption o 1532 support O Partial reconfiguration o Unlimited reprogrammability o Readback capability e Supported by Xilinx Foundation and Alliance series development systems Integrated VHDL and Verilog design flows ChipScope Pro Integrated Logic Analyzer 0 13 um nine layer copper process with 90 nm high speed transistors 1 5V VCCINT core power supply dedicated 2 5V VCCAUX auxiliary and VCCO powet supplies e IEEE 1149 1 compatible boundary scan logic support Hip Chip and Wire Bond Ball Grid Array BGA packages in standard 1 00 mm pitch Each device 100 factory tested 3 Foundation ISE 6 1i ISE Foundation is the industrys most complete programmable logic design environment ISE Foundation includes the industry s most advanced timing driven implementation tools available for programmable logic design along with design entry synthesis and verification capabilities With its ultra fast runtimes ProActive Timing Closure technologies and seamless integration with the industry s most advanced verification products ISE Foundation offers a great design environment for anyone looking for a complete programmable logic design solution 3 1 Foundation Features 3 1 1 Design Entry ISE greatly improves your Time to Matket productivity and design quality with robust design entry features ISE provides support for today s most popular methods for design capture including HDL and schematic ent
179. reset push button 51 causes the following sequence of events 1 Resetofthe Configuration FPGA and MCU 2 Reset of FPGA s through FPGA_GRSTn signal 3 FPGA configuration is cleared 4 If the dipswitch is set for SelectMAP configuration option and there is a valid SmartMedia card inserted into the socket then the FPGA s will be configured A SmartMedia card is valid if it complies with the SSFDC specification and contains a file named main txt in the root directory If the card is invalid or there is no card present then the FPGA will not be configured 5 The Main Menu will appear in the Terminal Window Note The identical sequence of events occurs at power up DN6000K10 User Guide www dinigroup com 94 BOARD HARDWARE 5 2 PPC Reset The DN6000K10 also contains another RESET push button S3 used to reset the PPC s in each FPGA This signal is pulled up on the DN6000K10 The user is responsible for debouncing the reset signal in the Configuration FPGA One of the 1 40 signals must be used to reset the PPC s in the FPGA s Table 16 shows the connection between the reset push button and the FPGA Table 16 PPC Reset Signal Name FPGA Pin Push Button Switch PPC_RESETn U13 H5 53 4 6 The DN6000K10 provides two different memory technologies to the user FLASH and DDR SDRAM in various densities 6 1 FLASH The FLASH memory components on the DN6000K10 can accommodate up to 4M x 16 devi
180. ry integration of IP cores as well as robust support for reuse of your own IP ISE even includes technology called IP Builder which allows you to capture your own IP and reuse it in other designs ISE s Architecture Wizards allow easy access to device features like the Digital Clock Manager and Multi Gigabit I O technology ISE also includes a tool called PACE Pinout Area Constraint Editot which includes a front end pin assignment editor a DN6000K 10 User Guide ww w dinigroup com 24 INTRODUCTION VIRTEX II AAND ISE design hierarchy browser and an area constraint editor By using PACE designers are able to observe and describe information regarding the connectivity and resource requirements of a design resource layout of a target and the mapping of the design onto the FPGA via location atea This rich mixture of design entry capabilities provides the easiest to use design environment available today for your logic design 3 1 2 Synthesis Synthesis is one of the most essential steps in your design methodology It takes your conceptual Hardware Description Language HDL design definition and generates the logical or physical representation for the targeted silicon device A state of the art synthesis engine is required to produce highly optimized results with a fast compile and turnaround time To meet this requirement the synthesis engine needs to be tightly integrated with the physical implementation tool and
181. s The main focus of the design flow is integrating the programs with each other to accomplish the system design The system design process can be loosely divided into the following tasks Builds the software application DN6000K10 User Guide www dinigroup com 26 INTRODUCTION VIRTEX II AAND 15 Simulates the hardware description e Simulates the hardware with the software application Simulates the hardware into the FPGA using the software application in on chip memory Runs timing simulation e Configures the bitstream for the FPGA DN6000K10 User Guide www dinigroup com 27 INTRODUCTION TO THE SOFTWARE TOOLS Chapter Introduction to the Reference Design This chapter introduces the DN6000K10 Reference Design including information on what the reference design does how to build it from the source files and how to modify it for another application 1 Exploring the Reference Design 1 1 What is the Reference Design The reference design is a fully functional Virtex Pro FPGA design capable of demonstrating most of the features available on the DN6000K10 Features exercised in the reference design include e Access to the DDR SDRAM Modules At 133Mhz e Access to FLASH memory UART Communication e FPGA Interconnect e Interaction with the Configuration FPGA and MCU e Use of Embedded PowerPC Processors Memory Mapped Access Between PPC And User Design e Access to external LED s
182. s generated from an external sources and presented to the FPGA as differential inputs The reference clocks connect to the REFCLK or BREFCLK ports of the multi gigabit transceiver MGT While only one of these reference clocks is needed to drive MGT BREFCLK or BREFCLK2 must be used for serial speeds of 2 5 Gbps or greater The reference clock also locks a Digital Clock Manager DCM or a BUFG to generate all of the other clocks for the GT Never run a reference clock through DCM since unwanted jitter will be introduced DN6000K10 User Guide www dinigroup com 90 BOARD HARDWARE 4 7 1 Clocking Methodology At speeds of 2 5 Gbps or greater REFCLK configuration introduces more than the maximum allowable jitter to the RocketlO transceiver For these higher speeds BREFCLK configuration is required The BREFCLK configuration uses dedicated routing resources that reduce jitter BREFCLK must enter the FPGA through dedicated clock I O BREFCLK can connect to the BREFCLK inputs of the transceiver and the CLKIN input of the DCM for creation of USRCLKs For more information refer to the Rocket IO User Guide available from the Xilinx website REF_CLK_V_SEL refclk REFCLKSEL refclk_out to PCS and PMA brefclk brefclk2 ug024 35 091802 Figute 29 REFCLK BREFCLK Selection Logic 4 7 2 1658442 Programmable LVDS Clock Synthesizer The DN6000K10 uses the ICS8442 LVDS clock synthesizer for generating
183. s pin determines the clock outputs disable state When this input is HIGH the clock outputs will disable to high impedance HI Z When this input is LOW the clock outputs will disable to HOLD OFF mode When in MID the device will enter factory test mode ROBO2 MODE ROBOCLOCK Z2 Output Mode This pin determines the clock outputs disable state When this input is HIGH the clock outputs will disable to high impedance HI Z When this input is LOW the clock outputs will disable to HOLD OFF mode When in MID the device will enter factory test mode MISC Power jumper 3 3 Switch Setup and Description Default Description Position 52 1 _ FPGA MSEL 0 used to set configuration mode for all VirtexII Pro FPGAs 52 2 FPGA_MSEL1 FPGA used to set configuration mode for all VirtexII Pro DN6000K10 User Guide www dinigroup com 10 GETTING STARTED Default Signal Name Description Position FPGAs Off MSEL2 FPGA MSEL 2 used to set configuration mode for all VirtexII Pro FPGAs DP SW3 Not used Configuration FPGA MSEL 0 CFPGA_MSEL1 Configuration FPGA MSEL 1 CFPGA_MSEL2 Configuration FPGA MSEL 2 Not Connected N A 3 4 Oscillator Setup The DN6000k10 is shipped from the factory with a 33 33MHz in X2 14 31818 in and 100MHz in X4 If the Rob
184. scillators Of note is the Epson line of oscillators called the SG 8002 Programmable Oscillators Any frequency between 1 00MHz 106 25MHz can be procured in the normal Digi Key shipping time of 24 hours A half can 3 3 CMOS version is needed with a tolerance of 50ppm The part number for an acceptable oscillator from this family would be SG 8002DC PCB ND e Package SG 8002DC Halfcan Output Enable 3 5 V CMOS 50 ppm the order is placed via the web page the requested frequency to two decimal places is placed in the Web Order Notes datasheet is on the CD ROM for this oscillator Any polarity of output enabled for each oscillator on pin 1 is acceptable Ensure the proper jumper settings for JP6 B1 JP6 B2 See Table 11 for a description 4 3 6 Common Clock Source Selections The following configuration is the most common Configuration 1 CLOCKA gt PLL1A CLOCKB PLL2BN RoboClock 1 062 is driven from oscillator RoboClock 2 063 is driven from oscillator X2 RoboClock 2 can also be driven from RoboClock 1 output ACLK9 if required 4 4 External Clocks The clock source jumper JP5 allows the user a simple means to attach external clocks to the clock grid The user can attach 10 pin ribbon cable to JP5B C which allows for connection the differential pair inputs of both RoboClocks JP5C ground pins for signal integrity These signals are described in Table 10 Both differential pairs provide som
185. se the PPC Reset Button S3 to reset the design DN6000K 10 User Guide ww w dinigroup com 30 INTRODUCTION THE SOFTWARE TOOLS 1 3 Compiling The Reference Design This section deals with the source code to the Reference Design which can be found on the CD ROM All file references are with respect to the root directory of the Reference Design source code source FPG A Files that specific to the DN6000K10 design are found in the DN6000K10 subdirectory whereas general application code is found in the common subdirectory 1 3 1 The Xilinx Embedded Development Kit EDK The Reference Design uses the Xilinx EDK to instantiate an embedded PowerPC Processor The EDK project can be found at IDN6000K10 PPC system xmp and can be opened and modified with the Xilinx Embedded Development Kit software 1 3 2 Synplicity Synplify The Dini Group uses Synplicity s Synplify software to for design synthesis The Synplicity projects for each of the 9 FPGA s on the DN6000K10 can be found at DN6000K10 synthesis pr These projects have been compiled using Synplify Pro version 7 3 1 3 3 Xilinx ISE A sample Project Navigator project is located at DN6000K10 implement fpga npl For information on using Xilinx ISE see the section Foundation ISE 6 1i in Chapter 3 1 3 4 The Build Utility Make bat The Build Utility is found at DN6000K10 build make bat This batch file is used to set system parameters to the desired confi
186. ssue any commands to External Host Command Register Status results can be read after command register is cleared decode for the test results is as follows Bit 0 overall pass fail pass 1 fail 0 Bit 1 register test pass fail Bit 2 flash test pass fail Bit 3 ddr test pass fail Bit 4 interconnect test pass fail 0 6 00 0018 0 6 00 0018 Contains information on what FPGAs are stuffed on the egister DN6000k10 as well as what type of FPGAs they are The register has the following format Bit 0 1 if FPGA A is stuffed 0 otherwise Bit 1 1 if FPGA B is stuffed 0 otherwise Bit 2 1 if FPGA is stuffed 0 otherwise Bit 2 1 if FPGA D is stuffed 0 otherwise Bit 2 1 if FPGA E is stuffed 0 otherwise Bit 2 1 if FPGA F is stuffed 0 otherwise Bit 2 1 if FPGA G is stuffed 0 otherwise Bit 7 1 if FPGA is stuffed 0 otherwise Bit 8 1 if FPGA I is stuffed 0 otherwise Bit 9 1 if FPGA is 2vp100 0 if 2vp70 Bit 10 1 if FPGA is 2vp100 0 if 2vp70 Bit 11 1 if FPGA C is 2vp100 0 if 2vp70 Bit 12 1 if FPGA D is 2vp100 0 if 2vp70 Bit 13 1 if FPGA E is 2vp100 0 if 2vp70 Bit 14 1 if FPGA F is 2vp100 0 if 2vp70 Bit 15 1 if FPGA is 2vp100 0 if 2vp70 Bit 16 1 if FPGA H is 2vp100 0 if 2vp70 Bit 17 1 if FPGA Lis 2vp100 0 if 2vp70 181 FPGAH Start End Address Read Descript
187. t the latencies associated with DDR SDRAM are on par with standard SDRAM 6 2 1 Basics of DDR Operation DDR SDRAM provides data capture at a rate of twice the clock frequency Therefore DDR SDRAM with a clock frequency of 100 MHz has a peak data transfer rate of 200 MHz or 6 4 Gigabits per second for a 16 bit interface In order to maintain high speed signal integrity and stringent timing goals a bi directional data strobe is used in conjunction with SSTL 2 signaling standard as well as differential clocks DDR SDRAM operates as a source synchronous system in which data is captured twice per clock cycle using a bi directional data strobe to clock the data The DDR SDRAM control bus consists of a clock enable chip select row and column addresses bank address and write enable Commands are entered on the positive edges of the clock and data occurs for both positive and negative edges of the clock The double data rate memoty utilizes a differential pair for the system clock and therefore has both a true clock CKp and complementary clock CKn signal 6 2 2 DDR SDRAM Configuration The DDR SDRAM memory components on the DN6000K10 are arranged as a 16 bit mode refer to Figure 32 as an example of a DDR interface shown is the DRR device on FPGA A Each FPGA has two discrete parts U22 U32 etc The components used are 64Mb x 16 parts organized as 16 million deep by 16 bits wide and 4 banks for more information refer to Micron s dat
188. te data after selection this option Performs a DWORD read at the current FPGA address You will see the current address and readback data at the top of the Main Menu b Test FLASH Chip Allows the user to select which FPGA FLASH to test The test through PPC s is actually run by the PPC s and all detailed test messages will appear on PPC PORT 1 P3 c Test DDR Chip Allows the user to select which FPGA DDR s to test The test through PPC s is actually run by the PPC s and all detailed test messages will appear on PPC PORT 1 P3 DN6000K 10 User Guide ww w dinigroup com 57 PROGRAMMING CONFIGURING THE HARDWARE d FULL MEMORY Runs the following tests on all configured FPGAs DDR TEST through FLASH Internal Registers and Interconnect The FPGA tests PPC s ate performed in parallel and the user needs to hook up the PPC Ports to see detailed test messages Only 4 FPGAs can output test messages via the PPC Ports so they will need to be setup before hand Interconnect Test Runs the interconnect test on all configured f Turn fans on off Either tutns the fans on off depending on current setting Selecting Option 2 results in the following menu to be displayed refer to Figure 10 DN5000106 HyperTerminal 9 x Ele Edit View Call Transfer 218 alal ENTER SELECTION 2 INTERRCTIVE CONFIGURRTION MENU 1
189. tform refer to Figure 48 DN6000K 10 User Guide www dinigroup com 171 BOARD HARDWARE Figure 48 PM7200 Server Case 12 1 2 PWB Dimension DN6000K 10 User Guide www dinigroup com 172 BOARD HARDWARE The DN6000K 10 PWB conforms to the following dimensions RR auta g ut neat 5 X HEAR Gut Unger gt HHHH x x X B x x ttytxt ff 5 Wu X 44 Ht i 44 1 x dbi 44 i it HH tet RE s X as iL m 47 meds ate M TER fe 7 Xe x x TM dx x iii Pee a PPP x PRUNUS sisi s PPP P 2 DN6000K 10 User Guide www dinigroup com 173 APPENDIX DN6000K 10 User Guide Chapter Appendix A Address Maps The DN6000k10 reference design can be used to verify the functionality of the board There are several ways to exercise the reference design features In each FPGA there is PowerPC code that allows the user to communicate directly with the FPGA through the RS232 port that is discussed in Using the Reference Design Another method of communication is through
190. the following 172 12 1 2 The DN6000K10 PWB conforms to the following dimensions 173 APPENDIX WU OE ER E 174 List of Figures DN6000K10 EOGIC Enmulatiort Board RUBUS UHR EUH NEUE NS eerie 6 Figure 2 Default Jumper Setup Figure 3 DN6000k10 Not Found Figure 4 Configuration PROM FPGA Programming Header Figure 5 New Project Screen Shot Figure 6 Figure 7 New Project Dialog Box Figure 8 Project Navigator Figure 9 Main Menu Figure 10 Interactive Configuration Option Menu Figure 11 DN6000K10 Block Diagram Figure 12 MCU EEPROM Interface Figure 13 MCU SRAM Figure 14 MCU FLASH Figure 15 MCU General Purpose IO Connectot Figure 16 USB Connector Figure 17 MCU Serial Pott Figure 18 Configuration PROM FPGA Programming Figure 19 SmartMedia Connector Figure 20 FPGA JTAG Connector Figure 21 Clocking Block Diagram Figure 22 LVPECL Clock Input and Termination Figure 23 Clock Source Jumper Figure 24 RoboClock Functional Block Diagram Figure 25 RoboClock Configuration Jumpers Figure 26 External SMA Clock Figure 27 DDR DCM Implementation Figure 28 PPC External Clock Figure 29 REFCLK BREFCLK Selection Logic Figure 30 Reset Topology Block Diagram Figure 31 FLASH
191. transceivers see the RocketlO Transceiver User Guide at http www xilinx com publications products v2pro userguide ug024 pdf The DN6000K10 board has 10 RocketIO transceivers available on the topside of the FPGA and 10 on the bottom side These 20 transceivers are connected in various configurations depending on the FPGA position on the board refer to the block DN6000K10 User Guide Www dinigroup com 124 BOARD HARDWARE diagram for more information FPGA A C G I has access to two SMA interfaces while the rest of the RocketIO interfaces are used for chip to chip communication Refer to the RocketIO Block Diagram in Figure 36 SMA 1 SMA2 SMA 1 SMA2 0 0 0 1 n i XILINX XILINX XILINX eooo Yl FPGAA FPGA B FPGAC A m ROCKETIO 10 ROCKETIO 10 ES 2VP70 100 to xoovpzooo xoovpzorto FE1704 FF1704 FF1704 1 1 t E EM P a Q NX 9 gt lu xe P E 8 T 8 5 ps 5 XILINX N XILINX XILINX o Im FPGAA nockerio 10 FPGA C x XC2VP70 100 XC2VP7O 100 XC2VP70 100 x 8 FF1704 AFF1704 FF1704 8 Pa ps H m d N E
192. tuffed 0 otherwise Bit 9 1 if FPGA is 2vp100 0 if 2vp70 Bit 10 1 if FPGA is 2vp100 0 if 2vp70 Bit 11 1 if FPGA is 2vp100 0 if 2vp70 Bit 12 1 if FPGA D is 2vp100 0 if 2vp70 Bit 13 1 if FPGA E is 2vp100 0 if 2vp70 Bit 14 1 if FPGA F is 2vp100 0 if 2vp70 Bit 15 1 if FPGA is 2vp100 0 if 2vp70 Bit 16 1 if FPGA H is 2vp100 0 if 2vp70 Bit 17 1 if FPGA Iis 2vp100 0 if Zvp70 182 Start End Address Read Description Address Write DDR 1 U73 0 8000 0000 OXS0FF FFFF Address maps directly to DDR 1 DDR 2 083 0 8100 0000 FFFF Address maps directly to DDR 2 083 only avail if 2vp100 FLASH U86 0 8800 0000 FFFF Address maps directly to FLASH DDR Phase Shift 0 8 00 0000 0 8 00 0000 R W DDR phase shift value upper WORD is read only and contains Register the current phase shift value lower WORD is write only External Host 0x8C00_0004 0x8C00_0004 R W Write Read register for MCU to issue the following commands Commands Register 0x1 test all functionality 0x2 test registers 0x3 test FLASH 0x4 test DDR s 0 5 test FPGA interconnect To issue a command MCU must write one of the above values to this register The MCU can then poll this register to check if the test 15 done register will return all zeros when finished
193. ugh the EDK GUI using the build utility or by hand The device line looks like one of the following Device xc2vp70 Device xc2vp100 When changing between FPGA s the build utility can be used as follows make VP70 makes changes to synplicity and EDK project files and UCF files to compile for VP70 make VP100 makes changes to synplicity and EDK project files and UCF files to compile for VP100 IV XILINX EDK PROCESSOR SOURCE CODE The file PPC code fpga_params h defines the software parameters for the PowerPC part of the design The folder PPC code fpga contains a parameter file for DN6000K10 User Guide www dinigroup com 36 INTRODUCTION THE SOFTWARE TOOLS each of the nine FPGA s When compiling for FPGA A the PPC code fpga params fpga should be modified for the appropriate parameters and then it s contents should be placed in PPC code fpga params h The build utility automatically copies the correct parameters to params h for each FPGA that it compiles The parameters found in fpga_params h and each file in the fpga_params folder are as follows FPGA_NAME Defines text used in print statements to identify the FPGA INTERCON_MASTER If INTERCON_MASTER was defined in the synplicity project file then it should be defined here to include the associated menu options See the synplicity project file section above for more information IN
194. vides 48 buffered I O signals available on headers J3 and The function of these signals is position dependent U1 U2 and U3 allow for different populating options and devices can be active or passive Active The LCV162245A is used for asynchronous communication between data buses It allows data transmission from the A to the B or from the B to the A bus depending on the logic level at the direction control DIR input The output enable OE input can be used to disable the device so that the busses are effectively isolated Passive The FST163245 bus switches are used to connect or isolate two ports without providing any current sink or source capabilities Thus they generate little or no noise of their own while providing a low resistance path for an external driver The output enable OE input can be used to disable the device so that the busses are effectively isolated 11 2 5 LVDS IO Low voltage differential signaling LVDS is a signaling method used for high speed transmission of binary data over copper It is well recognized that the benefits of balanced data transmission begin to outweigh the costs over single ended techniques when the signal transmission times approach 10 ns This represents signaling rates of about 30 Mbps or clock rates of 60 MHz in single edge clocking systems and above LVDS is defined in the TIA EIA 644 standards Connector 2 is Mini D Ribbon MDR connector 50 pin manufactured by 3M used
195. vision of the Xilinx tools so please be aware of minor differences 1 The DN6000K10 must be powered with the Xilinx JTAG cable connected to header J7 and the other end to a parallel port on the PC 2 Download the latest programming file for the Configuration FPGA from the Dini Group website filename 5 http www dinigroup com 3 RuniMPACT From the Windows START menu choose PROGRAMS Xilinx ISE 6 Accessories gt iMPACT 4 Select the Configure Devices option and proceed by clicking the NEXT button DN6000K10 User Guide www dinigroup com 41 PROGRAMMING CONFIGURING THE HARDWARE Operation Mode Selection x What do you want do first C Prepare Configuration Files C Load Configuration File cdf 5 Select the Boundary Scan Mode option and proceed by clicking the NEXT button OOO wantto configure device Boundary Scan Mode C Slave Serial Mode C SelectMAP Mode Desktop Configuration Mode lt Back Cancel Help 6 Select the Automatically connect to cable and identify Boundary Scan chain option and proceed by clicking the NEXT button DN6000K 10 User Guide ww w dinigroup com 42 PROGRAMMING CONFIGURING THE HARDWARE Boundary Scan Mode Selection 7 Ifthe process was successful the following window will appear Boundary Scan Chain Contents Summary 8 Click OK button 9 Enter the location of the PR
196. with your synplicity install directory This is usually of the form C Program Files Synplicity synplify XX where XX is the version number like synplify 76 for synplify version 7 6 The following directories must be in your Path environment vatiable XILINX bin nt EDKP enu Npowetpc eabiNntVbin XILINX_EDK xyewin bin SYNPLICITY bin At the bottom of each prj file in the synthesis directory is a line with the format option include_path Add the path SYNPLICITY lib xilinx to this line if it is not already there DN6000K 10 User Guide ww w dinigroup com 38 INTRODUCTION THE SOFTWARE TOOLS 2 Getting More Information 2 1 Printed Documentation The printed documentation as mentioned previously takes the form of a Virtex II Pro datasheet and a DN6000K10 User Guide 2 2 Electronic Documentation Multiple documents and datasheets have been included on the CD 2 3 Online Documentation There is a public access site that can be found on the Dini Group web site at http www dinigroup com DN6000K 10 User Guide ww w dinigroup com 39 PROGRAMMING CONFIGURING THE HARDWARE Chapter Programming Configuring the Hardware This chapter details the programming and configuration instructions for the DN6000K10 1 Programming the Configuration FPGA Note The Configuration FPGA PROM only needs to be programmed when an update is required Code updates will
197. y scan system testing 8 1 CPU Debug External debug mode can be used to alter normal program execution It provides the ability to debug system hardware as well as software The mode supports multiple functions starting and stopping the processor single stepping instruction execution setting breakpoints as well as monitoring processor status Access to processor resources is provided through the CPU Debug port The PPC405 JTAG Joint Test Action Group Debug port complies with IEEE standard 1149 1 1990 IEEE Standard Test Access Port and Boundary Scan Architecture This standard describes a method for accessing internal chip resources using a four signal or five signal interface The PPC405 JTAG Debug port supports scan based boatd testing and is further enhanced to support the attachment of debug tools These enhancements comply with the IEEE 1149 1 specifications for vendor specific extensions and are compatible with standard JTAG hardware for boundary scan system testing The PPC405 JTAG debug port supports the four required JTAG signals TMS TDI and TDO It also implements the optional TRST signal The frequency of the JTAG clock signal can range from 0 MHz DC to one half of the processor clock frequency The JTAG debug port logic is reset at the same time the system is reset using TRST When TRST is asserted the JTAG TAP controller returns to the test logic reset state Refer to the PPC405 Processor Block Manual for m

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