Home

Programming User`s Manual

1. TABLE 5 1 MCU INSTRUCTION TABLE CONTINUED 2 OF 5 Address Hex Number of Number of Flags Mnemonic Explanation Mode n Opcode Machine Cycles Bytes Affected BHS Branch if higher or same REL 24 3 O SS Branch if accumulator is higher or same as memory C 0 BIH Branch if interrupt line is high REL 2F 3 e ell Sa BIL Branch if interrupt line is low REL 2E 3 A See BIT Tests bits in memory A M IMM A5 2 2 NZ logical compare DIR B5 3 2 EXT C5 4 3 IX F5 3 1 IX1 E5 4 2 IX2 D5 5 3 BLO Branch if lower REL 25 3 2 Branch if accumulator is lower Branch on BLS Branch if low or same REL 23 3 2 Branch if accumulator is lower than or equal to memory BMC Branch if interrupt REL 2C 3 2 a a mask bit is clear BMI Branch if minus branch REL 2B 3 2 onN 1 BMS Branch if interrupt REL 2D 3 Z ass mask bit is set Branch on 1 BNE Branch if not equal REL 26 3 2 ol Branch onZ 0 BPL Branch if plus REL 2A 3 2u oe Branch on N 0 BRA Branch always REL 20 3 2 BRN Branch never REL 21 3 Q2 BRCLR Branch if bit n is clear BTB 1 2n 5 3 C BRSET Branch if bit n is set BTB 2n 5 3 C BSET Set bit n BSC 10 2n 5 2 BSR Branch to subroutine REL AD 6 2 CLC Clear carry flag INH 98 2 1 0 0 gt C CLI Clear interrupt mask INH 9A 2 0 bit 0 gt I CLR Clear INH A 4F 3 1 01 INH X 5F 3 1 DIR 3F 5 2 IX 7F 5 1 IX1 6F 6 2 2003 Silicon Sto
2. TABLE 5 1 MCU INSTRUCTION TABLE 1 OF 5 Address Hex Number of Number of Flags Mnemonic Explanation Mode n Opcode Machine Cycles Bytes Affected ADC Add memory to accumulator IMM AQ 2 2 H NZC with carry A M C gt A DIR B9 3 2 EXT C9 4 3 IX F9 3 1 IX1 E9 4 2 IX2 D9 5 3 ADD Add memory to accumulator IMM AB 2 2 H NZC A M gt A DIR BB 3 2 EXT CB 4 3 IX FB 3 1 IX1 EB 4 2 IX2 DB 5 3 AND AND memory with IMM A4 2 2 NZ accumulator DIR B4 3 2 A amp M gt A EXT C4 4 3 IX F4 3 1 IX1 E4 4 2 IX2 D4 5 3 ASR Shift right one bit INH A 47 3 1 NZC accumulator or memory INH X 57 3 1 b0 gt C DIR 37 5 2 b7 held constant IX 77 5 1 IX1 67 6 2 ASL same as LSL INH A 48 3 1 NZC Shift left one bit INH X 58 3 1 accumulator or memory DIR 38 5 2 b7 gt C IX 78 5 1 0 gt b0 IX1 68 6 2 BCC Branch on carry clear REL 24 3 23 eases Branch on C 0 BCLR Clear bit n BSC 114 2n 5 25 24 poe BCS Branch on carry set REL 25 3 2 Branch on C 1 BEQ Branch on result zero REL 27 3 2 Branch on Z 1 BHCC Branch if half carry clear REL 28 3 2 aS Branch on H 0 BHCS Branch if half carry set REL 29 3 2 Branch on H 1 BHI Branch if higher REL 22 3 2 Branch if accumulator is higher than memory unsigned 2003 Silicon Storage Technology Inc S74004 00 000 4 03 SST65P542R Programming Reference Manual
3. O Silicon Storage Technology Inc Programming User s Manual Remote Controller SST65P542R 2003 Silicon Storage Technology Inc The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology Inc S74004 00 000 4 03 SoftPartition is a trademark of Silicon Storage Technology Inc These specifications are subject to change without notice SST65P542R 7 Programming Reference Manual TABLE OF CONTENTS 10 INTRODUCTION 2 00 00 ofa a it Pe oe wide ree 4 2 0 BLOCK DIAGRAM isis care nce buss ee ice ee ees yee is ec ete on gcc te ea ed 5 3 0 PINCASSIGNMENT Swe he bd di diet See a ea eek ed oe Bed es 6 4 0 MEMORY ORGANIZATION ooo 7 5 0 MCU CORE AND INSTRUCTION SET 0 0000 c cect eens 8 5 1 Registers and Control Bit Assignments 00 0c ects 8 DM ACCUMUIALOr A aiuto city et at SA AN Seen eh a RIN Rk oa al ti Sot 9 5 1 2 Index Register X o cessa t E E E nents 9 5 1 3 Program Counter PO oooooccccoc tenets 9 5 1 4 Stack Pointer SP aiea aa e e e a tte tee eee 9 5 1 5 Processor Status Word PSW oooooocccccccocoo ene 10 5 2 Addressing Modes ii 42 io o a a ee A 10 5 2 1 Inherent INF eoeta ea ed E 10 5 2 2 Immediate IMM 2 00 ce ee A E nee 10 529 Direct BIR A Gy Be ae ee ee ee gs 11 524 Extended EXT A A ae A At A as 11 5 2 5 Indexed No Offset IX oooooooooooco eee tees 11 5 2 6 Indexed 8 bit Offset IX1 0 0 0 cee tne 11 5 2 7 Indexed 16 bit
4. 4004 F13 4 FIGURE 12 3 EXTERNAL FLASH BYTE PROGRAM ALGORITHM FOR EXTERNAL FLASH PROGRAMMING MODE Note Please refer to the SST65P542R data sheet for more information 2003 Silicon Storage Technology Inc 37 S74004 00 000 4 03 SST65P542R Programming Reference Manual Chip Erase Command Sequence Load data AAH Address 1555H Load data 55H Address 2AAAH Load data 80H Address 1555H Load data AAH Address 1555H Load data 55H Address 2AAAH Load data 10H Address 1555H Wait for End of Erase TSCE RY BY Chip erased to FFFFH Sector Erase Command Sequence Load data AAH Address 1555H Load data 55H Address 2AAAH Load data 80H Address 1555H Load data AAH Address 1555H Load data 55H Address 2AAAH Load data 30H Address SAx Wait for End of Erase TSE RY BY Sector erased to FFFFH 4004 F15 3 FIGURE 12 4 CHIP SECTOR ERASE COMMAND SEQUENCE FOR EXTERNAL FLASH PROGRAMMING MODE Note Please refer to the SST65P542R data sheet for more information 2003 Silicon Storage Technology Inc S74004 00 000 4 03 38 SST65P542R Programming Reference Manual 13 0 PACKAGING DIAGRAMS Pin 1 Identifier 23 gt 30 0 4 E Note 1 Complies with JEDEC publication 95 MS 013 AE dimensions although some dimensions may be more stringent 2 All linear dimensions are in millimeters min max
5. Meanwhile the other counter is enabled for counting Assuming that the high time counter is currently active The carrier output will be high and remand high until it reaches the high time register value Then the carrier will be driven low and the low time counter is activated The carrier output will be low and remand low until it reaches the low time register value Then the carrier will be driven high and the high time counter is activated The cycle repeats automatically generating a periodic carrier signal that is feed into the modulator block The lowest frequency maximum period and highest frequency minimum period which can be generated are defined as fmax fose 2x1 HZ fmin foso 2x 28 1 Hz In the general case the carrier generator output frequency is fout fosc Highcount Lowcount Hz where 0 lt Highcount lt 64 and 0 lt Lowcount lt 64 The duty cycle of the carrier signal is Highcount Duty cycle ____ ve Highcount Lowcount 2003 Silicon Storage Technology Inc S74004 00 000 4 03 29 SST65P542R 7 Programming Reference Manual 11 1 2 Carrier Generator Data Registers CHR1 CLR1 CHR2 and CLR2 There are two sets of Carrier Generator Data Registers Primary and secondary Each set contains one high time register CHR1 CHR2 and one low time register CLR1 CLR2 as shown below Carrier Data Register CHR1 Address Read Write Reset 0010H
6. 28 s0i 2 soic SG 5 3 Coplanarity 0 1 05 mm 4 Maximum allowable mold flash is 0 15mm at the package ends and 0 25mm between leads 28 PIN SMALL OUTLINE INTEGRATED CIRCUIT SOIC SST PACKAGE CODE SG Silicon Storage Technology Inc 1171 Sonora Court Sunnyvale CA 94086 Telephone 408 735 9110 Fax 408 735 9036 www SuperFlash com or www sst com 2003 Silicon Storage Technology Inc 39 S74004 00 000 4 03
7. MCU core registers the instruction set and the addressing modes 5 1 Registers and Control Bit Assignments The MCU contains five registers as shown in the programming model of Figure 5 1 The interrupt stacking order is shown in Figure 5 2 PROGRAM COUNTER PCL STACK POINTER 00000000 11 ACCUMULATOR INDEX REGISTER PSW REGISTER Unused Unused Unused Half Carry Interrupt Disable Negative Zero Carry 4004 F01 4 FIGURE 5 1 PROGRAMMING MODEL 2003 Silicon Storage Technology Inc S74004 00 000 4 03 SST65P542R Programming Reference Manual o Unstacking increasing address ACCUMULATOR A INDEX REGISTER X Stacking decreasing address 4004 F02 3 FIGURE 5 2 STACKING ORDER Stacking decreases memory address and unstacking Return increases memory address 5 1 1 Accumulator A The accumulator is a general purpose 8 bit register used to hold operands and results of an arithmetic calculation or data manipulations 5 1 2 Index Register X The index register is an 8 bit register which can contain the indexed addressing value used to create an effective address The index register may also be used as a temporary storage area 5 1 3 Program Counter PC The program counter is a 16 bit register which contains the address of the next byte to be fetched 5 1 4 Stack Pointer SP The stack pointer is a 16 bit register which contains the address of the next free l
8. Offset IX2 0 0 0 ttt tees 11 5 2 8 Relative REE koana vaso eed ted i poe teed Sade deeds gale dead gad i ea ae 12 5 2 9 Bit Set Clear BSC aiiai taam a ha aai tte ete 12 S210 Bit test and branch BT Bjeri oy peed eet tang al tara duties Ang 12 S Ss lASTUCION Set maid eho ee tern Been y eG Paes Waele eed cele ited Se eal Tarun eee 2 13 6 0 I O REGISTERS DEFINITION ooo 19 LO INTERRUPT Siicss otic hese kee Rated pee E ee eo ee Maret oa ae Mee eee PRE ae Be 22 8 0 RESETS AND CLOCKS 30 ia ie ee eee pe aa ee eee Pee eee ees od 23 9 0 POWER DOWN MODES 00 0 0 nett 24 DA STOP MOES cette daa att ana 24 9 2 ADEE MOIS seur dd ra Pett a DA A AA A 24 2003 Silicon Storage Technology n 89 74004 00 000 4 03 SST65P542R Programming Reference Manual 10 0THE CORE TIMER dodran eaa A it di 25 10 1 Computer Operating Properly Watchdog Timer Control Register CWTC 26 10 2 Timer Control and Status Register TCSR oooococcccccc eee 26 10 2 1 Core Timer Overflow CTOFP o ooococccccocco eens 26 10 2 2 Real Time Interrupt Flag RTIF 0 0 0 0 cece ee 26 10 2 3 Timer Overflow Enable TOFE 0 0 0 0 eee eens 26 10 2 4 Real Time Interrupt Enable RTIE 0 0 cee 26 10 2 5 Timer Overflow Flag Clear TOFC 0 000 c cece teen eens 26 10 2 6 Real Time Interrupt Flag Clear RTFC 0 00 00 c eect tenes 26 10 2 7 Real Time Interrupt Rate Select RT1 RTO
9. by reset 0 Extended space disabled 1 Extended space enabled BASE Baseband Enable Setting this bit to 1 disables the carrier generator and forces the carrier output to high The modulator output will be force to 1 for the duration of the mark period and force to 0 for the duration of a space period This bit should not be written to during a transmission This bit is cleared by reset 0 Baseband disabled 1 Baseband enabled MODE Mode Select This bit should not be changed during a transmission operation This bit is cleared by reset i e default Time mode 0 CMT operates in Time mode 1 CMT operates in FSK mode IE Interrupt Enabled Setting this bit to 1 will enable interrupt request send to MCU when EOC is set 0 CPU interrupt disabled 1 CPU interrupt enabled MCGEN Modulator and Carrier Generator Enable Setting this bit to 1 will enable the carrier generator and modulator Once enabled the carrier generator and modulator will function continuously To prevent spurious operation the user should initialize all data and control registers before enabling the carrier generator and modulator When this is set to 0 the current modulator cycle will be allowed to be completed and the modulator output will be forced to low This bit is cleared by reset 0 Modulator and carrier generator disabled 1 Modulator and carrier generator enabled 2003 Silicon Storage Technology Inc S74004 00 000 4 03 34 SST65P542R Programming Refe
10. can be used for various timing related functions including a software input capture Extended time periods can be achieved using the Timer Overflow function to increment a temporary RAM storage location there by simulating a 16 bit or larger counter Core Timer Counter Register CTCR Address 0009H Bit 7 6 5 4 3 2 1 Bit O Read D7 D6 D5 D4 D3 D2 D1 DO Write Xx Xx Xx Xx Xx Xx Xx Xx Reset 0 0 0 0 0 0 1 1 10 4 COP Watchdog Timer CWT Reset The CWT objective is to prevent the device to become stuck or locked up The COP Watchdog Timer CWT function is achieved by using the output of the RTI circuit and further dividing by 8 The minimum reset rates are listed in Table 10 1 If the CWT circuit times out an internal reset is generated This internal reset is equivalent to RESET pin reset To clear the CWT write OOH to address 3FFOH When CWT is cleared only the final divide by eight output of the RTI is cleared 10 5 Timer During IDLE Mode The MCU clock is stopped during IDLE mode but the timer remains active If interrupts are enabled a timer inter rupt will cause the processor to exit IDLE mode 2003 Silicon Storage Technology Inc S74004 00 000 4 03 27 SST65P542R r Programming Reference Manual 11 0 CARRIER MODULATOR TRANSMITTER CMT The carrier modulator transmitter CMT module is tailored for the IR remote controller applications This module is built by hardware with
11. contained in the two bytes following the opcode byte Instructions with extended addressing mode are capable of referencing arguments anywhere in mem ory with a single three byte instruction EA PC 1 PC 2 PC lt PC 3 Address bus high byte lt PC 1 Address bus low byte lt PC 2 5 2 5 Indexed No Offset IX In the indexed no offset addressing mode the effective address of the argument is contained in the 8 bit index reg ister This addressing mode can access the first 256 memory locations These instructions are only one byte long This mode is often used to move a pointer through a table or to hold the address of a frequently referenced RAM or I O location EA X PC lt PC 1 Address bus high byte lt 0 Address bus low byte lt X 5 2 6 Indexed 8 bit Offset IX1 In the indexed 8 bit offset addressing mode the effective address is the sum of the contents of the unsigned 8 bit index register and the unsigned byte following the opcode Therefore the operand can be located anywhere within the lowest 511 memory locations This addressing mode is useful for selecting the mt element in an n element table EA X PC 1 PC lt PC 2 Address bus high byte K Address bus low byte lt X PC 1 where K the carry from the addition of X and PC 1 5 2 7 Indexed 16 bit Offset IX2 In the indexed 16 bit offset addressing mode the effective address is the sum of the contents of the unsigned 8 bit index registe
12. for controlling multiple appliances The configura tions are either programmed at the factory during the manufacturing process or updated through a web download procedure using the serial interface Using the SuperFlash nonvolatile memory technology the SST65P542R enhances the functionality of the conven tional universal remote controller devices by integrating multiple functions of a remote controller system in a single chip solution The built in LED I O ports can directly drive LED indicators The IR transmitter port drives signals to the infrared transmitter which in turn remotely controls appliances The SoftPartition flash memory architecture allows seamless partition of the program code protocol tables and user data in the small granularity of 128 Byte sectors The small sector size and fast Erase Write time greatly increase the time and power efficiency when altering the contents of the flash memory The embedded controller is designed and manufactured using SST s patented and proprietary SuperFlash EEPROM technology SST s highly reliable SuperFlash technology provides significant advantages over conventional flash memory tech nology These advantages translate into significant overall cost savings and reliability benefits for customers PRODUCT FEATURES 8 bit MCU Core Enhanced 6502 Microprocessor Megacell e 4MHz Typical Oscillator Clock Frequency 8 MHz maximum clock frequency e 16 KByte of user programmable flash m
13. programmable ability for a wide variety of encoding schemes The incorporated hardware can off load MCU to perform lengthy time consuming tasks associated with code generation It s designed to han dle most of the protocols When a special protocol is needed the CMT modulator can be disabled A CMT register can be used to change the state of the infrared out pin IRO directly The CMT module consists of three blocks carrier generator modulator and transmitter output The block diagram is shown in Figure 11 1 Carrier Output Modulator Output fosc Primary Secondary Select Transmitter Polarity Carrier Generator Modulator Divide by two 4004 F20 0 FIGURE 11 1 CARRIER MODULATOR TRANSMITTER MODULE BLOCK DIAGRAM 11 1 Carrier Generator The carrier generator has a resolution of 500ns time steps with a 2MHZ fosc The high and low times of the carrier signal can be programmed by user independently to determine both period and duty cycle of carrier signal The period of carrier signal can be from 1 us 1MHz to 64 us 15 6KHz in 500ns increments The duty cycle resolution is depend on the number of counts required to complete the carrier period These counts are split between high and low times of the carrier signal The longer the carrier signal period the lower carrier signal frequency the higher the resolution as a percentage of the total period of carrier signal duty cycle In
14. 0 0 ccc ee eens 27 10 3 Core Timer Counter Register CTCR 0 0 0 e enna 27 10 4 COP Watchdog Timer CWT Reset o ooccccccoc 27 10 5 Timer During IDLE Mode 0 cee tet R EA 27 11 0 CARRIER MODULATOR TRANSMITTER CMT 0 000 cece teeta 28 11 1 Carrier Generators 2 4 A ea a ha we PE Sek a ER Qe wha ey 28 Test Time Counter sis 3 be eis ake ha 3 WA tai es Shido tebe hen BUN A es ETE lhl Ai 29 11 1 2 Carrier Generator Data Registers CHR1 CLR1 CHR2 and CLR2 05 30 Ti MOU lato lies ce ee erated A hed ae Ae Dah Bal RECA DON AA haan bea ewe 31 VAs Ad TIMES A O e ara 31 11 22 FORMOE usina ai A A ama E gaia de AA A Si and dsc boi ey 32 11 2 3 Extended Space Operation oooo oooooor eee 33 11 2 4 End Of Cycle EOC Interrupt 0 0 0 0 0 tte eee 33 11 2 5 Modulator Period Data Register MDR1 MDR2 and MDR3 2 4 35 12 0 PROGRAMMING FLOW DIAGRAM 2 0 0 0000 ccc tenet eens 36 13 0 PACKAGING DIAGRAMS 1 0 0 0 0c nent eens 39 2003 Silicon Storage Technology ING 8 74904 00 000 4 08 SST65P542R 7 Programming Reference Manual 1 0 INTRODUCTION The SST65P542R is a member of SST s 8 bit application specific microcontroller family targeting IR remote con troller applications The SST65P542R microcontroller provides high functionality to infrared remote controller products The device offers flexibility to store different remote control configurations
15. 3 CMT OPERATION IN TIME MODE 11 2 2 FSK Mode When the modulator operates in FSK mode the modulation mark and space periods are counted in multiple of car rier clocks Space period can be zero The modulator provides a signal to the carrier generator to toggle between primary and secondary data register values whenever the modulator mark period expires The space period pro vides an interpulse gap no carrier but if SBUFF 0 then the modulator and carrier generator will switch between carrier frequencies without a gap or any carrier glitches zero space Here are equations to calculate mark and space period for FSK mode MBUFF Ela fog Tmark ec SBUFF sec fog Where fog is the frequency output from the carrier generator Setting the DIV2 bit in the MCSR will double mark and space times Tspace 2003 Silicon Storage Technology Inc S74004 00 000 4 03 32 SST65P542R Programming Reference Manual 11 2 3 Extended Space Operation In either time or FSK mode the space period can be made longer than the maximum possible value of SBUFF Set ting the EXSPC bit in the MCSR will force the modulator to convert the subsequent modulation periods consisting of entirely the space periods with no mark periods Clearing EXSPC will return the modulator to standard operation at the beginning of the next modulation period Here is the equation to calculate the length of an extended space in time mode SBUFF1 MBU
16. 5P542R Programming Reference Manual 4004 F10 1 FIGURE 3 1 PIN ASSIGNMENTS FOR 28 PIN SOIC TABLE 3 1 PIN DESCRIPTIONS Pins Symbol Type Name and Functions 16 9 PA 7 0 1 01 Port A The state of any pin in Port A is software programmable and every line is configured as an input during any external reset 8 1 PB 7 0 I O with Port B The state of any pin in Port B is software programmable and every line is configured as internal an input during any external reset Each I O line contains a programmable interrupt pull up for pull ups keyscan PB 7 is used as a serial interface data line when the serial interface is enabled 20 17 PC 3 0 1 0 Port C Every pin in Port C is a high current pin and its state is software programmable All lines are configured as inputs during any external reset 23 IRO O IRO Suitable for driving IR LED biasing logic the IRO pin is the high current source and sink output of the carrier modulator transmitter subsystem Default state is low after any external reset 21 LPRST Low Power Reset An active low pin LPRST function sets MCU to low power reset mode The MCU once in low power reset mode is held in reset with all processor clocks and crystal oscillator halted An internal Schmitt trigger is included in the LPRST pin to improve noise immunity 24 RESET Reset By setting the RESET pin low the MCU is reset to a default st
17. Bit 7 6 5 4 3 2 1 Bit 0 IROLN CMTPOL PH5 PH4 PH3 PH2 PH1 PHO 0 0 U U U U U U U Unaffected Carrier Data Register CLR1 Address Read Write Reset 0011H Bit 7 6 5 4 3 2 1 Bit 0 IROLP 0 PL5 PL4 PL3 PL2 PL1 PLO 0 0 U U U U U U U Unaffected Carrier Data Register CHR2 Address Read Write Reset 0012H Bit 7 6 5 4 3 2 1 Bit 0 0 0 SH5 SH4 SH3 SH2 SH1 SHO 0 0 U U U U U U U Unaffected Carrier Data Register CHR2 Address Read Write Reset 0013H Bit 7 6 5 4 3 2 1 Bit 0 0 0 SL5 SL4 SL3 SL2 SL1 SLO 0 0 U U U U U U U Unaffected PHO PH5 and PLO PL5 Primary Carrier High PHO PH5 and Low PLO PL5 Time value These bits contain the number of input clocks for the carrier high and low time periods When operating in timer mode this register pair is always selected When operating in FSK mode the modulator alternately selects this register pair and the secondary register pair The primary carrier high and low time values are undefined out of reset These bits must be written to nonzero values before the carrier generator is enabled to avoid spurious results SHO SH5 and SLO SL5 Secondary Carrier High SHO SH5 and Low SLO SL5 Time Value These bits contain the number of input clocks for the carrier high and low time periods When operating in time mode this register pair i
18. FF2 1 SBUFF2 MBUFFn 1 SBUFFn x Gee Texspace r Cc osc Where the subscripts 1 2 n refer to the modulation periods that elapsed while the EXSPC bit was set Here is the equation to calculate the length of an extended space in FSK mode SBUFF1 MBUFF2 1 SBUFF2 4 MBUFFn 1 SBUFFN sec fog Where feg is the carrier frequency output from the carrier generator Texspace Please note that it is an invalid operation to use extended space EXSPC 1 at the beginning of a transmission e do not set extended space EXSPC to 1 and change MCGEN from 0 to 1 11 2 4 End Of Cycle EOC Interrupt At the end of each modulation cycle when a match of SREG occurs the end of cycle EOC flag is set and an interrupt will be issued to the CPU if the interrupt is enabled IE 1 Meanwhile the counter is reloaded from MBUFF The EOC interrupt provides a means for the user to reload new mark space values into the MBUFF and SBUFF registers As the EOC interrupt is coincident with reloading of the counter and SREG the previous MUBFF and SBUFF contents has been loaded into the counter and SREG respectively The EOC interrupt service routine ISR can update both mark MBUFF and space SBUFF period values with a new value for the next modulation period The EOC flag must be cleared within the ISR to prevent anther interrupt being generated after exiting the ISR This EOC flag is cleared by a read of the MCSR follow by an acc
19. ITIONS OF I O REGISTERS 1 OF 2 Addr Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito 0000H Port A Data Register PA7 PA6 PA5 PA4 PA3 PA2 PA1 PAO 0001H Port B Data Register PB7 PB6 PB5 PB4 PB3 PB2 PB1 PBO 0002H Port C Data Register X X X X PC3 PC2 PC1 PCO 0003H Reserved X X X X X X Xx Xx 0004H Port A Data DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRAO Direction Register 0005H Port B Data DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRBO Direction Register 0006H Port C Data X X X X DDRC3 DDRC2 DDRC1 DDRCO Direction Register 0007H Reserved X X X X X Xx Xx Xx 0008H Core Timer Control Sta CTOF RTIF TOFE RTIE TOFC TRFC RT1 RTO tus Register 0009H Core Timer Counter Xx Xx Xx Xx Xx Xx Xx Xx Register 000AH Port B Interrupt INPRB7 INPRB6 INPRB5 INPRB4 INPRB3 INPRB2 INPRB1 INPRBO Control Register 000BH SuperFlash PREN MEREN SEREN Xx PROG MERA SERA Xx Function Register 000CH Port B Pull up X X X X X Xx PU1 PUO Control Register 000DH CWT Control Register Xx Xx Xx Xx Xx Xx Xx CWT_EN 000EH Serial Interface Xx Xx Xx Xx Xx Xx TR Xx Control Register 000FH Serial Interface Xx Xx Xx Xx Xx LSBF Xx Xx Control Register 0010H Carrier Generator High IROLN CMT PH5 PH4 PH3 PH2 PH1 PHO Data Register CHR1 POL 0011H Carrier Generator Low IROLP X PL5 PL4 PL3 PL2 PL1 PLO Data R
20. NTINUED 5 OF 5 Address Hex Number of Number of Flags Mnemonic Explanation Mode n Opcode Machine Cycles Bytes Affected RTS Return from subroutine INH 81 6 A a Se Pc T PC 1 PC SBC Subtract memory IMM A2 2 2 NZC from accumulator DIR B2 3 2 with borrow EXT C2 4 3 A M C gt A IX F2 3 1 IX1 E2 4 2 IX2 D2 5 3 SEC Set carry flag INH 99 2 1 1 1 gt C SEI Set interrupt mask bit INH 9B 2 1 1 1 STA Store accumulator in memory DIR B7 4 2 NZ A M EXT C7 5 3 IX F7 4 1 IX1 E7 5 2 IX2 D7 6 3 STX Store index X in memory DIR BF 4 2 NZ X M EXT CF 5 3 IX FF 4 1 IX1 EF 5 2 IX2 DF 6 3 SUB Subtract memory IMM AO 2 2 NZC DIR BO 3 2 EXT CO 4 3 IX FO 3 1 IX1 EO 4 2 IX2 DO 5 3 SWI Software interrupt INH 83 10 1 1 TAX Transfer accumulator INH 97 2 1 to index X A gt X TST Test for negative or INH A 4D 3 1 NZ zero INH X 5D 3 1 DIR 3D 4 2 IX 7D 4 1 IX1 6D 5 2 TXA Transfer index X to INH 9F 2 1 accumulator X gt A T5 1 5 4004 2003 Silicon Storage Technology Ine 57400400000 4 03 17 SST65P542R 7 Programming Reference Manual Description The following is the description of each instruction and the operation during the execution of each instruction The key for MCU instructions is as follows The first three letters are the opcode the actual mnemonic of the instruction The possible addressing modes are indicated by th
21. Register 0001H Port B Data Register 0002H Port C Data Register 0003H Reserved 0004H Port A Data Direction Register 0005H Port B Data Direction Register 0006H Port C Data Direction Register 0007H Reserved 0008H Core Timer Control Status Register 0009H Core Timer Counter Register 000AH Port B Interrupt Control Register 000BH SuperFlash Function Register SFFR 000CH Port B Pull up Control Register 000DH COP Watchdog Timer Control Register CWTC 000EH Serial Interface Control Register SICON_TR 000FH Serial Interface Control Register SICON_LSBF 0010H Carrier Generator High Data Register1 CHR1 0011H Carrier Generator Low Data Register1 CLR1 0012H Carrier Generator High Data Register2 CHR2 0013H Carrier Generator Low Data Register2 CLR2 0014H Modulator Control and Status Register MCSR 0015H Modulator Data Register1 MDR1 0016H Modulator Data Register2 MDR2 0017H Modulator Data Register3 MDR3 0018H Power Save Control Register PSCR 0019H Serial Interface Control Register SICON_SI 001AH Serial Interface Data Register SIDAT 001BH Serial Interface Status Register SISTA 001CH Serial Interface Baud Rate Register SIBDR 001DH Serial Interface Control Register SICON_AP 001EH Serial Interface Control Register SICON_ENSI 001FH IR Input Control Register T6 1 3 4004 2008 Silicon Storage Technology n S7ADOA 00 000 4 03 SST65P542R A Programming Reference Manual TABLE 6 2 BiT DEFIN
22. STOP mode The bit will not be affected 9 2 IDLE Mode To enter IDLE Mode write 02H to Power Saving Control Register 0018H The IDLE Mode consumes more power than the STOP Mode Upon completion of the Write operation to the PSCR all modules remain active except MCU clock processing is suspended Any interrupt or reset will cause the MCU to exit IDLE mode When an interrupt is asserted interrupt will be serviced if mask bit I bit is clear otherwise interrupt will not be ser viced MCU will resume operation to the next instruction byte following the IDLE mode enabling Write operation The IDLE bit will be set to 1 when the device has been brought out of IDLE mode The bit will not be affected 2003 Silicon Storage Technology Inc S74004 00 000 4 03 24 SST65P542R Programming Reference Manual o 10 0 THE CORE TIMER The core timer is a 14 stage multifunctional ripple counter Its features include Timer Overflow TO Power On Reset POR Real Time Interrupt RTI and COP Watchdog Timer CWT The core timer operates as follows 1 The internal peripheral clock is divided by four driving an 8 bit ripple counter At any time the counter value can be read by accessing the Timer Counter Register TCR address 0009H 2 At the last stage of the counter a timer overflow is implemented This gives a possible interrupt rate of the internal peripheral clock E 1024 After three more stages the clock RTlout now E 4096
23. STRUCTION TABLE CONTINUED 4 OF 5 Address Hex Number of Number of Flags Mnemonic Explanation Mode n Opcode Machine Cycles Bytes Affected LDA Load accumulator IMM A6 2 2 NZ with memory DIR B6 3 2 M gt A EXT C6 4 3 IX F6 3 1 IX1 E6 4 2 IX2 D6 5 3 LDX Load index X with memory IMM AE 2 2 NZ M gt X DIR BE 3 2 EXT CE 4 3 IX FE 3 1 IX1 EE 4 2 IX2 DE 5 3 LSL same as ASL INH A 48 3 1 NZC Shift left one bit INH X 58 3 1 accumulator or memory DIR 38 5 2 b7 C IX 78 5 1 0 b0 IX1 68 6 2 LSR Shift right one bit INH A 44 3 1 0ZC memory or accumulator INH X 54 3 1 b0 gt C DIR 34 5 2 0 b7 IX 74 5 1 IX1 64 6 2 MUL Multiplication INH A 42 11 1 0 0 X A XA NEG Negate INH A 40 3 1 NZC Two s complement INH X 50 3 1 DIR 30 5 2 IX 70 5 1 IX1 60 6 2 NOP No operation INH 9D 2 1 ORA OR memory with IMM AA 2 2 NZ accumulator DIR BA 3 2 A M gt A EXT CA 4 3 IX FA 3 1 IX1 EA 4 2 IX2 DA 5 3 ROL Rotate one bit left INH A 49 3 1 NZC through carry memory INH X 59 3 1 or accumulator DIR 39 5 2 IX 79 5 1 IX1 69 6 2 ROR Rotate one bit right INH A 46 3 1 NZC through carry memory INH X 56 3 1 or accumulator DIR 36 5 2 IX 76 5 1 IX1 66 6 2 RSP Reset stack pointer INH 9C 2 1 RTI Return from interrupt PC P INH 80 9 1 2222 2003 Silicon Storage Technology Inc S74004 00 000 4 03 SST65P542R Programming Reference Manual TABLE 5 1 MCU INSTRUCTION TABLE CO
24. ate An internal Schmitt trigger is included in the RESET pin to improve noise immunity 28 OSC1 Oscillator 1 2 These 2 pins interface with external oscillator circuits 27 OSC2 O A crystal resonator a ceramic resonator or an external clock signal can be used 25 IRQ Interrupt Request The IRQ is negative edge sensitive triggered An internal Schmitt trigger is included in the IRQ pin to improve noise immunity 26 Vop Power Supply Supply Voltage 22 Vss Ground Circuit ground OV reference T3 1 5 4004 1 Input O Output 2003 Silicon Storage Technology Inc S74004 00 000 4 03 SST65P542R Programming Reference Manual 4 0 MEMORY ORGANIZATION The SST65P542R has a total of 64 KByte of addressable memory A memory map is shown in Figure 4 1 The memory consists of 32 Bytes of l O registers 352 Bytes of SRAM 16 KByte of user flash memory and 128 Bytes of user vectors 0180H Reset BFFFH Flash Memory 128 sectors 0000H 1 0 Registers 352 Bytes SRAM 001FH 0020H 017FH 0180H BFFFH CO00H 127 Sectors 128 Bytes per sector Flash Memory EF80H Read Protection FF7FH FF80H FFF4H Reset and Interrupt FFFFH Vectors 4004 F11 3 FFFFH FIGURE 4 1 MEMORY MAP 2003 Silicon Storage Technology Inc S74004 00 000 4 03 SST65P542R r Programming Reference Manual 5 0 MCU CORE AND INSTRUCTION SET This section provides a description of the
25. carrier generator block there are two sets of high and low times i e two set of carrier signal period frequency can be selected In normal mode subsequently referred to as time mode just one set will be used In FSK fre quency shift key mode the modulator selects the two sets of carrier frequency base on the data to be modulated to generate dual frequency FSK protocols without MCU intervention When the BASE bit in the modulator control and status register MCSR is set the carrier output to the modulator is held high continuously to allow for the gen eration of baseband protocols 2003 Silicon Storage Technology Inc 28 S74004 00 000 4 03 SST65P542R Programming Reference Manual o To enable carrier generator clocks the MCGEN bit in the MCSR must be set and the BASE bit in the MCSR must be cleared The block diagram is shown below Primary High Count Register Secondary High Count Register High Time Counter Carrier Output Primary Secondary Select ae Primary Low Count Register Secondary Low Count Register Low Time Counter 4004 F21 0 FIGURE 11 2 CARRIER GENERATOR BLOCK DIAGRAM 11 1 1 Time Counter The high or low time counter is a 6 bit up counter Only one counter is counting at a certain time After each incre ment the contents of the counter are compared with the appropriate high or low count value register When the value is reached the counter is reset and stopped
26. drives the real time interrupt circuit RTI The RTI circuit has three divider stages with a 4 1 selector The output of the RTI circuit is divided by eight This drives the CWT circuit O oa A O The Timer Control and Status register at location 0008H contains the RTI rate selector bits and the RTI and CTOF enable bits and flags Internal Bus a Internal Peripheral Clock E COP Clear Timer Counter Register TCR Eog 0009h E210 E 212 4 POR 5 Bit Counter c 215 c 214 c 213 c 212 RTI Select Circuit 1 Overflow Detect Circuit RTIouT Timer Control amp TCSR osn foro mne rore ave roro mro an wo Sats rs pp COP Watchdog Interrupt Circuit Timer 8 To Interrupt To Reset Logic Logic 4004 F12 5 Note 1 Internal Peripheral Clock is oscillator clock divided by two FIGURE 10 1 CORE TIMER BLOCK DIAGRAM 2003 Silicon Storage Technology Inc S74004 00 000 4 03 25 SST65P542R Programming Reference Manual 10 1 Computer Operating Properly Watchdog Timer Control Register CWTC Writing to CWT Control register QOODH can enable disable core timer CWT Control Register Address 000DH Bit 7 6 5 4 3 2 1 Bit O R Xx X X X X X CWT_EN Default 7 CWT_EN 1 CWT disabled 0 CWT enabled 10 2 Timer Control and Status Register TCSR The TCSR includes the timer interrupt flag the timer interrupt enable bits and the real time interrupt rate select bits Th
27. e letters following the opcode and they are as follows IMM immediate addressing INH A inherent addressing with respect to Accumulator INH X inherent addressing with respect to Index Register DIR direct addressing EXT extended addressing IX indexed addressing no offset IX1 indexed addressing with one byte offset IX2 indexed addressing with two byte offset BSC bit set clear BTB bit test and branch REL relative addressing The following abbreviations are used besides the ones used for addressing mode A accumulator C carry flag H half carry flag interrupt flag M memory N negative flag PC program counter PCL program counter lower byte PCH program counter higher byte SP stack pointer X index register Z zero flag OR function amp AND function A Exclusive OR function 22 load PSW from stack not affected Machine cycle is two oscillator clock cycles 2003 Silicon Storage Technology Inc S74004 00 000 4 03 SST65P542R Programming Reference Manual 6 0 I O REGISTERS DEFINITION The 32 Bytes of I O registers occupy address locations from 0000H to 001FH and include general purpose I O pin registers on chip peripheral control registers and SuperFlash Function Registers TABLE 6 1 I O REGISTER DESCRIPTIONS Address Location Register Description 0000H Port A Data
28. e table below shows the default value of each bit in the TCSR immediately after reset Timer Control and Status Register Address 0008H Bit 7 6 5 4 3 2 1 Bit O Read CTOF RTIF 0 0 TOFE RTIE RT1 RTO Write X X 2 TOFC RTFC Reset 0 0 0 0 0 0 1 1 10 2 1 Core Timer Overflow CTOF CTOF is a read only status bit set when the 8 bit ripple counter rolls over from FFH to OOH Writing a logical 1 to TOFC bit clears the CTOF Writing to CTOF has no affect Reset clears CTOF 10 2 2 Real Time Interrupt Flag RTIF The Real Time Interrupt circuit contains a 3 stage divider and a one of four choice selector The input frequency to the RTI is E 4096 and after three other divider stages allows a maximum interrupt period of 16 milliseconds at an internal peripheral clock rate of 2 048MHz RTIF is a read only status bit which is set when the output of the selected one of four divider stage goes active Clearing the RTIF is done by writing a logical 1 to RTFC Writing to RTIF has no affect Reset clears the RTIF bit 10 2 3 Timer Overflow Enable TOFE When the TOFE bit is set a MCU interrupt request is generated only if CTOF bit is set Reset clears this bit 10 2 4 Real Time Interrupt Enable RTIE When the RTIE bit is a set a MCU interrupt request is generated only if RTIF bit is set Reset clears this bit 10 2 5 Timer Overflow Flag Clear TOFC CTOF is cleared when logical 1 is written
29. efined as the address from which the argument for an instruction is fetched or stored The ten addressing modes of the processor are described below Parentheses are used to indicate contents of the location or register referred to For example PC indicates the contents of the location pointed to by the PC program counter An arrow indicates is replaced by and a colon indicates concatenation of two bytes 5 2 1 Inherent INH In the inherent addressing mode all the information necessary to execute the instruction is contained in the opcode Operations specifying only the index register or accumulator as well as the control instruction with no other arguments are included in this mode These instructions are one byte long 5 2 2 Immediate IMM In the immediate addressing mode the operand is contained in the byte immediately following the opcode EA PC 1 PC lt PC 2 2003 Silicon Storage Technology Inc S74004 00 000 4 03 SST65P542R Programming Reference Manual 5 2 3 Direct DIR In the direct addressing mode the effective address of the argument is contained in a single byte following the opcode byte Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two byte instruction EA PC 1 PC lt PC 2 Address bus high byte lt 0 Address bus low byte lt PC 1 5 2 4 Extended EXT In the extended addressing mode the effective address of the argument is
30. egister CLR1 0012H Carrier Generator High X X SH5 SH4 SH3 SH2 SH1 SHO Data Register 2 CHR2 0013H Carrier Generator Low Xx Xx SL5 SL4 SL3 SL2 SL1 SLO Data Register 2 CLR2 0014H Modulator Control and EOC DIV2 EIMSK EXSPC BASE MODE EOCIE MCGEN Status Register MCSR 0015H Modulator Data MB11 MB10 MB9 MB8 SB11 SB10 SB9 SB8 Register 1 MDR1 0016H Modulator Data MB7 MB6 MB5 MB4 MB3 MB2 MB1 MBO Register 2 MDR2 0017H Modulator Data SB7 SB6 SB5 SB4 SB3 SB2 SB1 SBO Register 3 MDR3 0018H Power Saving EN X X X X X STOP IDL Control Register PSCR 0019H Serial Interface Xx Xx Xx X Xx Xx Xx Sl Control Register X Reserved Recommended to write 0 to reserved bits for future compatibility T6 2 5 4004 2003 Silicon Storage Technology Ine S7404 00 000 4 03 20 SST65P542R Programming Reference Manual TABLE 6 2 BiT DEFINITIONS OF I O REGISTERS CONTINUED 2 OF 2 Addr Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito 001AH Serial Interface D7 D6 D5 D4 D3 D2 D1 DO Data Register 001BH Serial Interface Xx Xx S5 S4 S3 X X Xx Status Register 001CH Serial Interface Xx Xx Xx Xx F3 F2 F1 FO Baud Rate Register 001DH Serial Interface X X X X AP X X X Control Register 001EH Serial Interface X X X ENSI x x x X Control register 001FH IR Input Control X X X X Xx Xx IREN IRIN Register X Reserved Recommended to write 0 to reserved bits for future c
31. emory e 352 Bytes SRAM IR Input Pin for Learning Mode e Power down Modes Carrier Modulator Transmitter Supports Baseband Pulse Length Modulator PLM and Frequency Shift Keying FSK Core Timer Counter 14 stage multifunctional ripple counter Includes timer overflow POR RTI and CWT e General Registers Accumulator 8 bit Index Register 8 bit e Control registers Program Counter 16 bit Stack Pointer 16 bit 6 addressable bits Condition code register 8 bit Addressing modes supported 1 Immediate 3 Extended 5 Indexed no offset 7 Indexed 16 bit offset 9 Bit test and branch 2 Direct 4 Relative 6 Indexed 8 bit offset 8 Bit set clear 10 Inherent Data types supported 1 Bit data manipulation instructions 2 Byte data 2003 Silicon Storage Technology Inc S74004 00 000 4 03 SST65P542R Programming Reference Manual o 2 0 BLOCK DIAGRAM FUNCTIONAL BLOCK DIAGRAM Interrupt IRQ MCU Core 352K x8 SuperFlash EEPROM 16K x8 Carrier Modulator Transmitter Timer Counter Interrupt Real Time l l 1 Counter I Core Timer Counter COP Watchdog 4004 B2 5 2003 Silicon Storage Technology Inc S74004 00 000 4 03 3 0 PIN ASSIGNMENTS PBO OSC1 PB1 0SC2 PB2 1 VDD PB3 IRQ PB4 RESET PB5 IRO PB6 28 pin SOIC Vss PB7 LPRST PAO PC3 PA1 PC2 PA2 PC1 PA3 PCO PA4 PA7 PA5 PA6 SST6
32. ess of MDR2 or MDR3 If the EOC interrupt is not being used IE 0 the EOC flag need not be cleared Modulator Conirol and Status Register MCSR Address 0014H Bit 7 6 5 4 3 2 1 Bit 0 Read EOC ae DIV EIMSK EXSPC BASE MODE IE MCGEN rite Reset 0 0 0 0 0 0 0 0 Unimplemented Symbol Function EOC End Of Cycle status flag EOC is set when a match occurs between the logical complement of the counter contents and the SBUFF i e the end of the modulator cycle This flag is cleared by a read of the MCSR follow by an access of MDR2 or MDR3 The EOC flag is cleared by reset 0 Current modulation cycle in progress 1 End of modulator cycle 2003 Silicon Storage Technology Inc S74004 00 000 4 03 33 SST65P542R A Programming Reference Manual DIV2 Divide by two prescaler Setting this bit to 1 causes the modulator output to be timed at a twice slower clock i e doubled the mark and space time This bit should not be written to during a transmission This bit is cleared by reset 0 Divide by two prescaler disabled 1 Divide by two prescaler enabled EIMSK External Interrupt Mask The external interrupt mask bit is used to mask IRQ and port B interrupts This bit is cleared by reset 0 IRQ and port B interrupt enabled 1 IRQ and port B interrupt masked EXSPC Extended Space Enable For a description of the extended space enable bit see Extended Space Operation This bit is cleared
33. ier baseband In FSK mode the modulator counts carrier periods and providing a signal to switch the carrier generator between high low time register buffers to alternate between two carrier frequencies whenever a modulation period mark space counts expires When the modulator is enabled MCGEN 1 the space period register SREG is loaded with the contents of its buffer SBUFF the mark buffer register MBUFF is loaded into a 12 bit down counter and the modulator gate is opened for carry signal to pass through When this counter underflows the modulator gate is closed and the mod ulator output is forced to low The counter is continuously counting down and the logical complement of the con tents of the decrementing counter is compared with the SREG When a match is obtained the modulator control gate is opened the MBUFF is re loaded into the down counter and SREG is reloaded with the contents of SBUFF These cycles keep repeating until the modulator is disabled The current modulator cycle will be allowed to be com pleted and the modulator output will be forced to low When SREG 0 the match will happen immediately and no space period will be generated Some of FSK protocols that require successive bursts of different frequencies need to set SBUFF to 0 The 12 bit MBUFF and SBUFF registers are accessed through three 8 bit modulator period reg isters MDR1 MDR2 and MDR3 Bit 7 to bit O of the down counter can be read from 3FF2 Bit 11 to bit 8
34. ite bit in the first 256 locations of memory can be selectively set or cleared with a single two byte instruction EA PC 1 PC lt PC 2 Address bus high byte lt 0 Address bus low byte lt PC 1 5 2 10 Bit test and branch BTB The bit test and branch addressing mode is a combination of direct addressing and relative addressing mode The bit to be tested and its condition set or clear is included in the opcode The address of the byte to be tested is in the single byte immediately following the opcode byte EA1 The signed relative 8 bit offset in the third byte is sign extended and added to the PC if the specified bit is set or cleared in the specified memory location This single three byte instruction allows the program to branch based on the condition of any readable bit in the first 256 loca tions of memory The span of branch is from 125 to 130 from the opcode address The state of the tested bit is also transferred to the carry bit of the condition code register EA1 PC 1 PC lt PC 2 Address bus high byte 20 Address bus low byte PC 1 EA2 PC 3 PC 2 PC lt EA2 if branch taken otherwise PC lt PC 3 2003 Silicon Storage Technology Inc S74004 00 000 4 03 SST65P542R Programming Reference Manual 5 3 Instruction Set Table 5 1 summarizes the MCU instruction set A description of the instructions and an explanation of abbrevia tions follows the table on page 18
35. mation are not available externally Internal Processor Clock is half the frequency of OSC1 2 OSC1 line is not meant to represent frequency It is only used to represent time 3 The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence tp is 1 5tcyg minimum 4 The LPRST pin resets the CPU like RESET However 4064 clock cycles are counted before the reset vector address appears on the internal address bus FIGURE 8 1 RESET AND LPRST TIMING DIAGRAM 2003 Silicon Storage Technology Inc 23 S74004 00 000 4 03 SST65P542R 7 Programming Reference Manual 9 0 POWER DOWN MODES SST65P542R offers two modes to reduce system power consumption 9 1 STOP Mode To enter the STOP Mode write 01H to the Power Saving Control Register PSCR 0018H Upon completion of the Write operation to the PSCR the internal oscillator is turned off halting all internal processing including CMT and timer operations The microcontroller can be brought out of the STOP Mode by external Port B interrupts LPRST or RESET When external interrupt is asserted either on IRQ or Port B pins when Port B interrupt is enabled interrupt will be serviced if mask bit I bit is clear otherwise interrupt will not be serviced MCU will resume operation to the next instruction byte following the STOP mode enabling Write operation The STOP bit will be set to 1 when the device has ben brought out of
36. n idle mode and not operating If there has one pending CMT interrupt when idle mode is entered the pending interrupt will be served and pull the chip out of idle mode Pending or new CMT interrupt will bring the chip out of idle mode 11 2 5 3 Stop Mode Operation During stop mode the CMT halts all operation and no registers are affected 2003 Silicon Storage Technology Inc S74004 00 000 4 03 35 SST65P542R Programming Reference Manual 12 0 PROGRAMMING FLOW DIAGRAM Write 88H to address OBH Write data to the flash memory address to be programmed MCU halt for program complete done Next instruction 4004 F16 2 FIGURE 12 1 IN APPLICATION PROGRAMMING Chip Erase Sector Erase Write 44H to address OBH Write 22H to address OBH Write FFH to address COOOH Write FFH to sector address to be erased MCU halt for Erase complete MCU halt for Erase complete done done Next instruction Next instruction After Chip Erase all flash memory contents will be erased MCU should execute Chip Erase program in SRAM only 4004 F17 3 FIGURE 12 2 IN APPLICATION ERASE 2003 Silicon Storage Technology Inc S74004 00 000 4 03 36 SST65P542R Programming Reference Manual o Write data AAH Address 1555H Write data 55H Address 2AAAH Write data AOH Address 1555H Write Byte Address Byte Data Wait for end of Program TBP RY BY Program Completed
37. ocation on the stack During an MCU reset or the reset stack pointer RSP instruction the stack pointer is set to location OOFFH The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack When accessing memory the 8 most significant bits are permanently set to OOH These eight bits are appended to the lower 8 significant register bits to produce an address within the range of OOCOH to OOFFH Subroutines and inter rupts may use up to 256 decimal locations If 64 locations are exceeded i e if stack pointer is pointing to OOCOH and stacking operation carried out the stack pointer wraps around to OOFFH and overwrites the previously stored information A subroutine call occupies two locations on the stack an interrupt uses five locations 2003 Silicon Storage Technology Inc S74004 00 000 4 03 SST65P542R 7 Programming Reference Manual 5 1 5 Processor Status Word PSW The PSW is a 5 bit register These bits can be individually tested by a program and specific actions can be taken as a result of their state Each bit is explained in the following paragraphs 5 1 5 1 Half Carry H This bit is set during ADD and ADC operations to indicate that a carry has occurred between bits 3 and 4 of the accumulator during an ADD or ADC operation 5 1 5 2 Interrupt I When this bit is set all maskable interrupts are masked If an interrupt occurs while this bit is set the interrupt i
38. of the down counter can be read from 3FF2 lower 4 bits upper 4 bits will be 0 11 2 1 Time mode When the modulator operates in time mode the modulation mark and space periods are counted in multiple of fosc 8 clocks 250kHZ 2MHz osc This provides a modulator resolution of 4 us The maximum mark and the maximum space period are 16 384 ms 212 x 4 us These periods can be doubled by setting the DIV2 bit in the BCSR that will also decrease the resolution to 8us The modulator control gate and carrier clock are synchronized to prevent modulator output glitches When the modulator gate is opened mark the carrier signal passes through When modulator gate is closed space the modulator output is force to low If the carrier generator is in the base band mode BASE bit in MCSR is set to 1 the modulator output will be force to 1 for the duration of the mark period and force to 0 for the duration of a space period 2003 Silicon Storage Technology Inc S74004 00 000 4 03 31 SST65P542R Programming Reference Manual Here are the equations to calculate mark and space period for time mode MBUFF 1 x 8 AAA O Tmark r c osc Tspace SBUFF x 8 p sec osc Setting the DIV2 bit in the BCSR will double mark and space times fosc 8 CARRIER FREQUENCY MODULATOR GATE MARK SPACE MARK SPACE MARK TIME MODE OUTPUT BASEBAND OUTPUT 4004 F19 0 FIGURE 11
39. ompatibility T6 2 5 4004 Please see Section 10 0 for Core Timer and Section 11 0 for CMT register definitions All other register definitions are described in detail in the SST65P542R data sheet 2003 Silicon Storage Technology Inc S74004 00 000 4 03 21 SST65P542R 7 Programming Reference Manual 7 0 INTERRUPTS The MCU has 6 sources of interrupts including reset a software interrupt and 4 hardware interrupt lines If more than one interrupt line is active the one with highest priority will be serviced first The interrupt priority from high to low is hardware reset software interrupt external interrupt CMT interrupt Core Timer interrupt and Serial Inter face interrupt See Table 7 1 for Interrupt Address Vectors TABLE 7 1 MCU INTERRUPT ADDRESS VECTORS Interrupt Address Description Reset FFFEH FFFFH Restart vector FFFEH higher byte FFFFH lower byte SWI FFFCH FFFDH Software interrupt vector FFFCH higher byte FFFDH lower byte External Port B FFFAH FFFBH External Port B interrupt vector FFFAH higher byte FFFBH lower byte CMT FFF8H FFF9H CMT interrupt vector FFF8H higher byte FFF9H lower byte Core Timer FFF6H FFF7H Core Timer interrupt vector FFF6H higher byte FFF7H lower byte Serial Interface FFF4H FFF5H Serial Interface interrupt vector FFF4H higher byte FFF5H lower byte T7 1 3 4004 All four interrupt lines are masked by the interrupt mask bit I bit of the Process Statu
40. r and the two unsigned bytes following the opcode This address mode can be used in a manner simi lar to indexed 8 bit offset except that this three byte instruction allows tables to be anywhere in memory As with direct and extended addressing the assembler determines the shortest form of indexed addressing EA X PC 1 PC 2 PC lt PC 3 Address bus high byte lt PC 1 K Address bus low byte lt X PC 2 where K the carry from the addition of X and PC 2 2003 Silicon Storage Technology Inc S74004 00 000 4 03 SST65P542R 7 Programming Reference Manual 5 2 8 Relative REL The relative addressing mode is only used in branch instructions In relative addressing the contents of the 8 bit signed byte the offset following the opcode is sign extended and added to the PC if and only if the branch condi tions are true Otherwise control proceeds to the next instruction The span of relative addressing is from 126 to 129 from the opcode address The programmer need not calculate the offset when using the assembler since it calculates the proper offset and checks to see that it is within the span of the branch EA PC 2 PC 1 PC lt A if branch taken otherwise PC lt PC 2 5 2 9 Bit Set Clear BSC In the bit set clear addressing mode the bit to be set or cleared is part of the opcode The byte following the opcode specifies the address of the byte in which the specified bit is to be set or cleared Any read wr
41. rage Technology Inc S74004 00 000 4 03 14 SST65P542R Programming Reference Manual TABLE 5 1 MCU INSTRUCTION TABLE CONTINUED 3 OF 5 Address Hex Number of Number of Flags Mnemonic Explanation Mode n Opcode Machine Cycles Bytes Affected CMP Arithmetic compare IMM Al 2 2 NZC memory and accumulator DIR B1 3 2 unsigned EXT C1 4 3 A M IX F1 3 1 IX1 E1 4 2 IX2 D1 5 3 COM Component INH A 43 3 1 NZ1 one s complement INH X 53 3 1 DIR 33 5 2 IX 73 5 1 IX1 63 6 2 CPX Arithmetic compare IMM A3 2 2 NZC memory and index X DIR B3 3 2 unsigned EXT C3 4 3 X M IX F3 3 1 IX1 E3 4 2 IX2 D3 5 3 DEC Decrement by one INH A 4A 3 1 NZ INH X 5A 3 1 DIR 3A 5 2 IX 7A 5 1 IX1 6A 6 2 EOR Exclusive or memory IMM A8 2 2 NZ with accumulator DIR B8 3 2 A M A EXT C8 4 3 IX F8 3 1 IX1 E8 4 2 IX2 D8 5 3 INC Increment by one INH A 4C 3 1 NZ INH X 5C 3 1 DIR 3C 5 2 IX 7C 5 1 IX1 6C 6 2 JMP Jump to new location DIR BC 2 2 PC 1 PCL EXT CC 3 3 PC 2 PCH IX FC 2 1 IX1 EC 3 2 IX2 DC 4 3 JSR Jump to new location DIR BD 5 2 saving return address EXT CD 6 3 PC 2 IX FD 5 1 PC 1 PCL IX1 ED 6 2 PC 2 PCH IX2 DD 7 3 2003 Silicon Storage Technology Ine S7ADO4 00 00O 4 03 SST65P542R Programming Reference Manual TABLE 5 1 MCU IN
42. rence Manual 11 2 5 Modulator Period Data Register MDR1 MDR2 and MDR3 The MBUFF and SBUFF are 12 bit registers and can be accessed through three 8 bit registers MDR1 MDR2 and MDR3 MDR2 contains the least significant eight bits of MBUFF MB7 MBO MDR3 contains the least significant eight bits of SBUFF SB7 SBO MDR1 contains the two most significant nibbles of MBUFF MB11 MB8 and SBUFF SB11 SB8 Modulator Data Register MDR1 Address 0015H Bit 7 6 5 4 3 2 1 Bit 0 Read 2a MB11 MB10 MB9 MB8 SB11 SB10 SB9 SB8 Write Reset Unaffected by Reset Modulator Data Register MDR2 Address 0016H Bit 7 6 5 4 3 2 1 Bit O Read MB7 MB6 MB5 MB4 MB3 MB2 MB1 MBO Write Reset Unaffected by Reset Modulator Data Register MDR3 Address 0017H Bit 7 6 5 4 3 2 1 Bit 0 Read oe SB7 SB6 SB5 SB4 SB3 SB2 SBI SBO Write Reset Unaffected by Reset 11 2 5 1 Transmitter Block The state of infrared output pin IRO is controlled by the transmitter output block When the modulator carrier generator is enabled the IRO pin state is gated by the modulator output Otherwise the IRO pin is controlled by the state of the IRO latch which is described in CHR1 and CLR1 bit 7 11 2 5 2 Idle Mode Operation During idle mode if the CMT was enabled it continues to operate normally The CMT will not be able to be updated because the MCU is i
43. s latched and remains pending until the interrupt bit is cleared After any reset the interrupt mask is set and can be cleared by software instruction CLI 5 1 5 3 Negative N When set this bit indicates that the result of the last arithmetic logical or data manipulation was negative 5 1 5 4 Zero Z When set this bit indicates that the result of the last arithmetic logical or data manipulation was zero 5 1 5 5 Carry Borrow C When set this bit indicates that a carry or borrow out of the arithmetic logical unit ALU occurred during the last arithmetic operation This bit is also affected during bit test and branch instructions and during shifts and rotates 5 2 Addressing Modes Ten different addressing modes provide programmers with the flexibility to optimize their code for all situations The various indexed addressing modes make it possible to locate data tables code conversion tables and scaling tables anywhere in the memory space Short indexed accesses are single byte instructions the longest instruc tions three bytes enable access to tables throughout memory Short absolute direct and long absolute extended addressing are also included One or two byte direct addressing instructions access all data bytes in most applications Extended addressing permits jump instructions to reach all memory locations The term effective address EA is used in describing the various addressing modes The effective address is d
44. s Word Register The soft ware interrupt is generated by SWI instruction similar to that of any hardware instruction except that it is not maskable the execution of the SWI instruction is independent of the state of the mask bit All external interrupt lines are falling edge triggered and interrupts are always checked before fetching the next instruction If interrupt is recognized before the Program counter jumps to one of the address vectors the Program Counter Index Register Accumulator and the Process Status Word Register are pushed on to the stack see Figure 5 2 2003 Silicon Storage Technology Inc S74004 00 000 4 03 22 SST65P542R Programming Reference Manual o 8 0 RESETS AND CLOCKS SST65P542R has two sources for external reset LPRST and RESET After LPRSET switches from low to high 4064 clock cycles are counted before the reset vector address appears on the internal address bus RESET immediately resets the MCU without counting the 4064 clock cycles Crystal oscillator clock is divided by two to arrive at internal processor and peripheral clock Figure 8 1 shows RESET and LPRST timing diagram LPRST 4 osc12 lt gt toro INTERNAL PROCESSOR CLOCK I I I I INTERNAL RDS Aree Xr XewroXvewec rms X rere X rere X rere Ar MuewreXvewecX Bus l l INTERNAL I I OP OP BUS aa a nO OO a a H RESET 4004 F18 2 Notes I I I T I I I 1 Internal timing signal and bus infor
45. s never selected When operating in FSK mode the modulator alternately selects this register pair and the primary register pair The secondary carrier high and low 2003 Silicon Storage Technology Inc S74004 00 000 4 03 30 SST65P542R Programming Reference Manual time values are undefined out of reset These bits must be written to nonzero values before the carrier generator is enabled to avoid spurious results CMTPOL CMT Output Polarity This bit controls the polarity of the CMT output IRO When this bit is set to zero the CMT output is active high When this bit is set to one the CMT output is active low The reset state of this bit is zero IROLN and IROLP IRO Latch Control The IRO latch state can be read from either IROLN or IROLP bits The IRO latch state can be updated with being written on either negative or positive edge of the internal processor clock fosc 2 By writing to IROLN updates the IRO latch on the negative edge By writing to IROLP updates the IRO latch on the positive edge The IRO latch is cleared out of reset 11 2 Modulator The modulator can operate in two modes Time and FSk with a resolution of 4 us 2MHz external oscillator It can count either system clocks to provide real time control or it can count carrier clocks for self clocked protocols In time mode the modulator counts clocks derived from the system oscillator and modulates a single carrier fre quency TIME or no carr
46. to TOFC Writing a 0 to TOFC has no effect on CTOF TOFC has a 0 as default 10 2 6 Real Time Interrupt Flag Clear RTFC RTIF is cleared when RTFC bit is written to as 1 Writing a 0 to RTFC has no effect on RTIF RTFC has 0 as default 2003 Silicon Storage Technology Inc S74004 00 000 4 03 26 SST65P542R Programming Reference Manual 10 2 7 Real Time Interrupt Rate Select RT1 RTO These two bits select any one of four taps from the real time interrupt circuit stages Please reference Table 10 1 Reset sets these two bits to 11 selecting the lowest periodic rate and gives the maximum time to alter these bits if necessary CWT should be cleared before changing RTI taps If the selected tap is modified during a cycle in which the counter is switching a RTIF could be missed or an additional RTIF could be generated TABLE 10 1 RTI AND CWT RATES AT 4 096 MHz OSCILLATOR RTI Rate Minimum CWT Rates Maximum CWT Rates E 2 048 MHz RT1 RTO E 2 048 MHz E 2 048 MHz 2ms 22 E 00 215 212 E 14 ms 215 E 16 ms 4 ms 218 E 01 216 213 E 28 ms 216 E 32 ms 8 ms 24s E 10 217 214 E 56 ms 217 E 64 ms 16 ms 25 E 11 218 215 E 112 ms 2 8 E 128 ms T10 1 2 4004 10 3 Core Timer Counter Register CTCR The TCR is a read only register that contains the current value of the 8 bit ripple counter This counter is clocked by divided by four peripheral clock E 4 and

Programming User`s Manual

Contents

Download Pdf Manuals

Related Search

Related Contents