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Power PC 440GX Embedded Processor

1. Data Sheet Signals Listed Alphabetically Sheet 8 of 24 Signal Name Ball Interface Group Page GPIOO0 IRQO0 N18 GPIO01 IRQO1 L20 GPIO02 IRQ02 P20 GPIO03 IRQ03 L18 GPIO04 IRQ04 N14 05 005 M20 GPIO06 IRQ06 M14 GPIO07 IRQO7 P18 GPIO08 IRQO8 N20 GPIO09 IRQ09 P22 GPIO10 IRQ10 V18 GPIO11 GMCTxCIk TBIRxCIK1 P14 GPIO12 UART1 Rx C18 GPIO13 UART1 Tx J16 GPIO14 UART1 DSR CTS G06 GPIO15 UART1 RTS DTR E05 GPIO16 IIC1SCIK H11 GPIO17 IICTSDA H14 System GPIO18 TrcBSO IRQ13 N16 GPIO19 TrcBS 1 IRQ14 P17 GPIO20 TrcBS2 IRQ15 T20 GPIO21 TrcESO IRQ16 T21 GPIO22 TrcES1 IRQ17 P23 GPIO23 TrcES2 N09 GPIO24 TrcES3 P08 GPIO25 TrcES4 T05 GPIO26 TrcTS0 T04 GPIO27 TrcTS1 GMCCD GMC1RxClk P03 RTBI1RxCIk GPIO28 TrcTS2 GMCRxD4 GMC1RxDO0 TBIRxD4 RTBI1RxDO GP1O29 TreTS3 GMCRxD5 GMC1RxD1 B09 TBIRxD5 RTBI1RxD1 GPIO30 TrcTS4 GMCRxD6 GMC1RxD2 ES TBIRxD6 RTBI1RxD2 GPIO31 TrcTS5 GMCRxD7 GMC1RxD3 OB TBIRxD7 RTBI1RxD3 24 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Signals Listed Alphabetically Sheet 9 of 24 Signal Name Ball Interface Group Page Halt 05 System 55 HoldAck TrcTS4 Y21 External Master Peripheral 53 HoldReq TrcTS5 Y23 External Ma
2. Signal Name Ball Interface Group Page No ball A01 No ball A02 No ball A03 No ball A22 No ball A23 No ball A24 No ball B01 No ball B02 No ball B23 No ball B24 No ball C01 No ball C24 A physical ball does not exist at these ball coordinates NA No ball 01 No ball AB24 No ball 1 No ball 02 No ball AC23 No ball AC24 No ball AD01 Noball AD02 Noball AD03 No ball AD22 No ball AD23 No ball AD24 AMCC 29 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Signals Listed Alphabetically Sheet 14 of 24 Signal Name Ball Interface Group Page OVpp B04 OVpp B12 OVpp B19 OVpp 002 OVpp D10 OVpp D17 OVpp F08 OVpp F15 OVpp F23 OVpp OVpp H10 OVpp H13 OVpp H21 OVpp K04 Power 56 OVpp OVpp K19 OVpp M02 OVpp M17 OVpp N08 OVpp N23 OVpp R06 OVpp R17 OVpp R21 OVpp U04 OVpp U19 OVpp 02 OVpp AA23 PCIX133Cap G08 PCI X 49 PCIXAck64 DO9 PCI X 49 30 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Signals Listed Alphabetically Sheet 15 of 24 Signal Name Ball Interface Group Page PCIXADOO C17 PCIXADO1 B09
3. Input ns Output ns Output Current mA Signal Setup Time Hold Time Valid Delay Hold Time VOL Clock Notes Tis min Tig min Toy max min minimum minimum Internal Peripheral Interface 15 3 10 2 IICOSDA 15 3 10 2 IIC1SCIk na na na na 15 3 10 2 IIC1SDA 15 3 10 2 UARTSerClk na na na na na na UARTO_Rx na na na na UARTO Tx na na 10 3 7 1 UARTO DCD na na na na UARTO DSR na na na na UARTO CTS na na na na UARTO DTR na na 10 3 7 1 UARTO_RI na na na na UARTO_RTS na na 10 3 7 1 UART1_Rx na na na na UART1_Tx na na 10 3 7 1 UART1 DSR CTS na na na na UART1 RTS DTR na na 10 3 7 1 Interrupts Interface 000 17 JTAG Interface TDI na na async TMS na na async TDO 15 3 10 2 async TCK na na async TRST na na async AMCC 75 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Specifications All Speeds Sheet 7 of 7 Notes 1 Ethernet interface meets timing requirements as defined by IEEE 802 3 standard 2 PCI X timings are for asynchronous operation up to 133MHz PCI X input setup time requirement is 1 2ns for 133MHz and 1 7ns for 66MHz PCI timings in parentheses are for asynchronous operation up to 66 MHz PCI output hold time requirement is 1ns for 66MHz and 2ns for 33MHz 3 The clock frequency for RMII operation is 2
4. TBIRXCIKO RTBIORxClk Signal Name Ball Interface Group Page ECCO ABO7 ABOG ECC2 AD06 ECC3 wo7 DDR SDRAM 50 ECC4 009 5 ECC6 4 ECC7 AD04 EMCCD EMC1RxErr GMCGTxCIk GMCOTxCIk 407 Ethernet 50 EMCCrS EMCOCrSDV GMCTxD7 GMC1TxD3 TBITxD7 RTBI1TxD3 RO Ethernet 50 408 Ethernet 50 EMCMDIO 105 Ethernet 50 EMCRxCIk GMCTxD5 GMC1TxD1 TBITxD5 RTBI1TxD1 402 Ethernet 50 EMCORxD G03 EMCRxD1 EMCORxD1 EMC1RxD E01 EMCRxD2 EMC1RxD0 EMC2RxD GMCTxD0 GMCOTxDO TBITxDO A07 Ethernet 50 RTBIOTxDO EMCRxD3 EMC1RxD1 EMC3RxD GMCTxD1 GMCOTxD1 TBITxD1 9 RTBIOTxD1 EMCRxDV EMC1CrSDV GMCTxD4 GMC1TxD0 TBITxD4 RTBI1TxD0 K01 Ethernet 50 EMCRxErr EMCORxErr GMCTxD6 GMC1TxD2 TBITxD6 RTBI4TxD2 Ethernet 50 EMCTxCIk EMCRefCIK 06 Ethernet 50 EMCTxDO0 EMCOTxD Log EMCTxD1 EMCOTxD1 EMC1TxD K05 EMCTxD2 EMC1TxD0 EMC2TxD GMCTxD2 GMCOTxD2 TBITxD2 04 Ethernet 50 RTBIOTxD2 EMCTxD3 EMC1TxD1 EMC3TxD GMCTxD3 GMCOTxD3 TBITxD3 J03 RTBIOTxD3 EMCTxEn EMCOTxEn EMCSync 106 Ethernet 50 EMCTxErr EMC1TxEn GMCRxClk CUM prem 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009
5. Data Sheet Signals Listed Alphabetically Sheet 5 of 24 Signal Name Ball Interface Group Page GND B06 GND B10 GND B13 GND B17 GND B21 GND D04 GND D08 GND D12 GND D15 GND D19 GND D23 GND F02 GND F06 GND F10 GND F13 Power 56 GND F17 GND F21 GND H04 GND H08 GND H12 GND H15 GND H19 GND H23 GND K02 GND GND K10 GND K13 GND K17 GND K21 GND M04 AMCC 21 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Signals Listed Alphabetically Sheet 6 of 24 Signal Name Ball Interface Group Page GND M08 GND M12 GND M15 GND M19 GND M23 GND N02 GND N06 GND N10 GND N13 GND N17 GND N21 GND R04 GND R08 GND R12 GND R15 Power 56 GND R19 GND R23 GND 902 GND U06 GND U10 GND U13 GND U17 GND U21 GND W04 GND W08 GND W12 GND W15 GND W19 GND W23 22 AMCC Revision 1 20 June 9 2009 440GX Power 440GX Embedded Processor Data Sheet Signals Listed Alphabetically Sheet 7 of 24 Signal Name Ball Interface Group Page GND 02 GND 06 GND AA10 GND AA13 GND AA17 GND AA21 Power 56 GND AC04 GND 8 GND AC12 GND AC15 GND AC19 AMCC 23 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009
6. 59 Test ConditlOris u u See SET e 62 Spread Spectrum Clocking 65 DDR SDRAM I O Specifications 1 78 DDR SDRAM Write Operation 1 80 DDR SDRAM Read Operation 1 83 Initialization ied CRI rr ees 89 SUAPPING vk alae eR VEA 89 Serial EEPROM Z 22 feat xxu peed Oe ec eens Ee ies Pe pad ame EE 89 2 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Figures PPC440GX Functional Block Diagram 5 25mm 552 Ball Ceramic CBGA Package 15 25mm 552 Ball Plastic FC PBGA Package 16 Heat Sink Attached With Spring Clip 59 Heat Sink Attached With Adhesive 59 TIMING Waveform eid EE 3 Susa y 64 Input Setup and Hold Waveform 68 Output Delay and Float Timing Waveform
7. 71 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet UO Specifications All Speeds Sheet of 7 Notes 1 Ethernet interface meets timing requirements as defined by IEEE 802 3 standard 2 PCI X timings are for asynchronous operation up to 133MHz PCI X input setup time requirement is 1 2ns for 133MHz and 1 7ns for 66MHz PCI timings in parentheses are for asynchronous operation up to 66 MHz PCI output hold time requirement is 1ns for 66MHz and 2ns for 33MHz 3 The clock frequency for RMII operation is 2 100ppm 4 The clock frequency for operation is 125 MHz 100ppm 5 These are DDR signals that can change on both the positive and negative clock transitions Input ns Output ns Output Current mA Signal Setup Time Hold Time Valid Delay Hold Time VOL Clock Notes Tis min min Toy max min minimum minimum Ethernet SMII Interface EMCO 1RxD 0 8 0 8 na na 5 1 6 8 EMCRefCIK EMC2 3RxD 0 8 0 8 na na 5 1 6 8 EMCRefCIK EMCO 1TxD na na 3 5 2 5 1 6 8 EMCRefCIK EMC2 3TxD na na 3 5 2 5 1 6 8 EMCRefCIK EMCRefCIk na na na na na na Ethernet Interface GMCRxClk na na na na na na m GMCRxD0 7 2 0 na na 5 1 6 8 GMCRxEr 2 0 na na 5 1 6 8 GMCRxDV 2 0 5 1 6 8 GMCCrS na na
8. OOOOOOOOOOOOOOOOO 1 35 7 9 11131517 19 21 23 2 4 6 8 10 121416 18 20 22 24 gt 0 5 0 1 Pie gt 0 508 Ref 0 66 0 1 Solderball x 552 339 047 16 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Signal Lists The following table lists all the external signals in alphabetical order and shows the ball pin number on which the signal appears Multiplexed signals are shown with the default signal following reset not in brackets and the alternate signal in brackets Multiplexed signals appear alphabetically multiple times in the list once for each signal name on the ball The page number listed gives the page in Signal Functional Description on page 49 where the signals in the indicated interface group begin In cases where signals in the same interface group for example Ethernet have different names to distinguish variations in the mode of operation the names are separated by a comma with the primary name appearing first These signals are listed only once and appear alphabetically by the primary name Signals Listed Alphabetically Sheet 1 of 24 Signal Name Ball Interface Group Page APGND 401 ASGND J24 Power Analog ground 56 AMGND AA11 AMVpp AB11 Power MemClkOut PLL analog voltage 56 APVpp G01 Power PCI X PLL analog voltage 56 ASVpp G24 Power
9. AMCC 41 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Signals Listed by Ball Assignment Sheet 2 of 6 Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name E01 EMCRxD1 F01 PCIXAD35 G01 APVpp for PCI PLL H01 PCIXAD33 E02 PCIXAD40 F02 GND G02 PCIXAD39 H02 Vpp E03 PCIXCIK F03 PCIXAD44 G03 EMCRxDO PCIXAD32 E04 PCIXAD49 F04 Von G04 PCIXAD48 H04 GND E05 UART1 RTS DTR F05 PCIXAD52 G05 PCIXAD43 H05 PCIXAD38 E06 PCIXAD56 F06 GND UART1 DSR CTS H06 OVpp E07 PCIXAD60 F07 PCIXAD59 G07 PCIXIDSel 07 PCIXAD47 E08 PCIXAD63 F08 OVpp G08 PCIX133Cap Hos GND E09 PCIXReq64 FO9 PCIXC7 G09 PCIXC6 09 EMCRxD3 E10 PCIXAD03 F10 GND G10 PCIXAD02 H10 OVpp E11 PerAddr06 F11 PCIXADO6 G11 IIC0SCIk H11 IIC1SCIk E12 PCIXIRDY F12 Vpp G12 PCIXADO7 H12 GND E13 PCIXDevSel F13 GND G13 IICOSDA H13 OVpp E14 PerAdd09 F14 PCIXCO G14 PCIXADO8 H14 IICTSDA E15 PCIXAD11 F15 OVpp G15 PCIXAD12 H15 GND E16 PCIXC1 F16 PCIXParLow G16 UARTO_RTS H16 UARTO_RI E17 PerCSO F17 GND G17 UARTO Rx H17 Mon E18 PCIXAD16 F18 PCIXAD18 G18 PCIXAD19 H18 PerData05 E19 PCIXAD17 F19 G19 PerData04 H19 GND E20 PCIXReq2 F20 PCIXC3 G20 PerData03 H20 PerData02
10. Input ns Output ns Output Current mA Signal Setup Time Hold Time Valid Delay Hold Time VOL Clock Notes Tis min Tin min Tov max Tou min minimum minimum Ethernet RTBI Interface RTBIORXCIK na na na na na na 1 async RTBIORxDO 4 1 1 na na 5 1 6 8 RTBIORxClk 5 1 6 8 1 async RTBIOTxDO 4 na na 3 5 5 1 5 1 6 8 RTBIOTxClk RTBI1RxClk na na na na na na 1 RTBI1RxD0 4 1 1 na na 5 1 6 8 RTBI1RxClk RTBI1TxClk na na na na 5 1 6 8 1 RTBI1TxD0 4 na na 3 5 5 1 5 1 6 8 RTBI1TxClk GMCRefCIk na na na na na na async 74 AMCC Revision 1 20 June 9 2009 Data Sheet 440GX Power PC 440GX Embedded Processor Specifications All Speeds Sheet 6 of 7 Notes 1 Ethernet interface meets timing requirements as defined by IEEE 802 3 standard 2 PCI X timings are for asynchronous operation up to 133MHz PCI X input setup time requirement is 1 2ns for 133MHz and 1 7ns for 66 MHz PCI timings in parentheses are for asynchronous operation up to 66 MHz PCI output hold time requirement is 1ns for 66 MHz 2ns for 33MHz 3 The clock frequency for RMII operation is 50 MHz 100ppm 4 The clock frequency for operation is 125MHz 100ppm 5 These are DDR signals that can change on both the positive and negative clock transitions
11. TBI Receive clock 0 RTBIORXCIK RTBI Receive clock GMCCD GMII Collision detection 3 3V tolerant GMC1RxClk RGMII Receive clock 25V CMOS 5 RTBI1RxClk RTBI Receive clock AMCC 51 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Signal Functional Description Sheet 4 of 8 Notes 1 Receiver input has hysteresis 2 Must pull up recommended value is 3kQ to 3 3V 3 Must pull down recommended value is 1kQ 4 If not used must pull up recommended value is 3kQ to 3 3V 5 If not used must pull down recommended value is 1kQ to GND 6 Strapping input during reset pull up recommended value is 3kQ to 3 3V or pull down recommended value is 1kQ to GND required Signal Name Description y o Type Notes GMCCrs GMII Carrier sense 3 3V tolerant GMC1TxClk RGMII Transmit clock UO 25V CMOS RTBI1TxClk RTBI Transmit clock GMCRefCIk GMII RGMII TBI and RTBI Gigabit reference clock pb 5 2 5V CMOS GMCRXxD0 3 GMII Receive data GMCORxD0 3 RGMII Receive data 3 3V tolerant TBIRxDO 3 TBI Receive data 2 5V CMOS RTBIORxDO 3 RTBI Receive data GMCRxD4 7 GMII Receive data GMC1RxD0 3 RGMII Receive data 3 3V tolerant TBIRxD4 7 TBI Receive data 2 5V CMOS RTBI1RxD0 3 RTBI Receive data GMCRxDV GMII Receive data valid RGMII Receive control 3 3V tolerant TBIRxD8 TBI Receive
12. 4 5 GMCOTxCIK na na na na 5 1 6 8 1 GMCOTxCtl na na 0 5 3 5 5 1 6 8 GMCOTxClk 4 5 GMCOTxD0 3 na na 0 5 3 5 5 1 6 8 GMCOTxClk 4 5 GMC1RxClk na na na na na na 1 GMC1RxCtl 1 1 na na na na GMC1RxClk 4 5 GMC1RxD0 3 1 1 na na 5 1 6 8 GMC1RxClk 4 5 GMC1TxClk na na na na 5 1 6 8 1 GMC1TxCtl na na 0 5 3 5 5 1 6 8 GMC1TxClk 4 5 GMC1TxD0 3 na na 0 5 3 5 5 1 6 8 GMC1TxClk 4 5 GMCRefCIk na na na na na na async Ethernet TBI Interface 1 TBIRxClk1 na na na na na na 1 async TBIRxDO 9 2 5 1 5 na na 5 1 6 8 TBIRxClkx TBITxClk na na na na na na 1 async TBITxD0 9 na na 6 1 5 1 6 8 TBITxClk AMCC 73 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Specifications All Speeds Sheet 5 of 7 Notes 1 Ethernet interface meets timing requirements as defined by IEEE 802 3 standard 2 PCI X timings are for asynchronous operation up to 133MHz PCI X input setup time requirement is 1 2ns for 133MHz and 1 7ns for 66 2 PCI timings in parentheses are for asynchronous operation up to 66 MHz PCI output hold time requirement is 1ns for 66MHz and 2ns for 33MHz 3 The clock frequency for RMII operation is 2 100ppm 4 The clock frequency for operation is 125 MHz 100ppm 5 These are DDR signals that can change on both the positive and negative clock transitions
13. Data Sheet Signals Listed Alphabetically Sheet 4 of 24 Signal Name Ball Interface Group Page EOTO TCO R16 EOT1 TC1 P15 EOT2 TC2 GMCRxD2 GMCORxD2 P16 External Slave Peripheral 52 TBIRxD2 RTBIORxD2 EOT3 TC3 GMCRxD3 GMCORxD3 M16 TBIRxD3 RTBIORxD3 ExtAck TrcTS2 AA22 External Master Peripheral 53 ExtReq TrcTS3 AB23 External Master Peripheral 53 ExtReset T17 External Master Peripheral 53 GMCCD GMC1RxClk RTBHRXCIKITICTS1 GPIO27 S i GMCCrS GMC1TxClk RTBI1TxCIk TreTS6 ME 30 GMCRefClk 101 Ethernet 50 GMCRxD0 GMCORxDO TBIRxDO P06 RTBIORxD0 DMAAck2 SMCRxD1 GMC0RxD1 TBIRxD1 P11 RTBIORxD1 DMAAck3 GMCRxD2 GMCORxD2 TBIRxD2 P16 RTBIORxD2 EOT2 TC2 GMCRxD3 GMCORxD3 TBIRxD3 M16 RTBIORxD3 EOT3 TC3 Ethernet 50 GMCRxD4 GMC1RxDO TBIRxD4 R07 RTBI1RxD0J GPIO28 TrcTS2 SMCRxD5 GMC1RxD1 TBIRxD5 P09 RTBITRxD1 GPIO29 TrcTS3 GMCRxD6 GMC1RxD2 TBIRxD6 ROO RTBI1RxD2 GPIO30 TrcTS4 GMCRxD7 GMC1RxD3 TBIRxD7 RTBITRxD3 GPIO31 TrcTS5 GMCRxDV GMCORxCtl TBIRxD8 RTBIORxD4 DMAReq2 DER 90 GMCRxEr GMC1RxCtl TBIRxD9 RTBI1RxD4 P04 Ethernet 50 GMCTxEr GMC1TxCtl TBITxD9 107 Ethernet 50 RTBI1TxD4 Note Used as initialization strapping input GMCTxEn GMCOTxCtl TBITxD8 RTBIOTxD4 DMAReq3 PUE i GMCTxCIk TBIRXCIK1 GPIO1 1 P14 Ethernet 50 20 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor
14. Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name A01 No ball 01 No ball No ball 001 PCIXAD36 A02 Noball 02 No ball C02 PCIXAD41 002 OVpp A03 Noball B03 PCIXAD46 C03 PCIXC5 003 PCIXAD45 A04 51 B04 OVpp C04 50 D04 GND A05 Drvrinh2 05 PCIXAD54 C05 EMCTxErr 005 PCIXAD53 A06 PCIXAD58 GND C06 PCIXAD57 006 A07 EMCRxD2 B07 PCIXAD62 C07 PerBLast 007 PCIXAD61 A08 PCIXAD42 B08 Von C08 PCIXC4 DOS GND A09 UARTSerCIk 09 PCIXADO1 C09 PCIXAD55 009 PCIXAck64 A10 PCIXAD05 B10 GND C10 PCIXADO4 D10 OVpp A11 PCIXFrame B11 PerAddr02 C11 PerAddr01 D11 PerAddr0O A12 PerAddr03 B12 OVpp C12 PCIXTRDY D12 GND A13 PerAddr12 B13 GND C13 UARTO CTS 013 14 PCIXM66En 14 PerAddr13 C14 PerAddr14 D14 PerAddr15 A15 PCIXADOS B15 C15 PCIXAD10 D15 GND A16 PerAddr11 B16 PCIXAD13 C16 PCIXAD14 D16 PCIXAD15 A17 PCIXPErr B17 GND C17 PCIXADOO D17 OVpp A18 PCIXSErr B18 UARTO_DTR C18 UART1_Rx 018 PerAddr05 A19 PerAddr04 B19 OVpp C19 PCIXC2 D19 GND A20 PCIXAD21 B20 PerAddr16 C20 PerAddr10 D20 PCIXAD20 A21 PCIXAD22 B21 GND C21 PCIXAD23 D21 Vpp A22 No ball B22 PCIXAD25 C22 PCIXGnt D22 PCIXAD30 A23 Noball B23 No ball C23 PCIXAD28 D23 GND A24 Noball B24 No ball C24 No ball D24 PCIXAD31
15. clock frequency is 66 66Mhz If the Ethernet application is limited to 100Mbps the minimum OPB clock frequency is 33 33Mhz 3 In order to support 1Gbps Ethernet data rate the minimum MAL clock frequency is 83 33Mhz If the Ethernet application is limited to 100Mbps the minimum MAL clock frequency is 33 33Mhz AMCC 63 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Timing Waveform 64 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Spread Spectrum Clocking Care must be taken when using a spread spectrum clock generator SSCG with the PPC440GX This controller uses a PLL for clock generation inside the chip The accuracy with which the PLL follows the SSCG is referred to as tracking skew The PLL bandwidth and phase angle determine how much tracking skew there is between the SSCG and the PLL for a given frequency deviation and modulation frequency When using an SSCG with the PPC440GxX the following conditions must be met The frequency deviation must not violate the minimum clock cycle time Therefore when operating the PPC440GxX with one or more internal clocks at their maximum supported frequency the SSCG can only lower the frequency The maximum frequency deviation cannot exceed 3 and the modulation frequency cannot exceed 40kHz In some cases on board PPC440GX peripherals impose more stringent re
16. 02 G10 PCIXAD03 E10 PCIXAD04 C10 PCIXAD05 A10 PCIXADOG F11 07 G12 PCIXAD08 G14 09 15 PCIXAD10 C15 PCIXAD11 E15 PCIXAD12 G15 PCIXAD13 B16 PCIXAD14 C16 PCIXAD15 D16 PCI X 49 PCIXAD16 E18 PCIXAD17 E19 PCIXAD18 F18 PCIXAD19 G18 PCIXAD20 D20 PCIXAD21 A20 PCIXAD22 A21 PCIXAD23 C21 PCIXAD24 F22 PCIXAD25 B22 PCIXAD26 G21 PCIXAD27 E23 PCIXAD28 C23 PCIXAD29 F24 PCIXAD30 D22 PCIXAD31 D24 AMCC 31 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Signals Listed Alphabetically Sheet 16 of 24 Signal Name Ball Interface Group Page PCIXAD32 H03 PCIXAD33 H01 PCIXAD34 L08 PCIXAD35 F01 PCIXAD36 D01 PCIXAD37 J05 PCIXAD38 H05 PCIXAD39 G02 PCIXAD40 E02 PCIXAD41 C02 PCIXAD42 A08 PCIXAD43 G05 PCIXAD44 F03 PCIXAD45 D03 PCIXAD46 B03 PCIXAD47 H07 PCI X 49 PCIXAD48 G04 PCIXAD49 E04 PCIXAD50 C04 PCIXAD51 A04 PCIXAD52 F05 PCIXAD53 D05 PCIXAD54 B05 PCIXAD55 C09 PCIXAD56 E06 PCIXAD57 C06 PCIXAD58 A06 PCIXAD59 7 PCIXAD60 E07 PCIXAD61 007 PCIXAD62 B07 PCIXAD63 E08 32 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Signals Listed Alphabetically Sheet 17 of 24 Signal
17. Support for peripherals running on slower frequency buses Serial Port Features include One 8 pin UART and one 4 pin UART interface provided Selectable internal or external serial clock to allow wide range of baud rates Register compatibility with 16750 register set Complete status reporting capability Fully programmable serial interface characteristics Supports DMA using internal DMA engine Bus Interface Features include Two IIC interfaces provided Support for Philips amp Semiconductors 2 Specification dated 1995 Operation at 100kHz or 400 kHz 8 bit data 10 or 7 bit address Slave transmitter and receiver Master transmitter and receiver Multiple bus masters Supports fixed Vpp IIC interface Two independent 4 x 1 byte data buffers Twelve memory mapped fully programmable configuration registers One programmable interrupt request signal Provides full management of all IIC bus protocols Programmable error recovery General Purpose Timers GPT Provides a separate time base counter and additional system timers in addition to those defined in the processor core 32 bit Time Base Counter driven by the OPB bus clock Seven 32 bit compare timers General Purpose IO GPIO Controller Controller functions and GPIO registers are programmed and accessed via memory mapped OPB bus master accesses The 32 GPIOs are pin shared with other functions DCRs control whether a particular
18. TBI Transmit clock RTBI Transmit clock EMCCTIS MII Carrier sense EMCOCrsDV RMII 0 Carrier sense data valid GMCTxD7 GMII Transmit data up 3 3V tolerant GMC1TxD3 RGMII 1 Transmit data 2 5V CMOS TBITxD7 TBI Transmit data RTBI1TxD3 RTBI 1 Transmit data 3 3V tolerant MII Management data clock 25V CMOS MII and RMII Transfer command and status information between 3 3V tolerant FMCMDIO and PHY VO 25V CMOS 50 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Signal Functional Description Sheet 3 of 8 Notes 1 Receiver input has hysteresis 2 Must pull up recommended value is 3kQ to 3 3V 3 Must pull down recommended value is 1kQ 4 If not used must pull up recommended value is 3kQ to 3 3V 5 If not used must pull down recommended value is 1kQ to GND 6 Strapping input during reset pull up recommended value is 3kQ to 3 3V or pull down recommended value is 1kQ to GND required Signal Name Description y o Type Notes EMCRxDO 3 MII Receive data EMCORxDO 1 RMII 0 Receive data EMC1RxD0 1 RMII 1 Receive data EMCORxD SMII 0 Receive data EMC1RxD 1 Receive data 3 3V tolerant EMC2RxD 2 Receive data UO 25V CMOS EMC3RxD 3 Receive data GMCTxD0 1 GMII Transmit data GMCOTxD0 1 RGMII 0 Transmit data TBITxDO 1 TBI Transm
19. 3 The clock frequency for RMII operation is 5OMHz 100ppm 4 The clock frequency for SMII operation is 125 MHz 100ppm 5 These are DDR signals that can change on both the positive and negative clock transitions Input ns Output ns Output Current mA Signal Setup Time Hold Time Valid Delay Hold Time VOL Clock Notes Tig min min Toy max min minimum minimum Ethernet MII Interface 4 1 5 1 6 8 1 4 1 5 1 6 8 1 5 4 6 8 me EMCRxErr 4 1 na na 5 1 6 8 1 15 2 5 1 6 8 1 EMCTxEn na na 15 2 5 1 6 8 1 EMCTxErr na na 15 2 5 1 6 8 EMCTxClk 1 EMCCIS na na 5 1 6 8 PS EMCCD na na 5 4 6 8 E EMCMDIO 5 1 6 8 1 5 1 6 8 ma Ethernet RMII Interface EMCORxDO 1 2 1 na na 5 1 6 8 EMCRefClk EMCORxErr 2 1 na na 5 1 6 8 EMCRefClk EMCOCrSDV na na 5 1 6 8 EMCRefClk EMCOTxDO 1 na na 11 2 5 1 6 8 EMCRefClk 1 11 2 5 1 6 8 EMCRefClk EMC1RxD0 1 na na 5 1 6 8 EMCRefClk EMC1RxErr na na 5 1 6 8 EMCRefClk EMC1CrSDV na na 5 1 6 8 EMCRefClk EMC1TxD0 1 na na 11 2 5 1 6 8 EMCRefClk EMCRefClk na na na na na na
20. Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Date Contents of Modification 02 08 2006 Correct timing changes made in 12 22 05 version 04 04 2006 Add six new PNs two 533MHz and four 677 MHz Remove two PNs no Z shipping for 3NF533C or 3FF533C 06 09 2006 Update clocking specs and EEPROM information 09 11 2006 Add four posts to plastic package drawing f Reduce maximum E temperature rating for selected plastic parts Remove five PNs end of life 09 26 2006 Add change timing data system and DDR SDRAM for 800 MHz Rev F parts Increase minimum CPU frequency from 300MHz to 333MHz Increase SVpp for DDR SDRAM parts operating a 200MHz 02 23 2007 Add two new ceramic 400MHz PNs One is leaded C and the other is reduced lead R 03 05 2007 Change values for RGMII signals 08 30 2007 Change the technical support telephone and fax number 04 03 2008 Remove power supply power up sequence requirements 07 16 2008 Change package type to ceramic for PPC440GX 3RF400C Doc Issue 549 09 16 2008 Doc Issue 408 Rename AGND pins according to the analog voltage with which they are associated Doc Issue 483 Add two RGMII I O timing waveforms 09 22 2008 Doc Issue 595 Add pull up and pull down resistor values 11 06 2008 Bugzilla Issue 4921 Increase OPB clock minimum frequency specification Bugzilla Issue 5432 Modified the minimum and maximum values of the MemClkO
21. 68 DDR SDRAM Simulation Signal Termination Model 78 DDR SDRAM Write Cycle Timing 1 0 1 80 DDR SDRAM MemClkOut0 and Read Clock Delay 83 DDR SDRAM Read Data Path 0 2 84 DDR SDRAM Read Cycle Timing Example 1 86 DDR SDRAM Read Cycle Timing Example 2 2 87 DDR SDRAM Read Cycle Timing Example 3 1 88 Tables Order Part u u eme Ree Rx eR AEN 0 4 System Memory Address Map 1 6 DCR Address voee A EE e EE Rep RR aqa 8 Signals Listed Alphabetically 0 17 Signals Listed by Ball Assignment 41 PIN SUMMAN better eee hare et heed ee 47 Signal Functional Description 49 Absolute Maximum Ratings 57 Package Thermal Specifications 58 Recommended DC Operating Conditions 2 60 Input ia cues RR Ren
22. E21 PCIXReq1 F21 GND G21 PCIXAD26 H21 OVpp E22 PCIXGntO F22 PCIXAD24 G22 SysClk H22 PerData01 E23 PCIXAD27 F23 OVpp G23 PCIXReq4 H23 GND E24 PCIXReqO F24 PCIXAD29 G24 ASVpp for SysCIK PLL H24 PerData00 42 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Signals Listed by Ball Assignment Sheet 3 of 6 Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name J01 APGND K01 EMCRxDV 101 GMCRefCIk M01 PerAddr21 402 EMCRxCIk K02 GND 102 RefVEn 2 OVpp 403 EMCTxD3 EMCRxErr 103 PerCS4 PerAddr07 J04 EMCTxD2 4 OVpp 104 PCIXParHigh M04 GND 405 PCIXAD37 K05 EMCTxD1 105 EMCMDIO 5 TestEn J06 EMCTxCIk GND 106 EMCTxEn J07 EMCCD K07 EMCCIS 107 GMCTxEr M07 PCIXINT 08 K08 OVpp 108 PCIXAD34 M08 GND 409 PerData19 KO9 PerData28 109 EMCTxDO 09 PerOE J10 PerData18 K10 GND L10 PerCS1 M10 Voo J11 PerData17 K11 PerData27 L11 UARTO Tx M11 DMAReq1 J12 PerData16 K12 Von L12 PCIXStop M12 GND J13 PerData15 K13 GND 113 PerCS6 M13 Voo J14 PerData14 K14 PerData26 L14 PerData20 M14 IRQ06 J15 PerData13 K15 Vpp L15 PerAddr17 M15 GND J16 UART1 Tx K16 PerData25 L16 PerData31 M16 EOT3
23. N13 GND P13 DM3 R13 Vpp T13 MemData22 N14 IRQ04 14 1 R14 MemData14 T14 MemVRef1 N15 Vpp 15 EOT1 TC1 R15 GND T15 MemData18 N16 TrcBS0 P16 EOT2 TC2 R16 EOTO TCO DMO N17 GND 17 TrcBS1 R17 OVpp T17 ExtReset N18 IRQOO P18 IRQO7 R18 PCIXReq5 T18 PerWBEO N19 Vpp P19 PCIXGnt5 R19 GND T19 PerAddr24 N20 IRQ08 P20 IRQ02 R20 PCIXReq3 T20 TrcBS2 N21 GND P21 TrcTS6 R21 OVpp T21 TrcESO N22 PCIXGnt2 P22 IRQO9 R22 PCIXGnt4 T22 1 N23 OVpp P23 TrcES1 R23 GND T23 0 N24 TRST P24 PerAddr23 R24 PerAddr25 T24 PerCS3 44 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Signals Listed by Ball Assignment Sheet 5 of 6 Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name U01 TmrClk VO MemData55 WO MemData58 Y01 MemData51 U02 GND V02 UARTO DSR wo2 OVpp Y02 MemData53 U03 PerCS7 V03 DM7 W03 MemData59 Y03 DM6 U04 OVpp V04 PerCS2 W04 GND Y04 DQS6 U05 MemData63 05 Halt WO05 MemData62 05 WE U06 GND 06 MemData60 WO06 06 MemData46 UO7 MemData57 07 MemData54 W07 ECC3 Y07 MemData43 008 Vpp 08 MemCIkOutO wos GND Y08 MemData47 009 4 09 MemCIkOutO WO09 ClkEn3 Y09 2 U10 GND V10 MemAdd
24. 100ppm 4 The clock frequency for operation is 125 MHz 100ppm 5 These are DDR signals that can change on both the positive and negative clock transitions Input ns Output ns Output Current mA Signal Setup Time Hold Time Valid Delay Hold Time VOL Clock Notes Tis min min Toy max min minimum minimum System Interface SysClk na na na na TmrClk na na na na async SysReset na na async Halt na na na na async SysErr na na 10 3 7 1 async TestEn na na na na async Drvrinh2 na na na na GPIO00 31 10 3 7 1 Trace Interface TrcCIk na na 10 3 7 1 TrcBS0 2 10 3 7 1 TrcES0 4 10 3 7 1 TrcTS0 5 GPIO set 10 3 7 1 TrcTS1 5 EBC set 15 3 10 2 TrcTS6 15 3 10 2 76 AMCC Revision 1 20 June 9 2009 Data Sheet 440GX Power PC 440GX Embedded Processor UO Specifications 500 MHz 667 MHz rising edge at package with a 10pF load trails the internal PLB clock by approximately 1 3ns Input ns Output ns Output Current mA Signal oe Hold Time Valid Delay Hold Time OH VOL Clock Notes min min minimum minimum External Slave Peripheral Interface PerData00 31 2 8 1 6 6 0 15 3 10 2 PerClk PerAddr00 31 2 9 1 6 6
25. AMCC reserves the right to ship devices of higher grade in place of those of lower grade AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED INTENDED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT APPLICATIONS DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS AMCC is a registered Trademark of Applied Micro Circuits Corporation Copyright 2008 Applied Micro Circuits Corporation AMCC 93
26. Maps The PPC440GxX incorporates two address maps The first is a fixed processor system memory address map This address map defines the possible contents of various address regions which the processor can access The second address map is for Device Configuration Registers DCRs The DCRs are accessed by software running on the PPC440GX processor through the use of mtdcr and mfdcr instructions AMCC 5 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet System Memory Address Map Sheet 1 of 2 Function Sub Function Start Address End Address Size DDR SDRAM 0 0000 0000 0 7FFF FFFF 2GB SRAM 0 8000 0000 0 8000 3FFF 256KB Local Memory Reserve 0 8000 4000 0 FFFE FFFF IMU FFFF 0000 0 FFFF FFFF 64KB EBC 1 0000 0000 13FFF FFFF 1GB Reserved 1 4000 0000 14000 01FF UARTO 1 4000 0200 1 4000 0207 8B Reserved 1 4000 0208 1 4000 02FF UART1 1 4000 0300 1 4000 0307 8B Reserved 1 4000 0308 1 4000 03FF 1 4000 0400 1 4000 041F 32B Reserved 1 4000 0420 1 4000 04FF 1 4000 0500 1 4000 051F 32B Reserved 1 4000 0520 14000 05FF OPB Arbiter 1 4000 0600 1 4000 063F 64B Reserved 1 4000 0640 1 4000 06FF Internal Peripherals GPIO Controller 1 4000 0700 1 4000 077F 128B Ethernet PHY ZMII 1 4000 0780 1 4000 078F 16B Ethernet PHY GMII 1 4000 0790 1 4000 079F 16B Reserved 1 4000 07A0 14000 07FF Etherne
27. MemData00 07 0 638 1 165 200 DQS1 1 920 2 314 MemData08 15 0 631 1 149 200 DQS2 1 938 2 361 MemData16 23 0 634 1 151 200 DQS3 1 945 2 370 MemData24 31 0 624 1 169 200 DQS4 1 932 2 332 MemData32 39 0 630 1 151 200 DQS5 1 936 2 348 MemData40 47 0 619 1 133 200 DQS6 1 938 2 356 MemData48 55 0 635 1 149 200 DQS7 1 943 2 360 MemData56 63 0 642 1 151 200 DQS8 1 952 2 381 ECCO 7 0 641 1 141 In the following examples the data strobes DQS and the data are shown to be coincident There is actually a slight skew as specified by the SDRAM specifications and there can be additional skew due to loading and signal routing It is recommended that the signal length for all of the eight DQS signals be matched AMCC 85 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Example 1 If the data to PLB clock timing is as shown in the example below then the read clock is not delayed and the Stage 1 data is sampled at 1 Except for small low frequency memory systems with the memory located physically close to the 440 it is unlikely that Stage 1 data can be sampled When the data comes later it is necessary to sample Stage 2 or Stage 3 data see Examples 2 and 3 Another way to get the desired data to PLB timing to allow Stage 1 sampling is to buffer MemCIkOutO and skew it enough to guarantee the timing In this example 1 27ns at worst case conditions DDR SDRAM Read Cycle
28. Number Key Part Number Grade 3 Reliability Package PPC440GX 3C EC Case Temperature Range Processor Speed Revision Level AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet PPC440GX Functional Block Diagram Universal Interrupt Controller Timers MMU 63 internal PPC440 GP 18 external Processor Core DCR Bus Timers JTAG Trace 32KB 32KB On chip Peripheral Bus OPB D Cache v DMA Controller L2 Controller 4 Channel Processor Local Bus PLB v v External External 10 100 Bus Master Bus 10 100 x2 Controller Controller v rnet 83 MHz max 20 DDR SDRAM Sun 32 bit addr Messaging Bridge Controller i Bridge 32 bit data 133MHz max 166MHz max 32 64 bit data 13 bit addr 32 64 bit data The 440 is designed using the IBM Microelectronics Blue Logic methodology in which major functional blocks are integrated together to create an application specific product ASIC This approach provides a consistent way to create complex ASICs using IBM CoreConnect Bus Architecture Note IBM CoreConnect buses provide 128 bit PLB interfaces up to 166 MHz 32 bit OPB interfaces up to 83 33MHz 333MB s Address
29. PCI X in 0 10Vpp V 1 Output Logic Low 3 3V LVTTL 0 0 4 V Input Leakage Current No pull up or pull down lii 4 0 0 Input Leakage Current for Pull Down 112 0 LPDL 200 MPUL 5 Input Leakage Current for Pull Up lii 3 150 LPDL 0 MPUL HA 5 Input Max Allowable Overshoot 3 3V LVTTL VIMAO 3 9 V Input Max Allowable Undershoot 3 3V LVTTL Vimau 0 6 V Output Max Allowable Overshoot 3 3V LVTTL Vomao 3 9 V 60 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Recommended DC Operating Conditions Continued Device operation beyond the conditions specified is not recommended Extended operation beyond the recommended conditions can affect device reliability Parameter Symbol Minimum Typical Maximum Unit Notes Output Max Allowable Undershoot 3 3V LVTTL Vomau3 0 6 V Case Temperature rating Tc 40 85 G 6 7 8 Notes 1 2 3 on PCI X drivers meet PCI X specifications SVggr SVpp 2 The analog voltages used for the on chip PLLs can be derived from the logic voltage but must be filtered before entering the 440 See Absolute Maximum Ratings on page 57 There are no OVpp Vpp or SVpp power supply power up sequence requirements However external voltage should not be applied to the chip I O pins before OVpp is applied to the chip A power down cycle should complete OVpp and Vpp should bot
30. PCIXTRDY Note 2 3 0 5 0 3 8 6 0 7 Note 2 0 5 1 5 2 PCIXStop Note 2 3 0 5 0 3 8 6 0 7 Note 2 0 5 1 5 2 PCIXDevSel Note 2 3 0 5 0 3 8 6 0 7 Note 2 0 5 1 5 2 PCIXIDSel Note 2 3 0 5 0 na na na na PCIXClk 2 PCIXPErr Note 2 3 0 5 0 3 8 6 0 7 Note 2 0 5 1 5 2 PCIXSErr Note 2 3 0 5 0 3 8 6 0 7 Note 2 0 5 1 5 2 async PCIXReset na na na na na na PCIXCIk PCIXReq64 Note 2 3 0 5 0 3 8 6 0 7 Note 2 0 5 1 5 PCIXCIk 2 PCIXAck64 Note 2 3 0 5 0 3 8 6 0 7 Note 2 0 5 1 5 PCIXCIk 2 PCIXCap Note 2 3 0 5 0 na na na na PCIXClk 2 PCIX133Cap 3 8 0 7 0 5 1 5 2 PCIXM66En Note 2 3 0 5 0 na na na na PCIXClk 2 PCIXReq0 5 Note 2 3 0 5 0 na na na na 2 PCIXGnt0 5 na na 3 8 6 0 7 Note 2 0 5 1 5 2 70 Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Specifications All Speeds Sheet 2 of 7 Notes 1 Ethernet interface meets timing requirements as defined by IEEE 802 3 standard 2 PCI X timings are for asynchronous operation up to 133MHz PCI X input setup time requirement is 1 2ns for 133MHz and 1 7ns for 66MHz PCI timings in parentheses are for asynchronous operation up to 66 MHz PCI output hold time requirement is 1ns for 66 2 2ns for 33MHz
31. Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Absolute Maximum Ratings The absolute maximum ratings below are stress ratings only Operation at or beyond these maximum ratings can cause permanent damage to the device None of the performance specification contained in this document are guaranteed when operating at these maximum ratings Characteristic Symbol Value Unit Notes Supply Voltage Internal Logic VDD 0 to 1 65 V Supply Voltage UO Interface except DDR SDRAM OVpp to 3 6 V PLL Supply Voltages AXVpp 0 to 1 65 V 1 Supply Voltage DDR SDRAM Logic SVpp 0 to 2 7 V Input Voltage 3 3V LVTTL receivers ViN 0 to 3 6 V Storage Temperature Range Ter 55 to 150 Case Temperature under bias 40 to 120 C 2 Notes 1 The analog voltages used for the on chip PLLs can be derived from the logic voltage but must be filtered before entering the PPC440Gx A separate filter as shown below is recommended for each voltage Von e 6000 Las L SMT ferrite bead chip Murata BLM31A700S or equivalent L C 0 1 ceramic ee AxGND 2 This value is not a specification of the operational temperature range it is a stress rating only AMCC 57 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Package Thermal Specifications Thermal resistance values for the CBGA and PBGA pack
32. Timing Example 1 DQS at pin N Data at pin DQS Stage 1 C Data in Stage 1 D gt Data out Stage 1 Data in at RDSP with no ECC PLB Clock High Data out RDSP Low DO X D2 X X 1 Delay from DQS at package pin to C on Stage 1 FF Tp Propagation delay through FFs Tpin Delay from data at package pin to D on Stage 1 FF T1 Propagation delay Stage 1 input to RDSP input w o ECC 86 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Example 2 In this example Read Clock is delayed almost 1 2 cycle Without ECC Stage 2 data can be sampled at 2 If ECC is enabled Stage 3 data must be sampled see Example 3 In this example T 1 27ns and 3 589ns at worst case conditions DDR SDRAM Read Cycle Timing Example 2 DQS at pin Data at pin DQS Stage 1 Data in Stage 1 D High Low d PLB Clock Xn Ww Read Clock Delayed AHA 7 TP lt Data out Stage 1 High Data out Stage 2 Low DatainatRDsp High X 2 X without ECC Low Data at pap W High D with ECC Kg D3 High Data out at ROSP h E mE 388 without ECC Low X D1 X D3 2 Propagation delay from Stage 2 i
33. burst devices 8 16 32 bit byte addressable data bus 32 bit address 4 GB address space Peripheral Device pacing with external Ready Latch data on Ready synchronous or asynchronous Programmable access timing per device 256 Wait States for non burst 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses Programmable CSon CSoff relative to address Programmable OEon WEon WEoff 1 to 4 clock cycles relative to CS Programmable address mapping External DMA Slave Support AMCC 11 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet External master interface Write posting from external master Read prefetching on PLB for external master reads Bursting capable from external master Allows external master access to all non EBC PLB slaves External master can control EBC slaves for own access and control Ethernet Controller Interface Ethernet support provided by the 440 interfaces to the physical layer but the PHY is not included on the chip Features include One to four 10 100 interfaces running in full and half duplex modes One full Media Independent Interface MII with 4 bit parallel data transfer Two Reduced Media Independent Interfaces RMII with 2 bit parallel data transfer Four Serial Media Independent Interfaces SMII Oneortwo GMII interfaces running in full and half duplex modes at 10Mb s or 100Mb s or 1000Mb s O
34. data 2 5V CMOS RTBIORxD4 RTBI Receive data GMCRxEr GMII Receive error GMC1RxCtl RGMII Receive control 3 3V tolerant TBIRxD9 TBI Receive data 2 5V CMOS RTBI1RxD4 RTBI Receive data GMCTxEn GMII Transmit data enable GMCOTxCtl RGMII Transmit control o 3 3V tolerant TBITxD8 TBI Transmit data 2 5V CMOS RTBIOTxD4 RTBI Transmit data GMCTxEr GMII Transmit error GMC1TxCtl RGMII Transmit control o 3 3V tolerant 6 TBITxD9 TBI Transmit data 2 5V CMOS RTBI1TxD4 RTBI Transmit data GMCTxClk 10 100 Mbps Transmit clock TBIRXCIK1 TBI Receive clock 1 MER 3 External Slave Peripheral Interface Used by the PPC440GxX to indicate that data transfers have 3 3V tolerant EES occurred 25v cMos Used by slave peripherals to indicate they are prepared to transfer 3 3V tolerant DMAR6q0 9 data 2 5V CMOS 1 5 3 3V tolerant 0 3 0 3 End Of Transfer Terminal Count UO 25V CMOS 1 5 Peripheral address bus used by PPC440GX when not in external PerAddr00 31 master mode otherwise used by external master UO 3 3V LVTTL 1 Note PerAddr00 is the most significant bit msb on this bus PerWBE0 3 External peripheral data bus byte enables UO 3 3V LVTTL 1 2 PerBLast Used by either the peripheral controller DMA controller or uo 3 3V LVTTL 1 4 external master to indicates the last transfer of a memory access 50 7 External peripheral device select O 3 3V LVTTL 2 52 AMCC Revision 1 20 June 9 2009 Data Sh
35. delay and the selection of Stage 1 Stage 2 or Stage 3 data for sampling at RDSP AMCC 83 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet DDR SDRAM Read Data Path Package pins Read Select SDRAMO TR1 Programmed Read Clock Delay PLB Clock FF Timing Tis Input setup time 0 2ns FF Flip Flop Input hold time 0 1 5 XL Transparent Latch Tp Propagation delay D to Q or C to Q 0 4ns maximum 84 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet UO Timing DDR SDRAM Toy and Tom Notes 1 Tgiy Delay from DOG at package pin to C on Stage 1 FF 2 Delay from data at package pin to D on Stage 1 FF 3 The time values for include 1 4 of a cycle at the indicated clock speed Clock Speed MHz Signal Name deg Signal Name BLD tea 166 DQS0 2 132 2 884 MemData00 07 0 779 1 502 166 DQS1 2 132 2 867 MemData08 15 0 789 1 521 166 DQS2 2 127 2 873 16 23 0 779 1 530 166 DQS3 2 116 2 851 MemData24 31 0 791 1 553 166 DQS4 2 100 2 845 MemData32 39 0 766 1 501 166 DQS5 2 103 2 844 MemData40 47 0 754 1 525 166 DQS6 2 144 2 902 MemData48 55 0 747 1 513 166 DQS7 2 110 2 864 MemData56 63 0 770 1 521 166 DQS8 2 122 2 860 0 7 0 759 1 464 200 1 942 2 365
36. is 3kQ to 3 3V 5 If not used must pull down recommended value is 1kQ to GND 6 Strapping input during reset pull up recommended value is 3kQ to 3 3V or pull down recommended value is 1kQ to GND required Signal Name Description UO Type Notes PCIXTRDY Indicates the target 8 ability to complete the current data vO 3 3V PCI 4 phase of the transaction DDR SDRAM Interface BAO 1 Bank Address supporting up to four internal banks 2 5V SSTL_2 BankSel0 3 Selects up to four external DDR SDRAM banks 2 5V SSTL_2 CAS Column Address Strobe 2 5V SSTL_2 0 3 Clock Enable One for each bank 2 5V SSTL_2 Memory write data byte lane masks MEMDM8 is the byte lane DM0 8 mask for the ECC byte lane o DQS0 8 a lane data strobe DQS8 is the data strobe for the ECC byte vo 25VSSTL 2 ECCO 7 ECC check bits 0 7 2 5VSSTL 2 MemAddr00 12 Memory address bus 2 5V SSTL_2 MemCIkOut0 MemClkOuto Subsystem clock 2 5V SSTL_2 MemData00 63 Memory data bus 2 5V SSTL_2 Voltage Ref MemVRef1 2 Memory reference voltage input Receiver RAS Row Address Strobe 2 5V SSTL_2 WE Write Enable 2 5VSSTL 2 Ethernet Interface EMCCD MII Collision detection EMC1RxErr RMII 1 Receive error GMCGTxClk 1000 Mbps Transmit clock up 3 3V tolerant GMCOTXxCIKk RGMII Transmit clock 2 5V CMOS
37. low time 40 of nominal period 60 of nominal period ns Notes 1 is the period in ns of the OPB clock The internal OPB clock runs at an integral divisor ratio of the frequency of the PLB clock The maximum OPB clock frequency is 83 33 MHz Refer to the Clocking chapter of the PPC440GX Embedded Processor User s Manual for details 2 When the PCI X interface is used to support a legacy PCI interface the maximum frequency is 66 66 MHz AMCC 67 440GX Power 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Input Setup and Hold Waveform Inputs Toy max Outputs min High Drive Float High Z Low Drive 68 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Input Setup and Hold Waveform for RGMII Signals GMCnRxCIk RGMII 1000Mb timing is with reference to the raising and falling edge of GMCnRxCIk RGMII 10 100Mb timing is with reference only to the raising edge of GMCnRxCIk Output Delay and Hold Timing Waveform for RGMII Signals GMCnTxClk 1 25V Outputs Toy maxi High Drive 4 Float High Z Low Drive RGMII 1000Mb timing is with reference to the raising and falling edge GMCnTxClk RGMII 10 100Mb timing is with reference only to the raising edge of GMCnTxClk AMCC 69 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2
38. pin that has GPIO capabilities acts as a GPIO or is used for another purpose Each GPIO output is separately programmable to emulate an open drain driver that is drives to zero tri stated if output bit is 1 AMCC 13 440GX Power 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Universal Interrupt Controller UIC Four Universal Interrupt Controllers UIC are available They provide control status and communications necessary between the external and internal sources of interrupts and the on chip PowerPC processor Note Processor specific interrupts for example page faults do not use UIC resources Features include 18 external interrupts 63 internal interrupts Edge triggered or level sensitive Positive or negative active Non critical or critical interrupt to the on chip processor core Programmable interrupt priority ordering Programmable critical interrupt vector for faster vector processing PLB Performance Monitor The PLB Performance Monitor PPM provides hardware for counting certain events associated with PLB transactions The contents of the counters can be read by software for analysis and enhancement of PLB performance or software debug The data includes identification and duration of the events 120 Messaging Unit IMU The IMU interfaces to the PLB as a master or slave and allows messages to be transferred between two PLB masters for example the 440 CPU and
39. processor performance and reduces the PLB load Cache coherency maintained by a hardware snoop mechanism or software Data Array and Tag Array parity Unified data and instruction cache 4 way set associative 36 bit addressing Full LRU replacement algorithm Write through look aside Use as Ethernet packet store allows Ethernet packets to be held for processing by the TAH unit PCI X Interface The PCI X interface allows connection of PCI and PCI X devices to the PowerPC processor and local memory This interface is designed to Version 1 0a of the PCI X Specification and supports 32 and 64 bit PCI X buses PCI 32 64 bit conventional mode compatible with PCI Version 2 3 is also supported Reference Specifications PowerPC CoreConnect Bus PLB Specification Version 3 1 PCI Specification Version 2 3 PCI Bus Power Management Interface Specification Version 1 1 Features include PCI X 1 0a Split transactions Frequency to 133MHz 32 64 bit bus PCI 2 3 backward compatibility Frequency to 66MHz 32 64 bit bus Can be the PCI Host Bus Bridge or an Adapter Device s PCI interface Internal PCI arbitration function supporting up to six external devices that can be disabled for use with an external arbiter Support for Message Signaled Interrupts 10 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Simple message passing capability Asynchronous to
40. time 160 _ ns EMCMDCIk output low time 160 _ ns EMCTxCIk input frequency MII RMII 2 5 5 25 50 MHz EMCTxCIKk period MII RMII 40 20 400 200 ns input high time 35 of nominal period ns input low time 35 of nominal period ns EMCRxClk input frequency MII RMII 2 5 5 25 50 MHz period MII RMII 40 20 400 200 ns input high time 35 of nominal period ns input low time 35 of nominal period ns GMCRefCIk input frequency 125 MHz GMCRefCIk period 8 ns GMCRefClk input high time 47 of nominal period 53 of nominal period ns GMCRefClk input low time 47 of nominal period 53 of nominal period ns PerClk output frequency for ext master or sync slaves 33 33 83 33 MHz PerClk period 12 30 ns PerClk output high time 50 of nominal period 66 of nominal period ns PerClk output low time 33 of nominal period 50 of nominal period ns UARTSerClk input frequency 1000 2 1 2 2 1 UARTSerClk period 2 2 ns 1 UARTSerClk input high time TopB 1 _ ns 1 UARTSerCIk input low time Topp 1 ns 1 66 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Peripheral Interface Clock Timings Continued Parameter Min Max Units Notes TmrClk input frequency 100 MHz TmrClk period 10 ns TmrClk input high time 40 of nominal period 60 of nominal period ns TmrClk input
41. 0 15 3 10 2 PerCIk PerPar0 3 2 7 1 6 0 0 15 3 10 2 PerCIk PerWBE0 3 1 8 1 5 1 0 15 3 10 2 PerClk PerCS0 7 na na 5 8 0 15 3 10 2 PerClk PerOE na na 5 5 0 15 3 10 2 PerClk PerWE na na 5 5 0 15 3 10 2 PerBLast 3 3 1 5 7 na 15 3 10 2 PerClk PerReady Revrinh 4 9 1 na na na na PerClk PerR W 2 5 1 5 7 na 15 3 10 2 PerClk DMAReq0 3 dc dc na na na na PerClk DMAAck0 3 na na 6 0 0 5 1 6 8 PerClk EOT0 3 TC0 3 dc dc 6 3 0 45 3 10 2 PerClk External Master Peripheral Interface PerClk na na na na 15 3 10 2 PLB Clk 1 ExtReset na na 6 7 0 15 3 10 2 PerClk HoldReq 2 8 1 na na na na PerClk HoldAck na na 5 5 0 15 3 10 2 PerClk ExtReq 1 5 1 na na na na PerClk ExtAck na na 5 7 0 15 3 10 2 PerClk BusReq na na 5 7 0 15 3 10 2 PerClk PerErr 2 5 1 na na 15 3 10 2 PerClk AMCC 77 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet DDR SDRAM UO Specifications The DDR SDRAM controller times its operation with internal PLB clock signals and generates MemClkOut0 from the PLB clock The PLB clock is an internal signal that cannot be directly observed However MemClkOut0 is the same frequency as the PLB clock signal and is in phase with the PLB clock signal Note MemClkOut0 can be advanced with respect to the PLB clock by means of the SDRAMO CLKTR program ming register In a typical system users advance MemClkOut by 90 This depends on the specific applica tion and requires a thorough understanding of the memory system in general
42. 00000000 0000000000000000000000 0000000000000000000000 000000000000000000000 00000000000 1 3 5 7 9 11131517 19 21 23 2 4 6 8 10 1214 16 18 20 22 24 0 8 0 04 Solderball x 552 0 7 0 1 2 31 max 2 20 max i 89 min 2 00 min 0 81 max 1 0 60 max gt 0 71 min 0 40 max 3 977 max CH E 0 857 max 0 907 max 0 779 min 0 779 min 3 707 max 3 379 min 3 179 min AMCC 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet 25mm 552 Ball Plastic FC PBGA Package Top View A1 Corner a A PowerPc 440 3xxfffx Lot Number AAAAAAAA Part Number Notes 1 All dimensions are in mm 2 Available in lead free ROHS compliant version Bottom View E 1 214 Ref OOOOOOOOOOOOOOOOOOOOOO 120 EN OOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOO D Dm TI e SD Je lt
43. 003 Remove IBM Confidential 12 02 2003 Revise DDR SDRAM UO section 01 13 2004 Correct TrcTS6 signal data pin assignment and multiplexing 02 12 2004 Restore Vpp OVpp voltage sequence restriction 02 25 2004 Add three Revision C part numbers 03 04 2004 Update number list Update dimensions on package drawing 03 25 2004 Correct signal description from input only to I O 05 12 2004 Add plastic package data new power data and update part number list 05 20 2004 Upgrade 533MHz ceramic part to 105 C rating 06 15 2004 Correct dimensions on ceramic package drawing 06 30 2004 Replace missing 533 MHz temperature range part Add information on minimum SysClk and TRST duration during power on reset 11 01 2004 Remove power sequence restrictions note from Absolute Maximum Rating table Restate power sequencing restrictions in Recommended DC Operating Conditions table Convert to AMCC format 12 09 2004 Restore Preliminary to document classification 06 16 2005 Add S no L2 cache support temperature range part numbers 07 01 2005 Add reduced lead ceramic and lead free plastic part numbers 10 17 2005 Clarify DDR SDRAM interface diagram Remove metal layer specification from technology description 11 07 2005 Add logo and number nomenclature to package drawing 12 22 2005 Update I O timing specs for EMCO 3TxD GMCORxD0 3 GMC1RxD0 3 GMCRxDV GMC1RxCtl GMCRxDO 7 GMCRxEr GMCCrS GMCTxD0 7 90 AMCC
44. 009 Data Sheet Specifications All Speeds Sheet 1 of 7 Notes 1 Ethernet interface meets timing requirements as defined by IEEE 802 3 standard 2 PCI X timings are for asynchronous operation up to 133MHz PCI X input setup time requirement is 1 2ns for 133MHz and 1 7ns for 66MHz PCI timings in parentheses are for asynchronous operation up to 66MHz PCI output hold time requirement is 1ns for 66MHz and 2ns for 33MHz 3 The clock frequency for RMII operation is 5OMHz 100ppm 4 The clock frequency for SMII operation is 125 MHz 100ppm 5 These are DDR signals that can change on both the positive and negative clock transitions Input ns Output ns Output Current mA Signal Setup Time Hold Time Valid Delay Hold Time O H VOL Clock Notes Tis min min Toy max min minimum minimum PCI X Interface PCIXADO00 63 Note 2 3 0 5 0 3 8 6 0 7 Note 2 0 5 1 5 2 PCIXC3 0 BE3 0 Note 2 3 0 5 0 3 8 6 0 7 Note 2 0 5 1 5 2 PCIXParLow Note 2 3 0 5 0 3 8 6 0 7 Note 2 0 5 1 5 2 PCIParHigh Note 2 3 0 5 0 3 8 6 0 7 Note 2 0 5 1 5 2 PCIXFrame Note 2 3 0 5 0 3 8 6 0 7 Note 2 0 5 1 5 2 0 5 1 5 async PCIXIRDY Note 2 3 0 5 0 3 8 6 0 7 Note 2 0 5 1 5 2
45. 14 PerData21 K24 PerData22 K22 PerData23 K20 PerData24 K18 PerData25 K16 PerData26 K14 PerData27 K11 PerData28 K09 PerData29 L19 PerData30 L17 PerData31 L16 PerErr Trc TS6 P21 External Master Peripheral 53 PerOE Mog External Slave Peripheral 52 36 AMCC Revision 1 20 June 9 2009 Data Sheet 440GX Power PC 440GX Embedded Processor Signals Listed Alphabetically Sheet 21 of 24 Signal Name Ball Interface Group Page T23 PerPar1 T22 External Slave Peripheral 52 PerPar2 W20 PerPar3 U20 PerReady RcvrInh 07 External Slave Peripheral 52 PerR W P05 External Slave Peripheral 52 PerWBEO T18 PerWBE1 v19 External Slave Peripheral 52 PerWBE2 W22 PerWBE3 w24 PerWE P02 External Slave Peripheral 52 RAS AD07 DDR SDRAM 50 Revrinh PerReady 07 System 55 RefVEn 102 System 55 SVpp U12 SVpp U15 SVpp W10 SVpp W17 SVpp AA08 Power 56 SVpp AA15 SVpp 06 SVpp AC13 SVpp AC21 SysCIk G22 System 55 SysErr 2 System 55 SysReset P10 System 55 TCK V22 JTAG 54 TDI Y24 JTAG 54 TDO Y22 JTAG 54 TestEn M05 System 55 TmrCIk 901 System 55 TMS AB22 JTAG 54 AMCC 37 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Signal
46. 200 RAS 0 263 0 311 3 439 0 987 200 WE 0 280 0 288 3 462 0 970 UO Timing DDR SDRAM Ten and Typ Notes 1 Tsp and Typ are measured under worst case conditions 2 The time values in the table include 1 4 of a cycle at the indicated clock speed 3 To obtain adjusted Tsp and Typ values for lower clock frequencies subtract 1 5 ns from the values at 166MHz in the table and add 1 4 of the cycle time for the lower clock frequency e g Tsp 1 5 0 25 Clock Speed MHz Signal Names Reference Signal Tsp ns Typ ns 166 MemData00 07 DMO DQS0 1 240 1 224 166 MemData08 15 DM1 DQS1 1 236 1 188 166 MemData16 23 DM2 DQS2 1 223 1 224 166 MemData24 31 DM3 DQS3 1 221 1 185 166 MemData32 39 DM4 DQS4 1 238 1 230 166 MemData40 47 DM5 DQS5 1 286 1 175 166 MemData48 55 DM6 DQS6 1 234 1 214 166 MemData56 63 DM7 DQS7 1 257 1 154 166 ECC0 7 DM8 DQS8 1 237 1 243 200 MemData00 07 DM0 DQS0 0 916 0 542 200 MemData08 15 DM1 DQS1 1 018 0 522 200 MemData16 23 DM2 DQS2 1 017 0 527 200 MemData24 31 DM3 DQS3 0 951 0 532 200 MemData32 39 DM4 DQS4 1 030 0 533 200 MemData40 47 DM5 DQS5 1 014 0 536 200 MemData48 55 DM6 DQS6 0 994 0 534 200 MemData56 63 DM7 DQS7 0 994 0 546 200 ECCO 7 DM8 DQS8 1 000 0 532 82 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet DDR SDRAM Read Operation The fol
47. 4049 PPC440GX PPC440GX 3CF667C 667MHz 5 25mm 552 CBGA F 0x51B21894 0x52054049 PPC440GX PPC440GX 3FF533C 533MHz 25mm 552 PBGA F 0x51B21894 0x52054049 PPC440GX PPC440GX 3FF667C 667MHz 25mm 552 PBGA F 0x51B21894 0x52054049 PPC440GX PPC440GX 3RF533C 533MHz 25mm 552 CBGA F 0x51B21894 0x52054049 PPC440GX PPC440GX 3RF667C 667MHz 5 25mm 552 CBGA F 0x51B21894 0x52054049 PPC440GX PPC440GX 3NF533C 533MHz 25mm 552 PBGA F 0x51B21894 0x52054049 PPC440GX PPC440GX 3NF667C 667MHz 25mm 552 PBGA F 0x51B21894 0x52054049 Notes 1 Package code C leaded ceramic F plastic R reduced lead ceramic ROHS compliant N lead free plastic ROHS compliant Om O N Case Temperature Range code C 40 C to 85 C The parts are shipped in a tray Revision code C rev 2 1 F rev 3 1 If the 667MHz ceramic parts are operated at 533 2 or less the operational temperature range is extended up to 105 C If the 667MHz plastic parts are operated at 533MHz or less the operational temperature range is extended up to 100 C Each part number contains a revision code This is the die mask revision number and is included in the part number for identification purposes only The PVR Processor Version Register and the JTAG ID register are software accessible read only and contain information that uniquely identifies the part Refer to the PPC440GX User s Manual for details on accessing these registers Order Part
48. 5 1 6 8 Te GMCol na na 5 1 6 8 m I GMCGTxClk na na na na na na mo GMCTxD0 7 na na 5 5 0 5 5 1 6 8 GMCGTxClk GMCTxEr na na 5 5 0 5 5 1 6 8 GMCGTxClk GMCTxEn na na 5 5 0 5 5 1 6 8 GMCGTxClk 72 AMCC Revision 1 20 June 9 2009 Data Sheet 440GX Power PC 440GX Embedded Processor Specifications All Speeds Sheet 4 of 7 Notes 1 Ethernet interface meets timing requirements as defined by IEEE 802 3 standard 2 PCI X timings are for asynchronous operation up to 133MHz PCI X input setup time requirement is 1 2ns for 133MHz and 1 7ns for 66 MHz PCI timings in parentheses are for asynchronous operation up to 66 MHz PCI output hold time requirement is 1ns for 66 MHz 2ns for 33MHz 3 The clock frequency for RMII operation is 50 MHz 100ppm 4 The clock frequency for operation is 125MHz 100ppm 5 These are DDR signals that can change on both the positive and negative clock transitions Input ns Output ns Output Current mA Signal Setup Time Hold Time Valid Delay Hold Time VOL Clock Notes Tis min minimum minimum Ethernet RGMII Interface 1 1 1 4 5 GMCORxD0 3 1 1 na na 5 1 6 8
49. AMEE APPLIED MICRO CIRCUITS CORPORATION Part Number 440GX Revision 1 20 June 9 2009 440GX Data Sheet Power PC 440GX Embedded Processor Features PowerPC 440 processor core operating up to 667 MHz with 32KB and D caches with parity checking On chip 256KB SRAM configurable as L2 Code store or Ethernet Packet store memory Clocking chapter in the PPC440GX Embedded Processor User s Manual for details Double Data Rate DDR Synchronous DRAM SDRAM interface operating up to 166MHz External Peripheral Bus 32 bits for up to eight devices with external mastering DMA support for external peripherals internal UART and memory PCI X V1 0a interface 32 or 64 bits up to 133MHz with support for conventional PCI V2 3 Two Ethernet 10 100 1000 Mbps half or full duplex interfaces Operational modes supported are SMII GMII RGMII TBI and RTBI Description Designed specifically to address high end embedded applications the PowerPC 440GX PPC440GX provides a high performance low power solution that interfaces to a wide range of peripherals by incorporating on chip power management features and lower power dissipation This chip contains a high performance RISC processor core DDR SDRAM controller configurable 256KB SRAM to be used as L2 cache or software controlled on chip memory PCI X bus interface Gigabit Ethernet interfaces TCP IP acceleration hardware 120 messag
50. C1 AC06 SVpp AD06 ECC2 AA07 DM5 07 ECCO 07 MemData44 AD07 RAS AA08 SVpp ABO8 MemData40 8 GND ADO8 MemData41 09 DM4 09 MemData45 09 DQS5 09 AA10 GND AB10 1 AC10 Vpp AD10 MemData39 11 AMGND 11 SC for MemClk AC11 DQS4 AD11 BankSel2 AA12 Vpp AB12 MemData29 AC12 GND AD12 MemData33 AA13 GND AB13 DQS3 AC13 SVpp AD13 MemData24 AA14 MemData16 AB14 DM2 14 0052 AD14 MemData25 AA15 SVpp 15 BankSelO AC15 GND AD15 MemData17 AA16 BAO 16 MemData11 AC16 DQS1 AD16 MemAddr5 AA17 GND AB17 MemData15 AC17 Vpp AD17 0 AA18 DM1 AB18 MemAddr6 AC18 MemData12 AD18 MemAddr4 AA19 Vpp AB19 MemData07 AC19 GND AD19 MemData06 AA20 MemData03 AB20 MemAddr3 AC20 DQS0 AD20 MemAddr01 AA21 GND AB21 MemData01 AC21 SVpp AD21 MemData00 AA22 ExtAck AB22 TMS AC22 MemData02 AD22 No ball AA23 OVpp AB23 ExtReq AC23 No ball AD23 No ball 24 BusReq AB24 No ball AC24 No ball AD24 No ball 46 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Signal Description The PPC440GX embedded controller is provided in 552 ball ball grid array package The following tables describe the package level pinout Pin Summary Group No of Pins Signal pins non multiplexed 343 Signal pi
51. MemData05 V17 MemData06 AD19 MemData07 AB19 MemData08 18 MemData09 V16 MemData10 Y17 MemData11 AB16 MemData12 AC18 MemData13 Y18 MembData14 R14 MemData15 AB17 DDR SDRAM 50 MemData16 AA14 MemData17 AD15 MemData18 T15 MemData19 V15 MemData20 Y16 MemData21 U14 MemData22 T13 MemData23 Y15 MemData24 AD13 MemData25 AD14 MemData26 V14 MemData27 Y13 MemData28 P12 MemData29 AB12 MemData30 Y12 MemData31 V12 AMCC 27 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Signals Listed Alphabetically Sheet 12 of 24 Signal Name Ball Interface Group Page MemData32 W11 MemData33 AD12 MemData34 Y10 MemData35 T12 MemData36 U11 MemData37 T11 MemData38 T10 MemData39 AD10 MemData40 8 MembData41 AD08 MemData42 R11 MemData43 Y07 MemData44 AC07 MemData45 AB09 MemData46 Y06 MemData47 Y08 DDR SDRAM 50 MemData48 AA01 MemData49 AA03 MemData50 AB02 MemData51 Y01 MemData52 AB03 MemData53 Y02 MemData54 V07 MemData55 V01 MemData56 57 907 MemData58 WO MemData59 W03 MemData60 V06 MemData61 T07 MemData62 W05 MemData63 U05 MemVRef1 T14 DDR SDRAM 50 MemVRef2 09 28 Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Signals Listed Alphabetically Sheet 13 of 24
52. Name Ball Interface Group Page PCIXCO BEO F14 PCIXC1 BE1 E16 PCIXC2 BE2 C19 20 PCI X 49 PCIXCA BE4 C08 C03 G09 PCIXC7 BE7 F09 PCIXCap L23 PCI X 49 PCIXCIk E03 PCI X 49 PCIXDevSel E13 PCI X 49 PCIXFrame A11 PCI X 49 PCIXGntO E22 PCIXGnt1 IRQ12 C22 PCIXGnt2 N22 PCI X 49 PCIXGnt3 M18 PCIXGnt4 R22 PCIXGnt5 P19 PCIXIDSel G07 PCI X 49 PCIXINT 07 PCI X 49 PCIXIRDY E12 PCI X 49 PCIXM66En 14 PCI X 49 PCIXParHigh 104 PCI X 49 PCIXParLow F16 PCI X 49 PCIXPErr A17 PCI X 49 PCIXReq0 E24 PCIXReq1 IRQ11 E21 PCIXReq2 E20 PCI X 49 PCIXReq3 R20 PCIXReq4 G23 PCIXReq5 R18 PCIXReq64 E09 PCI X 49 PCIXReset M24 PCI X 49 PCIXSErr A18 PCI X 49 AMCC 33 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Signals Listed Alphabetically Sheet 18 of 24 Signal Name Ball Interface Group Page PCIXStop L12 PCI X 49 PCIXTRDY C12 PCI X 49 011 PerAddr01 C11 PerAddr02 B11 PerAddr03 A12 PerAddr04 A19 PerAddr05 D18 PerAddr06 E11 PerAddr07 PerAddr08 N01 PerAddr09 E14 PerAddr10 C20 PerAddr11 A16 PerAddr12 A13 PerAddr13 B14 PerAddr14 C14 PerAddr15 D14 External Slave Peripheral PerAddr16 B20 Note PerAddr00 is the most signific
53. PCI X Features include Three messaging methods 4 Message registers 2 inbound 2 outbound 2 Doorbell registers 1 inbound 1 outbound 4 Circular queues 2 inbound 2 outbound Up to 7 different interrupt outputs generated Support for interrupt masking JTAG Features include EEE 1149 1 Test Access Port RISCWatch Debugger support JTAG Boundary Scan Description Language BSDL 14 AMCC Revision 1 20 June 9 2009 Data Sheet 440GX Power PC 440GX Embedded Processor 25mm 552 Ball Ceramic CBGA Package Top View A1 Corner a A Lot Number Bottom View D Dm TI e SD Je lt gt gt rz 2 AMEE PPC440GX 3xxfffx Capacitor Notes 1 All dimensions are in mm Part Number 2 RoHS compliant reduced lead package available 3 Reduced lead package dimensions are in parentheses dimension 25 0 0 2 23 0 OOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOO OO OO OO OO 000000000000000000000000 0O00000000000000000000000 000000000000000000000000 000000000000000000000000 000000000000000000000000 000000000000000000000000 000000000000000000000000 0000000000000000
54. Peripheral Bus OPB and the Device Control Register Bus DCR The high performance high bandwidth cores such as the PowerPC 440 processor core the DDR SDRAM memory controller and the PCI X bridge connect to the PLB The OPB hosts lower data rate peripherals The daisy chained DCR provides a lower bandwidth path for passing status and control information between the processor core and the other on chip cores Features include e PLB 128 bit implementation of the PLB architecture Separate and simultaneous read and write data paths 64 bit address Simultaneous control address and data phases Four levels of pipelining Byte enable capability supporting unaligned transfers 32 64 byte burst transfers 166MHz maximum 5 2GB s simultaneous read and write Processor bus clock ratios of N 1 and N 2 AMCC 9 440GX Power 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet e OPB Dynamic bus sizing 32 16 and 8 bit data path 36 bit address 83 33MHz maximum 333 MB s e DCR 32 bit data path 10 bit address On Chip SRAM Features include Four banks of 64KB each for a total of 256KB Configurable as either Code L2 cache or software controlled on chip memory or SRAM Memory cycles supported Single beat read and write 1 to 16 bytes 32 and 64 byte burst transfers Guarded memory accesses Sustainable 2 6 GB s peak bandwidth at 166 MHz Use as an L2 cache improves
55. SysClk PLL analog voltage 56 BAO AA16 DDR SDRAM 50 BA1 ADO9 0 15 Bank Gel W14 DDR SDRAM 50 BankSel2 AD11 BankSel3 AD05 BEO PCIXCO F14 BE1 PCIXC1 E16 BE2 PCIXC2 C19 BE3 PCIXC3 F20 PCI X 49 BE4 PCIXC4 C08 BE5 PCIXC5 C03 BE6 PCIXC6 G09 BE7 PCIXC7 F09 BusReq TrcTS1 AA24 External Master Peripheral 53 CAS 05 DDR SDRAM 50 CIKEnO AD17 CIKEn1 AB10 DDR SDRAM 50 ClkEn2 Y09 ClkEn3 WO AMCC 17 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Signals Listed Alphabetically Sheet 2 of 24 Signal Name Ball Interface Group Page DMO T16 DM1 AA18 DM2 AB14 DM3 P13 DM4 AA09 DDR SDRAM 50 DM5 AA07 DM6 Y03 DM7 DM8 5 DMAAckO N05 DMAAck1 P07 DMAAck2 GMCRxD0 GMCORxDO P06 External Slave Peripheral 52 TBIRxDO RTBIORxDO DMAAck3 GMCRxD1 GMCORxD1 11 TBIRxD1 RTBIORxD1 DMAReqO R03 DMAReq1 M11 DMAReq2 GMCRxDV N11 External Slave Peripheral 52 TBIRxD8 RTBIORxD4 DMAReq3 GMCTxEn GMCOTxCtI Pot TBITxD8 RTBIOTxD4 DQS0 AC20 DQS1 AC16 DQS2 AC14 DQS3 AB13 DQS4 AC11 DDR SDRAM 50 DQS5 AC09 DQS6 Y04 DQS7 T01 DQS8 05 Drvrinh2 A05 System 55 18 AMCC Revision 1 20 June 9 2009 Data Sheet 440GX Power PC 440GX Embedded Processor Signals Listed Alphabetically Sheet 3 of 24
56. TC3 J17 PerData12 K17 GND L17 PerData30 M17 OVpp 418 PerData11 K18 PerData24 118 IRQ03 M18 PCIXGnt3 J19 PerData10 K19 OVpp L19 PerData29 M19 GND J20 PerData9 K20 PerData23 120 IRQO1 M20 IRQ05 J21 PerData8 K21 GND L21 PerAddr18 M21 J22 PerData7 K22 PerData22 L22 PerAddr19 M22 PerAddr20 423 PerData6 K23 Vpp 123 PCIXCap M23 GND 924 ASGND K24 PerData21 L24 PerAddr22 M24 PCIXReset AMCC 43 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Signals Listed by Ball Assignment Sheet 4 of 6 Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name NO1 PerAddr08 P01 DMAReq3 RO1 TrcTS6 0087 No2 GND P02 PerWE R02 Vpp TO2 SysErr N03 PerAddr28 TrcTS1 R03 03 PerCS5 NO4 Von P04 GMCRxEr RO4 GND T04 TrcTSO N05 DMAAckO 05 PerR W RO5 TrcCIk 05 TrcES4 N06 GND DMAAck2 RO6 OVpp 06 TrcTS5 N07 PerReady P07 DMAAck1 RO7 TrcTS2 TO7 MemData61 N08 OVpp 08 TrcES3 Ros GND 08 MemData56 N09 TrcES2 9 TrcTS3 RO9 TrcTS4 TO9 MemVRef2 N10 GND P10 SysReset R10 Vpp T10 MemData38 N11 DMAReq2 11 DMAAck3 R11 MemData42 T11 MemData37 N12 Vpp P12 MemData28 R12 GND T12 MemData35
57. Transmit data O 3 3V LVTTL 4 UARTO_DCD UARTO Data Carrier Detect 3 3V LVTTL UARTO_DSR UARTO Data Set Ready 3 3V LVTTL 6 UARTO CTS UARTO Clear To Send 3 3V LVTTL 1 4 AMCC 53 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Signal Functional Description Sheet 6 of 8 Notes 1 Receiver input has hysteresis 2 Must pull up recommended value is 3kQ to 3 3V 3 Must pull down recommended value is 1kQ 4 If not used must pull up recommended value is 3kQ to 3 3V 5 If not used must pull down recommended value is 1kQ to GND 6 Strapping input during reset pull up recommended value is 3kQ to 3 3V or pull down recommended value is 1kQ to GND required Signal Name Description y o Type Notes UARTO DTR UARTO Data Terminal Ready 3 3V LVTTL 4 UARTO_RTS UARTO Request To Send 3 3V LVTTL 4 UARTO_RI UARTO Ring Indicator 3 3V LVTTL 1 4 UART1_Rx UART1 Receive data UO 3 3V LVTTL 1 4 UART1_Tx UART1 Transmit data 1 0 3 3V LVTTL 1 4 URRTI DSR CTS 2 2 awivmL UART1_RTSIDTR detorminedby a DCR register bitseting VO 33VIVTTL 1 4 Peripheral Interface Serial Clock UO 3 3V LVTTL 1 2 IICOSDA Serial Data UO 3 3V LVTTL 1 2 IIC1SCIk IIC1 Serial Clock UO 3 3V 1 2 IIC1SDA IIC1 Serial Data UO 3 3V 1 2 Interrupts Interface IRQ00 10 Ex
58. a dea dhe bu PHS OU EA ORR ae cm d 61 DC Power Supply 03 62 Clocking Specifications 63 Peripheral Interface Clock Timings 2 66 Specifications All Speeds 70 500 2 667 2 77 DDR SDRAM Output Driver Specifications 79 Timing DDR SDRAM Te 81 Timing DDR SDRAM Tsa and Tun 81 Timing DDR SDRAM 2 82 Timing DDR SDRAM 4 85 Strapping Pin Assignments 89 AMCC 3 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Ordering and PVR Information For information on the availability of the following parts contact your local AMCC sales office Order Part Numbers None gea Rotas and Key drew Frequshey Package Level Pipo em PPC440GX PPC440GX 3CF533C 533MHz 25mm 552 CBGA F 0x51B21894 0x5205
59. ages in a convection environment are as follows Airflow Parameter Symbol Package ft min m sec Unit Notes 0 0 100 0 51 200 1 02 Ceramic lt 0 1 lt 0 1 lt 0 1 C W 1 Junction to case thermal resistance Plastic 1 2 1 2 1 2 C W 1 3 Case to ambient thermal resistance w o heat 6 ceramig 18 9 4 ma GIW 2 i CA sink Plastic 20 8 ecw 2 3 Range Min Nom Max Ceramic 1 5 2 2 C W 4 Junction to ball typical Plastic 8 2 C W Notes 1 Case temperature is measured at top center of case surface with device soldered to circuit board 2 The case to ambient thermal resistance is measured JEDEC JESD51 6 standard environment and may not accurately predict thermal performance in production equipment environments The operational case temperature must be maintained 3 Modeled on standard JEDEC 252 card 50x50mm 4 1 5 C W is the theoretical jg using an infinite heat sink The larger number applies to the module mounted on 1 8mm thick 2P card using 10z copper power planes with an effective heat transfer area of 75mm 58 AMCC Revision 1 20 June 9 2009 Data Sheet 440GX Power PC 440GX Embedded Processor Heat Sink Mounting Information Ceramic Package Only Proper thermal design is primarily dependent upon multiple system level effects that is the effects of the heat sink the air flow and the thermal interfac
60. ant bit msb on this bus PerAddr17 L15 PerAddr18 L21 PerAddr19 L22 PerAddr20 M22 PerAddr21 M01 PerAddr22 L24 PerAddr23 P24 PerAddr24 T19 PerAddr25 R24 PerAddr26 U22 PerAddr27 U24 PerAddr28 NO3 PerAddr29 V20 PerAddr30 V23 PerAddr31 V21 34 AMCC Revision 1 20 June 9 2009 Data Sheet 440GX Power PC 440GX Embedded Processor Signals Listed Alphabetically Sheet 19 of 24 Signal Name Ball Interface Group Page PerBLast C07 External Slave Peripheral 52 PerCIk U18 External Master Peripheral 53 80 E17 PerCS1 L10 PerCS2 V04 PercS3 T24 SE External Slave Peripheral 52 PerCS4 L03 PerCS5 T03 PerCS6 L13 PerCS7 U03 AMCC 35 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Signals Listed Alphabetically Sheet 20 of 24 Signal Name Ball Interface Group Page PerData00 H24 PerData01 H22 PerData02 H20 PerData03 G20 PerData04 G19 PerData05 H18 PerData06 J23 PerData07 J22 PerData08 J21 PerData09 J20 PerData10 J19 PerData11 J18 PerData12 J17 PerData13 J15 PerData14 J14 PerData15 J13 External Slave Peripheral PerData16 J12 Note PerData00 is the most significant bit msb on this bus PerData17 J11 PerData18 J10 PerData19 J09 PerData20 L
61. ccordance with operating conditions shown in the table Recommended DC Operating Conditions AC specifications are characterized with Vpp 1 5V 85 and 10pF test load as shown in the figure to the right Output Pin 62 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Clocking Specifications Symbol Parameter Minimum Maximum Units Notes SysClk Input Fo Frequency 33 33 83 33 MHz Tc Period 12 30 ns Tcs Edge stability cycle to cycle jitter _ 0 15 ns High time 40 of nominal period 60 of nominal period ns TeL Low time 40 of nominal period 60 of nominal period ns Note Input slew rate gt 1V ns PLL VCO Fo Frequency 600 1334 MHz Period 0 75 1 66 ns Processor Clock CPU Clock 333 667 MHz 1 Period 1 5 3 ns MemCIkOut and PLB Fc Frequency 533 667 MHz 100 166 66 MHz To Period 533 667 MHz 6 10 ns Tcu High time 4596 of nominal period 55 of nominal period ns OPB Clock Fc Frequency 66 66 83 33 MHz 2 Tc Period 12 15 ns 2 MAL Clock Fc Frequency 83 33 100 MHz 3 Tc Period 10 12 ns 3 Notes 1 The maximum supported processor clock frequency for any part is specified in the part number see Ordering and PVR Information on page 4 2 In order to support 1Gbps Ethernet data rate the minimum
62. dded Processor Data Sheet PowerPC 440 Processor Core The PowerPC 440 processor core is designed for high end applications RAID controllers SAN ISCSI routers switches printers set top boxes etc It is the first processor core to implement the Book E PowerPC embedded architecture and the first to use the 128 bit version of IBM s on chip CoreConnect Bus Architecture Features include Up to 667 MHz operation PowerPC Book E architecture e 32KB 32KB D cache UTLB Word Wide parity on data and tag address parity with exception force Three logical regions in D cache locked transient normal D cache full line flush capability 41 bit virtual address 36 bit 64 GB physical address Superscalar out of order execution 7 stage pipeline 3 execution pipelines Dynamic branch prediction Memory management unit 64 entry full associative unified TLB with parity Separate instruction and data micro TLBs Storage attributes for write through cache inhibited guarded and big or little endian Debug facilities Multiple instruction and data range breakpoints Data value compare Single step branch and trap events Non invasive real time trace interface 24 DSP instructions Single cycle multiply and multiply accumulate 32 32 integer multiply 16x 16 gt 32 bit MAC Internal Buses The PowerPC 440GX features three IBM standard on chip buses the Processor Local Bus PLB the On Chip
63. e material To reduce the die junction temperature heat sinks may be attached to the package by several methods adhesive spring clips to the printed circuit board or package or a mounting clip and screw assembly When attaching heat sinks it is important to avoid placing excessive mechanical stress on bonding of the chip to the substrate and the package to the board Heat Sink Attached With Spring Clip Heat sink gt Heat sink clip Thermal grease CBGA package gt Printed circuit J board Spring clip to package Static compression spring force 2 27 kg maximum Heat Sink Attached With Adhesive Heat sink Adhesive CBGA package Printed circuit board Weight force Heat sink Heat sink clip Thermal grease CBGA gt package Printed circuit board Spring clip to board Static compression spring 2 27 kg maximum Note 1 Force is limited by allowable compression on the die Allowable package compression force is 4 4kg Printed circuit board package Adhesive Heat sink gt Heat sink weight force 60g maximum Important All of the guidelines indicated in the above diagrams must be evaluated and adjusted to account for the shock and vibration effects of any particular application AMCC 59 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Reco
64. ee EE 5 PowerPC 440 Processor Core 2 4 9 Internal BUSES RD PRR we we xu eee byw ea Pa Le des 9 PCI X Interface Od pe Whe S SQ be eA eR Sa Peed ea dad ak ee eae ee 10 DDR SDRAM Memory 54 1 11 EE n UE NEEN 10 External Peripheral Bus Controller ERC 11 Ethernet Controller Interface 12 DMA Controller ssa ic ed mete 5 ee Rx ee aa QM 12 Serial Port 2 5 Pee ed ad SCH ENEE wayta Ge e aa a wu e ea AUR e wd 13 II C B s InterfaCce xou pe ue E E PUR CEPS Y a ee ew edo dd 13 General Purpose Timers GPT 13 General Purpose IO GPIO Controller 13 Universal Interrupt Controller UIC 14 PLB Performance Monitor 14 120 Messaging Unit IMU 1 14 My car 14 SIL 17 Signal xe br Ee ER RE ea ewes Edd 47 Heat Sink Mounting Information Ceramic Package
65. eet 440GX Power PC 440GX Embedded Processor Signal Functional Description Sheet 5 8 Notes 1 Receiver input has hysteresis 2 Must pull up recommended value is 3kQ to 3 3V 3 Must pull down recommended value is 1kQ 4 If not used must pull up recommended value is 3kQ to 3 3V 5 If not used must pull down recommended value is 1kQ to GND 6 Strapping input during reset pull up recommended value is 3kQ to 3 3V or pull down recommended value is 1kQ to GND required Signal Name Description y o Type Notes Peripheral data bus used by PPC440GX when not in external PerData00 31 master mode otherwise used by external master UO 3 3 LVTTL 1 Note PerData00 is the most significant bit msb on this bus Used by either peripheral controller or DMA controller depending PerOE upon the type of transfer involved When the PPC440Gx is the 3 3 LVTTL 2 bus master it enables the selected device to drive the bus PerPar0 3 External peripheral data bus byte parity VO 3 3 LVTTL 1 PerReady Used by a peripheral slave to indicate it is ready to transfer data 3 3 LVTTL Used by the PPC440GX when not in external master mode as output by either the peripheral controller or DMA controller depending upon the type of transfer involved High indicates PerR W read from memory low indicates a write to memory VO 3 3V LVTTL 1 2 Otherwise it u
66. encies use 1 4 of the cycle time for the lower clock frequency and add minimum at 166MHz 0 25Tcyc ns Tsa ns Tua ns Clock Speed MHz Signal Name Minimum Maximum Minimum Minimum 166 MemAddr00 12 0 184 0 592 3 908 1 684 166 BAO 1 0 439 0 683 3 817 1 939 166 BankSel0 3 0 249 0 779 3 721 1 749 166 ClkEn0 3 0 344 0 724 3 776 1 844 166 CAS 0 319 0 561 3 939 1 819 166 RAS 0 373 0 683 3 817 1 873 166 WE 0 393 0 639 3 816 1 893 200 MemAddr00 12 0 283 0 307 3 443 0 967 200 BAO 1 0 286 0 353 3 397 0 964 200 BankSel0 3 0 270 0 321 3 429 0 980 AMCC 81 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Timing DDR SDRAM Tsa and THa Sheet 2 of 2 Notes 1 is referenced to MemClkOut0 0 and Ty are referenced to MemClkOut0 90 2 To obtain adjusted Ts values for lower clock frequencies use 3 4 of the cycle time for the lower clock frequency and subtract maximum at 166MHz 0 75 3 To obtain adjusted Ty values for lower clock frequencies use 1 4 of the cycle time for the lower clock frequency and add minimum at 166MHz 0 25 ns Tsa ns Tua ns Clock Speed MHz Signal Name Minimum Maximum Minimum Minimum 200 0 3 0 280 0 298 3 452 0 970 200 CAS 0 270 0 294 3 456 0 980
67. h be below 0 4V before a new power up cycle is started LPDL is least positive down level MPUL is most positive up level Case temperature Tc is measured at top center of case surface with device soldered to circuit board If the 667MHz ceramic parts are operated at 533MHz or less the operational temperature range is extended up to 105 C If the 667MHz plastic parts are operated at 533MHz or less the operational temperature range is extended up to 100 C Input Capacitance Parameter Symbol Maximum Unit Notes Group 1 2 5V SSTL I O 12 pF Group 2 3 3V LVTTL I O CiN2 12 pF Group 3 PCI X I O Cina 12 pF Group 4 Receivers Cina 9 pF Group 5 3 3V tolerant CMOS I O Cins 16 pF AMCC 61 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet DC Power Supply Loads Parameter Symbol Frequency MHz Typical Maximum Unit Notes 533 1 37 1 69 A 2 Vpp active operating current Ipp 667 1 49 1 8 A 2 533 58 111 mA 2 OVpp active operating current lopp 667 58 111 mA 2 533 544 749 mA 2 SVpp active operating current Ispp 667 568 837 mA 2 AXV pp input current lADD 33 mA 1 2 Notes 1 See Absolute Maximum Ratings on page 57 for filter recommendations 2 The maximum current values listed above are not guaranteed to be the highest obtainable These values are dependent on many factors including the type of appl
68. habetically Sheet 23 of 24 Signal Name Ball Interface Group Page UARTO Tx L11 UART Peripheral 53 UART1 DSR CTS GPIO14 G06 UART Peripheral 53 UART1 RTS DTR GPIO15 E05 UART Peripheral 53 UART1 Rx GPIO12 C18 UART Peripheral 53 UART1 Tx GPIO13 J46 UART Peripheral 53 UARTSerClk A09 UART Peripheral 53 B08 Vpp B15 Vpp D06 Vpp D13 Vpp D21 04 Vpp F12 Vpp F19 Vpp 2 Vpp H17 Power 56 K12 K15 K23 M06 Vpp M10 Vpp M13 M21 N04 2 VDD N15 AMCC 39 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Signals Listed Alphabetically Sheet 24 of 24 Signal Name Ball Interface Group Page 19 R02 Vpp R10 Vpp R13 Vpp U08 Vpp U23 Vpp W06 Power 56 Von W13 W21 Vpp AA04 Vpp AA12 Vpp AA19 Vpp AC10 Vpp AC17 WE Y05 DDR SDRAM 50 40 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet In the following table only the primary default signal name is shown for each pin Multiplexed or multifunction signals are marked with an asterisk To determine what signals or functions are multiplexed on those pins look up the primary signal name in Signals Listed Alphabetically on page 17 Signals Listed by Ball Assignment Sheet 1 of 6
69. he IICO bus see Serial EEPROM below Some of the default values can be altered by strapping on external pins see Strapping below Strapping While the SysReset input pin is low system reset the state of certain I O pins is read to enable certain default initial conditions prior to PPC440GxX start up The actual capture instant is the nearest SysClk edge before the deassertion of reset These pins must be strapped using external pull up logical 1 recommended value is 3kQ to 3 3V or pull down logical 0 recommended value is 1 kQ to GND resistors to select the desired default conditions They are used for strap functions only during reset Following reset they are used for normal functions The following table lists the strapping pins along with their functions and strapping options Strapping Pin Assignments Ball Strapping Function Option V24 02 107 UARTO_DCD UARTO_DSR GMC1TxEr Serial device is disabled Each of the four options A 0 0 0 D is a combination of boot source boot source width and clock frequency specifications Refer to the IIC B 0 x 1 Bootstrap Controller chapter in the PPC440GX Embedded Processor User s Manual for details C 0 1 0 D 1 0 0 Serial device is enabled The option being 0x54 1 0 1 selected is the IICO slave address that will respond with strapping data 0x50 1 1 1 Serial EEPROM During reset initial conditions other than those
70. ications running clock rates use of internal functional capabilities external interface usage case temperature and the power supply voltages Your specific application can produce significantly different results logic current and power are primarily dependent on the applications running and the use of internal chip functions DMA PCI Ethernet and so on OVpp I O current and power are primarily dependent on the capacitive loading frequency and utilization of the external buses The following information provides details about the conditions under which the listed values were obtained a In general the values are measured using a PPC440GX Evaluation Board set for Ethernet mode 4 PCI X running at 100 MHz with an Intel Pro 1000 an Agilent Test card an EBMI test card a UART wrap plug and one 128MB Micron DIMM while running applications designed to maximize CPU power consumption An external PCI master heavily loads the PCI bus with transfers targeting SDRAM while the internal DMA controller further increases SDRAM bus traffic System clock rates are set as follows SysClk 33MHz CPU 667 MHz PLB 167 MHz and OPB EBC 83MHz b Typical current is characterized at 1 5V OVpp 3 3V SVpp 2 5V and Tc 47 C c Maximum current is characterized at 1 6V OVpp 3 6V SVpp 2 7V and Tc 85 C 3 Estimated values Test Conditions Clock timing and switching characteristics are specified in a
71. ing unit control for external ROM and peripherals DMA with scatter gather support serial ports IIC interface and general purpose Selectable processor bus clock ratios Refer to the TCP IP Acceleration Hardware TAH provided for 10 100 1000 Mbps ports that performs checksum processing TCP segmentation and includes support for jumbo frames Programmable Interrupt Controller supports interrupts from a variety of sources 20 Messaging unit for message transfer between the CPU and PCI X Programmable General Purpose Timers GPT Two serial ports 16750 compatible UART Two interfaces General Purpose I O GPIO interface available JTAG interface for board level testing Processor can boot from PCI memory Available in ceramic RoHs and non RoHS compliant versions and plastic packages RoHS and non RoHS compliant versions Technology CMOS Cu 11 0 13 Packages 25mm 552 ball Ceramic Ball Grid Array CBGA or Plastic Ball Grid Array PBGA in standard or RoHS compliant versions Power estimated Less than 4W typical 533 MHz 5W typical 667 MHz Supply voltages required 3 3V 2 5V 1 5V AMCC 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Contents Ordering PVR Information 4 4 Address Maps c uuu aaah ot dad CRURA ee Seales SEN RACE RUN Pelee OG S e
72. it data RTBIOTxDO 1 RTBI 0 Transmit data EMCRxDV Receive data valid EMC1CrSDV RMII 1 Carrier sense data valid GMCTxD4 GMII Transmit data VO 3 3V tolerant GMC1TxDO RGMII 1 Transmit data 2 5V CMOS TBITxD4 TBI Transmit data RTBI1TxDO RTBI 1 Transmit data MII Receive clock GMCTxD5 GMII Transmit data 3 3V tolerant GMC1TxD1 RGMII 1 Transmit data UO 25V CMOS TBITxD5 TBI Transmit data i RTBI1TxD1 RTBI 1 Transmit data EMCRxErr Receive error EMCORxErr RMII 0 Receive error GMCTxD6 GMII Transmit data 3 3V tolerant GMC1TxD2 RGMII 1 Transmit data 2 5V CMOS TBITxD6 TBI Transmit data RTBI1TxD2 RTBI 1 Transmit data Transmit clock 3 3V tolerant 5 EMCRefClk RMII SMII Reference clock 2 5V CMOS EMCTxDO0 3 MII Transmit data EMCOTxDO 1 RMII 0 Transmit data EMC1TxD0 1 RMII 1 Transmit data EMCOTxD 0 Transmit data EMC1TxD 1 Transmit data 3 3V tolerant EMC2TxD 2 Transmit data 25V CMOS EMC3TxD 3 Transmit data i GMCTxD2 3 GMII Transmit data GMCOTxD2 3 RGMII 0 Transmit data TBITxD2 3 TBI Transmit data RTBIOTxD2 3 RTBI 0 Transmit data EMCTxEn Transmit data enabled EMCOTxEn RMII 0 Transmit data enabled EMCSync Sync signal EMCTxErr Transmit error EMC1TxEn RMII Transmit data enabled Receive clock up 3 3V tolerant GMCORXCIk RGMII Receive clock 2 5V CMOS
73. l up recommended value is 3kQ to 3 3V or pull down recommended value is 1kQ to GND required Signal Name Description y o Type Notes PCI X Interface PCIXAD00 63 Address Data bus bidirectional UO 3 3V PCI PCIXCO 7 BEO 7 PCI X Command Byte Enables PCIXCap Capable of PCI X operation 3 3V LVTTL 5 PCIX133Cap PCI X devices are 133 MHz capable O 3 3V PCI Provides timing to the PCI interface for PCI transactions PCIXClk Note If the PCI X interface is not being used drive this pin with a 3 3V PCI 3 3V clock signal at a frequency between 1 and 66MHz PCIXDevSel Indicates the driving device has decoded its address as the target VO 3 3V PCI 4 of the current access Driven by the current master to indicate beginning and duration of VO 3 3V PCI 4 an access Indicates that the specified agent is granted access to the bus PCIXGntO When using an external PCI PCI X arbiter connect the external 3 3V PCI 4 arbiter s Grant line to this signal PCIXGnt1 Indicates that the specified agent is granted access to the bus VO 3 3V PCI 4 PCIXGnt2 5 Indicates that the specified agent is granted access to the bus 3 3V PCI Used as a chip select during configuration read and write PCIXIDSel transactions 3 3V PCI 5 PCIXINT Level sensitive PCI interrupt 3 3V PCI PCIXIRDY Indicates initiating agent s ability to complete the current data up 3 3V PCI 4 phase of the transaction PCIXM66En Capable of 66 MH
74. lowing examples of timing for DDR SDRAM read operations are based on the relationship between the incoming data and the PLB clock signal Since the PLB clock cannot be directly observed the delay of MemClkOut 0 relative to the PLB clock is provided The internal Read Clock signal like MemCIkOutO is derived from the PLB clock and can be delayed relative to the PLB clock by programming the and fields the SDRAMO TR1 register The delay be programmed from 0 to 1 2 cycle in steps using RDCT Setting RDCD results in a 1 2 cycle delay plus the value set The delay of Read Clock relative to the PLB clock shown below assumes the programmable Read Clock delay is set to zero DDR SDRAM MemCIkOut0 and Read Clock Delay PLB Clk A wo MemCIkOutO 0 567 ps 1705ps Read Clock A lt Trp Trpmin 6 5 183 DS In operation following the receipt of an address and read command from the PPC440GX the SDRAM generates data and the DQS signals coincident with MemClkOut0 The data is latched into the PPC440GX using a 005 signal that is delayed 1 4 of a cycle In order to accommodate timing variations introduced by the system designs using this chip the three stage data path shown below is used to eliminate metastability and allow data sampling to be adjusted for minimum latency This adjustment requires programming the Read Clock
75. mmended DC Operating Conditions Device operation beyond the conditions specified is not recommended Extended operation beyond the recommended conditions can affect device reliability Parameter Symbol Minimum Typical Maximum Unit Notes Logic Supply Voltage 533MHz Von 1 4 1 5 1 6 V 4 Logic Supply Voltage 667 MHz Vpp 1 5 1 55 1 6 V 4 UO Supply Voltage OVpp 3 0 3 3 3 6 V 4 DDR SDRAM Supply Voltage DDR clock up to 166MHz SVpp 2 3 2 5 2 7 V 4 PLL Supply Voltages 533MHz AxVpp 1 4 1 5 1 6 V 3 PLL Supply Voltage 667 MHz AxVpp 1 5 1 55 1 6 V 3 DDR SDRAM Reference Voltage SVREF 1 15 1 25 1 35 V 3 Input Logic High 2 5V SSTL SVggr 0 18 SVpp 0 3 V 2 Input Logic High 2 5V CMOS 3 3V tolerant receiver y 1 7 V Input Logic High 3 3V PCI X 0 50Vpp OVpp 0 5 V 1 Input Logic High 3 3V LVTTL 2 0 3 6 V Input Logic Low 2 5V SSTL 0 3 SVper 0 18 Input Logic Low 2 5V CMOS 3 3V tolerant receiver T 0 7 V Input Logic Low 3 3V PCI X 0 5 0 350Vpp V 1 Input Logic Low 3 3V LVTTL 0 0 8 V Output Logic High 2 5V SSTL 1 95 SVpp V Output Logic High 2 5V CMOS 3 3V tolerant receiver 2 0 V Output Logic High 3 3V PCI X is 0 90Vpp OVpp V 1 Output Logic High 3 3V LVTTL 24 OVpp V Output Logic Low 2 5V SSTL 0 0 55 V Output Logic Low 2 5V CMOS 3 3V tolerant receiver 0 4 V Output Logic Low 3 3V
76. n y o Type Notes Trace Interface TrcBS0 2 Trace branch execution status UO 3 3V LVTTL Trace data capture clock runs at 1 4 the frequency of the o 3 3V LVTTL processor TrcES0 4 Wie Execution Status is presented every fourth processor clock up 3 3V LVTTL Additional information on trace execution and branch status Note The trace signals TrcTS0 6 are duplicated on two sets of TrcTS0 5 chip balls and are multiplexed with other signals in both cases 3 3V tolerant multiplexed with GPIO signals This allows users to choose which set of multiplexed signals they 2 5V CMOS wish to use along with the TrcTS0 6 signals The trace signals this set are primary signals TrcTS1 5 Additional information on trace execution and branch status lO 3 3V LVTTL multiplexed with EBC signals Note The trace signals in this set are secondary signals TrcTS6 multiplexed with EBC and PUMA EEN trace execution and branch status vo 3 3V LVTTL Ethernet signals Note This trace signal is the primary signal Power Pins AxGND PLL analog voltage ground na na GND Ground na na 1 5V Filtered voltages input for PLLs analog circuits AxVpp Note A separate filter for each of the three voltages is na na recommended OVpp 3 3 except DDR SDRAM Ethernet na na SVpp 2 5V supply DDR SDRAM Ethernet na na Von 1 5V supply Logic voltage na na 56 AMCC
77. nals from MemClkOut0 90 Tsp Setup time for data signals minimum time data is valid before rising falling edge of DSQ Tup Hold time for data signals minimum time data is valid after rising falling edge of DSQ Tps Delay from rising falling edge of clock to the rising falling edge of DQS 80 AMCC Revision 1 20 June 9 2009 Data Sheet 440GX Power PC 440GX Embedded Processor UO Timing DDR SDRAM Tps Notes 1 All of the DQS signals are referenced to MemCIkOutO 0 2 The Tps values in the table include 3 4 of a cycle at the indicated clock speed 3 To obtain adjusted values for lower clock frequencies subtract 4 5 ns from the 166 MHz values the table and add 3 4 of the cycle time for the lower clock frequency Tps 4 5 0 75 Tps ns Clock Speed MHz Signal Name Minimum Maximum 166 DQSO 4 902 5 601 166 DQS1 4 872 5 535 166 DQS2 4 842 5 511 166 DQS3 4 855 5 546 166 DQS4 4 832 5 504 166 DQS5 4 867 5 525 166 DQS6 4 825 5 488 166 DQS7 4 880 5 543 166 DQS8 4 826 5 484 Timing DDR SDRAM and Sheet 1 of 2 Notes 1 is referenced to MemCIkOutO 0 and Ty are referenced to MemClkOut0 90 2 To obtain adjusted values for lower clock frequencies use 3 4 of the cycle time for the lower clock frequency and subtract maximum at 166MHz 0 75 3 To obtain adjusted values for lower clock frequ
78. ne full Gigabit Media Independent Interface GMII with 8 bit parallel data transfer Two Reduced Gigabit Media Independent Interfaces RGMII with 4 bit parallel data transfer Oneortwo TBl interfaces running in full and half duplex modes at 10Mb s or 100Mb s or 1000Mb s One full Ten Bit Interface TBI with 10 bit parallel data transfer Two Reduced Ten Bit Interfaces RTBI with 4 bit parallel data transfer Jumbo frame support 9016 byte Support for Ethernet Il formatted frames RFC894 Support for IEEE formatted frames RFC1042 Handles VLAN tagged frames TCP IP Acceleration Hardware TAH Features include Offloads Gigabit Ethernet protocol processing from the CPU Checksum verification for TCP UDP IP headers in the receive path Checksum generation for TCP UDP IP headers in the transmit path TCP segmentation support in the transmit path DMA Controller Features include Supports the following transfers Memory to memory transfers Buffered peripheral to memory transfers Buffered memory to peripheral transfers Four channels Scatter Gather capability for programming multiple DMA operations 8 16 32 bit peripheral support OPB and external 64 bit addressing 128 byte FIFO buffer Address increment or decrement Supports internal and external peripherals Support for memory mapped peripherals 12 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet
79. nput to RDSP input w o ECC Tre Propagation delay from Stage 2 input to RDSP input with ECC AMCC 87 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Example 3 In this example ECC is enabled This requires that Stage 3 data be sampled at 3 If ECC is disabled the system will still work but there will be more latency before the data is sampled into Again 1 27ns and 3 589ns at worst case conditions DDR SDRAM Read Cycle Timing Example 3 DQS at pin N N Data at pin D0 D1 X D2 X D3 X DOS Stage 1 C Data in Stage 1 D DO Tou al Tp gt High H LEON D1 X PLB Clock N N Read Clock Delayed Al 27 2 Iren lt Data out Stage 1 High Data out Stage 2 Low X High Data out Stage 3 with ECC Low Data at pap High with ECC Low D1 High X Data out RDSP with ECC Low X 3 Propagation delay from Stage 2 input to RDSP input w o ECC Tre Propagation delay from Stage 2 input to RDSP input with ECC 88 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Initialization The PPC440GxX provides the option for setting initial parameters based on default values or by reading them from a slave PROM attached to t
80. ns multiplexed 63 Total Signal Pins 406 3 AxGnd 3 OVpp 27 SVpp 9 Vpp 34 Gnd 70 Total Power Pins 146 Reserved 0 Total Pins 552 In the table Signal Functional Description on page 49 each I O signal is listed along with a short description of its function Active low signals for example RAS are marked with an overline Please see Signals Listed Alphabetically on page 17 for the pin ball number to which each signal is assigned Multiplexed Signals Some signals are multiplexed on the same pin so that the pin can be used for different functions In most cases the signal names shown in this table are not accompanied by signal names that may be multiplexed on the same pin If you need to know what if any signals are multiplexed with a particular signal look up the name in Signals Listed Alphabetically on page 17 It is expected that in any single application a particular pin will always be programmed to serve the same function The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible Multipurpose Signals In addition to multiplexing some pins are also multi purpose For example the EBC peripheral controller address pins PerAddr00 31 are used as outputs by the PPC440GX to broadcast an address to external slave devices when the PPC440GX has control of the external bus When during the course of normal chip operation an external ma
81. obtained from the strapping pins can be read from a ROM device connected to the IICO port At the de assertion of SysReset if the bootstrap controller is enabled the PPCA40GX sequentially reads 16 bytes from the ROM device on the port and sets the SDRO SDSTPO SDRO SDSTP1 SDRO SDSTP2 and SDRO SDSTP3 registers accordingly The initialization settings and their default values are covered in detail in the PowerPC 440GX Embedded Processor User s Manual 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Revision Log Date Contents of Modification 08 07 2002 Add revision log 08 30 2002 Change EMC0 1TxD0 1 and EMCO 1TxEn Toy from 15 to 11 ns 09 25 2002 Update for L2 cache 10 22 2002 Add heat sink mounting information 11 20 2002 Update UO timing data 01 07 2003 Update PCI X voltage specification Correct package drawing 01 22 2003 Correct description of SysReset signal Update for 533MHz parts and add power supply current values Update DDR SDRAM timing 03 25 2003 Change RTBIxTX and RX control signals to data signals 06 16 2003 Add 667 MHz part numbers update I O specifications and fill in missing data points Update information concerning higher speed parts bus clock ratios the duplicate trace signals and initialization 07 15 2003 strapping pins Update Ethernet signals with new and moved signals 07 17 2
82. ocument was determined in a specific or controlled environment and not submitted to any formal AMCC test Therefore the results obtained in other operating environments may vary significantly Under no circumstances will AMCC be liable for any damages whatsoever arising out of or resulting from any use of the document or the information contained herein 92 AMCC Revision 1 20 June 9 2009 Data Sheet 440GX Power PC 440GX Embedded Processor ZIMCU APPLIED MICRO CIRCUITS CORPORATION Applied Micro Circuits Corporation 215 Moffett Park Drive Sunnyvale CA 94089 Phone 408 542 8600 800 840 6055 Fax 408 542 8601 http www amcc com AMCC reserves the right to make changes to its products its data sheets or related documentation without notice and war rants its products solely pursuant to its terms and conditions of sale only to substantially comply with the latest available data sheet Please consult AMCC s Term and Conditions of Sale for its warranties and other terms conditions and limitations AMCC may discontinue any semiconductor product or service without notice and advises its customers to obtain the latest version of relevant information to verify before placing orders that the information is current AMCC does not assume any lia bility arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others
83. quirements Use the Peripheral Bus Clock for logic that is synchronous to the peripheral bus since this clock tracks the modulation Use the DDR SDRAM MemClkOut since it also tracks the modulation For PCI X and PCI 66 the maximum spread spectrum is 1 modulated between 30kHz and 33kHz Notes 1 The serial port baud rates are synchronous to the modulated clock The serial port has a tolerance of approximately 1 5 on baud rate before framing errors begin to occur The 1 5 tolerance assumes that the connected device is running at precise baud rates 2 Ethernet operation is unaffected 3 operation is unaffected Important It is up to the system designer to ensure that any SSCG used with the PPC440GX meets the above requirements and does not adversely affect other aspects of the system AMCC 65 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Peripheral Interface Clock Timings Parameter Min Max Units Notes input frequency asynchronous mode 133 33 MHz 2 period asynchronous mode 7 5 ns input high time 40 of nominal period 60 of nominal period ns input low time 40 of nominal period 60 of nominal period ns output frequency 2 5 MHz period 400 _ ns EMCMDCIk output high
84. r12 W10 SVpp Y10 MemData34 U11 MemData36 V11 MemAddr9 W11 MemData32 Y11 MemAddr1 1 012 SVpp V12 MemData31 W12 GND Y12 MemData30 U13 GND V13 MemAddr8 W13 Vpp Y13 MemData27 014 MemData21 V14 MemData26 W14 BankSel1 Y14 MemAddr7 U15 SVpp V15 MemData19 W15 GND Y15 MemData23 U16 MemData04 V16 MemData09 W16 MemAddr10 Y16 MemData20 U17 GND V17 MemData05 W17 SVpp Y17 MemData10 018 Pech V18 IRQ10 W18 MemData08 Y18 MemData13 U19 OVpp V19 PerWBE1 W19 GND Y19 U20 PerPar3 V20 PerAddr29 W20 PerPar2 Y20 MemAddr02 U21 GND V21 PerAddr31 W21 Y21 HoldAck U22 PerAddr26 22 TCK W22 PerWBE2 Y22 TDO U23 Vpp V23 PerAddr30 W23 GND Y23 HoldReq U24 PerAddr27 V24 UARTO DCD W24 PerWBE3 Y24 TDI AMCC 45 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Signals Listed by Ball Assignment Sheet 6 of 6 Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name 01 MemData48 ABO1 No ball ACO1 No ball AD01 No ball AA02 GND 2 MemData50 02 No ball ADO2 No ball AA03 MemData49 MemData52 5 ADO3 No ball AA04 4 ECC6 4 GND AD04 ECC7 AA05 DQS8 05 CAS AC05 DM8 AD05 BankSel3 AA06 GND 06 EC
85. refer to the DDR SDRAM controller chapter in the PowerPC 440GX User s Manual In the following sections the label MemClkOut0 0 refers to MemCIkOutO when it has not been phase shifted and MemClkOut0 90 refers to MemCIkOut0 when it has been phase advanced 90 Advancing MemCIkOutO by 90 creates a 3 4 cycle setup time and 1 4 cycle hold time for the address and control signals in relation to MemClkOut0 90 The rising edge of MemCIkOut0 90 aligns with the first rising edge of the DQS signal The following DDR data is generated by means of simulation and includes logic driver package RLC and lengths Values are calculated over best case and worst case processes with speed temperature and voltage as follows Best Case Fast process 40 C 1 6V Worst Case Slow process 85 C 1 4V Note In all the following DDR tables and timing diagrams minimum values are measured under best case condi tions and maximum values are measured under worst case conditions The signals are terminated as indicated in the figure below for the DDR timing data in the following sections DDR SDRAM Simulation Signal Termination Model MemCIkOutO MemCIkOutO PPC440GX SVpp 2 500 Addr Ctrl Data DQS 30pF Note This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data It is not a recommended physical circuit design for this interface An actual interface design
86. s Listed Alphabetically Sheet 22 of 24 Signal Name Ball Interface Group Page TrcBSO GPIO18 IRQ13 N16 TrcBS1 GPIO19 IRQ14 P17 Trace 56 TrcBS2 GPIO20 IRQ15 T20 TrcCIk R05 Trace 56 TrcESO GPIO21 IRQ16 T21 TrcES1 GPIO22 IRQ17 P23 TrcES2 GPIO23 N09 Trace 56 TrcES3 GPIO24 P08 TrcESA4 GPIO25 T05 TrcTSO GPIO26 T04 Trace 56 TrcTS1 GPIO27 GMCCD GMC1RxClk RTBHRxCIK Trace 56 TrcTS1 BusReq AA24 Trace 56 TrcTS2 GPIO28 GMCRxD4 GMC1RxDO TBIRxD4 RTBH RxDO ROZ dann 56 TrcTS2 ExtAck AA22 Trace 56 TrcTS3 GPIO29 GMCRxD5 GMC1RxD1 TBIRXD5 RTBI1RxD1 pee ieee P TrcTS3 ExtReq AB23 Trace 56 TrcTS4 GPIO30 GMCRxD6 GMC1RxD2 TBIRxD6 RTBHRxD2 56 TrcTS4 HoldAck Y21 Trace 56 TrcTS5 GPIO31 GMCRxD7 GMC1RxD3 RTBHRXxD3 Toss Hace 9 TrcTS5 HoldReq Y23 Trace 56 TrcTS6 GMCCrS GMC1TxCIk RTBITTxCIK A Trage 36 TrcTS6 PerErr P21 Trace 56 TRST N24 JTAG 54 UARTO CTS C13 UART Peripheral 53 UART Peripheral Ke Note Used as initialization strapping input 2d UART Peripheral 02 UTS DSP Note Used as initialization strapping input 9 UARTO B18 UART Peripheral 53 UARTO RI H16 UART Peripheral 53 UARTO RTS G16 UART Peripheral 53 UARTO Rx G17 UART Peripheral 53 38 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Signals Listed Alp
87. sed by the external master as an input to indicate the direction of transfer PerWE Wie Enable Low when any of the four PerWBEO 3 signals are o 3 3V LVTTL 2 External Master Peripheral Interface BusReq Bus Request Used when the PPC440GX needs to regain control o 3 3V LVTTL of peripheral interface from an external master ExtAck External Acknowledgement Used by the PPC440GxX to indicate o 3 3V LVTTL that a data transfer occurred ExtReq External Request Used by an external master to indicate it is 3 3V LVTTL 1 4 prepared to transfer data ExtReset Peripheral Reset Used by an external master and by o 3 3V LVTTL synchronous peripheral slaves HoldAck Hold Acknowledge Used by the PPC440GxX to transfer ownership o 3 3V LVTTL of peripheral bus to an external master HoldReq Hold Request Used by an external master to request ownership 3 3V LVTTL 1 5 of the peripheral bus PerClk Peripheral Clock Used by an external master and by synchronous o 3 3V LVTTL peripheral slaves PerErr External Error Used as an input to record external master errors up 3 3V LVTTL 1 5 and external slave peripheral errors UART Peripheral Interface Serial clock input that provides an alternative to the internally generated serial clock Used in cases where the allowable Kee internally generated clock rates are not satisfactory This input can SOMEN EIL d be individually connected to either or both UARTO and UART1 UARTO Rx UARTO Receive data 3 3V LVTTL 1 4 UARTO_Tx UARTO
88. ster Peripheral 53 IICOSCIK G11 Peripheral 54 IICOSDA G13 Peripheral 54 IIC1SCIK GPIO16 H11 Peripheral 54 IIC1SDA GPIO17 H14 IIC Peripheral 54 IRQOO GPIOO0 N18 IRQ01 GPIOO1 L20 IRQO2 GPIOO2 P20 IRQO3 GPIOO3 L18 IRQOA GPIOO4 N14 IRQO5 GPIOO05 M20 IRQOG GPIOO6 M14 IRQO7 GPIOO7 P18 IRQOS GPIOO8 N20 Interrupts 54 IRQO9 GPIOO9 P22 IRQ10 GPIO10 V18 IRQ11 PCIReq1 E21 IRQ12 PCIGnt1 C22 IRQ13 GPIO18 TrcBSO N16 IRQ14 GPIO19 TrcBS 1 P17 IRQ15 GPIO20 TrcBS2 T20 IRQ16 GPIO21 TrcESO T21 IRQ17 GPIO22 TrcES 1 P23 AMCC 25 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Signals Listed Alphabetically Sheet 10 of 24 Signal Name Ball Interface Group Page MemAddr00 Y19 MemAddr01 AD20 MemAddr02 Y20 MemAddr03 AB20 MemAddr04 AD18 MemAddr05 AD16 MemAddr06 AB18 DDR SDRAM 50 MemAddr07 Y14 MemAddr08 V13 MemAddr09 V11 MemAddr10 W16 11 Y11 MemAddr12 V10 MemCIkOutO 09 DDR SDRAM 50 MemCIkOutO V08 26 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Signals Listed Alphabetically Sheet 11 of 24 Signal Name Ball Interface Group Page MemData00 AD21 MemData01 AB21 MemData02 AC22 MemData03 AA20 MemData04 U16
89. ster gains ownership of the external bus these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC440Gx In this example the pins are also bidirectional serving both as inputs and outputs Multimode Signals In some cases for example Ethernet the function of a pin may vary with different modes of operation When a pin has multiple signal names assigned to distinguish different modes of operation all of the names are shown AMCC 47 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Strapping Pins One group of pins is used as strapped inputs during system reset These pins function as strapped inputs only during reset and are used for other functions during normal operation see Strapping on page 89 Note that these are not multiplexed pins since the function of the pins is not programmable 48 AMCC Revision 1 20 June 9 2009 Data Sheet 440GX Power PC 440GX Embedded Processor Signal Functional Description Sheet 1 of 8 Notes 1 Receiver input has hysteresis 2 Must pull up recommended value is 3kQ to 3 3V 3 Must pull down recommended value is 1kQ 4 If not used must pull up recommended value is 3kQ to 3 3V 5 If not used must pull down recommended value is 1kQ to GND 6 Strapping input during reset pul
90. t 0 Controller 1 4000 0800 1 4000 08FF 256B Ethernet 1 Controller 1 4000 0900 1 4000 O9FF 256B General Purpose Timer 1 4000 0A00 1 4000 OAFF 256B TCPIP Accelerator 0 1 4000 0800 1 4000 256B Ethernet 2 Controller 1 4000 0C00 1 4000 OCFF 256B TCPIP Accelerator 1 1 4000 0000 1 4000 ODFF 256B Ethernet 3 Controller 1 4000 0E00 1 4000 OEFF 256B Reserved 1 4000 0F00 1 FFFF Expansion ROM 1 F000 0000 1 FFDF FFFF 254MB Boot ROM 3 1 FFEO 0000 1 FFFF FFFF 2MB 6 AMCC Revision 1 20 June 9 2009 Data Sheet 440GX Power PC 440GX Embedded Processor System Memory Address Map Sheet 2 of 2 Function Sub Function Start Address End Address Size Reserved 2 0000 0000 2 FFFF PCI X 2 0800 0000 2 OBFF FFFF 64MB Reserved 2 0C00 0000 2 OEBF FFFF PCI X External Configuration Registers 2 OECO 0000 2 OECO 0007 8B PCI X Reserved 2 OECD 0008 2 OEC7 FFFF PCI X Bridge Core Configuration Registers 2 OEC8 0000 2 OEC8 OOFF 256B Reserved 2 OEC8 0100 2 0 8 00FF PCI X Special Cycle 2 OEDO 0000 20EDF FFFF 1MB PCI X Memory 2 OEEO 0000 F FFFF FFFF 55 76 GB Notes 1 DDR SDRAM and on chip SRAM can be located anywhere in the Local Memory area of the memory map 2 The Boot ROM and Expansion ROM areas of the memory map are intended for use by ROM or Flash type devices While locating volatile DDR SDRAM and SRAM in this region is supported use of these regions for this purpose is no
91. t recommended 3 When the optional boot from PCI X memory is selected the PCI X Boot ROM address space begins at 2 FFFE 0000 128 KB AMCC 440GX Power 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet DCR Address Map 4kB of Device Configuration Registers Function Start Address End Address Size Total DCR Address Space 000 3FF 1KW 4KB By function Reserved 000 00B 12W Clocking Power On Reset 00C 00D 2W System DCRs 00 OOF 2W Memory Controller 010 011 2W External Bus Controller 012 013 2W External Bus Master I F 014 015 2W PLB Performance Monitor 016 01F 10W SRAM 020 02F 16W L2 Controller 030 03F 16W Reserved 040 07 64W PLB 080 08F 16W PLB to OPB Bridge Out 090 09F 16W Reserved 0 8w OPB to PLB Bridge In DAF 8w Power Management OBO 0B7 8W Reserved 0B8 OBF 8W Interrupt Controller 0 DCH OCF 16W Interrupt Controller 1 000 ODF 16W Clock Control and Reset 0 0 OEF 16W Reserved OFO OFF 16W DMA Controller 100 13F 64W Reserved 140 17F 64W Ethernet MAL 180 1FF 128W Base Interrupt Controller 200 20F 16W Interrupt Controller 2 210 21F 16W Reserved 220 3FF 480W Notes 1 DCR address space is addressable with up to 10 bits 1024 or 1K unique addresses Each unique address represents a single 32 bit word register One kiloword 1024W equals 4KB 4096 bytes AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embe
92. ternal interrupt Requests 0 through 10 3 3V LVTTL 1 5 IRQ11 12 External interrupt Requests 11 through 12 3 3V PCI IRQ13 17 External interrupt Requests 13 through 17 3 3V LVTTL JTAG Interface TCK Test Clock 1 1 TDI Test Data In a 4 TDO Test Data Out O 3 3 LVTTL TMS Test Mode Select Se 1 NEE Test Reset During chip power up this signal must be low from the 3 3V LVTTL TRST start of Vpp ramp up until at least 16 SysClk cycles after Vpp is wioull up 5 stable in order to initialize the JTAG controller 54 AMCC Revision 1 20 June 9 2009 440GX Power PC 440GX Embedded Processor Data Sheet Signal Functional Description Sheet 7 of 8 Notes 1 Receiver input has hysteresis 2 Must pull up recommended value is 3kQ to 3 3V 3 Must pull down recommended value is 1kQ 4 If not used must pull up recommended value is 3kQ to 3 3V 5 If not used must pull down recommended value is 1kQ to GND 6 Strapping input during reset pull up recommended value is to 3 3V or pull down recommended value is 1kQ to GND required Signal Name Description y o Type Notes System Interface SysClk Main system clock input Clock 3 3V LVTTL SysErr Set to 1 when a machine check is generated 3 3V LVTTL Main system reset External logic can drive this bidirectional pin low minimum of 16 cycles to initiate a system reset A system reset can also be initiated by software The signal is implemented S
93. the PLB PCI Power Management 1 1 PCI register set addressable both from on chip processor and PCI device sides Ability to boot from PCI X bus memory Error tracking status Supports initiation of transfer to the following address spaces Single beat I O reads and writes Single beat and burst memory reads and writes Single beat configuration reads and writes type 0 and type 1 Single beat special cycles DDR SDRAM Memory Controller The Double Data Rate DDR SDRAM memory controller supports industry standard 184 pin DIMMs SO DIMMs and other discrete devices Up to four 512MB logical banks are supported in limited configurations Global memory timings address and bank sizes and memory addressing modes are programmable Features include Registered and non registered industry standard DIMMs 64 bit memory interface with optional 8 bit ECC SEC DED Sustainable 2 6 GB s peak bandwidth at 166 MHz 200MHz for 800MHz Rev F parts SSTL 2 logic 1 to 4 chip selects CAS latencies of 2 2 5 and 3 supported DDR200 266 333 support Page mode accesses up to eight open pages with configurable paging policy Programmable address mapping and timing Hardware and software initiated self refresh Power management self refresh suspend sleep External Peripheral Bus Controller EBC Features include Up to eight EPROM SRAM Flash memory and slave peripheral I O banks supported Up to 83 33 operation 333MB s Burst and non
94. ut and PLB OPB and MAL in the 12 19 2008 Clocking Specifications table on page 64 Added notes 2 and 3 Removed EOL part numbers Added Notes regarding operation of the 667MHz part at 533MHz or less at higher temperatures 105C for ceramic 06 09 2009 and 100C for plastic Removed 800MHz Removed 200MHz DDR timing AMCC 91 440GX Power 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Printed in the United States of America Thursday June 11 2009 The following are trademarks of AMCC in the United States or other countries or both AMCC Other company product and service names may be trademarks or service marks of others The information contained in this document is subject to change or withdrawal at any time without notice and is being provided on an AS IS basis without warranty or indemnity of any kind whether express or implied including without limitation the implied warranties of non infringement merchantability or fitness for a particular purpose Any products services or programs discussed in this document are sold or licensed under AMCC s standard terms and conditions copies of which may be obtained from your local AMCC representative Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of AMCC or third parties Without limiting the generality of the foregoing any performance data contained in this d
95. will depend on many factors including the type of memory used and the board layout 78 AMCC Revision 1 20 June 9 2009 Data Sheet 440GX Power PC 440GX Embedded Processor DDR SDRAM Output Driver Specifications Output Current mA Signal Path UO maximum L minimum Write Data MemData00 07 15 2 15 2 MemData08 15 15 2 15 2 MemData16 23 15 2 15 2 MemData24 31 15 2 15 2 MemData32 39 15 2 15 2 MemData40 47 15 2 15 2 MemData48 55 15 2 15 2 MemData56 63 15 2 15 2 ECCO 7 15 2 15 2 8 15 2 15 2 MemCIkOut0 15 2 15 2 MemAddr00 12 15 2 15 2 BA0 1 15 2 15 2 RAS 15 2 15 2 CAS 15 2 15 2 WE 15 2 15 2 BankSel0 3 15 2 15 2 ClkEn0 3 15 2 15 2 050 8 15 2 15 2 79 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet DDR SDRAM Write Operation The following diagram illustrates the relationship among the signals involved with a DDR write operation DDR SDRAM Write Cycle Timing MemCIkOut0 J N N MemCIkOut0 90 FA fet RE X 7 Isa Addr Cmd X lt Tsk THa gt Be P Tupi s gt Delay from rising edge of MemClkOut0 0 to rising falling edge of signal skew Tsa Setup time for address and command signals to MemClkOut0 90 Tua Hold time for address and command sig
96. ysReset as an open drain output two states 0 or open circuit 3 3V LVTTL 1 2 During chip power up this signal must be low from the start of Vpp ramp up until at least 16 SysClk cycles after Vpp is stable TmrCIk Processor timer external input clock 3 3 LVTTL Halt Halt from external debugger 3 3V LVTTL 1 4 General purpose UO 0 through 10 To access these functions GPlO009 31 software must set DCR register bits DS 33V EVITE 3 3V tolerant TestEn Test Enable 2 5V CMOS 3 Revrinh Receiver Inhibit Active only when TestEn is active 3 3V LVTTL RefVEn Reference Voltage Enable Do not connect for normal operation 3 3V LVTTL Pull up for Boundary Scan Description Language BSDL testing w pull down Drvrlnh2 Driver Inhibit Used for test purposes only Tie up for normal 3 3V LVTTL 2 operation w pull up AMCC 55 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Signal Functional Description Sheet 8 of 8 Notes 1 Receiver input has hysteresis 2 Must pull up recommended value is 3kQ to 3 3V 3 Must pull down recommended value is 1kQ 4 If not used must pull up recommended value is 3kQ to 3 3V 5 If not used must pull down recommended value is 1kQ to GND 6 Strapping input during reset pull up recommended value is 3kQ to 3 3V or pull down recommended value is 1kQ to GND required Signal Name Descriptio
97. z operation MEE vI 5 w pull up PCIXParHigh Even parity across PCIAD32 63 and PCIXCO 3 BEA 7 3 3V PCI PCIXParLow Even parity across 31 and PCIXCO 3 BEO 3 VO 3 3V PCI PCIXPErr Reports data parity errors during all PCI transactions except VO 3 3V PCI 4 Special Cycle An indication to the PCI X arbiter that the specified agent wishes PCIXReqO to use the bus When using an external PCI PCI X arbiter connect I O 3 3V PCI 4 the external arbiter s Request line to this signal An indication to the PCI X arbiter that the specified agent wishes PCIXReq1 5 td use the b s 3 3V PCI 4 PCIXReq64 Asserted by the current bus master indicating a 64 bit transfer VO 3 3V PCI 4 PCIXAck64 Indicates the target can transfer data using 64 bits VO 3 3V 4 PCIXReset Brings PCI device registers and logic to a consistent state 3 3V PCI PCIXSErr Reports address parity errors data parity errors on the Special VO 3 3V PCI 4 Cycle command or other catastrophic system errors PCIXStop Indicates the current target is requesting the master to stop the VO 3 3V PCI 4 current transaction AMCC 49 440GX Power PC 440GX Embedded Processor Revision 1 20 June 9 2009 Data Sheet Signal Functional Description Sheet 2 of 8 Notes 1 Receiver input has hysteresis 2 Must pull up recommended value is 3kQ to 3 3V 3 Must pull down recommended value is 1kQ 4 If not used must pull up recommended value

Power PC 440GX Embedded Processor

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