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Designing ASICs with the ADK Design Kit and Mentor

1. Designing ASICs with Mentor Graphics Tools 61 Copyright 2000 Mentor Graphics 12 14 01 11 28 am Chapter 6 Using the DA IC Flow You use the Schematic Editor in Design Architect IC to capture schematic information that describes your design A schematic is both a graphical and behavioral description of a circuit You can include detailed information about instances nets connectors test points timing and engineering notes To create a schematic model perform the steps that are detailed in the following sections 6 2 Creating a Schematic 6 2 1 Opening a Schematic Sheet To open a Schematic sheet from the Design Architect IC Session window perform the following steps 1 Click on Schematic in the Session palette menu under Open An Open Sheet dialog box appears 2 Enter the name of a new or existing component in the Component Name entry box You can dick on the Navigator button to locate a component 3 Click on the OK button to execute the dialog box SDL Parts 6 2 2 Choosing and Placing Compo Basic Logic Gates nent Symbols on a Sheet Inverters and Buffers Perform any of the following procedures to choose and NOEL place component symbols on a schematic sheet 401 Gates 6 2 2 1 Using the ADK_Library Palette to eee Place a Logic Component Symbol Hip Hops Latches You perform this procedure if you want to instantiate Pads and place a component that resides in the ADK General library In 1 Activate the ADK_Libra
2. Chapter 14 Simulating the Design Using QuickSim All of the signals that corresponds to the selected objects appear in the Trace window 14 5 Running the Simulator To begin a simulation run enter the following command in the popup command line run time If you do not specify a time the simulator will run indefinitely You can stop the simulator at any time by pressing the CONTROL and C key at the same time If you have found problems in your circuit or do not fully understand the behavior of the design you will need to make changes to both the design and stimulus before you proceed with further simulation The following sections briefly describe how you reset the simulator to time O set breakpoints back trace X states and change your design 14 6 Changing the Timing Mode in the Kernel Unless you set the kernel differently you will be running in unit delay mode That is all gates will have a unit delay and you will only be performing a functional test If you wish to see actual timing for the gates you will need to set the timing mode in the kernel Use the Setup 5Kernel 5Change 5Timing Mode menu to change the timing mode You can select from unit delay full delays or linear approximation delays Currently there are no linear models so if you choose that option the full delays will be used instead You can choose to use slow fast or typ timing values for your circuit The timing mode can be changed for all or s
3. Designing ASICs with Mentor Graphics Tools 11 3 Copyright 2000 Mentor Graphics 12 10 01 4 10 pm Chapter 11 Generating Padframes 11 4 Designing ASICs with Mentor Graphics Tools 12 10 01 4 10 pm Copyright 2000 Mentor Graphics chapter 12 Preparing Fabrication Data Once your layout is complete and you are ready to send your design for MOSIS for fabrication you will need to perform the following steps Step 1 Create a new top level cell for your scaled design Create a new cell in GE geometry editing mode Make sure you specify the correct process for the cell Step 2 Add your completed cell to this new cell use Add gt Cell to add your top level design to this new cell This top level should include your wired padframe as well You should not do any editing of your cell that this point Step 3 Scale your cell to the correct technology Use the ADK gt Scale menu to select the technology you are targeting This will appropriately scale your design for that technology Step 4 Write out GDSII for your cell Use Translate 3 CLink to write a GDSII stream or CIF but MOSIS prefers GDSII and it will scale properly with no manual edits Select the source format as Cgraph and the destination as GDSII Click OK and another dialog box will appear that will ask for the source and destination names and option file Enter the name of your source cell or use the navigator the destination including any extension such as
4. 7 Activate the Value entry box by moving the mouse pointer over the signal in the trace window and clicking the Select mouse button 8 Enter Lin the Value entry box 9 Click on the Location icon in the prompt bar 10 Move the mouse pointer which now appears as a Set of cross hairs to a point on the selected waveform in the Trace window SimView adds an X to 1 logic level transition to the signal in the Trace window 14 4 3 Creating a Force File The following example shows a force file for a State Machine design with a clock clk and reset and an input signal called x In addition to stimulus information you can also include other AMPLE commands such as OPEn SHEet ADD TRAce and ADD Designing ASICs with Mentor Graphics Tools 14 7 Copyright 2000 Mentor Graphics 12 14 01 11 02 am Chapter 14 Simulating the Design Using QuickSim LISt to the force file The following list shows the typical development process to create a force file 1 Generate the stimulus using the SimView tools e g palette icons and waveform editor 2 Verify the stimulus is correct by simulating the design 3 Delete the dock signal stimulus If you do not delete the dock signal every dock transition is added to the force file which makes the resulting force file difficult to edit 4 Save the stimulus into a force file as described n the next section 5 Edit the force file to ind ude the dock signal definition The following example
5. Go to the ADK Library palette and use the in out and bi symbols Make sure that you give each port a unique name 6 2 6 Adding Power and Ground Symbols If you desire to explicitly place power and ground symbols you must use the symbols in the SDL menu from the ADK Library palette These have the proper properties to drive the layout and simulation tools with the other models 6 2 7 Creating Comment Objects on a Schematic Sheet You can add comment text and graphics directly to a sheet in the Schematic E ditor To create graphical comment objects on a schematic sheet perform the following steps 6 6 Designing ASI Cs with Mentor Graphics Tools 12 14 01 11 28 am Copyright 2000 Mentor Graphics Creati ng a Schematic 1 View the schematic draw palette by clicking on the Schematic line in the palette window to bring up the main palette and then select Draw from that palette The schematic draw palette appears 2 Click on any of the functions in the palette menu to create a graphical object To create a comment text object perform the followi ng steps 3 Choose the following menu path from the Add popup menu Draw 5 Text or select Text from the palette menu and then select Comment Text The ADD TE prompt bar appears 4 Enter your comment text in the Text entry box 5 Click on the At Location button A ghost image of your comment text moves when you move the mouse 6 Movethe ghost image to the location you want to place t
6. Select Place amp Route from the IC Palette or PAR from the ADK Edit Palette then choose autofloorplan Autofp in the Place amp Route Palette Allow all options to default simply by clicking on OK in response to the Autofloorplan Options form Use View gt All from the top menu bar to see the automatically generated floor plan You will see a series of boxes enclosed by solid bars along each edge The boxes indicate the rows into which cells will be organized The solid bars indicate edges of the cells along which physical ports will be placed Step 3 AutoPlace the standard cells Choose Autoplace Std Cells StdCel under Autoplc in the Place amp Route palette and click on OK in the form once again leaving all options to their default values You should see individual cells placed in the floorplan boxes Cell locations are determined by their interconnectivity Cells which share connections are placed near one another You may wish to experiment with the results obtained thus far by selecting different Autofloorplan and Autoplace options Step 4 AutoPlace Ports Select Autoplace Ports Ports under Autoplc in the Place amp Route palette You can allow the options to default for now but you may wish to experiment with Designing ASICs with Mentor Graphics Tools 9 3 Copyright 2000 Mentor Graphics 12 10 01 4 10 pm Chapter 9 Automated IC Layout using IC Station them later also You will see lightly shaded areas along the port
7. 5 Change any of the property attributes in the dialog box 6 Click on the OK button to execute the dialog box A new Modify Property dialog box will appear for the next selected property Repeat step 5 until you are finished examining and modifying the selected properties 6 3 3 Creating Comment Objects on a Symbol To create a comment text object perform the following steps 1 2 3 4 5 Choose the Text menu item from the Add popup menu Enter your comment text in the Text entry box Click on the At Location button A ghost image of your comment text moves when you move the mouse Move the ghost image to the location you want to place the text Click on the L eft mouse button To convert symbol body graphics and text into comment objects perform the following steps 6 Select the objects that you want to convert 7 Choose the following pulldown menu path from the menu bar Edit 5 Convert to Comment Design Architect converts the selected object s into a comment object s When you unselect the object the comment object will be a different color than either the symbol body graphics or text Designing ASI Cs with Mentor Graphics Tools 6 9 Copyright 2000 Mentor Graphics 12 14 01 11 28 am Chapter 6 Using the DA IC Flow 6 3 4 Checking and Saving a Symbol All symbols must pass a set of required checks before you can place them on a schematic sheet You can check your design at various points in the d
8. Drawing a Net Bus To draw a net perform the following steps 1 Select the Add pull down menu and choose Wire from the top of the list or type add wire The ADD WI prompt bar appears 2 Position the mouse pointer where you want the net to begin usually this is at an instance pin and click the Select mouse button The initial point of the net becomes fixed and a ghost net image rubber bands as you move your mouse 3 Movethe end of the net segment to the location that you desire and click the Select mouse button Design Architect instantiates the net segment between the initial and final points that you specified 4 Tocontinue adding segments to the net move the mouse pointer to the next position and click the Select mouse button 5 To complete the net double click the Select mouse button The ADD WI prompt bar remains active so that you can begin drawing another net 6 Click on the Cancel button to remove the ADD WI prompt bar 6 2 3 1 Naming Nets To name a net in the schematic 1 Select Net 2 Display the Name Net prompt bar from the popup menu Name Net 6 2 3 2 Using Buses To connect buses to single nets and vice versa 1 Select the Add pull down menu and choose Bus Bundle from the top of the list or type add bus 2 Place your bus by clicking on the initial point and on each bend in the bus you desire 3 Doubleclick at the end of the bus 4 Give the bus a name It should be o
9. gdsii and the option file For the option file you should use ADK lib iclink_gdsii options A GDSII file will be produced and this is what you will send to M OSIS Be sure to check MOSIS s web pages for proper submission procedures and technology codes For all processes the ADK uses the sub micron SUBM design rules so you should specify that in your technology code If you used the second poly layer be sure to use the code for that as well If you do not use the second poly layers then you can use either the single or dual poly technology codes You will simply get a warning about no data on the second poly layer if you have none This can be safely ignored Designing ASI Cs with Mentor Graphics Tools 12 1 Copyright 2000 Mentor Graphics 12 14 01 11 28 am Chapter 12 Preparing Fabrication Data 12 2 Designing ASICs with Mentor Graphics Tools 12 14 01 11 28 am Copyright 2000 Mentor Graphics chapter 13 Performing Post Layout Verification using Mach TA Mach TA is an analog simulation tool for performing timing analysis and functional verification of digital designs Its rolein the ADK kit design flow is to perform analysis on netlists extracted from a design layout in IC station 13 1 Preparing to Simulate the Design Step 1 Extracting the SPICE Netlist from IC Station Mach TA uses SPICE netlists as its input To get a SPICE netlist for your design do an IC Extract M gt Lumped from the IC Palettes menu in IC Station o
10. general procedure for taking your scan design written from DF T Advisor and generating your test vectors Step 1 Invoke FastScan in GUI mode You can simply type fastscan to bring up a dialog box that will prompt you for all the proper arguments Step 2 Fill out the dialog box For Design enter the name of the scan design you output from DF TAdvisor Be sure the Format is correct for HDL source Enter the correct top level name for Top Module Enter ADK technology adk atpg for ATPG Library NOTE You must substitute your full path for SADK in the GUI It will not expand your environment variable Enter a name for the output log file if desired Click on the Invoke FastScan button to run FastScan Optionally you can do all this from the command line fastscan vhdl design vhd lib SADK technology adk atpg top toy dofile design scan dofile log fastscan log Step 3 Generate test patterns At this point you should be ready to generate patterns Your dofile that was generated from DF T Advisor that you ran in FastScan set up your circuit s scan and clocks All you need to do is enter the following commands set system mode atpg add fault all run save patterns top pat exit discard Optionally you can use the GUI or create a dofile with these commands in it and run that with 5 2 Designing ASI Cs with Mentor Graphics Tools 11 10 01 10 48 am Copyright 2000 Mentor Graphics Generating Test Vectors dofile do
11. such as adk da or adk ic If you use the standard tool it will not have any of the ADK enhancements A 1 ADK_DA adk_da is the command that will start Design Architect with the ADK extensions If you use this command you will have the following additional functionality in Design Architect A 1 1 ADK Libraries menu Under the standard DA Libraries menu you will see a new item ADK Libraries This selection will display the ADK Libraries palette menu which will have all of the libraries specific to the ADK on it Basic Logic Gates This library contains all of the schematic models for the basic logic standard cell gates and their variants AND NAND NOR OR FADD MUX The number following the gate name indicates the number of inputs for the AND NAND NOR and OR gates The number after FADD indi cates the number of bits in the full adder and for the MUX indicates the num ber of inputs and outputs e g MU X21 has two inputs and one output Inverters and Buffers This library contains all of the schematic models for the inverters and buffers Each in multiple drive strengths The number fol lowing each gate is the drive strength for the gate These are relative numbers so an INV02 has twice the drive strength as an INVO1 See the datasheets on the cells for more specific absolute drive strength information AO Gates This library contains all of the schematic models for the AND OR gates The numbers following the name indicate the grou
12. 12 14 01 11 02 am Chapter 14 Simulating the Design Using QuickSim 3 Enter the namein the E xpression entry box of a signal that currently has a breakpoint on it 4 Click on the OK button to execute the dialog box SimView removes the breakpoint from the breakpoint list 14 8 2 Back Tracing X States If your design produces X signal states during simulation you can use the Debug Gates palette to find the instances that are generating them You can easily search back through a circuit to find the cause of an X value First the simulator examines the inputs of the instance that is driving the selected net If the signal value of any input to the instance is X it then selects that net and notifies you that the backtrace has succeeded 14 8 3 Design Changes You can change your design within a simulation session and then resimulate it You can make the following types of design changes without exiting the simulator e Design property changes You can add or change property values This activity is referred to as annotating the design You can also import ASCII back annota tion files which contain a set of property changes e Swapping models You can substitute one model representation for another by changing the Model property By swapping models you can try using different manufacturing processes e Reload models You can reload models that you have changed in Design Archi tect For example if you find a mistake in a
13. 2000 Mentor Graphics Generating Stimulus h Click on the pattern type label button that describes the pattern that you want to generate i Describe the details of the pattern you want to generate in the entry boxes j Click on the OK button to execute the dialog box SimView generates the pattern and adds it tothe signal that you either selected or specified 14 4 2 Creating a Waveform Using the Waveform Editor You can use the Waveform Editor to create a variety of both simple and complex waveforms To create a simple waveform that transitions from an Undefined X toa High 1 logic value by using the Waveform Editor perform the following steps 1 Open the Trace window if it is not already open by performing the Opening the Trace Window procedure in this manual 2 Click on the red WF EDITOR palette button 3 Select a pin net or bus in the Schematic View window 4 Click on the Edit Waveform icon in the Waveform Editor palette menu The signal that corresponds to the selected object appears in the Trace window The Trace window displays any stimulus waveforms that you previously created for that signal 5 Activate the Trace window by moving the mouse pointer inside the Trace window and clicking the middle mouse button The Trace window becomes the active context window and all of the icons in the Waveform Editor palette menu become usable 6 Click on the Add Edge icon in the Waveform Editor palette menu
14. Create dft map file in your working directory Using your favorite editor create a file called dft map and enter these lines standard SMODEL_HOME vhdl_src std standard wvhd std logic 1164 SMODEL HOME vhdl src ieee stdlogic vhd adk SADK technology adk vhd Step 2 Invoke dfta Run DFTAdvisor on your structural HDL netlist for your design The first example if for VHDL the second for Verilog dftadvisor vhdl design vhd lib SADK technology adk atpg dftadvisor verilog design v lib SADK technology adk atpg Step 3 Inset Scan chain You can use the GUI or simply enter these commands in the command window This is a simple configuration but will demonstrate the basic steps necessary to insert a scan chain set system mode setup analyze control signal set system mode dft run insert test logic Step 4 Write the scan netlist You need to write out the new netlist with your scan chain instantiated Again simply type these commands in the command window write atpg setup top scan replace Designing ASICs with Mentor Graphics Tools 5 1 Copyright 2000 Mentor Graphics 11 10 01 10 48 am Chapter 5 Designing for Testability write netlist top dfta scan vhd replace Step 5 Exit DFTAdvisor exit discard 5 2 Generating Test Vectors Once you have inserted your scan chains you need to generate the test vectors that will be used to test your circuit You use FastScan to do this Hereis a
15. Design Data Optional 200002 eae 1 5 1 3 Setting up Leonardo 7 a kan aaau aaaea 1 6 1 3 1 Setting up the Leonardo GUI 2 xa paa aaaaa anaana 1 6 1 4 Checking your ADK Version 000 0 eee eee 1 7 Chapter 2 Using as little UNIX as possible 2 1 2 1 Setting up your Environment 0 000 c eee eee 2 1 2 2 Moving around the system 02 c eee ee 2 1 2 2 1 cd Change Directory 0 eee 2 1 2 2 2 pwd Print Working Directory 00 eee 2 2 22 Colo LO yaa ao Rees oe ee KA Ow le A ee BAS 2 2 PALA Cpe COPY 224568 ceeneesetewtenrst y a AA 2 2 2295 00 MONG cecuticuturdekh dbp bese bate heneetes eed bees sans 2 3 22 0 8 REMOVE 2 peulgae uua da hi i vate UND AUG LE E 2 3 Pee MOG wna ner needa cau Gee catia TY 2 3 2 2 8 chmod CHange permissions cece eee eee 2 3 2 3 Printing your files Nakagawa ee oo eee eee se eee Meh eat Ree eae 2 3 2 3 1 Ip printing ascii and postscript files 000 0c eee 2 3 2 3 2 Ipstat Viewing the printer status eee ee eee 2 4 LA PICCSSSeS ot nA Na AA hes aieare sites Een ehenreeeuene tee see ene 2 4 AO aa hte E he OAs CM Baten ne Pee GANAP Red a ee es 2 4 2 4 2 Nigga duane ee PG BAGA ANNP ha ANGARA cide haa ene aan ee KGG 2 4 2 5 Obtaining more help on UNIX commands ee ee eens 2 4 Chapter 3 Simulating HDL in ModelSim 3 1 3 1 Compiling HDL code aaa kaaa ARAB
16. Fundion Description rabl Remove metal 1 blockages This command will remove all metal1 blockages in your cell s12 Set cell process to AMI 1 2 s5 Set cell process to AMI 0 5 cp Checkpoint cell save the cell and then reserve the cell dup Delete unplaced ports If LVS reports unplaced ports but you see that they are all placed from your schematic the database might have duplicate ports This command will remove them A 6 Designing ASICs with Mentor Graphics Tools 12 14 01 11 28 am Copyright 2000 Mentor Graphics
17. HA AMAG DALA bebe ee he bg OS PSHE 3 1 3 2 Compiling the ADK cell libraries 0000 c eee eee 3 2 3 3 Invoking ModelSim 2 aaah xed ee ote ab NGA BY THEA KA 3 2 3 4 Setting up the ModelSim windows 000 cee eee eee eee 3 3 3 5 ADPIVING SUMMNUS mak ALAGA NENE ed DEBT eh KA NAA ee oeens Mean eeue 3 3 3 5 1 Using Force Files interactive cee eee eee 3 3 3 5 2 Force File Example 1 ss amawa a haaa KA ses deed eeeereat dee PAGA 3 4 Designing ASICs with Mentor Graphics Tools 1 Copyright 1999 Mentor Graphics 12 14 01 1 12 pm Chapter 3 5 3 Force File Example 2 loops 7x mad NEA ARALAN EA ok weed ews AREA 3 4 3 5 4 VHDL Test Bench example 0c eee 3 5 3 6 Running the Simulator g cccswedededcces BG PRE A ANA RADYE KANG AE 3 6 Chapter 4 Synthesizing VHDL or Verilog 4 1 4 1 Synthesizing HDL Using Leonardo GUI Mode 4 1 4 2 Synthesizing HDL Using Spectrum Command Line Mode 4 3 4 3 Creating a EDDM Schematic from EDIF cece eee 4 4 Chapter 5 Designing for Testability 5 1 5 1 Inserting Scan chains cc waaa waa Kid vied Seb bbteongadws pedasde bende as 5 1 5 2 Generating Test VECIOIS 44 kka NA Bb PAGA KANAN dadeeeeterdevbheedes 5 2 Chapter 6 Using the DA IC Flow 2222222 2 6 1 6 1 Invoking Design Archilect IC aa KAL ING KANAN hak KA bet eeu NG HG 6 1 6 2 Creating a Schem
18. Selected 14 4 Generating Stimulus QuickSim II uses stimulus that is stored in a waveform database SimView which manages a variety of waveform databases conveys the stimulus to QuickSim II applies the stimulus to your design and calculates the results QuickSim Il sends the results back to SimView to be stored in the Results Waveform Database You can use a number of formats to create waveform stimulus including Forcefiles Logfiles and Mentor Interactive Stimulus Language MISL files You can easily translate Forcefiles Logfiles and MISL files into a waveform database by using SimView to load the stimulus file into program memory You can also translate a waveform database into either a Forcefile or a Logfile The following procedures describe various methods that you can use to create and manipulate stimulus that QuickSim II can use to simulate your design Designing ASICs with Mentor Graphics Tools 14 5 Copyright 2000 Mentor Graphics 12 14 01 11 02 am Chapter 14 Simulating the Design Using QuickSim 14 4 1 Creating a Waveform Using Palette Icons You can create waveforms by using a variety of Stimulus palette icons Perform the following steps to create a new waveform that you want to apply to either a pin net or bus Step 1 Click on the red STIMULUS palette button Step 2 Select pins nets or busses In the Schematic View window move the mouse pointer over it and click the left button Step 3 Click on one
19. Start by creating a top level schematic for the whole chip that includes both the pads and the design core The core logic needs to have a symbol for each piece and a property called phy_comp for physical component and no comp property Simply place your core logic and the pads which will drive the automatic padframe generator in IC Station Step 1 Create a symbol for your core logic In Design Architect you need to generate a symbol Miscellaneous gt Generate Symbol for each piece of core logic that you want to instantiate in the pad frame You will have to have a completed IC layout for each component for which you have a symbol at this top level These can be SDL or standard cell designs or a combination of both Once you have generated your symbol you need to add the phy_comp property string to the symbol body The value of phy comp needs to be the name of the IC cell that you created or will create Do not place a comp property on this symbol Step 2 Use Choose Symbol to bring in the design part s and wire them together if necessary Perform a check 5 sheet and just ignore the unconnected pin warnings You can also eliminate the reporting of these warnings by selecting check 5 sheet 5 set defaults and setting dangles to errors only Step 3 In the ADK Library menu choose the pads to use from the appropriate library for your technology Based on the technology there Designing ASI Cs with Mentor Graphics Tools 111 C
20. The pp or place port macro will let you place a port contact a via from metal1 to metal2 and some blockage layers where ever you click once the ghost image appears Keepin mind that unless you change the port layer all ports will be on metal2 You will need to place a port contact or via to get to metal1 to connect your port to metal1 Don t forget to do this 10 6 5 Adding well contacts You will almost certainly want to add well or bulk contacts to your cells as well These will tie your wells or bulk to metal so you can properly bias it as necessary Again there are two macros that make this a little easier e nwcwill place an n well contact into your cell where you click e pwc will place a p well contact into your cell where you click Both macros place a cell that has been predefined with proper rules to pass DRC The bottom of the n well contact is designed to abut to your n well and the top of the p well contact is designed to abut to your p well Keep this in mind if you decide to rotate or flip your contacts You can always peek down into the contacts to see the full layout to better align your cells 10 7 Verifying your layout After placing components and ports and then wiring your circuit up you need to verify it s correctness There are three areas to check Design Rule Checks DRC Layout Versus Schematic LVS and functional correctness performance The last item will be discussed in the next section on extractio
21. are made visible to the IC tool as well 2 Viewpoint for CTrace The viewpoint called LVS is created and the primitive called element is appended It does not matter what the value or the type the primitive is Designing ASICs with Mentor Graphics Tools 10 1 Copyright 2000 Mentor Graphics 12 14 01 1 07 pm Chapter 10 Schematic Driven Layout using IC Station The element primitive in CTrace serves the same function as the model primitive for QuickSim namely that of identifyi ng the leaf parts of the design 10 2 Invoke IC Station ThelCgraph tool is the main entry point into the IC Station environment Before running the tool however we need to set the SMGC WD environment variable to the directory where the design resides This can be performed with the Unix alias macro swd To invoke IC Station from the unix command prompt simply type adk ic This is a special version of IC Station that has been enhanced with special features for the ADK 10 3 Creating a cell for SDL There aretwo ways to create a cell for SDL It is important to create you cell in one of these two ways else the logic and CStation databases might not correlate correctly Method 1 Use Create Cell J ust as in creating a cell for automatic place and route you can select CREATE from the menu on the right hand side of the screen A form titled CREATE CELL will appear Enter the following then click OK Cell Name SPROJECT layo
22. command are e a View all status information This is the most commonly used option Ipstat a e d This will show the system default destination for lpr lpstat d e oThis will snow all jobs being output to the named printer or all queued jobs if no printer is specified Ipstat o lt printername gt 2 4 Processes 2 4 1 ps The ps command is used to report information about active processes Flags used with this command are e e Print information about all processes Usage ps e e f Print a full listing of the processes Usage ps ef e u Print information about the processes of a specified user Usage ps u usa name or ps fu usa nam 2 4 2 kill The kill command is used to terminate a process es Use the ps command to determine the process id PID of the process that you will to termiate Usage kill PID from ps command Flags used with this command are e 9 A sure kill Usage kili 9 PID 2 5 Obtaining more help on UNIX commands On line help for commands is available Simply type man command name 2 4 Designing ASICs with Mentor Graphics Tools 11 10 01 10 48 am Copyright 2000 Mentor Graphics chapter 3 Simulating HDL in ModelSim You can invoke the M odelSim simulator on any compiled VHDL or Verilog design Once you invoke M odelSim you can apply stimulus to the design run the simulation analyze the results and modify the design based on those results You can then reset the
23. cursor to the Trace window perform the following steps L Activate the Trace window by moving the mouse pointer inside it and clicking on the Stroke drag middle mouse button Click on the red DBG GATES palette button The Debug Gates palette menu appears Click on the ADD CURSOR icon in the palette menu The Add Cursors dialog box appears Enter any cursor name that you want to assign to the new cursor 5 Click on the OK button to execute the dialog box SimView adds the cursor to the T race window at time zero To move the trace cursor to a different point in the time domain perform the following steps a Click on the SLIDE CURSOR icon in the palette menu b Movethe mouse pointer to a new location in the Trace window and dick the Select mouse button SimView moves the trace cursor to the new time domain location After you setup the schematic trace list etc windows within SimView you are ready to simulate the design by generating stimulus Designing ASICs with Mentor Graphics Tools 14 13 Copyright 2000 Mentor Graphics 12 14 01 11 02 am Chapter 14 Simulating the Design Using QuickSim 14 14 Designing ASI Cs with Mentor Graphics Tools 12 14 01 11 02 am Copyright 2000 Mentor Graphics chapter 15 Performing Static Timing Analysis One of the most critical aspects of VLSI design is timing analysis The ADK indudes the necessary library files to use the SST Velocity static timing analysis
24. designs adk 3 Compilethe ADK VITAL or Verilog into the ADK work library vcom ADK technology adk vhd work adk vlog ADK technology adk v work adk 3 3 Invoking ModelSim Enter the following line on the unix command line vsim model If you specify a design name model ModelSim will attempt to load the last 3 2 Designing ASICs with Mentor Graphics Tools 11 10 01 10 48 am Copyright 2000 Mentor Graphics Setting up the ModdSim windows compiled architecture or interface of the specified model from the work library If you did not specific a design name on the invocation line then M odelSim will display a dialog box that allows you to verify the library name in most cases it will be work and select the design that you want to simulate 3 4 Setting up the ModelSim windows ModelSim has a set of windows that allows you to view your design and simulation results In most cases you will only be using the Main Source and Wave windows 1 Display the source HDL code View gt Source VSIM gt view source 2 Displaying signal waveforms e Toadd all top level signals VSIM gt add wave e Toadd a specific signal VSIM gt add wave signal_name VSIM gt add wave clock VSIM gt add wave curr_state e Toreorder the list of signals Select and hold down the LMB on the signal in the wave window it will be highlighted with a box and then move the mouse until the skinny green box is at the point where you want t
25. do this the same way you checked your cell layout using Check in the Crules palette with one exception When you check the entire layout you will find some DRC errors in the pad frame as well as any DRC errors that still exist in the cell layout The pad frame errors are inconsequential and are a result of using an optional set of design rules Focus on the design rules that exist independent of the pad frame by excluding certain cells from the DRC 1 Select Check from the Crules palette 2 Click on options in the resulting prompt bar and enter the following under exclude cell PadOut PadSpace PadBidir PadlnC PadGnd PadVcc PadF C and any other pad names you see in your padframe If you also did a DRC on your core logic you can even exclude it from the checks This will exclude all pad cells from the DRC check and any errors will be exclusively related to your cell and the top level interconnect 9 6 Designing ASICs with Mentor Graphics Tools 12 10 01 4 10 pm Copyright 2000 Mentor Graphics chapter 10 Schematic Driven Layout using IC Station In addition to the automated tools for layout that let you do standard cell place and route you can use schematic driven layout SDL to place and route your cells or device level circuits This section will show you the basic features of SDL and how the ADK supports SDL for device and hierarchical cell layout For more complete documentation on all of the SDL features of IC Station see th
26. ed ee Haeaie GNG ee tee See 10 5 10 74 DRC Of y u r ll cossir vee se vad eels ee eed were eee ee 10 5 10 7 2 LVS of your cell ccs KPA WAA BIKE DNA PDA KEBBAYBOAEOLDT ee 10 6 Chapter 11 Generating Padframes 000e eee eenee 11 1 11 1 Top Level Layout Preparation 00 0000 e eee 11 1 11 2 Padframe Layoul c2cdccdevencedtey de Sasdectdudeewtede a a 11 2 Chapter 12 Preparing Fabrication Data 12 1 Chapter 13 Performing Post Layout Verification using Mach TA 13 1 13 1 Preparing to Simulate the Design 00220 13 1 13 1 1 Creating Test Vectors lt xcvcerbeseudcdvedebeeu si BUDA GANSA 13 1 13 1 2 Creating a Command File 0000 ees 13 1 13 2 Running Test Vectors and Viewing Results 200005 13 2 Chapter 14 Simulating the Design Using QuickSim Il 14 1 14 1 Setting up the Design Viewpoint 00 000 e eee eee ee 14 1 14 2 Invoking QuickSim Il 2 0 6 eee 14 1 14 3 Setting up the SimView Windows 0000 eee eee eee 14 2 14 3 1 Opening the Schematic View Window 02 005 14 2 14 3 2 Using a Trace Window 000 cece ees 14 2 14 3 2 1 Opening a Trace Window 000 0c eee eee eee 14 3 14 3 2 2 Adding a Signal to the Trace Window 14 3 14 3 2 3 Deleting a Signal from the Trace Window 14 3 14 3 3 Using a List Window 00 eee 14 4 14 3 4 U
27. not no yes defined c capacitance 100fF yes yes model device generator to use notchedr no yes ow neg cont type of contacts to bottom N no yes act style plate seethe DLA manual for possible options ar aspect ratio 1 no yes m number of plates 1 no yes By default the capacitor uses C capacitance W width and AR aspect ratio to define the size of the device The device generator will compute H height for you If you want a specific size then specify H and W only C wil be calculated If you want to specify C and H then W will be calculated for you You can change AR if you want to force a different aspect ratio The device generator will try to get as dose to the specified aspect ratio as possible It is just a guide however 8 2 Designing ASI Cs with Mentor Graphics Tools 12 14 01 1 08 pm Copyright 2000 Mentor Graphics Resi stor 8 3 Resistor For designs not using the AMI 1 2 1 6 micron process a resistor is available This resistor uses the high resistance HR poly that is available This allows resistors with a large range of values but precludes very small valued resistors like 10 ohms from being practical There are several properties that can be modified by the designer that will affect how the resistor is drawn These are shown inTable 8 3 Table 8 3 Resistor Properties Default Simulat Property Description Va le on Layout W width in lambda 10 no yes length in lambda not no yes defined
28. of the following Stimulus palette icons and per form its related procedure if any to create a waveform e Edit Waveform Adds the waveform to the default waveform database and to the Trace window e Force To State Applies the state value that you select from the State value cas cade menu at the current simulation time to the default force target waveform database e Add Force Applies the time value pairs and force type to the selected signal Perform the following steps to add a force a Click on the Add Force icon b Enter thetime value pairs and force types that you want to apply in the dialog box c Click on the OK button to execute the dialog box SimView adds the force to the selected signal s e Add Clock Applies a dock waveform that has the period time value pair and force type to the selected signal Perform the following steps to add a dock wave form d Click on the Add Clock icon e Enter the time value pairs and force type that you want to apply in the dialog box A typical clock signal has at least two time value pairs for both low and high values f Click on the OK button to execute the dialog box SimView adds the clock to the selected signal e Pattern Generator Generates a pattern waveform that it applies to the selected signal Perform the following steps to apply a pattern g Click on the Pattern Generator icon 14 6 Designing ASICs with Mentor Graphics Tools 12 14 01 11 02 am Copyright
29. r resistance 1k Ohm yes yes model device generator to use hr no yes res leg number of legs for the 1 no yes resistor res struc the structure of the straight no yes ture resistor straigh series parallel m number of plates 1 no yes By default the resistor uses W width and R resistance to define the size of the device The device generator will compute L length for you If you want a specific size then specify L and W only R wil be calculated If you want to specify R and L then W will be calculated for you Designing ASICs with Mentor Graphics Tools 8 3 Copyright 2000 Mentor Graphics 12 14 01 1 08 pm Chapter 8 Using the Analog SDL Parts 84 Designing ASI Cs with Mentor Graphics Tools 12 14 01 1 08 pm Copyright 2000 Mentor Graphics chapter 9 Automated IC Layout using IC Station Y g p y Y and route tools to edabi the internal layout You will also learn how to perform LVS and DRC checks You will then learn how to automatically generate then program a padframe for your design Finally you will learn how to manually edit the layout to connect the O ports of your design to the pad cells NOTE This chapter is appropriate only for standard cell designs If you are doing ransistor based designs using SDL for example please go to Chapter 8 for instructions on using IC Station for that PLEASE NOTE Several key steps in this manual cite ample shortcut macros hat are directory structure dependent Its a
30. shows a completed force file to test simulate a finite state machine Define Clock signal Set Clock Period 50 Force clk 0 20 Repeat Force clk 1 40 Repeat FORCe clk 0 0 0 Abs cr ct Initialize flip flops FORCe rst 0 0 0 Abs FORCe rst 1 1 0 Abs Test State Machine FORCe x 1 12 0 Abs FORCe x 0 75 0 Abs FORCe x 1 175 0 Abs FORCe x 0 225 0 Abs FORCE x 1 325 0 Abs FORCe x O 525 0 Abs FORCE x 1 575 0 Abs FORCe x 0 725 0 Abs 14 4 3 1 Saving Waveform Stimulus in a Forcefile To save the waveforms that you have created in a Forcefile perform the following steps 1 Click on the red STIMULUS palette button The Stimulus palette icons appear in the palette menu 2 Click on the SAVE WDB icon in the palette menu A Save Waveform DB dialog box appears 14 8 Designing ASI Cs with Mentor Graphics Tools 12 14 01 11 02 am Copyright 2000 Mentor Graphics Generating Stimulus 3 Enter a pathname in the Pathname entry box for the Forcefile that you want SimView to create You should save this file in the DE SI GNS sim directory Typically you name the file design do To execute the file within Quicksim II type DOFile SDESIGNS sim design do If the filename already exists click on the Replace button 4 Inthe Filetype field click on the Forcefile choice button 5 Specify both a start time and stop time in the Start time and Stop time entry boxes for th
31. simulation of a design containing VHDL models you can open a Design Architect Session window fix the model and then reload the modified model in the QuickSim II Session window You can perform the entire modify and reload process without re invoking QuickSim II The simulator keeps track of all incremental design changes This tracking ensures compatibility with related design information that you save The simulator automatically checks the data objects that are dependent on the design configuration and prohibits them from being used if they are not compatible 14 8 4 Viewing a Simulation Timing Report To view a timing report which contains all of the timing related information for selected signals perform the following steps 1 Select one or more pins nets and busses in the Schematic View window SimView highlights both the selected objects in the Schematic View window and the related signals in both the Trace and Monitor windows 2 Press the Menu mouse button and choose the following menu path from the popup menu Report gt Timing gt Selected 14 12 Designing ASICs with Mentor Graphics Tools 12 14 01 11 02 am Copyright 2000 Mentor Graphics Using QuickSim to Debug your design SimView opens a Timing Info window that describes the selected signals 14 8 5 Using Cursors to Get Waveform Information Cursors are domain markers that provide you with a quick way of getting information at a point on a waveform To add a trace
32. to view a file or output of a command one page at a time Pressing the spacebar will continue on to the next page Ctrl C is used to break out e Toview a file type more file e Toview the output of a command type command name more An example of this is Is more 2 2 8 chmod CHange permissions The chmod command is used to change the protections on your files and directories The protections can be set for yourself the group and others The permissions are read 4 write 2 and execute 1 An example of this would be setting a file to be readable writeable and executable by yourself only This would be done by typing chmod 755 set_dvpt do 2 3 Printing your files 2 3 1 Ip printing ascii and postscript files The lpr command is used to print out files If not other options are specified the file will be printed to the Laser et printer Every computer has a default printer that it is sent to See the information on the pstat command for more details on this Flags used with this command are lp d ps115 file More options are available Please look in usr spool p model and view the appropraite file ie laserjer postscript etc Designing ASICs with Mentor Graphics Tools 2 3 Copyright 2000 Mentor Graphics 11 10 01 10 48 am Chapter 2 Using as little UNIX as possible 2 3 2 Ipstat Viewing the printer status The lpstat command is used to check on the status of your printout Flags used with this
33. you define the clock using the commands in the previous example Your design will have only one clock domain Setting Multiple Synchronous Clocks If you have multiple docks in your design that are not in isolated clock domains a register in one domain drives logic connected to a register in another domain then you may define multiple clock signals within the same clock domain 15 2 2 Defining Constraints on Input Pins The input arrival time attribute specifies the maximum delay from outside the present design to the input port and the minimum and maximum slew that signal may exhibit You can specify input arrival constraints at any input ports in your design at any level of the hierarchy All input arrival times start at time zero and cannot be specified relative to a particular dock edge Arrival times are specified by choosing Input Arrival Times from the Specify pull down menu 15 2 3 Defining Constraints on Output Pins The output required time specifies the maximum time allowed from the register or primary input to the output port The time value is always relative to time zero and cannot be specified relative to a particular dock edge You can specify output constraints at any output ports in your design at any level of the hierarchy Required times are specified by choosing Output Setup H old Times from the Specify pull down menu 15 2 4 Defining False Paths False paths are paths in the design
34. 10 01 12 47 pm Chapter 4 Synthesizing VH DL or Verilog of 5 0 volts and a process number of O sigmas 3 Load the library by dicking on the Load Library button Optionally you could simply type the command load library ami05 typ You could substitute another process corner or the ami12 process as well The possible process corners are slow typ and fast Step 4 Read the VHDL file s Input FlowTab 1 Select the Input F lowtab 2 Set the working directory 3 Add the HDL files to the open files list 4 Click on the Read button to synthesize your design to generic gates You should observe the resultant transcript for the following warnings messages e Warnings about unconstrained signals By default all integers are 32 bits wide e Verify number of operators e g adders is as expected e Verify number of sequential elements is as expected Step 5 Optimize the design to the target technology Optimize FlowTab The Optimize F lowTab allows you to specify the following options e Target Technology Choose the desired technology from the picklist e Run type Optimize a design from the specified input files or remap a previ ously synthesized design to a different technology e Extended Optimization Effort f you check the extended optimization effort box Leonardo will perform four optimization passes using different algorithms and keep the best result e Optimize For This field informs Leonardo to keep either the
35. 12 14 01 Designing ASICs with the ADK Design kit and Mentor Graphics Tools GIMSRI2 HIGHER EDUCATION PROGRAM ADKO AS tC Die stig n KEPI Version 2 0 The purpose of this document is to provide university students with the basic flow and procedures for using Mentor Graphic design tools with ADK design kit The usage of this document is intended for student use only and in no way should be percieved as a complete process guide Please refer to standard Mentor Graphics documents for complete pro cess information Successful ASIC Designs with Mentor Tools The First Time Through Copyright 1996 2001 Chapter 1 Installing the ADK 2 2 2 cece eee 1 1 1 1 Setting up the Mentor ADK Environment 00000e eee eeee 1 2 1 1 1 Setting Your Environment c shell example 1 2 1 1 2 Example Mentor Tool Configurations a 1 3 1 1 2 1 SDL only flow using ICFlow 2001 2 or Later 1 3 1 1 2 2 SDL only flow using C x or D x tools aaa 1 3 1 1 2 3 SDL only flow using both ICFlow and C x D x trees 1 4 1 1 2 4 Non Eldo SDL only flow using both ICFlow and C x D x trees 1 4 1 1 2 5 ICFlow 2001 3 and EN2001 1 0002 1 4 1 1 3 Setting Your Location Map Xem tabs KIA GA NAUEK GERA ARUGA RD Wa 1 5 1 2 Setting up Student Accounts 000 eee 1 5 1 2 1 Common User Files 4 6 04 aw KAR PA KG NG BG AR KAG 1 5 1 2 2 Organizing
36. 4 Using the Active Symbol Window to Place a Component Symbol 7 4 7 2 3 Drawing a NEUBUS cccgeverdbcaseectesdeueu KE eeecdeeessetacud 7 5 7 2 3 1 Naming Nets aga namam BARA ED LALA BT AK KAG KA BA LNAG 7 5 7 2 3 2 Using BUSES nna nunnana 7 5 7 2 4 Annotating Properties aa saaana aaae 7 6 7 2 5 Adding Input and Output Ports 0c eee eee 7 6 7 2 6 Adding Power and Ground Symbols eee eee 7 6 7 2 7 Creating Comment Objects on a Schematic Sheet 7 7 7 2 8 Checking a Schematic for Errors 2 2 eee scwweedebedvdeebeudys 7 7 7 2 9 Saving the Schematic punasan a oye Waku Seu Nw de wee ee ew ee 7 7 7 3 Creating a Symbol from a Schematic cee eee eee 7 8 7 3 1 Adding Other Symbol Properties 0c eee eee eee 7 8 7 3 2 Mmodifying One or More Symbol Pproperties 7 9 7 3 3 Creating Comment Objects on a Symbol 7 9 7 3 4 Checking a Symbol 2 co ceuted dots PAS AGUA BAYANG KANA ee seus 7 10 7 3 5 Saving a Symbol saaan kdaaada dude s Di menkndeaiee ee ee 24 pin plea 7 10 Chapter 8 Using the Analog SDL Parts 8 1 8 1 MOSFETS s pa Na UNA alar os AG BKA NAA uses cae Rega S 8 1 8 2 APALIT dirsi IBUKA Ee EN KAPE ER ee BON eRe EE ad ee 8 2 BO ANGGISION 4 dateecswsgodadesd estate NENG NANANG GA es Pouedaess neces 8 3 Chapter 9 Automated IC Layout using IC Station 9 1 9 1 Creating D
37. Cs with Mentor Graphics Tools 12 14 01 11 02 am Copyright 2000 Mentor Graphics Generating Stimulus Opening the Monitor Window The Monitor window displays both the current simulation time and the current values of the signals that you have added to the window To open the M onitor window perform the following steps 1 Select one or more pins nets or busses in the Schematic View window 2 Press the Menu mouse button and choose the following menu path from the popup menu Add 5 Monitors gt Specified 3 Click on the OK button to execute the dialog box For moreinformation refer to the Opening and Adding Data to Windows section of the SimView Common Simulation User s Manual Adding Signals to the Monitor Window To add a signal to the Monitor window perform the following steps 1 Select one or more pins nets or busses in the Schematic View window 2 Press the Menu mouse button and choose the following menu path from the popup menu Add 5 Monitors 5 Selected Deleting a Signal from the Monitor Window To delete one or more signals from the M onitor window perform the followi ng steps 1 Activate the Monitor window by moving the mouse pointer inside the Monitor window and dicking the Stroke drag middle mouse button 2 Select the signal s you want to delete 3 Press the Menu mouse button while keepi ng the mouse pointer inside the Monitor window and choose the following path from the popup menu Delete 5
38. DIF Once you have synthesized and created your EDIF netlist you need to generate an EDDM database and schematic to drive the IC layout tools You do this with the edif2eddm script 1 Enter the edif directory where your EDIF output was written 2 Set your working directory GMGC WD to the current directory 3 edif2eddm design edf where design is the name of your design top above This script will locate the top level of your design from the EDIF file and will create a directory with your design s library name and put this top level circuit in it For example the output for top will reside in a directory called work within your edif directory This is the design that has a schematic and that you can create the necessary viewpoints for before going to IC Layout If you used a different library name than the default work you will see that library name used as the directory for your top level design 4 4 Designing ASICs with Mentor Graphics Tools 11 10 01 12 47 pm Copyright 2000 Mentor Graphics chapter 5 Designing for Testability The following sections describe how to use DF TAdvisor and FastScan with the Mentor Graphics ADK toinsert scan and generate test vectors 5 1 Inserting Scan chains This process has been largely automated by the DF TAdvisor tool The following steps will get you started using a default configuration and you can then experiment with the options as you gain more familiarity with the tools Step 1
39. E Eldo run so all the rules for such apply If you are unfamiliar with using SPICE you should see the DA IC User s Manual Chapter 9 for much more information on the options and use of these features 6 4 2 3 Choosing Probes You need to tell the simulator which nets nodes to save data for during the simulation run If you have a small circuit enabling all nodes is easy and allows you to see data for any of them after simulation Since saving all this data may takea large amount of memory for larger circuits you may choose only certain nodes by selecting them first In either case you then click on Probes under the Setup Results section of the simulation palette This dialog box lets you specify how you want to save probes 6 4 2 4 Selecting Models A model filein SPICE format must be specified so the simulator knows where your MOSFET and other models reside This is specified with the Library item under Setup Other on the simulation palette You can enter multiple library files if your models are in different places The ADK supplies an example model for each technology in 4DK technology accusim You can also specify the name of the library within each file if you have multiple libraries of models in a file The ADK files only have one library so this is optional for those but you might have MIN MAX TYP models for example in your own library files 6 4 2 5 Displaying your Setup At any point you may display the curre
40. E cia 384i 218 ded dos MA ee ee BEE Nay 15 2 15 2 2 Defining Constraints on Input Pins 00022 2 eae 15 2 15 2 3 Defining Constraints on Output Pins 0 2 0000 15 2 15 2 4 Defining False Paths 2226 06 o eeeeaeneanete ede el eaeennees 15 2 15 2 5 Defining Constant Levels nce a ccs sere ws eds PAA Cea e ae eas 15 3 15 2 6 Back Annotating from a SDF File a 15 3 15 3 TIMING Analysis ceceuceedute KAKA uid uapa nada ANG GALANG AS LIGA 15 3 Chapter A ADK Menus and Commands 22222 A 1 Designing ASICs with Mentor Graphics Tools 5 Copyright 1999 Mentor Graphics 12 14 01 1 12 pm Chapter 6 Designing ASI Cs with Mentor Graphics Tools 12 14 01 1 12 pm Copyright 1999 Mentor Graphics chapter 1 Installing the ADK FTP the tar file from Mentor Graphics using the ADK username password The file you need to obtain is adk tar gz Place this file in the directory where you want the kit installed Use GNU zip to uncompress the archive and untar it in this directory gunzip adk tar gz tar xf adk tar After installing the kit you should be sure to change all the permissions and or owners of the files to match your site s convention There is no reason the files need to be owned by any particular user so feel free to make any user the owner if you would like After installing the kit verify that you have the supported version s of the design tools you need Mentor only supports the lib
41. FILE 1717 lichost HHH H HEH HEH HEH HEH HE HEH HE H Setup ADK Library HH HEHE H HEH E E HH HE HE HE HE EHEH H ADK is set to the root of your installation of the ADK setenv ADK project adk You must set the MGC_LOCATION_MAP variable to a map that contains the necessary location map entries for the ADK setenv MGC LOCATION MAP SADK lib location map adk MGC VELOCITYLIB is set to where the technology files for Velocity reside setenv MGC VELOCITYLIB SADK technology velocity Add the directory with ADK scripts and programs to your 1 2 Designing ASICs with Mentor Graphics Tools 12 10 01 4 03 pm Copyright 2000 Mentor Graphics Setti ng up the Mentor ADK Environment path set path SADK bin Spath The environment variable SMGC WD should be set to the current working directory It is suggested that the alias swd be set to setenv MGC WD cwd in the user s cshrc file to make setting the variable easier Optionally you can use the ICF low 2001 2 tools with your existing Falcon tools by installing the IC tools in a separate tree as per Mentor s installation instructions and setting the MGC HOME variable to the IC tools location You then set LEGACY MGC HOME to point to the older MGC tree When you do this you will use adk da and ic from the IC Flow tree and other tools such as QuickSim and Accusim from the other tree 1 1 2 Example Mentor T
42. K technology ic process cell lib Process SADK technology ic process file Rules File SADK technology ic process rules Angle Mode 45 Logic Source SPROJECT layout Logic Source Type EDDM Logic Loading Flat 2 Gotothe ADK Edit palette menu and dick on Open to open the logic source win dow You should see your schematic in a new window 3 Select the core logic if you have more than one piece select them all Then dick on Inst on the DLA Logic palette to place these cells into your layout window Remember you must have previously designed these cells and they must have the name of the phy_comp property on your symbol If you wish to store your completed cells in a location other than your current working directory you will need to set your search path from the IC Station 11 2 Designing ASICs with Mentor Graphics Tools 12 10 01 4 10 pm Copyright 2000 Mentor Graphics Padframe Layout Setup gt SDL menu The search path should look something like this SADK technology ic ami 05 via PROJ ECT cells Thelast is important for it indudes the current or working directory Simply add any other paths you wish to search for your cells 4 Once you have placed the core logic block s you are ready to generate your pad frame Do not place the pads yourself Use the ADK 5Generate Padframe gt AM 0 5 or the appropriate technology for your design pulldown menu to generate the padframe Make l
43. List window displays a tabular listing of signal activity To open a List window perform the following steps 1 Click on the Setup palette button 2 Click on the List common command button in the palette menu If you want signals to automatically appear in the List window select the corresponding pin net or bus in the Schematic View window before you open the List window For more procedural information refer to both the List Window and the Creating a List Window sections of the Getting Started with QuickSim Il Training Workbook Adding Signals to the List Window To add signals to the List window perform the following steps 1 Select a pin net or bus in the Schematic View window 2 Press the Menu right mouse button and choose the following menu path from the popup menu Add gt Lists gt Selected Deleting Signals from the List Window To delete signals from the List window perform the following steps 1 Press the Mouse Menu button and choose the following menu path from the popup menu Delete gt Lists 2 Enter the name s of the signal s that you want to delete in the Signal Name entry box 3 Click on the OK button to execute the dialog box 14 3 4 Using a Monitor Window The Monitor window displays signal and expression values at the current time The following sections contain procedures that you perform to open a Monitor window and both add and delete signals from it 14 4 Designing ASI
44. Optional Project directories contain the data that will become a System Board or ASIC design This directory structure accommodates a combination of any tool use and allows the division of design activities across multiple members and even across multiple design sites A common directory structure for all projects is an enabler for efficient design participation of members of the design team as well as an efficient means for archival and transmission of data The Project Directory is the highest level of the design tree An environmental variable SPROJ ECT NAME is used to reference this directory and is used as a soft path to the design database For the labs used during the term create a directory called designs in home account and use the SDESIGNS environment variable When you start your major project create a project directory and set a environment variable called PROJ ECT It is also suggested to place both of these names in the location map so that the environment variables can override them and make the designs easier to manage should you find the need move or archive the data For each directory only certain types of data should be allowed in it Designing ASI Cs with Mentor Graphics Tools 1 5 Copyright 2000 Mentor Graphics 12 10 01 4 03 pm Chapter 1 Installing the ADK bin binaries scripts simulation vector files etc work compiled HDL design objects under development src source HDL code netlist EDIF
45. SICs with Mentor Graphics Tools 12 14 01 11 02 am Copyright 2000 Mentor Graphics chapter 14 Simulating the Design Using QuickSim II By using QuickSim Il you can apply stimulus to the design run the simulation analyze the results and modify the design based on those results You can then reset the simulator optionally revise or apply more stimulus to the design and start the cycle over When the design functions correctly you can save the stimulus and simulation results directly with the design You can perform various design simulation tasks including the following items e Examine the logic states of signals by tracing listing monitoring and break pointing them e Modify your design during simulation and then re simulate e Simulate your design using any of the following timing modes unit delay linear timing linear timing with constraint checking full timing and full timing with constraint checking e Calculate your design s timing as a function of pin loading and environmental effects such as temperature voltage and process The typical strategy for simulation is an iterative process that has three main phases verify functionality without regard for timing verify functionality accounting for timing effects and verify functionality once the design is placed and routed Although the focus of each phase is different the tasks that you perform within the simulator are very similar 14 1 Setting up the Design Viewp
46. VHDL or Verilog netlists reports tools transcripts and reports 1 3 Setting up Leonardo You need to copy all the data in ADK technology leonardo to your Leonardo library directory cp SADK technology leonardo 4 SEXEMPLAR 1lib This will copy the synthesis libraries and other data necessary for the integration with the Leonardo GUI 1 3 1 Setting up the Leonardo GUI If you wish to add the ADK libraries to the GUI in Leonardo perform the following steps This is optional and unnecessary if you only wish to run L eonardo in batch mode 1 cd EXEMPLAR lib 2 Append the adk devices ini file to the devices ini file cp devices ini d cat d adk_devices ini gt devices ini rm d 3 Edit the devices ini file to add the following DEVICE lines You will need to change the numbers to be sequential after the last number in your device ini file Also if you are using version 2000 1a you will need to change the DEVICE NUMBER line to correctly identify the number of devices you have Version 2000 1b removed this keyword DEVICE_152 AMI 1 2u slow DEVICE_153 AMI 1 2u typ DEVICE_154 AMI 1 2u fast DEVICE_155 AMI 0 5u slow DEVICE_156 AMI 0 5u typ DEVICE_157 AMI 0 5u fast DEVICE_158 TSMC 0 35u slow DEVICE_159 TSMC 0 35u typ DEVICE_1160 TSMC 0 35u fast 1 6 Designing ASICs with Mentor Graphics Tools 12 10 01 4 03 pm Copyright 2000 Mentor Graphics C
47. ace a Component Symbol You perform this procedure if the symbol you want to instantiate is located in a directory of user created Creating a Schematic Move the mouse pointer over to SDL parts and dick to show the SDL parts palette as shown tothe right Clickthe component you wish to instaltiate You can use the FETs with any technology supported by the ADK These are 4 terminal devices so you will need to wire up the bulk as appropriate for your design NOT FOR AMI 1 x The analog components are not available in the AMI 1 2 1 6 technologies If you attempt to use Capacitor them you will get errors later when you try and Resistor instantiate them in your layout You will have to create these components manually in the IC layout Generic tool if you need them and are using the AMI 1 2 1 6 gnd technol ogy ony widd The generic components may be used with the logic portin gates as well They are availablein all technologies portout Move the mouse pointer in the Schematic sheet window and dick to place the ghost image of the component to the position that you desire component symbols 1 Choose the following menu path from the popup menu Instance gt Choose Symbol The Add Instance dialog box appears Click on a component symbol name in the list box If the contents of the list box do not display the name you want use the Navigator buttons to display the directory where the component symbol resides and the
48. ach supported technology This library is subdivided into a separate library for each technology Be sure to select the appropriate technology for the pad libraries so as to match your target technology See the MOSIS web page for more information on the pads http www mosis org SDL Parts This library contains schematic models for the parts that may be used for schematic driven layout SDL These indude four terminal FETs for all technologies and capacitor and resistors for some technologies In addition some generic parts are supplied such as GND VDD and ports A 2 ADK_IC adk_icis the command that will start IC Station with the ADK extensions If you use this command you will have the following additional functionality in IC Station A 2 1 ADK pulldown menu Once you open a cell you will see a new additional menu called ADK in the menu bar This menu allows you to do several tasks specifically related to ADK designs A 2 Show ADK Palette This will change the palette to display the ADK palette menu This is a quick way to display that menu no matter which palette is currently displayed Scale This will display a submenu that will allow you to scale your design based on your target technology You must have your cell reserved for edit and you must bein GE mode to scale It is recommended that you instantiate you final layout into a new GE mode cell and then scale that new cell In this way you can more easily retarget to a dif
49. adk_ic and any other tools you would likein the normal ways after using DA IC See the appropriate chapters of this manual for information on those topics Designing ASICs with Mentor Graphics Tools 6 13 Copyright 2000 Mentor Graphics 12 14 01 11 28 am Chapter 6 Using the DA IC Flow 6 14 Designing ASI Cs with Mentor Graphics Tools 12 14 01 11 28 am Copyright 2000 Mentor Graphics chapter 7 Creating a Schematic 7 1 Invoking Design Architect The design creation process consists of symbol HDL and schematic creation hierarchical interpretation design rule verification and netlist generation Design Architect is the primary tool that you use to create schematic and symbol models Design Architect is a design creation environment that provides you with the following functionality e Schematic capture You can draw a schematic using components from both an ASIC library and your own symbol library e Symbol creation You can create a symbol to represent any collection of con nected components to create a hierarchical block For ADK design kit parts invoke the ADK modified Design Architect ADK bin adk_da Design Architect has been customized to add cell menus for the ADK supported technologies To exit from Design Architect double click the Select mouse button on the Window Menu button which is located at the top left corner of the Design Architect Session window You use the Schematic Editor in Design Architect to c
50. apture schematic information that describes your design A schematic is both a graphical and behavioral description of a circuit You can include detailed information about instances nets connectors test points timing and engineering notes To create a schematic model perform the steps that are detailed in the following sections 7 2 Creating a Schematic 7 2 1 Opening a Schematic Sheet To open a Schematic sheet from the Design Architect Session window perform the following steps 1 Click the Open Sheet icon in the Session palette menu An Open Sheet dialog box appears 2 Enter the name of a new or existing component in the Component Name entry box You can click on the Navigator button to locate a component 3 Click on the OK button to execute the dialog box Designing ASICs with Mentor Graphics Tools 7 1 Copyright 2000 Mentor Graphics 12 14 01 1 08 pm Chapter 7 Creating a Schematic NOTE DA opens schematic by default If you generated the schematic using AutoL ogic change schematic name to opt in Open Sheet options and use Open Design Sheet This overrides default value 5schematic with Model property from Back Annotation file 7 2 2 Choosing and Placing Component Symbols on a Sheet Perform any of the following procedures to choose and place component symbols on a schematic sheet 7 2 2 1 Place a Logic Component Symbol You perform this procedure if you want to instantiate and place a component tha
51. atic 2425 Kama WERE KG kee KA eee NGA sede ee NG 6 2 6 2 1 Opening a Schematic Sheet 02 c eee eee 6 2 6 2 2 Choosing and Placing Component Symbols on a Sheet 6 2 6 2 2 1 Using the ADK_Library Palette to Place a Logic Component Symbol 6 2 6 2 2 2 Using the ADK_Library Palette to Place an SDL Symbol 6 3 6 2 2 3 Using the Dialog Navigator to Place a Component Symbol 6 4 6 2 2 4 Using the Active Symbol Window to Place a Component Symbol 6 4 6 2 3 Drawing a NGUBUS 50 xa Kawi pa TIN Sedeccadedeseadiardesedeeee 6 5 6 2 3 1 Naming Nets 2 4 aaa ma nG edeveieiutessiiandaededed 6 5 6 2 3 2 Using BUSES 24s necacare Hodes DIREK ARN BAWANG Ene na Says 6 5 6 2 4 Annotating Properties aah Rake wee oe ede REE ee eS 6 6 6 2 5 Adding Input and Output Ports 00 eee eee eee 6 6 6 2 6 Adding Power and Ground Symbols eee eee 6 6 6 2 7 Creating Comment Objects on a Schematic Sheet 6 6 6 2 8 Checking a Schematic for Errors 02 0c eee eee 6 7 6 2 9 Saving the Schematic 0 2 2 eee 6 7 6 3 Creating a Symbol from a Schematic cee eee eee 6 8 6 3 1 Adding Other Symbol Properties 0000 022 e ee eee 6 8 6 3 2 Modifying One or More Symbol Properties 6 9 6 3 3 Creating Comment Objects on a Symbol 2000 055 6 9 6 3 4 Checking and Saving a Symbol cee eee eee 6 10 6 4 Simulating
52. ating HDL in ModdSim vcom work work SDESIGNS src count4 vhd and for Verilog you would use vlog work logical lib Verilog_source vlog work work SDESIGNS src count4 v If you do not specify the work logical lib information then the compliers will compile the HDL code into the work library This is simply a compilation step You can invoke the HDL simulator vsim on the compiled object in the work library The simulator is the only tool that uses this compiled object The synthesis tool reads the HDL code into memory without saving the compiled object to disk NOTE If you get an error about can t find work library or running vlib then execute the following two commands in a UNIX shell vlib my path designs work vmap work my_path designs work 4 Fix any errors and explain all warnings 5 Determine the Next Step After your HDL code compiles correctly you can either simulate the compiled object in ModelSim or synthesize the HDL using Leonardo 3 2 Compiling the ADK cell libraries If you want to compile a gate level netlist typically produced by Leonardo that contains ADK ami05 ami12 cells you will need to compile the VITAL VHDL or Verilog cell models into a ModelSim library similar to how you compile your design into the work library 1 Create a ADK work library vlib user student designs adk 2 Map the Logical name to the physical directory created in the previous step vmap adk user student
53. bars at the edge of the layout At this point it is assumed that you have arrived at a satisfactory initial placement for all cells of the layout Prior to autorouting the interconnect you may wish to observe a rats nest view of the signals connecting the various cells This is sometimes useful to the layout technician for determining sources of routing congestion To observe a rats nest of signal connections select Connectivity 5 Net 5 Restructure 5 All signal from the top menu bar It may look a little messy but keep in mind that it doesn t change the layout whatsoever Step 5 AutoRoute the IC cell Autoroute All from the Place 4 Route palette From the palette menu select All from the Autorou subsection of the menu A submenu will appear in the editing window Select Options and E xpert options and select Channel Over Cell Routing From the OCR options menu set the step size to 5 and the Operation M ode Type to Center Weighted OK all the forms and begin routing Depending on the size of the design this may take several minutes When the process has completed the mouse pointer changes back from an hourglass to an arrow and the results of the process are in the transcript Several small overflows may still exist which can be expected for larger designs These overflows are addressed in the next step Step 6 Find Overflows and Route Them This step is necessary even if overflows don t immediately appear in the rou
54. box A new Modify Property dialog box will appear for the next selected property Repeat step 5 until you are finished examining and modifying the selected properties 7 3 3 Creating Comment Objects on a Symbol To create a comment text object perform the following steps 1 2 3 4 5 Choose the Text menu item from the Add popup menu Enter your comment text in the Text entry box Click on the At Location button A ghost image of your comment text moves when you move the mouse Move the ghost image to the location you want to place the text Click on the L eft mouse button To convert symbol body graphics and text into comment objects perform the following steps 6 Select the objects that you want to convert 7 Choose the following pulldown menu path from the menu bar Edit 5 Convert to Comment Design Architect converts the selected object s into a comment object s When you unselect the object the comment object will be a different color than either the symbol body graphics or text Designing ASI Cs with Mentor Graphics Tools 7 9 Copyright 2000 Mentor Graphics 12 14 01 1 08 pm Chapter 7 Creating a Schematic 7 3 4 Checking a Symbol All symbols must pass a set of required checks before you can place them on a schematic sheet You can check your design at various points in the development cyde You can direct Design Architect to enforce optional design rules in addition to the required ones Your des
55. can use a number of conditions as breakpoints during the simulation to isolate specific problems You can interrupt the simulation based on either a simulation expression or signal state You can also interrupt the simulation based on the activation of a VHDL object T he following sections describe the procedures for adding reporting and deleting breakpoints Adding Breakpoints To add a breakpoint perform the following steps 1 Choose the following pulldown menu path from the menu bar Add 5 Breakpoint The Add Breakpoint dialog box appears 2 Click on the Expression choice button 3 Enter a signal name of either a pin net or bus in the E xpression entry box 4 Click on the On change button to specify that the breakpoint occurs when the evaluation of the signal changes 5 Specify in the On occurrence entry box how many times the breakpoint condition must occur before QuickSim II interrupts the simulation 6 Click on the OK button to execute the dialog box To view a report on all of the defined breakpoints choose the following pulldown menu path from the menu bar Report gt Setup 5 Breakpoints Deleting Breakpoints To delete a breakpoint perform the following steps 1 Choose the following pulldown menu path from the menu bar Delete gt Breakpoints The Delete Breakpoints dialog box appears 2 Click on the Expression choice button Designing ASICs with Mentor Graphics Tools 14 11 Copyright 2000 Mentor Graphics
56. d also save this netlist file in a separate directory e g DESIGNS netlist You will usually save two netlists e EDIF netlist for IC Layout e VHDL or Verilog Netlist for simulation in M odelSim 4 2 Synthesizing HDL Using Spectrum Command Line Mode If you prefer to write scripts or just want a way to automate your synthesis runs you don t have to use the Lenardo GUI All you need is a script and then the command spectrum file script name will run the synthesis using your script Here is an example of a script that will read in several VHDL files and synthesize to the ADK ADKsynthesis script set vhdl_write_component_package FALSE set vhdl_write_use_packages library ieee adk use ieee std logic 1164 all use adk all set edifout power ground style is net TRUE load library ami05 typ analyze abmux vhd format vhdl work work analyze alu vhd format vhdl work work analyze control vhd format vhdl work work analyze datamux vhd format vhdl work work analyze top vhd format vhdl work work elaborate top architecture structure work work ungroup all hierarchy Designing ASICs with Mentor Graphics Tools 4 3 Copyright 2000 Mentor Graphics 11 10 01 12 47 pm Chapter 4 Synthesizing VH DL or Verilog optimize ta ami05 typ effort standard macro area report area cell write edif top edf format edif write vhdlout top vhd format vhdl 4 3 Creating a EDDM Schematic from E
57. dow active 6 3 1 Adding Other Symbol Properties In most cases you will not need to add properties The symbol generation function in Design Architect will add all the necessary properties and pins To add one or more properties perform the following steps 1 Select one or more object diamonds 2 Choose the following popup menu path Properties 5 Add 5 Add Multiple Properties An Add Multiple Properties dialog box appears 3 Enter the property name and value pair for each property that you want add 4 Click on the OK button to execute the dialog box An ADD PR prompt bar appears 5 Movethe mouse pointer to the location that you want to add the new property and click on the Select mouse button 6 8 Designing ASI Cs with Mentor Graphics Tools 12 14 01 11 28 am Copyright 2000 Mentor Graphics 6 Creating a Symbol from a Schematic Repeat the previous step until you have added all of the properties that you specified in the Add Multiple Properties dialog box 6 3 2 Modifying One or More Symbol Properties 1 2 Select the object diamond s that have attached properties you want to modify Choose the following popup menu path Property 5 Change Values The Modify Properties dialog box appears 3 Select one or more property name value pairs in the list box 4 Click on the OK button to execute the dialog box A Modify Property dialog box appears which contains the values and attributes of a single property
58. e manual IC Station Device L evd Automation DLA Manual tt PLEASE NOTE Several key steps in this manual cite ample shortcut macros that are directory structure dependent Its assumed that the administrator responsible for installing the development environment kit has updated the macros for the directory structure the library is being created in Fields in the documentation below such as process mnemonic and process are dependent on the macro updates 10 1 Creating Design Viewpoints Before the actual layout process begins the design needs to be prepared for use with the layout tools In the same way simulation viewpoints were created for the part two more are required for layout creation and verification The viewpoints are created for the CTrace and Csdl tools specifically This process is automated by calling the script adk dve from your design project directory If you did not use adk daic to create your schematic run SADK bin adk dve lt design gt Do not run this script if you use adk daic Using adk daic will create all the necessary viewpoints if you follow the directions in Chapter 6 The adk_dve script creates the following viewpoints for IC station 1 Viewpoint Creation for the Csdl A viewpoint called sdl is created where the primitive called elemen is added A string parameter named lambda is also added and assigned the value of lambda for the process specified Some other properties
59. e this option to load a new rules file e Extract This function will perform a lumped mask level extraction of your circuit suitable for simulation with ELDO Mach TA or Accusim e LVS Run a mask level LVS of your cell e Report LVS reporting functions The options in this menu allow you to view the LVS report and to check your LVS errors if any Finally the last item is Repeat This is a toggle switch that will turn on or off the repeatable functions Functions with an asterisk by them will repeat If you do not want those functions to repeat click on the Repeat item to turn it off and dick on it again to turn it back on A 2 3 ADK Commands In addition to the new menus there are some new commands or macros that have been included with adk_ic Some of these commands are specific to creating and maintaining your standard cells and are offered as examples that you can modify for your own needs To use any of these commands simply type them in the cell window A prompt bar will appear with your command in it A 4 Designing ASICs with Mentor Graphics Tools 12 14 01 11 28 am Copyright 2000 Mentor Graphics Table A 1 Fundion pc pp pr NWC pwc pfp ec5 ec12 ab1 Description Place a poly contact places a poly contact centered at the current cursor position Place a port contact creates a port and places it where you dick Places standard cell power rails Places a VDD and a GND powe
60. e waveform activity that you want to save 6 Click on the OK button to execute the dialog box SimView saves the waveform activity in the Forcefile at the pathname that you specified 14 4 3 2 Loading and Viewing Waveform Stimulus from a Forcefile To save the waveforms that you have created perform the following steps 1 Reset the simulator to time zero by performing the following steps a Click on the RESET common command button in the palette menu The Reset dialog box appears b Click on the State radio button c Click on the OK button to execute the dialog box SimView resets the simulator time to zero 2 Press the Menu mouse button and choose the following menu path from the popup menu Force gt From File The Load Forcefile dialog box appears 3 Enter the name of the Forcefile in the Pathname entry box 4 Click on the OK button to execute the dialog box SimView executes the Force commands that were in the Forcefile To view the stimulus waveforms perform the following steps 5 Click on the red WF EDITOR palette button The Waveform Editor palette icons appear in the palette menu 6 Select the pins nets and busses in the Schematic View window that correspond to your Forcefile stimulus you want to view SimView highlights the selected objects 7 Click on the EDIT WAVEFORM icon in the Waveform Editor palette menu Designing ASICs with Mentor Graphics Tools 14 9 Copyright 2000 Mentor Graphics 12 14 01 11 02 am
61. ected from node VDD to node 0 ground and has magnitude 5 Volts 6 4 3 Running the Simulator Finally you are ready to actually run the simulation once you have completed all the setup and extracted your netlist Do to this dick on Run under the Simulator section of the simulation palette The Eldo simulator will run with its transcript in a separate window Any errors or warnings can be viewed before the window is dosed If everything ran smoothly you are ready to look at your results If you had any errors or warnings you should go back through the setup to be sure that everything is set properly for your intended simulation type A full log of the run can be viewed through View Log under Simulation also Common warnings are due to floating nodes Be sure to have a source on all inputs to edit the netlist to include proper inputs for your circuit 6 4 4 Viewing Simulation Results Once your simulation has competed successfully you can view the results by plotting various inputs outputs dependi ng on how you set up the probes The simplest method for viewing results is to a Select View gt invoke Viewer under the Results section of the simulation palette This will start the viewer window and connect it to your design b Select the type of object you want to view from the Xview menu under Results You can choose from Voltages Currents and Differentials between nodes If the case of Voltages and Currents yo
62. elected instances 14 7 Resetting the Simulator You can reset your simulation environment to start a simulation again at a time domain of zero or to reinstate the setup conditions for SimView and or QuickSim II that werein effect when you invoked the simulator You can use any or all of the following choices to reset a simulation e State Resets the simulation time to zero No other conditions that previously existed are reinstated stimulus are maintained but the data in the Results WDB is removed e SimView setup Reinstates the SimView setup conditions that were in effect when you invoked the simulator SimView closes all windows except the Session window deletes action lists and expression definitions and resets all bus defini tions synonyms probes groups and selection filters to their original settings e QuickSim setup Reinstates the kernel setup conditions that were in effect 14 10 Designing ASI Cs with Mentor Graphics Tools 12 14 01 11 02 am Copyright 2000 Mentor Graphics Using QuickSim to Debug your design when you invoked the simulator such as the timing modes delay modes check ing modes settings keep list run setup and breakpoint settings list To reset the simulator to time 0 and reinitialize the nodes in the design type reset state d 14 8 Using QuickSim to Debug your design 14 8 1 Using Breakpoints Breakpoints provide you with a powerful means to troubleshoot problems in your design You
63. enable 1 0 force clock 0 0 1 25 repeat 50 apply stimulus force clear 0 10 force enable 0 430 force enable 1 530 3 5 3 Force File Example 2 loops set time O force clock 0 0 1 25 repeat 50 force reset 1 0 force enter_sensor 0 0 force exit_sensor 0 0 force reset 0 30 count up to 15 for set num O num lt 15 incr num 1 incr time 50 force enter sensor 1 time incr time 50 force enter sensor 0 Stime incr time 100 force exit sensor 1 Stime incr time 50 force exit sensor O Stime incr time 50 3 4 Designing ASICs with Mentor Graphics Tools 11 10 01 10 48 am Copyright 2000 Mentor Graphics Applying sti mul us incr time 200 force exit sensor 1 Stime incr time 50 force exit sensor 0 Stime incr time 100 force exit sensor 1 Stime incr time 50 force exit sensor 0 time 3 5 4 VHDL Test Bench example LIBRARY ieee USE ieee std logic 1164 all ENTITY bcd tb IS END bcd tb ARCHITECTURE test OF bcd tb IS COMPONENT bcd pre compiled Device to Test PORT rst clk enable load up_down IN std_logic data IN std_logic_vector 3 downto 0 bed out OUT std_logic_vector 6 downto 0 END COMPONENT SIGNAL rst clk enable load up_down std_logic SIGNAL data std_logic_vector 3 downto 0 SIGNAL bcd out std_logic_vector 6 downto 0 BEGIN ul bed PORT MAP clk gt clk rst gt rst load gt load enable gt enable up_down gt up_down data gt data bcd_ou
64. enerally easier to have DA create the default symbol with all the required properties and then manually move the pins to their proper location You use the Symbol Editor in Design Architect to create and modify symbols By creating symbols that represents a portion of circuitry and then using themin another schematic you can create a logical hierarchy To generate a symbol from an existing schematic perform the following steps from within the Schematic Editor 1 Select the MISC 5 Generate Symbol menu item in the schematic editor 2 Usethe default values in the resulting form 3 After DA generates the symbol you can move DON T DELETE or RENAME the ins A kara with a rectangular symbol body and pins on the edges of the symbol body should appear in a Symbol Editor window All input pins are on the left side and all output pins are on the right DO NOT DELETE ANY PROPERTIES ON THE SYMBOL You can move the location of the pins by selecting the pin diamond shape on the symbol body the pin name e g clock and the pintype property e g IN If you do not move all three of these items when you change the pin ordering on the symbol bad things may happen with downstream tools e g QuickSim If you can not select these three items you may need to change the selection filter Edit 5 Selection Filter with the symbol window active 7 3 1 Adding Other Symbol Properties In most cases you will not need to add properties The sy
65. esign Viewpoints 00 cee eee 9 1 9 2 Invoke G Station cecccreakeecednnd HAI bA dee her kA a a AA U aa E 9 2 9 3 Autoplacement and Routing 2 00 c eee eee 9 2 9 4 Verifying Project LAVOUL Xa cndateue KABIL cw wattn ae ed ANN NA 9 5 9 5 Full Layout Verification 2250 05 66000 e cee eee bee be bee eee ees 9 6 Designing ASICs with Mentor Graphics Tools 3 Copyright 1999 Mentor Graphics 12 14 01 1 12 pm Chapter Chapter 10 Schematic Driven Layout using IC Station 10 1 10 1 Creating Design Viewpoints 002 10 1 10 2 Invoke IC Station 2caccecakecscinvatas taradodank wage nadia Se bees 10 2 10 3 Creating a cell for SDL 0 0 cee eee 10 2 10 4 Placing components into your layout 00 eeeeeeeee 10 3 10 4 1 AutoPlace instances sexe ast de kok eee ENG wet ho then ad ade bee eae 10 3 10 4 2 Manually placing instances 0c eee eee 10 3 10 5 Placing ports into your layout 0 2 000 e ee eee 10 3 10 6 Routing your cell 2eusuterre ute eee ee ees peau wis KARATE ody 10 4 10 6 1 Semi automatic routing 00 cee ee eee 10 4 10 6 2 Routing with paths xa ka eh bod ed shee AA BAG GRAD Aha K Ea dade 10 4 10 6 3 Routing by placing shapes a 10 4 10 6 4 Placing contacts and vias 4 ca de coats s Pewee AG NAAN GANG bu ae 10 5 10 6 5 Adding well contacts 00 cee eee 10 5 10 7 Verifying your layout a6 coweuewand sot ase Qe
66. etween schematic and layout Verify the layout for consistency with the transistor level schematic of your design Do this by returning to the main Cstation palette and selecting the ICtrace M mask level LVS option Click on LVS in the Ctrace M palette and in the form which appears enter the Source Name PROJ ECT LVS and dick on the Setup LVS button In the Setup LVS form change the following items and dick OK If you re already in the ADK Edit menu you can go directly to this dialog box by clicking on LVS Ground Names VSS GND Recognize Gates Yes Designing ASICs with Mentor Graphics Tools 9 5 Copyright 2000 Mentor Graphics 12 10 01 4 10 pm Chapter 9 Automated IC Layout using IC Station Step 4 View the connectivity check results When the check is complete the bottom message bar will read Mask results database loaded To view the results you can select Report 5 LVS from the palette menu Look for that magic smiley face If a nasty X appears instead go back and make certain that the LVS viewpoint has been properly setup and follow the above procedures again When doing so look for potential sources of discrepanci es between the schematic and how the layout was generated Step 5 Save the IC layout Save your completed project layout by selecting File 5 Cell 5 Save Cell gt Current Context 9 5 Full Layout Verification You may check your layout for design rule violations at any time using ICrules You can
67. evelopment cyde HUT You can direct Design Architect to enforce optional Edit Text design rules in addition to the required ones Your SSS SSS design must conform to certain design rules before you Check amp Save Hierarchy can successfully use downstream tools to either analyze Setup sim or simulate it If your design violates a required design rule a downstream tool may issue a warning upon invocation Mult Run Analysis therefore it is important that you first execute the Setup Results design checks to ensure that the results of analysis and 77 Temp Params simulation are both valid and accurate Probes pee To check and save your symbol choose the following Delete from the palette Setup Other Check amp Save Include Library Commands Options 6 4 Simulating your Design At any point in the design process you may enter simulation mode and simulate your circuit from within Design Architect IC In addition to running your Show simulations entering simulation mode will create all of Hetlist the necessary viewpoints for analog simulation Accusim or Eldo digital simulation QuickSim II Write layout IC and extraction Fre Metlat Edit Text Commands Simulation Fun 6 4 1 Entering Simulation Mode An S Results To enter simulation mode and create the viewpoints necessary for simulation and downstream tools you A Probe need to go back to the schematic palette and select the MPASUFES _ techn
68. f the form bus 15 0 where the numbers represent the bits in the bus Designing ASICs with Mentor Graphics Tools 65 Copyright 2000 Mentor Graphics 12 14 01 11 28 am Chapter 6 Using the DA IC Flow 5 Now add wires from your components to the bus To connect a wire to the bus dick on the bus or double dick if the wire should terminate on the bus 6 A bus ripper will appear and you will be prompted to enter the bit number for this net You can change these later if you change your mind If the Check Sheet function reports unconnected pins warnings you can add a Class property with a value of dangle to inform DA IC that this pin is supposed to dangle 7 Select pin 8 Add Class property with value of dangle 6 2 4 Annotating Properties Property annotation is the process of adding design information in the form of properties to both schematics and symbols To annotate properties on an instance follow these steps 1 Setup Selection Filter 2 Select the Object to which you want to add a property 3 Select the Properties gt Add 5 Single Item menu in the Schematic Popup menu to add a new property to the symbol 4 Select the Properties gt Modify menu item in the Schematic Popup menu to change an existing property on a symbol If you have multiple objects selected Design Architect should rotate through the selected objects allowing you to modify the property on each occurrence 6 2 5 Adding Input and Output Ports
69. f the p FET to your power rail and bias the bulk of the n FET to ground There are several properties that can be used to change how the MOSFETs will be generated in IC Station Other properties are used only for simulation Table 8 1 Summarizes the properties you might want to change depending on your needs Table 8 1 MOSFET Properties pilat Default Property Description Vaule Simulation Layout length length in lambda 2 no yes width width in lambda 5 no yes alength scaled length in microns 24tlengthtl yes no e6 awidth scaled width in microns 2 width le yes no 6 model name of the device nmos4 or no yes generator to use for this pmos4 device fold number of folds for large O no yes transistors The resistor and capacitor are not available in the AMI 1 2 1 6 micron processes Designing ASICs with Mentor Graphics Tools 8 1 Copyright 2000 Mentor Graphics 12 14 01 1 08 pm Chapter 8 Using the Analog SDL Parts 8 2 Capacitor For designs not using the AMI 1 2 1 6 micron process a capacitor is available This capacitor uses the electrode layer effectively a dual poly process with the poly layer as the plates of the capacitor There are several properties that can be modified by the designer that will affect how the capacitor is drawn T hese properties are shown in Table 8 2 Table 8 2 Capacitor Properties Default Simulat Property Description Va le lon Layout W width in lambda 10 no yes h height in lambda
70. ferent technology should you later decide to do so Generate Padframe This will display a submenu where you can automati cally generate a padframe for a 40 pin tinychip based on your target technol ogy See the chapter Automatic Padframe Generation for more information Designing ASICs with Mentor Graphics Tools 12 14 01 11 28 am Copyright 2000 Mentor Graphics A 2 2 ADK palette menu A new palette menu has been created which contains most of the commonly used operations that you will need for doing designs with the ADK You can show this palette by selecting ADK 5Show ADK Palette from the pulldown menu or by clicking on ADK Edit at the bottom of the session palette The first section of the ADK Edit menu will let you gain quick access to other palette menus Top will take you to the top level session menu Edit will take you to the standard edit menu for more editi ng functions than are presented on the ADK Edit menu PAR will take you to the place and route palette menu for placement and routing of your standard cell designs The next section labeled SDL has functions to help you preform your schematic driven layout Logic This will display a submenu that will let you set your logic source close the logic or update your logic should you have made an update outside of IC Station Open opens the current logic source in a schematic window Place This will display a submenu to allow you to select instances or ports and
71. file name At this point you have an HDL netlist with scan chains and a pattern file with the test patterns used to test your circuit This is only a very basic introduction to using the DFT tools See the Mentor documentation for more features and on how to debug your circuit should you have any problems with these tools on your netlist Designing ASICs with Mentor Graphics Tools 5 3 Copyright 2000 Mentor Graphics 11 10 01 10 48 am Chapter 5 Designing for Testability 5 4 Designing ASI Cs with Mentor Graphics Tools 11 10 01 10 48 am Copyright 2000 Mentor Graphics chapter 6 Using the DA IC Flow Starting with the CFlow 2001 1 tools Mentor has introduced a customized version of Design Architect DA that simplifies doing schematic based IC designs As of ADK 2 0 this flow is now supported and recommended especially for analog and non standard cell based designs It can be used for any type of design but its strength is in the capture modification and simulation of transistor based designs To take full advantage of the integrated environment you should also have Eldo installed Eldo is part of the Anacad distribution from Mentor You only need the Eldo engine and not any of the supporting tools in that distribution to take advantage of the features in DA IC While Eldo is not installed in your Mentor tree it has its own environment that needs to be properly set up to work Eldo should be in your path The CFlow distrib
72. fy the layer and width of the path via the Options button You can also specify other options for how the path should be drawn Once you have these options set simply click at each point where you want the path to go You will see the path being drawn as you go Double click at the end and the path will be complete You can then go on and repeat this process for other paths you wish to place 10 6 3 Routing by placing shapes Optionally you can have complete control over the size shape and placement of the routes by placing geometric shapes explicitly You do this with the Shape 10 4 Designing ASICs with Mentor Graphics Tools 12 14 01 1 07 pm Copyright 2000 Mentor Graphics Veri fyi ng your layout command on the ADK Edit menu When you dick on Shape you are prompted for points that will define the corners of a polygon You can use the Options button to select the layer on which the shape should be drawn 10 6 4 Placing contacts and vias Sooner or later you will need to place contacts from metal to poly or vias between metal layers If you are using the routing tool then vias within your routes are places automatically Contacts to poly and other methods of routing will require manual contact via placement however There are some handy macros that have been defined in the ADK that will make placing contacts and vias easier The pc or poly contact macro will place a poly contact to metal 1 centered at the current cursor position
73. he Add Instance dialog box appears 2 Click on a component symbol name in the list box If the contents of the list box do not display the name you want use the Navigator buttons to display the directory where the component symbol resides and then click on it 3 If the name of the component symbol you want is not the default name perform the following steps a Click on the Explore Contents Navigator button The list box displays the contents of the component b Click on the name of the component symbol you want 4 Click the OK button to execute the dialog box The ADD IN prompt bar appears and the mouse pointer becomes a location cursor 5 Movethe cursor into the Schematic Editor window A ghost image of the symbol moves with your mouse pointer 6 Movethe ghost image to the desired location and click the Select mouse button to instantiate the symbol 6 2 2 4 Using the Active Symbol Window to Place a Component Sym bol The active symbol is the symbol that the Active Symbol window displays To place a symbol that is in this window perform the following steps 1 Choose Active Symbol menu item from the Instance popup menu The PLA AC S prompt bar appears 2 Movethe mouse pointer inside the Schematic sheet window and click the Select mouse button to place the symbol in the desired location 6 4 Designing ASI Cs with Mentor Graphics Tools 12 14 01 11 28 am Copyright 2000 Mentor Graphics Creati ng a Schematic 6 2 3
74. he text 7 Click on the Select mouse button This places the text comment on your schematic sheet 6 2 8 Checking a Schematic for Errors You must check your schematic sheet before you can use it for some downstream tools You can check your design at various points in the development cycle In Design Architect you can perform checks of symbols schematics and entire designs You can direct Design Architect I C to enforce optional design rules in addition to the required ones Your design must conform to certain design rules before you can successfully use downstream tools to either analyze or simulate it If your design violates a required design rule a downstream tool may issue a warning upon invocation therefore it is important that you first execute the design checks to ensure that the results of analysis and simulation are both valid and accurate To check your design click on Check amp Save from the Schematic palette which you should get back to if you arein another palette This checks and then saves your schematic If you want to only check your schematic us the File pull down menu and choose Check Schematic 6 2 9 Saving the Schematic To save the schematic choose the following menu path from the menu bar File 5 Save Sheet This will save the sheet even if it does not pass a schematic check Designing ASI Cs with Mentor Graphics Tools 6 7 Copyright 2000 Mentor Graphics 12 14 01 11 28 am Chapter 6 Using the DA IC F
75. hecking your ADK Version 4 Now you should run Leonardo and verify that under the ASIC section of the technology flowtab you see ADK Under ADK you should see all six of these libraries 1 4 Checking your ADK Version If you are curious about what version of the ADK you are running or if instructed to find out for support purposes you can do this with the adk ver command The option a will also show you the current versions of several Mentor tools that the ADK supports such as IC Station DA ModelSim etc Designing ASI Cs with Mentor Graphics Tools 1 7 Copyright 2000 Mentor Graphics 12 10 01 4 03 pm Chapter 1 Installing the ADK 1 8 Designing ASI Cs with Mentor Graphics Tools 12 10 01 4 03 pm Copyright 2000 Mentor Graphics chapter 2 Using as little UNIX as possible 2 1 Setting up your Environment Project directories contain the data that will become a System Board or ASIC design Figure 1 represents the development of a design tree from the System or Board perspective This directory structure accommodates a combination of any tool use and allows the division of design activities across multiple members and even across multiple design sites A common directory structure for all projects is an enabler for efficient design participation of members of the design team as well as an efficient means for archival and transmission of data The Project Directory is the highest level of the design tree An environ
76. ic Source SPROJECT Layout Logic Source Type EDDM Logic Loading Flat PROJ ECT is your path to the part you created Table 1 shows the valid options for the other fields All other options should be left at default values It is very important to change the logic loading to flat if you have any logic other than standard cells in your design It is always safe to load flat so it is recommended to do so always Once you click OK on this dialog box a cell window will appear having the name of the design 9 2 Designing ASI Cs with Mentor Graphics Tools 12 10 01 4 10 pm Copyright 2000 Mentor Graphics Autoplacenent and Routing Table 1 Variable Fields for Cell Creataion Variable Name Possible Values Description process cell lib ami05 These are the libraries of standard cells ami12 and pads Currently only pads are avail tsmc035 able for tsmc035 The library for ami15 and ami12 are both ami12 No character ization has yet been done for ami15 process filel ami05 These are the process files for the cur ami12 rently available processes ami15 tsmc035 process rules ami05 rules The standard rules files are for all flows ami05 accusim rules except Accusim backannotation If you ami12 rules want to extract for backannotation to ami12 accusim rules Accusim use the accusim rules file ami15 rules ami15 accusim rules tsmc035 rules tsmc035 accusim rules Step 2 AutoFloorplan the IC cell
77. ife easy on yourself NEVER EDIT OR RELOCATE PAD CELLS 5 View the entire cell now to see the padframe and your logic Shift F 8 You should see the entire padframe with corner pads the pads you asked for and spacer pads for all the empty spaces or analog pads for the case of the ami12 technology You will also see overflows showing which ports get wired to which pins 6 At this point you might notice that your core logic should be rotated flipped or moved to make routing easier Do that now but be careful not to move the pads 7 After finalizing the placement of your core logic you can route the pads to the core You can do this manually or automatically 8 Toautoroute dick on PAR on the ADK Edit palette menu to bring up the Place amp Route palette menu Then click on All under Autorou On the prompt bar that appears dick Options and unselect Expand Channds from the menu Click OK on the menu and prompt bar to autoroute the pads 9 Now takea look at the final layout and fix any problems For example you might not like the width or placement of the power busses You can edit these routes or opt to manually route them initially until you are satisfied with the final result You should also check that the pads did not move during an autoroute If they did you need to unplace all the pads then rerun the generator and autoroute again verifying that Expand Channds is unseletced This is the most common reason for this problem
78. ign must conform to certain design rules before you can successfully use downstream tools to either analyze or simulate it If your design violates a required design rule a downstream tool may issue a warning upon invocation therefore it is important that you first execute the design checks to ensure that the results of analysis and simulation are both valid and accurate To check your symbol choose the following menu path from the menu bar Check 5 With Defaults Design Architect displays any errors and warnings in the Check status window 7 3 5 Saving a Symbol To save your symbol execute the following menu path from the menu bar File 5 Save Design Architect saves your symbol to disk 7 10 Designing ASI Cs with Mentor Graphics Tools 12 14 01 1 08 pm Copyright 2000 Mentor Graphics chapter 8 Using the Analog SDL Parts The ADK supports a high resistance poly2 resistor and a simple capacitor for analog designs as well as 4 terminal MOSFETs This chapter describes the model properties used to drive the layout of these devices If you wish to create addtional types of devices please refer to the IC Station Device Level Automation DLA Manual from Mentor Graphics 8 1 MOSFETs The MOSFET devices for the ADK are 4 terminal devices You must ensure that the bulk is properly connected for these devices to work If if you are doing digital designs and usually use 3 terminal devices you will almost vertainly want to bias the bulk o
79. ion window Schematic View List Trace Monitor Waveform Database and Waveform After you invoke QuickSim you setup the SimView environment as described in the following sections 14 3 Setting up the SimView Windows QuickSim Il uses the SimView common interface for all user interactions with the simulation kernel SimView is used by all Classic Mentor simulation products QuickHDL does not use SimView 14 3 1 Opening the Schematic View Window The Schematic View window displays the schematic of your design Perform the following steps to view your design in a Schematic View window 1 Click on the Setup palette button The Setup palette icons appear in the palette menu 2 Click on the Open Sheet icon in the palette menu The schematic of the design that you invoked QuickSim Il on appears ina Schematic View window The Schematic View window contains a schematic sheet This window enables you to view the design hierarchically You can graphically select and unselect design objects in the Schematic View window If you open a schematic sheet on a VHDL design an interactive list window appears Back annotations appear in the Schematic View window and are highlighted you can also hide them from view 14 3 2 Using a Trace Window The Trace window contains a waveform display of signal bus and expression values You can view stimulus in the Trace window before and after running a simulation This window uses line color s
80. is command are e a This will show all the file in your directory including the dot files Usage 1s a e F This will indicate directories by at after the name and executables by a after the name Usage 1s aF 2 2 4 cp CoPy The cp command is used to copy files The syntax is cp source target cp filel file2 copys fileltoa new file named file2 The cp command can also be used to copy a file from one directory to another e Tocopy a file into a subdirectory type cp file directory name This will copy the file to another file of the same name in the subdirectory of directory name e Tocopy a file from another users directory type cp bob file This will copy a file from the main directory of the user user nameto the directory in which you are currently located F lags used for this command are e r This will copy the directory all of its files and any subdirectories to the target directory Usage cp r source directory target directory 2 2 Designing ASICs with Mentor Graphics Tools 11 10 01 10 48 am Copyright 2000 Mentor Graphics Printing your files 2 2 5 mv MoVe The mv command is similar to the cp command however it will remove filel when file2 is created 2 2 6 rm ReMove Therm command is used to delete a file Type rm file Flags used with this command e r This will remove a directory and all of the files in that directory Usage rm r directory 2 2 7 more The more command is used
81. k ic as appropriate 1 1 2 5 ICFlow 2001 3 and EN2001 1 Based on pre release information these two sets of tools may coexist in the same Mentor tree They are scheduled to be released in December 2001 Check your release notes and also the ADK web pages for further information If this is true you can install all the tools in one tree and only set MGC_HOME Donot set LEGACY MGC HOME and all the scripts will work for you so long as the tool you wanted is installed 1 4 Designing ASICs with Mentor Graphics Tools 12 10 01 4 03 pm Copyright 2000 Mentor Graphics Setting up Student Accounts 1 1 3 Setting Your Location Map The ADK requires the following location map entries These are induded in an example location map in SADK 1ib l1location map adk and should be merged with your standard map MGC LOCATION MAP 2 Need to point to a valid installation of GENLIB SMGC_GENLIB idea_tree libraries gen_lib Required root of ADK tree SADK project ADK Set MGC_WD to something that can be overridden in the envi ronment SMGC_WD tmp HOME will be replaced with the user s home directory SHOME tmp 1 2 Setting up Student Accounts 1 2 1 Common User Files The environment variable MGC_WD should be set to the current working directory You may want to create an alias swd set to setenv MGC WD cwd in the users cshrc file to make setti ng the variable easier 1 2 2 Organizing Design Data
82. lock v enable v output 0 v output 1 v output 2 v output 3 Designing ASICs with Mentor Graphics Tools 13 1 Copyright 2000 Mentor Graphics 12 14 01 11 02 am Chapter 13 Performing Post L ayout Verification using Mach TA run tVvend dc count4 tv This script performs initial DC analysis selects which port pins signals to plot and starts test vector analysis with test vectors in a file called count4 tv 13 2 Running Test Vectors and Viewing Results Step 1 Invoking Mach TA Toinvoke Mach TA on a netlist using the nominal ami05 technology corner case mta t SADK technology mta ami05 tc NOM design mta sp This brings up the application and loads the design To execute a pre created dofile type dof design dofile namej do at the command line to begin analysis Commands can also be typed in manually on the comanaline in the lower command window See the previous section on dofiles for example commands Step 2 Viewing Results Once test vector analysis has passed and hopefully completed the simulation waveforms selected by the plot node_name command can be viewed from Tools Wave Viewer drop down menu If the display doesn t initially look correct select the equal button on the top row of the window to view the entire simulation period Given the case where the test vectors were derived from the Modelsim simulation results the simulation output from both tools should be comparable 13 2 Designing A
83. low 6 3 Creating a Symbol from a Schematic For student use you should not manually create symbols It is generally easier to have DA create the default symbol with all the required properties and then manually move the pins to their proper location You use the Symbol Editor in Design Architect to create and modify symbols By creating symbols that represents a portion of circuitry and then using themin another schematic you can create a logical hierarchy To generate a symbol from an existing schematic perform the following steps from within the Schematic Editor 1 Select the MISC 5 Generate Symbol menu item in the schematic editor 2 Usethe default values in the resulting form 3 After DA generates the symbol you can move DON T DELETE or RENAME the ins A kara with a rectangular symbol body and pins on the edges of the symbol body should appear in a Symbol Editor window All input pins are on the left side and all output pins are on the right DO NOT DELETE ANY PROPERTIES ON THE SYMBOL You can move the location of the pins by selecting the pin diamond shape on the symbol body the pin name e g clock and the pintype property e g IN If you do not move all three of these items when you change the pin ordering on the symbol bad things may happen with downstream tools e g QuickSim If you can not select these three items you may need to change the selection filter Edit 5 Selection Filter with the symbol win
84. mbol generation function in Design Architect will add all the necessary properties and pins To add one or more properties perform the following steps 1 Select one or more object diamonds 2 Choose the following popup menu path Properties 5 Add 5 Add Multiple Properties An Add Multiple Properties dialog box appears 3 Enter the property name and value pair for each property that you want add 4 Click on the OK button to execute the dialog box An ADD PR prompt bar appears 5 Movethe mouse pointer to the location that you want to add the new property and click on the Select mouse button 7 8 Designing ASICs with Mentor Graphics Tools 12 14 01 1 08 pm Copyright 2000 Mentor Graphics 6 Creating a Symbol from a Schematic Repeat the previous step until you have added all of the properties that you specified in the Add Multiple Properties dialog box 7 3 2 Mmodifying One or More Symbol Pproperties 1 2 Select the object diamond s that have attached properties you want to modify Choose the following popup menu path Property 5 Change Values The Modify Properties dialog box appears 3 Select one or more property name value pairs in the list box 4 Click on the OK button to execute the dialog box A Modify Property dialog box appears which contains the values and attributes of a single property 5 Change any of the property attributes in the dialog box 6 Click on the OK button to execute the dialog
85. mental variable SPROJ ECT NAME is used to reference this directory and is used as a soft path to the design database For the labs used during the term create a directory called designs in home account and use the SDESIGNS environment variable When you sart your major project create a project directory and set a environment variable called SPRO ECT Figure 1 Design Directory Structure ALA bin work src sim bin gt binaries scripts etc work gt design under development src gt source VHDL code sim gt Simulation Force Files The following procedure should be used to setup the files directories to complete this course 2 2 Moving around the system 2 2 1 cd Change Directory The cd command is used to move e Toa subdirectory type cd directory e Toanother users directory type cd usa name e Toyour main directory type cd Designing ASICs with Mentor Graphics Tools 2 1 Copyright 2000 Mentor Graphics 11 10 01 10 48 am Chapter 2 Using as little UNIX as possible e Back one directory level type cd e Toa lower level directory type cd directory 2 2 2 pwd Print Working Directory The pwd command is used to tell you where you are located on the system Simply type pwd and it will echo something like users u4 user_name Working with your directories and files 2 2 3 Is LiSt The ls command is used to list out all of your files and directories Flags used for th
86. multiple objects selected Design Architect should rotate through the selected objects allowing you to modify the property on each occurrence 7 2 5 Adding Input and Output Ports Go tothe ADK Library palette and use the SDL menu to select the portin or portout symbol Make sure that you give each port a unique name 7 2 6 Adding Power and Ground Symbols If you desire to explicitly place power and ground symbols you must use the symbols in the SDL menu from the ADK Library palette These have the proper properties to drive the layout and simulation tools with the other models 7 6 Designing ASI Cs with Mentor Graphics Tools 12 14 01 1 08 pm Copyright 2000 Mentor Graphics Creati ng a Schematic 7 2 7 Creating Comment Objects on a Schematic Sheet You can add comment text and graphics directly to a sheet in the Schematic Editor To create graphical comment objects on a schematic sheet perform the following steps 1 View the schematic_draw palette by clicking on the DRAW common command button in the schematic palette menu The schematic_draw palette appears 2 Click on any of the icons in the palette menu to create a graphical object To create a comment text object perform the following steps 3 Choose the following menu path from the Add popup menu Draw gt Text The ADD TE prompt bar appears 4 Enter your comment text in the Text entry box 5 Click on the At Location button A ghost image of your c
87. n 10 7 1 DRC of your cell You need torun a DRC of your cell to verify that you have not violated any design rules with the placement of your devices or routes This is most easily done from the ADK Edit menu via the DRC gt Check item When you select this and click OK Designing ASICs with Mentor Graphics Tools 10 5 Copyright 2000 Mentor Graphics 12 14 01 1 07 pm Chapter 10 Schematic Driven Layout using IC Station on the prompt bar a complete DRC of your entire cell is performed and the results presented in the prompt bar at the bottom of your screen The first error if any can be shown by selecting DRC gt First in the ADK Edit palette Then rest can be viewed by dicking on Next As you are checking you can fix errors and continue showi ng the next one as long as you d like Keep in mind that errors in nearby structures might be fixed with one change however so it is wise to rerun the DRC after every few fixes 10 7 2 LVS of your cell In addition to verifying the design rules with DRC you also will want to verify that your layout matches your schematic You want to verify that all components were placed and that you have not shorted anything together or left things unwired This is easy to do with LVS a First dose your logic using Logic gt Close from the ADK Edit menu b Then from the ADK Edit menu dick on LVS which will bring up the LVS dialog box You need to enter the viewpoint to use for LVS You should use
88. n click on it If the name of the component symbol you want is not the default name perform the following steps a Click on the Explore Contents Navigator button The list box displays the contents of the component b Click on the name of the component symbol you want Designing ASICs with Mentor Graphics Tools 7 3 Copyright 2000 Mentor Graphics 12 14 01 1 08 pm Chapter 7 Creating a Schematic Click the OK button to execute the dialog box The ADD IN prompt bar appears and the mouse pointer becomes a location cursor Move the cursor into the Schematic Editor window A ghost image of the symbol moves with your mouse pointer Move the ghost image to the desired location and click the Select mouse button to instantiate the symbol 7 2 2 4 Using the Active Symbol Window to Place a Component Sym bol The active symbol is the symbol that the Active Symbol window displays To place a symbol that is in this window perform the following steps 1 7 4 Choose Active Symbol menu item from the nstance popup menu The PLA AC S prompt bar appears Move the mouse pointer inside the Schematic sheet window and click the Select mouse button to place the symbol in the desired location Designing ASICs with Mentor Graphics Tools 12 14 01 1 08 pm Copyright 2000 Mentor Graphics Creati ng a Schematic 7 2 3 Drawing a Net Bus To draw a net perform the following steps 1 8 Display the Schematic palette menu b
89. ng a design for the ADK using the Leonardo synthesis tool Step 1 Invoke Leonardo leonardo Step 2 Set some ADK specific variables You should set the following variables in Leonardo to help routing in IC station avoiding timing DRC problems and creating a tighter integration with IC station M odelSim set vhdl_write_component_package FALSE set vhdl_write_use_packages library ieee adk use ieee std logic 1164 all use adk all set edifout power ground style is net TRUE set max fanout load 14 set force user load values You can set these variables globally for all users of the L eonardo software tree by adding the previous variable settings to the E XE M PLAR data exemplar ini file Step 3 Load the technology library Technology FlowTab 1 Select the desired ADK library from the ASIC 5 ADK library list in the Technology F lowTab 2 Ignore the process variables in the Technology F lowTab Although the Technology F LowTab displays the PVT derating factors they have no affect on the timing values in the library FYI The slow process corner uses a temperature of 80 degrees C a voltage of 4 5 volts and a process number of 3 sigmas The fast process corner uses a temperature of 0 degrees C a voltage of 5 5 volts and a process number of 3 sigmas The typical process corner uses a temperature of 27 degrees C a voltage Designing ASI Cs with Mentor Graphics Tools 41 Copyright 2000 Mentor Graphics 11
90. nt setup on your schematic for documentation purposes To do this select Show under the Commands section A ghost image of some text will appear on your schematic window and you can click to place this anywhere on your schematic It will not be automatically updated when you change Designing ASICs with Mentor Graphics Tools 6 11 Copyright 2000 Mentor Graphics 12 14 01 11 28 am Chapter 6 Using the DA IC Flow selections so you will have to remove and replace it if you made changes to the setup 6 4 2 6 Extracting the Netlist To extract the netlist for simulation you select Write under Netlist on the simulation palette This will invoke EldoNet and write a netlist for your design You can view and or edit the netlist by selecting Edit in the same Netlist section of the palette 6 4 2 7 Adding Voltage Sources and Additional Netlist Items Assuming that you use the Vdd symbol from the libraries menu you need to tell the simulator what voltage this will be You might have other nodes in your circuit that are voltage or current sources also If you did not implicitly place a source on them you can use the Edit option under Netlist to add these lines to your netlist Optionally you could create a separate file with such directives and use an Include file under the Setup Other section of the simulation palette menu For the case of Vdd you would add V1 VDD 05 to indicate that this is a voltage source conn
91. o move the signal to NOTE You can also define the order that signals are added by using explicitly wave commands when you set up the Wave window For example add wave clock add wave clear add wave enable add wave count e Toremovea signal select the signal in the wave window it will be high lighted with a box and select the Edit gt Cut menu item in the Wave Window 3 5 Applying stimulus 3 5 1 Using Force Files interactive A signal changes value either by the user applying stimulus to the signal force command or by the simulator applying stimulus due to design functionality The following list shows examples of how to apply forces to the design Typically you only apply forces to signals defined in the top level entity Designing ASICs with Mentor Graphics Tools 3 3 Copyright 2000 Mentor Graphics 11 10 01 10 48 am Chapter 3 Simulating HDL in ModdSim e Toapply stimulus to a signal force signal_name value time If you do not specify a time then ModelSim applies the force at the current simulation time Some examples force reset 1 force reset 0 100 e Tospecify a clock signal force clock time_value_pair time_value_pair repeat period There must be an even number of time_value_pair combinations For example force clk 0 O 1 25 repeat 50 50nS clock with 50 duty force clk O 10 1 20 repeat 50 50 nS clock with 10nS pulse 3 5 2 Force File Example 1 initialize design force clear 1 0 force
92. oint If you are not running adk daic you need to run SADK bin adk_dve s t technology gt design This command will setup viewpoints for QuickSim in addition to viewpoints for IC layout and analog simulation You should not run this if you are using adk ic Using adk_daic will create all the viewpoints you need if you follow the instructions in Chapter 6 Specify the technology you wish to use ami05 ami12 or ami15 tsmc035 If you do not specify a technology ami05 is assumed 14 2 Invoking QuickSim Il You can invoke QuickSim II by issuing the adk_quicksim or adk qs command from an operating system shell SimView is automatically invoked when you invoke QuickSim II Do not attempt to invoke SimView independently The following sections detail these two invocation methods Designing ASICs with Mentor Graphics Tools 14 1 Copyright 2000 Mentor Graphics 12 14 01 11 02 am Chapter 14 Simulating the Design Using QuickSim To invoke QuickSim II from a shell window enter the following command adk quicksim design ami 05 ami 12 tsmc035 You must use an existing Design Viewpoint and add any additional switches to specify a variety of modes and setup conditions When you invoke the QuickSim ll simulator it displays a default window called the Session window The Session window which is managed by SimView controls the interactions between the data in the Session s sub windows You can open up the following windows inside a Sess
93. ology you wish to use by clicking and holding a down the mouse button on the arrow to the right of the Edit Simulation text on the palette menu Annotation Merge Toggle DCOP Show Hide 6 4 2 Preparing for Simulation You need to prepare a few items before you can simulate These include defining the ground 0 nodein CO your circuit as well as the type of simulation Mod Sel parameters for simulation and netlisting poe 6 10 Designing ASICs with Mentor Graphics Tools 12 14 01 11 28 am Copyright 2000 Mentor Graphics Simulating your Design 6 4 2 1 Setting Node 0 SPICE and Eldo requires that you have defined node 0 as the ground in your circuit By default this is done but the name is ground which is not used in the ADK logic or SDL symbols Use the pull down menu Setup gt Simulation gt Setup Netlister to display a dialog box where you can specify the names of your ground nets Specify GND and any other names you wish tied to ground 0 in your circuit GND is what the ADK cells and devices use so be sure to enter at least that Multiple entries should be separated with commas 6 4 2 2 Setup Analysis Parameters You may set up the type s of analysis to run with the Analysis item under Setup Sim section on the simulation palette menu You will be presented with a dialog box where you can select the items you wish to use and then set the necessary parameters for them You are setting up a SPIC
94. omment text moves when you move the mouse 6 Movethe ghost image to the location you want to place the text 7 Click on the Select mouse button Design Architect places the text comment on your schematic sheet 7 2 8 Checking a Schematic for Errors You must check your schematic sheet before you can use it You can check your design at various points in the development cycle In Design Architect you can perform checks of symbols schematics and entire designs You can direct Design Architect to enforce optional design rules in addition to the required ones Your design must conform to certain design rules before you can successfully use downstream tools to either analyze or simulate it If your design violates a required design rule a downstream tool may issue a warning upon invocation therefore it is important that you first execute the design checks to ensure that the results of analysis and simulation are both valid and accurate To check your design choose the following pulldown menu path from the menu bar Check gt Sheet 7 2 9 Saving the Schematic To save the schematic choose the following menu path from the menu bar File gt Save Sheet Design Architect saves the schematic sheet Designing ASICs with Mentor Graphics Tools 7 7 Copyright 2000 Mentor Graphics 12 14 01 1 08 pm Chapter 7 Creating a Schematic 7 3 Creating a Symbol from a Schematic For student use you should not manually create symbols It is g
95. ool Configurations The following configurations have been tested and are suggested setups Other configurations may work but may be unsupported in the future It is strongly suggested that CF low tools be installed These are the latest IC tools and contain the most recent versions of IC Station DA IC and Eldonet All of the most recent features in the ADK can be used with these tools and adk daic makes your SDL flow much simpler It is only available with the CF lows installation however 1 1 2 1 SDL only flow using ICFlow 2001 2 or Later This configuration is best if you do not need to use any standard cells and also do not plan to use QuickSim You will be able to do all of your schematic capture and simulation from within adk daic and will do your layouts with adk ic e ICFlow tools installed and MGC HOME set to the install directory e ANACAD tools eldo installed and the anacad environment properly set as per M entor s installation instructions e LeaveLEGACY MGC TOOLS unset in your environment e Useadk daic and adk ic as appropriate 1 1 2 2 SDL only flow using C x or D x tools This configuration is best when you do not have the CF low 2001 x tools installed anywhere on your system You will use adk_da for schematic entry adk_dve for viewpoint generation adk_as for Accusim adk_qs for Quicksim and adk_ic for layout e MGC Tools installed and MGC HOME set to the install directory e Leave LEGACY MGC TOOLS unset in
96. opyright 2000 Mentor Graphics 12 10 01 4 10 pm Chapter 11 Generating Padframes may be different types of pads available You can only use one set of technology pads and it must agree with the technology of your design Add the pads to your schematic and wire them up to your core logic Change the property PINXX shift F 7 to replace the XX with the pin number on the package you wish to connect this signal to in the final design Be sure to add power VDD GND pads as necessary Any pads not in your schematic will not appear in your completed padframe Check and save your schematic Note For all processes the corner pads will be automatically instantiated for you For ami12 this includes the power corner pads which power the padframe You still must instantiate core logic power and ground however Step 4 Use adk_dve to create proper viewpoints for the top level design Run adk_dve design like you did for other schematics This will create the necessary viewpoints for layout and verification 11 2 Padframe Layout In IC station adk ic you can create a new cell for the top level logic and the padframe that will be generated based on your schematic Note The automatic padframe generator will only generate 40 pin tiny chip padframes at this time 1 Create a new layout cell for the whole chip Enter the following in the new cell form allowing all else to default Cell Name SPROJECT layout design name Attach Library SAD
97. pings of inputs to the AND gates An A021 gate has a two input AND gate and a one input AND gate a wire all feedi ng into a two input OR gate An AO221 would have two two input AND gates and a wire feeding into a three input OR gate AOI Gates This library contains all of the schematic models for the AND OR INVERT gates The numbers following the name indicate the groupings of inputs to the AND gates An AO121 gate has a two input AND gate and a one input AND gate a wire all feeding into a two input NOR gate An AO01221 would have two two input AND gates and a wire feeding into a three input Designing ASI Cs with Mentor Graphics Tools A 1 Copyright 2000 Mentor Graphics 12 14 01 11 28 am Chapter ADK Menus and Commands NOR gate OAl Gates This library contains all of the schematic models for the OR AND INVERT gates The numbers following the name indicate the groupings of inputs to the OR gates An OAI21 gate has a two input OR gate and a one input OR gate a wire all feeding into a two input NAND gate An OAI221 would have two two input OR gates and a wire feedi ng into a three input NAND gate Flip Flops Latches This library contains all of the schematic models for the d type flip flops d type latches and scan d type flip flops Ther and s letters following the cell name indicate the presence of any asynchronous reset and or set inputs respectively Pads This library contains all of the schematic models for the pads in e
98. ption from the Report gt Timing Violations pull down menu These options let you select a specific path by indicating To and From pins or you can analyze the entire design by dicking on the OK button To determine the longest or shortest delay paths in a design select the Longest Delay Paths or Shortest Delay Paths option from the Report gt Delay Paths pull down menu Again you can either specify a particular path or analyze the entire design Clock information such as clock tree details gating locations merged clock locations clock skew statistics clock latency statistics clock pulse width statistics and asynchronous domain crossings can be determined by selecting the desired option from the Report gt Clock Information pull down menu A more in depth discussion of timing analysis can be found in the Analyzing a Design chapter of the SST Velocity User s Manual Designing ASICs with Mentor Graphics Tools 15 3 Copyright 2000 Mentor Graphics 12 14 01 11 02 am Chapter 15 Performi ng Static Timing Analysis 154 Designing ASI Cs with Mentor Graphics Tools 12 14 01 11 02 am Copyright 2000 Mentor Graphics appendix A ADK Menus and Commands The ADK provides some enhanced functionality over the standard Mentor tools There are several new menus palettes and commands that have been created to ease the use of the tools for ADK designs You will only see these enhancements if you use the ADK version of the tools
99. r click on Extract in the ADK Edit palette menu In the form that appears select the Netlist button enter the filnename for the netlist and enter the ground node name as GND OK the form to generate the netlist An incongruence exists between the format of the netlist that IC Station provides and the format expected by Mach TA Specifically the netlist generated by IC Station is defined as a subcircuit while Mach TA expects a flat file with no defined subcircuits To correct this an awk script ADK bin mta_prep awk has been provided in the kit to reformat the netlist To use the script invoke cat design sp nawk f SADK bin mta prep awk sed s 4 g 5 design mta sp The second pipe though sed may not be necessary as that it only removes line wrapping in netlist files with an excessive number of ports defined in the subcircuit 13 1 1 Creating Test Vectors To apply stimulus to a design netlist Mach TA requires a test vector tv filein Lsim format This can be acquired from early M odelsim test results be either using the VTRAN conversion utility www sourcelii com or writing a customized script to convert the simulation results 13 1 2 Creating a Command File A command dofile for Mach TA makes it very convenient to automate test vector analysis Such a dofile is automatically generated when using the mta_layout_prep script for test vector creation An example script would look like ac plot v clear v c
100. r rail in metal 1 with the height of a standard cell Also creates proper port and net properties for the rails These rails are short but can be stretched to and desired width for your cell Place an n well contact creates and places an n well contact on the standard cell power rails Place a p well contact creates and places p well contact on the standard cell power rails Place an fp1 layer For standard cells you need to specify an fp1 floor plan layer This command automatically generates and places one to the extent of the cell Place a poly path of width 2 minimum width Prompts you to place a poly path Place a metal1 path of width 3 minimum width Prompts you to place a metal1 path Move unconstrained Moves the selected object s Lumped mask extraction for AMI 0 5 This command scripts the extraction toa specific location that probably does not exist at your site Modify this command if you wish to use it Lumped mask extraction for AMI 1 2 This command scripts the extraction toa specific location that probably does not exist at your site Modify this command if you wish to use it Add metal1 blockages to entire cell This command will place a metal1 blockage on top of all metal1 shapes in your cell This is useful for autorouting with hierarchy Designing ASICs with Mentor Graphics Tools A 5 Copyright 2000 Mentor Graphics 12 14 01 11 28 am Chapter ADK Menus and Commands Table A 1
101. rary versions and scripts available on the MGC website Currently the kit has been verified with the following versions of the tools e Falcon Tools C 4 IC Station v8 7 5 5 or higher recommended Or ICFlow 2001 2 IC Station v8 9 3 1 e Leonardo Spectrum 1999 1 and higher current 2001 1d e ModelSim 5 3 and higher current 5 5e Designing ASI Cs with Mentor Graphics Tools 1 1 Copyright 2000 Mentor Graphics 12 10 01 4 03 pm Chapter 1 Installing the ADK 1 1 Setting up the Mentor ADK Environment You will need to set up the following environment variables based upon your operating system type version and where you installed each of the components H ere is an example of a typical setup 1 1 1 Setting Your Environment c shell example HHEH EEE HH HEE HE HEH HEH EH HEH FF Setup Mentor Software HEHEHE EH HEE HE HE EEE HEH HH HEH FF MGC_HOME is set to the root of the MGC tree setenv MGC HOME idea_tree idea_C 4 F ss5 MODEL HOME is set to the root of the ModelTech tree setenv MODEL HOME mti 5 3e modeltech EXEMPLAR is set to the root of the Exemplar tree setenv EXEMPLAR exemplar spectrum_99 1h ss5 Add everything to the path according to your hardware platform type Also ensure MODEL_HOME comes before MGC_HOME set path SEXEMPLAR bin SEXEMPLAR bin Sun085 SMODEL_HOME sunos5 SMGC HOME bin path Set your license file variables appropriately setenv MGLS LICENSE
102. right 2000 Mentor Graphics 12 10 01 4 10 pm Chapter 9 Automated IC Layout using IC Station 9 2 Invoke IC Station ThelCgraph tool is the main entry point into the IC Station environment Before running the tool however we need to set the SMGC WD environment variable to the directory where the design resides This can be performed with the Unix alias macro swd ToinvokelC Station from the unix command prompt simply type adk ic This is a special version of IC Station that has been enhanced with special features for the ADK 9 3 Autoplacement and Routing Autoplacement and routing is the process of automatically generating a layout from a previously existing schematic or design To increase our confidence in the correctness of a generated result we setup Cgraph the layout editor to carefully check every action taken by ICblocks the autoplacement router We will now describe Cblocks use to automatically place and route a layout These steps will walk you through a relatively simple direct path to an automatically placed and routed layout Step 1 Create an IC cell Select CREATE from the menu on the right hand side of the screen A form titled CREATE CELL will appear Enter the following then click OK Cell Name SPROJECT layout design name Attach Library SADK technology ic process cell lib Process SADK technology ic process file Rules File SADK technology ic process rules Angle Mode 45 Log
103. ry palette menu by performing the following steps Bi Brdr a Click on Library in the palette menu b Click on Standard Cells in the new palette menu The ADK Libraries palette appears which displays classes of components in the ADK library as shown to the right 2 Movethe mouse pointer over the type of gate you wish to place such as Basic Logic Gates 6 2 Designing ASI Cs with Mentor Graphics Tools 12 14 01 11 28 am Copyright 2000 Mentor Graphics Creati ng a Schematic AND OR Inverters etc The items under the General heading are things like ports sheet borders and power supplies 3 A new palette will appear and you can then click on the specific component you wish to instantiate 1e ic library schematic Standard Cells Transistors 4 Movethe mouse pointer in the Schematic sheet window and click to place the ghost image of the component to the position that you desire 6 2 2 2 Using the ADK_Library Palette to iia SUU Place an SDL Symbol Resistors 1 Activate the ADK_Library palette menu by hrpoly performing the following steps Capacitors a Click on Library in the palette menu b Click on Standard Cells in the new palette menu The ADK Libraries palette appears which displays classes of components in the ADK library as shown to the right Cap General In Out Bi Brdr YDD GND SOUrCeS F AC D pe H EXP iv lj PAT V il PULSE il r
104. simulation as possible Although the automatic tools performed the layout in Correct by Construction mode it is always good to verify the layout for correctness in terms of both layout design rules and connectivity to insure consistency between the varous tools used This establishes a system of checks and balances that increases the overall confidencein the design First check for layout design rule errors using I Crules then verify the layout by double checking it against the transistor level representation of the logic diagram Step 1 Check Layout Design Rules From the main Cstation palette select Crules then select Check from the ICrules palette A prompt box will appear at the lower left of the screen Click on OK to proceed with the check Optionally if you are using the ADK Edit menu you can use Drc gt Check Step 2 Fix any Design Rule Errors When the check is complete design rule errors which exist in the layout will be reported in the message bar at the bottom of the Cstation window The first one can be shown by selecting First in the palette or DRC gt First in the ADK Edit palette Then rest can be viewed by clicking on Next As an example one or more design rule errors of the type DRC4 4 p space P select space 2L may exist The design rule checker is complaining about p select mask layers being too close in adjacent cells A similar error may occur with n select masks Step 3 Verify connectivity b
105. simulator optionally revise or apply more stimulus to the design and start the cycle over When the design functions correctly you can save the stimulus and simulation results directly with the design Thetypical strategy for simulation is an iterative process that will be utilized during two steps of the overall design process e verify functionality of HDL code prior to synthesis e verify functionality once the design is placed and routed Although the focus of each phase is different the tasks that you perform within the simulator are very similar The following procedure describes how to simulate an HDL design 3 1 Compiling HDL code 1 Ina UNIX shell change to the directory containing your HDL source code For example cd DESIGNS src 2 If you have not already done so map the Logical HDL library to a physical directory vlib phy lib path vmap logical lib phy lib path vlib SDESIGNS hd1 work vmap work SDESIGNS hdl work In this example all files compiled into the work library would be saved in the DESIGNS hdl work directory This information is saved in the modelsim ini file 3 RuntheHDL compiler by typing the following on the UNIX command line vcom filename vhd for VHDL vlog filename v for Verilog To compile a VHDL file into a predefined library vcom work logical_lib VHDL_source Designing ASICs with Mentor Graphics Tools 3 1 Copyright 2000 Mentor Graphics 11 10 01 10 48 am Chapter 3 Simul
106. sing a Monitor Window sasssa 00 c eee ee ees 14 4 14 4 Generating Stimulus 1 5 naaa ENG Chae ds anna eee ieee Rk be Sees 14 5 14 4 1 Creating a Waveform Using Palette Icons 14 6 14 4 2 Creating a Waveform Using the Waveform Editor 14 7 4 Designing ASICs with Mentor Graphics Tools 12 14 01 1 12 pm Copyright 1999 Mentor Graphics 14 4 3 Creating a Force File 4X Cebu dae GG Pe eee Cees ee ee es 14 7 14 4 3 1 Saving Waveform Stimulus in a Forcefile 14 8 14 4 3 2 Loading and Viewing Waveform Stimulus from a Forcefile 14 9 14 5 Running the Simulator 0 54 vce Cees bp eek ee WERE oe eee eee 14 10 14 6 Changing the Timing Mode in the Kernel 0 0 2005 14 10 14 7 Resetting the Simulator h BARA GAEL DAGA LAB IKAA ADDY AnG 14 10 14 8 Using QuickSim to Debug your design aa 14 11 14 8 1 Using Breakpoints xa AN vee Siew Gs KAB eau oy 14 11 14 8 2 Back Tracing X States 0 0 00 0 14 12 14 8 3 Design Changes ode Jea samaan nka BUKAKA KANA ce age eee es 14 12 14 8 4 Viewing a Simulation Timing Report 2005 14 12 14 8 5 Using Cursors to Get Waveform Information 14 13 Chapter 15 Performing Static Timing Analysis 15 1 15 1 Setting Up and Invoking SST Velocity cee 15 1 15 2 Setting TIMING Constraints cxcccedscveseacdds LA KGKEKULA AALAGA 15 1 15 2 1 Defining Clocks ama a KAN
107. smallest result area or the fastest result delay e Hierarchy Choose preserve to keep the design hierarchy in the synthesized design aids in debugging or flatten to merge the design into a single level of hierarchy allows optimization across hierarchical boundaries e Add I O Ports MAKE SURE THIS OPTION IS NOT SELECTED The cur rent release of the ADK library for Leonardo does NOT indude support for automatic O insertion You will need to manually add 1O using Design Archi tect e Run timing optimization This option forces Leonardo to make an addi tional optimization pass to help critical paths meet timing specifications Leonardo optimizes the original result of synthesis reading in the design so 4 2 Designing ASICs with Mentor Graphics Tools 11 10 01 12 47 pm Copyright 2000 Mentor Graphics Synthesizing HDL Using Spectrum Command Line Mode running multiple optimization passes will not produce better results The first optimization iteration is as good as it gets Step 6 Determine the Size and Speed of the optimized design 1 Determine the gate count Report FlowTab Report Area PowerTab You should examine the area report to examine the size of your design AND that leonardo used the correct number of memory resources flip flops 2 Determine the critical path Report FlowTab Report Dday PowerTab Step 7 Save the Design Output FlowTab Specify a filename usually the name of the top level entity You shoul
108. ssumed that the administrator responsible for installing the development environment kit has updated the macros or the directory structure the library is being created in Fields in the documentation below such as process mnemonic and process are dependent on he macro updates 9 1 Creating Design Viewpoints Before the actual layout process begins the design needs to be prepared for use with helayout tools In the same way QuickSim viewpoints were created for the part two more are required for layout creation and verification The viewpoints are created for helCTrace and CBlocks tools specifcally This process is automated by calling the script adk dve from your design proj ect directory For ADK parts run SADK bin adk dve lt design gt he script creates the following viewpoints for IC station 1 Viewpoint Creation for the Cblocks place and route tool A viewpoint called sdl is created where primitives called element and comp are added A string parameter named lambda is also added and assigned the value of lambda for the process specified Viewpoint for CTrace The viewpoint called LVS is created and the primitive called element is appended It does not matter what the value or the type the primitive is The element primitive in CTrace serves the same function as the model primitive for QuickSim namely that of identifying the leaf parts of the design Designing ASICs with Mentor Graphics Tools 9 1 Copy
109. t gt bcd out Initialize all input signals clk lt 0 rst lt 1 load lt 0 enable lt 1 up_down lt 1 data lt 0101 Designing ASICs with Mentor Graphics Tools 3 5 Copyright 2000 Mentor Graphics 11 10 01 10 48 am Chapter 3 Simulating HDL in ModdSim 3 6 Running the Simulator Specify 10 ns clock clock process clk begin clk lt NOT clk after 5 ns end process Specify Test Vectors stim process begin rst lt 0 after 15 ns enable lt 0 after 63 ns enable lt 1 after 87 ns load lt 1 after 163 ns load lt 0 after 187 ns up_down lt 0 after 203 ns end process END test Torun the simulator for a specified amount of time use the following command For example to run the simulator for 1000 ns enter VSIM gt run time VSIM gt run 1000 If you just type run then the simulator runs for 100 nS 3 6 11 10 01 10 48 am Designing ASICs with Mentor Graphics Tools Copyright 2000 Mentor Graphics chapter 4 Synthesizing VHDL or Verilog The following section describes how to synthesize the HDL code that you created compiled and simulated in the earlier chapters As usual this chapter provides an overview of the flow and does not go into all the options available 4 1 Synthesizing HDL Using Leonardo GUI Mode The following list describes the basics of optimizi
110. t resides in the ADK library 1 7 2 2 2 Place an SDL Symbol 1 7 2 Movethe mouse pointer in the Schematic sheet Activate the ADK_Library palette menu by performing the following steps Choose the Libraries pulldown menu from the menu bar and press and hold the Select mouse button Slide the mouse pointer down to ADK Libraries in the Libraries pulldown menu The ADK_Libraries palette appears which displays classes of components in the ADK library Inverters and Buffers as shown to the right Basic Logic Gates AO Gates Movethe mouse pointer over the type of gate you AOI Gates wish to place such as Basic Logic Gaets AND OR Inverters etc DAI Gates Anew palette will appear and you can then click Hip Flops Latches on the specific component you wish to instantiate Pads window and click to place the ghost image of the SDL Parts component to the position that you desire Activate the ADK_Library palette menu by performing the following steps Choose the Libraries pulldown menu from the menu bar and press and hold the Select mouse button Slide the mouse pointer down to ADK Libraries in the Libraries pulldown menu The ADK_Libraries palette appears which displays classes of components in the ADK library as shown to the right on the previous page Designing ASICs with Mentor Graphics Tools 12 14 01 1 08 pm Copyright 2000 Mentor Graphics 2 7 2 2 3 Using the Dialog Navigator to Pl
111. te menu Designing ASICs with Mentor Graphics Tools 7 5 Copyright 2000 Mentor Graphics 12 14 01 1 08 pm Chapter 7 Creating a Schematic 2 Place your bus by clicking on the initial point and on each bend in the bus you desire 3 Doubleclick at the end of the bus 4 Give the bus a name It should be of the form bus 15 0 where the numbers represent the bits in the bus 5 Now add wires from your components to the bus To connect a wire to the bus dick on the bus or double click if the wire should terminate on the bus 6 A bus ripper will appear and you will be prompted to enter the bit number for this net You can change these later if you change your mind If the Check Sheet function reports unconnected pins warnings you can add a Class property with a value of dangle to inform DA that this pin is supposed to dangle 7 Select pin 8 Add Class property with value of dangle 7 2 4 Annotating Properties Property annotation is the process of adding design information in the form of properties to both schematics and symbols To annotate properties on an instance follow these steps 1 Setup Selection Filter 2 Select the Object to which you want to add a property 3 Select the Properties gt Add 5 Single Item menu in the Schematic Popup menu to add a new property to the symbol 4 Select the Properties gt Modify menu item in the Schematic Popup menu to change an existing property on a symbol If you have
112. ted layout When zoomed out small overflows may not be viewable but may still exist To select all overflows in the design type check over In the form window that appears select All and OK theform Next from the Place and Route palette menu select Overflw If the response An object of type Overflow must be selected appears in the status block there are no overflows to route Otherwise the overflows should be routed Step 7 Save the IC cell Save the layout by selecting File gt Cell gt Save Cell gt Current Context You may save the layout and exit the Cgraph session at any time To reload the layout later choose open from the IC staton palette If you wish to make changes to the cell you must also select File gt Cell gt Reserve Cell gt Current Context 9 4 Designing ASICs with Mentor Graphics Tools 12 10 01 4 10 pm Copyright 2000 Mentor Graphics Verifyi ng Project L ayout 9 4 Verifying Project Layout For layout verification the physical layout data is interpreted in at least two important ways e The first determines if the the geometries within the layout meet a set of physical design rules established by the IC foundry This helps insure a more manufactur able and reliable chip e The second determines whether the layout precisely conforms to the schematic developed during the front end design phase This of course helps guarantee that the actual fabricated circuit will perform as much like the front end
113. that you want SST Velocity to ignore during timing analysis To eliminate a false path from consideration during timing analysis designate the path as a false path by indicating the from and to points or through points on the path These points can be listed in the False Paths option in the Specify pull down menu 15 2 Designing ASICs with Mentor Graphics Tools 12 14 01 11 02 am Copyright 2000 Mentor Graphics Timing Analysis 15 2 5 Defining Constant Levels It may be necessary in certain designs to define pins as being held at a constant logic level Such paths may include set reset or enable pins that would put the design in an undesired state for timing analysis To define a constant level on a pin choose the Assign Constant Level option from the Specify pull down menu 15 2 6 Back Annotating from a SDF File If you intend to back annotate a design from a post layout SDF file you must first load the file by specifying the desired SDF file in the FilesOpen5Back Annotation screen This will replace the library delay values with those calculated based on the actual physical layout of the design 15 3 Timing Analysis Now that the timing constraints of your design have been described you can perform several different types of timing analysis To perform a slack analysis you can select either the Setup Recovery Constraints Hold Removal Constraints or Clock Pulse Widths o
114. the LVS viewpoint for LVS c Now click on Setup Lvs and change the ground name to ground and OK the dialog box d OK theLVS dialog box torun LVS e Toview the results use Results gt LVS next to the LVS item on the ADK Edit menu If you see a checkmark a smiley face and Correct then you are good If not read the report to see what types of problems you might have If you have many errors you can go to the Ctrace M menu off the main IC Station menu for many more LVS options At this point you should have verified that your cell has no DRC errors and matches your schematic The final step in verification is extraction and simulation of your design 10 6 Designing ASI Cs with Mentor Graphics Tools 12 14 01 1 07 pm Copyright 2000 Mentor Graphics chapter 11 Generating Padframes The ADK has a facility for automatically generating a TinyChip padframe for fabrication through MOSIS If you wish to automatically generate and route to your padframe you need to prepare your design data in a particular manner to facilitate this feature It is important to note that while you can use both analog and digital cdls in the same design you must not mix then on thesamerow or column of your padframe If you do the pads will short each other out You need to have all of a row or column only analog or only digital 11 1 Top Level Layout Preparation To begin you need a top level part containing the design inside a padframe
115. to place unplaced instances and ports Inst nstantiates all selected instances into your cell or all unplaced instances should you not have any schematic instances selected Autol nst will automatically instantiate all unplaced instances into your cell Port place selected ports or all ports if none currently selected DE dit This will display a submenu that will give you options on editing placed devices You will have options to move MOS pins split and join MOS devices define the folding for MOS devices and modify capacitor and resistor properties as well Clean This will clean up your schematic should a placement abort due to an error If your schematic updating seems to be stuck try to clean it up The section on routing has many useful functions for routing your devices and cleaning up your layout Route This is a menu with options to help you create overflows and manage your routing database SsNet This function will select all nets that are shorted or of the same net to the currently selected object MkPort This will make the selected object a port You will be prompted for the type and name of the port SsPort The nets connected to the selected port will be selected for you ResAll This function will restructure all nets in your design and update the overflows to display the updated database Useful after moving many objects or if you see stray overflows in your cell ResSel Restructure selected net s only AutoR A
116. tool to perform slack analysis find longest or shortest delay paths or examine dock statistics The ADK also supports post layout back annotation of designs for static timing analysis 15 1 Setting Up and Invoking SST Velocity Before working with a VHDL design you must define a velocity map file in your local directory that will map the logical names of design units and standard packages to their physical locations The velocity map file must include the locations of all design subunit files which are referenced in the top level file For a description of creating a velocity map file and examples refer tothe VHDL section of the Setting Upa Design chapter in the SST Velocity User s Manual After creating the velocity map file VHDL users only you must then set the target technology In the pull down menu File choose the Set Technology option Choose your desired technology from the list of available libraries When you have chosen a target technology you will now be able to choose File gt Open gt Design Navigate to your top level design and click on the OK button 15 2 Setting Timing Constraints SST Velocity requires that you set the following constraints before executing timing analysis Setting constraints is the most important part of timing analysis If you set the constraints too aggressively SST Velocity will will report inaccurate timing violations If you set constraints that are too relaxed the res
117. ttom of the Session window 14 3 2 2 Adding a Signal to the Trace Window To add a signal to the Trace window perform the following steps 1 Select a net or bus in the Schematic View window or a VHDL description in a VHDL Description window by moving the mouse pointer over it and clicking the Select mouse button SimView highlights the object that you selected 2 Choose the following menu path from the menu bar Add gt Traces The Add Traces dialog box appears 3 Click on the OK button to execute the dialog box The signal that is on the selected pin net or bus appears in the Trace window 14 3 2 3 Deleting a Signal from the Trace Window To delete a signal from the Trace window perform the following steps 1 Select one or more signals in the Trace window by moving the mouse pointer over each signal label and clicking the Select mouse button Designing ASICs with Mentor Graphics Tools 14 3 Copyright 2000 Mentor Graphics 12 14 01 11 02 am Chapter 14 Simulating the Design Using QuickSim 2 Press the Menu right mouse button and choose the following menu path from the popup menu Delete 5 Selected 14 3 3 Using a List Window The List window contains a listing of signal bus and expression values This window enables you to view signal activity in tabular form The following sections contain procedures that you perform to open a List window and both add and delete signals from it Opening the List Window The
118. tyle and position to show signal states and strengths A Trace window displays signal names along its left edge A row of tic marks that are located to the right of each signal name helps you to identify the signal s logic level The following list describes the logic levels and their corresponding positions 0 Below the tic marks 14 2 Designing ASICs with Mentor Graphics Tools 12 14 01 11 02 am Copyright 2000 Mentor Graphics Setti ng up the SimView Windows L Above the tic marks X Through the tic marks The following list describes the drive strengths and their default appearances S Solid or light blue line R Dashed or medium blue line Z Dotted or green line I Bold solid or yellow line The following sections contain procedures that you perform to open a Trace window and both add and delete signals from it 14 3 2 1 Opening a Trace Window The Trace window displays waveforms of signal activity To open a Trace window perform the following steps 1 Open the Schematic View window if it is not already open by performing the Opening the Schematic View Window procedure in this manual 2 Select either a net or bus in the Schematic View window or a VHDL description in a VHDL Description window by moving the mouse pointer over it and clicking the Select mouse button SimView highlights the object that you selected 3 Click on the Trace common command button in the palette menu The Trace window appears along the bo
119. u 9 I SFFM V il SIN V hj GEN V hj 2 Click the component you wish to instantiate You can use the FETs with any technology supported by the ADK These are 4 terminal devices so you will need to wire up the bulk as appropriate for your design The analog components are not available in the AMI 1 2 1 6 technologies If you attempt to use them you will get errors later when you try and instantiate them in your layout You will have to create these components manually in the IC layout tool if you need them and are using the AMI 1 2 1 6 technology The General components may be used with the logic gates as well They are available in all technologies CCCS CCYS YCCS2 CCS4 YEYE VCVS4 The Sources are available for simulation purposes You can place these various sources on Designing ASI Cs with Mentor Graphics Tools 6 3 Copyright 2000 Mentor Graphics 12 14 01 11 28 am Chapter 6 Using the DA IC Flow your schematic and they will generate proper Eldo netlist information when you extract the netlist 3 Movethe mouse pointer in the Schematic sheet window and click to place the ghost image of the component to the position that you desire 6 2 2 3 Using the Dialog Navigator to Place a Component Symbol You perform this procedure if the symbol you want to instantiate is located in a directory of user created component symbols 1 Choose the following menu path from the popup menu Instance 5 Choose Symbol T
120. u will be prompted for a 6 12 Designing ASICs with Mentor Graphics Tools 12 14 01 11 28 am Copyright 2000 Mentor Graphics What to do After Design Architect IC rectangle to draw around the items to add to the plot You can use this command as many times as needed to get all the signals you want viewed c When done select View 5Close Viewer to dose the viewer application If the connection between the viewer and DA IC doesn t work you can probably fix this by telling DA IC which ports to use for communication You do this via the Setup gt Simulation gt Setup Simulation Viewer pull down menu Then dick on the Advanced button and enter the dataport number that was reported when the viewer was last invoked 6 5 What to do After Design Architect IC After creating your design with adk_daic you might want to run another simulator such as QuickSim II If you prefer Accusim then you might want to run that before going to layout or might be ready to go straight to layout at this point To move on to any other tool you will need to create the appropriate viewpoints so that they will work with your data If you ever entered simulation mode in DA IC then you will have created all the viewpoints that are necessary for other tools If you never entered the simulation mode you can do so before leaving DA IC and that will create all your viewpoints You do not have torun the simulator just enter simulation mode You can run adk_qs adk_as
121. u will need to place your instances transistors resistors capacitors ports You can use auto placement features manual placement or a combination of both You will need to have your logic opened to do either so if it is not yet open you should go to the ADK Edit menu and then click on Open to open your logic 10 4 1 AutoPlace instances You can quickly place all of your instances in your schematic into your cell by dicking on Autolnst in the ADK edit menu The positions of the devices will resemble the placement of the schematic instances That is if a transistor is above another one in your schematic it will be in your layout also Once the devices are placed you can move them to fine tune the placement You will see overflows between the pins of the devices that will help you to see the connectivity in your design Use these as guides when moving your devices around If you only want to place some of the components select them in the schematic and then click on Autol nst to instantiate only the selected item s 10 4 2 Manually placing instances If you prefer more control over initial placement of your devices you can place them manually To do this select the instance s that you wish to place in your schematic Then click on Inst in the palette menu A ghost image of each component one at a time will appear in your layout window Click where you want to place this instance and then the next one will appear and you contin
122. ue this procedure until all selected instances are placed Again you will see overflows to help you locate the best placement In addition you will see the current instance highlighted in your schematic Once placed the devices can be moved around your cell as any object 10 5 Placing ports into your layout Before placing the ports you will need to select a port style You do this via the Setup gt SDL pulldown menu One of the options you can select is SDL Port Style You should then select the Process Port button and select the default port from the list This is a minimum sized port on metal2 By default all ports are on metal2 You can change this after placement if you desire Unlike placing instances you must place your ports manually To do this simply Designing ASI Cs with Mentor Graphics Tools 10 3 Copyright 2000 Mentor Graphics 12 14 01 1 07 pm Chapter 10 Schematic Driven Layout using IC Station select the port s you wish to place and click on Port This will prompt you one at a time to place the ports like you did the instances If you wish to place all the ports at this time you can select no ports and then click Port This is a semi automatic mode that will prompt you to place all ports in the design 10 6 Routing your cell Once you have placed your components or at least as many as you Want to you can route the over flows There are many ways to route your design All are manual or semi a
123. ultant design might not meet the timing requirements of the system outside the design being analyzed A more in depth discussion of timing parameters can be found in the Specifying Timing Parameters and Backannotating a Design chapters of the SST Velocity User s Manual Using the Specify Menu For a given level of the design hierarchy the Specify menu enables you to specify various timing constraints for either ports or nets The design must be fully constrained before meaningful results can be obtained To determine whether or not you have specified all timing constraints click on the pull down menu choice Report gt Missing Timing Specfications gt All Designing ASICs with Mentor Graphics Tools 15 1 Copyright 2000 Mentor Graphics 12 14 01 11 02 am Chapter 15 Performi ng Static Timing Analysis 15 2 1 Defining Clocks Clocks define the timing between registers Without clocks defined all registers are assumed unconstrained and all combinational logic between registers will be ignored during timing analysis When you definea clock you have effectively constrained the maximum delay between all registers to one clock period You can describe clocks in SST Velocity using the Specify gt Clock Definitions pull down menu When defining a dock be sure to specify the clock period duty cycle edge positions arrival time variance edge region and slew Setting a Single Clock If your design only has one dock
124. ut design name Process SADK technology ic process file Rules File SADK technology ic process rules Angle Mode 45 Logic Source SPROJECT sdl Logic Source Type EDDM Logic Loading Flat PROJ ECT is your path to the part you created Table 1 in the previous Chapter shows the valid options for the other fields All other options should be left at default values It is very important to change the logic loading to flat Since you are not using a standard cell library for your design you should leave the library line blank If you wish to use the default technology of AMI05 you can leave the process and rules lines blank also They are loaded by default Once you click OK on this dialog box a cell window will appear having the name of the design Method 2 Use Create SDL If you wish to use the default technology of AM1 05 or want to change the technology process information later you can use Create SDL from Click on Creade SDL on the palette menu to bring up the dialog box Enter the following data and then click OK Already have viewpoint 10 2 Designing ASICs with Mentor Graphics Tools 12 14 01 1 07 pm Copyright 2000 Mentor Graphics Placing components into your layout Path to Viewpoint SPROJECT layout design name sd1 It is important that you specify the SDL viewpoint 10 4 Placing components into your layout Once you have opened your cell you can start performing your layout Yo
125. ution also indudes EldoNet that is a netlister for Eldo You need to be sure EldoNet is also installed in your tree 6 1 Invoking Design Architect IC The design creation process consists of symbol HDL and schematic creation hierarchical interpretation design rule verification and netlist generation Design Architect IC is the preferred tool that you use to create schematic and symbol models Design Architect IC DA IC is a design creation environment that provides you with the following functionality e Schematic capture You can draw a schematic using components from both an ASIC library and your own symbol library e Symbol creation You can create a symbol to represent any collection of con nected components to create a hierarchical block e Analog Simulation You can run an Eldo simulation of your design from within DA IC and view the results You can then make any necessary changes and rerun the simulation without ever leaving the DA_IC environment e Viewpoint Creation You can create all necessary viewpoints for simulation layout and extraction from within DA IC For ADK design kit parts invoke the ADK modified Design Architect IC ADK bin adk_daic Design Architect IC has been customized to add cell menus for the ADK supported technologies To exit from Design Architect I C double click the Select mouse button on the Window Menu button which is located at the top left corner of the Design Architect IC Session window
126. utomatic There is no fully automatic autorouting for SDL designs 10 6 1 Semi automatic routing You can use the AddR command from the ADK Edit menu to add a route A route is a semi automatic way to place metal connections within your circuit DRC rules are followed and you are shown boundary lines where you are allowed to place your route You are restricted to only using valid routing layers such as metall and metal2 so this is does not work for poly for example To use the AddR command simply dick on AddR in the palette menu and then select one pin that has an overflow going to from it You then dick at each point where the wire should bend If you want to change layers and put down a via where appropriate press the space bar to cycle through the valid layers When done double click and the route will end You can continue this procedure for all the metal connections in your cell The routes placed are really paths so you can edit them as you would any path 10 6 2 Routing with paths For some layers like poly you cannot use the semi automatic routing tools Here you must use a manual tool One such way to manually route is to use paths Paths are of a set width and you simply dick at each point at which the path should touch You can set the path to be defined from a center point or the left or right edge of the path To add a path click on Path in the ADK Edit menu The path prompt bar will appear and you will be able to speci
127. utoroute the currently selected overflow This will only route on the Designing ASICs with Mentor Graphics Tools A 3 Copyright 2000 Mentor Graphics 12 14 01 11 28 am Chapter ADK Menus and Commands metal routing layers It will not route on poly e Comp Compact your design This runs the IC Station compactor The next section has functions to add various shapes and text e Shape This is the Add Shape command to allow you to add arbitrary shapes on any layer you wish e Path This function allows you to place paths in your cell e AddR Add Route This is the routing tool to manually route your design This will only route on the metal routing layers defined in the process e Text Allows you to add text to your cell TheEdit section provides several functions for editing your cell and the objects in the cell Copy Copy selected object s to location you specify Move Move the selected object s to the location you specify Align Align selected object s Rotate Rotate the selected object s Flip Flip the selected object s e Stretch Stretch the selected objects cannot be used on devices The verification section of the palette menu allows your to easily perform DRC LVS and extraction of your cell without leaving the palette e DRC This menu allows you to run the DRC check and then to scan through the results and view your DRC errors if any e Load Rules f you need to change the rules that you are using us
128. y moving the mouse pointer into the palette menu area and choosing the following popup menu item Display Schematic Palette A schematic palette appears View the schematic add rou palette by clicking on the ADD ROUTE common command button in the schematic palette menu Theschematic add rou palette appears Click on the ADD WIRE icon in the schematic add rou palette menu The ADD WI prompt bar appears Position the mouse poi nter where you want the net to begin usually this is at an instance pin and dick the Select mouse button Theinitial point of the net becomes fixed and a ghost net image rubber bands as you move your mouse Movethe end of the net segment to the location that you desire and click the Select mouse button Design Architect instanti ates the net segment between theinitial and final points that you specified To continue adding segments to the net move the mouse pointer to the next position and dick the Select mouse button To complete the net double dick the Select mouse button The ADD WI prompt bar remains active so that you can begin drawing another net Click on the Cancel button to remove the ADD WI prompt bar 7 2 3 1 Naming Nets To name a net in the schematic 1 2 Select Net Display the Name Net prompt bar popup gt Name Net 7 2 3 2 Using Buses To connect buses to single nets and vice versa 1 Click on the ADD BUS icon in the schematic_add_rou palet
129. your Design 2 000 eee 6 10 6 4 1 Entering Simulation Mode 000 e eee eee 6 10 6 4 2 Preparing for Simulation 0 0 000000 e eee 6 10 6 4 2 1 Setting Node 0 eicninexndcead bebe eaten KANG es a bes 6 11 6 4 2 2 Setup Analysis Parameters cece eee 6 11 6 4 2 3 Choosing Probes soc ede scenes BG KA BG DRA eases dee 6 11 6 4 2 4 Selecting Models 0 0202 c cece eee 6 11 6 4 2 5 Displaying your Setup 20000 eee 6 11 2 Designing ASICs with Mentor Graphics Tools 12 14 01 1 12 pm Copyright 1999 Mentor Graphics 6 4 2 6 Extracting the Netlist 204G accesses Gene decku eee t ceed 6 12 6 4 2 7 Adding Voltage Sources and Additional Netlist Items 6 12 6 4 3 Running the Simulator 000 eee eee 6 12 6 4 4 Viewing Simulation Results 00 eee 6 12 6 5 What to do After Design Architect IC 0000 eee eee 6 13 Chapter 7 Creating a Schematic an 7 1 7 1 Invoking Design Architect 000 cece ee ee 7 1 7 2 Creating a Schematic ca ak eke iaedey LA DEGREE KA b ha tb KGG 7 1 7 2 1 Opening a Schematic Sheet 0c e eee eee 7 1 7 2 2 Choosing and Placing Component Symbols on a Sheet 7 2 7 2 2 1 Place a Logic Component Symbol 200000 7 2 7 2 2 2 Place an SDL Symbol 7 oad can ce nannaa 7 2 7 2 2 3 Using the Dialog Navigator to Place a Component Symbol 7 3 7 2 2
130. your environment e Useadk da adk dve adk as adk gs and adk ic as appropriate Designing ASI Cs with Mentor Graphics Tools 1 3 Copyright 2000 Mentor Graphics 12 10 01 4 03 pm Chapter 1 Installing the ADK 1 1 2 3 SDL only flow using both ICFlow and C x D x trees This configuration is best when you have CF low 2001 x installed are using standard cells and want to use QuickSim to do digital simulation before or after layout You will use adk daic for schematic entry and analog simulation adk qs for QuickSim simulations adk_ic for layout e CFlow tools installed and MGC HOME set to the install directory e ANACAD tools eldo installed and the anacad environment properly set as per M entor s installation instructions e C xor D x treeinstalled and LEGACY MGC TOOLS set to the installation path e Useadk daic adk qs and adk ic as appropriate 1 1 2 4 Non Eldo SDL only flow using both ICFlow and C x D x trees This configuration is best when you have ICF low 2001 x installed are using standard cells do not have Eldo installed and want to use QuickSim to do digital simulation before or after layout You will use adk daic for schematic entry and analog simulation adk qs for QuickSim simulations adk as for analog simulations and adk ic for layout e ICFlow tools installed and MGC HOME set to the install directory e C xor D x treeinstalled and LEGACY MGC TOOLS set to the installation path e Useadk daic adk qs and ad

Designing ASICs with the ADK Design Kit and Mentor

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