Home

LPC2917,19 - NXP Semiconductors

1. 14 OVEIVIEW e cee praire ped xx Rus 14 Description eso beard OS ks 15 Flash memory controller pin description 16 Flash memory controller clock description 16 Flash 16 Flash bridge wait states 17 External static memory controller 17 OvelVIeW cd ques i x Rd erue ES 17 18 External static memory controller description 22522 xS 19 External static memory controller clock description 19 External memory timing diagrams 19 General subsystem 21 General subsystem clock description 21 8 3 2 8 3 2 1 8 3 2 2 8 3 2 8 8 3 3 8 3 3 1 8 3 3 2 8 3 3 3 8 3 4 8 3 4 1 8 3 4 2 8 3 4 3 8 4 8 41 8 4 2 8 4 2 1 8 4 2 2 8 4 2 3 8 4 2 4 8 4 3 8 4 3 1 8 4 3 2 8 4 3 3 8 4 3 4 8 4 4 8 4 4 1 8 4 4 2 8 4 4 3 8 4 4 4 8 4 5 8 4 5 1 8 4 5 2 8 4 5 3 8 4 5 4 8 4 5 5 8 4 6 8 4 6 1 8 4 6 2 8 4 6 3 8 4 6 4 8 5 8 5 1 8 5 2 8 5 3 8 6 8 6 1 8 6 2 ARMS microcontroller with CAN and LIN Chip and feature identification 21 Overview 21 21 CFID pin 21 System control unit 21 Overview 21
2. FF LPC2917 19 BUS ARMS microcontroller with CAN and LIN Rev 01 31 July 2008 Product data sheet 1 Introduction 1 1 About this document This document lists detailed information about the LPC2917 19 device It focuses on factual information like pinning characteristics etc Short descriptions are used to outline the concept of the features and functions More details and background on developing applications for this device are given in the LPC2917 19 User manual see Ref 1 No explicit references are made to the User manual 1 2 Intended audience This document is written for engineers evaluating and or developing systems hard and or software for the LPC2917 19 Some basic knowledge of ARM processors and architecture and ARM968E S in particular is assumed see Ref 2 2 General description 2 1 Architectural overview The LPC2917 19 consists of An ARM968E S processor with real time emulation support An AMBA Advanced High performance Bus AHB for interfacing to the on chip memory controllers Two DTL buses a universal NXP interface for interfacing to the interrupt controller and the Power Clock and Reset Control cluster also called subsystem Three ARM Peripheral Buses APB a compatible superset of ARM s AMBA advanced peripheral bus for connection to on chip peripherals clustered in subsystems One ARM Peripheral Bus for event router and system control T
3. 21 SCU description 21 Event 21 Overview 22 222522 222 2 2 2 21 Description csse ke Rs 22 Event router pin description and mapping to register bit positions 22 Peripheral subsystem 22 Peripheral subsystem clock description 22 Watchdog timer 23 Overview 23 23 Pin description 23 Watchdog timer clock description 23 TiffiGl ores uo eis ada RE REI LES 24 OVeIVIGW e ere E RR ins 24 Description 24 Pin description 24 Timer clock description 25 UAFITS eR RR UA SOR atone Bans 25 i oos per Se EE E 25 Description sese ne RR ERR 25 UART pin description 25 UART clock description 26 Serial peripheral interface 26 Overview essere pkt eee 26 Functional description 26 Modes of operation 27 SPI pin 27 SPI clock 27 General purpose 28 Overview 28 Description isse RE hm RR Rs 28 GPIO pin description
4. HF HF HF ORG FF FF OR FF ok ok ok FF RUN kot OR Fo Ft v4 o FH BG HF HF ok NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 48 of 67 NXP Semiconductors LPC291 7 1 9 8 8 6 3 8 9 8 9 1 8 9 2 LPC2917 19 1 ARMS microcontroller with CAN and LIN Table 27 Branch clock overview continued Legend 1 Indicates that the related register bit is tied off to logic HIGH all writes are ignored 0 Indicates that the related register bit is tied off to logic LOW all writes are ignored Indicates that the related register bit is readable and writable Branch clock name Base clock Implemented switch on off mechanism WAKE UP AUTO RUN CLK_ADC1 BASE_ADC_CLK CLK_ADC2 BASE_ADC_CLK CLK_TESTSHELL_IP BASE CLK TESTSHELL 0 0 1 PMU pin description The PMU has no external pins Vectored interrupt controller Overview The LPC2917 19 contains a very flexible and powerful Vectored Interrupt Controller VIC to interrupt the ARM processor on request The key features are Level active interrupt request with programmable polarity 56 interrupt request inputs Software interrupt request capability associated with each request input Observability of interrupt request state before masking Software programmable priority assignments
5. 32 bit watchdog with timer change protection running on safe clock Upto 108 general purpose pins with programmable pull up pull down or bus keeper Vectored Interrupt Controller VIC with 16 priority levels Two 8 channel 10 bit ADCs provide a total of up to 16 analog inputs with conversion times as low as 2 44 us per channel Each channel provides a compare function to minimize interrupts Up to 24 level sensitive external interrupt pins including CAN and LIN wake up features External Static Memory Controller SMC with eight memory banks up to 32 bit data bus up to 24 bit address bus Processor wake up from power down via external interrupt pins CAN or LIN activity Flexible Reset Generation Unit RGU able to control resets of individual modules Flexible Clock Generation Unit CGU able to control clock frequency of individual modules On chip very low power ring oscillator fixed frequency of 0 4 MHz always on to provide a Safe Clock source for system monitoring On chip crystal oscillator with a recommended operating range from 10 MHz to 25 MHz maximum PLL input 15 MHz On chip PLL allows CPU operation up to a maximum CPU rate of 80 MHz Generation of up to 10 base clocks Seven fractional dividers Highly configurable system Power Management Unit PMU Clock control of individual modules NXP B V 2008 All rights reserved Product data sheet
6. detail X UNIT A1 A2 bp c Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE SOT486 1 136 23 5 026 Ede 00 03 14 03 02 20 Fig 15 Package outline SOT486 1 LQFP144 LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 58 of 67 NXP Semiconductors LPC291 7 1 9 ARMS microcontroller with CAN and LIN 14 Soldering of SMD packages 14 1 14 2 This text provides a very brief insight into a complex technology A more in depth account of soldering ICs can be found in Application Note AN10365 Surface mount reflow soldering description Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards PCBs to form electrical circuits The soldered joint provides both the mechanical and the electrical connection There is no single soldering method that is ideal for all IC packages Wave soldering is often preferred when through hole and Surface Mount Devices SMDs are mixed on one printed wiring board however it is not suitable for fine pitch SMDs Reflow soldering is ideal for the small pitches and high densities that come
7. lo 125 SG all voltages are measured with respect to ground positive currents flow into the IC unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Power up reset Vtrip high high trip level voltage 6 1 1 1 4 1 6 V Virip low low trip level voltage 1 0 1 3 1 5 V Vuip dit difference between high 6 50 120 180 mV and low trip level voltage 1 All parameters are guaranteed over the virtual junction temperature range by design Pre testing is performed at Tamb 125 on wafer level Cased products are tested at Tamb 25 final testing Both pre testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range 2 Leakage current is exponential to temperature worst case value is at 125 Ty All clocks off Analog modules and flash powered down 3 For Port 0 pin O to pin 15 add maximum 1 5 pF for input capacitance to ADC For Port 0 pin 16 to pin 31 add maximum 1 0 pF for input capacitance to ADC 4 This value is the minimum drive capability Maximum short circuit output current is 33 mA drive HIGH level shorted to ground or 38 mA drive LOW level shorted to Vpp o The device will be damaged if multiple outputs are shorted 5 Cyta is crystal load capacitance and are the two external load capacitors 6 The power up reset has a time filter Vpp cong must be above Virip high for 2 us before reset is de assert
8. ARMS microcontroller with CAN and LIN Table 7 Base clock and branch clock overview continued Base clock Branch clock name Parts of the device clocked by Remark this branch clock BASE_UART_CLK CLK_UARTO UART 0 interface clock CLK_UART1 UART 1 interface clock BASE_SPI_CLK CLK_SPIO SPI 0 interface clock CLK_SPI1 SPI 1 interface clock CLK SPI2 SPI 2 interface clock BASE TMR CLK CLK TMRO Timer 0 clock for counter part CLK TMR1 Timer 1 clock for counter part CLK TMR2 Timer 2 clock for counter part CLK TMR3 Timer 3 clock for counter part BASE ADC CLK CLK ADC1 Control of ADC 1 capture sample result CLK ADC2 Control of ADC 2 capture sample result BASE CLK TESTSHELL TESTSHELL 1 This clock is always on cannot be switched off for system safety reasons 2 In the peripheral subsystem parts of the Timers watchdog timer SPI and UART have their own clock source See Section 8 4 for details 3 the Power Clock and Reset Control subsystem parts of the CGU RGU PMU have their own clock source See Section 8 8 for details 4 The clock should remain activated when system wake up on timer or UART is required 8 Block description 8 1 Flash memory controller 8 1 1 Overview LPC2917 19 1 The Flash Memory Controller FMC interfaces to the embedded flash memory for two tasks Providing memory data transfer Memory configuration via triggering programming and erasing The flash memory has a 128 bit w
9. Overview The LPC2917 19 contains two identical UARTs located at different peripheral base addresses The key features are 16 byte receive and transmit FIFOs Register locations conform to 550 industry standard Receiver FIFO trigger points at 1 byte 4 bytes 8 bytes and 14 bytes Built in baud rate generator Description The UART is commonly used to implement a serial interface such as RS232 The LPC2917 19 contains two industry standard 550 UARTS with 16 byte transmit and receive FIFOs but they can also be put into 450 mode without FIFOs UART pin description The two UARTSs in the LPC2917 19 have the following pins The UART pins are combined with other functions on the port pins of the LPC2917 19 Table 15 shows the UART pins x runs from 0 to 1 Table 15 UART pins Symbol Direction Description UARTx TXD OUT UART channel x transmit data output UARTx RXD IN UART channel x receive data input NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 25 of 67 NXP Semiconductors LPC291 7 1 9 8 4 4 4 8 4 5 8 4 5 1 8 4 5 2 LPC2917 19 1 ARMS microcontroller with CAN and LIN UART clock description The UART modules are clocked by two different clocks SYS PESS and CLK_UARTx x 0 1 see Section 7 2 2 Note that each UART has its own UARTx branch clock for power management The frequency of all CLK UARTx clocks is identical since they are derived fr
10. The PWM block diagram in Figure 10 shows the basic architecture of each PWM PWM functionality is split into two major parts a APB domain and a PWM domain both of which run on clocks derived from the BASE MSCSS This split into two domains affects behavior from a system level perspective The actual PWM and prescale counters are located in the PWM domain but system control takes place in the APB domain The actual PWM consists of two counters a 16 bit prescale counter and a 16 bit PWM counter The position of the rising and falling edges of the PWM outputs can be programmed individually The prescale counter allows high system bus frequencies to be scaled down to lower PWM periods Registers are available to capture the PWM counter values on external events Note that in the Modulation and Sampling SubSystem each PWM has its individual clock source CLK MSCSS x runs from 0 to Both the prescale and the timer counters within each PWM run on this clock MSCSS PWMXx and all time references are related to the period of this clock See Section 8 8 for information on generation of these clocks Synchronizing the PWM counters A mechanism is included to synchronize the PWM period to other PWMs by providing sync input and a sync output with programmable delay Several PWMs can be synchronized using the trans enable in trans enable out and sync in sync out ports See Section 8 7 2 1 for details of the connections of the
11. 28 GPIO clock 28 CAN 29 Overview dr SEES 29 Global acceptance 29 CAN pin 29 a EET 29 Overview 22522222222 002 2 2554 21 29 LIN pin 30 continued gt gt NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 66 of 67 NXP Semiconductors LPC2917 19 8 7 8 7 1 8 7 2 8 7 2 1 8 7 3 8 7 4 8 7 5 8 7 5 1 8 7 5 2 8 7 5 8 8 7 5 4 8 7 6 1 8 7 6 2 8 7 6 3 8 7 6 4 8 7 6 5 8 7 6 6 8 7 7 8 7 7 1 8 7 7 2 8 7 7 8 8 7 7 4 8 8 1 8 8 2 8 8 3 8 8 4 8 8 4 1 8 8 4 2 8 8 4 3 8 8 4 4 8 8 5 8 8 5 1 8 8 5 2 8 8 5 3 8 8 6 8 8 6 1 8 8 6 2 8 8 6 3 8 9 1 8 9 2 8 9 3 8 9 4 10 11 12 Modulation and sampling control subsystem Description Synchronization and trigger features of the 5 55 MSCSS pin MSCSS clock description Analog to digital converter OVERVIEWS eus ADC pin description ADC clock Description avi RED Eu Synchronizing the PWM counters Master an
12. Rev 01 31 July 2008 3 of 67 NXP Semiconductors LPC291 7 1 9 ARMS microcontroller with CAN and LIN Allows minimization of system operating power consumption in any configuration Standard ARM test and debug interface with real time in circuit emulator Boundary scan test supported Dual power supply CPU operating voltage 1 8 V 5 96 operating voltage 2 7 V to 3 6 V inputs tolerant up to 5 5 V B 144 pin LQFP package 40 C to 85 C ambient operating temperature range 4 Ordering information Table 1 Ordering information Type number Package Name Description Version LPC2917FBD144 LQFP144 plastic low profile quad flat package 144 leads body 20 x 20 x 1 4 mm SOT486 1 LPC2919FBD144 LQFP144 plastic low profile quad flat package 144 leads body 20 x 20 x 1 4 mm SOT486 1 4 1 Ordering options Table 2 Part options Type number Flash memory RAM SMC LIN 2 0 Package LPC2917FBD144 512 kB 80 kB including TCMs 32 bit 2 LQFP144 LPC2919FBD144 768 kB 80 kB including TCMs 32 bit 2 LQFP144 LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 4 of 67 NXP Semiconductors LPC2917 19 5 Block diagram ARMS microcontroller with CAN and LIN LPC2917 2919 ITCM 16 kB VECTORED INTERRUPT CONTROLLER CLOCK GENERATION C UNIT RESET GENERATION UNIT POWER MANAGEMENT UNIT nN TIMERO t MTMR
13. The register interface towards the system bus is clocked by CLK MSCSS ADOx Control logic for the analog section of the ADC is clocked by CLK ADOx see also Figure 9 PWM Overview The MSCSS in the LPC2917 19 includes four PWM modules with the following features Six pulse width modulated output signals Double edge features rising and falling edges programmed individually Optional interrupt generation on match each edge Different operation modes continuous or run once 16 bit PWM counter and 16 bit prescale counter allow a large range of PWM periods A protective mode TRAP holding the output in a software controllable state and with optional interrupt generation on a trap event Three capture registers and capture trigger pins with optional interrupt generation on a capture event Interrupt generation on match event capture event PWM counter overflow or trap event A burst mode mixing the external carrier signal with internally generated PWM Programmable sync delay output to trigger other PWM modules master slave behavior Description The ability to provide flexible waveforms allows PWM blocks to be used in multiple applications e g automotive dimmer lamp control and fan control Pulse width modulation is the preferred method for regulating power since no additional heat is generated and it is energy efficient when compared with linear regulating voltage control networks The PWM delivers
14. 8 1 4 8 1 5 8 1 6 8 2 8 2 1 8 2 2 8 2 3 8 2 4 8 2 5 8 3 8 3 1 LPC2917 19 1 Introduction 1 About this 1 Intended audience 1 General description 1 Architectural overview 1 968 5 2 On chip flash memory system 2 On chip static 3 2 222224 2 4 3 3 Ordering 4 Ordering 4 Block diagram 5 Pinning 6 PINNING me 6 Pin description 6 General 6 LQFP144 pin assignment 6 Functional description 10 Reset debug test and power description 10 Reset and power up behavior 10 Reset strategy 10 IEEE 1149 1 interface pins JTAG boundary scan test 11 Power supply pins description 11 Clocking strategy 11 Clock 11 Base clock and branch clock relationship 12 Block 14 Flash memory
15. Controller Area Network CAN part 1 data link layer and physical signalling LIN LIN specification package revision 2 0 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 63 of 67 NXP Semiconductors LPC291 7 1 9 ARMS microcontroller with CAN and LIN 17 Revision history Table 35 Revision history Document ID Release date Data sheet status Change notice Supersedes LPC2917 19 1 20080731 Product data sheet LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 64 of 67 Semiconductors 2917 19 18 Legal information 18 1 Data sheet status ARMS microcontroller with CAN and LIN Document 112 Product statusi Definition Objective short data sheet Development Preliminary short data sheet Qualification Product short data sheet Production This document contains data from the objective specification for product development This document contains data from the preliminary specification This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 term short data sheet is explained in section Definitions 3 product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The la
16. GPIOO pin 31 0 IN OUT GPIO port x pins 31 to 0 GPIO1 pin 31 0 IN OUT GPIO port x pins 31 to 0 GPIO2 pin 27 0 IN OUT GPIO port x pins 27 to 0 GPIO3 pin 15 0 IN OUT GPIO port x pins 15 to 0 GPIO clock description The GPIO modules are clocked by several clocks all of which are derived from BASE SYS SYS PESS SYS x 0 3 see Section 7 2 2 Note that each GPIO has its own CLK 65 5 GPIOx branch clock for power management The frequency of all clocks SYS GPIOx is identical to CLK SYS PESS since they are derived from the same base clock BASE SYS NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 28 of 67 NXP Semiconductors LPC291 7 1 9 8 5 8 5 1 8 5 2 8 5 3 8 6 8 6 1 LPC2917 19 1 ARMS microcontroller with CAN and LIN CAN gateway Overview Controller Area Network CAN is the definition of a high performance communication protocol for serial data communication The two CAN controllers in the LPC2917 19 provide a full implementation of the CAN protocol according to the CAN specification version 2 0B The gateway concept is fully scalable with the number of CAN controllers and always operates together with a separate powerful and flexible hardware acceptance filter The key features are Supports 11 bit as well as 29 bit identifiers Double receive buffer and triple transmit buffer Programmable error warn
17. including interrupts 8 9 3 VIC pin description The VIC module in the LPC2917 19 has no external pins 8 9 4 VIC clock description The VIC is clocked by CLK SYS VIC see Section 7 2 2 LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 50 of 67 NXP Semiconductors LPC2917 19 9 Limiting values Table 28 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 ARMS microcontroller with CAN and LIN Symbol Parameter Conditions Supply pins Prot total power dissipation VDD CORE core supply voltage Vpp osc Oscillator and PLL supply voltage 3 3 V ADC analog supply voltage I O supply voltage supply current average value per supply pin lss ground current average value per ground pin Input pins and pins voltage OSC Vito I O input voltage Vanc ADC input voltage I O port 0 VvREFP voltage on pin VREFP VVREFN voltage on pin VREFN ADC input current average value per input pin Output pins and I O pins configured as output lous HIGH level short circuit drive HIGH output shorted output current to Vss o lois LOW level short circuit drive LOW output shorted output current to vpp o General Tstg storage temperature Tamb ambient temperature Ty virtual junction temperature Memory lendu tl endurance of flash memory tret tl flash memory retention time LPC291
18. 10 pins supply 3 3 V Vss 0 I O pins ground Vpp oso oscillator and PLL supply Vss oso oscillator ground Vppa apcava X ADC1 2 3 3 V supply Vss PLL PLL ground Clocking strategy Clock architecture The LPC2917 19 contains several different internal clock areas Peripherals like Timers SPI UART CAN and LIN have their own individual clock sources called Base Clocks All base clocks are generated by the Clock Generation Unit CGU They may be unrelated in frequency and phase and can have different clock sources within the CGU The system clock for the CPU and AHB Bus infrastructure has its own base clock This means most peripherals are clocked independently from the system clock See Figure 3 for an overview of the clock areas within the device Within each clock area there may be multiple branch clocks which offers very flexible control for power management purposes All branch clocks are outputs of the Power Management Unit PMU and can be controlled independently Branch clocks derived from the same base clock are synchronous in frequency and phase See Section 8 8 for more details of clock and power control within the device NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 11 of 67 2917 19 ARMS microcontroller with CAN and LIN NXP Semiconductors JTAG interface LPC2917 2919 TEST DEBUG INTERFACE ARM968E S AHB bus VECTORED AHB TO D
19. 500 us PLL fi PLL PLL input frequency 10 25 MHz fo PLL PLL output frequency 10 160 MHz direct mode 156 320 MHz Analog to digital converter input frequency Bl 4 4 5 MHz simax maximum sampling 4 5 MHz rate fs fiapcy n 1 with n resolution resolution 2 bit 1500 ksample s resolution 10 bit 400 ksample s conversion time In number of ADC clock 3 11 cycles cycles In number of bits 2 10 bits Flash memory linit initialization time 150 us twr pg page write time 0 95 1 1 05 ms ter sect sector erase time 95 100 105 ms th BIST flash word BIST time 38 70 ns ta clk clock access time 63 4 ns la A address access time 60 3 ns LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 56 of 67 NXP Semiconductors LPC291 7 1 9 ARMS microcontroller with CAN and LIN Table 31 Dynamic characteristics continued VDD CORE 2 7 V to 3 6 V VDDA ADC3V3 3 0Vto 3 6 V Ty 4096 all voltages are measured with respect to ground positive currents flow into the IC unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit External static memory controller ta R int internal read access 20 5 ns time tacwyint internal write access 24 9 ns time UART fUART UART frequency Vesoaafckuart Vofcik uart MHz SPI SPI operating master operation
20. C 5 PWMo 2 3 C ac GLOBAL ACCEPTANCE gt FILTER NEN S Fig 1 LPC2917 19 block diagram Nir nic press AHB TO APB BRIDGE C JTAG interface TEST DEBUG INTERFACE DTCM 16 kB ARM968E S A0 bus 3 EXTERNAL STATIC MEMORY CONTROLLER C EMBEDDED SRAM 16 kB C EMBEDDED SRAM 32 kB C EMBEDDED FLASH 512 768 kB cm BRIDGE C SYSTEM CONTROL C EVENT ROUTER GENERAL PURPOSE I O PORTS 0 1 2 3 C AHB TO APB BRIDGE TIMER 0 1 2 3 SPIO 1 2 UARTO 1 WDT 002aad840 LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 5 of 67 NXP Semiconductors LPC2917 19 6 Pinning information 6 1 Pinning ARMS microcontroller with CAN and LIN Fig 2 Pin configuration for SOT486 1 LQFP144 LPC2917FBD144 LPC2919FBD144 002aad935 6 2 Pin description 6 2 1 General description The LPC2917 19 has up to four ports two of 32 pins each one of 28 pins and one of 16 pins The pin to which each function is assigned is controlled by the SFSP registers in the SCU The functions combined on each port pin are shown in the pin description tables in this section 6 2 2 LQFP144 pin assignment Table3 LQFP144 pin assignment Pin name Pin Description Default function Function 1 Function 2 Function 3 TDO 1 IEEE 1149 1 te
21. NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 20 of 67 NXP Semiconductors LPC291 7 1 9 8 3 8 3 1 8 3 2 8 3 2 1 8 3 2 2 8 3 2 3 8 3 3 8 3 3 1 8 3 3 2 8 3 3 3 8 3 4 8 3 4 1 LPC2917 19 1 ARMS microcontroller with CAN and LIN Address pins on the device are shared with other functions When connecting external memories check that the pin is programmed for the correct function Control of these settings is handled by the SCU General subsystem General subsystem clock description The general subsystem is clocked by CLK SYS GESS see Section 7 2 2 Chip and feature identification Overview The key features are Identification of product dentification of features enabled Description The Chip Feature ID CFID module contains registers which show and control the functionality of the chip It contains an ID to identify the silicon and also registers containing information about the features enabled or disabled on the chip CFID pin description The CFID has no external pins System control unit Overview The SCU takes care of system related functions The key feature is configuration of the I O port pins multiplexer Description The SCU defines the function of each I O pin of the LPC2917 19 The I O pin configuration should be consistent with peripheral function usage SCU pin description The SCU has no external pins Event router
22. OUT address bus EXTBUS 0 31 0 IN OUT data bus 8 2 4 External static memory controller clock description The External Static Memory Controller is clocked by CLK_SYS_SMC see Section 7 2 2 8 2 5 External memory timing diagrams A timing diagram for reading from external memory is shown in Figure 4 The relationship between the wait state settings is indicated with arrows cs OE es Ll e WSTOEN WSTI 002aad936 WSTOEN 3 WST1 7 Fig 4 Reading from external memory A timing diagram for writing to external memory is shown In Figure 5 The relationship between wait state settings is indicated with arrows LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 19 of 67 NXP Semiconductors LPC2917 19 LPC2917 19 1 ARMS microcontroller with CAN and LIN CLK SYS cs WE N BLS DATA X X WSTWEN werg 002aad937 WSTWEN 3 WST2 7 Fig 5 Writing to external memory Usage of the idle turn around time IDCY is demonstrated In Figure 6 Extra wait states are added between a read and a write cycle in the same external memory device CLK SYS CS WE N BLS gt WSTOEN WSTWEN WST1 IDCY WST2 002aad938 WSTOEN 5 WSTWEN 5 WST1 7 WST2 6 IDCY 5 Fig 6 Reading writing external memory
23. Overview The event router provides bus controlled routing of input events to the vectored interrupt controller for use as interrupt or wake up signals Key features Up to 24 level sensitive external interrupt pins including CAN LIN and RXD wake up features plus three internal event sources nput events can be used as interrupt source either directly or latched edge detected Direct events disappear when the event becomes inactive NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 21 of 67 NXP Semiconductors LPC2917 19 8 3 4 2 Description 8 3 4 3 8 4 8 4 1 LPC2917 19 1 ARMS microcontroller with CAN and LIN Latched events remain active until they are explicitly cleared Programmable input level and edge polarity Event detection maskable Event detection is fully asynchronous so no clock is required The event router allows the event source to be defined its polarity and activation type to be selected and the interrupt to be masked or enabled The event router can be used to start a clock on an external event The vectored interrupt controller inputs are active HIGH Event router pin description and mapping to register bit positions The event router module in the LPC2917 19 is connected to the pins listed below The pins are combined with other functions on the port pins of the LPC2917 19 Table 13 shows the pins connected to the event router and also the
24. Section 8 8 5 Pin description The watchdog has no external pins Watchdog timer clock description The watchdog timer is clocked by two different clocks CLK SYS PESS CLK SAFE see Section 7 2 2 The register interface towards the system bus is clocked by CLK SYS PESS The timer and prescale counters are clocked by SAFE which is always on NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 23 of 67 NXP Semiconductors LPC291 7 1 9 8 4 3 8 4 3 1 8 4 3 2 8 4 3 3 LPC2917 19 1 ARMS microcontroller with CAN and LIN Timer Overview The LPC2917 19 contains six identical timers four in the peripheral subsystem and two in the Modulation and Sampling Control SubSystem MSCSS located at different peripheral base addresses This section describes the four timers in the peripheral subsystem Each timer has four capture inputs and or match outputs Connection to device pins depends on the configuration programmed into the port function select registers The two timers located in the MSCSS have no external capture or match pins but the memory map is identical see Section 8 7 7 One of these timers has an external input for a pause function The key features are 32 bit timer counter with programmable 32 bit prescaler Up to four 32 bit capture channels per timer These take a snapshot of the timer value when an external signal connected to the TIMERx CAPn input cha
25. Vesoz4fck spi Vofctk spi MHz frequency slave operation Vesoz4fck sp Vafotk spi MHz Jitter specification liit cc p p cycle to cycle jitter on CAN TXDC pin B 0 4 1 ns peak to peak value 1 2 3 4 5 All parameters are guaranteed over the virtual junction temperature range by design Pre testing is performed at Tamb 125 C ambient temperature on wafer level Cased products are tested at Tamp 25 C final testing Both pre testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range See Table 23 This parameter is not part of production testing or final testing hence only a typical value is stated Oscillator start up time depends on the quality of the crystal For most crystals it takes about 1000 clock pulses until the clock is fully stable Duty cycle clock should be as close as possible to 50 96 LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 57 of 67 NXP Semiconductors LPC2917 19 13 Package outline LQFP144 plastic low profile quad flat package 144 leads body 20 x 20 x 1 4 mm a pin 1 index DIMENSIONS mm are the original dimensions ARMS microcontroller with CAN and LIN SOT486 1
26. can be copied to the secondary buffer line which allows the flash to start a speculative read of the next flash word Both buffer lines are invalidated after Initialization Configuration register access Data latch reading Index sector reading The modes of operation are listed in Table 8 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 15 of 67 NXP Semiconductors LPC291 7 1 9 8 1 4 LPC2917 19 1 ARMS microcontroller with CAN and LIN Table8 Flash read modes Synchronous timing No buffer line for single non linear reads one flash word read per word read Single buffer line default mode of operation most recently read flash word is kept until another flash word is required Asynchronous timing No buffer line one flash word read per word read Single buffer line most recently read flash word is kept until another flash word is required Dual buffer line single on a buffer miss a flash read is done followed by at most one speculative speculative read optimized for execution of code with small loops less than eight words from flash Dual buffer line always most recently used flash word is copied into second buffer line next speculative flash word read is started highest performance for linear reads Flash memory controller pin description The flash memory controller has no external pins However the flash can be programmed via the JTAG pins s
27. care of communication with the AHB system bus LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 39 of 67 NXP Semiconductors LPC2917 19 ARMS microcontroller with CAN and LIN AHB2DTL BRIDGE EXTERNAL OSCILLATOR LOW POWER RING OSCILLATOR CGU REGISTERS RGU branch clocks CLOCK AHB master disable grant ENABLE CONTROL AHB master disable request PMU k REGISTERS eae AHB_RST REGISTERS NY RESET OUTPUT SCU RST DELAY LOGIC WARM RST COLD RST PCR RST RGU RST INPUT DEGLITCH SYNC RST N device pin reset from watchdog counter Fig 11 PCRSS block diagram 7 v Y POR RST 002aad836 LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 40 of 67 NXP Semiconductors LPC291 7 1 9 8 8 3 8 8 4 8 8 4 1 8 8 4 2 LPC2917 19 1 ARMS microcontroller with CAN and LIN PCR subsystem clock description The PCRSS is clocked by a number of different clocks CLK_SYS_PCRSS clocks the AHB side of the AHB DTL bus bridge and CLK PCR SLOW clocks the CGU RGU and PMU internal logic see Section 7 2 2 CLK SYS PCRSS is derived from BASE SYS CLK which can be switched off in low power modes CLK PCR SLOW is derived from BASE PCR CLK and is always on in order to be able to wake up from l
28. frequency that guarantees stable operation of the LPC2917 19 2 Fixed to low power oscillator NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 41 of 67 NXP Semiconductors LPC291 7 1 9 ARMS microcontroller with CAN and LIN For generation of these base clocks the CGU consists of primary and secondary clock generators and one output generator for each base clock CLOCK GENERATION UNIT CGU i clkout EXTERNAL clkout120 OSCLLLATOR clkout240 FREQUENCY CLOCK MONITOR DETECTION M 002aad835 Fig 12 Block diagram of the CGU There are two primary clock generators a low power ring oscillator LP OSC and a crystal oscillator See Figure 12 LP OSC is the source for the BASE PCR CLK that clocks the CGU itself and for BASE SAFE CLK that clocks a minimum of other logic in the device like the watchdog timer To prevent the device from losing its clock source OSC cannot be put into power down The crystal oscillator can be used as source for high frequency clocks or as an external clock input if a crystal is not connected Secondary clock generators are a PLL and seven fractional dividers FDIVO 6 The PLL has three clock outputs normal 120 phase shifted and 240 phase shifted Configuration of the CGU For every output generator generating the base clocks a choice can be made from the primary and secondary clo
29. from BASE CLK If specific PWM or ADC modules are not used their corresponding clocks can be switched off Analog to digital converter Overview The MSCSS in the LPC2917 19 includes two 10 bit successive approximation analog to digital converters The key features of the ADC interface module are ADC1 and ADC2 Eight analog inputs time multiplexed measurement range up to 3 3V External reference level inputs 400 ksample s at 10 bit resolution up to 1500 ksample s at 2 bit resolution Programmable resolution from 2 bit to 10 bit Single analog to digital conversion scan mode and continuous analog to digital conversion scan mode Optional conversion on transition on external start input timer capture match signal PWM sync or previous ADC Converted digital values are stored a register for each channel Optional compare condition to generate a less than or an equal to or greater than compare value indication for each channel Power down mode Description The ADC block diagram Figure 9 shows the basic architecture of each ADC The ADC functionality is divided into two major parts one part running on the MSCSS Subsystem clock the other on the ADC clock This split into two clock domains affects the behavior from a system level perspective The actual analog to digital conversions take place in the ADC clock domain but system control takes place in the system clock domain A mechanism is
30. mode normal mode Power down mode Input pins and I O pins configured as input Vi input voltage HIGH level input voltage LOW level input voltage Vhys hysteresis voltage HIGH level input leakage current LPC2917 19 1 all port pins and Vpp o applied except port 0 pins 16 to 31 see Section 9 port O pins 16 to 31 all port pins and Vpp o not applied all other pins RESET N TRST N TDI JTAGSEL TMS TCK all port pins RESET N TRST_N TDI JTAGSEL TMS TCK all port pins RESET_N TRST_N TDI JTAGSEL TMS TCK 2 218 1 71 0 5 2 0 0 4 1 80 14 30 Unit 1 89 V 2 5 mA MHz 450 uA 3 6 V 1 89 V 4 5 mA mA 2 uA 3 6 V 1 9 mA 4 HA 5 5 V VVREFP 3 6 V Vpp 0 V V 0 8 V V 1 HA NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 53 of 67 2917 19 ARMS microcontroller with CAN and LIN NXP Semiconductors Table 30 Static characteristics continued Vpb coRE Vpb osc Vpp io 2 7 V to 3 6 V Vppa apcava 3 0 V to 3 6 V Ty 40 C to 125 all voltages are measured with respect to ground positive currents flow into the IC unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit lu LOW level input leakage E 1 li pd pull down input current all port pins Vj 3 3 V 25 50 100 uA 5 5 li pu pull
31. signals towards the peripheral modules The RGU provides individual reset control as well as the monitoring functions needed for tracing a reset back to source 1 Only for 1 8 V power sources LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 10 of 67 NXP Semiconductors LPC291 7 1 9 7 1 3 7 2 7 2 1 LPC2917 19 1 ARMS microcontroller with CAN and LIN IEEE 1149 1 interface pins JTAG boundary scan test The LPC2917 19 contains boundary scan test logic according to IEEE 1149 1 also referred to in this document as JTAG The boundary scan test pins can be used to connect a debugger probe for the embedded ARM processor Pin JTAGSEL selects between boundary scan mode and debug mode Table 5 shows the boundary scan test pins Table 5 IEEE 1149 1 boundary scan test and debug interface Symbol Description JTAGSEL controller select input LOW level selects ARM debug mode and HIGH level selects boundary scan and flash programming pulled up internally TRST_N test reset input pulled up internally active LOW TMS test mode select input pulled up internally TDI test data input pulled up internally TDO test data output TCK test clock input Power supply pins description Table 6 shows the power supply pins Table 6 Power supplies Symbol Description VDD CORE digital core supply 1 8 V Vss CORE digital core ground digital core ADC 1 2 VDp
32. supply for I O P2 8 PMATO 0 SCSO 2 83 GPIO 2 pin 8 PWMO MATO SPIO SCS2 P2 9 PMATO 1 SCSO 1 84 GPIO 2 ping PWMO 1 SPIO SCS1 P1 3 J SCS2 1 PMAT3 S A3 85 GPIO 1 pin 3 SPI2 SCS1 PWMS3 EXTBUS P1 2 SCS2 3 PMAT3 2 A2 86 GPIO 1 pin2 SPI2 SCS3 PWM3 2 EXTBUS A2 P1 1 EH PMATS 1 A1 87 GPIO1 pin 1 EXTINT1 PWM3 1 EXTBUS A1 Vss CORE 88 ground for digital core VDD CORE 89 1 8 V power supply for digital core P1 O EIO PMATS 0 AO 90 GPIO 1 pin 0 EXTINTO PWMS3 EXTBUS 0 LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 8 of 67 NXP Semiconductors LPC2917 19 ARMS microcontroller with CAN and LIN Table3 LQFP144 pin assignment continued Pin name Pin Description Default function Function 1 Function 2 Function 3 P2 10 PMATO 2 SCSO 0 91 GPIO 2 10 PWMO MAT2 SPIO SCSO P2 11 PMATO S SCKO 92 GPIO 2 pin 11 PWMO MAT3 SPIO SCK PO O TXDCO D24 93 GPIO 0 pin 0 CANO TXDC EXTBUS D24 Vss lo 94 ground for I O PO 1J RXDCO D25 95 GPIO 0 pin 1 CANO RXDC EXTBUS D25 PO 2 PMATO O D26 96 2 PWMO MATO EXTBUS D26 PO 3 PMATO 1 D27 97 GPIOO pin PWMO 1 EXTBUS D27 P3 0 PMAT2 0 CS6 98 GPIO 3 0 PWM2 MATO EXTBUS CS6 P3 1J PMAT2 1 CS7 99 GPIO 3 pin 1 PWM2 MAT1 EXTBUS CS7 P2 12 PMATO 4 SDIO 100 GPIO 2 pin 12 PWMO SPIO SDI P2 13 PMATO 5 SDOO 101 GPIO 2 pin 13 PWMO MAT
33. the output clock or sent directly to the output The main output clock is then divided by M by the programmable feedback divider to generate the feedback clock The output signal of the analog section is also monitored by the lock detector to signal when the PLL has locked onto the input clock PSEL bits P23EN bit Y EP li 2PDIV clkout120 ee cco E clkout m bypass direct Fig 14 PLL block diagram e clkout MSEL bits 002aad833 2 Generation of the main clock is restricted by the frequency range of the PLL clock input See Table 31 Dynamic characteristics LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 44 of 67 NXP Semiconductors LPC291 7 1 9 8 8 4 4 8 8 5 8 8 5 1 8 8 5 2 LPC2917 19 1 ARMS microcontroller with CAN and LIN Triple output phases For applications that require multiple clock phases two additional clock outputs can be enabled by setting register P23EN to logic 1 thus giving three clocks with a 120 phase difference In this mode all three clocks generated by the analog section are sent to the output dividers When the PLL has not yet achieved lock the second and third phase output dividers run unsynchronized which means that the phase relation of the output clocks is unknown When the PLL LOCK register is set the second and third phase of the output dividers are
34. to interrupt requests up to 15 levels Software programmable routing of interrupt requests towards the ARM processor inputs IRQ and FIQ Fast identification of interrupt requests through vector Support for nesting of interrupt service routines Description The Vectored Interrupt Controller routes incoming interrupt requests to the ARM processor The interrupt target is configured for each interrupt request input of the VIC The targets are defined as follows Target 0 is ARM processor FIQ fast interrupt service Target 1 is ARM processor IRQ standard interrupt service Interrupt request masking is performed individually per interrupt target by comparing the priority level assigned to a specific interrupt request with a target specific priority threshold The priority levels are defined as follows Priority level 0 corresponds to masked i e interrupt requests with priority 0 never lead to an interrupt Priority 1 corresponds to the lowest priority NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 49 of 67 NXP Semiconductors LPC291 7 1 9 ARMS microcontroller with CAN and LIN Priority 15 corresponds to the highest priority Software interrupt support is provided and can be supplied for Testing Real Time Operating System RTOS interrupt handling without using device specific interrupt service routines Software emulation of an interrupt requesting device
35. 14 2 14 3 14 4 15 16 17 18 18 1 18 2 18 3 18 4 19 20 ARMS microcontroller with CAN and LIN Package 58 Soldering of SMD packages 59 Introduction to soldering 59 Wave and reflow soldering 59 Wave 0 0 59 Reflow 0 0 60 Abbreviations 62 63 Revision history 64 Legal information 65 Data sheet 65 Definitions 65 65 Trademarks 65 Contact information 65 Contents coii REIR RE 66 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2008 All rights reserved For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 31 July 2008 Document identifier LPC2917 19 1
36. 17 19 1 ARMS microcontroller with CAN and LIN General purpose Overview The LPC2917 19 contains four general purpose ports located at different peripheral base addresses In the 144 pin package all four ports are available All I O pins are bidirectional and the direction can be programmed individually The pad behavior depends on the configuration programmed in the port function select registers The key features are General purpose parallel inputs and outputs Direction control of individual bits Synchronized input sampling for stable input data values e All I O defaults to input at reset to avoid any possible bus conflicts Description The general purpose provides individual control over each bidirectional port pin There are two registers to control I O direction and output level The inputs are synchronized to achieve stable read levels To generate an open drain output set the bit in the output register to the desired value Use the direction register to control the signal When set to output the output driver actively drives the value on the output when set to input the signal floats and can be pulled up internally or externally GPIO pin description The five GPIO ports in the LPC291 7 19 have the pins listed below The GPIO pins combined with other functions on the port pins of the LPC2917 19 Table 17 shows the GPIO pins Table 17 GPIO pins Symbol Direction Description
37. 2 57 GPIO 1 pin 10 SPI SDI EXTBUS CS2 P3 12 SCS1 O El4 58 GPIO3 pin 12 SPI SCSO EXTINT4 Vss CORE 59 ground for digital core VDD CORE 60 1 8 V power supply for digital core P3 13 SDO1 EI5 61 GPIO3 pin 13 SPH SDO EXTINT5 P2 4 MAT 1 O EIO D12 62 GPIO2 pin 4 TIMER1 MATO EXTINTO EXTBUS D12 P2 B MAT 1 1 EH D13 63 GPIO2 pind TIMER1 MAT1 EXTINT1 EXTBUS D13 P1 9 SDO1 RXDL 1 CS1 64 GPIO 1 ping SPH SDO LIN1 RXDL EXTBUS CS1 Vss 0 65 ground for I O P1 8 SCS1 O TXDL1 CSO 66 GPIO 1 pin 8 SPI SCSO LIN1 TXDL EXTBUS 50 P1 7 SCS1 S RXD1 A7 67 GPIO 1 pin 7 SPI SCS3 UART1 RXD EXTBUS A7 P1 6 SCS1 2 TXD1 A6 68 GPIO 1 pin 6 SPI SCS2 UART1 TXD EXTBUS A6 P2 6 MAT1 2 EI2 D14 69 GPIO2 pin 6 TIMER1 MAT2 EXTINT2 EXTBUS D14 P1 5 SCS1 1 PMAT3 5 A5 70 GPIO 1 pin 5 SPI1 SCS1 PWM3 5 EXTBUS A5 P1 4 SCS2 2 PMAT3 4 A4 71 GPIO 1 pin 4 SPI2 SCS2 PWMS3 EXTBUS A4 TRST N 72 IEEE 1149 1 test reset NOT active LOW pulled up internally RST N 73 asynchronous device reset active LOW pulled up internally Vss osc 74 ground for oscillator XOUT_OSC 75 crystal out for oscillator XIN_OSC 76 crystal in for oscillator 77 1 8 V supply for oscillator Vss PLL 78 ground for PLL P2 7 MAT1 S EI3 D15 79 GPIO 2 pin 7 TIMER1 EXTBUS D15 P3 14 J SDH EIG TXDCO 80 GPIO3 pin 14 SPI SDI 6 TXDC P3 15 SCK1 EI7 RXDCO 81 GPIO3 pin 15 SPI SCK EXTINT7 CANO RXDC 82 3 3 V power
38. 32 words deep Serial data is transmitted on SPI TXD and received SPI RXD The SPI module includes a programmable bit rate clock divider and prescaler to generate the SPI serial clock from the input clock CLK SPlx The SPI module s operating mode frame format and word size are programmed through the SLVn SETTINGS registers A single combined interrupt request SPI INTREQ output is asserted if any of the interrupts are asserted and unmasked NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 26 of 67 NXP Semiconductors LPC291 7 1 9 8 4 5 3 8 4 5 4 8 4 5 5 LPC2917 19 1 ARMS microcontroller with CAN and LIN Depending on the operating mode selected the SPI CS OUT outputs operate as an active HIGH frame synchronization output for Texas Instruments synchronous serial frame format or an active LOW chip select for SPI Each data frame is between four and 16 bits long depending on the size of words programmed and is transmitted starting with the MSB There are two basic frame types that can be selected Texas Instruments synchronous serial Motorola Serial Peripheral Interface Modes of operation The SPI module can operate in Master mode Normal transmission mode Sequential slave mode Slave mode SPI pin description The three SPI modules in the LPC2917 19 have the pins listed below The pins are combined with other functions on the port pins of the
39. 5 SPIO SDO PO 4 PMATO 2 D28 102 GPIOO pin 4 PWMO MAT2 EXTBUS D28 PO 5 PMATO 3 D29 103 GPIOO pin 5 PWMO MAT3 EXTBUS D29 104 3 3 V power supply for I O PO 6 PMATO 4 D30 105 GPIOO 6 PWMO EXTBUS D30 PO 7 PMATO 5 D31 106 GPIOO pin 7 PWMO 5 EXTBUS D31 VDDA ADC3V3 107 3 3 V power supply for ADC JTAGSEL 108 TAP controller select input LOW level selects the ARM debug mode HIGH level selects boundary scan and flash programming pulled up internally 109 not connected VREFP 110 HIGH reference for ADC VREFN 111 LOW reference for ADC PO 8 IN1 O TXDL 0 A20 112 GPIO 0 pin 8 ADC1 INO LINO TXDL EXTBUS A20 PO 9 IN1 1 RXDLO A21 113 GPIO 0 ping ADC1 IN1 LINO RXDL EXTBUS 21 PO 10 IN1 2 PMAT 1 0 A8 114 GPIO O pin 10 ADC1 IN2 PWM1 MATO EXTBUS A8 PO 11 IN1 3 PMAT1 1 A9 115 GPIOO pin 11 ADC1 IN3 PWM1 1 EXTBUS 9 P2 14 PCAPO O BLSO 116 GPIO 2 pin 14 PWMO CAPO EXTBUS BLSO P2 15 PCAPO 1 BLS1 117 GPIO 2 pin 15 PWMO CAP1 EXTBUS BLS1 2 2 2 118 GPIO 2 TIMER3 PWM2 2 Vss 10 119 ground for I O P3 3 MAT3 1 PMAT2 3 120 GPIO 3 pin 3 TIMER3 MAT1 PWM2 MAT3 PO 12 IN1 4 PMAT1 2 A10 121 GPIO 0 pin 12 ADC1 IN4 PWM 1 2 EXTBUS A10 PO 13 IN1 5 PMAT 1 3J A1 1 122 GPIOO 13 ADC1 IN5 PWM1 EXTBUS A11 PO 14 IN1 6 PMAT 1 4 A12 123 GPIO 0 pin 14 ADC1 IN6 1 EXTBUS 12 PO 15 IN1 7 PMAT1 5 A13 124
40. 7 19 1 Min Max Unit 1 W 0 5 2 0 V 0 5 42 0 V 0 5 44 6 V 0 5 446 V 98 Ba 98 mA 0 5 2 0 BIAB 0 5 Vpp o 3 0 V 15 0 5 VDDA ADC3V3 V 4 0 5 0 5 13 6 V 0 5 13 6 V B 35 mA 9 33 mA 9 38 40 150 C 40 85 C 6 40 4125 100000 20 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 51 of 67 NXP Semiconductors LPC291 7 1 9 ARMS microcontroller with CAN and LIN Table 28 Limiting values continued In accordance with the Absolute Maximum Rating System IEC 60134 Symbol Parameter Conditions Min Max Unit ESD Vesd electrostatic discharge on all pins voltage human body model U 2000 2000 V machine model 81 200 200 charged device model 500 500 V on corner pins charged device model 750 750 V 1 2 3 4 5 6 7 8 9 Based on package heat transfer not device power consumption Peak current must be limited at 25 times average current For I O Port 0 the maximum input voltage is defined by Vipc Only when Vpp oy is present Note that pull up should be off With pull up do not exceed 3 6 V In accordance with 60747 1 An alternative definition of the virtual junction temperature is Tyj Tamb Ptot where Rinj a is a fixed value see Section 10 The rating for Ty limits the allowable combinations of power dissipation and
41. ADC2 IN6 2 EXTBUS A18 Vss 0 141 ground for I O PO 23 IN2 7 PMAT2 5 A19 142 GPIO 0 pin 23 ADC2 IN7 PWM2 5 EXTBUS A19 P2 20 PCAP2 O D18 143 GPIO 2 pin 20 2 CAPO EXTBUS D18 TDI 144 IEEE 1149 1 data in pulled up internally 7 Functional description 7 1 7 1 1 Reset debug test and power description Reset and power up behavior The LPC2917 19 contains external reset input and internal power up reset circuits This ensures that a reset is extended internally until the oscillators and flash have reached a stable state See Section 11 for trip levels of the internal power up reset circuit See Section 12 for characteristics of the several start up and initialization times Table 4 shows the reset pin Table 4 Reset pin Symbol Direction Description RST N IN external reset input active LOW pulled up internally At activation of the RST_N pin the JTAGSEL pin is sensed as logic LOW If this is the case the LPC2917 19 is assumed to be connected to debug hardware and internal circuits reprogram the source for the BASE SYS CLK to be the crystal oscillator instead of the Low Power Ring Oscillator LP OSC This is required because the clock rate when running at LP OSC speed is too low for the external debugging environment Reset strategy The LPC2917 19 contains a central module the Reset Generation Unit RGU in the Power Clock and Reset SubSystem PCRSS which controls all internal reset
42. GPIOO pin 15 ADC1 IN7 PWM1 5 EXTBUS A13 PO 16 IN2 0 TXDO0 A22 125 GPIO 0 pin 16 ADC2 INO UARTO TXD EXTBUS A22 PO 17 IN2 1 RXD0 A23 126 GPIOO pin 17 ADC2 IN1 UARTO RXD EXTBUS A23 VDD CORE 127 1 8 V power supply for digital core VSS CORE 128 ground for digital core P2 16 TXD1 PCAPO 2 BLS2 129 GPIO 2 pin 16 UART1 TXD PWMO CAP2 EXTBUS BLS2 LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 9 of 67 NXP Semiconductors LPC2917 19 ARMS microcontroller with CAN and LIN Table 3 LQFP144 pin assignment continued Pin name Pin Description Default function Function 1 Function 2 Function 3 P2 17 RXD1 PCAP1 0 BLS3 130 GPIO 2 pin 17 UART1 RXD PWM1 CAPO EXTBUS BLS3 VpD O 131 3 3 V power supply for I O PO 18 IN2 2 PMAT2 O A14 132 GPIOO pin 18 ADC2 IN2 PWM2 MATO EXTBUS A14 19 1 2 3 2 1 15 133 GPIO 0 pin 19 ADC2 IN3 2 MAT1 EXTBUS A15 P3 4 MAT3 2 PMAT2 4 TXDC 1 134 GPIO3 pin 4 TIMER3 MAT2 2 CAN1 TXDC P3 B MAT3 S PMAT2 B RXDC 1 135 GPIO3 pin 5 TIMER3 PWM2 MAT5 CAN1 RXDC P2 18 PCAP1 1 D16 136 GPIO 2 pin 18 PWM 1 CAP1 EXTBUS D16 P2 19 PCAP1 2 D17 137 GPIO 2 pin 19 PWM1 2 EXTBUS D17 PO 20 IN2 4 J PMAT2 2 A16 138 GPIO 0 pin 20 ADC2 IN4 PWM2 MAT2 EXTBUS A16 PO 21 IN2 5 PMAT2 3 A17 139 GPIOO 21 ADC2 IN5 PWM2 EXTBUS A17 PO 22 IN2 6 PMAT2 4 A18 140 GPIO 0 22
43. LPC2917 19 see Section 8 3 3 Table 16 shows the SPI pins x runs from 0 to 2 y runs from 0 to 3 Table 16 SPI pins Symbol Direction Description SCSy IN OUT SPIx chip selectHl2 SPIx SCK IN OUT SPIx clock SPIx SDI IN SPIx data input SPIx SDO OUT SPIx data output 1 Direction of SPIx SCS and SPIx SCK pins depends on master or slave mode These pins are output in master mode input in slave mode 2 slave mode there is only one chip select input pin SPIx SCSO The other chip selects have no function in slave mode SPI clock description The SPI modules are clocked by two different clocks CLK SYS PESS and CLK_SPIx x 0 2 see Section 7 2 2 Note that each SPI has its own CLK_SPIx branch clock for power management The frequency of all clocks CLK SPlx is identical as they are derived from the same base clock BASE CLK SPI The register interface towards the system bus is clocked by CLK SYS PESS The serial clock rate divisor is clocked by CLK_SPIx The SPI clock frequency can be controlled by the CGU In master mode the SPI clock frequency CLK_SPIx must be set to at least twice the SPI serial clock rate on the interface In slave mode CLK_SPIx must be set to four times the SPI serial clock rate on the interface NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 27 of 67 NXP Semiconductors LPC291 7 1 9 8 4 6 8 4 6 1 8 4 6 2 8 4 6 3 8 4 6 4 LPC29
44. N and LIN 8 7 7 2 Description See section Section 8 4 3 2 for a description of the timers 8 7 7 3 MSCSS timer pin description MSCSS timer 0 has no external pins MSCSS timer 1 has a PAUSE pin available as external pin The PAUSE pin is combined with other functions on the port pins of the LPC2917 19 Table 22 shows the MSCSS timer 1 external pin Table 22 MSCSS timer 1 pin Symbol Direction Description MSCSS PAUSE IN pause pin for MSCSS timer 1 8 7 7 4 MSCSS timer clock description The Timer modules in the MSCSS clocked by CLK_MSCSS_MTMRx x 0 1 see Section 7 2 2 Note that each timer has its own MSCSS MTMRx branch clock for power management The frequency of all these clocks is identical to MSCSS since they are derived from the same base clock BASE MSCSS Note that unlike the timer modules in the Peripheral SubSystem the actual timer counter registers run at the same clock as the system interface CLK MSCSS This clock is independent of the AHB system clock If a timer module is not used its MSCSS MTMRx branch clock can be switched off 8 8 Power clock and reset control subsystem 8 8 1 Overview The Power Clock and Reset Control Subsystem PCRSS in the LPC2917 19 includes a Clock Generation Unit CGU a Reset Generation Unit RGU and a Power Management Unit PMU 8 8 2 Description Figure 11 provides an overview of the PCRSS An AHB to DTL bridge takes
45. O 1 MATO 1 EI5 20 GPIO1 pin 31 TIMERO CAP1 TIMERO 1 EXTINT5 Vss 10 21 ground for I O 1 0 0 14 22 GPIO 1 pin 30 TIMERO CAPO TIMERO MATO EXTINT4 P3 8 SCS2 0 PMAT 1 2 23 GPIO3 pin8 SPI2 SCSO PWM1 MAT2 P3 9 SDO2 PMAT1 3 24 GPIO3 pin 9 SPI2 SDO PWM 1 P1 29 CAP1 0 TRAPO 25 GPIO 1 pin 29 TIMER1 CAPO PWM TRAPO MAT5 5 EXT START P1 28 CAP1 1 TRAP1 26 GPIO 1 pin 28 TIMER1 1 PWM TRAP1 PWMs3 MAT4 PMAT3 4 ADC1 EXT START P2 26 CAPO 2 MATO 2 El6 27 GPIO 2 pin 26 TIMERO CAP2 TIMERO MAT2 6 P2 27 CAPO S MATO S EI7 28 GPIO 2 pin 27 TIMERO TIMERO MAT3 EXTINT7 P1 27 CAP1 2 TRAP2 29 GPIO 1 pin 27 TIMER1 CAP2 PWM TRAP2 PWMS PMAT3 S3 ADC2 EXT START P1 26 PMAT2 0 TRAP3 30 GPIO 1 pin 26 PWM2 MATO PWM TRAP3 MAT2 PMAT3 2 31 V power supply for I O 1 25 1 0 1 32 GPIO 1 pin 25 PWM 1 PWMS3 MAT1 P1 24 J PMATO O PMAT3 0 33 GPIO 1 pin 24 PWMO MATO PWM3 P1 23J RXDO CS5 34 GPIO 1 pin 23 UARTO RXD EXTBUS CS5 P1 22 TXDO CS4 35 GPIO 1 pin 22 UARTO TXD EXTBUS 54 TMS 36 IEEE 1149 1 test mode select pulled up internally TCK 37 IEEE 1149 1 test clock P1 21 CAP3 3 CAP1 3 D7 38 GPIO 1 pin 21 TIMER3 TIMER1 CAP3 EXTBUS D7 MSCSS PAUSE P1 20 CAPS 2 SCSO 1 D6 39 GPIO 1 pin 20 TIMER3 2 SPIO SCS1 EXTBUS D6 P1 19J CAPS3 1 SCSO 2 D5 40 GPI
46. O 1 pin 19 TIMERS3 CAP1 SPIO SCS2 EXTBUS D5 1 18 0 5000 04 41 1 pin 18 TIMER3 CAPO SPIO SDO EXTBUS D4 1 17 2 3 5010 03 42 GPIO 1 17 2 SPIO SDI EXTBUS D3 Vss 10 43 ground for I O P1 16 CAP2 2 SCK0 D2 44 GPIO 1 pin 16 TIMER2 CAP2 SPIO SCK EXTBUS D2 P2 O MAT2 O TRAPS3 D8 45 GPIO 2 pind TIMER2 MATO PWM TRAP3 EXTBUS D8 P2 1 MAT2 1 TRAP2 D9 46 GPIO 2 pin 1 TIMER2 1 PWM TRAP2 EXTBUS D9 P3 10 SDI2 PMAT 1 4 47 GPIOGS pin 10 SPI2 SDI 1 11 5 2 1 5 48 11 SPI2 SCK PWM 1 5 P1 15J CAP2 1 SCSO O D1 49 GPIO 1 pin 15 TIMER2 CAP1 SPIO SCSO EXTBUS D1 P1 14 J CAP2 0 SCSO S DO 50 GPIO 1 pin 14 TIMER2 CAPO SPIO SCS3 EXTBUS DO LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 7 of 67 NXP Semiconductors LPC2917 19 ARMS microcontroller with CAN and LIN Table 3 LQFP144 pin assignment continued Pin name Pin Description Default function Function 1 Function 2 Function 3 P1 13J EI3 WE 51 GPIO 1 pin 13 EXTBUS WE P1 12 El2 OE_N 52 GPIO 1 pin 12 EXTINT2 EXTBUS OE_N 53 3 3 V power supply for I O P2 2 MAT2 2 TRAP 1 D10 54 GPIO 2 pin 2 TIMER2 MAT2 PWM TRAP1 EXTBUS D10 P2 3 MAT2 3 TRAPO D11 55 GPIO 2 pin 3 TIMER2 PWM TRAPO EXTBUS D11 P1 11 SCK1 CS3 56 1 11 SPI1 SCK EXTBUS CS3 P1 10 J SDH CS
47. PWM modules within the MSCSS in the LPC2917 19 PWM 0 can be master over PWM 1 PWM 1 can be master over PWM 2 etc NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 37 of 67 NXP Semiconductors LPC291 7 1 9 8 7 6 4 8 7 6 5 8 7 6 6 8 7 7 8 7 7 1 LPC2917 19 1 ARMS microcontroller with CAN and LIN Master and slave mode A PWM module can provide synchronization signals to other modules also called Master mode The signal sync out is a pulse of one clock cycle generated when the internal PWM counter re starts The signal trans enable out is a pulse synchronous to sync out generated if a transfer from system registers to PWM shadow registers occurred when the PWM counter restarted A delay may be inserted between the counter start and generation of trans enable out and sync out A PWM module can use input signals trans enable in and sync in to synchronize its internal PWM counter and the transfer of shadow registers Slave mode PWM pin description Each of the four PWM modules in the MSCSS has the following pins These are combined with other functions on the port pins of the LPC2917 19 Table 21 shows the PWMO to PWMsB pins Table 21 PWM pins Symbol Direction Description 0 IN PWM n capture input 0 PWMn PWM n capture input 1 PWMn 2 IN PWM n capture input 2 PWMn 0 OUT PWM n match output 0 PWMn 1 OUT PWM n mat
48. S CLK BASE MSCSS CLK Branch clock name CLK SAFE CLK SYS CPU CLK SYS SYS CLK SYS PCRSS CLK SYS FMC CLK SYS RAMO CLK SYS 1 CLK SYS SMC CLK SYS GESS CLK SYS VIC CLK SYS PESS CLK SYS GPIOO CLK_SYS_GPIO1 SYS 2 CLK SYS SYS IVNSS CLK PCR SLOW CLK IVNSS APB CLK IVNSS CANCA CLK IVNSS CANCO CLK IVNSS CANC1 CLK IVNSS LINO IVNSS LIN1 CLK MSCSS APB CLK MSCSS MTMRO CLK MSCSS 1 CLK MSCSS PWMO CLK MSCSS PWM 1 CLK MSCSS PWM2 CLK MSCSS PWM3 CLK MSCSS ADC1 PB CLK MSCSS ADC2 A PB Parts of the device clocked by Remark this branch clock watchdog timer ARM968E S TCMs AHB bus infrastructure AHB side of bridge in PCRSS Flash Memory Controller Embedded SRAM Controller 0 32 kB Embedded SRAM Controller 1 16 kB External Static Memory Controller General Subsystem Vectored Interrupt Controller x Peripheral Subsystem GPIO bank 0 GPIO bank 1 GPIO bank 2 GPIO bank 3 AHB side of bridge of IVNSS PCRSS CGU RGU and PMU logic clock APB side of the IVNSS CAN controller Acceptance Filter CAN channel 0 CAN channel 1 LIN channel 0 LIN channel 1 APB side of the MSCSS Timer 0 in the MSCSS Timer 1 in the MSCSS PWM 0 PWM 0 PWM 0 PWM 0 APB side of ADC 1 APB side of ADC 2 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 13 of 67 NXP Semiconductors LPC291 7 1 9
49. TL MEMORY SYS_CLK gt CONTROLLER C C C SUBSYSTEM RESET CLOCK GENERATION AHB TO DTL AHB TO APB POR Rowen SYSTEM CONTROL TS AHB TO APB BRIDGE C AHB TO APB BRIDGE 40v MSCSS CLK TIMERO 1 MTMR C 5 EIN GENERAL PURPOSE 1 0 2 3 TIMER 0 1 2 3 TMR CLK 5 0 1 2 SPI CLK UARTO 1 UART CLK WDT SAFE CLK GLOBAL ACCEPTANCE FILTER 002aad839 Fig 3 LPC2917 19 block diagram overview of clock areas 7 2 2 Base clock and branch clock relationship The next table contains an overview of all the base blocks in the LPC2917 19 and their derived branch clocks A short description is given of the hardware parts that are clocked with the individual branch clocks In relevant cases more detailed information can be NXP B V 2008 All rights reserved LPC2917 19 1 Product data sheet Rev 01 31 July 2008 12 of 67 NXP Semiconductors LPC2917 19 LPC2917 19 1 ARMS microcontroller with CAN and LIN found in the specific subsystem description Some branch clocks have special protection since they clock vital system parts of the device and should for example not be switched off See Section 8 8 6 for more details of how to control the individual branch clocks Table 7 Base clock and branch clock overview Base clock BASE SAFE CLK BASE SYS CLK BASE PCR CLK BASE IVNS
50. ad838 Fig 9 ADC block diagram 8 7 5 3 ADC pin description The two ADC modules in the MSCSS have the pins described below The ADCx input pins are combined with other functions on the port pins of the LPC2917 19 The VREFN and VREFP pins are common for both ADCs Table 20 shows the ADC pins Table 20 Analog to digital converter pins Symbol Direction Description ADOn IN 7 0 IN analog input for ADCn channel 7 to channel 0 n is 1 or 2 ADCn EXT START ADC external start trigger input n is 1 or 2 VREFN IN ADC LOW reference level VREFP IN ADC HIGH reference level 8 7 5 4 ADC clock description The ADC modules are clocked from two different sources MSCSS ADOx and CLK_ADCx x 1 or 2 see Section 7 2 2 Note that each ADC has its own CLK ADCx and MSCSS ADOx branch clocks for power management If an ADC is unused both its CLK MSCSS ADOx APB and CLK ADOx can be switched off LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 35 of 67 NXP Semiconductors LPC291 7 1 9 8 7 6 8 7 6 1 8 7 6 2 LPC2917 19 1 ARMS microcontroller with CAN and LIN The frequency of all the MSCSS ADOx clocks is identical to CLK MSCSS APB since they are derived from the same base clock BASE MSCSS Likewise the frequency of all the CLK ADOx clocks is identical since they are derived from the same base clock BASE
51. ambient temperature Human body model discharging a 100 pF capacitor via a 10 kO series resistor Machine model discharging a 200 pF capacitor via a 0 75 uH series inductance and 10 Q resistor 112 mA per or should not be exceeded 10 Thermal characteristics Table 29 Thermal characteristics Symbol Parameter Conditions Value Unit Fih j a thermal resistance from free air junction to ambient package LQFP144 62 K W LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 52 of 67 NXP Semiconductors LPC2917 19 11 Static characteristics Table 30 Static characteristics ARMS microcontroller with CAN and LIN VDD CORE Vpp osc PLL E Vpp o 2 7 03 6 VDDA ADC3V3 3 0Vt03 6V 40 to 125 all voltages are measured with respect ground positive currents flow into the IC unless otherwise specified Symbol Parameter Supplies Core supply VDD CORE core supply voltage IDD CORE core supply current supply Vpb o supply voltage Oscillator supply Vpp osc PLL oscillator and PLL supply voltage PL oscillator and PLL supply current Analog to digital converter supply Vppa pcavs 3 3 V ADC analog supply voltage 3 3 V ADC analog supply current IDDA ADC3V3 Conditions ARM9 and all peripherals active at max clock speeds all clocks off start up normal mode Power down
52. bedded Flash Memory Controller FMC EMC RST COLD RST embedded SRAM Memory Controller SMC RST COLD RST external Static Memory Controller SMC GESS A2V RST WARM RST GeSS AHB to APB bridge PESS A2V RST WARM RST PeSS AHB to APB bridge GPIO RST WARM RST all GPIO modules UART WARM RST all UART modules TMR RST WARM RST all Timer modules in PeSS SPI RST WARM RST all SPI modules IVNSS A2V RST WARM RST IVNSS AHB to APB bridge IVNSS CAN RST WARM RST all CAN modules including Acceptance filter IVNSS LIN RST WARM RST all LIN modules MSCSS A2V RST WARM MSCSS AHB to APB bridge MSCSS RST WARM_RST all PWM modules MSCSS ADC RST WARM_RST all ADC modules MSCSS WARM all Timer modules MSCSS VIC RST WARM RST Vectored Interrupt Controller VIC AHB RST WARM RST CPU and AHB Bus infrastructure RGU pin description The RGU module in the LPC2917 19 has the following pins Table 26 shows the RGU pins Table 26 RGU pins Symbol Direction Description RST N IN external reset input active LOW pulled up internally Power Management Unit PMU Overview This module enables software to actively control the system s power consumption by disabling clocks not required in a particular operating mode Using the base clocks from the CGU as input the PMU generates branch clocks to the rest of the LPC2917 19 Output clocks branched from the same base clock are phase and frequency related These branc
53. ch output 1 PWMn 2 OUT PWM n match output 2 PWMn 3 OUT PWM n match output 3 PWMn MAT 4 OUT PWM n match output 4 PWMn 5 OUT PWM n match output 5 PWMn TRAP IN PWM n trap input PWM clock description The PWM modules are clocked by MSCSS PWMXx x 0 3 see Section 7 2 2 Note that each PWM has its own CLK MSCSS PWMXx branch clock for power management The frequency of all these clocks is identical to MSCSS since they are derived from the same base clock BASE MSCSS Also note that unlike the timer modules in the Peripheral SubSystem the actual timer counter registers of the PWM modules run at the same clock as the APB system interface CLK MSCSS APB This clock is independent of the AHB system clock If a PWM module is not used its MSCSS PWMXx branch clock can be switched off Timers in the MSCSS Overview The two timers in the MSCSS are functionally identical to the timers in the peripheral subsystem see Section 8 4 3 The features of the timers in the MSCSS are the same as the timers in the peripheral subsystem but the capture inputs and match outputs are not available on the device pins These signals are instead connected to the ADC and PWM modules as outlined in the description of the MSCSS see Section 8 7 2 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 38 of 67 NXP Semiconductors LPC291 7 1 9 ARMS microcontroller with CA
54. ck generators according to Figure 13 LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 42 of 67 NXP Semiconductors LPC291 7 1 9 LPC2917 19 1 ARMS microcontroller with CAN and LIN d gt EXTERNAL OSCILLATOR 7 FDIVO 6 clkout clkout120 clkout240 Mil OUTPUT CONTROL clock outputs 002aad834 Fig 13 Structure of the clock generation scheme Any output generator except for BASE SAFE CLK and BASE PCR CLK can be connected to either a fractional divider FDIVO 6 or to one of the outputs of the PLL or to OSC crystal oscillator directly BASE SAFE CLK and BASE PCR CLK can use only LP OSC as source The fractional dividers can be connected to one of the outputs of the PLL or directly to OSC crystal Oscillator The PLL can be connected to the crystal oscillator In this way every output generating the base clocks can be configured to get the required clock Multiple output generators can be connected to the same primary or secondary clock source and multiple secondary clock sources can be connected to the same PLL output or primary clock source Invalid selections programming connecting the PLL to an FDIV or to one of the PLL outputs itself for example will be blocked by hardware The control register will not be written the previous value will be kept although all other fields wil
55. corresponding bit position in the event router registers and the default polarity Table 13 Event router pin connections Symbol EXTINTO EXTINT1 EXTINT2 EXTINT3 EXTINT4 EXTINT5 EXTINT6 EXTINT7 CANO RXDC CAN1 RXDC LINO RXDL LIN1 RXDL Direction na na na Bit position 01 9 13 to 10 14 15 21 to 16 22 23 24 26 to 25 Description external interrupt input O external interrupt input 1 external interrupt input 2 external interrupt input 3 external interrupt input 4 external interrupt input 5 external interrupt input 6 external interrupt input 7 CANO receive data input wake up CAN1 receive data input wake up reserved LINO receive data input wake up LIN1 receive data input wake up reserved CAN interrupt internal VIC FIQ internal VIC IRQ internal reserved Default polarity O O a oa 1 1 Peripheral subsystem Peripheral subsystem clock description The peripheral subsystem is clocked by a number of different clocks e CLK_SYS_PESS NXP 2008 All rights reserved Product data sheet Rev 01 31 July 2008 22 of 67 NXP Semiconductors LPC291 7 1 9 8 4 2 8 4 2 1 8 4 2 2 8 4 2 3 8 4 2 4 LPC2917 19 1 ARMS microcontroller with CAN and LIN CLK UARTO 1 e SPIO 1 2 e 0 1 2 3 CLK SAFE see Section 7 2 2 Watchdog timer Overview The purpose of
56. d LIN 1 Indicates that the related register bit is tied off to logic HIGH all writes are ignored 0 Indicates that the related register bit is tied off to logic LOW all writes are ignored Indicates that the related register bit is readable and writable Branch clock name CLK SYS VIC CLK SYS PESS CLK SYS GPIOO CLK SYS GPIO1 CLK SYS GPIO2 CLK SYS CLK SYS IVNSS A CLK SYS MSCSS A CLK SYS CHCA CLK SYS CHCB CLK PCR SLOW CLK IVNSS APB IVNSS CANCO IVNSS CANC CLK IVNSS LINO CLK IVNSS CLK MSCSS APB CLK MSCSS MTMRO CLK MSCSS MTMHR1 CLK MSCSS PWMO MSCSS PWM 1 CLK MSCSS PWM2 CLK MSCSS PWM3 CLK MSCSS ADC1 CLK MSCSS ADC2 APB CLK UARTO UART1 CLK SPIO CLK SPI CLK SPI2 CLK TMRO CLK TMR1 CLK TMR2 CLK TMR3 Base clock BASE SYS CLK BASE SYS CLK BASE SYS CLK BASE SYS CLK BASE SYS CLK BASE SYS CLK BASE SYS CLK BASE SYS CLK BASE SYS CLK BASE SYS CLK BASE PCR CLK BASE IVNSS CLK BASE IVNSS CLK BASE IVNSS CLK BASE IVNSS CLK BASE IVNSS CLK BASE MSCSS CLK BASE MSCSS CLK BASE MSCSS CLK BASE MSCSS CLK BASE MSCSS CLK BASE MSCSS CLK BASE MSCSS CLK BASE MSCSS CLK BASE MSCSS CLK BASE UART CLK BASE UART CLK BASE SPI CLK BASE SPI CLK BASE SPI CLK BASE TMR CLK BASE TMR CLK BASE TMR CLK BASE TMR CLK Implemented switch on off mechanism WAKE UP AUTO
57. d slave mode PWM pin description PWM clock Timers in the 5 55 Overview Lid eode dope MSCSS timer pin description MSCSS timer clock description Power clock and reset control subsystem 2 2 522 2 2 2 PCR subsystem clock description Clock Generation Unit CGU OvervieW 0 2 cece PLL functional description CGU pin Reset Generation Unit RGU RGU Power Management Unit PMU OvervieW cece le E ERE RES Description us cuir mre PMU pin Vectored interrupt controller OvervieW locos es ro ER RE CREE VIC pin VIC clock description Limiting Thermal characteristics Static characteristics Dynamic characteristics founded by 13 14 14 1
58. detected normally only one BASE PCR CLK cycle is needed to detect activity After reset all clocks are assumed to be non present so the status register will be correct only after 32 BASE PCR CLK cycles Note that this mechanism cannot protect against a currently selected clock going from active to inactive state Therefore an inactive clock may still be sent to the system under special circumstances although an interrupt can still be generated to notify the system Glitch Free Switching Provisions are included in the CGU to allow clocks to be switched glitch free both at the output generator stage and also at secondary source generators In the case of the PLL the clock will be stopped and held low for long enough to allow the PLL to stabilize and lock before being re enabled For all non PLL Generators the switch will occur as quickly as possible although there will always be a period when the clock is held low due to synchronization requirements If the current clock is high and does not go low within 32 cycles of BASE PCR CLK it is assumed to be inactive and is asynchronously forced low This prevents deadlocks on the interface PLL functional description A block diagram of the PLL is shown in Figure 14 The input clock is fed directly to the analog section This block compares the phase and frequency of the inputs and generates the main clock These clocks are either divided by 2 P by the programmable post divider to create
59. e Supports static memory mapped devices including RAM ROM flash burst ROM and external devices NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 17 of 67 NXP Semiconductors LPC291 7 1 9 ARMS microcontroller with CAN and LIN Asynchronous page mode read operation in non clocked memory subsystems Asynchronous burst mode read access to burst mode ROM devices Independent configuration for up to eight banks each up to 16 MB Programmable bus turnaround idle cycles one to 16 Programmable read and write wait states up to 32 for static RAM devices e Programmable initial and subsequent burst read wait state for burst ROM devices Programmable write protection Programmable burst mode operation Programmable external data width 8 bits 16 bits or 32 bits Programmable read byte lane enable control 8 2 2 Description LPC2917 19 1 The SMC simultaneously supports up to eight independently configurable memory banks Each memory bank can be 8 bits 16 bits or 32 bits wide and is capable of supporting SRAM ROM burst ROM memory or external I O devices A separate chip select output is available for each bank The chip select lines are configurable to be active HIGH or LOW Memory bank selection is controlled by memory addressing Table 10 shows how the 32 bit system address is mapped to the external bus memory base addresses chip selects and bank internal addres
60. ector size kB Sector base address 11 64 0004 0000h 12 64 0005 0000h 13 64 0006 0000h 14 64 0007 0000h 15 64 0008 0000h 1611 64 0009 0000h 1701 64 000A 0000h 1811 64 000B 0000h 1 Availability of sector 15 to sector 18 depends on device type see Section 4 Ordering information The index sector is a special sector in which the JTAG access protection and sector security are located The address space becomes visible by setting the FS 155 bit and overlaps the regular flash sector s address space Note that the index sector cannot be erased and that access to it has to be performed via code outside the flash Flash bridge wait states To eliminate the delay associated with synchronizing flash read data a predefined number of wait states must be programmed These depend on flash memory response time and system clock period The minimum wait states value can be calculated with the following formulas Synchronous reading WST gt 146010 _ 1 T ielk sys Asynchronous reading lacc addr t WST gt 1 2 tclk sys Remark If the programmed number of wait states is more than three flash data reading cannot be performed at full speed i e with zero wait states at the AHB bus if speculative reading is active External static memory controller Overview The LPC2917 19 contains an external Static Memory Controller SMC which provides an interface for external off chip memory devices Key features ar
61. ed Vpp cong must be below Vtrip ow for 11 us before internal reset is asserted 7 Not 5 V tolerant when pull up is on 8 For I O Port 0 the maximum input voltage is defined by Vipc 9 This parameter is not part of production testing or final testing hence only a typical value is stated Maximum and minimum values are based on simulation results LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 55 of 67 NXP Semiconductors LPC291 7 1 9 ARMS microcontroller with CAN and LIN 12 Dynamic characteristics Table 31 Dynamic characteristics Vpp coRE Vpp osc 2 7 V to 3 6 V Vppa apcava 3 0 V to 3 6 V 409 all voltages are measured with respect to ground positive currents flow into the IC unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit pins HIGH to LOW C 30 pF 4 13 8 ns transition time tru LOW to HIGH C 30 pF 4 13 8 ns transition time Internal clock folk sys system clock frequency 2 10 E 80 MHz Tolk sys system clock period 2 12 5 100 Low power ring oscillator fref RO RO reference 0 36 0 4 0 42 MHz frequency tstartup start up time at maximum frequency B 6 100 us Oscillator fitosc oscillator input maximum frequency is 10 80 MHz frequency the clock input of an external clock source applied to the Xin pin tstartup start up time at maximum frequency
62. ee Section 7 1 3 Flash memory controller clock description The flash memory controller is clocked by CLK SYS see Section 7 2 2 Flash layout The ARM processor can program the flash for ISP In System Programming and IAP In Application Programming Note that the flash always has to be programmed by flash words of 128 bits four 32 bit AHB bus words hence 16 bytes The flash memory is organized into eight small sectors of 8 kB each and up to 11 large sectors of 64 kB each The number of large sectors depends on the device type A sector must be erased before data can be written to it The flash memory also has sector wise protection Writing occurs per page which consists of 4096 bits 32 flash words A small sector contains 16 pages a large sector contains 128 pages Table 9 gives an overview of the flash sector base addresses Table 9 Flash sector overview Sector number Sector size kB Sector base address 0000 0000h 0000 2000h 0000 4000h 0000 6000h 0000 8000h 0000 A000h 0000 000 0000 E000h 0001 0000h 0002 0000h 0003 0000h o A DON Oo c1 WD o o o o NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 16 of 67 NXP Semiconductors LPC291 7 1 9 8 1 6 8 2 8 2 1 LPC2917 19 1 ARMS microcontroller with CAN and LIN Table 9 Flash sector overview continued Sector number S
63. ey features of the Reset Generation Unit RGU are Reset controlled individually per subsystem Automatic reset stretching and release Monitor function to trace resets back to source Register write protection mechanism to prevent unintentional resets Description The RGU controls all internal resets Each reset output is defined as a combination of reset input sources including the external reset input pins and internal power on reset see Table 25 The first five resets listed in this table form a sort of cascade to provide the multiple levels of impact that a reset may have The combined input sources are logically OR ed together so that activating any of the listed reset sources causes the output to go active NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 45 of 67 Semiconductors 2917 19 8 8 5 3 8 8 6 8 8 6 1 LPC2917 19 1 ARMS microcontroller with CAN and LIN Table 25 Reset output configuration Reset output Reset source Parts of the device reset when activated POR RST power on reset module LP_OSC is source for RGU RST POR RST RST N pin RGU internal is source for RST PCR RST RST WATCHDOG internal is source for COLD RST COLD RST PCR RST parts with COLD RST as reset source below WARM RST COLD RST parts with WARM RST as reset source below SCU RST COLD RST SCU CFID RST COLD RST CFID FMC RST COLD RST em
64. flash memory system The LPC2917 19 includes a 512 kB or 768 kB flash memory system This memory can be used for both code and data storage Programming of the flash memory can be accomplished in several ways It may be programmed in system via a serial port e g CAN NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 2 of 67 NXP Semiconductors LPC291 7 1 9 ARMS microcontroller with CAN and LIN 2 4 On chip static RAM 3 Features LPC2917 19 1 3 1 In addition to the two 16 TCMs the LPC291 7 19 includes two static RAM memories one of 32 kB and one of 16 Both may be used for code and or data storage General ARM968E S processor at 80 MHz maximum B AHB system bus at 80 MHz On chip memory Two Tightly Coupled Memories 16 kB Instruction ITCM 16 kB Data DTCM Two separate internal SRAM instances 32 kB and 16 kB Up to 768 kB flash program memory B Two channel CAN controller supporting Full CAN and extensive message filtering B Two LIN master controllers with full hardware support for LIN communication Two 550 UARTs with 16 byte TX and RX FIFO depths Three full duplex queued SPs with four slave select lines 16 bits wide 8 locations deep TX FIFO and RX FIFO Four 32 bit timers each containing four capture and compare registers linked to I Os E Four 6 channel PWMs with capture trap functionality
65. h CAN and LIN Each ADC module has four start inputs An ADC conversion is started when one of the start ADC conditions is valid Start 0 ADC external start input pin can be triggered at a positive or negative edge Note that this signal is captured in the ADC clock domain e Start 1 If the preceding ADC conversion is ended the sync out signal starts an ADC conversion This signal is captured in the MSCSS subsystem clock domain see Section 8 7 5 2 As can be seen in Figure 8 the sync out of ADC1 is connected to the start 1 input of ADC2 and the sync out of ADC2 is connected to the start 1 input of ADC1 e Start 2 The PWM sync out can start an ADC conversion The sync out signal is synchronized to the ADC clock in the ADC module This signal is captured in the MSCSS subsystem clock domain Start 3 The match outputs from MSCSS timer 0 are connected to the start 3 inputs of the ADCs This signal is captured in the ADC clock domain The PWM sync and trans enable in of PWM 0 are connected to the 4th match output of MSCSS timer 0 to start the PWM after a pre programmed delay This sync signal is cascaded through all PWMs allowing a programmable delay offset between subsequent PWMs The sync delay of each PWM can be programmed synchronously or with a different phase for spreading the power load The match outputs of MSCSS timer 1 PWM control are connected to the corresponding carrier inputs of the PWM modules The carrier sig
66. h clocks can be individually controlled by software programming NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 46 of 67 NXP Semiconductors LPC2917 19 ARMS microcontroller with CAN and LIN The key features are Individual clock control for all LPC2917 19 sub modules Activates sleeping clocks when a wake up event is detected Clocks can be individually disabled by software e Supports AHB master disable protocol when AUTO mode is set Disables wake up of enabled clocks when Power down mode is set Activates wake up of enabled clocks when a wake up event is received Status register is available to indicate if an input base clock can be safely switched off i e all branch clocks are disabled 8 8 6 2 Description LPC2917 19 1 The PMU controls all internal clocks of the device for power mode management With some exceptions each branch clock can be switched on or off individually under control of software register bits located in its individual configuration register Some branch clocks controlling vital parts of the device operate in a fixed mode Table 27 shows which mode control bits are supported by each branch clock By programming the configuration register the user can control which clocks are switched on or off and which clocks are switched off when entering Power down mode Note that the standby wait for interrupt instructions of the ARM968E S processor p
67. he LPC2917 19 configures the ARM968E S processor in little endian byte order All peripherals run at their own clock frequency to optimize the total system power consumption The AHB2APB bridge used in the subsystems contains a write ahead buffer one transaction deep This implies that when the ARM968E S issues a buffered write action to a register located on the APB side of the bridge it continues even though the actual write may not yet have taken place Completion of a second write to the same subsystem will not be executed until the first write is finished founded by Philips NXP Semiconductors LPC291 7 1 9 LPC2917 19 1 2 2 2 3 ARMS microcontroller with and LIN ARM968E S processor The ARM968E S is a general purpose 32 bit RISC processor which offers high performance and very low power consumption The ARM architecture is based on RISC principles and the instruction set and related decode mechanism are much simpler than those of microprogrammed CISC This simplicity results in a high instruction throughput and impressive real time interrupt response from a small and cost effective controller core Amongst the most compelling features of the ARM968E S are Separate directly connected instruction and data Tightly Coupled Memory TCM interfaces Write buffers for the AHB and TCM buses Enhanced 16 x 32 multiplier capable of single cycle MAC operations and 16 bit fixed point DSP instructions to accelerate sig
68. ide data interface and the flash controller offers two 128 bit buffer lines to improve system performance The flash has to be programmed initially via JTAG In system programming must be supported by the bootloader In application programming is possible Flash memory contents can be protected by disabling JTAG access Suspension of burning or erasing is not supported The key features are Programming by CPU via AHB Programming by external programmer via JTAG JTAG access protection Burn finished and erase finished interrupt NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 14 of 67 NXP Semiconductors LPC291 7 1 9 ARMS microcontroller with CAN and LIN 8 1 2 Description LPC2917 19 1 After reset flash initialization is started which takes tini time see Section 12 During this initialization flash access is not possible and AHB transfers to flash are stalled blocking the AHB bus During flash initialization the index sector is read to identify the status of the JTAG access protection and sector security If JTAG access protection is active the flash is not accessible via JTAG ARM debug facilities are disabled to protect the flash memory contents against unwanted reading out externally If sector security is active only the concerned sections are read Flash can be read synchronously or asynchronously to the system clock In synchronous operation the flash goes into standb
69. ing limit and error counters with read write access Arbitration lost capture and error code capture with detailed bit position e Single shot transmission i e no re transmission Listen only mode no acknowledge no active error flags Reception of own messages self reception request Full CAN mode for message reception Global acceptance filter The global acceptance filter provides look up of received identifiers called acceptance filtering in CAN terminology for all the CAN controllers It includes a CAN ID look up table memory in which software maintains one to five sections of identifiers The CAN ID look up table memory is 2 kB large 512 words each of 32 bits It can contain up to 1024 standard frame identifiers or 512 extended frame identifiers or a mixture of both types It is also possible to define identifier groups for standard and extended message formats CAN pin description The two CAN controllers in the LPC2917 19 have the pins listed below The CAN pins are combined with other functions on the port pins of the LPC2917 19 Table 18 shows the CAN pins x runs from 0 to 1 Table 18 pins Symbol Direction Description CANx TXDC OUT CAN channel x transmit data output CANx RXDC IN CAN channel x receive data input LIN Overview The LPC2917 19 contain two LIN 2 0 master controllers These can be used as dedicated LIN 2 0 master controllers with additional support for sync break generation and w
70. ith hardware implementation of the LIN protocol according to spec 2 0 The key features are NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 29 of 67 NXP Semiconductors LPC291 7 1 9 8 6 2 8 7 8 7 1 8 7 2 LPC2917 19 1 ARMS microcontroller with CAN and LIN Complete LIN 2 0 message handling and transfer Oneinterrupt per LIN message Slave response time out detection Programmable sync break length Automatic sync field and sync break generation Programmable inter byte space Hardware or software parity generation Automatic checksum generation Fault confinement Fractional baud rate generator LIN pin description The two LIN 2 0 master controllers in the LPC2917 19 have the pins listed below The LIN pins are combined with other functions on the port pins of the LPC2917 19 Table 19 shows the LIN pins For more information see Ref 1 subsection 3 43 LIN master controller Table 19 LIN controller pins Symbol Direction Description LINO 1 TXDL OUT LIN channel 0 1 transmit data output LINO 1 RXDL IN LIN channel 0 1 receive data input Modulation and sampling control subsystem Overview The Modulation and Sampling Control Subsystem MSCSS in the LPC2917 19 includes four Pulse Width Modulators PWMs two 10 bit successive approximation Analog to Digital Converters ADCs and two timers The key features of the MSCSS are Two 10 bit 400
71. ksample s 8 channel ADCs with 3 3 V inputs and various trigger start options Four 6 channel PWMs Pulse Width Modulators with capture and trap functionality Two dedicated timers to schedule and synchronize the PWMs and ADCs Description The MSCSS contains Pulse Width Modulators PWMs Analog to Digital Converters ADCs and timers Figure 7 provides an overview of the MSCSS An AHB to APB bus bridge takes care of communication with the AHB system bus Two internal timers are dedicated to this subsystem MSCSS timer 0 can be used to generate start pulses for the ADCs and the first PWM The second timer MSCSS timer 1 is used to generate carrier signals for the PWMSs These carrier patterns be used for example in applications requiring current NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 30 of 67 NXP Semiconductors LPC291 7 1 9 ARMS microcontroller with CAN and LIN control Several other trigger possibilities are provided for the ADCs external cascaded or following a PWM The capture inputs of both timers can also be used to capture the start pulse of the ADCs The PWMs can be used to generate waveforms in which the frequency duty cycle and rising and falling edges can be controlled very precisely Capture inputs are provided to measure event phases compared to the main counter Depending on the applications these inputs can be connected to digital sensor motor o
72. l be written with new data This prevents clocks being blocked by incorrect programming Default Clock Sources Every secondary clock generator or output generator is connected to OSC at reset In this way the device runs at a low frequency after reset It is recommended to switch BASE SYS CLK to a high frequency clock generator as one of the first step s in the boot code after verifying that the high frequency clock generator is running Clock Activity Detection Clocks that are inactive are automatically regarded as invalid and values of CLK SEL that would select those clocks are masked and not written to the control registers This is accomplished by adding a clock detector to every clock generator The RDET register keeps track of which clocks are active and inactive and the NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 43 of 67 NXP Semiconductors LPC291 7 1 9 8 8 4 3 ARMS microcontroller with CAN and LIN appropriate CLK SEL values are masked and unmasked accordingly Each clock detector can also generate interrupts at clock activation and deactivation so that the system can be notified of a change in internal clock status Clock detection is done using a counter running at the BASE PCR CLK frequency If no positive clock edge occurs before the counter has 32 cycles of BASE PCR CLK the clock is assumed to be inactive As BASE PCR CLK is slower than any of the clocks to be
73. low temperature Volume mm 350 350 to 2000 gt 2000 lt 1 6 260 260 260 1 6 to 2 5 260 250 245 gt 2 5 250 245 245 Moisture sensitivity precautions as indicated the packing must be respected at all times Studies have shown that small packages reach higher temperatures during reflow soldering see Figure 16 LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 60 of 67 NXP Semiconductors LPC2917 19 LPC2917 19 1 ARMS microcontroller with CAN and LIN temperature maximum peak temperature MSL limit damage level minimum peak temperature minimum soldering temperature peak temperature time 001aac844 MSL Moisture Sensitivity Level Fig 16 Temperature profiles for large and small components For further information on temperature profiles refer to Application Note AN10365 Surface mount reflow soldering description NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 61 of 67 NXP Semiconductors LPC2917 19 ARMS microcontroller with CAN and LIN 15 Abbreviations LPC2917 19 1 Table 34 Abbreviations list Abbreviation ADC AHB AMBA APB BCL BDL BEL BIST CAN CCO CISC DAC DTL FIFO FIQ GPIO y o IAP IRQ ISP JTAG LIN MAC PLL PCRSS PWM RISC RTOS RX SFSP SCL SCU SPI SSP TAP TCM TX UART VIC Desc
74. nal is modulated with the PWM generated waveforms The pause input of MSCSS timer 1 PWM Control is connected to an external input pin Generation of the carrier signal is stopped by asserting the pause of this timer The pause input of MSCSS timer 0 ADC Control is connected to a NOR of the PWM sync outputs start 2 input on the ADCs If the pause feature of this timer is enabled the timer only counts when one of the PWM sync outputs is active HIGH This feature can be used to start the ADC once every x PWM cycles where x corresponds to the value in the match register of the timer In this case the start 3 input of the ADC should be enabled start on match output of MSCSS timer 0 The signals connected to the capture inputs of the timers both MSCSS timer 0 and MSCSS timer 1 are intended for debugging LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 32 of 67 NXP Semiconductors LPC291 7 1 9 ARMS microcontroller with CAN and LIN Fig 8 ADC2 EXT START ADC1 EXT START pause 0 Y pause MSCSS TIMER 0 500 0 501 m1 4 502 2 _0 mscss 1 TIMER 1 gt c1 gt gt MSCSS PAUSE f PWMO TRAP PWM1 TRAP PWM2 TRAP PWM3 002 347 Timers CO to capture in 0 to capture in m0 to m3 match o
75. nal processing algorithms and applications Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously The ARM968E S is based on the ARMV5TE five stage pipeline architecture Typically in a three stage pipeline architecture while one instruction is being executed its successor is being decoded and a third instruction is being fetched from memory In the five stage pipeline additional stages are added for memory access and write back cycles The ARM968E S processor also employs a unique architectural strategy known as Thumb which makes it ideally suited to high volume applications with memory restrictions or to applications where code density is an issue The key idea behind Thumb is that of a super reduced instruction set Essentially the ARM968E S processor has two instruction sets Standard 32 bit ARMv5TE set 16 bit Thumb set The Thumb set s 16 bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM s performance advantage over a traditional 16 bit controller using 16 bit registers This is possible because Thumb code operates on the same 32 bit register set as ARM code Thumb code can provide up to 65 of the code size of ARM and 160 of the performance of an equivalent ARM controller connected to a 16 bit memory system The ARM968E S processor is described in detail in the ARM968E S data sheet Ref 2 On chip
76. nges state A capture event may also optionally generate an interrupt e Four 32 bit match registers per timer that allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Up to four external outputs per timer corresponding to match registers with the following capabilities Set LOW on match Set HIGH on match Toggle on match Do nothing on match Pause input pin MSCSS timers only Description The timers are designed to count cycles of the clock and optionally generate interrupts or perform other actions at specified timer values based on four match registers They also include capture inputs to trap the timer value when an input signal changes state optionally generating an interrupt The core function of the timers consists of a 32 bit prescale counter triggering the 32 bit timer counter Both counters run on clock CLK TMRx x runs from 0 to 3 and all time references are related to the period of this clock Note that each timer has its individual clock source within the Peripheral SubSystem In the Modulation and Sampling SubSystem each timer also has its own individual clock source See section Section 8 8 6 for information on generation of these clocks Pin description The four timers in the peripheral subsystem of the LPC2917 19 have the pins described below The tw
77. nts are exposed to the wave Solder bath specifications including temperature and impurities NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 59 of 67 NXP Semiconductors LPC291 7 1 9 ARMS microcontroller with CAN and LIN 14 4 Reflow soldering Key characteristics in reflow soldering are Lead free versus SnPb soldering note that a lead free reflow process usually leads to higher minimum peak temperatures see Figure 16 than a SnPb process thus reducing the process window Solder paste printing issues including smearing release and adjusting the process window for a mix of large and small components on one board Reflow temperature profile this profile includes preheat reflow in which the board is heated to the peak temperature and cooling down It is imperative that the peak temperature is high enough for the solder to make reliable solder joints a solder paste characteristic In addition the peak temperature must be low enough that the packages and or boards are not damaged The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 32 and 33 Table 32 SnPb eutectic process from J STD 020C Package thickness mm Package reflow temperature C Volume mm lt 350 gt 350 lt 2 5 235 220 gt 2 5 220 220 Table 33 Lead free process from J STD 020C Package thickness mm Package ref
78. o timers in the modulation and sampling subsystem have no external pins except for the pause pin on MSCSS timer 1 See Section 8 7 7 for a description of these NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 24 of 67 NXP Semiconductors LPC291 7 1 9 8 4 3 4 8 4 4 8 4 4 1 8 4 4 2 8 4 4 3 LPC2917 19 1 ARMS microcontroller with CAN and LIN timers and their associated pins The timer pins are combined with other functions on the port pins of the LPC2917 19 see Section 8 3 3 Table Table 14 shows the timer pins x runs from 0 to 3 Table 14 Timer pins Symbol Direction Description TIMERx CAP 0 TIMER x capture input 0 TIMERx CAP 1 TIMER x capture input 1 TIMERx CAP 2 IN TIMER x capture input 2 TIMERx CAP 3 IN TIMER x capture input 3 MAT O OUT TIMER x match output 0 TIMERx MAT 1 OUT TIMER x match output 1 TIMERx MAT 2 OUT TIMER x match output 2 MAT 3 OUT TIMER x match output 3 Timer clock description The timer modules are clocked by two different clocks CLK_SYS_PESS and CLK_TMRx x 0 3 see Section 7 2 2 Note that each timer has its own CLK_TMRx branch clock for power management The frequency of all these clocks is identical as they are derived from the same base clock BASE_CLK_TMR The register interface towards the system bus is clocked by CLK SYS PESS The timer and prescale counters are clocked by CLK TMRx UARTs
79. om the same base clock BASE CLK UART The register interface towards the system bus is clocked by CLK SYS PESS The baud generator is clocked by the CLK UARTx Serial peripheral interface Overview The LPC2917 19 contains three SPI modules to allow synchronous serial communication with slave or master peripherals The key features are Master or slave operation Supports up to four slaves in sequential multi slave operation Supports timer triggered operation Programmable clock bit rate and prescale based on SPI source clock BASE SPI CLK independent of system clock Separate transmit and receive FIFO memory buffers 16 bits wide 32 locations deep Programmable choice of interface operation Motorola SPI or Texas Instruments Synchronous Serial Interfaces Programmable data frame size from 4 to 16 bits Independent masking of transmit FIFO receive FIFO and receive overrun interrupts e Serial clock rate master mode fserial lt fcik spi 2 e Serial clock rate slave mode fserial clk fci spi 4 Internal loopback test mode Functional description The SPI module is a master or slave interface for synchronous serial communication with peripheral devices that have either Motorola SPI or Texas Instruments Synchronous Serial Interfaces The SPI module performs serial to parallel conversion on data received from a peripheral device The transmit and receive paths are buffered with FIFO memories 16 bits wide x
80. ow power modes Clock Generation Unit CGU Overview The key features are Generation of 10 and 2 test base clocks selectable from several embedded clock Sources Crystal oscillator with power down Control PLL with power down Very low power ring oscillator always on to provide a safe clock e Seven fractional clock dividers with L D division Individual source selector for each base clock with glitch free switching Autonomous clock activity detection on every clock source Protection against switching to invalid or inactive clock sources Embedded frequency counter Register write protection mechanism to prevent unintentional alteration of clocks Remark Any clock frequency adjustment has a direct impact on the timing of on board peripherals such as the UARTs SPI watchdog timers CAN controller LIN master controller ADCs or flash memory interface Description The clock generation unit provides 10 internal clock sources as described in Table 23 Table 23 CGU base clocks Numbe Name Frequency Description r MHz 1 0 BASE SAFE CLK 0 4 base safe clock always on 1 BASE SYS CLK 80 base system clock 2 BASE PCR CLK 0 4 21 base PCR subsystem clock 3 BASE IVNSS CLK 80 base IVNSS subsystem clock 4 BASE MSCSS CLK 80 base MSCSS subsystem clock 5 BASE UART CLK 80 base UART clock 6 BASE SPI CLK 40 base SPI clock 7 BASE TMR CLK 80 base timers clock 8 BASE ADC CLK 4 5 base ADCs clock Maximum
81. provided to modify configuration of the ADC and control the moment at which the updated configuration is transferred to the ADC domain The ADC clock is limited to 4 5 MHz maximum frequency and should always be lower than or equal to the system clock frequency To meet this constraint or to select the desired lower sampling frequency the clock generation unit provides a programmable fractional NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 34 of 67 NXP Semiconductors LPC291 7 1 9 ARMS microcontroller with CAN and LIN system clock divider dedicated to the ADC clock Conversion rate is determined by the ADC clock frequency divided by the number of resolution bits plus one Accessing ADC registers requires an enabled ADC clock which is controllable via the clock generation unit see Section 8 8 4 Each ADC has four start inputs Note that start 0 and start 2 are captured in the system clock domain while start 1 and start 3 are captured in the ADC domain The start inputs are connected at MSCSS level see Section 8 7 2 1 for details CLK_ADCx CLK_ADCx_APB ADC clock MSCSS sub system clock up to 4 5 MHz APB SUB SYSTEM ADC DOMAIN DOMAIN update analog inputs ARB systemi bust ADC conversion data ADC ADC IRQ CONTROL CONTROL ANALOG IN 0 7 AND configuration data AND MUX REGISTERS REGISTERS IN 0 7 start 0 start 2 start 1 start 3 sync out 002a
82. ription Analog to Digital Converter Advanced High performance Bus Advanced Microcontroller Bus Architecture ARM Peripheral Bus Buffer Control List Buffer Descriptor List Buffer Entry List Built In Self Test Controller Area Network Current Controlled Oscillator Complex Instruction Set Computers Digital to Analog Converter Device Transaction Level First In First Out Fast Interrupt reQuest General Purpose Input Output Input Output In Application Programming Interrupt ReQuest In System Programming Joint Test Action Group Local Interconnect Network Multiply Accumulate Phase Locked Loop Power Clock and Reset SubSystem Pulse Width Modulator Reduced Instruction Set Computer Real Time Operating System Receive SCU Function Select Port x y use without the P if there are no x y Slot Control List System Control Unit Serial Peripheral Interface Synchronous Serial Port Test Access Port Tightly Coupled Memory Transmit Universal Asynchronous Receiver Transmitter Vectored Interrupt Controller NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 62 of 67 NXP Semiconductors LPC2917 19 16 References LPC2917 19 1 1 2 3 4 5 ARMS microcontroller with CAN and LIN UM LPC2917 19 user manual ARM ARM web site ARM SSP ARM primecell synchronous serial port 022 technical reference manual CAN ISO 11898 1 2002 road vehicles
83. ses Table 10 External memory bank address bit description 32 bit Symbol Description system address bit field 31 to 29 BA 2 0 external static memory base address three most significant bits the base address can be found in the memory map see Ref 1 This field contains 010 when addressing an external memory bank 28 to 26 CS 2 0 chip select address space for eight memory banks see 1 25 and 24 always 00 other values are mirrors of the 16 MB bank address 23 to 0 A 23 0 16 MB memory banks address space Table 11 External static memory controller banks CS 2 0 Bank 000 bank 0 001 bank 1 010 bank 2 011 bank 3 100 bank 4 101 bank 5 110 bank 6 111 bank 7 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 18 of 67 NXP Semiconductors LPC291 7 1 9 ARMS microcontroller with CAN and LIN 8 2 3 External static memory controller pin description The external static memory controller module in the LPC2917 19 has the following pins which are combined with other functions on the port pins of the LPC2917 19 Table 12 shows the external memory controller pins Table 12 External memory controller pins Symbol Direction Description EXTBUS CSx OUT memory bank x select x runs from 0 to 7 EXTBUS BLSy OUT byte lane select input y y runs from 0 to 3 EXTBUSWE N OUT write enable active LOW EXTBUS OUT output enable active LOW EXTBUS A 23 0
84. st data out P2 21 PCAP2 1 D19 2 GPIO 2 pin 21 PWM2 1 EXTBUS D19 PO 24 TXD1 TXDC1 SCS2 0 3 GPIO 0 24 UART1 TXD CAN1 TXDC SPI2 SCSO PO 25 RXD1 RXDC1 SDO2 4 GPIO 0 pin 25 UART1 RXD CAN1 RXDC SPI2 SDO PO 26 SDI2 5 GPIO 0 pin 26 SPI2 SDI PO 27 SCK2 6 GPIO 0 pin 27 SPI2 SCK PO 28 CAPO O MATO O 7 GPIO 0 28 TIMERO CAPO TIMERO MATO PO 29 CAPO 1 MATO 1 8 GPIO 0 29 TIMERO CAP1 TIMERO 1 VpD 0 9 3 3 V power supply for I O 2 22 2 2 020 10 GPIO 2 pin 22 PWM 2 2 EXTBUS 020 2 23 0 021 11 GPIO 2 pin 23 EXTBUS D21 P3 6 SCSO S PMAT1 OJ TXDL 1 12 GPIO3 pin 6 SPIO SCS3 PWM1 MATO LIN1 TXDL P3 7 SCS2 1 PMAT1 1 RXDL 1 13 7 SPI2 SCS1 PWM1 MAT1 LIN1 RXDL PO SO0 CAPO 2 MATO 2 14 pin 30 TIMERO CAP2 TIMERO MAT2 PO 31 CAPO S MATO 3 15 GPIO 0 pin 31 TIMERO CAP3 TIMERO LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 6 of 67 NXP Semiconductors LPC2917 19 ARMS microcontroller with CAN and LIN Table 3 LQFP144 pin assignment continued Pin name Pin Description Default function Function 1 Function 2 Function 3 P2 24 PCAP3 1 D22 16 GPIO 2 pin 24 PWM3 1 EXTBUS D22 P2 25 PCAPS 2 D23 17 GPIO 2 pin 25 PWM3 2 EXTBUS D23 VDD CORE 18 1 8 V power supply for digital core Vss CORE 19 ground for digital core P1 31 CAP
85. synchronized to the main output clock CLKOUT PLL thus giving three clocks with a 120 phase difference Direct output mode In normal operating mode with DIRECT set to logic 0 the CCO clock is divided by 2 4 8 or 16 depending on the value on the PSEL 1 0 input giving an output clock with a 50 96 duty cycle If a higher output frequency is needed the CCO clock can be sent directly to the output by setting DIRECT to logic 1 Since the CCO does not directly generate a 50 duty cycle clock the output clock duty cycle in this mode can deviate from 50 96 Power down control A Power down mode has been incorporated to reduce power consumption when the PLL clock is not needed This is enabled by setting the PD control register bit In this mode the analog section of the PLL is turned off the oscillator and the phase frequency detector are stopped and the dividers enter a reset state While in Power down mode the LOCK output is low indicating that the PLL is not in lock When Power down mode is terminated by clearing the PD control register bit the PLL resumes normal operation and makes the LOCK signal high once it has regained lock on the input clock CGU pin description The CGU module in the LPC2917 19 has the pins listed in Table 24 below Table 24 CGU pins Symbol Direction Description XOUT OSC OUT oscillator crystal output XIN OSC IN oscillator crystal input or external clock input Reset Generation Unit RGU Overview The k
86. tation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in medical military aircraft space or life support equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected 19 Contact information For more information please visit http www nxp com to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 may cause permanent damage to the device Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied Exposure
87. test product status information is available on the Internet at URL http www nxp com 18 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet shall prevail 18 3 Disclaimers General Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limi
88. the watchdog timer is to reset the ARM9 processor within a reasonable amount of time if the processor enters an error state The watchdog generates a system reset if the user program fails to trigger it correctly within a predetermined amount of time Key features Internal chip reset if not periodically triggered Timer counter register runs on always on safe clock Optional interrupt generation on watchdog time out Debug mode with disabling of reset Watchdog control register change protected with key Programmable 32 bit watchdog timer period with programmable 32 bit prescaler Description The watchdog timer consists of a 32 bit counter with a 32 bit prescaler The watchdog should be programmed with a time out value and then periodically restarted When the watchdog times out it generates a reset through the RGU To generate watchdog interrupts in watchdog debug mode the interrupt has to be enabled via the interrupt enable register A watchdog overflow interrupt can be cleared by writing to the clear interrupt register Another way to prevent resets during debug mode is via the Pause feature of the watchdog timer The watchdog is stalled when the 9 is in debug mode and the PAUSE ENABLE bit in the watchdog timer control register is set The Watchdog Reset output is fed to the Reset Generation Unit RGU The RGU contains a reset source register to identify the reset source when the device has gone through a reset See
89. the waveforms pulses of the desired duty cycles and cycle periods A very basic application of these pulses can be in controlling the amount of power transferred to a load Since the duty cycle of the pulses can be controlled the desired amount of power can be transferred for a controlled duration Two examples of such applications are Automotive dimmer controller The flexibility of providing waves of a desired duty cycle and cycle period allows the PWM to control the amount of power to be transferred to the load The PWM functions as a dimmer controller in this application Motor controller The PWM provides multi phase outputs and these outputs can be controlled to have a certain pattern sequence In this way the force torque of the motor can be adjusted as desired This makes the PWM function as a motor drive NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 36 of 67 NXP Semiconductors LPC291 7 1 9 ARMS microcontroller with CAN and LIN IRQ pwm IRQ capt match APB system bus gt capture data i PWM sync_in transfer_enable_in APB DOMAIN PWM DOMAIN update match outputs PWM capture inputs COUNTER PONE PRESCALE PWM counter value NTER REGISTERS 1 i ab SHADOW config data REGISTERS trap input carrier inputs IRQ s transfer enable out sync out 002aad837 Fig 10 PWM block diagram 8 7 6 3 LPC2917 19 1
90. to limiting values for extended periods may affect device reliability Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms including those pertaining to warranty intellectual property rights infringement and limitation of liability unless explicitly otherwise agreed to in writing by NXP Semiconductors In case of any inconsistency or conflict between information in this document and such terms and conditions the latter will prevail No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights 18 4 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners I C bus logo is a trademark of NXP B V For sales office addresses please send an email to salesaddresses nxp com LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 65 of 67 NXP Semiconductors LPC2917 19 20 Contents 1 1 1 1 2 2 2 1 2 2 2 3 2 4 3 3 1 4 4 1 5 6 6 1 6 2 6 2 1 6 2 2 7 7 1 7 1 1 7 1 2 7 1 3 7 1 4 7 2 7 2 1 7 2 2 8 1 8 1 1 8 1 2 8 1 3
91. up input current all port pins RESET 25 50 100 uA TRST_N TDI JTAGSEL TMS Vi 0 V Vi gt 3 6 Vis not allowed input capacitance 3 8 pF Output pins and pins configured as output Vo output voltage 0 x Vpp 0 V HIGH level output voltage 4 Vppuoj 70 4 V VoL LOW level output voltage 4 mA 0 4 V load capacitance 25 pF Analog to digital converter supply VyREFN voltage on pin VREFN 0 Vvrerp 2 V VvyREFP voltage on pin VREFP VvyREFN 2 B VppA apoava Vi ADC input voltage on port 0 pins VVREEN VvREEP V Zi input impedance between Vyrern and 4 4 VVREFP FSR full scale range 2 10 bit INL integral non linearity 2 2 LSB DNL differential non linearity 1 1 LSB Verr offset offset error voltage 20 20 mV Verr FS full scale error voltage 20 20 Oscillator Rg xtal crystal series resistance fose 10 MHz to 15 MHz Cytal 10 pF 160 Q 18 pF 20 pF 60 Q Cext 39 pF fose 15 MHz to 20 MHz 10 pF 80 18 pF Ci input capacitance of XIN OSC 9 2 pF LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 54 of 67 NXP Semiconductors LPC291 7 1 9 ARMS microcontroller with CAN and LIN Table 30 Static characteristics continued VDD CORE Vpp osc PLL 2 7 V to 3 6 V VDDA ADC3V3 3 0Vt03 6V Tj 40
92. ut 0 to match out 3 ADCs StO to st3 start 0 to start inputs 50 to 53 sync out 0 to sync out PWMs c_i carrier in s_i sync_in S 0 sync out i trans enable in TE o trans enable out Modulation and sampling control subsystem synchronization and triggering LPC2917 19 1 8 7 3 MSCSS pin description The pins of the LPC2917 19 MSCSS associated with the two ADC modules are described in Section 8 7 5 3 Pins directly connected to the four PWM modules are described in Section 8 7 6 5 pins directly connected to the MSCSS timer 1 module are described in Section 8 7 7 3 8 7 4 MSCSS clock description The MSCSS is clocked from a number of different sources NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 33 of 67 NXP Semiconductors LPC291 7 1 9 8 7 5 8 7 5 1 8 7 5 2 LPC2917 19 1 ARMS microcontroller with CAN and LIN e SYS MSCSS A clocks the AHB side of the AHB to APB bus bridge CLK MSCSS APB clocks the subsystem APB bus e MSCSS clocks the timers MSCSS PWMO 3 clocks the PWMs Each ADC has two clock areas a part clocked by CLK MSCSS ADOx APB 1 or 2 and a control part for the analog section clocked by CLK ADOx 1 or 2 see Section 7 2 2 All clocks are derived from the BASE MSCSS except for SYS MSCSS which is derived form BASE SYS CLK and the CLK ADOx clocks which are derived
93. utputs or digital external signals Interrupt signals are generated on several events to closely interact with the CPU The ADOCs can be used for any application needing accurate digitized data from analog sources To support applications like motor control a mechanism to synchronize several PWMs and ADCs is available sync in and sync out Note that the PWMs run on the PWM clock and the ADCs on the ADC clock see Section 8 8 4 ADC2 IN 7 0 ADC2 EXT START ADC1 IN 7 0 ADC1 EXT START ADC clock MSCSS TIMER 0 v ADC ADC CONTROL 1 ADC 3 3 V 2 AHB APB sub system bus SYNCS system bus to all sub blocks y BRIDGE PWMO MAT 5 0 MSCSS PWM gt 1 0 PWM1 5 0 PWM gt PWM 1 PWM2 5 0 CONTROL PWM gt 2 PWM3 MAT 5 0 CARRIERS PWMO0 PWMO 2 0 PWM1 TRAP PWM1 CAP 2 0 PWM2 TRAP PWM2 CAP 2 0 PWM3 TRAP PWM3 CAP 2 0 002aad348 Fig 7 Modulation and sampling control subsystem block diagram 8 7 21 Synchronization and trigger features of the MSCSS The MSCSS contains two internal timers to generate synchronization and carrier pulses for the ADCs PWMs Figure 8 shows how the timers are connected to the ADC and PWM modules LPC2917 19 1 NXP B V 2008 All rights reserved Product data sheet Rev 01 31 July 2008 31 of 67 NXP Semiconductors LPC291 7 1 9 ARMS microcontroller wit
94. utting the ARM CPU into a low power state are not supported Instead putting the ARM CPU into power down should be controlled by disabling the branch clock for the CPU Remark For any disabled branch clocks to be re activated their corresponding base clocks must be running controlled by the CGU Table 27 shows the relation between branch and base clocks see also Section 7 2 1 Every branch clock is related to one particular base clock it is not possible to switch the source of a branch clock in the PMU Table 27 Branch clock overview Legend 1 Indicates that the related register bit is tied off to logic HIGH all writes are ignored 0 Indicates that the related register bit is tied off to logic LOW all writes are ignored Indicates that the related register bit is readable and writable Branch clock name Base clock Implemented switch on off mechanism WAKE UP AUTO RUN CLK_SAFE BASE SAFE CLK 0 0 1 CLK SYS CPU BASE SYS CLK 1 5 5 BASE SYS CLK 1 CLK SYS PCR BASE SYS CLK 1 CLK SYS BASE SYS CLK CLK SYS RAMO BASE SYS CLK CLK SYS RAM1 BASE SYS CLK 5 5 5 BASE SYS CLK SYS GESS BASE SYS CLK NXP 2008 All rights reserved Product data sheet Rev 01 31 July 2008 47 of 67 Semiconductors 2917 19 LPC2917 19 1 Table 27 Legend Branch clock overview continued ARMS microcontroller with CAN an
95. with increased miniaturization Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder The wave soldering process is suitable for the following Through hole components Leaded or leadless SMDs which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered Packages with solder balls and some leadless packages which have solder lands underneath the body cannot be wave soldered Also leaded SMDs with leads having a pitch smaller than 0 6 mm cannot be wave soldered due to an increased probability of bridging The reflow soldering process involves applying solder paste to a board followed by component placement and exposure to a temperature profile Leaded packages packages with solder balls and leadless packages are all reflow solderable Key characteristics in both wave and reflow soldering are Board specifications including the board finish solder masks and vias Package footprints including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead free soldering versus SnPb soldering 14 3 Wave soldering LPC2917 19 1 Key characteristics in wave soldering are Process issues such as application of adhesive and flux clinching of leads board transport the solder wave parameters and the time during which compone
96. y after returning the read data Started reads cannot be stopped and speculative reading and dual buffering are therefore not supported With asynchronous reading transfer of the address to the flash and of read data from the flash is done asynchronously giving the fastest possible response time Started reads can be stopped so speculative reading and dual buffering are supported Buffering is offered because the flash has a 128 bit wide data interface while the AHB interface has only 32 bits With buffering a buffer line holds the complete 128 bit flash word from which four words can be read Without buffering every AHB data port read starts a flash read A flash read is a slow process compared to the minimum AHB cycle time so with buffering the average read time is reduced This can improve system performance With single buffering the most recently read flash word remains available until the next flash read When an AHB data port read transfer requires data from the same flash word as the previous read transfer no new flash read is done and the read data is given without wait cycles When an AHB data port read transfer requires data from a different flash word to that involved in the previous read transfer a new flash read is done and wait states are given until the new read data is available With dual buffering a secondary buffer line is used the output of the flash being considered as the primary buffer On a primary buffer hit data

LPC2917,19 - NXP Semiconductors

Contents

Download Pdf Manuals

Related Search

Related Contents