Application Note 1376 External Serial Interface Reduces
Contents
1. 2005 National Semiconductor Corporation External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs 1 0 Introduction A critical issue with any FPGA Field Programmable Gate Array design is Simultaneous Switching Output SSO noise SSO noise also known as ground bounce is a result of large instantaneous changes in current across the power ground inductance of the integrated circuit This potential problem becomes more and more serious as the number of active high drive LVCMOS outputs on a FPGA design in creases In large FPGAs with several synchronous parallel interfaces this phenomenon can result in poor system per formance or intermittent data errors This application note highlights how using external SerDes in conjunction with minimum current drive FPGA I O can reduce FPGA s internal noise and reap the benefits of a serial interface across the system This may allow designers to use low end FPGAs with external SerDes to reduce cost and still have high analog performance The FPGA SSO noise is minimized by using the lowest drive current from the FPGA and reduces the parallel bus to a single differential signal LVCMOS outputs from the FPGA are unsuited for driving over long interconnects or at high data rates Upgrading the parallel interfaces with an external Serializer Deserializer SerDes interface to the FPGA will reduce SSO noise and improve the overall system perfor mance The close proximity of t2. Jitter The reduction in jitter will improve analog performance of adjacent components like the DS92LV16 Starting with a clean clock source means that significantly reduced jitter within the PLL bandwidth will allow for enhanced high speed signal integrity By reducing the FPGA interconnect to short to point topol ogy the low drive 2 mA setting can efficiently and cleanly drive the LVCMOS interconnect into the LVDS SerDes Pro gramming to the low drive setting reduces the noise gener ated by the FPGA and reduces system EMI Figure 7 and www national com 9ZEL NV AN 1376 3 0 Simultaneous Switching Output Noise Continued Figure 8 clearly show undershoot and overshoot is com pletely eliminated and noise reduction achieved with low drive FPGA programming Tek 2 00GS75 7 Acgs F eaaa TEZEL SELEZ Peete ee ee 8S Jossajao dfeefonenfvee el 4 i H i offen TE odpadejo M25 0ns Cha J 50mV 6 Jan 2005 17 22 38 20146111 FIGURE 7 24 mA FPGA Output 4 Trace with PRBS Data 6 Jan 2005 17 28 17 20146112 FIGURE 8 2 mA FPGA Output 4 Trace with PRBS Data 4 0 Benefits of Using External SerDes LVCMOS outputs from the FPGA are unsuited for driving over long interconnects or at high data rates To address these system demands and to reduce the number of signals at backplane or cable interfaces SerDes devices with low voltage differential signaling LVDS technology are oft
3. data stream is output as a Low Voltage Differential Signaling LVDS signal with a maximum speed of 1 44 Gbps across cables or backplanes The deserializer takes the differential LVDS signal and trans lates it back into 16 bit parallel LVCMOS data The device also contains loop back test capability for testing line and local interfaces The Serializer and Deserializer operate in dependently with separate clock enable and power down pins 2 2 2 Altera Cyclone FPGA Table 1 shows the Cyclone device family and features After selecting an FPGA to handle the logic and processing re quirements of the application the designer may chose to add an external SerDes due to system interface require ments The FPGA choice depends on the end application requirements the DS92LV16 can be effectively used with any FPGA density or architecture 9ZEL NV LINE_LE Parallel to Serial g DO Timing and oe Power gt Control LOCAL_LE Serial to Parallel RIN RIN Timing and Control Clock Recovery 20146103 FIGURE 3 DS92LV16 Block Diagram TABLE 1 Device Features LEs 2 910 4 000 5 980 12 060 20 060 Total RAM Bits 59 904 78 336 92 160 239 616 294 912 Maximum User I O Pins 301 249 301 3 0 Simultaneous Switching The following test was conducted with the FPGA to Output Noise DS92LV16 parallel bus clocking at 80 MHz and the LVCMOS output drive current of the FPGA set to either 24 mA or 2 mA SSO noise as the nam
4. stand alone SerDes is an effective way to minimize device generated SSO noise in the FPGAs The external SerDes device allows the used to program the FPGA with a minimum output drive The minimum drive limits the noise generated by the FPGA due to reduced simultaneous switching currents Reduced noise lowers the risk that adja cent analog components will become inadvertent victims of excessive digital noise In addition to the local noise reduction benefits shown in the application note Using a stand alone SerDes function pro vides lower jitter BER and longer drive capability resulting in better analog performance External SerDes function may also allow lower cost solutions with performances compa rable to the higher cost solutions Analog enhancements such as pre emphasis have enabled even higher speeds and longer drive distances over lossy interconnect This capability achieved though low cost sili con upgrades can be used to extend the operational life and enhance the functionality of systems currently deployed in the field 5 1 RESOURCES AND REFERENCES 1 DS92LV16 Design Guide National Semiconductor Oc tober 2002 www national com 2 DS92LV16 Bus LVDS SerDes Demo Kit User Manual National Semiconductor October 2003 www national com 3 LVDS Owner s Manual National Semiconductor 3rd Edition Spring 2004 www national com 4 Cyclone Device Handbook Volumes 1 amp 2 Altera 2003 and 2004 www altera com 5 Quartu
5. 0 feet of cable This added feature increases the reach of LVDS SerDes by up to 5x at gt 1 Gbps serial data rates www national com 9ZEL NV AN 1376 4 0 Benefits of Using External SerDes_ Continued External Direct i aranea a SEA E OSERE AS Ha py Diy Amalie J put ETA in et 20146116 Measured after 15m of Infiniband Cable at the Input of the DS92LV18 Receiver frek 66 MHz 1 32 Gbps No Pre emphasis FIGURE 11 Eye Diagram measured after 15m of Infiniband Cable at the Input of the DS92LV18 Receiver freck 66 MHz 1 32 Gbps No Pre emphasis www national com 8 4 0 Benefits of Using External SerDes Continued SU Lh Ahatuite NOL me zig Extemal Direct ME fi g TES TM T Gabe Patt pod ate phi ae i Cu fa H La ay a de i seen wha a NVA a HW listqrm hin C1 Me S f 5 J the if ds f t f 20146117 Measured after 15m of Infiniband Cable at the Input of the DS92LV18 Receiver freLk 66 MHz 1 32 Gbps Max Pre emphasis FIGURE 12 Eye Diagram measured after 15m of Infiniband Cable at the Input of the DS92LV18 Receiver frek 66 MHz 1 32 Gbps Max Pre emphasis The eye diagrams shown in Figure 11 and Figure 12 clearly show the value of pre emphasis for driving cables up to 15 to 20 meters in length ASCAN921821 Dual 18 bit Serializer is transmiting the data while a DS92LV18 SerDes is receiving the data 5 0 Conclusion Using a
6. RE 1 DS92LV16 SerDes and Cyclone FPGA Test Setup AN201461 www national com 9ZEL NV SV5d Ul SION nd n o HulyouMsS SnosuelNWIS se9onpsy so9ejJ19 U JLM S JLU 9 ZEL NV AN 1376 2 0 Test Setup for Simultaneous used for the interface would depend upon the device se S itchi O Noi lected additional required functionality and other layout con witc Ing utput OISE Continued straints For the best and most consistent AC performance all the FPGA SerDes interconnects should be selected 2 1 TEST SETUP SCHEMATIC from a single I O bank Figure 2 shows an example of a system implementation using the Cyclone and DS92LV16 The specific Cyclone I Os Cyclone DS92LV16 DS92LV16 DIN 15 DIN 14 DIN 13 DIN 12 DIN 11 DIN 10 DIN 9 DIN 8 DIN 7 DIN 6 DIN 5 DIN 4 DIN 3 DIN 2 DIN 1 DIN 0 TCLK SYNC Backplane DEN ITPWDN or Cable ROUT 13 ROUT 12 ROUT 11 ROUT 10 ROUT 9 ROUT 8 ROUT 7 ROUT 6 ROUT 5 ROUT 4 ROUT 3 ROUT 2 LVCMOS I O ROUT 1 ROUT 0 RCLK LOCK REN RPWDN LINE_LE LOCAL_LE at REFCLK XTAL OSC 20146102 FIGURE 2 Cyclone and DS92LV16 Connections www national com 2 2 0 Test Setup for Simultaneous Switching Output Noise Continued 2 2 COMPONENT INFORMATION 2 2 1 National DS92LV16 SerDes Figure 3 shows the block diagram for the DS92LV16 Ser Des The serializer takes 16 bits of parallel LVCMOS data and translates it into a serial stream with embedded clock The serial
7. e implies is the result of internal and This will allow for the observation of SSO noise and other external circuitry switching at the same time The cumulative effect of all this switching current passing through power and ground inductance is device generated noise This noise is visible on non switching outputs as internal movement in the ground or power network noise related effects on the parallel bus 1 Simultaneous Switching Outputs Switched 16 FPGA outputs simultaneously while monitoring a quiet output for ground bounce on the FPGA evaluation board www national com AN 1376 3 0 Simultaneous Switching Output Noise Continued 2 Clock Output Jitter Switched 16 FPGA outputs simul taneously while monitoring a FPGA clock output for jitter Tek Run T 4 4 d t f k L i i Figure 4 shows the level of noise that can result from only 16 LVCMOS 1 Os switching at the same time 10 00 20146105 FIGURE 4 Active Output Transitions and Quiet Output bottom SS Data 24 mA The upper waveform CH1 is the active switching transition repeated on 15 additional LVCMOS FPGA outputs driven at 24 mA There is a visible 600 mV undershoot present just after the waveform falling edge As expected the bottom quiet output waveform CH2 tends to follow this pattern highlighting an internal ground movement of 500 mV around the true board ground This internal noise in the gro
8. en employed www national com 4 1 External SerDes Reliability The main function of any SerDes chipset is to translate data originating from a wide parallel bus into one or more serial bit streams and to convert the data back a wide parallel bus at the receiving end With the system improvements SerDes devices bring one of the first questions system designers may ask is how long the interconnect between the serializer and the deserializer can be that will still ensure error free data transfer To find out the answers to questions of How far and How fast a type of testing called BER or Bit Error Rate Testing is done on the serial interface Figure 9 shows the eye diagram at the DS92LV16 receiver after 1m of CAT5 cable This diagram shows the wide open eye possible with inexpensive CAT5 cable running at a data rate of almost 1 Gbps The maximum data rate of the DS92LV16 is approximately 1 5 Gbps Tek 250GS s ET 1 391M Acqs DPO Brightness 50 l 19 Jan 2005 13 40 15 20146114 FIGURE 9 Eye Diagram after 1m of CAT5 Cable A related example of this type of testing is shown below As depicted in Figure 10 a BER transmitter provided 18 bit wide PRBS 2 1 and a BER receiver received 18 bit wide PRBS 2 1 The DS92LV18 transmitter serialized the se quence and sent it across a cable assembly the DS92LV18 receiver then de serialized the data and sent the 18 bit wide PRBS pattern back to the BERT for anal
9. he external SerDes to the National Semiconductor Application Note 1376 Lee Sledjeski April 2005 FPGA allows the FPGA I O to be programmed at the mini mum CMOS drive level of about 2 mA Reducing the drive level lowers the dynamic currents within the FPGA curbing the generation of SSO noise Noise generated in the I Os on a FPGA can corrupt the analog performance of FPGA PLLs or other system analog resources The Altera Cyclone or Xilinx Spartan are good examples of economical FPGAs intended for low to medium end applica tions They do not contain dedicated serialization or deseri alization circuitry for high speed communications limiting the maximum data rate This makes the Cyclone and Spartan good candidates for an external serial interface Using a SerDes external to an FPGA allows an entire multi byte parallel interface to be condensed to one or more high speed signal pairs for economical transmission across sys tem interfaces Before and after measurements of the SSO noise on a Cyclone FPGA will help to quantify the improve ments made by the change in the FPGA programmed I O Current drive 2 0 Test Setup for Simultaneous Switching Output Noise The FPGA SerDes evaluation test setup is shown in Figure 1 CH1 FPGA Evaluation Board Oscilloscope Boot Loader and RS 232 DS92LV16 3 3VDC Serializer Circuitry 1 meter Z Pack Twinax cable DS92LV16 Deserializer 3 3VDC DG 2040 20146101 FIGU
10. increased dramatically the serial interface can transfer data at a rate and distance just not possible with a parallel interface In order to accommo date Gigabytes of data 32 64 or even 128 bit parallel bus designs have been implemented This resulted in massive routing bottlenecks at cable assemblies memory board and backplane interfaces These performance limiting issues were addressed when the parallel interfaces were replaced with one or more high speed serial interfaces This architec ture shift has enabled system performance packaging and features that could not otherwise have been achieved 4 2 External SerDes With Pre Emphasis Feature Even at the lower data rates used in parallel architectures a factor limiting transmission distance has always been the electrical losses of the transmission media Serial architec tures have progressed to address the dielectric and skin effect loss issues associated with high speed design in sev eral ways In order to achieve high speed reliable data trans mission across cables up to 50 feet long something must be done to compensate for the high frequency loss in the cable Pre emphasis is a circuit design technique that adds high frequency energy to the transmitter output signal negating the loss incurred during data transmission across the me dium The National Semiconductor SCAN921821 a dual 18 bit Serializer uses 6 dB of pre emphasis to maintain robust error free communication across 5
11. ling can be reasonably expected to result in a significant injury to the user BANNED SUBSTANCE COMPLIANCE 2 Acritical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification CSP 9 111C2 and the Banned Substances and Materials of Interest Specification CSP 9 111S2 and contain no Banned Substances as defined in CSP 9 111S2 National Semiconductor National Semiconductor Americas Customer Europe Customer Support Center Support Center Fax 49 0 180 530 85 86 Email new feedback nsc com Email europe support nsc com Tel 1 800 272 9959 Deutsch Tel 49 0 69 9508 6208 English Tel 44 0 870 24 0 2171 www national com Fran ais Tel 33 0 1 41 91 8790 National Semiconductor National Semiconductor Asia Pacific Customer Japan Customer Support Center Support Center Fax 81 3 5639 7507 Email ap support nsc com Email jon feedback nsc com Tel 81 3 5639 7560
12. ogrammed into the FPGA outputs large excursions outside the supply rails are clearly visible Tek Run 100GS s ET Sample MJO DPO Brightness 50 H ae eee ee a ee ee a Da a a E E R E E E E E i je C a E a ones pepaj r e a 1 44 V 18 Jan 2005 14 30 58 20146109 M S00ps Ch3 S Rising Edge Magnification This view shows greater than 200 ps of clock jitter in the FPGA output that is a result of the increased drive current PLL analog performance In addition to the reduction in FPGA performance analog devices located adjacent to the FPGA will also be affected by the increase in ground noise The following series of waveforms Figure 6 show how a reduction in drive strength can improve the signal integrity and lower the jitter seen on FPGA output signals Tek Run 25 0GS s ET Sample Pe DPO Brightness 50 F 14 18 15 20146108 Reducing the FPGA programmed drive to 2 mA results in a tightly controlled clock waveform Tek Run 100GS s ET Sample M F lossafsesejosso fa ooa feso aosfoscefoscofrecefsso a H T MEE UOU PENY DOY VOE SON MEY UE E A M O A WET OOE OE O M MR ssesfeossfjssesjomofp es T 44 V 18 Jan 2005 14 26 25 20146110 M 500ps Cha J Rising Edge Magnification This view shows how a reduced 2 mA drive current maintains good signal integrity and exceptionally low 50 ps jitter FIGURE 6 24 mA Drive vs 2 mA Drive for FPGA Output Clock Signal Integrity and
13. s Il Handbook Volumes 1 2 amp 3 Altera 2004 www altera com 6 DS92LV16 16 Bit Bus LVDS Serializer Deserializer Datasheet National Semiconductor 2004 www national com 7 DS92LV18 18 Bit Bus LVDS Serializer Deserializer Datasheet National Semiconductor 2004 www national com 8 SCAN921821 Bus LVDS Dual 18 Bit Serializer Demo Kit User Manual National Semiconductor 2004 www national com 9 DS92LV16 Bus LVDS SerDes Demo kit User Manual National Semiconductor October 2003 www national com www national com 9ZEL NV ise in FPGAs AN 1376 External Serial Interface Reduces Simultaneous Switching Output No AN 1376 Notes National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications For the most current product information visit us at www national com LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labe
14. und and power systems can dynamically alter the supply b b 8 b 1 1 8 F voltage of switching logic The dynamic shift in supply volt age will cause changes in the switching characteristics of internal signals and reduce the performance of other more sensitive analog circuitry In addition the output signal also shows ringing and undershoots i 4 E i N UT we i 4 L i T ejs T ee i L I Y 1 i Y i 4 i i Chil 2 00 YQ fai 500mY 2 Mi2 00ns Al Chi 1 40V 10 00 20146106 FIGURE 5 Active Output Transitions and Quiet Output bottom SS Data 2 mA Figure 5 shows the quiet and switching waveforms with the FPGA programmed for 2 mA minimum current drive The upper waveform CH1 is the active switching transition re peated on 15 additional LVCMOS FPGA outputs Compared to the previous waveform the 2 mA drive current results in www national com slower transition times and greatly reduced undershoot rela tive to external ground Monitoring the signal on a quiet output CH2 shows the improvement on the internal ground as well 3 0 Simultaneous Switching Output Noise Continued The FPGA drive current reduction improves the signal integ rity and lowers the jitter of output Clock signals The noise on the clock signal is another indication of diminished FPGA Tek Run 25 0GS s ET Sample DPO Brightness 50 14 20 08 20146107 With 24 mA of drive pr
15. ysis Configuring the test setup in this manner allows the maximum operating frequency to be determined for each cable length The maxi mum operating frequency of this system is defined as the maximum frequency of the device transmitter clock TCLK at which the device receiver misinterprets zero out of 10 data bits This equates to the bit error rate of less than 1 x 10 The test was conducted at room temperature and the power supply voltage for both devices was set to 3 3 volts For a DS92LV18 SerDes the TCLK frequency equates to 1 20th of the high speed serial data rate For example at the chipset maximum TCLK of 66MHz the serial data rate is running at a speed of 1 32Gbps 4 0 Benefits of Using External SerDes Continueo PCB 1 DS92LV18 Transmitter or ASIC FPGA PCB 2 DS92LV18 Receiver or ASIC FPGA 20146115 FIGURE 10 DS92LV18 SerDes BER Test Setup Based on the BERT results the DS92LV18 can be used in short to medium length cable interface applications If em ployed to move data between two points across a generic category 5 cable it can operate at its highest operating frequency 66 MHz for cable lengths up to 10 feet For lower operating frequencies it can transmit error free data over cables longer than 50 feet Shielded cables with lower nomi nal attenuation paired with connectors rated for gigabit op eration enable you to make longer high speed error free connections Even though the speeds have
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