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PCBLA final report rev. 5 by jason

1. l C Done 2 Figure 11 Display Block 16 Start Print Save Print or Save Take screen shot Take screen shot Write to printer Write as jpeg driver Figure 12 Output Block Division of Labor Jason Nielsen e Programming the graphical user interface e USB device drivers e Data display e Triggering Jeff Earleson Hardware detection of 8 to 16 digital lines USB interface Probe connection Microcontroller USB interface Schedule of Development Software Programming the graphical user interface 2 weeks USB device drivers 3 weeks Data display 3 weeks Triggering 2 weeks Hardware Hardware detection 3 weeks USB interface 3 weeks Probe connection 1 week Microcontroller USB interface 3 weeks Part List 1 Junior Lab computer Microsoft NET framework 16 high impedance probes 32 Schmitt triggers USB interface chip 17 e microcontroller Appendix A Full Feature List Primary Cursors indicating time difference Trigger on clock line internal or external Print waveform Logic levels at the cursors Display binary or hex value of a multiple line bus at the cursors Change the number of lines displayed Basic idiot protection Indeterminate state Trigger position in the buffer middle pre post TTL or CMOS level detection Secondary 1 2 3 4 5 6 T 8 Trigger on user defined
2. Increment k Yes No Increment 1 Is 1i lt USB data size Done Figure 9 Memory Store Yes Probe Data 1 Trigger Mask Yes Increment 1 Isi lt Front of Probe v Data index No Store trigger Doe 4 Figure 10 Trigger Block C Stt Place trigger Index at desired display position y Draw every tenth data point pre and post of trigger index C Done 2 Figure 11 Display Block Start Print Save Print or Save Take screen shot Take screen shot E E Write to printer Write as jpeg driver Figure 12 Output Block 10 Appendix IX Original Project Proposal PC Based Logic Analyzer Project Proposal Advisors Dr James H Irwin Mr Jos S nchez Team Members Jeffery Earleson Jason Nielsen November 30 2004 EE 451 Bradley University Electrical and Computer Engineering Department 11 Introduction A logic analyzer is an instrument that displays digital signals It functions much like an analog oscilloscope except it only displays four levels low high tri state and indeterminate it also samples more lines This project will create a PC based logi
3. ep dataout out std logic vector 7 downto 0 end component component okWireOut port ti clk In std logic ti control In std logic vector 12 downto 0 ti data out std logic vector 7 downto 0 ep addr In std logic vector 7 downto 0 ep datain In std logic vector 7 downto 0 end component component okBufferedPipeOut port ti clk in std logic ti control an std logic vector 12 downto 0 ti data out std logic vector 7 downto 0 ep addr in std logic vector 7 downto 0 ep clk in std logic ep reset in std logic ep write in std logic ep datain in std logic vector 7 downto 0 ep full out std logic ep empty out std logic ep status out std logic vector 3 downto 0 end component signal ti clk STD LOGIC signal ti control STD LOGIC VECTOR 12 downto 0 signal ti data STD LOGIC VECTOR 7 downto 0 signal epOOwire STD LOGIC VECTORf 7 downto 0 signal epO1 wire STD_LOGIC_VECTOR 7 downto 0 signal ep20wire STD LOGIC VECTOR T downto 0 signal clk2 STD LOGIC signal reset STD LOGIC signal pipewrite STD LOGIC signal pipeData STD LOGIC VECTOR downto 0 signal pipefull STD LOGIC signal pipeEmpty STD LOGIC signal pipeStatus STD LOGIC VECTOR S downto 0 signal countr STD LOGIC VECTOR 1 downto 0 signal pipebuffer STD LOGIC VECTOR 31 downto 0 signal testcount STD LOGIC VECTOR T downto 0 begin Due to the
4. int arrsize this qViewSize double arr arr new double arrsize int j 0 int 1 beginPoint usually this qviewfront will be passed it but doing so isn t required int tmpcnt this qViewSize while tmpcnt 0 arr j this gArray i 1 1 1 capacity j tmpcnt return arr j Standard pop function removes an element from the queue public void Pop if this qcount_ 0 queue empty this gempty true else this qfront_ this qfront_ 1 capacity this qfull false this qcount items point j pcbla specific Push function adds new data point to back of queue public void Push double data if this qcount_ Capacity queue full if the queue is full pop so the new data can be pushed this 1s a pcbla application specific action because want pcbla to continually throw away data until the correct trigger 1s found and filling the queue stops di qtull_ true this Pop j this qArray this gback data this qback this qback_ 1 capacity this gempty false this qcount j Properties to be accessed by programmer const int capacity 10000 specifies max number of storable queue public int Capacity get return capacity_ j Static Properties These are static because they should be the same for all the lines You wouldn t want to zoom only one line and there can be only one trigge
5. Now that the data is in a linear array it can be displayed Graphical User Interface The GUI Graphical User Interface is the main program and was written in C It calls the C programs provides user control and displays the signals When the GUI starts it 1nitializes the display and calls the FPGA configuration program Upon successful return from configuration the GUI waits for user input The user enters an input using the mouse or keyboard Figure 23 shows the several inputs the user can select scroll bar zoom bar data txt Recenter Trigger and Run Until Trigger The user uses the data txt button to load data from the data text file This button can be used to redisplay data that the user saved from previous sessions To acquire new 20 data the user clicks Run Until Trigger This calls the pcbladata exe C program to read new data from the XEM 3001 until a trigger event is found A trigger event is defined by a rising edge of probe line zero When a trigger is found the index of the trigger event is stored in linedat 0 qTriggerPoint see Appendix IV pg 4 The program then plots the gathered data with the trigger point in the middle of the display Once the data is plotted the user can scroll and zoom the display to analyze the data After scrolling or zooming if the user wants to recenter the trigger point all they have to do is click the Recenter Trigger button The number next to the zoom bar 1s the array index of the t
6. e Logic penny High Z Comparison circuit Figure 3 Comparison Circuit Block Diagram 2 Bits from Comparison Line to USB circuit Controller Write Read Controller Controller Figure 4 Buffer Block Diagram Data line to PC From Buffer USB Transceiver Chip Figure 5 USB Interface Block Diagram PC Functionality m USB Data Memory Conditioned Signals Reason Data Store Data gt Trigger Display Data gt Display vim Output A A A Trigger Control SE Display Control Control Mouse Output Control Figure 6 PC Block Diagram PC Inputs Conditioned Signals Signals sent from the POD to the PC with all sampled data in packet form using USB protocols Keyboard Mouse Commands entered using keyboard and mouse to setup trigger conditions change display format save the waveform setup and hardcopies Outputs Monitor Display Displays captured data trigger signal cursors and basic Windows functions print save etc Prints the displayed waveform The PC is the user interface to the logic analyzer The conditioned signals are received by the PC and the raw data 1s extracted from the USB packets The raw data 1s then stored in memory A significant amount of data will be kept in memory such that all trigger conditions could be adequately displayed
7. Endpoint types used in the PC Based Logic Analyzer design include Wire and BufferedPipe The Wire function is an 8 bit connection that is only updated when the PC dictates this makes it ideal for set up information but poor for large data transfer The BufferedPipe function is an 8 bit connection that 1s started and stopped on the PC and the PC dictates how much data it would like to receive It is buffered on the sender in this case the FPGA in a FIFO First in First Out structure so that a large amount of data can be sent rapidly from the FPGA to the PC Figure 9 from the Opal Kelly user manual helps explain endpoints FrontPanel Software on PC FPGA object class pushbutton lt label gt Start lt label gt sposition 10 10 position lt size gt 80 20 lt size gt zendpoint 0x08 c endpoint lt bit gt 3 lt bit gt Verilog or VHDL okWireIn startEP ep addr 8 hOB ep data buttonwire Figure 9 Opal Kelly s user manual endpoint description Figure The FPGA is programmed with a bit file compiled from VHDL see appendix V and VI and runs in a state machine format The FPGA has four states it cycles through In the first state it transfers from JP2 where the comparison circuitry s data enters all thirty two bits into a temporary location This is to ensure that every sample occurs at the same time on all lines Also in the first state it places the first eight bits of the thirty two into the
8. SW2 Close end test toArray This function plots all the data in the linedat cQueues I have overloaded the function to provide better viewing capabilities public void pcblaPlot cQueue linedat VerticalGridType Plotting plotSurface Clear Grid Code Grid mygrid new Grid mygrid MajorGridPen new Pen Color Chartreuse 1 took the following line out because NPlot creates a dotted gray line by default This is what I wanted for the minor grid lines If desired the line could be uncommented mygrid MinorGridPen new Pen Color Blue om Note It seems from trial and error that HorizontalGridType actually refers to the vertical grid on the actual plot Likewise refers to the horizontal grid on the plot Thus HorizontalGridType is set to None a mygrid HorizontalGridType Grid GridType None mygrid VerticalGridType Grid GridType Fine plotSurface Add mygrid end Grid Code for int 1 071 lt numlines i lineplots i new StepPlot lineplots 1 OrdinateData linedat i ToArray lineplots 1 Pen new Pen linecolor i 1 plotSurface Add lineplots 1 j Axis Configure For now the x axis will be configured by default by NPlot left yaxis1 configuration LinearAxis lyl LinearAxis plotSurface Y Axis 1 ly1 WorldMin 0 0f ly1 LargeTickStep 1 ly1 NumberOfSmallTicks 2 ly1 HideTickText tr
9. hi_cs hi_irq gt hi_irq hi_busy gt hi_busy hi_addr gt hi_addr hi data gt hi data ti_clk gt 11 clk ti control gt ti control ti data gt ti data ep00 okWireln port map ti clk gt ti clk ti control gt ti control ti data gt ti data ep addr gt x 00 ep dataout gt ep00wire ep0l okWireln port map ti clk gt ti clk ti control gt ti control ti data gt ti data ep addr gt x 01 ep dataout gt ep01 wire ep20 okWireOut port map ti clk gt ti clk ti control gt ti control ti data gt ti data ep addr gt x 20 ep datain gt ep20wire epAO okBufferedPipeout port map end BEHV ti clk gt ti clk ti control gt ti control ti data gt ti data ep addr gt x AO ep clk gt clk2 ep reset gt reset ep write gt pipewrite ep datain gt pipeData ep full gt pipefull ep empty pipeEmpty ep status pipestatus Appendix VI Pin listing ucf listing XEM3001 Xilinx constraints file Pin mappings for the XEM3001 NET hi cl LOC P79 NET hi cs LOC P57 NET hi rdwr LOC P58 NET hi busy LOC P81 NET hi irq LOC P85 NET hi addr 0 LOC P64 NET hi addr 1 LOC P63 NET hi addr 2 LOC P62 NET hi addr 3 LOC P61 NET hi datax05 LOC P67 NET hi datax15 LOC P68 NET hi datax25 LOC P72 NET hi datax35 LOC P74 NET hi data
10. Call Pop to NO remove one item Store passed value in array Yes Increment qBack modulo ncremen capacity qFront modulo capacity Y ES true T baka Full false Increment Deceme Eum count End End Figure 18 Push Flowchart Figure 19 Pop Flowchart 17 In order for the data to be displayed it must be stored in a standard array The library contains a ToArray function that 1s overloaded twice to facilitate three logic analyzer operations plotting all acquired data centering the trigger point and scrolling see Appendix III pg 1 3 The basic ToArray function just copies the whole circular queue cQueue to an array This 1s done by copying the values of the cQueue one by one to an array and returning the array If cQueue 1s empty the function returns an array of 0 5 This avoids a null pointer reference when the data 1s plotted This 1s shown in Figure 20 Start Queue Yes Create new array of queue capacity d Create new array of 0 5 Copy values from queue array to new array Return array Figure 20 Basic ToArray Flowchart Displaying the whole buffer can sometimes be useful but more useful is displaying the trigger point at the middle of the screen This functionality 18 provided by the ToArray int trigPoin
11. FIFO buffer to be sent The remaining three states simply place the 2 3 and 4 bytes of the thirty two bits into the FIFO respectively The flow chart below Figure 10 shows the flow of the VHDL The clock speed on the FPGA is 48 MHz so the overall sampling rate is 12 MHz EVENT Clock Rising Edge Enter Next State Write to FIFO Buffer Command if enabled Perform action based on State State S3 Ybus 7 to Pipebuffer 0 to FIFO 15 to 8 Write Ybus to FIFO Pipebuffer 23 to 16 Pipebuffer 31 to 24 to FIFO to FIFO to Pipebuffer Figure 10 VHDL State machine flow chart Finally once the data is in the FIFO buffer whenever the PC requests for data to be sent ideally at cyclical intervals the buffer is transferred and the data from the sampled lines 1s now in the PC portion 10 Software The main program for the logic analyzer 1s written in C This language was chosen because Windows XPIM systems are the target environment and C a good IDE integrated development environment The Microsoft Visual Studio NET M IDE provides drag and drop GUI graphical user interface creation The one problem with using C is the Opal Kelly Front Panel API Application Program Interface 1s a static C library C cannot link to a static library it needs a DLL dynamic link library Opal Kelly developed a DLL version of the API but it was not ready early enough to be used in this project One solution to this problem was to h
12. LinearAxis lyl LinearAxis plotSurface Y Axis Afly1 WorldMin 0 0f ly1 LargeTickStep 1 ly1 NumberOfSmallTicks 2 ly1 HideTickText true ly1 WorldMax 31 66 ly1 WorldMin 1 LinearAxis 1x1 LinearAxis plotSurface XAxis1 Ix1 HideTickText true end Axis Configure plotSurface Refresh end Plotting j This overload of the function is used to provide the scrolling through linedat public void pcblaPlot cQueue linedat int viewfront bool dummyvariable Plotting plotSurface Clear Grid Code Grid mygrid new Grid mygrid MajorGridPen new Pen Color Chartreuse took the following line out because NPlot creates a dotted gray line by default This is what I wanted for the minor grid lines If desired the line could be uncommented mygrid MinorGridPen new Pen Color Blue Note It seems from trial and error that HorizontalGridType actually refers to the vertical grid on the actual plot Likewise VerticalGridType refers to the horizontal grid on the plot Thus HorizontalGridType is set to None zi mygrid HorizontalGridType Grid GridType None mygrid VerticalGridType Grid GridType Fine plotSurface Add mygrid end Grid Code for int 1 0 1 lt numlines i lineplots 1 new StepPlot lineplots 1 OrdinateData linedat 1 ToArray viewfront false lineplots 1 Pen new Pen lin
13. able to transfer the full sixteen lines of data into the PC It also uses a state machine instead of a counter library IEEE use IEEE std logic 1164 all use IEEE std logic arith all use IEEE std logic misc all use IEEE std logic unsigned all entity Test4 1s port hi clk in STD LOGIC hi cs in STD LOGIC hi rdwr in STD LOGIC hi busy out STD LOGIC hi irq out STD LOGIC hi addr in STD LOGIC VECTOR Q downto 0 hi data inout STD LOGIC VECTOR 7 downto 0 led out STD LOGIC VECTOR 7 downto 0 ybus in STD LOGIC VECTOR 31 downto 0 xbus out STD LOGIC VECTOR 31 downto 24 button in STD LOGIC VECTOR Q downto 0 clk1 in STD LOGIC end Test4 architecture BEHV of Test4 1s type STATE TYPE is S1 S2 S3 S4 attribute ENUM ENCODING STRING attribute ENUM_ENCODING of STATE TYPE type is 00 01 10 11 signal CS NS STATE TYPE component okHostInterface port hi clk In std logic hi rdwr In std logic hi cs In std logic hi irq out std logic hi busy out std logic hi addr In std logic vector 3 downto 0 hi data inout std logic vector 7 downto 0 t clk out std logic ti control out std logic vector 12 downto 0 t data Inout std logic vector 7 downto 0 end component component okWireln port t clk In std logic ti control In std logic vector 12 downto 0 ti data In std logic vector 7 downto 0 ep addr In std logic vector 7 downto 0
14. based on the samples contained in memory The user can set the trigger conditions using the keyboard the mouse and the GUI When the trigger condition is met the software will display the samples that are relevant to the time at which the trigger condition was met The software will also display a user controlled length of data both before and after the trigger condition This allows the user to see data prior to the trigger point to see data after the trigger or see a percentage of data before and after the trigger point The displayed image 1s going to be based on the user s choice of sample rate If a slower sample rate 1s chosen then the user will be able to see a longer length of time in around each trigger but with less resolution if a faster rate is chosen more detail is shown but the length of time displayed around a trigger is less More detail in each section of the block diagram can be seen in the Figure 7 and Figure 8 C Start D C San Keyboard or I mouse entry Store as a 32 bit unsigned integer Set trig ger Ma display point output type number of signals to Remove USB display Header Bits C End P C End b Figure 7 Control Block Diagram Figure 8 USB Data Acquisition Sat o Store USB Data i in Temp Temp amp Mask Adjust queue indices l Store Temp to the front of Line k l Mask 4
15. fact that there 1s no High Z there is no combinational logic needed Data is transfered via the pipe function clk2 ti clk makes clock for FIFO same as system clock Writes data regarding the state of the FIFO to the wire for PC to read ep20wire 0000 amp pipeStatus 3 downto 0 led lt 11 amp not pipeStatus 3 downto O amp pipefull amp pipeEmpty Puts data from wire from PC into the reset value reset not button 0 or not button 1 or not button 2 or not button 3 pipewrite lt epOl wire 0 xbus testcount The state machine sets it up so it reads all 16 lines into a buffer then each state 1t writes one of the bytes into the FIFO buffer SYNC PROC process clk1 begin if rising edge clk1 then CS 2 NS testcount lt testcount 1 end 1f end process COMB PROC process CS begin case CS is when SI gt pipebuffer not ybus reads in all data pipeData not ybus 7 downto 0 NS lt S2 when 2 gt pipeData pipebuffer 15 downto 8 write second byte NS S3 when 3 gt pipeData pipebuffer 23 downto 16 write thrid byte NS S4 when S4 gt pipeData pipebuffer 31 downto 24 write fourth byte NS FSL end case end process Instantiate the okHostInterface and connect endpoints to the target interface okHI okHostInterface port map hi_clk gt hi_clk hi_rdwr gt hi_rdwr hi_cs gt
16. from sixteen to four by shifting the data bits as shown in Figure 13 Shifting the mask selects different two data bits representing a different probe line 14 each time through the masking loop The masking loop happens four times per byte because there are eight bits in a byte and two bits are analyzed at a time Now that the data 1s stored in a text file the C program must read and store it for plotting CirQlar Since a logic analyzer handles large streams of data it must use an efficient storage structure One such structure 1s a circular queue A queue 1s FIFO First In First Out memory structure Each time data 1s removed from the queue all the data values must be shifted so that the first element is in the first index position The time required to shift data increases as more data elements are added to the queue A circular queue removes the need for shifting the data when an element 1s removed because the front index 1s shifted instead of the data This means that no matter how many data elements the queue contains the complexity 1s constant A circular queue requires two basic functions Push and Pop Push adds a new value to the back of the queue and Pop increments the pointer to the first element For example an empty circular queue with six elements will look like Figure 14 qg Front and qBack point to the same element and the count of elements 1s zero qFront qBack lo a 2 Figure 14 Circular Queue Initial P
17. on channel 2 an identical signal It should be noted that the line experiencing the cross talk was not connected or floating if connected to a signal or ground cross talk will have much less effect By running ground lines between the pins cross talk can be reduced if not eliminated in future designs However the probe connection did accomplish the major goal of successfully transferring signals into the comparison circuitry Tek Run Trig d AA 3 76 1 86V Ch1 Freq 1 697MHz 2 1 00V Ma00Ons A Chl 7 1 06 vi 5 May 2005 i 720 0000ns 10 47 22 Figure 5 Cross talk on parallel probe lines Comparison Circuitry The comparison circuitry portion of the pod determines which of three states the sixteen sampled lines are in The three states the comparison circuitry checks for are Low Indeterminate and High it should be noted that the threshold for the states is based on the current selection of CMOS or TTL To accomplish this a resistor tree is set up to create the threshold voltages for both CMOS and TTL These voltages are tied into banks of comparators two per line The flow of the system can be seen in the Figure 6 The signal from a DUT s data line comes in through the probe connection at the lower left of the figure The signal enters both comparators which determine if it 1s V High M dw To FPGA From Probe Figure 6 Comparison Circuitry exceeding the low and high logic thresholds This resul
18. sixteen digital lines configured to respond to a TTL and or CMOS signal levels It samples them synchronously using a designated clock line or asynchronously using an internal clock For synchronous mode the clock signal coming from the device under test DUT dictates when samples are taken thus creating the appearance that all signals on all lines change on the clock This 1s useful for simple testing it allows the user to quickly see what happens in the device through each of its clock cycles In asynchronous mode all sixteen lines are sample lines An internal clock set at a very high frequency dictates when samples will be taken This 1s useful for allowing the user to see the independent activity of lines during a DUT s clock cycle Moreover this allows for much more detailed debugging The comparison circuit determines one of four states for each line The comparator can classify signals as high low intermediate signal between high and low thresholds or no signal a High Z condition Once the state has been determined the data 1s sent in the form of 2 bits into a buffer Once several samples for all sixteen lines have been collected in the buffer the buffer sends the data to the PC through the USB interface More detail on the separate sections can be seen in figures below Designated Clock Lj we Synchronous Internal asynchronous Clock switch To Buffer Sampled lines 2 bits KOS High Comparison circuit Combinational
19. 120 1 lt xfer_len pkt_len 1 len pkt len ret2 xem ReadFromPipeOut Oxa0 len buf2 if false ret2 cout lt lt ReadFromPipeOut failed An break j if pkt len len cout Wanted pkt len but got len diff pkt len len lt lt n break j xem SetWireln Value Ox01 0x00 set the write to buffer signal on FPGA to 0 1e don t write xem gt UpdateWirelIns dump the whole buffer unparsed to a text file for int 1 0 1 lt pkt_len i j bufdump lt lt buf2 1 Data parsing code for text file int numlines 16 unsigned short parse data unsigned short mask OxCO unsigned short pd int cnt 0 for int 1 Oji pkt len i cnt parse data buf2 1 mask OxCO for int 0 j lt 4 j pd parse_data amp mask pd pd gt gt 6 2 mask mask gt gt 2 if G 0 amp amp j 0 amp amp cnt 0 goto gohere switch pd case Ox00 outFile lt lt 0 00 if cnt 4 outFile lt lt break case Ox01 outFile lt lt O 33 if cnt 4 outFile lt lt break case 0x02 outFile lt lt O 66 if cnt 4 outFile xx break case Ox03 outFile 1 00 if cnt 2 4 outFile xx break gohere default outFile Probe Line Parsing Error j if cnt 4 outFile lt lt endl cnt 0 j j cnt outFile 0 3
20. 3 delete buf2 cout OK endl End Opal Kelley Pipe Code bufdump close cout lt lt close file outFile close cout lt lt OK lt lt endl int x cin gt gt x return 0 Appendix III cirQlar Code cirQlar Description A circular queue library that allows indexing within the queue to accomodate a trigger index Author Jason Nielsen Creation Date 2 10 05 Revision 3 22 05 Changed the storage array to double instead of int because of the way a I was implementing the plot in pcbla Revision 4 11 05 Added a count variable to track the number of elements in the queue P Modified the toArray method so that it returns an array if the queue is full ki Made it throw away the oldest data 1f the queue 1s full and a new value is pushed Revision 4 21 05 Added overloads for the ToArray function that will provide pcbla specific functionality Made a qBackMinus function to help with triggering using System namespace cirQlar summary Provide circular queue functions lt summary gt public class cQueue Constructor public cQueue fint qArray new int capacity this qfront_ 0 this qback_ 0 this qTriggerPoint 0 this gArray new double 10000 j This funtion returns an array of all the elements in the queue public double ToArray double arr if this qcount_ 0 added this so a
21. OC P167 LOC P166 LOC P165 LOC P162 LOC P184 LOC P52 LOC P51 LOC P50 LOC P48 LOC P46 LOC P45 LOC P44 LOC P43 LOC P42 LOC P40 LOC P39 LOC P37 LOC P36 LOC P35 LOC P34 LOC P33 LOC P31 LOC P29 LOC P28 LOC P277 LOC P26 LOC P24 LOC PR LOC P21 LOC P20 LOC P19 LOC P18 LOC P16 LOC P15 LOC P13 LOC P12 LOC P11 LOC P10 NET ybus 33 NET ybus 34 NET ybus 35 NET xclk1 NET xbus lt 0 gt NET xbus 1 NET xbus lt 2 gt NET xbus lt 3 gt NET xbus lt 4 gt NET xbus lt 5 gt NET xbus lt 6 gt NET xbus lt 7 gt NET xbus lt 8 gt NET xbus 9 NET xbus 10 NET xbus 11 NET xbus lt 12 gt NET xbus 13 NET xbus lt 14 gt NET xbus lt 15 gt NET xbus lt 16 gt NET xbus 17 NET xbus lt 18 gt NET xbus lt 19 gt NET xbus lt 20 gt NET xbus lt 21 gt NET xbus 22 NET xbus lt 23 gt NET xbus lt 24 gt NET xbus lt 25 gt NET xbus lt 26 gt NET xbus lt 27 gt NET xbus lt 28 gt NET xbus lt 29 gt NET xbus lt 30 gt NET xbus lt 31 gt NET xbus 32 NET xbus 33 NET xbus lt 34 gt NET xbus lt 35 gt LOC PO LOC P7 LOC P5 LOC P180 LOC P156 LOC Pl LOC P154 LOC P152 LOC
22. P150 LOC P149 LOC P148 LOC z P147 LOC P146 LOC P144 LOC P143 LOC P141 LOC P140 LOC P139 LOC P138 LOC P137 LOC PIOS LOC P133 LOC P132 LOC P131 LOC P130 LOC P128 LOC P126 LOC PRO LOC P124 LOC P123 LOC P122 LOC PEO LOC P119 LOC P117 LOC P116 LOC P115 LOC P114 LOC P113 LOC P111 LOC P109 Peripherals NET led 0 LOC P205 NET led 1 LOC P204 NET led lt 2 gt LOC P203 NET led lt 3 gt LOC P200 NET led lt 4 gt LOC P199 NET led 5 LOC P198 NET led lt 6 gt LOC P197 NET led lt 7 gt LOC P196 NET button lt 0 gt LOC P194 NET buttonx15 LOC P191 NET button 2 LOC P190 NET button 3 LOC P189 Appendix VII Original Functional Description PC Based Logic Analyzer Functional Description Advisors Dr James H Irwin Mr Jos S nchez Team Members Jeffery Earleson Jason Nielsen October 28 2004 EE 451 Bradley University Electrical and Computer Engineering Department Introduction A logic analyzer is an instrument that displays digital signals It functions much like an analog oscilloscope except it only displays four levels low high tri state and indeterminate it also samples more lines This project will create a PC based logic analyzer for use in Junior laboratory It will hav
23. PC Based Logic Analyzer Final Report Team Members Jeff Earleson Jason Nielsen Advisors Dr James Irwin Mr Jos Sanchez May 13 2005 EE 452 Bradley University Electrical and Computer Engineering Abstract The PC Based Logic Analyzer 1s a device that determines the logical state High Low or Unknown of a signal then displays with respect to time the state in a Graphical User Interface GUI on a Personal Computer PC A Field Programmable Gate Array FPGA and external circuitry determine the logical state then the PC communicates with the FPGA using Universal Serial Bus 2 0 transferring the resulting logical states to the PC The PC GUI written in the language of C interprets the stream of data and based upon a triggering event displays pertinent data on the screen Outline Introduction Project Description Hardware Design Software Design Conclusions Appendix Appendix I FPGA Config Code Appendix II Pcbladata Code Appendix III CirQlar Code Appendix IV Pcbla Code Appendix V VHDL Code Appendix VI Pin Listing ucf Appendix VII Original Functional Description Appendix VIII Original System Block Diagrams Appendix IX Original Project Proposal A I A TI A I A IV A V A VI A VII A VIII A IX p 11 22 TD NI NI pi po psg mm rar I ha a OO PP m O A A Jesse oo Introduction To have a better understanding of what a PC based logic analyzer 1s it helps to understand what
24. a logic analyzer 1s and its purpose in the electrical engineering world With these goals in mind a definition of logic analyzers is in order A logic analyzer 1s a device that through sampling allows a user to view the logical values High Low Intermediate High Z silence and transitions on a digital device A logic analyzer is very similar in nature to an oscilloscope Both devices are tools for debugging testing and verifying electronics They differ on a few key points notably a logic analyzer only allows a user to view logical states whereas oscilloscopes show voltage levels and logic analyzers sample many more lines than typical oscilloscopes As was earlier stated logic analyzers function as a debugging instrument Common situations for which a logic analyzer would be ideal are those where multiple line testing 1s needed but logical values not voltage levels will suffice Examples of this would be debugging any sort of microcontroller combinational logic circuit or entire device such as a PCI Peripheral Component Interconnect card To allow a user to debug a digital device the logical analyzer displays all lines being sampled using a GUI Graphical User Interface It is through this GUI that a user navigates through the sampled logical data discovers possible discrepancies on data lines or timing issues between lines Another important topic necessary to better understand logic analyzers 1s triggering Triggering is a metho
25. at program the appropriate error message is reported to the user public void configFPGA Process proc null ProcessStartInfo procInfo new ProcessStartInfo fpga config exe procInfo UseShellExecute false procInfo CreateNoWindow true proc Process Start procInfo proc WaitForExit int exitcode proc ExitCode if exitcode 4 MessageBox Show Opening XEM3001 failed exitcode times Please check that the logic analyzer 1s plugged in j else if exitcode 24 MessageBox Show Configuring FPGA failed exitcode 20 times Check that the test4 bit file is in the same folder as fpga_config exe j j This function calls the C pcbladata exe which will read data from the XEM3001 and store it in a text file public void getData Process proc null ProcessStartInfo procInfo new ProcessStartInfo pcbladata exe procInfo UseShellExecute false procInfo CreateNoWindow true proc Process Start procInfo proc WaitForExit j This function reads the data from the text file and stores it in the array of cQueues called linedat This array of cQueues represents all the probe lines As the function is pushing the data onto the queues it looks for a rising edge a 0 to l transition of line zero When it find one it sets the index of the 1 to the trigger point If there is more than one rising edge of linedat 0 the most most recent one will be set to the tri
26. ata and freeze the display The display can still be zoomed and the cursors moved Appendix VIII Original System Block Diagrams PC Based Logic Analyzer Complete System Level Block Diagram Advisors Dr James H Irwin Mr Jos S nchez Team Members Jeffery Earleson Jason Nielsen November 23 2004 EE 451 Bradley University Electrical and Computer Engineering Department Introduction A logic analyzer is an instrument that displays digital signals It functions much like an analog oscilloscope except it only displays four levels low high tri state and indeterminate it also samples more lines This project will create a PC based logic analyzer for use in Junior laboratory It will have external conditioning hardware known as a POD connected to the PC The PC will provide a Graphical User Interface GUI triggering and signal display This data flow is seen in Figure 1 POD PC Analog Signals Conditioned Signals Monitor GUI Keyboard Printer Mouse Storage Figure 1 System Block Diagram Inputs Analog Signals ignals on the POD s probes These can be TTL or CMOS based PC Commands Commands entered using keyboard and mouse Outputs Monitor Display Displays captured data trigger signal cursors and basic Windows functions print save etc Prints the displayed waveform System Description POD This will accept analog signa
27. ave the C main program call C programs would communicate with the XEM 3001 There are two operations that must be completed by the C programs FPGA configuration and data collection FPGA Configuration The FPGA on the XEM 3001 board is a Xilinx Inc Spartan 3 A synthesized BIT file must be loaded into the Spartan in order for the FPGA to operate The Front Panel API provides functions for loading a BIT file into the Spartan Figure 11 shows the process for configuring the Spartan Space left black for formatting Figure 11 on next page 11 Stat i Open XEM3001 No ConfigureFPGA test4 bit lt Fain gt No Report failure 24 End Figure 11 FPGA Configure Flowchart Report failure 4 If opening an instance of the XEM 3001 fails an error code of 4 is reported This error code tells the user via a message box to check that the XEM 3001 board is connected to the USB The ConfigureFPGA function tries to load test4 bit to the Spartan 3 see Appendix I for syntax If this fails a message box informs the user This error condition should not happen unless the bit file becomes corrupted or there is a more serious hardware problem If no errors occur the Spartan is configured and the XEM 3001 is ready to gather data at the user s command Data Collection The data collection program acquires data using a pipe style data transfer Thi
28. c analyzer for use in Junior laboratory It will have external conditioning hardware known as a POD connected to the PC The PC will provide a Graphical User Interface GUI triggering and signal display This data flow is seen in Figure 1 POD PC Analog Signals Conditioned Signals Monitor GUI Keyboard Printer Mouse Storage Figure 1 System Block Diagram Inputs Analog Signals ignals on the POD s probes These can be TTL or CMOS based PC Commands Commands entered using keyboard and mouse Outputs Monitor Display Displays captured data trigger signal cursors and basic Windows functions print save etc Prints the displayed waveform System Description POD This will accept analog signals on 8 16 data lines The signals originate from TTL or CMOS based circuits The POD will condition the signal to be transmitted to the PC via USB PC The software will receive conditioned signals and display them in a user friendly manner It will provide several forms of triggering cursors zooming etc and standard window features 17 Modes of Operation Setup Mode In this mode the user selects the desired threshold levels for the analog signal type TTL or CMOS the number of lines to be sampled the trigger condition and the sampling method synchronous or asynchronous Sample Mode In this mode started by the user the analyzer
29. c bool qEmpty get return gempty private bool qempty_ true public bool qFull private bool qfull_ false end Instance Specific Properties get return qfull Appendix IV pcbla Code using System using System Drawing using System Drawing Drawing2D using System Collections using System ComponentModel using System Windows Forms using System Drawing Printing using System Data using NPlot using System IO using System Reflection using System Diagnostics using cirQlar namespace pcbla summary Summary description for mainForm lt summary gt public class mainForm System Windows Forms Form form designer added objects declaration private System Windows Forms MainMenu mainMenu private System Windows Forms Menultem menultem1 private System Windows Forms Menultem menultem2 private System Windows Forms Menultem menultem3 private System Windows Forms Menultem menultem4 private System Windows Forms Menultem menultem5 private System Windows Forms Menultem menultem6 private System Windows Forms Menultem menultem7 private NPlot Windows PlotSurface2D plotSurface private System Windows Forms Button bReload private System Windows Forms HScrollBar sbHistory private System Windows Forms Label IStatus private System Windows Forms Button bRunTilTrig private System Windows Forms Button bRecenterTrigger private System Windows For
30. c4 LOC P86 NET hi datac5 LOC P87 NET hi datac6 LOC P90 NET hi datax75 LOC P92 Hoo PLL Clock pins S NET clk1 LOC P80 NET clk2 LOC P77 NET clk3 LOC P76 Hoo Port JPI zbus NET zclk1 LOC P183 NET zclk2 LOC P181 NET zbus lt 0 gt LOC P187 NET zbus lt 1 gt LOC P185 NET zbus lt 2 gt LOC P182 NET zbus lt 3 gt LOC P178 NET zbus lt 4 gt LOC P176 NET zbus lt 5 gt LOC P175 NET zbus lt 6 gt NET zbus lt 7 gt NET zbus lt 8 gt NET zbus lt 9 gt NET zbus lt 10 gt NET zbus lt 11 gt NET zbus lt 12 gt NET zbus lt 13 gt NET yclk1 NET ybus lt 0 gt NET ybus lt 1 gt NET ybus lt 2 gt NET ybus lt 3 gt NET ybus lt 4 gt NET ybus lt 5 gt NET ybus lt 6 gt NET ybus lt 7 gt NET ybus lt 8 gt NET ybus lt 9 gt NET ybus lt 10 gt NET ybus lt 11 gt NET ybus lt 12 gt NET ybus lt 13 gt NET ybus lt 14 gt NET ybus 15 NET ybus lt 16 gt NET ybus lt 17 gt NET ybus lt 18 gt NET ybus 19 NET ybus 20 NET ybus lt 21 gt NET ybus lt 22 gt NET ybus 23 NET ybus lt 24 gt NET ybus lt 25 gt NET ybus lt 26 gt NET ybus lt 27 gt NET ybus lt 28 gt NET ybus lt 29 gt NET ybus 30 NET ybus lt 31 gt NET ybus lt 32 gt LOC P172 LOC P171 LOC P169 LOC P168 L
31. cal and Computer Engineering Laboratories It utilizes an external pod for sampling and software written for a PC Designed to cost less than 500 this logic analyzer s functionality is geared for an academic setting where not all features of commercial logical analyzers are necessary This project achieves this goal by designating a significant portion of the project to be implemented on a PC thus reducing the cost of the project to the construction costs of the external pod Figure 2 is a block diagram of our system and shows the relationship between pod and PC and the overall flow of the system Table 1 designates the inputs outputs and significant internal signals POD PC Analog Signals Conditioned Signals Monitor GUI Keyboard Mouse Figure 2 Overall System Block Diagram Inputs Analog Signals signals on the POD s probes These can be TTL or CMOS based PC Commands Commands entered using keyboard and mouse Transferred Signals Conditioned Signals Signals sent via USB containing state information for all sampled lines Outputs Monitor Display Displays captured data trigger signal cursors and basic Windows functions print save etc Table 1 Inputs Outputs and Transferred Signals POD Analog Signals Conditioned sit Figure 3 Pod portion of the design Pod Hardware Design The P
32. collects the conditioned signals based on the selected triggering method Display Mode This mode is entered automatically after the buffer 1s filled and the trigger occurs The display can be zoomed and the cursors moved POD Functionality Sampled lines Comparison USB Interface Circuit Figure 2 POD Block Diagram Data line to PC Inputs Sixteen lines These are the lines that are of interest to the user They can be TTL or CMOS type In addition one of the signals may be designated as a clock signal on the target device and can be used for synchronous sampling Outputs Data line to PC This is the sampled data in a 2 bit per sample per line form A packet is sent on this line and USB protocols are used The POD is the sampling device for the logic analyzer The POD has eight or sixteen digital lines configured to respond to a TTL and or CMOS signal levels It samples them synchronously using a designated clock line or asynchronously using an internal clock For synchronous mode the clock signal coming from the device under test DUT dictates when samples are taken thus creating the appearance that all signals on all lines change on the clock This 1s useful for simple testing it allows the user to quickly see what happens in the device through each of its clock cycles In asynchronous mode all sixteen lines are sample lines An internal clock set at a very high frequency dictates when samples will be taken This 1s u
33. combinational logic Hardware options controlled by software Display window resize Variable trigger position in the buffer Rearrange line locations on the display Trigger on one signal line Save wavelorm as an image Zoom on waveform Tertiary 1 2 3 a 5 Program Decoding Tristate detection Super hardware idiot protection Save the whole buffer data in the image so the whole buffer can be regenerated when loaded into the PCBLA software Option to change the number of lines sampled to any number divisible by two 18
34. d of organizing information in such a way such that a single events or cyclical events are displayed coherently Since logic analyzers operate similarly to oscilloscopes the difference between an untriggered and triggered display is shown in the figure below Figure 1 Untriggerea PORWR ORE hes Display ea oz S Sep MT Figure 1 Unrigged vs Triggered Displays As the figure shows in an untriggered case the data streams across the display in a way that can be nearly impossible to decipher The triggered display by triggering on a voltage threshold shows signals in a much more coherent manner Logic analyzers work in a similar manner however they trigger on logical events rather than voltage thresholds A logical event consists of several different situations such as a single line changing values a clock signal would be a common example of this or a combination of many lines changing to specified values The result is data is organized by the clock signal or by a specific situation occurring Commercial logic analyzers are quite expensive common logic analyzers cost several thousand dollars with top of line logic analyzers costing upwards of 50 000 The high cost of commercial logic analyzers has caused a need for low cost logic analyzers in an academic setting This is where this project the PC Based Logic Analyzer Project fits in Project Description The PC Based Logic Analyzer is designed for use in Bradley University Electri
35. e external conditioning hardware known as a POD connected to the PC The PC will provide a Graphical User Interface GUI triggering and signal display This data flow is seen in Figure 1 POD PC Analog Signals Conditioned Signals Monitor GUI Keyboard Printer Mouse Storage Figure 1 System Block Diagram Inputs Analog Signals ignals on the POD s probes These can be TTL or CMOS based PC Commands Commands entered using keyboard and mouse Outputs Monitor Display Displays captured data trigger signal cursors and basic Windows functions print save etc Prints the displayed waveform System Description POD This will accept analog signals on 8 16 data lines The signals originate from TTL or CMOS based circuits The POD will condition the signal to be transmitted to the PC via USB PC The software will receive conditioned signals and display them in a user friendly manner It will provide several forms of triggering cursors zooming etc and standard window features Modes of Operation Setup Mode In this mode the user selects the desired threshold levels for the analog signal type TTL or CMOS the number of lines to be sampled and the triggering method Run Mode In this mode the analyzer displays the conditioned signals based on the selected triggering method Stop Mode This mode allows the user to stop collecting d
36. e rate 1s chosen then the user will be able to see a longer length of time in around each trigger but with less resolution if a faster rate is chosen more detail is shown but the length of time displayed around a trigger is less More detail in each section of the block diagram can be seen in the Figure 7 and Figure 8 C Start D Start Keyboard or I mouse entry Store as a 32 bit unsigned integer Set trig ger say display point output type number of signals to Remove USB display Header Bits C End P C End P Figure 7 Control Block Diagram Figure 8 USB Data Acquisition 15 Sat o Store USB Data i in Temp Temp amp Mask Adjust queue indices l Store Temp to the front of Line k l Mask 4 Increment k Yes No Increment 1 Is 1 lt USB data size Doe o Figure 9 Memory Store Yes Probe Data 1 Trigger Mask Yes Increment i Isi lt Front of Probe Data v Store trigger index No Done Figure 10 Trigger Block C Stt Place trigger Index at desired display position y Draw every tenth data point pre and post of trigger index
37. ecolor i 1 plotSurface Add lineplots 1 j Axis Configure For now the x axis will be configured by default by NPlot occurs left yaxis1 configuration LinearAxis lyl LinearAxis plotSurface Y Axis 1 ly1 WorldMin 0 0f ly1 LargeTickStep 1 lyl NumberOfSmallTicks 2 ly 1 HideTickText true ly1 WorldMax 31 66 ly1 WorldMin 1 LinearAxis 1x1 LinearAxis plotSurface X Axis 1 Ix1 HideTickText true end Axis Configure plotSurface Refresh end Plotting j This handles repositioning GUI elements when a resize event occurs This handler is attached to the window in the main function at the top of the page Note that every element must be accounted for when a resize or else a button might end up in the plot or something of that nature private void ResizeHandler object sender System EventArgs e plotSurface Width this Width 25 plotSurface Height this Height 110 bReload Top this Height 50 sbHistory Top this Height 104 sbHistory Width this Width 25 IqTriggerPoint Top this Height 50 bRecenterTrigger Top this Height 50 bRecenterTrigger Left this Width 330 bRunTilTrig Top this Height 50 bRunTilTrig Left this Width 225 IStatus Top this Height 50 IStatus Left this Width 110 sbZoom Top this Height 50 j summary Clean up any resources being used This func
38. ferring the data to the PC via USB Universal Serial Bus The XEM 3001 incorporates a Xilinx Spartan 3 FPGA and a USB 2 0 transfer chip onto a single board Not only does it provide the connections between the FPGA and the USB 2 0 chip but it provides functions on both the FPGA and PC side to interface the PC and FPGA seamlessly through USB The way the XEM 3001 interfaces 1s through endpoints In a typical FPGA inputs and outputs are assigned to pins which correspond to a physical pin on the FPGA In the XEM 3001 s case all of these pins are predetermined Many of them are still available for user inputs and outputs on three I O blocks JP1 JP2 and JP3 see figure 8 3200 00 4ml 680800880880888888808828082868 A AE Hi 3 a die He g HE EN bo EE E e ee o a E HE 2 ci sea Bus icc san a R E o rs i 4500 00 m1 Figure 8 Layout of Opal Kelly XEM 3001 However many of the pins are permanently used by the interface to the PC These inaccessible pins are then used as endpoints for the exchange of data between the PC and FPGA These endpoints are described on the FPGA side by having VHDL Very High Level Integrated Circuit Hardware Description Language libraries define functions which correlate to different types of endpoints On the PC C libraries and now DLLs dynamic link library define the functions to be able to use the same endpoints to communicate with the FPGA in real time
39. fileName fileName data txt the bufdump txt file provides a raw dump of the acquired data for debugging purposes string fileNamebd fileNamebd bufdump txt ofstream bufdump cout lt lt Opening File bufdump open fileNamebd c str if bufdump is open Q cout lt lt ERROR Cannot open file for writing lt lt endl return 1 cout lt lt OK lt lt endl ofstream outFile cout lt lt Opening File outFile open fileName c str if loutFile is open cout ERROR Cannot open file for writing endl return 1 cout lt lt OK lt lt endl Opal Kelly pipe code unsigned char buf long xfer len 1024 long pkt len 1024 long len Pipe Out Test unsigned char buf2 buf2 new unsigned char pkt len Perform transfer bool ret2 cout Testing pipe read Create an instance of the okCUSbXEM okCUsbXEM xem new okCUsbXEM Open the first available device xem Open 0 J s This was commented out because it was just used for testing this function 1s now being handled by fpga config exe Download a configuration file to the FPGA int configfailcnt 20 bool check false while check false check xem gt ConfigureFPGA test4 bit configfailcnt if configfailcnt 24 return configfailcnt T xem 5SetWireIn Value 0x01 0x01 xem gt Update Wirelns for int
40. gger point public void fillLinedat string filename bool trigger read txt file to fill cQueues StreamReader SR new StreamReader filename string myval SR ReadLine string mystrs double mydouble while myval null mystrs myval Split for int 1 0 1 lt mystrs Length i mydouble Convert ToDouble mystrs i linedat 1 Push mydouble 1 2 finds rising edge O to 1 transition of line zero if 0 amp amp trigger if linedat 0 qArray linedat 0 qBackMinus 1 amp amp linedat O qArray linedat 0 qBackMinus 2 0 j linedat 0 qTriggerPoint linedat 0 qBack j j j myval SR ReadLine SR Close end Read File to Fill cQueues This function writes all the linedat buffers to a text file This function was used for debugging but it can also be used for a Save data menu function It would required a few changes related to letting the user pick the file name but other than that is ready to go A load data function could also be used created using the fillLinedat function so the user could view old saved data public void writeLinedat test toArray function Stream Writer SW2 new StreamWiriter linedat txt double myarra for int 1 Oji numlines i myarra linedat i ToArray for int j 0 j lt myarra Length j SW2 Write myarra 31 SW2 Write j SW2 WriteLine j
41. is menultem2 this menultem3 menultem1 this menulteml Index 0 this menultem1 MenulItems AddRange new System Windows Forms Menultem this menultem4 this menultemS this menultem6 this menultem7 this menultem1 Text File menultem4 i this menultem4 Index 0 this menultem4 Text New menultem5 this menultem5 Index 1 this menultem5 Text Open menultem6 this menultem6 Index 2 this menultem6 Shortcut System Windows Forms Shortcut CtrlS this menultem6 Text Save menuItem7 this menultem7 Index 3 this menultem7 Text Print menultem2 this menultem2 Index 1 this menultem2 Text Edit menultem3 this menultem3 Index 2 this menultem3 Text View plotSurface 10 this plotSurface AllowSelection false this plotSurface AutoScaleAutoGeneratedAxes false this plotSurface AutoScaleTitle false this plotSurface BackColor System Drawing SystemColors ControlLightLight this plotSurface Legend null this plotSurface Location new System Drawing Point 8 8 this plotSurface Name plotSurface this plotSurface Padding 10 this plotSurface RightMenu null this plotSurface ShowCoordinates false this plotSurface Size new System Drawing Size 664 328 this plotSurface SmoothingMode System Drawing Drawing2D SmoothingMode None this plotSurface TabIndex 0
42. lay Control Control Mouse Output Control 14 Figure 6 PC Block Diagram PC Inputs Conditioned Signals Signals sent from the POD to the PC with all sampled data in packet form using USB protocols Keyboard Mouse Commands entered using keyboard and mouse to setup trigger conditions change display format save the waveform setup and hardcopies Outputs Monitor Display Displays captured data trigger signal cursors and basic Windows functions print save etc Prints the displayed waveform The PC is the user interface to the logic analyzer The conditioned signals are received by the PC and the raw data 1s extracted from the USB packets The raw data 1s then stored in memory A significant amount of data will be kept in memory such that all trigger conditions could be adequately displayed based on the samples contained in memory The user can set the trigger conditions using the keyboard the mouse and the GUI When the trigger condition is met the software will display the samples that are relevant to the time at which the trigger condition was met The software will also display a user controlled length of data both before and after the trigger condition This allows the user to see data prior to the trigger point to see data after the trigger or see a percentage of data before and after the trigger point The displayed image 1s going to be based on the user s choice of sample rate If a slower sampl
43. ls on 8 16 data lines The signals originate from TTL or CMOS based circuits The POD will condition the signal to be transmitted to the PC via USB PC The software will receive conditioned signals and display them in a user friendly manner It will provide several forms of triggering cursors zooming etc and standard window features Modes of Operation Setup Mode In this mode the user selects the desired threshold levels for the analog signal type TTL or CMOS the number of lines to be sampled the trigger condition and the sampling method synchronous or asynchronous Sample Mode In this mode started by the user the analyzer collects the conditioned signals based on the selected triggering method Display Mode This mode is entered automatically after the buffer 1s filled and the trigger occurs The display can be zoomed and the cursors moved POD Functionality Sampled lines Comparison USB Interface Circuit Figure 2 POD Block Diagram Data line to PC Inputs Sixteen lines These are the lines that are of interest to the user They can be TTL or CMOS type In addition one of the signals may be designated as a clock signal on the target device and can be used for synchronous sampling Outputs Data line to PC This is the sampled data in a 2 bit per sample per line form A packet is sent on this line and USB protocols are used The POD is the sampling device for the logic analyzer The POD has eight or
44. ms Label lqTriggerPoint private System Windows Forms HScrollBar sbZoom end form designer added objects declaration const int numlines 16 defines the number of lines StepPlot lineplots new StepPlot numlines Color linecolor 2 new Color 16 Color Red Color Blue Color Green Color Purple Color DarkGreen Color DarkBlue Color Dark Magenta Color MidnightBlue Color Red Color Blue Color Green Color Purple Color DarkGreen Color DarkBlue Color DarkM agenta Color MidnightBlue something Declare cQueues array cQueue linedat new cQueue numlines double pushval 0 0 const int trigline 0 lt summary gt Required designer variable lt summary gt private System ComponentModel Container components null public mainForm Required for Windows Form Designer support InitializeComponent TODO Add any constructor code after InitializeComponent call The following line adds a resize event handler to mainForm The code for this handler is at the bottom of this code this Resize new System EventHandler this ResizeHandler Declare linedat elements for int 1 0 1 lt numlines i j linedat i 2 new cQueue sbZoom Value linedat 0 q ViewsSize this configFPGA configure the FPGA and then wait for the user to do j This function calls the fpga config C program If an error value is returned from th
45. null reference wouldn t be returned to NPlot this case shouldn t happen but if it does this should at least avoid a program crash arr new double 1 0 5 else j arr new double this qcount_ intj o int 1 this qfront int tmpcnt this qcount while tmpcnt 0 arr j this gArray i 1 141 capacity j tmpcnt j j return arr This function returns an array of size qviewsize with the trigger point 1n the middle of the array public double ToArray int trigPoint int arrsize this qViewSize if this qcount_ lt arrsize j double arr if this qcount_ 0 j else arrsize this qcount_ set max array size to element in queue arr new double 1 0 5 arr new double arrsize int temp trigPoint arrsize 2 if temp 0 this qviewfront this qfront_ j else this qviewfront_ trigPoint arrsize 2 j intj o int 1 this qviewfront_ int tmpcnt this qViewSize while tmpcnt 0 arr j this gArray i 1 1 1 Jo capacity j tmpcnt j j return arr j This function is used for the zoom and scroll feature of pcbla It returns an array of qviewsize starting at beginPoint beginPoint is passed by the scrollbar in pcbla The dummyvariable just distinguishes between this and the trigger point version of the ToArray function public double ToArray int beginPoint bool dummyvariable
46. od Hardware portion Figure 3 of the design is the portion in which the signals from the DUT are sampled at high speed converted to logical states and transferred at high speed to the PC It accomplishes these tasks in two subsystems external circuitry and an Opal Kelly XEM 3001 This can be seen 1n the figure below Figure 4 Opal Kelly XEM 3001 Analog Signals External Circuitry Conditioned Signals Figure 4 Detailed Block Diagram of Pod Hardware portion of design The External Circuitry portion can be divided further into two portions a probe connection and comparison circuitry Probe Connection The probe connection is where the Device Under Test DUT connects to the PC based logic analyzer It carries 16 lines on a ribbon cable into the comparison circuitry with an external eround connection between the DUT and the PC based logic analyzer Future designs of the PC based logic analyzer should include a ground connection on the probe This ground connection should also be used to eliminate cross talk between lines Figure 5 shows the cross talk problem Channel 1 is the high bit after the comparator it is checking to see if the line is above TTL high threshold with the input to the comparators being a 0 to 5 volt square wave at near 2 MHz The cross talk was large enough for it to cause the line next to it to also exceed the high state threshold thus displaying what can be seen
47. oint 15 If three values are pushed the circular queue contains three elements gFront points to the first element and qBack points to the next empty element qFront bo TY a ga ODAK Figure 15 Three Values Pushed When Pop 1s called twice qFront gets incremented by two and still points to the first element 2 qFront 1 3 qBack Figure 16 Two Values Popped Pushing two more values increments qBack modulo the queue capacity qBack is now set to zero rather than six as it would have been without using the modulo operator qBack N C 2 qFront 1 3 Figure 17 Two More Pushes 16 C provides a queue that has these basic functions With this queue the programmer can only view the first element and cannot index within the queue This does not work well for the logic analyzer because a trigger point must be set to an index in the queue and a subset of data around the trigger point must be accessible To obtain these features a new circular queue library called cirQlar was developed see Appendix III This library provides the basic circular queue functions plus some functions specific to the logic analyzer Figures 18 and 19 are the flowcharts for the Push and Pop functions They operate as discussed earlier The Push function is logic analyzer specific because rather than stop filling when the queue 1s full it removes the oldest value and then stores the new value Stat Gio Fu Yes ws
48. ould be removed if actual data could be obtained private void bRunTilTrig Click object sender System EventArgs e linedat 0 qTriggerPoint 0 IStatus Text Seeking Trigger IStatus Refresh this must be refreshed or it won t be updated before the rest of the function happens because display update 1s given less priority bRunTilTrig Enabled false bReload Enabled false int seekcnt 0 while linedat 0 qTriggerPoint 0 if seekcnt 5 MessageBox Show Finding a trigger event failed seekcnt times Plotting acquired data break this getData this fillLinedat data txt true seekcnt j this getData this fillLinedat false this pcblaPlot linedat Iinedat 0 qTriggerPoint IStatus Text Status Idle bRunTilTrig Enabled true bReload Enabled true j This function recenters the trigger point in the display private void bRecenterTrigger Click object sender System EventArgs e 14 IqTriggerPoint Text Convert ToString linedat 0 qTriggerPoint this pcblaPlot linedat linedat 0 q TriggerPoint j This function 1s a scroll bar that handles the zoom level private void sbZoom Scroll object sender System Windows Forms ScrollEventArgs e linedat 0 q ViewSize e New Value this pcblaPlot linedat linedat 0 q ViewFront false 15 Appendix V VHDL code Test4 vhd This 1s a test program for the Logic Analyzer It attempts to be
49. r this bRunTilTrig Click new System EventHandler this bRunTilTrig Click bRecenterTrigger this bRecenterTrigger Location 2 new System Drawing Point 352 392 this bRecenterTrigger Name bRecenterTrigger this bRecenterTrigger Size new System Drawing Size 104 23 this bRecenterTrigger TabIndex 15 this bRecenterTrigger Text Recenter Trigger this bRecenterTrigger Click new System EventHandler this bRecenterTrigger_Click lqTriggerPoint this lqTriggerPoint Location new System Drawing Point 88 392 this lqTriggerPoint Name IqTriggerPoint this IqTriggerPoint Size new System Drawing Size 80 24 this lqTriggerPoint TabIndex 11 this lqTriggerPoint Text qTriggerPoint this IqTriggerPoint TextAlign System Drawing ContentAlignment MiddleCenter sbZoom this sbZoom LargeChange 50 this sbZoom Location 2 new System Drawing Point 176 392 this sbZoom Maximum 1000 this sbZoom Minimum 10 this sbZoom Name sbZoom this sbZoom Size new System Drawing Size 160 16 this sbZoom SmallChange 10 this sbZoom T ablndex 16 this sbZoom Value 10 17 this sbZoom Scroll new System Windows Forms ScrollEventHandler this sbZoom Scroll mainForm this AutoScaleBaseSize new System Drawing Size 5 13 this ClientSize new System Drawing Size 680 417 this Controls Add this sbZoom this Controls Add this bRecente
50. r public int qViewSize get return qviewsize set qviewsize value j static int qviewsize 100 public int qTriggerPoint set qtriggerpoint_ value get return qtriggerpoint j static int qtriggerpoint end Static Properties Instance Specific Properties public double qArray public double qTriggerPointValue get return this gArray qtriggerpoint j public int qViewFront get return qviewfront set qviewfront value j private int qviewfront 0 public int qViewBack get return qviewback j private int qviewback_ 5 public int qCount j private int qcount 0 get return qcount public int qFront private int qfront_ get return qfront_ public double qFrontValue get return qArray this qfront j public int qBack get return qback_ j private int qback this function provides a modulo capacity subtract function This is needed because subtracting can result in negative indices with throws an exception When triggering it 1s helpful to look at previous values this makes certain that the indices are in with in the range of the queue public int qBackMinus int subtractor int result int tmp tmp this qback subtractor if tmp lt 0 result 2 capacity tmp j else j return result result this qback subtractor j publi
51. rTrigger this Controls Add this bRunTil Trig this Controls Add this 1Status this Controls Add this lqTriggerPoint this Controls Add this sbHistory this Controls Add this bReload this Controls Add this plotSurface this Name mainForm this Text PC Based Logic Analyzer this ResumeLayout false j endregion lt summary gt The main entry point for the application This function was added by VS NET lt summary gt STA Thread static void Main j Application Run new mainForm This function loads sample data into linedat when the button is pushed A function similar to this could be used to load old saved data private void bReload_Click object sender System EventArgs e this fillLinedat data 512 1 O txt true lqTriggerPoint Text Convert ToString linedat 0 qTriggerPoint this pcblaPlot linedat j This handles scrolling through the data private void sbHistory Scroll object sender System Windows Forms ScrollEventArgs e 13 linedat 0 q ViewFront e NewValue linedat 0 qCount linedat 0 q ViewsSize 100 this pcblaPlot linedat linedat 0 q ViewFront false j This function trys 5 times to find a trigger in the data acquired from the XEM3001 If at can t find it by then it reports that and displays the data it does have The limit of five was set because we weren t getting data in from XEM3001 This limit could sh
52. rigger point The status label in the bottom right corner tells the user what the logic analyzer 1s current doing By default it 1s Status Idle E n data tut 129 ag i gt er Run Until Trigger Status Idle Figure 23 Graphical User Interface 21 The signals are plotted using the NPlot library This 1s an open source plotting library developed by Matt Howlett The source files and documentation can be found at http netcontrols org nplot The StepPlot portion of NPlot was used because this was the easiest way to plot the four possible logical states Each of the logical states 1s represented by a different step height step These steps are 0 0 33 0 66 and 1 as discussed in Data Collection section of this report The probe line number is added to each the display signals so they do not all plot in the O to 1 range Conclusions The team was successfully in the following areas Successful determination of 3 states VHDL capable of transferring data from the pod to the PC successful transfer of data from the pod to the PC and successfully display and GUI Though all of these items were accomplished continuous data transfer was not achieved and High Z was not detected To be able to accomplish these goals another element must be added in the comparison circuitry that will aid in determining if a High Z state is in effect also the DLL released by Opal Kelly should speed up transfers immensely on the PC side making con
53. s style of transfer provided buffered data transmission between the PC and the XEM 3001 The buffer will allow more processing time for the PC Once the data is read it must be parsed and written to a text file so the C program can interpret and display the data T his process is shown in Figure 12 17 Open data txt Figure 12 Data Collection Flowchart The ReadFromPipeOut function reads a buffer of 1024 characters from the XEM 3001 into a character array Each probe line 1s represented by two bits thus it takes four characters to store one sample of all sixteen lines This means 1024 characters store a total of 256 samples Each two bit value must be parsed and written to data txt so it is available to read by the C program The program parses data using a shifting two bit mask and a switch statement This is shown in Figure 13 Space left black for formatting Figure 13 on next page 13 Loop 1024 times Get byte from array Figure 13 Parsing Flowchart The switch statement has four cases corresponding to states logic O indeterminate high Z and logic 1 For a logic 0 the two data bits are 00 and a O is written to data txt For indeterminate the data is 01 and a 0 33 1s written to data txt For high Z the data is 10 and a 0 66 is written to data txt For a logic 1 the data is 11 and a 1 is written to data txt It 1s possible reduce the number of cases
54. seful for allowing the user to see the independent activity of lines during a DUT s clock cycle Moreover this allows for much more detailed debugging The comparison circuit determines one of four states for each line The comparator can classify signals as high low intermediate signal between high and low thresholds or no signal a High Z condition Once the state has been determined the data 1s sent in the form of 2 bits into a buffer Once several samples for all 13 sixteen lines have been collected in the buffer the buffer sends the data to the PC through the USB interface More detail on the separate sections can be seen in figures below Designated Clock Lj me Synchronous Internal asynchronous Clock switch To Buffer Sampled lines 2 bits High Comparison circuit Combinational e Logic Low Comparison circuit W High Z Comparison circuit Figure 3 Comparison Circuit Block Diagram 2 Bits from Comparison Line to USB circuit Controller Write Read Controller Controller Figure 4 Buffer Block Diagram Data line to PC From Buffer USB Transceiver Chip Figure 5 USB Interface Block Diagram PC Functionality m USB Data Memory Conditioned Signals Reason Data Store Data gt Trigger Display Data gt Display vim Output A A A Trigger Control SE Disp
55. t function This function returns an array that is only a portion of the whole cQueue size The center point of the array 1s the trigger point that was passed as a parameter The size of the view 18 window 1s set by the user but the trigger point 1s always the center element Figure 21 shows the flow for this function Stat Set Array size to view size qCount lt Array Yes size Y Set Array size to qCount Yes Check Adjust bound of view window Y I Create new array of 0 5 Copy values from queue array to new array Return array lt Y C End Figure 21 ToArray int trigPoint Flowchart The graphical user interface will provide the ability to scroll through the buffer The ToArray int beginPoint bool dummyvariable function accommodates this feature The dummy variable exists just to differentiate between the trigger point and begin point versions of the function The ToArray int beginPoint bool dummyvariable function returns an array that has the value of 19 beginPoint as the first element and is the size of view window size The flow for this is in Figure 22 oet Array size to view size oet copy starting point to beginPoint Copy values from queue array to new array Return array Figure 22 ToArray int beginPoint bool dummyvariable Flowchart
56. this plotSurface Title this plotSurface TitleFont new System Drawing Font Arial 14F System Drawing FontStyle Regular System Drawing GraphicsUnit Pixel this plotSurface X Axis null this plotSurface XAx1s2 null this plotSurface Y Axis null this plotSurface YAxis2 null bReload this bReload Location 2 new System Drawing Point 8 392 this bReload Name bReload this bReload Tablndex 3 this bReload Text data txt this bReload Click new System EventHandler this bReload Click sbHistory this sbHistory Location 2 new System Drawing Point 8 336 this sbHistory Maximum 10008 this sbHistory Name sbHistory this sbHistory Size new System Drawing Size 664 16 this sbHistory TabIndex 10 this sbHistory Scroll new System Windows Forms ScrollEventHandler this sbHistory Scroll IStatus this IStatus Location new System Drawing Point 576 392 this IStatus Name IStatus this IStatus Size new System Drawing Size 88 23 11 this 1Status TabIndex 13 this 1Status Text Status Idle this 1Status TextAlign System Drawing Content Alignment MiddleRight bRunTilTrig this bRunTilTrig Location 2 new System Drawing Point 464 392 this bRunTilTrig Name bRunTilTrig this bRunTilTrig Size 2 new System Drawing Size 104 23 this bRunTilTrig TabIndex 14 this bRunTilTrig Text 2 Run Until Trigge
57. tinuous data transfer a reality 22 Appendix I fpga config Code include iostream include fstream this is hard coded because VS C was having problems finding the header file when rebuilding the project in a new directory make sure the path is correct include lt C Documents and Settings Jason My Documents project fpga config fpga config okCUsbXEM h gt include lt string gt using namespace std int main Create an instance of the okCUSbXEM okCUsbXEM xem new okCUsbXEM Open the first available device If fail return 4 as error code int openfailcnt 0 bool check false while check false check xem gt Open 0 opentailcnt if openfailcnt 4 return openfailcnt j j Download a configuration file to the FPGA If fail return 24 as error code int configfailcnt 20 check false while check false check xem gt ConfigureFPGA test4 bit configfailcnt if configfailcnt 24 return configfailcnt j return Q Appendix II pcbladata Code include iostream include lt fstream gt this is hard coded because VS C was having problems finding the header file when rebuilding the project in a new directory make sure the path is correct include lt C Documents and Settings Jason My Documents project pcbladata pcbladata okCUsbXEM h gt include lt string gt using namespace std int main string
58. tion was added by VS NET lt summary gt protected override void Dispose bool disposing if disposing if components null j components Dispose j base Dispose disposing j region Windows Form Designer generated code summary Required method for Designer support do not modify the contents of this method with the code editor lt summary gt private void InitializeComponent l this mainMenul new System Windows Forms MainMenu this menultem1 new System Windows Forms Menultem this menultem4 new System Windows Forms Menultem this menultem5 new System Windows Forms Menultem this menultem6 new System Windows Forms Menultem this menultem7 new System Windows Forms Menultem this menultem2 new System Windows Forms Menultem this menultem3 new System Windows Forms Menultem this plotSurface new NPlot Windows PlotSurface2D this bReload new System Windows Forms Button this sbHistory new System Windows Forms HScrollBarQ this IStatus new System Windows Forms Label this bRunTilTrig new System Windows Forms Button this bRecenterTrigger new System Windows Forms Button this lqTriggerPoint new System Windows Forms Label this sbZoom new System Windows Forms HScrollBar this SuspendLayout mainMenul this mainMenul Menultems AddRange new System Windows Forms Menultem this menulteml th
59. ts in two signals being sent to the Opal Kelly XEM 3001 FPGA These signals can be seen in Figure 7 Tek Run n nn Trig d TE 920mV 420us 880us Ch1 Freq 294 6 Hz chil 2 00V BYE 1 00 V BI LIII Thr F 3 40 7 Ref 1 1 00 V 1 00ms m 0 000005 10 52 44 Figure 7 Triangle Wave demonstrating threshold levels 5 May 2005 In Figure 7 channel is a triangle wave and is the source on a single sampled line The reference line R1 is the high bit line it is a 1 when below the 2 0V threshold and a 0 when above Channel 2 is the low bit line it is a 1 when below the 0 8V threshold and a O when above The comparators used are AD8564 manufactured by Analog Devices They are ideal for the design because they have an inherent high impendence run off of a single 5V power supply and are capable of operating at very high frequencies The rise and fall time in the output from the AD8564 is 3 8ns rise and 1 5ns fall This allows for clear signal sampling well above the overall PC based logic analyzer s maximum sampling rate 12 MHz With two output lines per each sampled data line 32 lines or bits are sent to the Opal Kelly XEM 3001 FPGA FPGA This brings us to the second portion of the Pod Hardware design the Opal Kelly XEM 3001 FPGA The Opal Kelly XEM 3001 FPGA is responsible for sampling and organizing the 32 bits of data it 1s receiving from the comparison circuitry and then trans
60. ue ly1 WorldMax 31 66 ly1 WorldMin 1 LinearAxis 1x1 LinearAxis plotSurface X Axis 1 Ix1 HideTickText true j end Axis Configure plotSurface Refresh end Plotting This overload centers the display around the trigger point that is passed as a parameter public void pcblaPlot cQueue linedat int trigPoint VerticalGridType Plotting plotSurface Clear Grid Code Grid mygrid new Grid mygrid MajorGridPen new Pen Color Chartreuse I took the following line out because NPlot creates a dotted gray line by default This is what I wanted for the minor grid lines If desired the line could be uncommented mygrid MinorGridPen new Pen Color Blue E Note It seems from trial and error that HorizontalGridType actually refers to the vertical grid on the actual plot Likewise refers to the horizontal grid on the plot Thus HorizontalGridType is set to None W mygrid HorizontalGridType Grid GridType None mygrid VerticalGridType Grid GridType Fine plotSurface Add mygrid end Grid Code for int 1 0 1 lt numlines i lineplots i new StepPlot lineplots 1 OrdinateData linedat i ToArray trigPoint lineplots 1 Pen new Pen linecolor i 1 plotSurface Add lineplots 1 j Axis Configure For now the x axis will be configured by default by NPlot left yaxis configuration

PCBLA final report rev. 5 by jason

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