HP E1399A Register-Based Breadboard Module User`s Manual
Contents
1. l rr ys Y BASE 2 I E 8 yo E13 Stotus Control L BASE 4 pue E ap l BASE 6 I Brach Be Eer T RSR Ze me Base 2 I N T 1 2B t BASE 14 i l un 1 LA uin I T T LA S DEVICE TYPE i 1 Los REGISTER oc u15 Imc U10 L UN LEN 18462 SP2 cue P Dus MS 1 16 a Dis o 10 10 U7 yo pls oo n v I 1 3120 2018 Ma Ora 1 1M20 5 2115 Aug ya HZ 1 I 2 Aan 30117 8 n 1 NS i le 14 A valle 2 I 3 540 ao LS L 3c DEA poo 4 ool 5 ya US 3 I 4 San PI 5V DC mo a 5 o ol2 Blas ys 14 4 I S Zen BAD L Se D Pio ie s Sh HNS ye 3 5 8179 7q Hs E M 9 o ott l H gt 10 1 ala7 y7 42 6 i 280 802 5 628 WR UNN ESAE m yg t 7 m SHEET 2 L cl 1 MIS 5 E DVB 15 0 I RPI 26 4K eg a a a clc os os is tl Ll PIACH NOTE x O PACK 16 NOR LATCH with Dis for EDGE LATCH signal SHEET 2 13 EE SR SYSFINH O SHEEL gel 8 PSN t 510 uso vpt Di sera 9 SYSFAIL O SHEEL2 Dr wer WRITE Na A SYSRESET SYSRESET 21A Y ACKADOR xk ACKADOR 5 e ir DTACKINH A A2. DBO DB15 Internal Data Bus PIACKx 0 7 Logical Device OB 0 ase A6 A15 Address 0 255 O Bose 6 AMO AMS O Base 8 S I O Base A JACK 2 ADDRESS O Base C LWORD DECODING O Base E O LAT Enable Lo LA2 O LA3 i I O LAS A1 A5 HO LAS BASE 2 REGISTER 1 WRIT DECODING Base 4 2 RITE Base 4 BASE 4 Latch Address amp BC 0 3 Inx A1 A5 Match Model 4 i R017 Device 0 7 Type IRQ Mem Avail Register 2 Acknowledge m Level A E ____ BG 0 3 Out Select BASE 4 D E 3 Jumpers E SR70 amp DBEN ACKADDR CADDR SEC ge SE Status DSO S Bis se20 Registe DS1x SR1O e SRO O A DTACK Logical Device SE SYSCLK A Interrupt Address Enable Control IACKIN H interface L C ai EH et IACKOUT 2 g IRQ Latch o amp 8 S Request A IRON O E S RA Ge ace aH 2 1 7 Select PUR SM Contro be jumpers V CR26 4 Registe z O DTKINH CR1O DTACK L CROO H Clear WRITES BEER 1 DTACK l EN Lo Write SYSRESET Do O oi HRESETx CRESET DO D15 GR DBO DB15 Internal Dota Bus DRIVERS t O SERCLK SERDAT 1399 Fig1 1 I O ACFAIL NOTE L O ALL POWER SUPPLIES
3. WRITES 61 U10 BASE 2 19 402 In 16 2f y 18 DBO 2 5 o 115 1 MN yo 07 D81 Alen 4 43 y3 116 DB2 4 5 p5 H 5 ag ya 115 DBS 5 5 96 12 HI ys 14 D84 6 5 9 1 L Z A6 Ye 13 DBS 7 o 10 1 8 A7 y 12 DB6 8 5 gt p 12 pl 9 AB vg 1 DB7 e V N TO DATA BUS DRIVERS E1399 fig2 9 Figure 2 9 Device Type Register The bits can be reconfigured using the DIP switch The range of device types for an A24 or A32 device is 0 4095 For an A16 device all 16 bits are available for specifying the device type for a range of 0 65535 The user will need to add the required buffer and resistor network to implement the full A16 device type range The default factory setting is FFxxh Note Per the V XIbus Specification OBSERVATION C 2 6 device types 0 255 are reserved for register based Slot 0 devices Refer to the V XIbus Specification Section C 2 1 1 2 for detailed information concerning Device Type Register implementation restrictions Table 2 6 shows the Device Type Register bit definitions 28 Configuring the HP E1399A Chapter 2 Control Reg ister The Control Register is an 8 bit register which causes specific actions to be executed by the breadboard module when written to from the backplane data bus The primary component of the Control Register is U13 as shown in Figure 2 10 Table 2 9 shows the part number for U
4. CARD ADDRESS CARD BOUNDRY DETECT U20A i DEC gis 1 82 DAE B wack 2120 ao DE 1 i i gc a2 Z OWE e RES 8 2 po 3 Zen BI 3_OVME 2 83 35 ACFAlL 3 67 DWE 10 z Ae u17 ja E DWE 3 PEG EN 6 8 pp as E D ME A as 37 cs 59 DME 12 A 15 0 8 8 ac E D ME S pe 38 ce ZO OWE 13 1 1 aJ LL DWE S B7 39 co EL 0We 14 ag E D MEC ali oa Z2 DEI a E GROUND ag 4 cgl Z3 GROUND a10 10 SYSCLK eio cio Z4 SEN tie GROUND g 43 5 BERR Boek wall St MAE cia I6 SYSRESETe EZ ELENCO Salt cas LT WORD Aalt R We B14 4S c14 28 AM RP25 as E GROUND pjo 47 cas US 4JK are E DACKE 816 48 AMO ME 17 1 GROUND gi 49 AM ME AUERS pial SO AM 2 618122 aro IO GROUND yg BLAWG EU ago 20 ACI p20 2 GROUND l t joi 2L W 682 1 3 SERCLK ES A2222 ACKOUTe elt SEROMAM 86 azs 25 Ma 673 95 GROUND l t A 15 ma P1 70235140 5 0 NEXU pza S Oe cza BE 14 NE aos 25
5. DTACKINH 4 HRESET x 13 SHEET 2 5 OIRO STATUS U218 Y CONTROL CRESET 42 U21D y CRESET 5V REGISTER REGISTER PAL WE IFC die R2 a Ue 2 Da oi jl D Manga 3 59 STATUS O O t Y 1D 10 e KEE STATUS 1 O SI v2 HZ vM 4120 205 CONTROL 3 ry a PASSED O AS pe E 239 E O CONTROL 5 unk 4 SG IACKIN EXTENDED O SM ya 115 3 8140 sol O CONTROL 7 m d STATUS 4 O i AS y n A i 7 50 50 Z O CONTROL 5 CHORE LE STATUS 5 O E A6 Ye 6D 60 O CONTROL 4 DIAGN DR STATUS 6 O SAT v p2 SA 1279 elt O CONTROL 2 ora DER STATUS 7 O EMG ya LU 1 7 N0 1880 sop L 9R Bi 1155 E 10 pso m aoe GO LH MNEMONIC DEFINTIONS Pack Foe eu VME BACKPLANE OUTPUT Ing LEVEL SELECT i MISD Address Bus ROH Ro 1 2 I 1 wegl Address Modifier Bus ACKOUT S WORT I L as l JMIS ASS Address Strobe Diack i p USA rol Km EL 25 1801 D TERI Enable Lines A 2 1 CADDR open P16 aoc l 1 FB ROL CONTROLO 1 I 2 Qi PL RQ3 l CONTROLL J 1 2 M23 3 I CRESER Control Reset I BE OL PLES 1804 l DBEN Data Bus Enable I 1 2 MM ag 1 DSO DS I po oL P1387 IROS l DTACK Dota Transfer Acknowledge I 2 M235 4 l DTACKINH i Tas wie IRQ6 l DV8 15 0 Buffered VME Data Bus I kV 2 io BUS 207 Ge VME Date Bus T ea 1 HRESET Hardware Reset I DTACK We Interrupt Acknowledge l PL22S CKOUT Wei Interrupt Acknowledge In IACKOUT Interrupt Acknowledge Out r 1 IRQ Interrupt Request IRQX IRQ1s IRQ7 l l l Dr P o EN Ed 5V 5V I LATCH Latch Um 1 1
6. Driver Direction 1 O SYSFAIL Q User Access Pionts Figure 1 1 Digital Backplane Interface Block Diagram Chapter 1 HP E1399A Introduction 11 e Status Register A read of this 8 bit register provides information about the status of the breadboard module Implemented signals are Extended and Passed There are also provisions for implementing device dependent status bits ID Register A read of this 16 bit register identifies the Manufacturer ID number the Device Class and the addressing mode of the Breadboard This register is implemented as a Hewlett Packard A16 register bassed device Device Type Register A read of this 8 bit register identifies the unique card model as defined by the device manufacturer The card model number is switch selectable Control Register A write to this 8 bit register causes specific actions to be executed by the device Reset and System Fail Inhibit are implemented Other device dependent control bits may be implemented by the user Read Write Operations Using the backplane interface circuitry provided it is possible to read the contents of the Status ID or Device Type Registers onto the data bus DO D15 or to write information into the Control Register from the data bus DTACK The interface contains the circuitry required for generating a delayed DTACK data transfer acknowledge signal nterrupt Interface The breadboard module has D16 interrupt
7. AS DSO DS1 SYSCLK SYSFAIL SYSRESET Address strobe used in data transfer cycles Data strobes used in the data transfer cycles Provides 16 MHz clock signals to Interface IC U6 for clocking the state machines SYSFAIL input If the SYSFAIL INHBT line output of the Control Register CR1 is also low not inhibited then SYSFAIL is asserted System reset signal normally used to initialize the backplane interface circuitry and your own custom circuits to a known state Provides a hardware reset capability As implemented HRESET it clears the Status Register and the Control Register It also asserts the software reset line access point CRESET on the module CRESET can also be asserted via software by writing a high signal D GE Control Register access point CRO providing an input to 21D 34 Configuring the HP E1399A Chapter 2 User Access Points The breadboard module contains traces stubs for accessing many of the signal lines on backplane connector P1 Table 2 13 shows the signal lines that are brought onto the module but not implemented They are available as signal access points for your custom circuits Table 2 14 shows all of the implemented signal lines available as access points either as inputs from the backplane to your own custom circuitry or as outputs to the backplane from your custom circuits Table 2 13 User Access Points Stubs Signal Lines Description
8. 0 is indicated by zero V ground at the specified signal point A mnemonic suffixed with an asterisk such as WRITE indicates inverse logic 0 or low true 1 or high false Address Lines and Figure 2 6 shows the address line and register decoding circuitry while Regi ster Decoding Table 2 1 shows the applicable parts list The HP E1399A Breadboard Module is designed to be used as an A16 D16 device As such only backplane address lines A1 A15 and data lines DO D15 have been implemented on the module To address the module the information present on backplane lines A6 A13 must be identical to the logical address as set by address switch SP1 0 7 These eight bits allow up to 255 different V XIbus logical devices to be selected on a V XIbus system 22 Configuring the HP E1399A Chapter 2 Table 2 1 Address Lines and Register Decoding Parts Reference HP Part Number Description Designator
9. LATCH DBEN DATA BUS ENABLE U5B U15 LATCHES A1 A3 6 DTACKx 3 4 R2 30 1K po i d LAR OR sy WRITE uta U10 E1399 FIG2 11 Figure 2 12 Interrupt Circuitry only one at a time allowed for both the IRQ request output line IRQ1 IRQ7 and the IRQ acknowledge input line ACKADDR IRQ request and acknowledge levels must always be the same IRQ1 is shown selected in Figure 2 12 To generate an interrupt request to the interrupt handler and start the IRQ state machine in U6 the user s custom circuits must provide a high signal at the IRQ access point input to U6 ACKADDR 32 Configuring the HP E1399A Chapter 2 The IRQ state machine monitors the following interrupt related lines to determine its actions IACK valid DSO IACKIN AS ACKADDR If the module is asserting IRQ and the interrupt related lines are in the proper state the IRQ state machine asserts IRQX high true on U6 IRQX high true inverted by USA pulls the jumper selected IRQ1 line low true on the backplane The state machine then waits for the interrupt handler to recognize the interrupt request When the interrupt handler responds it places the code for the interrupt request priority level that it is acknowledging onto lines A1 A3 It then sets IACK low true which sets IACKIN low true IACK low true starts the interrupt acknowledge cycle disabling normal address decoding on the breadboard module
10. WE Gla Be E1399A FIGe 1 Figure 2 1 HP E1399A Breadboard Module amp Connector Pinout Chapter 2 Configuring the HP E1399A 17 160mm 6 25 in PC Board Length 222mm 8 75in 233 5mm 9 19 in PC Board width Le User available component area PE Grid Hole Spacing 0000 2 54mm 0 1in 0000 0000 QUO GO 05 Grid Hole Inside Diameter 1 17mm 0 046 in 96mm 3 78in Maximum Component Hieght 11 7mm 0 5in n Maximum Lead Length Without Insulatin O 1 3mm 0 05in 5 Le UU Side View of Mounted Components E1399A FIGe 2 Figure 2 2 HP E1399A Dimensions 18 Configuring the HP E1399A Chapter 2 Cooling The V XIbus Specification requires module manufacturers to establish a Requ irements cooling specification for each of their modules The specification is to consist of 1 the airflow required in liters second for adequate cooling and 2 the pressure drop
11. surface on the mainframe thus bringing you the module and the mainframe to the same static potential Hardware Description Backplane Connections Module Dimensions Figure 2 1 shows the module with interface circuit components installed As shown the module consists of a circuit board with one backplane connector P1 and a front panel connector J1 Approximately one third of the circuit board contains traces for installing the backplane interface circuitry See Backplane Interface Circuitry for interface circuitry installation The breadboard module interfaces your custom circuits to a standard B size VXIbus backplane connector P1 This enables you to access the backplane control signals data lines address lines and power supplies Figure 2 1 shows backplane connector P1 which connects to the V XIbus backplane Figure 2 2 shows the dimensions of the module and the component height and lead length restrictions The maximum component height allowed above the circuit board is 12 7mm 0 5in The maximum component lead length allowed below the circuit board is 1 3mm 0 05in Do not mount components closer than 4mm 0 16in to the extreme upper or lower edges of the circuit board This space is used to guide the module into the mainframe module slot An area of 220 cm 34 in is available on the module to install your own circuitry 16 Configuring the HP E1399A Chapter 2 Backplane Interface L Circuitry g iss Ez
12. 1 1 I a o l LCADDRe l c38_ c39 c40 k C42 l I LWORD Longword Onur i L Our our LOF PASSED Passed Self Test Flag A b A SE Peripheral Interrupt Acknowledge x 10 STATUS 7 0 SYSCLK System Clock pon T EH l l SYSFAlL System Fail tot H i l f SYSFAIL INHIBIT System Fail Inhibit ken jeca ecs SYSRESET Systern Reset elt di i 12 Wire I 2 l l I l l Figure B 1 HP E1399A Breadboard Schematic 2 of 2 Appendix B HP E1399A Parts List Schematic 55 56 HP E1399A Parts List Schematic Appendix B A Access Points 35 Address Lines 10 22 Backplane Buffering 12 BAckplane Connections 16 Backplane Interface Circuitry 22 Backplane Interface Diagram 11 Backplane Interface Features 10 Block Diagram 11 Breadboard Description 10 Breadboard Features 10 Buffering 12 C Certification 3 Comment sheet reader 7 Components Mounting 13 Configuring Interrupts 44 Conformity declaration 5 Connectors 13 Control Register 12 29 41 Control Signals 34 Cooling Requirements 19 D Data Bus Drivers 25 Data Lines 10 Declaration of conformity 5 Description 10 16 Detecting Errors 47 Device Type Register 12 25 27 Dimensions 16 Documentation history 4 DTACK 12 30 Index HP E1399A Breadboard Module User s Manual E Errors 47 F Features 10 G Generating Interrupts 44 H Hardware 13 ID Register 12 Interrupt Interface 12 Int
13. 1 in 1 17 mm 0 046 in 12 7 mm 0 5 in above board 1 3 mm 0 05 in below board Register Based Slave Interrupter A16 D16 1 7 selectable Determined by mainframe cooling Cannot exceed the number of watts per module per slot total cooling backplane interface circuitry consumes 0 5 watts Voltage 5 Vdc Peak Module Current IPM A 0 10 Dynamic Module Current IDM A 0 01 0 5 backplane interface circuitry only User circuitry not included Appendix A HP E1399A Breadboard Specifications 49 Me Cooling per Slot Environment Humidity Operating Temperature Storage Temperature Safety EMI RFI Safety To maintain less then 10C rise on the breadboard about 0 08 liter sec of airflow is required for each watt dissipated At a power dissipation of 20W the pressure drop across a typically populated breadboard will be 0 05 mm H20 65 0 40 C 0 55 C 40 C to 70 C ets FTZ 1046 1984 CSA 556B IEC 348 UL 1244 50 HP E1399A Breadboard Specifications Appendix A Appendix B HP E1399A Parts List Schematic The parts list below shows parts which are supplied by Hewlett Packard when you order the HP E1399A See Chapter 2 Configuring the E1399A for components required by each interface functional group See Figure B 1 for the schematic of the digital backplane interface circuitry To order a part listed in the tables quote the Hewlett Packard part number the desired
14. 2 15 are available on short stubs from the connectors The 5 VDC and 12 VDC power supplies are fused Users should fuse and filter any other power supplies they access to protect their mainframe All ground pins are connected together and are accessible in several places No ground loops are present in the module The front panel of the module is not grounded Table 2 15 Power Supply Voltages and Pin Numbers Voltage Connector and Pin Numbers 5 V dc 5V stdby 12V dc 12V dc P1 A32 B32 C32 P1 B31 P1 C31 P1 A31 36 Configuring the HP E1399A Chapter 2 Chapter 3 Using the HP E1399A This chapter shows how to use the backplane interface circuitry on the HP E1399A Breadboard Module This chapter includes e Reading Data From Registers e Writing Data to Registers Using Interrupts Resetting the Module e Detecting Errors Using Other Power Supplies Reading Data From Registers The breadboard module contains circuitry for two readable registers as determined by the VXIbus Specification e Status Register e Device Type Register Status Register Bit Table 3 1 shows the status register bit definitions It will be used as an Definitions example of how to read from a register on the breadboard module As shown in Table 3 1 only four of the eight bits in the register are predefined by the VXIbus Specification The other four bits are device dependent That is they can repr
15. 6 Y4 ETE UM13 JM14 JMI6 20 5V G1 pt L DBEN FROM US SEH 462A i p CADDR TO U6 5 BS wa E1399 Fig2 6 Figure 2 6 Address Lines and Register Decoding Chapter 2 Configuring the HP E1399A 23 If a logical address match occurs and IACK is high false equality detector U18 produces a low at its output which enables U17 Next equality detector U17 compares the information on backplane lines A14 A15 AMO AMI and AM3 AMS to a hardwired code of 11101X012 Since AM2 is not examined this hard wired code will be a match if all three of the following conditions are true e a hexadecimal code of either 2916 or 2D16 is present on lines AMO AMS Al4and A15 are both high 1 e LWORD is high false Either of the two address modifier hexadecimal codes indicated above will establish A16 addressing per the V XIbus Specification Section C 2 1 1 4 In the VXIbus addressing scheme for an A16 device A14 and A15 are always set to 1 to select the upper 16K of the 64K A16 address space per the VXIbus Specification Sections A 2 3 3 and C 2 1 1 1 LWORD is high false when decoding short word transfers If a second match occurs at U17 its output goes low This triggers a data transfer cycle using the DTACK state machine in the Interface IC U6 by the low at U6 input CADDR See DTACK Interrupt and Control for more information on the DTACK state machine As part of the data transfer cycle
16. Breadboard Module User s Manual Contents Certification Hewlett Packard Company certifies that this product met its published specifications at the time of shipment from the factory Hewlett Packard further certifies that its calibration measurements are traceable to the United States National Institute of Standards and Tech nology formerly National Bureau of Standards to the extent allowed by that organization s calibration facility and to the calibration facilities of other International Standards Organization members Warranty This Hewlett Packard product is warranted against defects in materials and workmanship for a period of three years from date of ship ment Duration and conditions of warranty for this product may be superseded when the product is integrated into becomes a part of other HP products During the warranty period Hewlett Packard Company will at its option either repair or replace products which prove to be defective For warranty service or repair this product must be returned to a service facility designated by Hewlett Packard HP Buyer shall pre pay shipping charges to HP and HP shall pay shipping charges to return the product to Buyer However Buyer shall pay all shipping charges duties and taxes for products returned to HP from another country HP warrants that its software and firmware designated by HP for use with a product will execute its programming instructions when properly installed on that p
17. DS1 low true 44 Using the HP E1399A Chapter 3 M Sit WAN aaa E A m IN IRQX idi o i Lf e AT a Aag EE or TO LT ES Im DS0 ius NR Es Ai DBEN cB DTAC 240 7 62 5 e 962 5 62 5 62 5 62 5 10 15 1 DTACKINH high will hold E1399 FIG3 5 DTACK cycle here until DTACHINH goes low sync with SYSCLOCK Figure 3 5 Interrupt Timing Chapter 3 Using the HP E1399A 45 D8 D16 INTERRUPT ACKNOWLEDGE CYCLE PARTICIPATING R W ni SEI Np X rp V fri f X fni AS IRQ IRQX IACKIN IACKOUT ACKADDR To meet VME timing spec an external SSES IACKOUT disable is also used Figure 3 6 Interrupt Timing Wrong IRQ Level or No Interrupts Pending 46 Using the HP E1399A Chapter 3 Resetting the Module A reset signal is provided to initialize the backplane interface circuit and your own custom designed circuitry to a known state Both hardware and software resets are implemented for your convenience Hardware Reset The backplane SYSRESET line drives both the hardware reset HRESET and the software reset CRESET user access points low 0 on the breadboard module HRESET also goes to the clea
18. HP E1399A Parts List Schematic provides HP part numbers and descriptions of all parts required by the HP E1399A It also includes a complete schematic of the E1399A digital backplane interface Specification Compliance Warranty Warning The HP E1399A Breadboard Module is designed in full compliance with the VMEbus Specification Revision C 1 and the V XIbus specification Revision 1 3 The HP E1399A warranty statement located at the front of this manual is different from the standard Hewlett Packard warranty for the HP E1300A E1301 A mainframe and other plug in modules Hewlett Packard is only responsible for defEcts in materials and workmanship of the blank circuit board and supplied hardware Hewlett Packard is not responsible for the performance of your custom designed circuitry Hewlett Packard is not responsible for damage to or improper operation of your VXI mainframe or other plug in modules caused by the HP E1399A Breadboard Module Chapter 1 HP E1399A Introduction 9 HP E1399A Description The HP E1399A Breadboard Module is a B size register based device that provides a convenient interface to a VXI mainframe backplane It allows you to construct your own custom hardware for use with the mainframe General Module The module is supplied with all interface components loaded and soldered Features Your VXI mainframe can communicate with this module configured as an A16 D16 device The breadboard module interface circu
19. P1 contains 16 bi directional data lines labeled DO through D15 The breadboard module connects to these data lines using the circuitry shown in Figure 2 7 Table 2 3 shows the Data Bus Drivers parts list Data buffering is provided for the data lines by two tri state octal bus transceivers U16 buffers DO through D7 and U35 buffers D8 through D15 Note that the data lines are labeled DBO through DB 15 on the module side of the buffers U16 and U35 are enabled during a data bus transfer cycle when DBEN Data Bus Enable goes low true This occurs whenever the breadboard is correctly addressed by a match of the module s logical address as set by SP1 0 7 The direction of data transfer is determined by WRITE When WRITE is low a write operation information present on backplane lines DO D15 is transferred to the breadboard Control Register via DBO DB 15 When WRITE is high a read operation information present on DBO DB15 is transferred to backplane lines DO D15 WRITE is the signal available on the VXI bus backplane This signal is converted immediately to WRITE via U20F schmidt trigger inverter The signal accessible to the user on the breadboard is WRITE not WRITE During a normal read operation the information present on DBO DB15 is selected by the Address Decode circuitry from one of two sources e Status Register U14 Device Type Register U10 You can also write to or read from up to five more device dependen
20. U6 sets DBEN low true latching the remaining backplane address lines A1 A5 at the U15 outputs to the two 3 to 8 line decoders U7 and U8 Latch U15 ensures that the data is held valid until the data strobes go high false even though the address lines may no longer be valid U8 is enabled if G1 is high and both G2A and G2B are low Therefore A4 and A5 must both be low to select a register for connection to the data bus DO D15 G1 will be high via U9C if there was a match at U17 If US is enabled backplane lines A1 A3 are decoded to specify which register Status ID Device Type or Control is to be connected to the data bus Other user supplied registers can be selected also If additional decoding is necessary A4 and A5 are accessible on the module See Table 2 2 and Figure 2 6 for information on implementing your own register selections 24 Configuring the HP E1399A Chapter 2 Data Bus Drivers Note Table 2 2 1 Register Selection A3 A2 A1 Enable Line Register 000 Base 0 ID 001 Base 2 Device Type 010 Base 4 Status Control 0 1 1 Base 6 User Assignable 100 Base 8 User Assignable 101 Base A User Assignable 110 Base C User Assignable 111 Base E User Assignable The HP E1399A Breadboard Module is designed to be used as an A16 and a D16 device only As such only backplane address lines A1 A15 and data lines DO D15 have been implemented on the module VXIbus backplane connector
21. When IACKIN goes low true the IRQ state machine checks to see if its own IRQ level has been acknowledged input line ACKADDR at U1 will be set low by a correct match of U7 s decoded output and the jumper selection for IRQ ACKNOWLEDGE If its own level is not being acknowledged or if the module is not asserting IRQ the state machine passes the daisy chained IACKIN signal through IACKOUT on U6 The IACKOUT signal is gated with an inverted AS to meet release time requirements for IACKOUT as outlined in the VMEbus Specification If the acknowledge level matches the request level the IRQ state machine sets PIACK low true releases IRQX and IRQ1 and starts the DTACK state machine for a read cycle The interrupt handler initiates the read cycle to get the logical device address from the interrupter when it sees IRQ1 go low true PIACK low true enables U11 to place the modules logical address from SP1 onto the lower eight bits of the internal data bus DBO DB7 The logical address is then transferred to backplane lines DO D7 during the read data transfer cycle In this way the interrupt handler knows which device is asserting IRQ if more than one device has the same interrupt priority assigned to it Chapter 2 Configuring the HP E1399A 33 Control Table 2 12 shows the control signals which are implemented see the Backplane Interface Schematic in Appendix B Table 2 12 Control Signals Signal Definition
22. With both inputs to U21C set low the output is a positive going pulse that clocks the control data from DBO DB7 through U13 to access points CRO CR15 3 Set LACK high false to enable address equality detector U18 4 Set data strobes DSO and DS1 low true to indicate a 16 bit data transfer Figure 3 4 shows timing required for the Interface IC U6 control and signal lines 42 Using the HP E1399A Chapter 3 Read D16 only min times Lu in ee ed a et a MIENNE un Wm I Data valid on VME bus SS DBENx DTACK 0 125 62 5 62 5 62 5 62 5 NOTE Data strobe means a a DSO x DST when going high ond DTACKINH high will hold LATCH and DTACK occur DSO DST when g le here until nominally at the same time rdware di js E1399 Fig3 4 DTACHINH goes low sync Either edge may go high first with SYSCLOCK Figure 3 4 Timing for Writing to the Control Register Chapter 3 Using the HP E1399A 43 Using Interrupts The breadboard module can be configured to generate an interrupt to the interrupt handler when service is required If you are not going to implement the interrupt capability on your breadboard module you must tie the IRQ user access point to ground to prevent undesired interrupts Co nfigu ri ng for To configure the module to generate
23. in Mainframe E1399 Fig2 5 Figure 2 5 Terminal Module Installation Chapter 2 Configuring the HP E1399A 21 Backplane Interface Circuitry The backplane interface circuitry allows you to access the backplane control signals data lines address lines and power supplies Approximately one fourth of the circuit board is reserved for installing the backplane interface components All of the components required for the interface are provided with the module and are already loaded and tested Your VXIbus mainframe can communicate with the HP E1399A in a manner similar to other VXIbus plug in modules The backplane interface circuitry consists of the following functional groups Address Lines and Register Decoding Data Bus Drivers Status Register ID Register Device Type Register Control Register DTACK Interrupt and Control Backplane Signals and Voltages Available on the Module The following sections discuss the backplane interface functional groups Each section includes a description partial schematics timing diagrams where applicable and a parts list showing the components required by that group See Appendix B HP E1399A Parts List Schematic for a complete parts list and for a schematic of the entire backplane interface Note In the discussions of hardware operation that follow a high state 1 is indicated by a positive voltage usually 5 V and a low state
24. quantity the check digit abbreviated CD and the description Address the order to the nearest Hewlett Packard Sales and Support Office addresses are provided at the back of this manual Terminal Block Parts List HP Part Number Total Qty Description E1300 84401 E1300 01202 E1300 44101 1515 2109 1390 0846 E1399 66510 E1399 26510 0361 1294 1252 1593 Terminal Board Case Assembly Strain Relief Clamp Clear Molded Cover Screw PH 10 24 by 5 8 Screw PH M25 by 15 SL Ma aa Terminal Breadboard Assembly Blank Terminal Breadboard Rivet 0099 by 0328LG Connector Right Angle 96 Pin aya Appendix B HP E1399A Parts List Schematic 51 Breadboard Parts List ron Reference Designator HP Part Number Total Qty Description P1 U6 C44 C38 42 C45 46 F1 F2 R9 RP1 2 25 RP26 32 SP1 2 U21 U10 14 U5 U9 20 U13 U17 U18 U16 35 U7 8 U15 E1399 66201 E1399 00202 E1300 84308 E1300 84309 0515 0444 0515 1968 3050 0082 E1399 26501 0050 2183 0361 1295 0361 1294 1252 1596 1820 6731 0180 1746 0160 4835 0160 4835 2110 0665 0757 0417 1810 0279 1810 0279 3101 3066 1820 4643 1820 3975 1820 4057 1820 4242 1820 4086 1820 3631 1820 3714 1820 3079 1820 4147 NMNMNANANHHNWANNOHHNMNNHANNNH HHH Breadboard Assembly F tPanel blank formerly E1399 00201 Handle Front Panel HP logo formerly E1300 04115 Handle Front Panel VXI logo
25. that occurs across the module when the specified airflow is applied Note It is the user s responsibility to furnish adequate cooling for any module to be used in a V XIbus system Module cooling requirements are described in the VXIbus Specification Rev 1 3 in Section B 7 2 4 Mainframe cooling requirements are discussed in Section B 7 3 5 For ease of integration you should label the airflow requirements for your finished application circuitry on the module For example the label might read 0 3 liters sec 0 2 mm H20 Due to the nature of a breadboard module it is not possible to specify cooling requirements without knowing the application and the amount of power to be dissipated Given the application however cooling requirements may be estimated as follows 1 Determine the airflow required as a function of power dissipation To maintain a 10 C rise approximately 0 08 liters second are required for every watt dissipated For example if a module dissipates 20 watts 1 6 liter second of airflow is required for cooling 2 Establish the relationship between airflow and pressure drop For a breadboard loaded with typical components such as ICs relays and a few heat sinks the curve in Figure 2 3 may be used to determine the pressure drop across the module Determine the pressure drop as the intersection of the curve and the required airflow For example if the airflow required is 1 6 liter second the pressure drop across a t
26. 13 Table 2 8 Control Register Bit Definitions Data Bit s Definitions CRO CRESET software reset CR1 SYSFAIL INHIBIT CR2 CR7 Device Dependent User assignable Table 2 9 Control Register Parts Reference HP Part Number Description Designator U13 1820 4086 IC 74H T 73 Octal D Type Flip Flop 1 HRESET 9 F7 61 E U13 CONTROLL 7 CLK FROM U2 IC 28 3 1p Q2 CRI SYSFAIL DBS 4 5 CR3 INHIBIT DB5 J 2D 2Q 6 CR5 TO U2 1A 3D 3Q DB 8 an 409 CR7 DB6 13 5p 5042 CR6 DB4 14 ep 60U5 CR4 DB2 17 7p 7018 CR2 DBO 18 gp 80 49 CRO CRESET TO U2 1D From Data Bus Drivers 1399 fig2 10 Figure 2 10 Control Register Table 2 8 shows the Control Register bit definitions The Control Register is selected for writing to by the BASE 4 enable line see Table 2 2 BASE 4 going low at the input of U21C combined with a negative pulse for one clock cycle of SYSCLK from the LATCH output of U6 also applied to U21C provides a positive going edge clocking pulse CONTROL to U13 This pulse clocks whatever is present on DBO DB7 through U15 to the Control Register access points CRO CR7 Chapter 2 Configuring the HP E1399A 29 DTACK Interrupt and Control DTACK Users may connect any or all of these points to custom circuitry keeping in mind the pre defined bit assignments
27. 8 p25 57 ROS cos EL A 13 LWORD x gt 26 M5 58 IRQ5 90 A 12 Pack PUCK k AS ETT B26 50 eo D s au A27 B27 KH INTERRUPT VECTOR SEU gos 50 RoS 008 2210 REGISTER LOW VID A29 29 M2 829 61 IRQ2 cog 83 9 aso 20 AQ 830 82 F i cao 94 8 F2 12V Inet Uti OBEN 31 12VR 63 455 95 12VR y LIA 69 sz a BP Ga a C31 06 va o ot Switch SPI A32 832 c32 Position 1 C wem 8 o o o 1 2 IM Y CADOR 5 5V 7 We rop Aa Y2 SE 6 el De ACKADDR 3 lo Y _ ot 8 12 5 o 5 19 Die Ya Den 4 pool 10 Gs Y5 E o Va y 2 d AT Y GROUND O 34 1 16 o oH 13 Slag Ya VME BACKPLANE INPUT BUFFERS Es i SySRESET ELE deg t EE uc peas d JACION gt U208 AS s EL IR 3 gt f AS CADDR gt 1 U20F 1 OTACKINH ette AO 1 WRITE U20D st osil 3 De oso I EE eu Denk EL 1 5 AO 6 sys gt 21 00 EE WER E REA D VU 4l ISS BUS BUFFERS rig 1 U35 l DIR 1 DWE 15 0 i 1 a C 2 fm B1 l 1 RP32 I 3 Je B2 4 7K 4 as 83 I SE B4 l BA 85 I 1 16 86 1 I B 87 I i 3 Je B8 H I I I l U16 i I l d L 21 81 l RP26 3 2 82 4 1K l ta 83 l 5 B4 l 8 a5 B5 l l 116 86 i i BA 87 i 3 Je 88 Ds Posts He e a coll oo o is Rum EA EN ed 4 Figure B 1 HP E1399A Breadboard Schematic 1 of 2 54 HP E1399A Parts List Schematic Appendix B
28. ACFAIL AC Input Power failure BERR Bus ERRor signal SERCLK Synchronizes data transmission on the VMSbus SERDAT Used for VMSbus data transmission Table 2 14 User Access Points Implemented Signals A1 A5 Backplane address lines A1 A5 latched BASE 0 ID Register Enable line BASE 2 Device Type Register Enable line BASE 4 Status and Control Registers Enable line BASE 6 User assignable Enable line BASE 8 User assignable Enable line BASE A User assignable Enable line BASE C User assignable Enable line BASE E User assignable Enable line CR2 CR7 Control Register output lines DBO DB15 Breadboard Module internal Data Bus lines DSO amp DS1 Buffered data strobes SRO SR1 Status Register pulled up SR2 Status Register pulled up SR3 Status Register pulled up SR4 SR7 Status Register pulled up DBEN Data bus buffer enable CRESET Card RESET software CRO or hardware SYSRESET DTACK Data Transfer ACKnowledge DTACK high DTACK low DTACK INH DTACK INHibit AS Buffered address strobe SYSFAIL Card failure signal jumpered to GND SYSFAIL INH SYSFAIL INHibit jumpered to GND HRESET Hardware RESET from SYSRESET IRQ Interrupt ReQuest line User implemented jumper to ground LATCH Latches data into write registers PIACK Peripheral Interrupt ACKnowledge line CADDR Card ADDRess match Chapter 2 Configuring the HP E1399A 35 Power Supplies All of the power pins on P1 as shown in Table
29. Contents HP E1399A Breadboard Module User s Manual Drug T a P Ook EE 3 pb oc hot e eae Cee de T7 4 Salely Symbols sides SHEE A E ARE EOE EO OEE SOS OES 4 Declan of Camron ss a kt ke o Ur po obe EE 3 Reader Comment SINGLE sida oe eh dose oo oru e po Dba eed 7 1 AP S994 DHEOGOHOBOU qu 3 uoa d Boy Se Se ERE ERE SERRE RES 9 Mama COGS us dos hae RR ge e dee A Des b Sede te ed 9 Specification Compliance Warranty 5 cc 64 es eb eee y xx 9 HPEI3DUA Descrip ui ace oo ESRB ue EROR CORR RR KE RRS 10 General Module Features 444 de gy RO SURE EES REOR Y Eo Rex 10 Backplane Inteitace Petes A sos goo omo RARA 10 HP EI 399A Hardware Features oas cc ook zou NEE RR RS KREGER HS 13 2 Comites the HP E1399 poa oak eR eR pde eue ec oe epe NR eod 15 Handling PECHOS uae be beet ah kb LEDGES EERE ROE EES 15 Reducing Risk of Static Discharge Damage ooo o 16 Hardware Leet dlc soda oe eS ase cR ES OES RON dee died 16 Backplane Connectolll sea oi Eke P e be ee eR Eee OO o 16 Module Dimensions sasse ode Reo ek AAR ERR ARE ORB DEREK 16 Cooling REGUIEMER S 19 544 445646 S40 A RU REY 19 Tenninal Module s m 20 Backplane E Ceuty uo ack x Rak RASH Eo E E MER R IS BRA 22 Address Lines and Register Decoding 2 222 9X RR Y x 22 Das Bus D VERI 40400640 uk 8 a pide pec dub Ron he Ae E e e 29 nius REISE acu dok ook ood ROSE LEED HELE PEEK dep dedi s 26 Deuce Type Reisen zu kos he bee Pe dar So dS 27 A o sige ab d eve Be II T ew p Oe SH b
30. ESSEE y PEE HEWLETT PACKARD COMPANY Measurement Systems Division E Learning Products Department P O Box 301 Loveland CO 80539 9984 Mmmm an fold here Please pencil in one circle for each statement below Disagree X Agree e The documentation is well organized O O O O O e Instructions are easy to understand O O O O O e The documentation is clearly written O O O O O e Examples are clear and useful O O O O O e llustrations are clear and helpful O O O O O The documentation meets my overall expectations O O O O O Please write any comments or suggestions below be specific 8 HP E1399A Register Based Breadboard Module User s Manual Chapter 1 HP E1399A Introduction Manual Contents This manual has three chapters and two appendixes Chapter 1 Introduction summarizes manual contents warranty status and specification compliance It also includes an overall description of the module Chapter 2 Configuring the HP E1399A describes module hardware and dimensions and discusses operation of the backplane interface circuits on the module It also provides a typical application example showing user circuits connected to the backplane interface circuits Chapter 3 Using the HP E1399A shows how to use the module in a V XIbus system Appendix A HP E1399A Breadboard Specifications lists the hardware specifications for the HP E1399A module e Appendix B
31. FITNESS FOR A PARTICULAR PURPOSE HP shall not be liable for errors contained herein or for incidental or consequential damages in connection with the furnishing performance or use of this material This docu ment contains proprietary information which is protected by copyright All rights are reserved No part of this document may be photo copied reproduced or translated to another language without the prior written consent of Hewlett Packard Company HP assumes no responsibility for the use or reliability of its software on equipment that is not furnished by HP Restricted Rights Legend Use duplication or disclosure by the U S Government is subject to restrictions as set forth in subparagraph c 1 ii of the Rights in Technical Data and Computer Software clause in DFARS 252 227 7013 Hewlett Packard Company 3000 Hanover Street Palo Alto California 94304 U S A Rights for non DOD U S Government Departments and Agencies are as set forth in FAR 52 227 19 c 1 2 LA HEWLETT PA PACKARD HP E1399A Register Based Breadboard Module User s Manual Edition 2 Copyright 1995 Hewlett Packard Company All Rights Reserved HP E1399A Register Based Breadboard Module User s Manual 3 Documentation History All Editions and Updates of this manual and their creation date are listed below The first Edition of the manual is Edition 1 The Edi tion number increments by 1 whenever the manual is revised Updates which are issued be
32. ROM CONFIGURATION REGISTERS E1399 fig2 7 Figure 2 7 Data Bus Drivers Table 2 4 shows the status register bit definitions See Chapter 3 Using the HP E1399A for additional information on using the status register Refer to the VXIbus Specification Section C 2 1 1 2 for detailed information concerning status register implementation restrictions Table 2 4 Status Register Bit Definitions Data Bit s Definitions SRO SR1 Device Dependent User assignable SR2 0O Failed Executing Self test 1 Passed Self test SR3 If 0 and Passed bit 1 Extended Self test active SR4 SR7 Device Dependent User assignable As shown in Figure 2 8 the status register circuitry consists primarily of the data bus line Driver U14 and a resistor network Table 2 5 shows the parts list for the status register The status register is enabled during a read status register operation by the BASE 4 enable line set low decoded from address lines A1 A3 and by 26 Configuring the HP E1399A Chapter 2 WRITE set high false The information presented to U14 by status lines SRO SR7 is placed on the internal data bus DBO DB7 The user must provide any latches required to latch and hold this information Table 2 5 Status Register Parts Reference HP Part Number Description Designator RP2 1810 0279 Resistor Network 9 by 4 7kOhm U14 1820 3975 IC 74HC541 Octal Line Driver Device Type The Device Ty
33. RP25 1810 0279 Resistor Network 9 by 4 7kOhms SP1 3101 3066 Switch DIP 8 rocker 0 05A 30VDC U11 1820 3975 IC 74HC541 Octal Line Driver U20A 9C 1820 4242 IC 74HCT14 Schmitt Trigger Inverter U17 18 1820 3631 IC 74HCT688N 8 bit Magnitude Comparator U7 8 1820 3079 IC 74HC138N 3 to 8 Line Decoder U15 1820 4147 IC 74HCT573 Octal D Type Latch LWORD AMO AMT AM2 AM3 1 G U18 1 C U17 AMA AB Aro AM3 Ze Ge Kees DCS n ud H y 2 A7 13 e AIS 13 d 12 15 oc Al4 15 56 A9 Le AS ien 19 P Q P Q Al 8 3 3 Q0 Q0 10 Sa So e H S Q2 45V 02 AS sal 2 AB a4 4 Q4 71405 14 s AT 12 16 16 AS 9 tal 181 e 07 Q7 A10 An TNT EI Se A12 RP25 from U6 A13 4 7K See 2 3 45 617 8 9 10 PER U18 A15 ES 9 NIOX 7 NTINI ZW 3 19 6 8 9 1012 5 e epi 1 2 3 4 5 j6 7 B8 6 Hp y D DBO 1 3 45 vol DBI ji s A AS y3 16 DB A4 Y4 15 DB eet AS vs p DB4 DATA BUS DRIVERs 13 DB5 E 12 8 We 12 DBS 13 II ag vg l DBZ CADDR ENABLE LINES Ha Ug wll O BASERO LD REGISTER 2 B Yi 14 BASE 2 DEVICE TYPE REGISTER 3 C Y2 e BASE 4 STATUS CONTROL REGISTER Y3 BASE 6 id oc U15 5 Mi 6 yg PSU BASE 8 L 61 ys 0 BASE A DEVICE DEPENTENT 14 LEN A 62A Yo BASE C 2 628 np BASE E Zu 1002 LCADDR A1 3 A2 2Q 18 LAT A2 az PNT Lio AS 5 A4 208 LAS M Blas BAIE LM A5 7 6 sollt Lu AT Wies 1 15 DEVICE TYPE REGISTER ENABLE 12 an A E A Se 2 S me Y p CONTROL REGISTER ENABLE V Ae yop 12 Y3 ES RO ACKNOWLEDGE LEVEL SELECT
34. SC S 10 CONTROL 5 pos rol 091 RECISTER DSOx T DSO ENABLE SYSCLK 2 CLK 5V Ges U20D p m DTACK pen 2 po 18 DTACK DTAC 13 ob rca LATCH WRITE ud DBEN E DATA BUS ENABLE U15 LATCHES A1 A3 WRITE DESABLES THE READ REGISTERS E1399 FIG2 11 Figure 2 11 DTACK Circuitry 30 Configuring the HP E1399A Chapter 2 In the first part of the transfer cycle the system controller places the address of the breadboard module on the backplane address A1 A15 address modifier AMO AM5 and address strobe AS lines and then sets the appropriate data strobe lines low DSO and DS1 for a D16 device When the address equality detectors U17 U18 detect the address match the output of U17 goes low This low is sensed at the Card ADDRess CADDR input to U6 which together with the active data strobes tells the DTACK state machine in the Interface IC U6 that the module has been addressed for a data transfer cycle This starts the state machine with all signals being clocked by SYSCLK 16 MHz In the first active state the data bus drivers U16 U35 are enabled and the register specifier part of the address A1 A5 is latched onto the outputs of U15 using the Data Bus ENable DBEN output of U1 If the data transfer cycle is a read operation as indicated by WRITE high the decoded output of U8 determines which one of the registers Status ID or Device Type is enabled to put its contents
35. SRO SR7S gip ph ple oculta e a e we El399A FIG3 1 Figure 3 3 Control Register Access Points Chapter 3 Using the HP E1399A 41 Writing to Control To write to the control register from the backplane data lines you must Reg ister implement the following signal and control lines 1 Address the module correctly by placing the data shown in Table 3 4 on the backplane address lines Table 3 4 Backplane Address Lines Control Register Line s Data Required Lines A1 A3 Lines A4 A5 Lines A6 A13 Lines A14 A15 Lines AMO AM5 Line LWORD Must be set low high low 010 to select the BASE 4 enable line BASE44 set low provides an enable function at U21C for control register drivers U13 to be clocked by the LATCH pulse See Table 2 2 Must both be low 0 to enable 3 to 8 line decoder U8 Must equal the logical address of the module as set on DIP switch sw Must always be set high 1 to access the upper 16K of address space Must be set to either hexadecimal 29 10 1001 or hexadecimal 2D 10 1101 Refer to the VMEbus Specification and the VXIbus Specification Rule C 2 10 Must always be set high false since this is a 16D device short word transfer 16 bits or less 2 This is a write operation so WRITE must go low true to provide the LATCH signal from the DTACK state machine in U6 LATCH is a one clock cycle negative going pulse that is applied to the other input to U21C
36. cess points Just remember that you must provide your own fusing and filtering on board the module for each power supply you access from the backplane You must also provide adequate cooling for dissipation of the heat generated by the power requirements of your customs circuitry See Cooling Requirements in Chapter 2 for more information on establishing cooling specifications for your module Recommended power supply voltage applications are listed in Table 3 5 Table 3 5 Power Supply Voltage Applications Supply Application 5 VDC Main power source for all systems Used for supplying power to logic devices 12 VDC General purpose power for switching power converters analog devices and disc drives 12 VDC General purpose power for analog devices 5 VDC Stdby Power to sustain memory clocks etc when 5 V dc is lost User may supply this power if necessary 48 Using the HP E1399A Chapter 3 Appendix A HP E1399A Breadboard Specifications Mechanical VXIbus Interface Power and Cooling Module Size Weight Connectors Used Number of Slots Used User Component Area Grid Hole Spacing Grid Hole Inside Diameter Max Component Height Maximum Lead Length Device Type VXIbus Interface Capability Interrupt Level Maximum Power Dissipation Power Requirements Watts per Slot 0 7 Kg P1 1 222 mm X 96 cm 8 75 in X 3 78 in 2 54 mm X 2 54 mm 0 1 in X 0
37. e clean handling and anti static techniques when handling the module to protect the sensitive components from damage due to electro static discharge ESD Chapter 2 Configuring the HP E1399A 15 Reducing Risk of Static Discharge Damage The smallest static voltage most people can feel is about 3500 V It takes less than one tenth of that about 300 V to destroy or severely damage static sensitive circuits Often static damage does not immediately cause a malfunction but significantly reduces the component s life Adhering to the following precautions will reduce the risk of static discharge damage e Keep the module in its conductive plastic bag when not installed in a VXIbus mainframe Save the bag for future module storage Before handling the module select a work area where potential static sources are minimized Avoid working in carpeted areas and non conductive chairs Keep body movement to a minimum If possible use a static controlled workstation Avoid touching any components or edge connectors When you are ready to configure the module remove it from its protective bag and lay it on top of the bag while keeping your free hand in contact with the bag This technique maintains your body and the module at the same static potential When you install the module keep one hand in contact with the protective bag as you pick up the module with your other hand Then before installing the module move your free hand to a metal
38. ee de A 29 DTACK Interrupt and Control i2 ccu roo x Rx 30 Uses Access POIDS que qoo E Eod KES eode o Rod d CUR TRE verde de dd 35 Power SUEDE 2a qq pd Ing bcn petes qid obe ode i ob e o nb de i ole en 36 S Usme Me EP BIOS 2 222493 4 2 d ABE A RESEDA 37 Reading Data Promi Registers 4 54444 x A REO KEES RA 37 Status Register Bit Debitis uus scu d ee oe ee RIO d 37 Reading the Status Register osmosis RRR ESLER SES 39 Write Data to Control Register hee eck ie cee 9 RR Ree PREY eg 41 Control Register Bit Oehimuens uuu sack apos bee ee E RE ER dete RES 41 Writing to Control Register eeo ceog 66 bb bdo eed ee EERE ROE HES 42 Meter MENDE o ande a ARERR DOERR A e RC e ede RE LE 44 Configuring for Intetmpls ecos pd do Rue SHOR ESR EE 44 Generating Last Requests iu us eue de ee eR Ree ORO A 44 HP E1399A Breadboard Module User s Manual Contents 1 Resetting thie Module eposa oko poA ERE eoo ek op on V ee EE of ded Hardware Reset 2246 oom ee EERE EELS SEEKS RR s DOGS RES e e a ahhh kh DE AKER REDEEMER de Oe ee eA Deri EO auus obe eee Be BA ek e eg e ee dad Using Other Power S ppli soe eda korr Re EKER RAR A HP E1I399A Brealboard Specifications rossi DR RR A UR ERR ES B HP E1399A Parts List chematie cse 64444684664 66 XO OR X OES Terminal Block Parts List occiso Breadboaid Parts List 26406 ge DO me OS de odo Xo E Dw DHEA OR xc eB Backplane Interface SCALE ues d Rx m AR AUR EUR REOR huke ngpa Notes 2 HPE1399A
39. er capability It does not contain an interrupt handler Interrupt priority is jumper selectable for pulling the appropriate interrupt request line IRQ1 IRQ7 Interrupts are generated by the IRQ state machine on the Interface IC U6 The daisy chained IACKIN IACKOUT signal pair is implemented Module Reset Both hardware and software reset signals are provided to initialize the backplane interface circuitry and your own custom designed circuitry to a known state Backplane Buffering Buffering is provided for all signals that interface with the V XIbus backplane Power Supply The following power supply voltages all unfiltered are available 5 VDC fused at 4 Amps 12VAC fused at 4 Amps 12VAC unfused 5VDC standby unfused 12 HP E1399A Introduction Chapter 1 HP E1 399A An overview of the HP E1399A hardware features follows Hardware Features l e Connectors Two 96 pin DIN connectors are provided with the module P1 connects to the VXI backplane while J1 allows connection of devices from the front of the board or connection of an E1399A terminal card Component Area An area of approximately 220 cm 34 in is available on the module to install your own custom circuitry This area does not include the portion of the circuit board required by the backplane interface components Component Height Lead Length The maximum component height allowed above the circuit board is 12 7 mm 0 5 in The ma
40. errupts 30 44 L Logical Address 24 Module Description 10 16 Module Dimensions 16 Module Features 10 Module Reset 12 47 Module Terminal 20 P Parts List 52 Power Supplies 36 48 Power Supply 12 HP E1399A Breadboard Module User s Manual Index 57 R Read Write Register 12 Reader comment sheet 7 Reading Data 37 Reading the Status Register 39 Register Decoding 10 22 Registers Control 29 Control Register 41 Device Type 27 Reading 37 Status 26 37 Writing 41 Reset 12 47 S Safety warnings 4 Schematic 52 Specifications 49 50 Status Register 12 25 26 37 Reading 39 T Terminal Block Parts List 51 Terminal Module 20 U User Access 35 W WARNINGS 4 Warranty 3 Writing to Control Register 41 Writing to Registers 41 58 HP E1399A Breadboard Module User s Manual Index
41. esent any condition that you define The inputs to the status register are provided by the user from the custom circuitry on the module Access points SRO SR7 are provided on the module to tie into the status register as shown in Figure 3 1 You must add latches to the circuitry if you need to latch your status bits to catch a transient condition Otherwise you can tie into the status register line drivers directly at the access points provided Chapter 3 Using the HP E1399A 37 Table 3 1 Status Register Bit Descriptions Data Bit s Defintions SRO SR1 Device Dependent User assignable SR2 0 Failed Executing Self Test 1 Passed Self Test SR3 If 0 ands Passed bit 1 Extended Self Test Active SR4 SR7 Device Dependent User Assignable SRO SR74 9 E1399A FIG3 1 RPe U14 U13 Figure 3 1 Status Register Access Points Using the HP E1399A Chapter 3 Reading the Status For example assume you need to use up to 8 bits of the status register To Reg ister latch your status data and then read the 8 bit contents of the status register onto the backplane you must implement the following signal and control lines 1 Address the module correctly by placing the data shown in Table 3 2 on the backplane address lines Table 3 2 Backplane Address Lines Statu
42. formerly E1300 041 16 Screw PH M25 by 08 Torx Screw PH M25 by 11 Washer Flat Non Metalic PC Board Blank Bracket Panel Mount Rivet 0099 by 0406LG Rivet 0099 by 0328LG Connector Right Angle 96 Pin IC Interface PAL Fixed Capacitor 15 uF 1096 20 V Fixed Capacitor 0 1 uF 10 50 V Fixed Capacitor 0 1 uF 10 50V Fuse Subminiature 1A 125V Fixed Resistor 562 Ohm 1 1 8 W Resistor Network 9 by 4 7 kOhm 10 pin Resistor Network 9 by 4 7 kOhm 10 pin Switch DIP 8 rocker 0 05 A 30 V dc IC 74HCTO2N Quad 2 input NOR Gate CMOS IC 74HC541N Octal Line Driver CMOS IC 74F38N Quad 2 input NAND Buffer TTL IC 74HCT14 Hex Schmitt Trig Invrtr CMOS IC PC74HCT273N Octal D Type Flip Flop CMOS IC 74HCI688N 8 bit Magnitude Comp CMOS IC 74ALS245A 1N Octal Bus Xcvr 3 state TTL IC 74HC138N 3 to 8 line Decoder CMOS IC 74HCI573 Octal D Type Trnspnt Latch CMOS indicates part used on modules with serial numbers 2934A00824 and earlier Backplane Interface Schematic Figure B 1 shows the complete schematic of the digital backplane interface circuitry See Chapter 2 Configuring the HP E1399A for information on individual interface groups 52 HP E1399A Parts List Schematic Appendix B Appendix B HP E1399A Parts List Schematic 53 VME CONNECTOR P1
43. interrupts you must first assign an Interru pts interrupt level to the module Levels 1 7 are available with level 7 being the highest level Connect a jumper in two places for the selected level one for the IRQ REQuest line and one for the IRQ ACKnowledge line As shown in Figure 2 12 Chapter 2 jumpers have been installed to select interrupt level 1 IRQ1 Remember both level selects must be the same Gene rating To generate the interrupt request and accept the interrupt acknowledgment Interru pt Req uests from the interrupt handler you must implement the following actions 1 You must provide the interrupt request from your custom circuits by setting the IRQ access point high 1 when the interrupt is to occur 2 Monitor PIACK after setting IRQ After PIACK goes low true and before it goes high false release IRQ or another interrupt will be generated 3 If you do not implement the interrupter capability leave the jumper between IRQ and GND intact 4 Your system controller and or interrupt handler must react to the signal timing in the Interface IC U6 for the IRQ and DTACK state machines as shown in Figure 3 5 5 The circuitry provided implements a read operation for only the lower 8 bits of status ID during the interrupt acknowledge cycle using PIACK to enable buffer U11 If you want to use the upper 8 bits also you must provide an additional buffer to the internal data bus that is enabled by PIACK low true and
44. itry is implemented and accessible according to the requirements outlined in the VXIbus Specification Users can still provide custom extensions to expand module addressing capability to A24 or A32 by adding appropriate circuitry according to the VMEbus and VXIbus specifications Backplane Interface An overview of the HP E1399A interface features follows Figure 1 1 Features Shows a block diagram of this interface Note For hardware operation a mnemonic suffixed with an asterisk such as WRITE indicates inverse logic 0 or low true 1 or high false A high state 1 is defined as a positive voltage usually 5 V and a low state 0 is defined as zero V ground at the specified signal point The HP E1399A interface features are e Address Lines and Register Decoding The module implements 15 address lines A1 A15 to allow for 1 decoding one of 255 switch selectable logical device addresses in the upper fourth of the A16 VME address space and 2 selecting one of the breadboard configuration registers for read write operations The module decodes the Address Modifier lines AMO AMS and acts on codes 2916 and 2D 16 only e Data Lines Data lines DO D15 are available for use on the Breadboard module These 16 lines are buffered by data bus drivers and used for writing to and reading from the configuration registers Status ID Device Type and Control via an internal data bus DBO DB15 10 HP E1399A Introduction Chapter 1
45. onto the module s internal data bus DBO DB15 The next state then generates a high at the DTACK output of U6 This forces DTACK low true on the backplane through USC acknowledging to the system controller that the module has received the request for data and has placed the contents of the specified register onto the data lines With U16 and U35 enabled internal data lines DBO DB 15 are connected directly to the backplane data lines DO D15 If the data transfer cycle is a write operation as indicated by WRITE low an additional state sets the U1 LATCH output low enabling the Control Register to receive data from the data bus drivers before DTACK is set low true The resulting Control Register outputs CRO CR15 can then control the user s circuits as desired Again DTACK going low true tells the system controller that the data transfer cycle is complete In a write operation WRITE going low true disables the Status Register the ID Register and the Device Type Register For both read and write operations the DTACK state machine holds DTACK low and the address latched until the data strobes are invalid After the data strobes go invalid the data bus drivers are disabled and the address latch is released In the next state DTACK is released and the state machine returns to the idle state If the DTACK INHibit signal DTKINH is set high it is wire jumpered low on the HP E1399A implementation it allows the user to hold
46. operation can be verified by service trained personnel If necessary return the product to a Hewlett Packard Sales and Service Of fice for service and repair to ensure that safety features are maintained DO NOT service or adjust alone Do not attempt internal service or adjustment unless another person capable of rendering first aid and resuscitation is present DO NOT substitute parts or modify equipment Because of the danger of introducing additional hazards do not install substitute parts or perform any unauthorized modification to the product Return the product to a Hewlett Packard Sales and Service Office for service and repair to ensure that safety features are maintained 4 HP E1399A Register Based Breadboard Module User s Manual Declaration of Conformity according to ISO IEC Guide 22 and EN 45014 Manufacturer s Name Hewlett Packard Company Loveland Manufacturing Center Manufacturer s Address 815 14th Street S W Loveland Colorado 80537 declares that the product Product Name Register Based Breadboard Module Model Number E1399A Product Options All conforms to the following Product Specifications Safety IEC 1010 1 1990 Incl Amend 1 1992 EN61010 1 1993 CSA C22 2 1010 1 1992 UL 1244 EMC CISPR 11 1990 EN55011 1991 Groupl Class A IEC 801 2 1991 EN50082 1 1992 4kVCD 8k VAD TEC 801 3 1984 EN50082 1 1992 3 V m TEC 801 4 1988 EN50082 1 1992 1kV Power Line SkV Signal Lines Su
47. pe Register is an 8 bit register which contains a Reg ister device dependent module type identifier This field is set on the module by the use of an 8 position DIP switch on the inputs to the data bus line driver U10 as shown in Figure 2 9 Table 2 7 shows the resistor and IC part numbers for a Device Type Register 5v RP2 47K 2 3 4 5 6 y s 10 Lou 1 BASE 4 401 ig 014 WRITE ml 402 STATUS 0 0 Za y 18 DBO DBO STATUS 10 S A2 yo HZ DB1 Nen STATUS 2O SIE y3 16 DB2 082 STATUS 30 i 3 A4 HUE DBS 083 STATUS 4 O D Sas ys 4 m 084 STATUS 50 L ag Ye 113 DB5 Bee STATUS 6 O i 8 47 y7 i2 DB6 D86 STATUS 7 O D Has ye H OB 087 TO DATA BUS DRIVERS E1399 fig2 8 Figure 2 8 Status Register Chapter 2 Configuring the HP E1399A 27 Table 2 6 Device Type Register Bit Definitions Data Bit s Definitions DBO DB7 DB8 DB15 Device Type or Model Code Range 0 4095 Set to 1 Table 2 7 Device Type Register Parts Reference Designator HP Part Number Description RP1 U10 SP2 1810 0279 Resistor Network 9 by 4 7kOhm 1820 3975 IC 74HC541 Octal Line Driver 3101 3066 Switch DIP 8 Rocker OSA 30VDC Each bit in the Device Type Register is normally pulled high 1 by RP1 1 5V RP 1 4 7K
48. pplementary Information The product herewith complies with the requirements of the Low Voltage Directive 73 23 EEC and the EMC Directive 89 336 EEC and carries the CE marking accordingly Tested in a typical configuration in an HP B Size VXI mainframe April 1995 ft QA Manager European contact Your local Hewlett Packard Sales and Service Office or Hewlett Packard GmbH Department HQ TRE Herrenberger Stra e 130 D 71034 B blingen Germany FAX 49 703 1 14 3143 HP E1399A Register Based Breadboard Module User s Manual 5 Notes 6 HP E1399A Register Based Breadboard Module User s Manual cut along this line Please fold and tape for mailing Reader Comment Sheet HP E1399A Register Based Breadboard Module User s Manual Edition 2 You can help us improve our manuals by sharing your comments and suggestions In appreciation of your time we will enter you in a quarterly drawing for a Hewlett Packard Palmtop Personal Computer U S government employees cannot participate in the drawing Your Name City State Province Company Name Country Job Title Zip Postal Code Address Telephone Number with Area Code Please list the system controller operating system programming language and plug in modules you are using fold here NO POSTAGE NECESSARY IF MAILED IN THE UNITED STATES BUSINESS REPLY MAIL FIRST CLASS PERMIT NO 37 LOVELAND CO E POSTAGE WILL BE PAID BY ADDR
49. precautions or with specific warnings elsewhere in this manual violates safety standards of design manufacture and intended use of the product Hewlett Packard Company assumes no liability for the customer s failure to comply with these requirements Ground the equipment For Safety Class 1 equipment equipment having a protective earth terminal an uninterruptible safety earth ground must be provided from the mains power source to the product input wiring terminals or supplied power cable DO NOT operate the product in an explosive atmosphere or in the presence of flammable gases or fumes For continued protection against fire replace the line fuse s only with fuse s of the same voltage and current rating and type DO NOT use repaired fuses or short circuited fuse holders Keep away from live circuits Operating personnel must not remove equipment covers or shields Procedures involving the removal of covers or shields are for use by service trained personnel only Under certain conditions dangerous voltages may exist even with the equipment switched off To avoid dangerous electrical shock DO NOT perform procedures involving cover or shield removal unless you are qualified to do so DO NOT operate damaged equipment Whenever it is possible that the safety protection features built into this product have been im paired either through physical damage excessive moisture or any other reason REMOVE POWER and do not use the product until safe
50. r input of U13 which drives all of the control register outputs access points CRO CR7 low 0 Software Reset Control register output bit CRO is used for the software reset If you write a 1 to bit CRO the CRESET access point on the module is driven low 0 by U21D You can use CRESET any way you choose in your custom circuitry Detecting Errors The breadboard module implements the following error fail circuitry e The status register implements bit SR2 as a self test Passed Failed bit see Table 2 4 If SR2 PASSED access point is set low 0 indicating your custom circuit self test either failed or is currently still executing and the SYSFAIL INHBT bit CR1 output of the control register has been set low O then the module sets the backplane SY SFAIL line low true through U21A and USD this is the default If either SYSFAIL INHBT or the PASSED bit are set high SYSFAIL remains high false The ACFAIL line has been stubbed onto the module from backplane connector P1 pin B3 and is available as a user access point for your convenience e BERR Buss ERRor If an invalid bus cycle is discovered this can be asserted instead of DTACK Chapter 3 Using the HP E1399A 47 Using Other Power Supplies You can use any of the other power supply voltages from a standard V XIbus backplane as described in the VXIbus Specification All of the available voltages have been stubbed onto the breadboard module as user ac
51. roduct HP does not warrant that the operation of the product or software or firmware will be uninterrupted or error free Limitation Of Warranty The foregoing warranty shall not apply to defects resulting from improper or inadequate maintenance by Buyer Buyer supplied prod ucts or interfacing unauthorized modification or misuse operation outside of the environmental specifications for the product or im proper site preparation or maintenance The design and implementation of any circuit on this product is the sole responsibility of the Buyer HP does not warrant the Buyer s circuitry or malfunctions of HP products that result from the Buyer s circuitry In addition HP does not warrant any damage that oc curs as a result of the Buyer s circuit or any defects that result from Buyer supplied products NO OTHER WARRANTY IS EXPRESSED OR IMPLIED HP SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Exclusive Remedies THE REMEDIES PROVIDED HEREIN ARE BUYER S SOLE AND EXCLUSIVE REMEDIES HP SHALL NOT BE LIABLE FOR ANY DIRECT INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES WHETHER BASED ON CON TRACT TORT OR ANY OTHER LEGAL THEORY Notice The information contained in this document is subject to change without notice HEWLETT PACKARD HP MAKES NO WAR RANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WAR RANTIES OF MERCHANTABILITY AND
52. s Register Line s Data Required Lines A1 A3 Must be set low high low 010 to select the BASE 4 enable line BASE 4 provides one half of the enable function for line driver U7 See Table 2 2 in Chapter 2 Lines A4 A5 Must both be low 0 to enable 3 to 8 line decoder U8 Lines A6 A13 Must equal the logical address of the module as set on DIP switch SP1 Lines A14 A15 Must always be set high 1 to access the upper 16K of address space Lines AMO AM5 Must be set to either hexadecimal 29 101001 or hexadecimal 2D 10 1101 Refer to the VMEbus Specification and the VXIbus Specification Rule C 2 10 Line LWORD Must always be set high false since this is a D16 device short word transfer 16 bits or less 2 This is a read operation so WRITE must remain high false to provide the second half of the U14 enable function 3 Set IACK high false to enable address equality detector U18 4 Set both data strobes DSO and DS1 low true to indicate a 16 bit data transfer Figure 3 2 shows timing required for the Interface IC U6 control and signal lines Chapter 3 Using the HP E1399A 39 Read D16 only min times m ATI E p NH AS Lan V SES Di Wi d INN Dm Data valid on VME bus D EN DTACK 0 125 62 5 62 5 62 5 NOTE Data s
53. shown in Table 2 2 Data present on DBO DB7 would have been written there by the same DTACK state machine data transfer cycle that provided the LATCH pulse See DTACK for a discussion of the DTACK state machine operation See Chapter 3 Using the HP E1399A for additional information on using the Control Register Refer to the VXIbus Specification Section C 2 1 1 2 for detailed information concerning Control Register implementation restrictions An Interface IC U6 provides the timing and control signals for standard data transfer cycles and interrupt requests acknowledgments Hardware and software reset signals together with a card fail signal have also been implemented The Data Transfer ACKnowledge DTACK circuitry is centered around the Interface IC U6 A state machine in this IC controls all read and write data transfer cycles Operation begins with the state machine in the idle state See Figure 2 11 for the following discussion Table 2 10 lists the parts for the DTACK circuitry Table 2 10 DTACK Circuitry Parts Reference HP Part Number Description Designator U21C 1820 4643 IC 74HCTO2N Quad 2 input NOR U6 1820 6731 IC Interface PAL U5C 1820 4057 IC 74F38N Quad 2 input NAND Buffer U20C D F 1820 4242 IC 74HCT14 Hex Schmitt Trig Invrtr U6 BASE 4 3 FROM ADDRESS ADDRESS MATCH CADOR DECODE CIRCUITS DTKINH z DTKINH U21C 8 U20C S
54. t registers using the extra enable lines provided Refer to Table 2 2 and to Figure 2 6 to see the user assignable enable lines Chapter 2 Configuring the HP E1399A 25 Table 2 3 Data Bus Drivers Parts Reference HP Part Description Designator Number RP26 32 1810 0279 Resistor Network 9 by 4 7kOhm U16 35 1820 3714 IC 74ALS245A 1 Octal Bus Trnscvr TTL Status Reg ister The Status Register is an 8 bit register which provides some specific status information as defined by the V XIbus Specification and which has other bits available for custom device dependent status information as implemented by the user EEN 080 DB7 WRITE FROM U6 FROM LOGICAL ADDRESS SELECT ACKADDR PIACK mm ma RP26 Nee 49 19 11 Hc U16 e U35 LK z x ES DIR 3 DB15 DB7 3 ome nee 4l 5 D813 DBS 5 D15 Al 81118 DBI Zu 81118 E e mz ome 6 ISS p ou nas 3 iy gu DB 3 Ju go 17 0814 8 D810 D82 8 16 D85 4 16 0813 A3 B3 S AS B3 9 089 DPI 9 e15 D84 Poe T M B4 15 DA A 8415 0812 10 pas go 10 AS B5 14 DB A5 B5 14 DB11 A6 36 13 87y Tas p m aL 081 Ste B712 089 P Ba 11 DB 9 8 B8 11 DB i A f lo Jos db bs ba bs e o bialn bis biais DO Io 102 ID3 104 IDS ID6 ID D8 ID9 101010 D12 1013 ID TO F
55. the state machine in the first state of latched address and enabled data bus drivers Chapter 2 Configuring the HP E1399A 31 Interrupt A priority interrupt scheme has been implemented using the Interface IC U6 Another state machine controls interrupt request and acknowledge operations See Figure 2 12 for the following discussion Table 2 11 lists the parts for the Interrupt Circuitry Table 2 11 Interrupt Circuitry Parts Reference HP Part Number Description Designator U21C 1820 4643 IC 74HCTO2N Quad 2 input NOR Gate U6 1820 6731 IC Interface PAL U5A B C 1820 4057 74F38N Quad 2 input NAND Buffer U20B C D F 1820 4242 IC 74HCT14 Hex Schmitt Trig Invrtr The VMEbus interrupt request levels IRQ1 IRQ7 are jumper selectable ENABLE LOGICAL o ADDRESS FROM ADDRESS BUFFER dE CIRCUITS VY 7 PACK 1 Am IRQ uma MIS JM20 RP32 000 AUR 4 7K JM13 JMI7 JM19 M16 po CONTROL 2 REGISTER ENABLE i RQ 7 6 5 43 2 1 ACKNOWLEDGE U6 LEVEL 4 RO ACKADDR REQUEST ro LEVEL IACKINe IACKIN 5V AS am21 O RQ2 ADDRESS MATCH SJ CADDR SE DTKINH 4 DTKINH 45V Me Ro I RAN USA MSO U20C MPA LA M24 O RO 0S0 KS 10 psg 1 9 an c wee Bi SYSCLK Zo U20D 19 9C PIACK 8 F SET IAckour LS WRITE i pTackH8 4 DTACK LATCH
56. trobe means CH DSO x DS when going high and DTACKINH high will hold DSO DS1 when going low DTACK cycle here until See hardware diagram DTACHINH goes low sync with SYSCLOCK Figure 3 2 Timing for Reading the Status Register 40 Using the HP E1399A Chapter 3 Writing Data to Control Register Control Register Bit Definitions The breadboard module contains circuitry for a control register You can write to this register from the backplane over data lines DO D15 The data is passed to the internal data bus DBO DB15 and then clocked into the control register for use by the custom circuitry on the breadboard at access points CR2 CR7 Table 3 3 shows the definitions preassigned to control register data bits per the V XIbus Specification Section C 2 1 1 2 Table 3 3 Control Register Bit Definitions Data Bit s Definitions CRO CRESET 1 Reset the module User defines reset actions CR1 SYSFAIL inhibit 1 Inhibit setting of SYSFAIL Reset 0 Safe CR2 CR14 Device Dependent User assignable CR15 1 Enable access to A24 A32 Registers 0 Disable You may connect any of the control register outputs to your custom circuitry using the control register access points CRO CR 15 shown in Figure 3 3 HRESETT 7 f I CRESET LEOTE Ki 1 D 1 1 OL iL abr eae he O i EG CRe CR7
57. tween Editions contain replacement pages to correct or add additional information to the current Edition of the manual Whenever a new Edition is created it will contain all of the Update information for the previous Edition Each new Edition or Update also includes a revised copy of this documentation his tory page Edition T2 n a eate Ree AINE dE Novemberr 1989 Update lu ci eere tee og pectet ee ROS November 1989 Edition Age AE US e SP ke PSUR pel OD ale OW April 1995 Safety Symbols Instruction manual symbol affixed to prod uct Indicates that the user must refer to the N Alternating current AC manual for specific WARNING or CAU TION information to avoid personal injury or damage to the product occ Direct current DC Indicates hazardous voltages Indicates the field wiring terminal that must be connected to earth ground before operat f ing the equipment protects against electri Calls attention to a procedure practice or cal shock in case of fault WARNING condition that could cause bodily injury or death Calls attention to a procedure practice or con Frame or chassis ground terminal typi CAUTION dition that could possibly cause damage to r3 or cally connects to the equipment s metal equipment or permanent loss of data frame WARNINGS The following general safety precautions must be observed during all phases of operation service and repair of this product Failure to comply with these
58. ximum component lead length allowed below the circuit board is 1 3mm 0 05 in Warning Since the inputs to the HP1399A Breadboard Module are through a 96 pin connector and a terminal card assembly limit voltage to 250Vdc 250Vrms Chapter 1 HP E1399A Introduction 13 14 HP E1399A Introduction Chapter 1 Chapter 2 Configuring the HP E1399A This Chapter contains a detailed hardware description of the breadboard module and discusses the backplane interface circuitry It also shows a sample application to control 16 relays on the module Handling Precautions WARNINGS CAUTIONS and guidelines to reduce the risk of static discharge damage to the HP E1399A follow Warning SHOCK HAZARD Only qualified service trained personnel who are aware of the hazards involved should install remove or configure any module Before removing any installed module turn off all power to the mainframe and to all external devices connected to the mainframe or to any of the modules For electrical shock protection ensure that the module face plate is securely tightened against the mainframe Warning Since the inputs to the HP 1399A Breadboard Module are through a 96 pin connector and a terminal card assembly limit voltage to 250Vdc 250Vrms Caution STATIC SENSITIVITY The backplane interface circuitry described in this Chapter uses static sensitive CMOS integrated circuit devices If you implement the circuitry described herein you must us
59. ypically populated breadboard will be approximately 0 05 mm H20 AL 34 co N T 24 E E HL 0 0 2 4 6 Liters Second Figure 2 3 Pressure vs Airflow Chapter 2 Configuring the HP E1399A 19 Terminal Module An optional terminal module is available for making external connections to the HP 1399A Breadboard Module This module consists of a connector mounted on a breadboard so that you can access the connector pins by soldering wires to the breadboard Figure 2 4 shows the layout of this terminal module Figure 2 5 shows how to make the connections and install the module Warning Since the inputs to the HP 1399A Breadboard Module are through a 96 pin connector and a terminal card assembly limit voltage to 250Vdc 250Vrms For electrical shock protection ensure that the module face plate is securely tightened against the mainframe before installing the terminal card ee aa 13994 FIG2 4 Figure 2 4 Terminal Module Assembly 20 Configuring the HP E1399A Chapter 2 1 Remove Clear Cover Ki di Unscrew and Remoye Strain Relief ill Ee T 5 1 Pry open with screwdriver G ES Ca ES k c Remove Breadboard with Attached Plug Attach Wires as Appropriate and Solder CR Reinstall the Clear Cover E E Connect Terminal Block to Module CN 5 Already Installed
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