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1. 6 75 a a arten ae ee cil ie ee eles 6 76 No Operation E 6 77 OR ReGISte 6 78 OR Small Immediate a a a ie 6 79 OR Large Immediate vanene daterer ide bunader 6 80 Coad Register fr m Stack u n Hebe E EE eee EA 6 81 Load Register from Stack a iiie ite iiti mr ace radert eden 6 82 Load Register to Stack ub Le a esee ei 6 83 Load Register to Stack uuu eredi ete o ate tenes aves eee 6 84 Ret from Subroutine with Delay 6 85 Return from Fast Interr pt cis cer cnc 6 86 Return from Interrupts as io denn ER Deo RR 6 87 Return from Software Interrupt a a emen ene 6 88 Rotate ket an a EE 6 89 Rotate Right Lara D S 6 90 Rotate Right with Carry u NU m 6 91 Subtract with Carry 6 92 Subtract with Carry Immediate a a nenne 6 93 he teen 6 94 Shit Left Byte Linate ende iu hua ob en Ee pe DER PH Oe asa ka 6 95 Side 6 96 Shift Right Arithmetic dee oe eed invari 6 97 Shift Right Pd 6 98 S btract Beglsler roten ode vi 6 99 Subtract Small IWWediate a uU SI a a 6 100 Subtract Extended Reg
2. dg Ur tui ec hand CalmRISC16 C Compiler 16 CalmRISC16 Relocatable Assembler CaIm8ASM emen enne CalmRISC16 Linker 8 Emulation Probe Board Configuration Use Clock Setting for External Clock Mode memes Sub Clock Setting The Eowpass Filter Tor PUL aiii ee eto Erbe po an un ad he l nt Powemr S eleCtlion Se Glock Selection sss a ma ee amu si S au Ri EM itte JP1 JP2 Pin Assignment erret es ere e JPA PincAssignment ua best fiske as S3CC11B FC11B MICROCONTROLLER xi List of Figures Figure Title Number 1 1 S3CC11B FC11B Top Block Diagram 1 2 S3CC11B FC11B Pin Assignments 100 1420 1 3 S3CC11B FC11B Pin Assignments 100 1414 1 4 Pin Circuit Type oscuro Aaa 1 5 Pin Circuit Type 2 RESET u u s nu nani asuaka houses 1 6 1 7 Pin Ci
3. 23 11 25 1 Descriptions of Pins Used to Read Write the FLASH 25 4 S3CC11B FC11B MICROCONTROLLER xvii List of Instruction Descriptions Instruction Full Instruction Name Page Mnemonic Number ADC 1 Add with Garry Register 6 21 ADC 2 Add with Carry mme nnns 6 22 ADD 1 Add Ftegister eiut te et ec DEBE e aa aa Deed dx 6 23 ADD 2 Add Small Immediate ete cte dex che e pee eere 6 24 ADD 3 Add Immediate e ev Re uet imp EE 6 25 ADD 4 Add Extended 6 26 ADD 5 Add Immediate to Extended 6 27 ADD 6 Add 5 bit Immediate to Extended 1 6 28 AND 1 AND REGISTER e ine 6 29 AND 2 AND Small Immediate ee 6 30 AND 3 AND Large e inet efe t er steven dead e gg 6 31 BITop BIT Operation argentineren 6 32 BNZD Branch Not Zero with 6 33 BR Conditional Branches re eh Leve Ite Ens 6 34 BRA EC Branch on External 6 35 BREAK BREAK Zu oss Eun EI oe E LO m au 6 36 BSRD Branch Subroutine wi
4. a a a nennen nenne 21 37 Short Direct Associated Addressing 21 38 Operating Voltage Range siosio ien aaie S nnne 23 4 Input Timing for External Interrupts Ports 0 Ports 4 a a 23 5 Input Timing tor RESET eti tr Re repe Io REF Peter m Face MOERS det asa ete 23 5 Stop Mode Release Timing When Initiated by a 23 6 Stop Mode main Release Timing Initiated by 23 7 Stop Mode sub Release Timing Initiated by 23 7 Clock Timing Measurement at XN ier enni enne 23 8 Clock Timing Measurement at XT 2 23 9 100 QFP 1420C Package 24 2 100 TQFP 1414 Package 24 3 SSFC11B Pin Assignments 100 142060 25 2 SSFC11B Pin Assignments 100 4 25 3 Emulation Probe Board Configuration 26 2 S3CC11B FC11B MICROCONTROLLER xv List of Tables Table Title Page Number Number 1 1 S3CC11B FC11B Pin esee nne nnne nnne 1 6 4 1 25 4 1 5 1 Registers ui
5. Wu qa nenne 6 7 LD Register H Immediate s u co eee ed ee 6 7 Branch Instr ctioris oo sn ecd u ee 6 8 Bit Operations En redd Ceo iti Nea ert ba as ue TE Ru tee 6 10 Miscellaneous Instructiorts ei Eee EEN 6 11 CalmRISC16 Instruction Set MaD ua nsspa 6 12 Quick Reference 6 17 S3CC11B FC11B MICROCONTROLLER vii Table of Contents continued Part Il Hardware Descriptions Chapter 7 PLL Phase Locked Loop Overview EL ee 7 1 Chapter 8 RESET and Power Down be A ee 8 1 Chapter 9 I O Ports Port Data Registers yn un ail ed Gs ae 9 1 Chapter 10 Basic Timer OA n atte me sent Seiad cepa baad ad i are 10 1 Basic Timer amp Watchdog Timer Block Diagram a mme 10 4 Chapter 11 Watch Timer M EE 11 1 Watch 15 Rr UR 11 3 Chapter 12 8 Bit Timer 0 OVOIVIOWS eee 12 1 Function Descriptions coi n inr Gee via ead vests 12 2 Timer 0 Control Register 12 3 Block ent 12 4 Chapter 13 16 Bit Timer 1 8 Bit Timer A amp B OVGIVIGW dear ene etu rtu h aa sipin 13 1 Interval Timer FUncliori eio e E etel mox
6. Register instruction is used to perform bitwise operation on two values in registers Rn and Ri The result is stored in register Rn The T bit is updated based on the result 15 14 13 12 4 8 7 6 5 4 3 0 jojojo m _ R Operation Rn Rn Ri T bit Rn Ri 0 if Rn R6 R7 Z0 Z1 Rn Ri 0 Exceptions None Notes None 6 110 ELECTRONES S3CC11B FC11B INSTRUCTION SET 2 XOR Small Immediate Format Description Operation Exceptions Notes XOR RO lt imm 8 gt This type of XOR instruction is used to perform bitwise XOR operation on two values in register RO and lt imm 8 gt The result is stored in register RO The T bit is updated based on the result 15 14 43 12 4 10 9 8 7 0 mm RO RO lt imm 8 gt T bit RO lt imm 8 gt 7 0 0 None The register used in this operation is fixed to RO Therefore the operand should be placed in RO before this instruction executes lt imm 8 gt is zero extended to a 16 bit value before operation ELECTRONES 6 111 INSTRUCTION SET S3CC11B FC11B XOR 3 XOR Large Immediate Format XOR Rn lt imm 16 gt Description This type of XOR instruction is used to perform bitwise XOR operation on two values in register Rn and lt imm 16 gt The result is stored in register Rn The T bit is updated based on the result 15 14 13 12 1l 10 9
7. 13 1 Timer 1 Bloek Diagram reperire ette p ege do S3CC11B FC11B MICROCONTROLLER Page Number xiii List of Figures continued Figure Title Page Number Number 14 1 SIO Pre scaler Register SIOPS uuu aasan nenne hene nennen nennen nnne 14 3 142 SIO Functional Block DIagram eio e e teer Ure PR Rieder 14 3 143 Serial Timing in Transmit Receive Mode Tx at falling SIOCON 4 0 14 4 14 4 Serial Timing Transmit Receive Mode Tx at rising SIOCON 4 1 14 4 15 1 Simple System Configuration 15 2 15 2 ECC Processor Block 15 5 16 1 A D Converter Control Register 10 16 2 16 2 A D Converter Data Register ADDATAH10 ADDATAL10 16 3 16 3 A D Converter Functional Block Diagram a eme 16 3 16 4 Recommended A D Converter Circuit for Highest Absolute Accuracy 16 4 17 1 CODEG Block Diagram vanene EY eed ete cra edo Op 17 4 17 2 Single Ended Input nennen nnne nnne 17 5 18 1 LCD Function Diagram i EE 18 1 182 BEIC u Pu EET 18 2 18 3 LCD Display Register 18 3 18 4 LCD Voltage Div
8. 1 es umm rrr 9 9 m omme of Ls a a rp ea o i ee sas emm rp o of me resecowmms Ni peo o r mme somma h of mme sema Ei GE ror mme 21 54 ELECTRONES S3CC11B FC11B QUICK REFERENCE EMAD Mi XiYi mgx EMSB EMLD EMUL EMAD Mi rp01s ELECTRONES CalmMAC1616 Function Flag lt P lt Xi Yi op3 op4 Mi lt Mi P P Xi Yi 3 lt 4 lt P lt Xi Yi op3 op4 VMi V N Z Mi lt P P lt Xi Yi op3 op4 VMi V N Z P lt Xi Yi op3 op4 Mi lt Mi P P lt Xi Yi op3 op4 op5 op6 Mi Mi P P lt Xi Yi op3 op4 op5 op6 Mi P P lt Xi Yi op3 op4 op5 op6 P lt Xi Yi op3 op4 op5 lt op6 Mi lt Mi P P Xi Yi Mi lt MiP P Xi Yi i Mi Mi Mi Mi Mi Mi P P Xi Yi Mi i Mi Mi Mi Mi Mi Mi Mi lt Mi P 3 lt 4 3 lt 4 Mi lt Mi P op3 op4 _ _ V V V V V Xi Yi V Xi Yi V Mi lt Mi P op3 op4 V V V VMi V Mi lt Mi P op3 lt op4 Ai lt Ai Mi op3 op4 Ai lt Ai Mi op3 op4 Ai Mi op3 op4 21 55 CalmMAC1616 S3CC11B FC11B QUICK REFERENCE Continued Ai lt Ai Mi op3 op4 VMi Ai lt Ai Mi op3 op4 V N Z C VMi Ai lt Mi op3 lt op4 V N Z V Mi
9. VREFOUT 75 SEG24 P7 1 1 ADGAIN 2 74 SEG23 P7 0 ADININ 3 73 FA SEG22 P6 7 ADINP 4 72 SEG21 P6 6 AVDD2 5 71 FA SEG20 P6 5 AVSS2 6 70 SEG19 P6 4 DAOUT 7 69 3 SEG18 P6 3 LPF 8 68 FI SEG17 P6 2 AVDD1 67 FI SEG16 P6 1 AVSS1 66 I SEG15 P6 0 P0 4 65 I SEG14 P5 7 PO 3 INT3 S3CC11B 64 1 VDD2 VDD1 S3FC11B 63 VSS2 VSS1 62 1 SEG13 P5 6 Xout 100 1414 61 SEG12 5 5 Xin 60 SEG11 P5 4 TEST 59 1 SEG10 P5 3 XTin 58 L3 SEG9 P5 2 XTout 57 1 SEG8 P5 1 nRESET 56 L3 SEG7 P5 0 P0 2 INT2 55 L3 SEG6 P4 7 INT7 PO 1 INT1 54 1 SEG5 P4 6 INT6 P0 0 INT0 53 1 SEG4 P4 5 INT5 P1 0 I O0 52 II SEG3 P4 4 INT4 P1 1 1 01 51 1 SEG2 P4 3 CCLK O f 10 lt 00 O O Q t 10 CO CO CO CO CO sb SE SE SE SF SE SE SF wo LLLI UH ET HE ET HE ET EF EFT EF EE ET EE ET CE ET LE CT EE ET ET LT ET L C 3 10 cO Ix m u LL O N X X E moo 9889892t2 2050020d 2dag825 04 FToLLSraACa rams ta AGEHONST eee NEE FFF NOanNNDADAAESSNaAaALa Soap SH 5 aa 5 O O c Figure 1 3 S3CC11B FC11B Pin Assignments 100 TQFP 1414 ELECTRONES 1 5 PRODUCT OVERVIEW Bolka P1 0 P1 7 P4 0 P4 1 P4 2 P4 3 P4 4 P4 7 P5 0 P5
10. dep d E 13 1 Block Diagram asas NE H E 13 4 viii S3CC11B FC11B MICROCONTROLLER Table of Contents continued Chapter 14 Serial Interface OVOIVIQW raneren Programming cod cave vt euet oo SIO Pre Scaler Register SIOPS Bl k Diagrama e Serial I O Timing Diagrams Chapter 15 SSFDC Solid State Floppy Disk Card Se Ecc teer ere dU den dip euer Ke E SSFDG Register Description uu LE Reste Bandet k ene bend dr ee SmartMedia Control Register hene nennen nnne nnn SmartMedia ECC Count Register SmartMedia ECC Data Register ECCDATA mme ene enne nennen SmartMedia ECC Result Data Register ECCRST Chapter 16 10 Bit Analog To Digital Converter GNI 5 A dl Lie Function Description Gonversion TIMING a A repo x Het a au AE A D Converter Control Register ADCON10 Internal Reference Voltage Levels Block Diagram Chapter 17 Codec M GAGN ae tees ag Socks EE A D Converter Control Register ADCON Chapter 18 LCD Controller Driver OLEA EN ECD Circuit Diag ran E EGCD Display Fiegisters ans eee HERE ER ERE
11. LCD Gontrol Register LCON Ru u tete eap T aq Naar eee LCD Voltage Dividing Resistors S3CC11B FC11B MICROCONTROLLER Table of Contents continued Chapter 19 Battery Level Detector OVEIVIEW 19 1 Battery Level Detector Control Register 19 2 Chapter 20 8 16 Bit Serial Interface for External Codec Ou LE 20 1 Programming Procedt te ER Pe Rees Aetat raner 20 1 CSIO Control Register GSIOCOND u uu ama upiana nnns nnn 20 2 Chapter 21 CaimMAC1616 IMTROGUCHION NEM c 21 1 Architecture Features e re aed ee re eee VE enr eet aa aty sq 21 1 Technology Features xs EE u EM 21 1 Block Diagram EID 21 2 Programming M d l u eee rope E sess goes 21 3 Multiplier and Accumulator 21 4 Arithrnetie Upit a aaae ae a eaa araa aaRS 21 7 Status Register aina 21 11 Ram Pointe rnit UE ER 21 13 Address Modification y so fecit a S e EORR ADT EA e o doe Rr ut 21 15 Data Memory Spaces and 21 19 Artthimetic Unir a err eee eR tbe ate etuer 21 21 Overflow Protection in 21 22 Ex
12. 9 1 1 op2 1 T2Z 22 0 me 22 ema ip m e op1 lt 0 0p1 7 0 0 op2 7 0 op1 lt 0 0p1 7 0 op2 7 op2 7 0 op1 lt 0p1 7 0p1 7 0 0 op2 7 0 lt 0 1 7 0 1 7 0 lop2 7 op2 7 0 0p1 lt SP 2 op2 lt SP 4 SP lt SP 4 SP lt op1 SP 2 lt op2 SP lt SP4 ELECTRONES 6 19 INSTRUCTION SET S3CC11B FC11B Table 6 2 Quick Reference Continued 2 UE NN En lt SP 2 Rn lt SP 4 Em SP 6 Rm lt SP 8 SP lt SP 8 SP lt Rn G SP 2 En SP 4 Rm 5 6 lt SP lt SP 8 BSRD e A14 lt PC 2 PC lt 2 op eoffset8 _ if EC 2 1 lt PC 2 op2 eoffset 8 20 0 lt PC 2 op2 lt EE eoffset 8 if Z1 0 PC lt PC 2 op2 R7 lt 7 1 BRA BRAD eoffset 11 PC lt 2 RN ap mm b femme cop mu 1 6 20 ELECTRONES S3CC11B FC11B INSTRUCTION SET ADC 1 Add with Carry Register Format ADC Rn Ri Description The ADC Add with Carry Register instruction is used to synthesize 32 bit addition If register pairs RO R1 and R2 hold 32 bit values RO and R2 hold the least significant word the following instructions leave the 32 bit sum in RO R1 ADD R2 ADC R1 R3 The inst
13. Dividend 23 0001 0111 Dividend 17 0001 0001 Divisor 6 0110 Divisor 6 0110 MA 0 0001 0111 MA 0 0001 0001 P 0110 0000 P 0110 0000 ESLA MA 0 0010 1110 ESLA MA 0 0010 0010 EDIVQ 110100000 EDIVQ 110100000 11100 1110 1 1100 0010 1 1004 1100 1 1000 0100 EDIVQ 001100000 EDIVQ 4 001100000 111111100 1 1140 0100 1 1444 1000 1 1100 1000 EDIVQ 001100000 EDIVQ 001100000 0 0101 1000 0 0010 1000 MA 0 1011 0001 MA 0 0101 0001 EDIVQ 110100000 EDIVQ 110100000 0 0101 0001 11111 0001 MA 010100011 4 MA 111100010 aen ERESR 00000 0000 ERESR 00000 0000 MA 0 1010 0011 MA 0 1010 0011 ESRA MA 0 0101 0001 ESRA MA 0 0101 0001 Remainder Remainder 5 5 Figure 21 4 Integer Division Example A 32 16 integer division example code is as follows ER NQ Initialize Division Step ESLA MA Arithmetic Shift Left 1 EDIVQ MA P Division Step EDIVQ MA P Division Step 16 times ERESRMA P Remainder Restoring ESRA MA Arithmetic Shift Right 1 ELECTRONES 21 9 CalmMAC1616 S3CC11B FC11B Dividend 23 128 0001 0111 Dividend 29 128 0001 1101 Divisor 6 8 0110 Divisor 6 8 0110 MA 0 0001 0111 MA 0 0001 1101 P 0110 0000 P 0110 0000 0 0001 0111 0 0001 1101 1 1010 0000 1 1010 0000 1 1011 0111 1 1011 1101 10110 1110 10111 1010 0 0110 0000 0 0110 0000 11001 1100 11101 1010 11001 1100 11011 0100 0 0110 0000 0 0110 0000 11111 1100 0 0001 0100 11
14. Data ROM OOBFFEH Program Memory 000000H 46222 Byte NOTE The total size of ROM Program ROM Data ROM is the 32K x 16bits The program ROM s address is 0000H BFFEH and the data ROM s address is COOOH FFFEH Figure 2 1 Program Memory Configuration 2 2 ELECTRONES S3CC11B FC11B ADDRESS SPACE DATA MEMORY Data memory configuration is shown in Figure 2 2 CalmMAC16 only can access the internal data memory if the memory request tries to access non existent memory area FIQ Fast Interrupt request is generated In this case if FE bit in CalmRISC16 s SR register is 1 the violation service routine is called and served CalmRISC16 can access the internal data memory But the FIQ is not used in the S3CC11B The address of the CalmRISC16 consists of 8 bits while the address of the MAC1616 consists of 16bits So if the address of the CalmRISC16 is E800H the address of the MAC1616 is 7400H Program ROM can be accessed in the view of ROM with LDC instruction that has 0000 BFFEH address Also and in the view of RAM with LDB LDW instructions that has same address Data ROM can be accessed in the view of ROM with LDC instruction that has C000 FFFEH address Also and in the view of RAM with LDB LDW instructions that has 11000 14FFFH address Of course Data ROM can be accessed by MAC1616 The address ranges are 8800H to A7FFH The memory violation access the non existent area FIQ can be also generated
15. Eoffset 11 Sao ao se mms s 9 mms e Dn 15 0 RO R7 e 2 EC0 EC1 EC2 EC3 e H 15 0 R6 R7 e Disp unsigned displacement e An 21 0 A8 A15 concatenation of En and Rn e offset even signed offset e En 5 0 E8 E15 MS 6 bit of An e disp even unsigned displacement e SP equal to A15 6 16 ELECTRONES S3CC11B FC11B INSTRUCTION SET QUICK REFERENCE Table 6 2 Quick Reference o operation Rn imm 7 op1 op1 op2 NM 20 Z1 V Ri lt op2 1 Rn imm 8 op1 op2 ZO Z1 imm 16 Ri Rn SP edisp 9 lt op2 Ai edisp 5 Ai Rj Ai disp 16 SP edisp 9 op1 op2 An edisp 5 An Rm Ai disp 16 Ai edisp 5 lt op2 Ai Rj Ai disp 16 5 Ai op1 op2 An Rm te SP disp 8 1 lt 8 0 0 2 7 0 Ai disp 4 Ai Rj Ai disp 16 A8 disp 8 0p1 lt 8 h0 0p2 7 0 SP disp 8 op1 lt op2 7 0 An disp 4 Q Ai Rj Kra 16 EU op1 op1 op2 T T2C V 16 lt op2 2071 Ri op1 op1 amp op2 T Z imm 16 op1 lt op1 op2 1 op1 op2 amp op2 T Z ms 16 LDW LDW LDW LDW LDB ELECTRONES 6 17 INSTRUCTION SET S3CC11B FC11B Table 6 2 Quick Reference Continued op1 op2 1 T N 1
16. R7 Same mechanism as the case R6 H is a register specifier denoting either R6 or R7 None When BNZD checks if H is zero by looking up the ZO for R6 or Z1 for R7 bit in SR these flags are updated as BNZD decrements the value of the register For the first iteration however the user is responsible for resetting the flag ZO or Z1 before the loop starts execution ELECTRONES 6 33 INSTRUCTION SET S3CC11B FC11B Conditional Branch Format BRtype lt eoffset 11 gt Description BR Conditional Branch instruction is used to change the program flow conditionally or unconditionally The allowed forms of the instruction include BRA always BRAD always with delay slot BRT when T bit is set BRTD when T bit is set with delay slot BRF when T bit is clear and BRFD when T bit is clear with delay slot The branch target address is calculated by 1 sign extending offset 10 to 22 bits 2 adding this to the PC which contains the address of the branch instruction plus 1 15 14 13 12 11 10 9 0 Operation if Condition PC PC 2 lt eoffset 11 gt Here the lt Type gt field determines whether this branch is BRA 01 BRF 10 or BRT 11 If D is set the branch instruction has one branch delay slot meaning that the instruction following the branch will be executed always regardless of the branch outcome If D is clear the immediately following instruction is NOT executed if the bran
17. Rn DM SP 2 10 h000 En SP SP 4 else DM SP Rn DM SP 2 10 h000 En DM SP 4 Rm DM SP 6 10 h000 Em SP SP 8 None None ELECTRONES S3CC11B FC11B INSTRUCTION SET RETD Ret from Subroutine with Delay Slot Format RETD Description The RETD Return from Subroutine with Delay Slot instruction is used to finish a subroutine and return by jumping to the address specified by the link register or A14 The difference between RETD and JMP A14 is that RETD has a delay slot which allows efficient implementation of small subroutines Operation PC A14 Exceptions None Notes None ELECTRONES 6 85 INSTRUCTION SET S3CC11B FC11B RET FIQ Return from Fast Interrupt Format RET_FIQ Description The RET FIQ Return from Fast Interrupt instruction is used to finish a FIQ handler and resume the normal program execution When this instruction is executed SSR FIQ saved SR is restored into SR and the program control transfers to SPCH FIQ SPCL FIQ Operation SR SSR_FIQ PC SPCH_FIQ SPCL_FIQ Exceptions None Notes Fast Interrupt is requested through the core signal nFIQ When the request is acknowledged SR and current PC are saved in the designated registers namely SSR_FIQ and SPCH_FIQ SPCL_FIQ assigned for FIQ processing Such bits in SR as FE IE and TE are cleared and PM is set 6 86 ELECTRONES S3CC11B FC11B INSTRUCTION SET RET
18. e GE Rn imm 16 AND Fo Hn lole of mma CMPU GT Rn imm 16 EQ Rn imm 16 CMPU GE Rn imm 16 o m an ELECTRONS 6 13 INSTRUCTION SET S3CC11B FC11B Table 6 1 CalmRISC16 Instruction Set Map Continued 15 8 7 a ORRosimm8 _ Jrjofofifrfofo i 2420002 Imm 8 Ro simm8 st of 0 1 4 LDB RO GjAB dispS sf 1 Of 1 t disp sRO t1 0 O 1 GjA amp R bs3 100111 GIAS Ri bs8 Jrjofoft BITC Gumi bss Ss tf 1 BITT sd tf Of sys mms CIRSRb3 sd bs 3 1 lofo SETSR bs 3 sel 5 ipsa _ min mrm o fifefoli mrsm mm wasara 1281 np H E E LD R0 SSR_IRQ x Reseved sid en B EC EE E ERE Reseved __ Reserved __ t 1 DE E Ur KEE EERE 6 14 ELECTRONES S3CC11B FC11B Table 6 1 CalmRISC16 Instruction Set Map Continued 15 8 7 up seeria Ro frjofoftfifift 011 LD SPCH FIQ RO 1 0 0 111 1 1011 LD SSR FIQ RO Reserved LD SPCL IRQ RO LD SPCH IRQ RO LD SSR RO Reserved Reserved LD SSR SWI RO Reserved Reserved Reserved Reserved LD An PC
19. of Words 1 ELECTRONES 21 105 CalmMAC1616 S3CC11B FC11B ERND Round Format ERND Mi Operation MAi lt MAi 000008000h This Instruction adds one of the 36 bit MAi accumulator and rounding constant and stores the result value into the same accumulator register It performs two s complement rounding Flags VMi Set if result is overflowed to guard bits Reset if not MV Set if guard bit is overflowed Unchanged if not Notes VMi denotes for VMO or VM1 according to Mi Examples ERND MAO of Words 1 21 106 ELECTRONES S3CC11B FC11B CalmMAC1616 ERPD Update Pointer w Destination Index Format ERPD rpd Operation RPi lt mod RPi D0 D1 This Instruction updates the selected pointer with the selected index value The modulo arithmetic affect the result value when ME bit of selected pointer is set It only modifies the pointer without memory access Flags _ Notes _ Examples ERPD RP0 D1 of Words 1 ELECTRONES 21 107 CalmMAC1616 S3CC11B FC11B ERPN Update Pointer w Immediate Value Format ERPN rpi lt op gt op imm 16 An Operation RPi mod RPi lt op gt This Instruction updates the selected pointer with 16 bit op value If op is one of 16 bit An register LSB 16 bit of the accumulator An is only valid The modulo arithmetic affect the result value when ME bit of selected pointer is set It only modifies the pointer without memory access Flags B Notes _
20. src lt dest gt lt src gt Ai Mj Ai MjSR Ai MjSL mgx rps Operation MAi lt MAi P P lt Xi Yi dest src This instruction subtracts the P register from the values of 36 bit Multiplier Accumulator MAi and stores the result back into the same Multiplier Accumulator MAi At the same time multiplier multiplies Xi register value and Yi register value and stores the result to the P register This instruction also stores source operand from data memory or 16 bit higher portion of the MAj register to the destination register Flags VMi Set if result is overflowed to guard bits Reset if not MV Set if guard bit is overflowed Unchanged if not When dest is Ai Z Set if the value to Ai is zero by load Reset if not V Set if overflow is generated by load Reset if not N Set if loaded value is negative Notes MjSR 1 bit right shifted MAj 31 16 MjSL 1 bit left shifted MAj 31 16 VMi denotes for VMO or VM1 according to Mi Examples EMSB MAO X1Y0 A MAOSR EMSB 0 0 X0 RP1 S1 of Words 1 21 96 ELECTRONES S3CC11B FC11B CalmMAC1616 3 3 multiply and Subtract w Two Parallel Moves Format EMSB Mi Xi rp01s Yi rp3s Operation MAi MAi P P Xi Yi Xi operand1 by rp01s Yi operand2 by rp3s This instruction subtracts the P register from the values of 36 bit Multiplier Accumulator MAi and stores the result back into the same Mult
21. Add Immediate Format Description Operation Exceptions Notes ADD Rn lt imm 16 gt The ADD Add Immediate instruction is used to add a 16 bit immediate value to a register 32 bit addition or subtraction can be achieved by executing ADC or SBC instruction in pair with this instruction ADD adds the value of register Rn and the value of lt imm 16 gt and stores the result in register Rn The T bit and the V flag are updated based on the result 15 14 13 12 1l 10 9 8 7 6 5 4 3 0 Rn Rn lt imm 16 gt T bit Carry from Rn lt imm 16 gt V flag Overflow from Rn lt imm 16 gt R6 R7 20 21 flag Rn lt imm 16 gt 0 None This is a 2 word instruction where the 16 bit immediate follows the instruction word shown above Unlike 1 word instructions therefore fetching of ADD Rn lt imm 16 gt takes 2 cycles The instruction SUB Rn lt imm 16 gt does not exist The result of SUB Rn lt imm 16 gt instruction is identical with the result of ADD Rn 2 s complement of lt imm 16 gt except when lt imm 16 gt is zero In that case SUB Rn lt imm 7 gt can be used ELECTRONES 6 25 INSTRUCTION SET S3CC11B FC11B ADD 4 Add Extended Register Format ADD An Ri Description The ADD Add Extended Register instruction is used to add a 16 bit unsigned register value to a 22 bit register This instruction
22. ELECTRONES 6 95 INSTRUCTION SET S3CC11B FC11B SR shift Right Format SR Rn Description The SR Shift Right instruction shifts the value of Rn right by one bit and stores the result back in Rn T bit is updated as a result of this operation 15 14 13 12 11 10 9 8 7 6 5 4 3 0 Operation Rn Rn gt gt 1 with Rn 15 set to 0 T bit Rn 0 before shifting Exceptions None Notes None 6 96 ELECTRONES S3CC11B FC11B INSTRUCTION SET SRA shift Right Arithmetic Format SRA Rn Description The SRA Shift Right Arithmetic instruction shifts the value of Rn right by one bit and stores the result back in Rn While doing so the original sign bit most significant bit is copied to the most significant bit of the result T bit is updated as a result of this operation Operation Rn Rn gt gt 1 with Rn 15 set to the original value T bit Rn 0 before shifting Exceptions None Notes None ELECTRONES 6 97 INSTRUCTION SET S3CC11B FC11B SRB shift Right Byte Format SRB Rn Description SRB Shift Right Byte instruction shifts the value of Rn right by 8 bit and stores the result back in Rn The high 8 bit positions are filled with O s T bit is updated as a result of this operation Operation Rn 7 0 Rn 15 8 and Rn 15 8 8 h00 T bit Rn 7 before shifting Exceptions None Notes None 6 98 ELECTRONES S3CC11B FC11
23. Examples ERPN RP3 1555h ERPN RP1 A of Words 1 2 when op is imm 16 21 108 ELECTRONES S3CC11B FC11B ERPR Format Operation Flags Notes Examples of Words Bit Reverse Pointer ERPR rpi RP3 bit reverse RPi CalmMAC1616 This Instruction generates the reversed bit pattern on LSB n bit of the selected pointer according to the MC1 15 13 bit values which specifies bit reverse order Refer to MC1 register configuration in chapter 2 The result bit pattern is written to current bank register pointer field The source pointer value is not changed at all ERPR RP2 ELECTRONES 21 109 CalmMAC1616 S3CC11B FC11B ERPS Update Pointer w Source Index Format ERPS rps Operation mod 50 51 This Instruction updates the selected pointer with the selected index value The modulo arithmetic affect the result value when ME bit of selected pointer is set It only modifies the pointer without memory access Flags _ Notes _ Examples ERPS RP0 S1 of Words 1 21 110 ELECTRONES S3CC11B FC11B ES Bit set Format ES bs Operation Specified bit in bs field lt 1 This instruction sets the specified bit in bs field to 1 Flags _ Notes _ Examples ES OP ES ME3 of Words 1 ELECTRONES CalmMAC1616 21 111 CalmMAC1616 S3CC11B FC11B ESAT saturate Format ESAT Mi Operation if VMi 1 MAi maximum magnitude This I
24. N channel open drain output Not available 5 4 P2 6 nCE0 Configuration Bits o o smmwmemu O Fe r mswdopu 3 2 P2 5 CLE Configuration Bits 1 0 P2 4 ALE Configuration Bits papas o t Pushpuloupt N channel open drain output Not available NOTE When the SmartMedia control SMCON register is enabled the access of port 2 generate the read or write strobe signal to the SmartMedia memory However other pins for SmartMedia interface should set interface condition and generate interface signal by CPU instruction This provide the custom er with the high speed memory access time small chip size and small power consumption together ELECTRONES 9 7 PORTS S3CC11B FC11B P2CONL Port 2 Control Register Low 3F0029H Bit Identifier _ 7 s 4 3 2 o 0 0 0 0 0 0 0 0 Reset Value Read Write R W R W R W R W R W R W R W R W 7 6 P2 3 R nB Configuration Bits lo Schmitt trigger input Push pull output 5 4 3 2 EN Schmitt trigger input Push pull output 1 0 NOTE When the SmartMedia control SMCON register is enabled the access of port 2 generate the read or write strobe signal to the SmartMedia memory However other pins for SmartMedia interface should set interface condition and generate interface signal by CPU instruction This provide the customer with the high speed memory access time small chip
25. Operation Exceptions Notes RL Rn The RL Rotate Left instruction rotates the value of Rn left by one bit and stores the result back in Rn T bit is updated as a result of this operation 15 14 43 12 1l 10 9 8 7 6 5 4 3 0 1 1 Rn Rn lt lt 1 Rn 0 MSB of Rn before rotation T bit MSB of Rn before rotation None None ELECTRONES 6 89 INSTRUCTION SET S3CC11B FC11B RR Rotate Right Format Description Operation Exceptions Notes 6 90 RR Rn The RR Rotate Right instruction rotates the value of Rn right by one bit and stores the result back in Rn T bit is updated as a result of this operation 15 14 43 12 1l 10 9 8 7 6 5 4 3 0 m Rn Rn gt gt 1 MSB of Rn Rn 0 before rotation T bit Rn 0 before rotation None None ELECTRONES S3CC11B FC11B INSTRUCTION SET RRC Rotate Right with Carry Format Description Operation Exceptions Notes RRC Rn The RRC Rotate Right with Carry instruction rotates the value of Rn T bit right by one bit and stores the result back in Rn T bit is updated as a result of this operation 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 Rn Rn gt gt 1 MSB of Rn T bit before rotation T bit Rn 0 before rotation None None ELECTRONES 6 91 INSTRUCTION SET S3CC11B FC11B
26. 6 22 ELECTRONES S3CC11B FC11B INSTRUCTION SET ADD 1 Add Register Format ADD Rn Ri Description The ADD Add Register instruction is used to add two 16 bit values in registers 32 bit addition can be achieved by executing ADC instruction in pair with this instruction ADD adds the value of register Rn and the value of register Ri and stores the result in register Rn The T bit and the V flag are updated based on the result 15 14 13 12 4 8 7 6 5 4 3 0 m Jojojojo m Operation Rn Rn Ri T bit Carry from Rn Ri V flag Overflow from Rn Ri R6 R7 20 71 flag Rn Ri 0 Exceptions None Notes None ELECTRONES 6 23 INSTRUCTION SET S3CC11B FC11B ADD 2 Add Small Immediate Format Description Operation Exceptions Notes 6 24 ADD Rn lt imm 7 gt This form of ADD instruction is used to add a 7 bit positive immediate value to a register ADD adds the value of register Rn and the value of lt imm 7 gt and stores the result in register Rn The T bit and the V flag are updated based on the result 15 14 13 12 1l 8 7 6 0 Jo 99 Rn Rn lt imm 7 gt T bit Carry from Rn lt imm 7 gt V flag Overflow from Rn lt imm 7 gt if Rn R6 R7 Z0 Z1 flag Rn lt imm 7 gt 0 None lt imm 7 gt is an unsigned amount ELECTRONES S3CC11B FC11B INSTRUCTION SET ADD 3
27. ELECTRONES 2 3 ADDRESS SPACE S3CC11B FC11B Address of Address of CalmRISC16 MAC1616 3FFFFEH OI N 3F0080H LCD Display Registers 3F007FH Control Registers 3F0000H u 015000H 014FFFH Data ROM 011000H 010FFFH Y Memory Data RAM 010000H OOFFFFH Area X Memory 00E800H Data CalmRISC16 Program ROM 000000H K Byte NOTES The address of the calmRISC consists of 8 bits while the address of the MAC1616 consists of 16 bits The total size of ROM Program ROM Data ROM is the 32K x 16bits The program ROM s address is 0000H BFFFH and the data ROM s address is C000H FFFEH The data of program memroy Program ROM can be loaded to a register by load instructions Figure 2 2 Data Memory Configuration 2 4 ELECTRONES S3CC11B FC11B Calm16Core Calm16Core INTRODUCTION The main features of CalmRISC16 a 16 bit embedded RISC MCU core are high performance low power consumption and efficient coprocessor interface It can operate up to 32MHz and consumes 200uA MHz 3 3V When operating with MAC 1616 a 16 bit fixed point DSP coprocessor CalmRISC16 can operate up to 32MHz Through efficient coprocessor interface CalmRISC16 provides a powerful and flexible MCU DSP solution The following gives brief summary of main features of CalmRISC16 FEATURES Architecture Instruction Set e Harvard RISC architecture e 16 bit instruction
28. Main Accumulators A B Each Ai A or B register is organized as a regular 16 bit register The Ai accumulators can serve as the source operand as well as the destination operand of all ARU instructions and serve as a source operand of exponent instruction The Ai registers can be read or written though the XB bus It can be read or written to the data memory during some MAU instructions and some ARU instructions parallel move Auxiliary Accumulators C D Each Ci C or D register is organized as a regular 16 bit register and can serve as the source operand as well as the destination operand of some ARU instructions and serve as a source operand of exponent instruction Some ARU instruction can only acces s main accumulators A B as a source or destination operand and auxiliary accumulators C D are only accessed in some special instructions The Ci registers can be read or written though the XB bus It can be read or written to the data memory during some ARU instructions parallel move ELECTRONES 21 21 CalmMAC1616 S3CC11B FC11B XB 15 0 Shifter Shifter 16 bit Adder El Generation Figure 21 12 Arithmetic Unit Block Diagram Overflow Protection in Accumulators The Ai or Ci accumulator saturation is performed during arithmetic operation that causes overflow if overflow protection bit OP in MSRO register is enabled The limited values are 7FFFh positive overflow or 8000h negative overflow During accumulator register
29. Reserved EADD Ai Mi mgx rps ESUB Ai Mi mgx rps ELD Ai Mi nis rps EADD ALM Mem esuemmimops EDAM Mers Jolfifofififm m meme o s o s s a t v NOTE d means DONT Care abl ELECTRONES 21 51 CalmMAC1616 S3CC11B FC11B Overall COP Instruction Set Continued s s 5 215T5 m ELD ALM pepe pe m e r 1 oe 1 M 9 1 m EDAMLOpdP 1 0 1 1 0 1 M 1 md ELD es reserved 0j SSE FEADD ALG ESB NOL EOP AG EMAXAICLCiOms Jo EMN ALG Eomer 9 Vo ELD rpdAn So EMAD Mi Xi rp01s YiGrp3s 1 EMSB Mi Xi rp01s Yi rp3s 1 C EMUL XY XO Ones 1 FELD Xi rp01s Viss _ reserved 1 1 EN ES EN EN EN 015 reserved EN i EN EN EN ER EN EH 5 0 9 21 52 ELECTRONES S3CC11B FC11B CalmMAC1616 Overall COP Instruction Set Map Continued w n w s s z 6 s 2431213
30. Rising edge interrupt 6 P4 6 s Interrupt State Setting Bit Falling edge interrupt 1 Rising edge interrupt 5 P4 5 s Interrupt State Setting Bit Falling edge interrupt 1 Rising edge interrupt 4 P4 4 o Interrupt State Setting Bit alling edge interrupt ising edge interrupt 3 P4 7 s Interrupt Enable Bit isable interrupt nable interrupt 2 P4 6 o Interrupt Enable Bit isable interrupt nable interrupt 41 P4 5 o Interrupt Enable Bit isable interrupt 1 nable interrupt 0 P4 4 s Interrupt Enable Bit Disable interrupt k Enable interrupt 9 16 ELECTRONES S3CC11B FC11B VO PORTS P5CONH Port 5 Control Register High 3F0034H Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 P5 7 SEG14 Configuration o Schmitt trigger input ESSEN Push pull output N channel open drain output Alternative function SEG14 output 5 4 5 6 5 13 Configuration Bits 2 Fo r mswdopu Nerem openan 3 2 P5 5 SEG12 Configuration Bits o somos SS Co i smm neram openana 1 0 P5 4 SEG11 Configuration Bits 0 o Semittriggerinput i 011 Puhpuloupt N channel open drain output Alternative function SEG11 output ELECTRONES 9 17 I O PORTS S3CC11B FC11B P5CONL Port 5 Control Register Low 3F0035H Bit
31. The address registers are used to generate 22 bit program and data addresses 3 2 ELECTRONES S3CC11B FC11B Calm16Core SPECIAL REGISTERS The special registers consist of 16 bit SR Status Register 22 bit PC Program Counter and saved registers for IRQ interrupt FIQ fast interrupt and SWI software interrupt When IRQ interrupt occurs the most significant 6 bits of the return address are saved in SPCH_IRQ the least significant 16 bits of the return address are saved in SPCL_IRQ and the status register is saved in SSR_IRQ When FIQ interrupt occurs the most significant 6 bits of the return address are saved in SPCH FIQ the least significant 16 bits of the return address are saved in SPCL_FIQ and the status register is saved in SSR_FIQ When a SWI instruction is executed the return address is saved in A14 register E14 concatenated with R14 and the status register is saved in SSR_SWI The least significant bit of PC SPCL IRQ and SPCL FIQ is read only and its value is always O The 16 bit register SR has the following format 15 8 7 0 2 e FE enable bit FIQ is enabled when FE is set e E IRQ enable bit IRQ is enabled when IE is set e TE TRQ enable bit Trace is enabled when TE is set e V overflow flag set clear accordingly when arithmetic instructions are executed e 70 zero flag of set when R6 equals zero and used as the branch conditio
32. The conditional instructions can only be executed when the T bit is set Otherwise performs no operation The T bit can be modified by instructions writing to MSRO register explicitly 21 26 ELECTRONES S3CC11B FC11B CalmMAC1616 STATUS REGISTER 2 MSR2 MSR2 register of three CalmMAC16 status registers MSR0 MSR1 MSR2 is used to select EI 2 0 port of the CalmMAC16 from various flags and status information in MSRO and register and to specify current bank of each pointer and index register The MSR2 register is used at external condition generation unit in the ARU The contents of each field definitions are described as follows 15 14 13 12 11 8 7 4 3 0 Bank Selection RPi SDi 0 Bank 0 RPi SDi Reset Value 1 Bank 1 RPi SDi EC2 Selection EC1 Selection ECO Selection 0000 2 0000 2 0000 2 0001 Z 0001 2 0001 Z 0010 0010 2 N 0010 0011 N 0011 N 0011 N 0100 C 0100 C 0100 C 0101 0101 C 0101 C 0110 2 V 01102 V 01102 V 0111 V 0111 V 0111 V 1000 1000 1000 1001 LE 1001 LE 1001 LE 1010 VMO 1010 1010 1011 VM1 1011 VM1 1011 VM1 1100 VS 1100 VS 1100 VS 1101 reverved 1101 reverved 1101 reverved 1110 MV 1110 MV 1110 MV 11112 11112 11112 Figure 21 15 MSR2 Register Configuration ELECTRONES 21 27 CalmMAC1616 S3CC11B FC11B BK3 BK2 BK1 BK0 Bit 15 Bit 12 These bits def
33. lower 6 bits of DM SP 6 Rm DM SP 8 SP SP 8 ELECTRONES S3CC11B FC11B INSTRUCTION SET PUSH 1 Load Register to Stack Format PUSH Rn Rm PUSH Rn Description PUSH instruction load one or two 16 bit data from general registers to software stack In the instruction of PUSH Rn Rm there are some restrictions Rn and Rm Rn and Rm should not be R15 If Rn is one of the 8 registers from RO to R7 Rm should also be one of them If Rn is one of the registers from R8 to R14 Rm should also be one of them For example PUSH R7 R8 is illegal If Rn is the same as Rm push operation occurs only once PUSH Rn is equivalent to PUSH Rn Operation if Rn Rm PUSH Rn DM SP Rn SP SP 2 else DM SP Rn DM SP 2 Rm SP SP 4 Exceptions None Notes None ELECTRONES 6 83 INSTRUCTION SET S3CC11B FC11B PUSH 2 Load Register to Stack Format Description Operation Exceptions Notes 6 84 PUSH An Am PUSH An The PUSH instruction load one or two 22 bit data to software stack from extended registers In the instruction of PUSH An Am there are some restrictions on An and Am Anand Am should not be A15 If Anis the same as Am push operation occurs only once PUSH An An is equivalent to PUSH An 15 14 13 12 11 10 8 7 6 5 4 3 2 0 Am PUSH An DM SP
34. op2 1 T N amp Z 1 2 1 T C 1 op2 1 T C amp Z 1 T Z Rn lt op1 0 op1 15 1 1 0 lt op1 14 0 op1 15 T op1 15 lt T op1 15 1 1 0 1 8 h00 0p1 15 8 1 7 op1 0 0p1 15 1 T op1 0 lt op1 15 op1 15 1 T op1 0 lt 0p1 7 0 8 h00 T 0p1 8 DT Rn op1 lt 1 Oxffff T Z 20 71 NG i T 21 lt opt T 1 1 0xffff T lt 1 1 1 lt 1 pe emen imm 16 JPF if T220 PC lt op1 JPT addr 22 if T221 PC lt op1 JMP PC lt 1 JSR A14 lt 214 lt 1 ADD imm 16 op1 lt op1 op2 ADD imm 16 op1 op1 op2 SUB imm 5 op1 op1 op2 Ri imm 8 lt 4 8 h00 0p2 lt 8 h00 op2 lt 8 h00 0p2 1 amp 8 h00 0p2 A8 R1 bs 3 1 0 2 lt 0 T op1 op2 1 0 2 lt 1 1 0 2 lt op1 op2 op1 op2 lt op1 op2 ss ms onoo NEIN 6 18 ELECTRONES S3CC11B FC11B INSTRUCTION SET Table 6 2 Quick Reference Continued bs 3 SR op1 0 SR op1 1 T SR op1 LD SR op1 op2 SPCL_FIQ SPCH FIQ SSR FIQ SPCL IRQ SPCH IRQ SSR IRQ SSR SWI LD SR op1 op2 SPCL_FIQ SPCH FIQ SSR FIQ SPCL IRQ SPCH IRQ SSR IRQ SSR SWI LD An PC 1 op2 4 Ai 1 op2 imm 22
35. 0 Exceptions None Notes The register used in this operation is fixed to RO Therefore the operand should be placed in RO before this instruction executes ELECTRONES 6 107 INSTRUCTION SET S3CC11B FC11B TST 3 Test Large Immediate Format TST Rn lt imm 16 gt Description This type of TST instruction is used to determine if many bits of a register are all clear or if at least one bit of a register is set TST performs a comparison by logically ANDing the value of register Rn with the value of Ri T bit is set according to the result 15 14 13 12 1l 10 9 8 7 6 5 4 3 0 Operation Temp Rn amp lt imm 16 gt T bit Rn amp lt imm 16 gt 0 Exceptions None Notes This is a 2 word instruction where the 16 bit immediate follows the instruction word shown above Unlike 1 word instructions therefore fetching of this instruction takes 2 cycles 6 108 ELECTRONES S3CC11B FC11B INSTRUCTION SET tTest SR Format Description Operation Exceptions Notes TSTSR bs 3 The TSTSR Test SR instruction is used to test a specified bit in SR as the following example shows TST FE IE TE V Z0 Z1 PM To set or clear a specified bit the SETSR or CLRSR instruction is used 15 14 13 12 1l 10 9 8 7 6 5 4 3 2 0 T bit SR lt bs 3 gt None None ELECTRONES 6 109 INSTRUCTION SET S3CC11B FC11B XOR 1 XOR Register Format XOR Rn Ri Description
36. 0 IRR5 gt IRR6 IRR7 1 IRR6 IRR7 gt IRR3 Subgroup C 0 IRR6 gt IRR7 1 IRR7 gt IRR6 Group 0 X0 Y0 Z0 Group 1 X1 X1 Z1 IRR7 mee IRR5 IRR4 IRR3 IRR2 IRR1 mo IRR15 IRR14 IRR13 IRR12 IRR11 IRR10 mme IRR8 NOTES IPRL 000005H IPRH 000004H 1 X Y Z represent priority groups A B C determined by bits 7 4 1 2 If bits 7 4 1 are 1 1 1 then X Y Z is corresponded to A B C 3 If bits 7 4 1 are 1 0 1 then X Y Z is corresponded to C B A 4 8 Figure 4 3 Interrupt Priority Register IPR ELECTRONES S3CC11B FC11B EXCEP TIONS INTERRUPT ID REGISTER Interrupt ID register IIR represents an ID of the interrupt to be serviced When any interrupt of 21 sources requests a service from core the core can selects the target interrupt source by reading IIR The pending bit is cleared by hardware when the CPU reads the IIR register value in an interrupt service routine But also the corresponding bit is cleared by S W when it is written ID 2 value to the IIR register Where the ID is a bit of IRR For example the ID of SIO INT is 8 All pending bits are cleared when 80H is written to IIR register ELECTRONES 4 9 EXCEPTIONS S3CC11B FC11B NOTES 4 10 ELECTRONES S3CC11B FC11B MEMORY MAP MEMORY MAP OVERVIEW To support the control of peripheral hardware the address for peripheral control registers are memory mapped to the are
37. 0H 0H R W OH OH OH E ELECTRONES 5 3 MEMORY MAP S3CC11B FC11B Table 5 1 Registers Continued Register Name Mnemonic Decimal Hex Reset Rw 800 aata register extension mw ECC clear i ECCCLR 3F005DH s soe am Locations 3F0060H 3F0063H are not mapped Locations 3F0065H 3F0067H are not mapped Ao AD dataregisierlow _ ADDATA Location 3F006FH is not mapped Watch timer control register WTCON 3F0070H Location 3F0071H is not mapped LCD control register LCON 3F0072H 00H R W Location 3F0075H is not mapped Locations 3F0079H 3F007FH are not mapped 5 4 ELECTRONES S3CC11B FC11B INSTRUCTION SET INSTRUCTION SET ALU INSTRUCTIONS In operations between a 16 bit general register and an immediate value the immediate value is zero extended to 16 bit The following figure shows an example of 7 bit immediate numbers 7 bits Immediate In operations between a 22 bit register and an immediate value the immediate value is zero extended to 22 bit In operations between a 22 bit register and a 16 bit register the 16 bit register is zero extended to 22 bit The overflow flag in a 16 bit arithmetic operation is saved to V flag in SR register ALU instructions are classified into 3 classes as follows e ALUop Register Immediate e ALUop Register Register e ALUop Register ELECTRONES 6 1
38. Format EDECC T An Operation C This instruction subtracts 1 from the value of one of 16 bit Accumulator An if current carry flag is cleared and stores the result back into the same Accumulator Flags C Set if carry is generated Reset if not 2 Set if result is zero Reset if not V Set if overflow is generated Reset if not N Exclusive OR of V and MSB of result Refer to Chapter 2 for more detailed explanation about this convention Notes EDECCT instruction can be executed only when the T flag is set Otherwise No operation is performed Examples EDECC A EDECCT D of Words 1 ELECTRONES 21 71 CalmMAC1616 S3CC11B FC11B EDIVQ Division Step Format EDIVQ Mi P Operation if NQ 0 Adder output lt P else Adder output lt MAi P Adder output gt 0 MAi Adder output 2 1 else MAi Adder output 2 This Instruction adds or subtracts one of the MAi accumulator from P register according to the NQ bit value and calculates one bit quotient and new partial remainder Flags NQ If Adder output gt 0 NQ 0 else NQ 1 VMi Set if result is overflowed to guard bits Reset if not MV Set if guard bit is overflowed Unchanged if not Notes VMi denotes for VMO or VM1 according to the Mi Examples EDIVQ of Words 1 21 72 ELECTRONES S3CC11B FC11B CalmMAC1616 EEXP EEXPT Exponent Value Evaluation Format EEXP T An Opera
39. INSTRUCTION SET S3CC11B FC11B ALUOP REGISTER IMMEDIATE ADD ADC SUB SBC AND OR XOR TST CMP CMPU Rn imm 16 The instructions perform an ALU operation of which source operands are a 16 bit general register Rn and a 16 bit immediate value In the instructions TST CMP CMPU only T flag is updated accordingly as the result In the instructions ADD ADC SUB SBC the value of T flag is the carry flag of the operations and the value of V flag indicates whether overflow or underflow occurs In the instructions AND OR XOR TST the value of T flag indicates whether the result is zero T 1 CMP GT GE EQ Rn imm 16 instructions are for signed comparison operations GT for greater than GE for greater than or equal to and EQ for equal to and CMPU GT GE Rn imm 16 instructions are for unsigned comparison operations NOTE imm 16is defined as a 16 bit immediate number ADD SUB An imm 16 The immediate value is zero extended to 22 bit value No flag update occurs ADD SUB Rn imm 7 The immediate value is zero extended to 16 bit value T flag is updated to the carry of the operation V flag is updated AND OR XOR TST RO imm 8 The immediate value is zero extended to 16 bit value T flag indicates whether the lower 8 bit of the logical operation result is zero CMP EQ Rn imm 8 The immediate value is zero extended to 16 bit value Rn is restricted to RO to R7 T flag is updated as the result of the instruction CMP GE
40. Ltd San 24 Nongseo Ri Giheung Eup Yongin City Gyeonggi Do Korea C P O Box 37 Suwon 449 900 TEL 82 331 209 1907 FAX 82 331 209 1889 Home Page URL Printed in the Republic of Korea Http www samsungsemi com Preface The S3CC11B FC11B Microcontroller User s Manual is designed for application designers and programmers who are using the S3CC11B FC11B microcontroller for application development It is organized in two main parts Part Programming Model Part Il Hardware Descriptions Part contains software related information to familiarize you with the microcontroller s architecture programming model instruction set and interrupt structure It has seven chapters Chapter 1 Product Overview Chapter 4 Exceptions Chapter 2 Address Spaces Chapter 5 Memory Map Chapter 3 Calm16Core Chapter 6 Instruction Set Chapter 1 Product Overview is a high level introduction to S3CC11B FC11B with general product descriptions as well as detailed information about individual pin characteristics and pin circuit types Chapter 2 Address Spaces describes program and data memory spaces Chapter 2 also describes ROM code option Chapter 3 Calm16Core describes the special registers Chapter 4 Exceptions describes the internal register file Chapter 5 Memory Map describes the S3CC11B FC11B memory map structure in detail Chapter 6 Instruction Set describes the S3CC11B FC11B instruction set structure in
41. P3CONL Assign Pins to ADC Input Conversion Result 10 bit D A ADDATAH10 ADDATAL10 Converter Figure 16 3 A D Converter Functional Block Diagram ELECTRONICS 16 3 10 BIT A D CONVERTER S3CC11B FC11B Reference Voltage Input AVREF lt VDD Analog AD0 AD3 Input Pin P S3CC11B FC11B NOTE symbol R signifies an offset resistor with a value of from 50 to 1000 Figure 16 4 Recommended A D Converter Circuit for Highest Absolute Accuracy 16 4 ELECTRONICS S3CC11B FC11B CODEC CODEC OVERVIEW The CODEC is Sigma Delta type ADC for speech and telephony applications The CODEC contains both digital IIR FIR filters and an on chip voltage reference circuit is included to allow supply operations FEATURES e 256X oversampling e On decimation filter for ADC interpolation filter for DAC ELECTRONES 17 1 CODEC S3CC11B FC11B CODEC CONTROL REGISTER CDCON User can select the CODEC input clock for dividing higher crystal by controlling CDCON A D converted data are 14 bit resolution and are input to ADDATAH High byte ADDATAL Low byte in 16 bit data format also D A converted data are 14 bit resolution and are input to DADATAH high byte DADATAL low byte in 16 bit data format Because CODEC use 256X over sampling for 8 kHz sampling when crystal is 2 048 MHz 8 kHz x 256 user must select fx as CODEC input clock And when crystal is 4 096 MHz 2 x 8 kHz x 256
42. This type of AND instruction is used to perform bitwise AND operation on two values in register Rn and lt imm 16 gt The result is stored in register Rn The T bit is updated based on the result 15 14 13 12 4 10 9 8 7 6 5 4 3 0 Rn Rn amp lt imm 16 gt T bit Rn amp lt imm 16 gt 0 if Rn R6 R7 70 71 flag Rn amp lt imm 16 gt 0 None This is a 2 word instruction where the 16 bit immediate follows the instruction word shown above Unlike 1 word instructions therefore fetching of this instruction takes 2 cycles ELECTRONES 6 31 INSTRUCTION SET S3CC11B FC11B BITop Operation Format Description Operation Exceptions Notes 6 32 BlTop A8 R1 lt bs 3 gt The BITop Bit Operation instruction is used to perform a bit operation on an 8 bit memory value The allowed operations include reset BITR set BITS complement BITC and test BITT BITop fetches the value of memory location specified by A8 R1 performs the specified operation on the specified bit and stores the result back into the same memory location 15 14 43 12 4 10 9 8 7 6 5 4 3 2 0 Temp MEM A8 R1 T bit Temp lt bs 3 gt if BlTop BITT Result BITop Temp lt bs 3 gt MEM A8 R1 Result Here BITop is BITR OP 00 BITS 01 BITC 10 BITT 11 The bit location of these operations is specified by lt bs 3 gt None The ad
43. and immediately the write operation the bit is automatically cleared to 0 The watch dog timer counter is cleared to when 1 is written to 0 and immediately the write operation the bit is automatically cleared to 0 Figure 10 1 Basic Timer amp Watchdog Timer Block Diagram 10 4 ELECTRONES S3CC11B FC11B WATCH TIMER 1 1 WATCH TIMER OVERVIEW Watch timer functions include read time and watch time measurements After the watch timer starts and time elapses the watch timer interrupt is automatically set to 1 and interrupt requests commence in 3 91ms 0 25s 0 5s or 1 second intervals The watch timer can generate a steady 0 5 kHz 1 kHz 2 kHz or 4 kHz signal to the BUZZER output By setting WTCON 3 2 to 11b the real time clock will function in high speed mode generating an interrupt every 3 91 ms High speed mode is useful for timing events for program debugging sequences Real Time and Watch Time Measurement Using a Main Oscillator or Sub Oscillator Clock Source Buzzer Output Frequency Generator Timing Tests in High Speed Mode ELECTRONES 11 1 WATCH TIMER S3CC11B FC11B WTCON watch Timer Control Register 3F0070H Bit Identifier Reset Value Read Write 3 2 11 2 __ 7 5 3 2 9 _ 0 0 0 0 0 0 0 _ R W R W R W R W R W R W R W Bit 7 Watch Timer Clock Source Selection Bit When WTCON 1 0 Only 128 64 KIC
44. arithmetic 8 bit Left Shift Accumulator Format ESLA8 T Operation An lt An lt lt 8 This instruction shifts the value of one of 16 bit Accumulator An to 8 bit left and stores the result back into the same accumulator Flags C Set if last shifted out bit is 1 Reset if not Z Set if result is zero Reset if not V Set if overflow is generated Reset if not N Exclusive OR of V and MSB of result Refer to Chapter 2 for more detailed explanation about this convention Notes instruction can be executed only when the T flag is set Otherwise No operation is performed Examples ESLA8 C ESLA8T B of Words 1 ELECTRONES 21 121 CalmMAC1616 S3CC11B FC11B ESLC ESLCT arithmetic 1 bit Left Shift Accumulator w Carry Format ESLC T An Operation An lt An 1 An 0 lt C This instruction shifts the value of one of 16 bit Accumulator An to 1 bit left with carry i e the carry bit is shifted into LSB of An register and stores the result back into the same accumulator Flags C Set if shifted out bit is 1 Reset if not Z Set if result is zero Reset if not V Set if overflow is generated Reset if not N Exclusive OR of V and MSB of result Refer to Chapter 2 for more detailed explanation about this convention Notes ESLCT instruction can be executed only when the T flag is set Otherwise No operation is performed Example s ESLC A ESLCT C of Words 1 21
45. rp01s Yi lt operand2 by rp3s This instruction loads the P register value to one of 36 bit Multiplier Accumulator MAi At the same time multiplier multiplies Xi register value and Yi register value and stores the result to the P register This instruction also stores two source operands from data memory one from X memory space and one from Y memory space to the 16 bit Xi register and Yi register respectively Flags VMi Set if result is overflowed to guard bits Reset if not MV Set if guard bit is overflowed Unchanged if not Notes VMi denotes for VMO or VM1 according to Mi Examples X1YO X0 RP1 S1 Y0O RP3 S0 of Words 1 21 94 ELECTRONES S3CC11B FC11B CalmMAC1616 EMSB DS Multiply and Subtract Format EMSB Mi XiYi Operation lt P P lt Xi Yi This instruction subtracts the P register from the values of 36 bit Multiplier Accumulator MAi and stores the result back into the same Multiplier Accumulator MAi At the same time multiplier multiplies Xi register value and Yi register value and stores the result to the P register Flags VMi Set if result is overflowed to guard bits Reset if not MV Set if guard bit is overflowed Unchanged if not Notes VMi denotes for VMO or VM1 according to Mi Examples EMSB MAO X1 YO of Words 1 ELECTRONES 21 95 CalmMAC1616 S3CC11B FC11B EMSB 2 Multiply and Subtract w One Parallel Move Format EMSB Mi XiYi dest
46. 1011 The algorithm for determining the exponent result for a 16 bit number is as follows Let N be the number of the sign bits i e the number of MSBs equal to bit 15 found in the evaluated number The exponent result is N 1 This means that the exponent is evaluated with respect to bit 16 Therefore the exponent result is always greater than or equal to zero Refer to following table as examples A non zero result represents an un normalized number When evaluating the exponent value of one of the accumulator register the result is the amount of left shifts that should be executed in order to normalize the source operand An exponent result equal to zero represents a normalized number Normalization Full normalization can be achieved in 2 cycles using EEXP instruction followed by ESFT instruction The EEXP instruction evaluates the exponent value of one of the Ai register The second instruction ESFT is shifting the evaluated number according to the exponent result stored at SA register Normalization EEXPA ESFT A SA The block normalization is also possible using the exponent unit and EMIN instruction The EMIN instruction can select the minimum exponent value from all evaluated exponent result Double Precision Supports The CalmMAC16 DSP coprocessor has an instruction which can evaluate exponent values of double precision 32 bit data operand Double precision exponent evaluation can be achieved in 2 cycl
47. 13 1 Timer 1 Block Diagram 13 4 ELECTRONES S3CC11B FC11B SERIAL INTERFACE SERIAL I O INTERFACE OVERVIEW The SIO module can transmit or receive 8 bit serial data at a frequency determined by its corresponding control register settings To ensure flexible data transmission rates you can select an internal or external clock source PROGRAMMING PROCEDURE To program the SIO modules follow these basic steps 1 Configure the I O pins at port SO nSCK SI by loading the appropriate value to the POCONH register if necessary 2 Load an 8 bit value to the SIOCON register to properly configure the serial module In this operation SIOCON 2 must be set to 1 to enable the data shifter 3 When you transmit data to the serial buffer write data to SIODATA and set SIOCON 3 to 1 the shift operation starts 4 When the shift operation transmit receive is completed the SIO pending bit is set to 1 and a SIO interrupt request is generated ELECTRONK S 14 1 SERIAL I O INTERFACE 3CC11B FC11B SIOCON serial VO Control Register 3F006EH Bit Identifier _ 7 6 s 4 3 2 9 0 0 0 0 0 0 _ Reset Value Read Write R W R W R W R W R W R W 7 Serial I O Shift Clock Selection Bit nternal clock 1 External clock SCk 6 Data Direction Control Bit MSB first mode LSB first mode 5 Serial Mode Selection 0 Receive only mode 1 Transmit receive mode 4 Tx Rx Edge Selection Bi
48. 16 bit immediate follows the instruction word shown above Unlike 1 word instructions therefore fetching of CMPmode lt imm 16 gt takes 2 cycles ELECTRONES 6 41 INSTRUCTION SET S3CC11B FC11B CMP 3 Compare Short Immediate Format Description Operation Exceptions Notes 6 42 CMP GE Dn lt imm 6 gt The CMP Compare Immediate instruction is used to perform signed comparison of the register Dn and an unsigned immediate value lt imm 6 gt Dn is one of the registers from RO to R7 CMP subtracts the value of lt imm 6 gt from the value of Dn and performs signed comparison based on the result The contents of Dn is not changed however after this operation The T bit is updated for later reference 15 14 13 12 1l 10 9 5 4 3 2 1 0 8 7 6 m T bit Negative of Rn lt imm 6 gt None None ELECTRONES S3CC11B FC11B INSTRUCTION SET CMPEQ 1 Compare Equal Extended Register Format Description Operation Exceptions Notes CMP EQ An Ai The CMP EQ Compare Equal Extended Register instruction is used to compare two values in registers An and Ai This instruction is a restricted form of more general CMPmode instructions for a 22 bit equality comparison between register values 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 T bit Ai An or Ai refers to registers from A8 to A15 with their 6 bit ex
49. 21 6 Integer Division Example 21 9 Fractional Division 21 10 Register Configuration 21 11 RAM Pointer Unit Block 21 14 Pointer Register and Index Register 21 15 Modulo Control Register Configuration een 21 17 CalmMAC16 Data Memory Space eene eene nnne 21 19 CalmMAC16 Data Memory Allocation 21 20 Arithmetic Unit Block m Henn rennen nnn 21 22 Accumulator Register 21 23 MSR0 Register Configuration 21 25 MSR2 Register Configuration 21 27 Barrel Shifter and Exponent Unit Block Diagram a 21 29 Various Barrel Shifter Instruction Operation ee 21 31 Indirect Addressing Example I Single Read 21 34 Indirect Addressing Example II Dual Read 21 35 Indirect Addressing Example Write Operation 21 36 Short Direct Addressing 21 36 Long Direct Addressing Example
50. 3F0078H Reset Value _ _ _ _ _ 0 0 Read Write _ R W RAN 7 2 Bits 7 2 41 Y Data ROM Control Bit Disable Y Data ROM Enable Y Data ROM 0 Flash Memory Accessing Speed Selection Bit When fxx is more than 10 MHz When fxx is under 10 MHz 1 ELECTRONES 22 1 PROGRAM MEMORY ACCES S SPEED S3CC11B FC11B NOTES 22 2 ELECTRONES S3CC11B FC11B ELECTRICAL DATA ELECTRICAL DATA OVERVIEW Table 23 1 Absolute Maximum Ratings TA 25 C v v Vpp VI Output voltage Vo TA Operating 25 to 85 temperature Storage TsrG 65 to 150 temperature Table 23 2 D C Electrical Characteristics Output current One pin active 18 mA high All I O pins active 60 TA 25 C to 85 C Vpp 2 0 V to 3 6 V Operating Voltage Vpp fx 32MHz fx 4MHz Input high voltage Input low voltage Ports 0 9 nRESET ELECTRONK S 23 1 ELECTRICAL DATA S3CC11B FC11B Table 23 2 D C Electrical Characteristics Continued TA 25 C to 85 C Vpp 2 0 to 3 6 V Output high voltage 3 0 V to 3 6 V lH 1 mA Ports 0 9 Output low voltage VoL Vpp 3 0 V to 3 6 V lo 15 mA Pons 0 9 Input high leakage current ENT All om pins except li jp xr XTIN Input low leakage liL 4 MEN OV current EM F All input pins except 12 2 Vn 0V Xn XTN Output high leakage oH Vout Vpp current All Output pins Outp
51. 5 2 P9 7 COMO Configuration Bits Schmitt trigger input Pull up resistor enable Push pull output Alternative function COM4 COM7 signal output ELECTRONES 9 23 PORTS S3CC11B FC11B NOTES 9 24 ELECTRONES S3CC11B FC11B BASIC TIMER BASIC TIMER OVERVIEW The basic timer s primary function is to measure a predefined time interval The standard time interval is equal to 256 basic clock pulses and the period of a clock pulse can be selected by basic timer control register The 8bit counter register BTCNT is increased each time the clock signal which can be selected by the clock signal selection field in basic timer control register is detected BTCNT will increase until an overflow occurs An overflow internally sets an interrupt pending flag to signal that the predefined time has elapsed An interrupt request BTINT is then generated BTCNT is cleared to zero and the counting continues from 00h Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval after a reset or when STOP mode is released by an external interrupt In STOP mode whenever a reset or an external interrupt occurs the oscillator starts and releases the CPU from STOP mode to normal mode The BTCNT value then starts increasing at the rate of bsc 2048 for reset or at the rate of the preset clock source for an external interrupt When BTONT is increased to 80h
52. 67 Ea SEG16 P6 1 AVSS1 661 SEG15 P6 0 0 4 65E3 SEG14 P5 7 PO 3 INT3 S3FC11B VDD1 GQ N VSS1 62 I SEG13 P5 6 Xout 100 TQFP 1414 619 SEG12 5 5 Xin 60 I SEG11 P5 4 TEST 59 1 SEG10 P5 3 XTin 58 J SEG9 P5 2 XTout 57 F3 SEG8 P5 1 nRESET nRESET 56 L3 SEG7 P5 0 PO 2 INT2 55 SEG6 P4 7 INT7 PO 1 INT1 54 L3 SEG5 P4 6 INT6 PO0 0 INTO 53 0 SEG4 P4 5 INT5 P1 0 1 00 529 SEG3 P4 4 INT4 P1 1 I O1 51 1 SEG2 P4 3 CCLK O2 Cj 26 9 27 O4 9 28 O5 G 29 O6 C 30 O7 C331 P4 0 CDR I 48 P3 2 AD2 42 SEGO P4 1 CDX 49 SEG1 P4 2 CFS 50 P2 1 nRE 33 P2 2 WP 34 P2 3 R nB 35 P2 4 ALE Cj 36 P2 5 CLE 37 P2 6 nCEO 38 P3 0 ADO 9 40 P3 1 AD1 41 P3 3 AD3 TOCLK 43 P1 4 P1 5 P1 6 P1 7 P1 2 P1 3 P2 7 nCE1 39 P3 4 TOPWM H 44 P3 5 BUZ T1CLK 45 P3 6 TAOUT 46 P3 7 TBOUT 47 Figure 25 2 S3FC11B Pin Assignments 100 TQFP 1414 ELECTRONES 25 3 S3FC11B FLASH MCU S3CC11B FC11B Table 25 1 Descriptions of Pins Used to Read Write the FLASH ROM SDAT 0 4 100 QFP 13 100 TQFP 11 SCLK P0 3 100 QFP 14 100 TQFP 12 During Programming Serial data pin Output port when reading and input port when writing Can be assigned as a Input push pull output port Serial clock pin Input only pin 100 TQFP 17 RESET 100 QFP 22 nRESET 100 TQFP 20 Vpp1 Vssi 100 QFP 15 16 Masi 100 TQFP 13 14 enters i
53. Ai lt Ai Mi op3 lt op4 V N Z G Ai lt Ai Mi op3 lt op4 V N Z C Ai lt Mi op3 lt op4 opcode operand VMi or VM1 according to Mi hen VMi is written MV is written 21 56 ELECTRONES S3CC11B FC11B CalmMAC1616 Quick Reference Continued rp3s lt 2 op3 lt op4 An lt op2 de adr 5 op1 An rpdi adr 5 rpd E lt 2 E po mi morar JU s EN EE Mi Mi Mi lt Mi op2 G G Gm Lena sem EA Qrps Ai max Ai Ci op3 op4 RP3 lt V N Z C address Ai lt min Ai Ci op3 lt op4 RP3 lt V N Z C address ELECTRONES 21 57 CalmMAC1616 S3CC11B FC11B Quick Reference Continued oe om om o ops ED em D 1 e _ _ sa ms se EMAX EA Ai lt max Ai op2 RP3 lt address V N Z C EMN Aiemin Aiop2 RP3 lt address n MUN UE I _______ opi op op1 lt op2 ENOP No Operation NOTE VMi is affected wien op1 is Quick Reference Continued SG SR lt 0p1 lt lt gt gt op2 logical VS N Z C SG SR lt 0p1 lt lt gt gt op2 arithmetic VS N Z C SG lt SG 0p1 lt lt gt gt 0p2 VS N Z C SR op1 0p2 SG lt SG 0p1 lt lt gt gt 0p2 VS N Z C 90 SG SG amp mask pattern by imm VS N Z SD1 ns op2 SD2 ns op2 SD3 ns op2 1 lt DE E
54. B lt e 2 1 8 ELECTRONES S3CC11B FC11B PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS VDD P CHANNEL PULL UP IN RESISTOR N CHANNEL SCHMITT TRIGGER Figure 1 4 Pin Circuit Type 1 Figure 1 5 Pin Circuit Type 2 nRESET P Channel Out Output lt N Channel Disable Figure 1 6 Pin Circuit Type 3 ELECTRONES 1 9 PRODUCT OVERVIEW S3CC11B FC11B VDD Pull up Resistor D Resistor Enable Vpp Open Drain Data Output Disable Figure 1 7 Pin Circuit Type 4 P0 4 P0 7 P1 P2 P3 4 P3 7 P4 0 Pull up Resistor di Resistor Open Drain Enable Data Output Disable External Interrupt Input Figure 1 8 Pin Circuit Type 5 P0 0 P0 3 1 10 ELECTRONES S3CC11B FC11B PRODUCT OVERVIEW Pull up Enable Open Drain Enable Out Data Output Disable Digital In Analog In Figure 1 9 Pin Circuit Type 6 P3 0 P3 3 Pull up Resistor Pul up Enable o gt Select Port Data Alternative Signal Open Drain Output Disable Alternative Input Normal Input Figure 1 10 Pin Circuit Type 7 ELECTRONES 1 11 PRODUCT OVERVIEW Resistor Enable D Data Output Type 3 Disable 1 COM SEG Circuit sem Disable 2 Figure 1 11 Pin Circuit Type 7 P6 P7 P8 P9 Pull up Resistor Resistor Open Drain Enable Data o I O Output Disable SEG Output Disable Figure 1 12 Pin Circuit Type 9 P4 1 P4 3
55. Buzzer Signal Selection Bits 0 0 5 kHz 1 1kHz Watch Timer Speed Selection Bits 0 1 Set watch timer interrupt 0 55 Watch Timer Clock Selection Bit 0 Select clock divided by 29 or 27 fxin 64 or fxin 128 Select sub clock fxt Watch Timer Enable Bit 0 Disable watch timer Clear frequency dividing circuits Enable watch timer ELECTRONES S3CC11B FC11B WATCH TIMER WATCH TIMER BLOCK DIAGRAM WTCON 7 WTCON 6 WTCON 5 WTCON 4 WTCON 3 WTCON 2 WTCON 1 WTCON 0 ELECTRONES BUZZER Output fw 64 0 5 kHz fw 32 1 kHz fw 16 2 kHz fw 8 4 kHz Selector Watch Timer INT Enable Disable Circuit Clock Frequency Dividing Selector Tr 32 768 kHz Circuit 2048 Hz WTCON 6 fxin Main clock where fxin 4 19 MHz fxt Sub clock 32 768 kHz fw Watch timer frequency fxin 128 Figure 11 1 Watch Timer Block Diagram WATCH TIMER S3CC11B FC11B NOTES 11 4 ELECTRONES S3CC11B FC11B 8 BIT TIMER 0 8 BIT TIMER 0 OVERVIEW The 8 bit timer 0 is an 8 bit general purpose timer counter Timer 0 has three operating modes one of which you select using the appropriate TOCON setting Interval timer mode Toggle output at TO pin Capture input mode with a rising or falling edge trigger at the TOCAP pin PWM mode TOPWM ELECTRONK S 12 1 8 BIT TIMER 0 S3CC11B FC11B FUNCTION DESCRIPTION Timer 0 Interrupts The
56. C1 1 x 1055 82 C1 50 pF Figure 17 2 Single Ended Input Application ELECTRONES 17 5 CODEC S3CC11B FC11B NOTES 17 6 ELECTRONES S3CC11B FC11B LCD CONTROLLER DRIVER LCD CONTROLLER DRIVER OVERVIEW The S3CC11B FC11B microcontroller can directly drive an up to 288 dot 36 segments x 8 commons LCD panel Its LCD block has the following components LCD contoller driver Display RAM for storing display data 36segment output pins SEGO SEG35 8 common output pins COMO COM7 nternal resistor circuit for LCD bias pin for controlling the driver and bias voltage The LCD control register LCON is used to turn the LCD display on and off switch the current to the dividing resistors for the LCD display and frame frequency Data written to the LCD display RAM can be automatically transferred to the segment signal pins without any program control When a subsystem clock is selected as the LCD clock source the LCD display is enabled even in the main clock stop or idle mode VLC1 LCD Controller COMO COM7 Driver 2 UJ E 00 c o o SEGO SEG35 Figure 18 1 LCD Function Diagram ELECTRONS 18 1 LCD CONTROLLER DRIVER LCD CIRCUIT DIAGRAM 18 2 Data Bus Displa E EE Selector Timing Controller COM Control LCD Voltage Control Figure 18 2 LCD Circuit Diagram S3CC11B FC11B SEG35 P8 4 SEGO P4 1 COM7 P9 0 COMS P9 1 CO
57. Contrast Control Application With Contrast Control SSFC11B S3FC11B LCON 7 6 on LCON 7 6 off NOTES 1 The Vic3 VLc4 is short circuit when 1 4 bias is selected by LCON 3 2 2 The Vic2 VLC3 and VLC4A VLCs is short circuit respectively when 1 3 bias is selected LCON 3 2 Figure 18 4 LCD Voltage Dividing Registers Connection 18 6 ELEGTRONK 5 S3CC11B FC11B LCD CONTROLLER DRIVER Vict Vic2 Vic3 VLca VLos Vss Vict Vic2 VLC3 c4 VLC9 Vss Vict Vic2 Vi c3 Vi C4 VLCS Vss Vict Vic2 Vic3 VLCA4 VLO5 Vss Vict Vic2 Vic3 VLca VLos Vss Vie1 1 3V LC1 SEGO COMO OV Uc 18 Figure 18 5 LCD Signal Waveforms 1 3 Duty 1 3 Bias ELECTRONES 18 7 LCD CONTROLLER DRIVER S3CC11B FC11B SEG SEGO Vict Vi c2 Vic3 Vica Vics Vss Vict Vic2 Vic3 Vi c4 VL c9 Vss ca Vi Vi Vss Vict Vic2 Vic3 Vica Vics Vict 2 Vss Vict VLc2 Vic3 VLCA VLCS Vss Vici 1 8 V SEGO COM 0 OV UO M8 Vici Figure 18 6 LCD Signal Waveforms 1 4 Duty 1 3 Bias 18 8 ELEGTRONK 5 S3CC11B FC11B LCD CONTROLLER DRIVER lol 1121 al 4 sl el 7l ol 5121 al 41 el 7l VLC1 Vss VLC2 VLC3 VLC4 VLc5 Vss Vict VLC2 VLc3 VLCA VLC5 Vss VLC1 VLc2 VLC3 VLC4 VLC5 Vss VLC1 VLc2 VLC3 VLC4 VLC5 Vss VLC2 VLC3 VLC4 VLC5
58. Enable counting operation 8 BIT TIMER 0 S3CC11B FC11B NOTES 12 6 ELECTRONES S3CC11B FC11B 16 BIT TIMER 1 8 BIT TIMER A amp B 16 BIT TIMER 1 8 BIT TIMER A amp B OVERVIEW The 16 bit timer 1 is used in one 16 bit timer or two 8 bit timers When Bit 2 of TBCON is 1 it operates as one 16 bit timer When it is 0 it operates as two 8 bit timers When it operates as one 16 bit timer the TBCNT s clock source can be selected by setting TBCON 3 If TBCON 3 is 0 the timer A s overflow would be TBCNT s clock source If it is 1 the timer A s interval out would be TBCNT s clock source The timer clock source can be selected by the S W INTERVAL TIMER FUNCTION The timer A amp B module can generate an interrupt the Timer A and or Timer B match interrupt TAINT TBINT In interval timer mode a match signal is generated when the counter value is identical to the value written to the reference data register TADATA TBDATA The match signal generates Timer A and or Timer B match interrupt and clears the counter TB can be toggled whenever the timer B match interrupt occurs if I O port setting is appropriate ELECTRONES 13 1 16 BIT TIMER 1 8 BIT TIMER A amp B S3CC11B FC11B TACON Timer 1 A Control Register 3F0048H Reset Value 0 0 0 0 0 Read Write _ R W R W R W _ _ R W R W 7 Bit 7 6 4 Timer 1 A Clock Selection Bits fxx 512 FN oie stem ao O o eera
59. M 0 LDW Rn Ai lt disp 16 gt Rn disp 16 M 1 LDW An lt disp 16 gt Ri DMI An lt disp 16 gt Ri None This is a 2 word instruction where the 16 bit immediate follows the instruction word shown above Unlike 1 word instructions therefore fetching of this instruction takes 2 cycles For memory transfer per word the byte address need to be aligned to be even Thus if Ai lt disp 16 gt is an odd number it will be made even by clearing the least significant bit ELECTRONES 6 71 INSTRUCTION SET S3CC11B FC11B LDW 4 Load Word Register Indexed Format Description Operation Exceptions Notes 6 72 LDW Rn Ai Rj LDW G An Rm Ri The LDW Load Word Register Indexed instruction is used to load a word from or to data memory at the location specified by the register Ai or An and the second register Rj or Rm which is an unsigned value 15 14 43 12 1l 8 7 6 4 3 0 o o u M 0 LDW Rn Ai Rj Rn DM Ai Rj 1 LDW Q An Rm Ri DM An Rm Ri None For memory transfer per word the byte address needs to be aligned to be even Thus if Ai Rj or An Rm is an odd number it will be made even by clearing the least significant bit ELECTRONES S3CC11B FC11B INSTRUCTION SET LDW 5 Load Word Register Small Disp Format Description Operation Exceptions Notes LDW A
60. Request RESET CLEAR H W S W Timer 0 match capture H W S W H W S W H W S W H W S W H W S W H W S W Timer 0 overflow Timer 1 A match Timer B match Basic Timer overflow CODEC INT SIO INT for external Codec H W S W Watch timer INT H W S W SIO INT O S W Ext INTO HW S W Ext INT1 HW S W Ext INT2 HW S W Ext HW S W Ext INT4 C Oh HW S W Ext INT5 Ext INT6 Ext INT7 Trace Interrupt Request 000002H 000006H Software Interrupt 000008H 0000FEH NOTES 1 The IRQ vector has several interrupt sources The priority of the sources is controlled by setting the IPRH IPRL registers 2 External interrupts are triggered by a rising or falling edge depending on the corresponding control register setting Ext INT4 Ext INT7 have no interrupt pending bit but have an enable bit Figure 4 1 Interrupt Sources IRQ ELECTRONES 4 3 EXCEPTIONS S3CC11B FC11B INTERRUPT STRUCTURE Clear Timer 0 match capture Timer 0 overflow Timer 1 A match Timer B match Basic timer overflow CODEC INT SIO INT for external Codec Watch Timer INT SIO INT Ext INTO Ext INT1 Ext INT2 Ext INT3 0 Ext INT4 li III PAINT 1 Ext INT5 P4INT 2 Ext INT6 PAINT 3 Ext INT7 Stop amp Idle Release NOTE The pending bit is cleared by hardware when the CPU reads the IIR register value in an interrupt
61. Reset if not N Exclusive OR of V and MSB of result Refer to Chapter 2 for more detailed explanation about this convention Notes EINCCT instruction can be executed only when the T flag is set Otherwise No operation is performed Examples EINCC A EINCCT C of Words 1 ELECTRONES 21 77 CalmMAC1616 S3CC11B FC11B ELD 1 _ Load Accumulator Format 1 ELD An lt mem gt mem rps rpdi adr 5 adr 16 2 ELD An op op Am simm 5 simm 16 mgx mg Operation An lt lt mem gt or lt op gt This instruction load lt mem gt or lt op gt value to the one of 16 bit Accumulator An If lt op gt is immediate value it is first right adjusted and sign extended to 16 bit value If op is 16 bit register it is zero extended Flags Z Set if result is zero Reset if not V Set if overflow is generated Reset if not Set if loaded value is negative Notes Flags are not affected when a source operand is from memory Examples ELD A RP0 S0 ELD B RPD1 5h ELD C 0486h ELDD A ELD A RPO of Words 1 2 when lt op gt is adr 16 or simm 16 21 78 ELECTRONES S3CC11B FC11B CalmMAC1616 ELD 2 Load Accumulator w One Parallel Move Format ELD Ai Mi lt dest gt lt src gt lt dest gt lt src gt mgx rps Mi rps rpd mga rpd P Operation Ai lt MAi dest src This instruction load higher 16 bit part of Multiplier Accumulator MAi to the
62. SET BSRD Branch Subroutine with Delay Slot Format BSRD lt eoffset 13 gt Description The BSRD Branch Subroutine with Delay slot instruction is used to change the program flow to a subroutine by assigning the address of the subroutine to PC after saving the return address PC 4 in the link register or A14 The address of the subroutine is calculated by 1 sign extending lt eoffset 13 gt to 22 bits 2 adding this to the PC which contains the address of the branch instruction plus 1 After executing the subroutine the program flow can return back to the instruction that follows the BSRD instruction by setting PC with the value stored in A14 see JMP Ai instruction in page 7 52 and RET instruction in page 7 85 This instruction has a delay slot the instruction that immediately follows BSRD will be always executed 15 14 43 12 4 0 lt 2 Operation 14 4 PC PC 2 lt eoffset 13 gt Exceptions None Notes None ELECTRONES 6 37 INSTRUCTION SET S3CC11B FC11B CLD Coprocessor Load Format Description Operation Exceptions Notes 6 38 CLD Dn lt imm 5 gt CLD lt imm 5 gt Di The CLD Coprocessor Load instruction is used to transfer data from and to coprocessor by generating the core signals nCLDID and CLDWR The content of DA 4 0 is lt imm 5 gt the address of coprocessor register to be read or written When data item is read from coprocesso
63. SR result Notes Examples ESFTA A B ESFTA SI SA of Words 1 21 116 ELECTRONES S3CC11B FC11B CalmMAC1616 ESFTD Double Shift by Barrel Shifter Format ESFTD asr asa Operation SG SG asr asa This instruction shifts the value of 16 bit asr values by the amount of 7 bit asa If the value of asa is positive left shift operation is performed and if the value of asa is negative right shift operation is performed The 16 bit shifted result is ORed with previous SG register value and then stored into SG register Flags C Set if last shifted out bit is 1 Reset if not Unchanged when shift amount is 0 Z Set if SG result is zero Reset if not VS Reset N MSB of SG result Notes _ Examples ESFTD A B ESFTD SI SA of Words 1 ELECTRONES 21 117 CalmMAC1616 S3CC11B FC11B ESFTL Format Operation Flags C VS Notes Examples of Words 21 118 Linked Shift by Barrel Shifter ESFTL asr asa SR asr lt lt asa SG lt SG asr asa This instruction shifts the value of 16 bit asr values by the amount of 7 bit asa If the value of asa is positive left shift operation is performed and if the value of asa is negative right shift operation is performed The 16 bit shifted result is stored into SR register and the 16 bit shifted out result is ORed with previous SG value and stored into SG register The other bits of SR register are filled with zeros Set if
64. Set if result is zero by addition Reset if not Set if overflow is generated by addition Reset if not Exclusive OR of V and MSB of result by addition Refer to Chapter 2 for mare detailed explanation about this convention Set if result is overflowed to guard bits Reset if not Notes VMi denotes for VMO or VM1 according to Mi if dest is Mi Examples of Words 21 128 ESUB A MAO X0 RP0 S1 ESUB B MA1 RP1 S0 ESUB MAO RP3 D1 ESUB A C C RP2 S1 1 ELECTRONES S3CC11B FC11B CalmMAC1616 ESUB UM Subtract Multiplier Accumulator Format ESUB Mi op op P PSH Operation MAi MAi op This instruction subtracts op value from the values of 36 bit Multiplier Accumulator MAi and stores the result back into the same Multiplier Accumulator MAi The PSH means 16 bit arithmetic right shifted P register value Flags VMi Set if result is overflowed to guard bits Reset if not MV Set if guard bit is overflowed Unchanged if not Notes VMi denotes for VMO or VM1 according to Mi Examples ESUB MAO P ESUB MA1 PSH of Words 1 ELECTRONES 21 129 CalmMAC1616 S3CC11B FC11B ESUB P Subtract Multiplier Accumulator w One Parallel Move Format ESUB Mi P dest src dest src mgx rps An rps rpd mga rpd P Operation MAi lt MAi P dest src This instruction subtracts the value of the Product register P from the va
65. The first letter of the two letter qualifiers corresponds to Rn and the second corresponds to Ri For example in the instruction MUL SU RO R1 the 8 bit signed value in the lower byte of RO and the 8 bit unsigned value in the lower byte of R1 are multiplied and the 16 bit result is saved in RO RR RL RRC SR SRA SLB SRB DT INCC DECC COM COM2 COMC EXT Rn For DT Rn Decrement and Test and COM Rn Complement instructions T flag indicates whether the result is zero In the instruction of EXT Rn Sign Extend no flag update occurs In all other instructions carry out of the operation is transferred to T flag In the instruction of DT INCC and DECC V flag indicates whether overflow or underflow occurs ELECTRONK S 6 3 INSTRUCTION SET S3CC11B FC11B LOAD INSTRUCTIONS Load instructions move data from register memory immediate to register memory When the destination is a memory location only general registers and extension registers can be the source We can classify Load instructions into the following 4 classes LD Register Register e LD Register Immediate LD Data Memory Register LD Register Data Memory e LD Register Program Memory LD REGISTER REGISTER LD Rn Ri LD An Ai The instructions move 16 bit or 22 bit data from the source register to the destination register When the destination register is R6 R7 the zero flag Z0 Z1 is updated In all other cases no flag update occurs LD
66. Timer 0 module can generate two interrupts the Timer 0 overflow interrupt TOOVF and the Timer 0 match capture interrupt TOINT Interval Timer Function The Timer 0 module can generate an interrupt the Timer 0 match interrupt TOINT In interval timer mode a match signal is generated and TO is toggled when the counter value is identical to the value written to the TO reference data register TODATA The match signal generates a Timer 0 match interrupt and clears the counter If for example you write the value 10H to TODATA and OAH to TOCON the counter will increment until it reaches 10H At this point the TO interrupt request is generated and the counter value is reset and counting resumes Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the TOPWM pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the Timer 0 data register In PWM mode however the match signal does not clear the counter but can generate a match interrupt The counter runs continuously overflowing at FFH and then repeats the incrementing from OOH Whenever an overflow occurs an overflow OVF interrupt can be generated Although you can use the match or the overflow interrupt in PWM mode interrupts are not typically used in PWM type applications Instead the pulse at the TOPWM pin is held to High level as long a
67. Writable RP0 RP1 Modulo Size 000 210 modulo area dddd0000000000 dddd MCO 9 0 001 23 modulo area dddddddddddd000 ddddddddddd MC 2 0 010 2 modulo area ddddddddddd0000 dddddddddd MC 3 0 011 25 modulo area dddddddddd00000 ddddddddd MC 4 0 100 26 modulo area ddddddddd000000 dddddddd MC 5 0 101 27 modulo area dddddddd0000000 ddddddd MC 6 0 110 28 modulo area ddddddd00000000 dddddd MC 7 0 111 29 modulo area dddddd000000000 ddddd MC 8 0 Modulo Upper Boundary Bit Reverse Modulo Size Upper Boundary Bit Reverse Order 000 reverse RPi 4 0 001 reverse RPi 5 0 010 reverse RPi 6 0 011 reverse RPi 7 0 100 reverse RPi 8 0 101 reverse RPi 9 0 110 reverse RPi 10 0 111 2 reverse RPi 11 0 RP2 RP3 Modulo Size 000 210 modulo area dddd0000000000 dddd MCO 9 0 ELECTRONES 001 23 modulo area 010 24 modulo area 011 25 modulo area 100 28 modulo area 101 27 modulo area 110 28 modulo area 111 29 modulo area Modulo Upper Bounda NOTE dddddddddddd000 ddddddddddd MC 2 0 ddddddddddd0000 dddddddddd MC 3 0 dddddddddd00000 ddddddddd MC 4 0 ddddddddd000000 dddddddd MC 5 0 dddddddd0000000 ddddddd MC 6 0 ddddddd00000000 dddddd MC 7 0 dddddd000000000 ddddd MC 8 0 ry d means DON T CARE Figure 21 9 Modulo Control Register Configuration 21 17 CalmMAC1616 S3CC11B FC11B Bit Reverse Capabi
68. a 22 bit register This instruction subtracts the value of 5 bit immediate imm 5 from the value of 22 bit register An and stores the result in register An 15 14 43 12 4 10 8 7 6 5 4 0 am Operation An An lt imm 5 gt Exceptions None Notes None ELECTRONES 6 103 INSTRUCTION SET S3CC11B FC11B SWI software Interrupt Format Description Operation Exceptions Notes 6 104 SWI lt imm 6 gt The SWI Software Interrupt instruction performs a specified set of operations i e an SWI handler This instruction can be used as an interface to the low level system software such as operating system Executing this instruction is similar to performing a function call However interrupts IRQ and TRQ will be masked off so that when a software interrupt is handled it can be seen as an uninterruptible operation Note that FIQ can still be triggered when an SWI is serviced Return from a SWI handler is done by RET SWI unlike normal function calls 15 14 43 12 4 10 9 8 7 6 5 0 mme 14 2 SSR SWI SR IE 0 TE 0 PC lt imm 6 gt lt lt 2 None Program addresses from 000000h to 0000feh are reserved for SWI handlers SWI vectors 0 and 1 are not used as the addresses from 000000h to 000007h are reserved for other interrupts ELECTRONES S3CC11B FC11B INSTRUCTION SET SYS System Forma
69. an absolute minimum Any change in the input level perhaps due to noise will invalidate the result If the chip enters to STOP or IDLE mode in conversion process there will be a leakage current path in A D block You must use STOP or IDLE mode after ADC operation is finished ELECTRONICS 16 1 10 BIT A D CONVERTER S3CC11B FC11B CONVERSION TIMING The A D conversion process requires 4 steps 4 clock edges to convert each bit and 10 clocks to set up A D conversion Therefore total of 50 clocks are required to complete an 10 bit conversion When fxx 8 is selected for conversion clock with an 4 5 MHz fxx clock frequency one clock cycle is 1 78 us Each bit conversion requires 4 clocks the conversion rate is calculated as follows 4 clocks bit x 10 bit set up time 50 clocks 50 clock x 1 78 us 89 us at 0 56 MHz 4 5 MHz 8 Note that A D converter needs at least 2545 for conversion time A D CONVERTER CONTROL REGISTER ADCON10 The A D converter control register ADCON10 is located at address 51H It has three functions Analog input pin selection bits 4 5 End ofconversion status detection bit 3 ADC clock selection bits 2 and 1 A D operation start or disable bit 0 After a reset the start bit is turned off You can select only one analog input channel at a time Other analog input pins ADO AD3 can be selected dynamically by manipulating the ADCON10 4 5 bits And the pins not used for analog in
70. analog input And you write the channel selection data in the A D converter control register ADCON10 4 5 to select one of the eight analog input pins AD0 AD3 and set the conversion start or enable bit ADCON10 0 The read write ADCON10 register is located in address 51H The pins which are not used for ADC can be used for normal I O or TOCLK signal During a normal conversion ADC logic initially sets the successive approximation register to 800H the approximate half way point of an 10 bit register This register is then updated automatically during each conversion step The successive approximation block performs 10 bit conversions for one input channel at a time You can dynamically select different channels by manipulating the channel selection bit value ADCON10 5 4 in the ADCON10 register To start the A D conversion you should set the enable bit ADCON10 0 When a conversion is completed ADCON 10 3 the end of conversion EOC bit is automatically set to 1 and the result is dumped into the ADDATAH10 ADDATAL10 register where it can be read The A D converter then enters an idle state Remember to read the contents of ADDATAH10 ADDATAL10 before another conversion starts Otherwise the previous result will be overwritten by the next conversion result NOTE Because the A D converter has no sample and hold circuitry it is very important that fluctuation in the analog level at the ADO ADS input pins during a conversion procedure be kept to
71. and TE bits are cleared SWI 0 and SWI 1 are prohibited because the addresses are reserved for other interrupts When RET SWI instruction is executed SR is restored from SSR_SWI and the return address is restored to PC from A14 BREAK EXCEPTION Break exception is reserved only for an in circuit debugger When a core input signal BKREQ is high the CalmRISC16 core is halted or in the break mode until BKREQ is deactivated Another way to drive the CalmRISC16 core into the break mode is by executing a break instruction BREAK When BREAK is fetched it is decoded and the CalmRISC16 core output signal nBKACK is generated An in circuit debugger generates BKREQ active by monitoring nBKACK to be active BREAK instruction is exactly the same as the NOP no operation instruction except that it does not increase the program counter and activates nBKACK There once BREAK is encountered in the program execution it falls into a deadlock BREAK instruction is reserved for in circuit debuggers only so it should not be used in user programs NOTE imm 6 is defined as 6 bit immediate number 4 2 ELECTRONES S3CC11B FC11B FIQ Sources EXCEP TIONS If the memory request tries to access non existent memory area FIQ is generated In this case if the FE bit in SR is 1 then FIQ routine is called and executed But the FIQ is not used in the S3CC11B INTERRUPT SOURCES IRQ Vector 000000H 000002H Source Hardware Reset Fast Interrupt
72. and link 51 ESFT B A Previous Data Shift ESUB A 16 Preprocessing for Linking ESFTL SIA Current Data Shift Right Link SR SG lt B gt gt A and link SI ESFT Previous Data Shift EADD A 16 Preprocessing for Linking ESFTL SILA Current Data Shift Bit Field Operation The barrel shifter supports a bit field masking operation This operation can be used for data bit stream manipulation only Various bit field operations such as bit set bit reset bit change and bit test operation is supported in CalmRISC16 host processor So the CalmMAC16 need not powerful bit operation capabilities ENMSK instruction is provided for bit pattern masking This instruction masks MSBs of SG register with selected mask pattern The mask pattern is generated according to the 4 bit immediate operand embedded in the instruction 21 32 ELECTRONES S3CC11B FC11B CalmMAC1616 EXPONENT BLOCK The exponent block performs exponent evaluation of one of the four 16 bit accumulator registers A B C D The result of this operation is a signed 7 bit value and transferred into the Shift Amount register SA The source operand is unaffected by this calculation Table 21 1 Exponent Evaluation and Normalization Example Evaluated Number lt N Exponent Result Normalized Number 00001101 3 shift left by 3 01101 11101010 2 shift left by 2 101010 00000011 5 shift left by 5 011 11111011 4 shift left by 4
73. display using VLC1 with external voltage P Tr off 1 0 Not available Normal display using VLC1 with internal voltage P Tr on 5 4 Bits 5 4 3 2 LCD Duty and Bias Selection Bits o o fvadmyGow comesse ides Fo ides i 1 0 selec v rs E 1 0 LCD Clock Selection Bits fw 27 256 Hz when fw is 32 768 kHz fw 29 512 Hz when fw is 32 768 kHz 1 fw 25 1 024 Hz when fw is 32 768 kHz fw 24 2 048 Hz when fw is 32 768 kHz 18 4 ELECTRONES S3CC11B FC11B LCD CONTROLLER DRIVER LMOD Lcp Node Control Register 3F0073H Reset Value _ _ _ 0 0 0 Read Write _ R W R W R W 4 3 Bits 7 3 2 SEG2 Signal Selection Bit When P4 3 is selected as alternative function only CCLK output SEG2 output 4 Signal Selection Bit When P4 2 is selected as alternative function only EN CFS output SEG1 output 0 SEGO Signal Selection Bit When P4 1 is selected as alterna tive function only ELECTRONES CDX output SEGO output BB 18 LCD CONTROLLER DRIVER S3CC11B FC11B LCD VOLTAGE DIVIDINGRESISTORS On chip voltage dividing resistors for the LCD drive power supply are fixed to the c _V cs pins Figure 15 5 shows the bias connections for the S3CC11B FC11B LCD drive power supply To cut off the flow of current through the dividing resistor manipulate bits 7 and 6 of the LCON register Application Without
74. is generated by load Reset if not N Set if loaded value is negative Notes MjSR 1 it right shifted MAj 31 16 MjSL t bit left shited MAj 31 16 Examples EMUL X1Y0 A MA1SR EMUL 0 0 X0 RP1 S1 of Words 1 ELECTRONES 21 99 CalmMAC1616 S3CC11B FC11B EMUL _ multiply w Two Parallel Moves Format EMUL 015 Yi rp3s Operation P Xi Yi Xi operand1 by rp01s Yi operand2 by rp3s This instruction multiplies Xi register value and Yi register value and stores the result to the P register This instruction also stores two source operands from data memory one from X memory space and one from Y memory space to the 16 bit Xi register and Yi register respectively Flags _ Notes _ Examples EMUL X1YO X0 RP0 S1 Y0 RP3 S0 of Words 1 21 100 ELECTRONES S3CC11B FC11B CalmMAC1616 negate Format ENEG T An Operation lt 1 This instruction negates the value of one of 16 bit Accumulator and stores the result back into the same Accumulator Flags C set if carry is generated Reset if not Z set if result is zero Reset if not V set if overflow is generated Reset if not N exclusive OR of V and MSB of result Refer to Chapter 2 for more detailed explanation about this convention Notes ENEGT instruction can be executed only when the T flag is set Otherwise No operation is performed Examples ENEG A
75. is specified as PRN the rounded value of 16 bit higher portion of P register is read as a source operand The value of MA register or P register itself is not changed at all MA Shifting Capabilities Two shift operations are enabled inside the CalmMAC16 the first one concerns the whole 32 bit MAi accumulator register and 4 bit extension nibble the second concerns a higher 16 bit portion of MAi register MAiH during 16 bit arithmetic operation in ARU Each of the two multiplier accumulators can be shifted arithmetically by 1 bit left or right The first shift operation is provided by the ESLA 1 bit shift left arithmetic or ESRA 1 bit shift right arithmetic instruction The second shifting is provided as a form of source operand MAISL or MAiSR When the source operand of 16 bit arithmetic operation ARU is specified as MAISL the 1 bit left shifted value of 16 bit higher portion of register is read as a source operand When the source operand is specified as MAISR the 1 bit right shifted value of 16 bit higher portion of MAi register is read The value of MA register itself is not changed at all Double Precision Multiplication Support The arithmetic unit support for double precision multiplication by add or subtract instruction with an alignment option of the P register EADD MAi PSH or ESUB MAi PSH instruction In this case the P register is aligned shifting 16 bits to the right before accumulating the p
76. last shifted out bit is 1 Reset if not Unchanged when shift amount is 0 Set if SR result is zero Reset if not Reset MSB of SR result ESFTL A B ESFTL SI SA ELECTRONES S3CC11B FC11B CalmMAC1616 ESLA ESLAT Arithmetic 1 bit Left Shift Accumulator Format ESLA T An Operation An An lt lt 1 This instruction shifts the value of one of 16 bit Accumulator An to 1 bit left and stores the result back into the same accumulator Flags C Set if shifted out bit is 1 Reset if not Z Set if result is zero Reset if not V Set if overflow is generated Reset if not N Exclusive OR of V and MSB of result Refer to Chapter 2 for more detailed explanation about this convention Notes ESLAT instruction can be executed only when the T flag is set Otherwise No operation is performed Examples ESLA A ESLAT D of Words 1 ELECTRONES 21 119 CalmMAC1616 S3CC11B FC11B ESLA 2 _ Arithmetic 1 bit Left Shift Multiplier Accumulator Format ESLA Mi Operation MAi MAi 1 This instruction shifts one of the 36 bit Multiplier Accumulator MAi to 1 bit left and stores the result back into the same Multiplier Accumulator Flags VMi Set if result is overflowed to guard bits Reset if not MV Set if guard bit is overflowed Unchanged if not Notes VMi denotes for VMO or VM1 according to Mi Examples ESLA MAO of Words 1 21 120 ELECTRONES S3CC11B FC11B CalmMAC1616 ESLA8 ESLAS8T
77. least significant byte of Di Dn and Di are registers from RO to R7 The 16 bit multiplication result is written back to Dn The mode is one of UU US SU SS The mode indicates each operand is signed value or unsigned value if M1 0 amp amp M2 0 mode UU Dn lower 16 bits of 0 Dn 7 0 0 Di 7 0 else if M1 0 amp amp M2 1 mode US Dn lower 16 bits of 0 Dn 7 0 Di 7 Di 7 0 else if M1 1 amp amp M2 0 mode SU Dn lower 16 bits of Dn 7 Dn 7 0 0 Di 7 0 else mode SS Dn lower 16 bits of Dn 7 Dn 7 0 Di 7 Di 7 0 None None ELECTRONES S3CC11B FC11B INSTRUCTION SET NOP Operation Format NOP Description The NOP No Operation instruction does not perform any operation Operation None Exceptions None Notes None ELECTRONES 6 77 INSTRUCTION SET S3CC11B FC11B OR 1 Format Description Operation Exceptions Notes 6 78 OR Register OR Rn Ri The OR OR Register instruction is used to perform bitwise OR operation on two values in registers Rn and Ri The result is stored in register Rn The T bit is updated based on the result 15 14 13 12 4 8 7 6 5 4 3 0 m Rn Rn Ri T bit Rn Ri 0 if Rn R6 R7 Z0 Z1 Rn Ri 0 None None ELECTRONES S3CC11B FC11B OR 2 Format Description Operation Exceptions
78. moved scrolled highlighted added or removed docked or undocked completely IN CIRCUIT EMULATOR The evaluation chip of CalmRISC16 has a basic debugging utility block Using this block evaluation chip directly interfaces with host through only communication wire So InvisibleMDS offers simple and powerful debugging environment CalmRISC16 C COMPILER CalmCC16 The CalmRISC16 Compiler offers the standard features of the C language plus many extensions for MCU applications such as interrupt handling in C and data placement controls designed to take fully advantage of CalmRISC16 facilities It conforms to the ANSI specification It supports standard library of functions applicable to MCU systems The standard library also conforms to the ANSI standard It generates highly size optimized code for CalmRISC16 by fully utilizing CalmRISC16 architecture It is available in a Windows version integrated with the CalmSHINE CalmRISC16 REL OCATABLE ASSEMBLER Calm8ASM The CalmRISC16 Assembler is a relocatable assembler for Samsung s CalmRISC16 MCU and its MAC1616 and MAC2424 coprocessors It translates a source file containing assembly language statements into a relocatable machine object code file in Samsung format It runs on WINDOWS95 compatible operating systems It supports macros conditional assembly It produces the relocatable object code only so the user should link object files Object files can be linked with other object files and
79. multiplier multiplies Xi register value and Yi register value and stores the result to the P register This instruction also stores source operand from data memory or 16 bit higher portion of the MAj register to the destination register Set if result is overflowed to guard bits Reset if not Set if guard bit is overflowed Unchanged if not When dest is Ai Set if the value to Ai is zero by load Reset if not Set if overflow is generated by load Reset if not Set if loaded value is negative Notes MjSR 1 bit right shifted MAj 31 16 Examples of Words 21 86 MjSL 1 bit left shifted MAj 31 16 denotes for VMO or VM1 according to the Mi EMAD MAO X1Y0 A MA1SR EMAD MA1 X0Y0 X0 RP1 S1 1 ELECTRONES S3CC11B FC11B CalmMAC1616 3 EMAD 3 _ multiply Add w Two Parallel Moves Format EMAD Mi XiYi Xi rp01s Yi rp3s Operation MAi MAi P P Xi Yi Xi operand1 by rp01s Yi lt operand2 by rp3s This instruction adds the values of 36 bit Multiplier Accumulator MAi and P register together and stores the result back into Multiplier Accumulator MAi At the same time multiplier multiplies Xi register value and Yi register value and stores the result to the P register This instruction also stores two source operands from data memory one from X memory space and one from Y memory space to the 16 bit Xi register and Yi register respectively Flags VMi Set if result i
80. ofo ofo ofi ofa alo alo 3 2 Bit 3 2 1 Timer 1 A Counter Clear Bit No effect 1 Clear the timer 1 A counter when write 0 Timer 1 A Counter Enable Bit Disable counting operation 1 Enable counting operation 13 2 ELECTRONES S3CC11B FC11B 16 BIT TIMER 1 8 BIT TIMER A amp B TBCON Timer B Control Register 3F0049H Reset Value 0 0 0 0 0 0 0 Read Write _ R W R W R W R W R W R W R W 7 Bit 7 6 4 Timer B Clock Selection Bits opos ofpe 1 o ft sub clock 3 16 Bit Operation Timer B Clock Input Selection Bit Timer overflow out 1 Timer A interval out 2 Timer Mode Selection Bit 0 8 bit operation mode 1 16 bit operation mode 1 Timer B Counter Clear Bit No effect 1 Clear the timer B counter when write 0 Timer B Counter Enable Bit Disable counting operation 1 Enable counting operation 1 ELECTRONES 13 16 BIT TIMER 1 8 BIT TIMER A amp B S3CC11B FC11B BLOCK DIAGRAM TBCON 2 Timer A Data Register MUX TBCON 2 TBCON O Read Write TBCON3 a TBCON 3 TACON 6 5 4 Timer A Buffer Register Q fxx 409 104096 0 Interval fxx 512 8 Bit Comparator Output Gen 1 TACNT 8 Bit TAINT Up Counter Read Only 0 and 1 means mux input fxx 409 fxx 512 fxx 64 fxx 8 Interval TBOU Output Gen TBINT TBCNT 8 Bit Up Counter Read Olny Timer B Data Register Read Write Figure
81. op This instruction subtracts op value from the value of one of 16 bit Accumulator An and stores the result back into the same Accumulator If op is immediate value it is first right adjusted and sign extended to 16 bit value If op is 16 bit register it is zero extended Flags C Set if carry is generated Reset if not Z Set if result is zero Reset if not V Set if overflow is generated Reset if not N Exclusive OR of V and MSB of result Refer to Chapter 2 for more detailed explanation about this convention Notes _ Examples SUB A 0486h ESUB B C ESUB D RP0 of Words 1 2 when op is simm 16 ELECTRONES 21 127 CalmMAC1616 S3CC11B FC11B ESU B 2 Subtract Accumulator w One Parallel Move Format Operation Flags C Z V N VMi 1 ESUB Ai Mi dest src lt dest gt lt src gt mgx rps Mi rps rpd mga rpd P 2 ESUB Ai Ci Cj rps 1 Ai Ai Mi dest lt src 2 Ai lt Ai Cj lt rps This instruction subtracts higher 16 bit part of Multiplier Accumulator MAO or MA1 register the value of 16 bit Accumulator Ci C or D register from the values of 16 bit Accumulator Ai A or B register and stores the result back into the same accumulator Ai This instruction also stores a source operand from memory or register to the destination register or memory location Set if carry is generated by addition Reset if not
82. por me x NOTE suffix means that instruction is executed when T flag is set 21 48 ELECTRONES S3CC11B FC11B CalmMAC1616 e emod2 Encoding ERESR 0101 Restore Remainder 0110 Reserved om me _ gt gt n ee SSCS e Mnemonic X0Y0 X0 15 0 YO 15 0 X0Y1 01 X0 15 0 Y1 15 0 X1Y0 10 X1 15 0 Y0 15 0 xiYi 1 15 0 Y1 15 0 Xi Yi wem YO 0115 0 YO 15 0 register X1 15 0 Y1 15 0 register X1 Y1 ELECTRONES 21 49 CalmMAC1616 S3CC11B FC11B rs em o Sen S Mnemonic im Description MAO 31 0 p rpi mnemonic 21 50 ELECTRONES S3CC11B FC11B CalmMAC1616 Overall COP Instruction Set Map uus mee Te Tr s sp s 1 ELD mg imm 16 imm fafa ELD mgx imm 6 rir oe m r mms EIER ER T ON Fe o o 1 T 1 0 A avs ________ 1 an avs EMAD Mi ay mgx rps XiYi evs wi moe o Bien eee pom cri E ESUBMP mOms mx 1 1 m EADD Mi P An em Mi EM pi S 3 ELD MiP An ps m a EE p NC sn CN ESUBMP Opima ELD P X mga Mi dri i ESUB Mi P ELD Mi P rpd P
83. read through XB bus the saturation is not occurred Saturation Condition Arithmetic instruction amp 16 bit Overflow amp OP 21 22 ELECTRONES S3CC11B FC11B CalmMAC1616 Main Accumulators Auxiliary Accumulators Figure 21 13 Accumulator Register Configuration Maximum Minimum Possibilities A single Cycle maximum minimum operation is available with pointer latching and modification One of the Ai accumulator registers defined in the instruction holds the maximum value in a instruction or the minimum value in a EMIN instruction In one cycle the two accumulators are compared and when a new maximal or minimal number is found this value is copied to the above defined accumulator In the same instruction one of pointer register RPi except RP3 pointer can be used as a buffer pointer The address pointer register that generates address can be post modified according to the specified mode in the instruction When the new maximum or minimum number is found the address register user invisible register value is latched into RP3 pointer register The address register stores original pointer register value during pointer modification instructions instructions with indirect addressing ERPS ERPD instruction or ERPN instruction For more details refer to EMAX and EMIN instructions in chapter 4 on the instruction set The examples which searches block elements are as follows ELD C RP0 S0
84. service routine But also the corresponding pending bit is cleared by S W when it is written ID x 2 value to the IIR register Where the ID is a bit of IRR for example the ID of SIO INT is 8 All pending bits are cleared when 80H is written to IIR register IRQ Core Figure 4 2 Interrupt Structure 4 4 ELECTRONES S3CC11B FC11B EXCEP TIONS INTERRUPT CONTROL REGISTER The calmRISC16 has 4 types registers IRR IMR IIR IPR INTERRUPT MASKING REGISTER Interrupt masking register is IMR The role of IMR masks the pending interrupt Although any interrupt source sets the nterrupt pending register the interrupt cannot be send to the core if the interrupt is masked 0 mask defaule value 1 unmask INTERRUPT PROIRITY REGISTER Interrupt priority register is IPR The IPR register determine the serving order of interrupts when any interrupts of 21 sources occur simultaneously ELECTRONES 4 5 EXCEPTIONS S3CC11B FC11B IMRH Interrupt Mask Register High 3F0006H Reset Value 0 0 0 0 0 0 Read Write _ R W R W R R W R W R W Addressing Mode Register addressing mode only 7 6 Bits 7 6 0 Always logic 0 5 External P4 4 P4 7 IRR 13 Interrupt Enable Bit Disable interrupt request Enable interrupt request 4 External P0 3 IRR 12 Disable interrupt request 1 Enable interrupt request 3 External P0 2 IRR 11 Interrupt Enable Bit Disable interrupt request 1 Enable interrupt request 2
85. source operands The 16 bit value is rightjustified and sign extended to the 16 bit operand when the destination operand is 16 bit When the destination register has 16 bit width the immediate value is no changed The long immediate requires the second instruction code 21 38 ELECTRONES S3CC11B FC11B CalmMAC1616 INSTRUCTION CODING Abbreviation Definition and Encoding mps wemws meg O O RPO SO 000 RPO post modified by 500 SO field RP14S0 RP1 post modified by SD1 SO field RP2 S0 RP2 post modified by 502 50 field RP3 S0 RP3 post modified by SD3 S0 field RP0 S1 RP0 post modified by SD0 S1 field RP1 S1 RP1 post modified by SD1 S1 field RP2 S1 RP2 post modified by SD2 S1 field RP3 S1 RP3 post modified by SD3 S1 field rpd Mnemonic Encoding Description RP0 D0 000 RP0 post modified by SD0 DO field 001 Pisco om AP postmtiod by s01 Dotee RP1 D1 RP1 post modified by SD1 D1 field RP2 D1 RP2 post modified by SD2 D1 field RP3 D1 RP3 post modified by SD3 D1 field e 1 015 RPO0 S0 RPO post modified by SDO S0 field RPO post modified by SDO S1 field RP1 post modified by SD1 S1 field RP0 S1 RP1 S1 RP1 S0 RP1 post modified by SD1 S0 field ELECTRONES 21 39 CalmMAC1616 S3CC11B FC11B rp3s Emo Bemhin RP3 S0 O RP3 postmodified by 503 SO field RP3 post modified by SD3 S1 field Encoding Description 000 Y0 15 0 register 0 15 0 registe
86. the 4 bit immediate value to the specified bit field of MSR2 register bit 15 bit 12 Only 4 bit field of 16 bit register value is changed Flags Notes Examples EBK 1010b of Words 1 21 66 ELECTRONES S3CC11B FC11B CalmMAC1616 ECLD Coprocessor Accumulator Load from host processor Format ECLD ereg Dn ECLD Dn ereg Operation ereg lt Dn or Dn lt ereg This instruction moves the selected 16 bit general purpose register value of host processor to the An A B C or D accumulator register or shifter register SA SR SG SI or vice versa This instruction is mapped to CLD instruction of CalmRISC microcontroller Flags Notes This instruction has delay slot Because this instruction is 2 cycle instruction Examples ECLD A R0 ECLD R3 BH ECLD SI R3 of Words 1 ELECTRONES 21 67 CalmMAC1616 ECP Format Operation Flags C Notes Examples of Words 21 68 Compare Accumulator ECP An lt op gt lt op gt simm 5 simm 16 Am mg mgx An lt op gt S3CC11B FC11B This Instruction compares the values of Accumulator An and lt op gt by subtracting lt op gt from Accumulator Content of Accumulator is not changed If op is immediate value it is first right adjusted and sign extended to 16 bit value If op is 16 bit register it is zero extended Set if carry is generated Reset if not Set if result is zero Reset if not Set if overflow
87. when BLDCON O is set If VDD level is lower than the reference voltage selected with BLDCON 4 2 BLDCON 1 will be set If VDD level is higher BLDCON 1 will be cleared When users need to minimize current consumption do not operate the BLD block Vpp Pin Battery Level BLDCON 1 Detector BLD Out BLDCON 0 Battery BLD Run Level Setting BLDCON 4 2 Set the Level Figure 19 1 Block Diagram for Battery Level Detect ELECTRONICS 19 1 BATTERY LEVEL DETECTOR S3CC11B FC11B BATTERY LEVEL DETECTOR CONTROL REGISTER BLDCON The bit 0 of BLDCON controls to run or disable the operation of battery level detect Basically this Vg p is set as invalid by system reset and it can be changed in 2 kinds voltages by selecting Battery Level Detect Control register BLDCON When you write 3 bit data value to BLDCON an established resistor string is selected and the Vg p is fixed in accordance with this resistor Table 16 1 shows specific Vg p of 2 levels Battery Level Detector Control Register BLDCON Resistor String 74H R W Reset 00H Not used Comparator BLD OUT BANDGAP BLD Enable Disable NOTES 1 The reset value of BLDCON is 00H 2 VREFis about 1 volt Figure 19 2 Battery Level Detector Circuit and Control Register Table 19 1 BLDCON Value and Detection Level 2 45 2 70 V 19 2 ELECTRONICS S3CC11B FC11B 8 16 BIT SERIAL INTERFACEFOR EXTERNAL CODEC 8 16 BIT SERIAL INTERFACE FOR EXT
88. wmm Pona Regier _____ Pa om mw mem Port 6 Data Register 1 Pe War l P8 Pot 7 Daa Resist room om mw Daa Regis sme om mw Pont 9 Data Register po see om I O Port n Data Register n 0 9 n 0 9 R W 8 3 2 Figure 9 1 Port Data Register Structure ELECTRONES 9 1 PORTS S3CC11B FC11B POCONH Port 0 control Register High 3F0020H Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 P0 7 SCK Configuration Bits Schmitt trigger input SCK input Push pull output N channel open drain output 3 2 1 0 P0 4 Configuration Bits Schmitt trigger input Push pull output N channel open drain output Not available 9 2 ELECTRONES S3CC11B FC11B VO PORTS POCONL Port 0 Control Register Low 3F0021H Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 P0 3 INT3 Configuration Bits 0 o Schmitt trigger input O Push pull output N channel open drain output Not available 5 4 P0 2 INT2 Configuration Bits ofo op moa Nerem openana 7 3 2 P0 1 INT1 Configuration Bits 1 0 P0 0 INTO Configuration Bits 0 o Schmitmoger
89. 00pF 250pF ELECTRONICS 26 3 DEVELOPMENT TOOLS S3CC11B FC11B POWER SELECTION JP10 State Description Same Power Source from Target System CLOCK SELECTION Description OSC is used to clock source for evaluation chip MXOUT OSC CLK CPU X TAL X TAL is used to clock source for evaluation chip XTALO MXOUT XTALI CPU 26 4 ELECTRONICS S3CC11B FC11B DEVELOPMENT TOOLS JP1 JP2 PINASSIGNMENT ur rn aria in _ Pi w ov 1 we mer a me 3 fe mer Ls s mes we 7 sN a 7 e me ow s wer pw Es s mens ma MPO 2 MPO 1 MP6 5 MP6 6 25 MPO 0 26 MP1 0 25 MP6 7 26 MP7 0 MP1 5 MP1 6 31 MP7 5 32 7 6 wo p owe am wm men wes wes 3 0 we 5 wes wea as we wes wes wmo wer e wer s wee w wes so wes JP11 PIN ASSIGNMENT L n 3 4 5 ELECTRONICS 26 5 DEVELOPMENT TOOLS S3CC11B FC11B NOTES 26 6 ELECTRONICS
90. 1111000 0 0010 1001 0 0110 0000 1 1010 0000 0 0101 1000 1 1100 1001 1010 0001 9406 11001 0010 Quotient 1 8 0010 0 0000 0000 0 1100 0000 0 1011 0001 0 0101 0010 Remainder Remainder 11 128 5 128 Figure 21 5 Fractional Division Example A 32 16 fractional division example code is as follows ER NQ Initialize Division Step EDIVQ MA P Division Step EDIVQ MA P Division Step 16 times ERESR MA P Remainder Restoring Note that the validity of the division operand must be checked before all of these code i e the dividend is strictly smaller than the divisor The previous two figures show division with 9 bit dividend and 8 bit divisor Assume that the MA register and P register are 8 bit wide and MA guard bit is 1 bit wide 21 10 ELECTRONES S3CC11B FC11B CalmMAC1616 STATUS REGISTER 1 MSR1 register of three CalmMAC16 status registers MSRO MSR1 MSR2 is used to hold the flags control bits status bits for MAU The contents of each field definitions are described as follows If MSR1 register is used as a 16 bit source operand in 16 bit arithmetic operation the 16 bit MSR1 register is zero extended to a 16 bit operand 8 7 6 5 4 3 2 1 0 MA1 Register Extension Nibble MAO Register Extension Nibble Arithmetic Overflow Protection 0 when Reset Not Quotient 0 Subtraction Reset Value 1 Addition Product Left Shift 1 Control 0 No Shift Reset Value 1 1 bit Lef
91. 122 ELECTRONES S3CC11B FC11B CalmMAC1616 ESRA ESRAT arithmetic 1 bit Right Shift Accumulator Format ESRA T An Operation An lt An 1 This instruction shifts the value of one of 16 bit Accumulator An to 1 bit right and stores the result back into the same accumulator Flags C Set if shifted out bit is 1 Reset if not Z Set if result is zero Reset if not V Set if overflow is generated Reset if not N Exclusive OR of V and MSB of result Refer to Chapter 2 for more detailed explanation about this convention Notes ESLRT instruction can be executed only when the T flag is set Otherwise No operation is performed Examples ESRA A ESRAT B of Words 1 ELECTRONES 21 123 CalmMAC1616 S3CC11B FC11B ESRA _ Arithmetic 1 bit Right Shift Multiplier Accumulator Format ESRA Mi Operation lt gt gt 1 This instruction shifts one of the 36 bit Multiplier Accumulator to 1 bit right and stores the result back into the same Multiplier Accumulator Flags VMi Set if result is overflowed to guard bits Reset if not MV Set if guard bit is overflowed Unchanged if not Notes VMi denotes for VMO or VM1 according to Mi Examples ESRA MA1 of Words 1 21 124 ELECTRONES S3CC11B FC11B CalmMAC1616 ESRAS ESRAGBT arithmetic 8 bit Right Shift Accumulator Format ESRAB8 T An Operation lt An gt gt 8 This instruction shifts the value of one of 16 bit Ac
92. 15 Eo rere m o 3 ae m ore m Espia mme Eswwama frfofifolifi m mme v o o mf mme m A woo m o mo An gt mm o _ o o m a a xw emomxmam r o om EE EMAX Ai EMAX AiCi EMIN Ai Ci 1 1 Ci 0 1 uL eeepc OE TONY 33 mos Cm Suse EN foe pap EMSB Mi XiYi Ai mommas 1 wowxw 4 fifififofolo ELECTRONES 21 53 CalmMAC1616 S3CC11B FC11B Overall COP instruction set map Continued 5 EAD XM AMSA ppp o resem moman o ewuan a a o EMDMiXYi ________ 1 1 1 1 1 1 4 xvi EMUL XiYi 1 1 XiYi er HER NU ELD An imm 5 imm 5 eomas _____ e omes ECP An imm 5 1 0 An imm 5 Ems rpi An 0 nana aoma oo 2 Mi 1 1 1 1 1 0 1 ETST cc T EC3 1 1 1 1 1 0 0 TE mere ep poo Eme
93. 15t Data load Loop start EMAX EMIN A C C RP0 S0 1S Min Max evaluation 279 Data load JP Loop_start EMAX EMIN A C Last Min Max evaluation Conditional Instruction Execution Some instructions can be performed according to the T flag value of MSRO register These instructions may operate when the T flag is set and do nothing if the T flag is cleared The instructions which have suffix T are this type of instructions emod1 type instruction The conditional instruction execution capabilities can reduce the use of branch instructions which require several cycles Shifting Operations A few options of shifting are available in the ARU and all of them are performed in a single cycle All shift operations performed in the ARU are arithmetic shift operations i e right shift filling the MSBs with sign values and left shift filling with LSBs with zeros The source and destination operands are one of 16 bit Ai or Ci accumulator registers The shift instructions performed in the ARU are all conditional instructions The shift amount is limited to 1 and 8 right or left respectively The shift with carry is also supported ELECTRONES 21 23 CalmMAC1616 S3CC11B FC11B Multi Precision Support Various instructions which help multi precision arithmetic operation are provided in the CalmMAC16 The instructions with suffix C indicates that the operation is performed on source operand and current carry flag value By using these
94. 16 bit Accumulator Ai This instruction also stores source operand from memory or register to destination register or memory Flags Z Set if result is zero by load Reset if not V Set if overflow is generated by load Reset if not N Set if loaded value is negative Set if result is overflowed to guard bits Reset if not Notes VMi denotes for VMO or VM1 according to Mi if dest is Mi Examples ELD A XO QRPO S1 ELD A MA RP1 S0 ELD A RP3 D1 A of Words 1 ELECTRONES 21 79 CalmMAC1616 S3CC11B FC11B ELD M Load Multiplier Accumulator Format ELD MAO MA1 ELD MA1 MAO Operation This instruction loads the value of the one 36 bit Multiplier Accumulator MAi from the other Multiplier Accumulator Flags VMi Set if result is overflowed to guard bits Reset if not Notes VMi denotes for VMO or VM1 according to destination Multiplier Accumulator Examples ELD MA1 MAO ELD MAO MA1 of Words 1 21 80 ELECTRONES S3CC11B FC11B CalmMAC1616 ELD 4 _ Load Multiplier Accumulator w One Parallel Move Format ELD Mi P lt dest gt lt src gt lt dest gt lt src gt mgx rps An rps rpd mga rpd P Operation MAi lt P lt dest gt lt lt src gt This instruction load sign extended 32 bit Product register P to the 36 bit Multiplier Accumulator MAi This instruction also stores source operand from memory or register to destination register or me
95. 16 bit operand the 16 bit value is zero extended to 16 bit value The detailed block diagram of the RAM Pointer Unit is shown in Figure 21 7 ELECTRONES 21 13 CalmMAC1616 YA 14 0 XA 14 0 e we sm X Modulo Logic Y Modulo Logic Bit Reverse Logic Figure 21 7 RAM Pointer Unit Block Diagram 21 14 S3CC11B FC11B ELECTRONES S3CC11B FC11B CalmMAC1616 ADDRESS MODIFICATION The RPU can generate up to two 15 bit addresses every instruction cycle which can be post modified by two modifiers linear and modulo modifier The address modifiers allow the creation of data structures in the data memory for circular buffers delay lines FIFOs etc Address modification is performed using 16 bit two s complement linear arithmetics Linear Step Modifier During one instruction cycle one or two of the pointer register RPi can be post incremented decremented by a 2 s complement 4 bit step from 8 to 7 If XSD bit of MSRO register is set these 4 bit step is extended to 8 bit from 128 to 127 by concatenating index register with extended index register SDOE SD3E when selected pointer is RPO or RP3 The selection of linear modifier type one out of four is included in the relevant instructions The four step values are stores in each index register SDi If the instruction requires a data memory read operation SO bit 3 to bit 0 or S1 bit 7 to bit 4 field of SDi register is selected as an index value
96. 2H 7 6 5 gt 0 0 R W R W Bits 7 2 Not used System Clock Selection Bits 1 EK 7 3 PLL Phase Locked Loop S3CC11B FC11B Stop Release INT Sub System Watch Timer PLLCON Main Oscillator and Oscillator PLL Circuit Circuit BLD Selector 1 2 OSCCON 3 d OSCCON 2 Stop OSCCON 0 Basic Timer Timer Counters Watch Timer fxin 128 Battery Level Detector 1 1 1 4096 LCD Controller Frequency Dividing Circuit Serial I O PWM Modules 1 1 1 2 1 3 1 8 SSFDC Interface CODEC Serial Interface for ext Codec CLKCON 1 0 Selector 2 CPU stop signal Oscillator by idle or stop DA 7 0 Control Circuit Idle or stop instruction makes DA 7 0 signal SYS intruction by CalmRISC16 CPU Figure 7 2 System Clock Circuit Diagram 7 4 ELECTRONES S3CC11B FC11B PLL Phase Locked Loop Figure 7 3 External Loop Filter for PLL ELECTRONES 7 5 PLL Phase Locked Loop 7 6 NOTES S3CC11B FC11B ELECTRONES S3CC11B FC11B RESET AND POWER DOWN RESET AND POWER DOWN OVERVIEW During a power on reset the voltage at goes to High level and the nRESET pin is forced to Low level The nRESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock This procedure brings S3CC11B into a known operating status For the time for CPU clock oscillation to stabilize t
97. 3 Subtract Extended Register Format Description Operation Exceptions Notes SUB An Ri This form of SUB instruction Subtract Extended Register is used to add a 16 bit unsigned register value from a 22 bit value in register This instruction subtracts the value of 16 bit register Ri from the value of 22 bit register An and stores the result in register An 15 14 13 12 11 10 8 7 6 5 4 3 0 am ififo o R Ri ELECTRONES 6 101 INSTRUCTION SET S3CC11B FC11B SUB 4 Subtract Large Immediate Format Description Operation Exceptions Notes 6 102 SUB An lt imm 16 gt The SUB Subtract Large Immediate instruction is used to subtract a 16 bit unsigned immediate value from a 22 bit register SUB subtracts the value of lt imm 16 gt from the value of An and stores the result in register An 15 14 13 12 1 10 9 8 7 6 5 4 3 2 0 t t a An An lt imm 16 gt None This is a 2 word instruction where the 16 bit immediate follows the instruction word shown above Unlike 1 word instructions therefore fetching of this instruction takes 2 cycles ELECTRONES S3CC11B FC11B INSTRUCTION SET SUB 5 Subtract 5 bit Immediate Format SUB An lt imm 5 gt Description This form of SUB instruction Subtract Extended Register is used to subtract a 5 bit unsigned immediate value from
98. 3 AVDD1 SEG17 P6 2 AVSS1 SEG16 P6 1 P0 4 SEG15 P6 0 P0 3 INT3 S3CC11B SEG14 P5 7 VDD1 S3FC11B o VSS1 2 Xout SEG13 P5 6 XIN 100 QFP 1420C SEG12 5 5 TEST SEG11 P5 4 XTin SEG10 P5 3 XTout SEG9 P5 2 nRESET SEG8 P5 1 P0 2 INT2 SEG7 P5 0 PO 1 INT1 SEG6 P4 7 INT7 PO O INTO SEG5 P4 6 INT6 1 0 1 00 SEG4 P4 5 INT5 P1 1 1 01 SEG3 P4 4 INT4 P1 2 1 02 SEG2 P4 3 CCLK P1 3 1 03 SEG1 P4 2 CFS P1 4 1 04 SEG0 P4 1 CDX 9 GQ 9 CO SE lt p SB FF VO LU LI UL LIE LL UT LT DE CE LE LE UE CE LT DD U LI L LQ CO LU LJ Q m LJ LI O o 999zt2t40009 92020000 BERS Aa eRe amp 15 2 2 Figure 1 2 S3CC11B FC11B Pin Assignments 100 QFP 1420C 1 4 ELECTRONES S3CC11B FC11B PRODUCT OVERVIEW P lt o N o X ON O Ix c GN GOGoogooocomDmlppmbonaauaax 599 55565 55545566566 co c 0 00 00 S x 10 Q c 6 AAN A AN Q QUGONROZZZZzZzzzmogooooOooo00G00 o o o OO OO OO O O ui mu LI LI LL LLIE LI LL LLI LLI gt gt amp gt 00 LO st O O O O LO QNI O O 00 cO O gt OO CO CO
99. 32k x 16 P0 0 P0 3 INTO INT3 P0 4 PO 5 SI P0 6 SO P0 7 SCK PORTO 3 1 00 P1 0 1 07 1 7 CLE ALE WP nWE nRE nCEO nCE1 3 R nB 4 LCD Driver Controller Smartmedia Interface PRODUCT OVERVIEW P7 0 P7 7 PORT7 SEG23 SEG30 P8 0 P8 4 e 8 SEG31 SEG35 P9 0 P9 7 PORTS COM7 COMO SI PO 5 50 SO P0 6 SCK P0 7 TOCLK P3 3 5 TIMER 0 TOOUT TOPWM TOCAP P3 4 TIMER A T1CLK P3 5 BUZ 3 TAOUT P3 6 TIMERB TBOUT P3 7 jar WATCH BUZ P3 5 T1CLK TIMER CDR P4 0 SIO for CDX P4 1 SEG0 ext Codec CFS P4 2 SEG1 CCLK P4 3 SEG2 AD0 AD2 P3 0 P3 2 AD3 P3 3 TOCLK C AVDD2 AVSS2 ADINP gt CODEC ADINN ADGAIN DAOUT VREFOUT COMO COM7 P9 7 P9 0 SEG0 SEG35 P4 1 P8 4 VLC1 Figure 1 1 S3CC11B FC11B Top Block Diagram ELECTRONES PRODUCT OVERVIEW S3CC11B FC11B PIN ASSIGNMENT 100 FI PO 5 SI 99 P0 6 SO 98 FI P0 7 SCK 97 I VLC1 96 COMO P9 7 9 COM1 P9 6 94 2 9 5 93 3 COM3 P9 4 92 COM4 P9 3 91 3 COM5 P9 2 90 1 COM6 P9 1 89 FI COM7 P9 0 88 Fa SEG35 P8 4 87 SEG34 P8 3 86 M SEG33 P8 2 85 FI SEG32 P8 1 84 Fa SEG31 P8 0 83 SEG30 P7 7 82 FI SEG29 P7 6 81 SEG28 P7 5 VDD3 1 80 SEG27 P7 4 VSS3 2 79 SEG26 P7 3 VREFOUT 3 78 SEG25 P7 2 ADGAIN 4 77 SEG24 P7 1 ADINN 5 76 SEG23 P7 0 ADINP 6 75 SEG22 P6 7 AVDD2 7 74 SEG21 P6 6 AVSS2 8 73 SEG20 P6 5 DAOUT SEG19 P6 4 LPF SEG18 P6
100. 6 P5 7 P6 0 P6 7 P7 0 P7 7 Same general characteristics as port6 8 NOTE The parentheses are a pin number of 100 TQFP package Table 1 1 SSCC11B FC11B Pin Description Circuit Type Description I O port with bit programmable pins Schmitt trigger input or pushpull open drain output and software assignable pull ups P0 0 P0 3 is alternatively used for external interrupt input noise filters I O port with nibble programmable pins Schmitt trigger input or push pull open drain output and software assignable pull ups Also configurable as smartmedia interface lines 1 00 07 I O port with bit programmable pins Schmitt trigger input or push pull open drain output and software assignable pull ups Also configurable as smartmedia interface lines nWE nRE WP R nB ALE CLE nCEO and nCE1 I O port with bit programmable pins Schmitt trigger input or push pull open drain output and software assignable pull ups P3 0 P3 3 is alternatively used for analog input I O port with bit programmable pins Schmitt trigger input or push pull open drain output and software assignable pull ups P4 4 P4 7 is alternatively used for external interrupt input noise filters interrupt enable control I O port with bit programmable pins Schmitt trigger input or push pull open drain output and software assignable pull ups I O port with nibble programmable pins Schmitt trigger input or push pull out
101. 70 71 Rn TO 0 None None ELECTRONES 6 51 INSTRUCTION SET S3CC11B FC11B JMP 1 Jump Register Format Description Operation Exceptions Notes 6 52 JPF JPT JMP JSR Ai The Jump Register instructions change the program flow by assigning the value of register Ai into PC JPF and JPT are conditional jumps that check the T bit to determine whether or not to jump to the target address JMP unconditionally jumps to the target JSR is an unconditional jump but saves the return address the immediately following instruction to JSR in the link register A14 At the end of each subroutine JMP A14 will change the program flow back to the original call site 12 11 15 14 13 10 9 8 7 6 5 4 3 2 1 0 pi lui s fr o Tolu ai M 00 JPF if T bit FALSE PC Ai M 01 JPT if T bit TRUE PC Ai M 10 JMP PC Ai M 11 JSR 14 2 PC Ai None There is no delay slot for these instructions Therefore when conditional branch JPF or JPT is taken the instruction in the pipeline which is fetched from PC 2 will be squashed In case of JMP and JSR always taken the following instruction fetched will be always squashed ELECTRONES S3CC11B FC11B INSTRUCTION SET JMP 2 Jump Immediate Format JPF JPT JMP JSR lt imm 22 gt Description The Jump Immediate instructions change the program flow by assigning the value of lt imm 22 gt into P
102. 8 7 6 5 4 3 0 Operation Rn Rn lt imm 16 gt T bit Rn lt imm 16 gt 0 if Rn R6 R7 20 21 Rn lt imm 16 gt 0 Exceptions None Notes This is a 2 word instruction where the 16 bit immediate follows the instruction word shown above Unlike 1 word instructions therefore fetching of this instruction takes 2 cycles 6 112 ELECTRONES S3CC11B FC11B PLL Phase Locked Loop PLL PHASE LOCKED LOOP OVERVIEW S3CC11B FC11B builds clock synthesizer for system clock generation which can operate external crystal for reference using internal phase locked loop PLL and voltage controlled oscillator VCO The input clock to the PLL block should be 2 048 MHz by the pre scaler System Clock Circuit The system clock circuit has the following component e External crystal oscillator 32 768 kHz e Phase comparator noise filter and frequency divider e Lock detector e PLL control circuit Control register PLLCON and PLL frequency divider data register PLLCON O PLLDATA 6 5 ber PLLDATA 1 0 PLLCON 1 PLLDATA 4 2 NOTES 1 By a system reset the PLL block is disabled and the fxin is selected for the fx with the PLLCON 0 0 It should be written to the PLLCON 1 0 with a 11 to use the PLL output frequency fout as system clock Ifthe PLL block is disabled with the PLLCON 0 0 a current through the PLL block should be under 1uA The PLL block should be disabled by software before enteri
103. ATA Oscillation Osc Start Stabilization Time up Time Operating lt Data Retention Mode gt Mode VDD Execution of STOP Instruction INT NOTE twarr is the same as 2048 x 32 x 1 fxx The value of 2048 which is selected for the clock source of the basic timer counter can be changed And then the value of tWAIT will be changed Figure 23 5 Stop Mode main Release Timing Initiated by Interrupts Oscillation Osc Start Stabilization Time up Time Y y t Stop Normal Operating Data Retention Mode Mode Execution of STOP Instruction twaAIT is the same as 2048 x 32 x 1 fxx The oscillator start up time is less then 100ms The value of 256 which is selected for the clock source of basic timer counter can be changed And then the value of twArT will be changed Figure 23 6 Stop Mode sub Release Timing Initiated by Interrupts ELECTRONK S ELECTRICAL DATA S3CC11B FC11B Table 23 5 Main Oscillator Characteristics 25 C to 85 C Vpp 2 0 V to 3 6 V Clock sParameter Test Condition Typ Ceramic Oscillator Stabilization occurs when Vpp is equal to the minimum oscillator voltage range Crystal Oscillator External XIN Clock Xy input high and low level width NOTES 1 Oscillation frequency and Xy input frequency data are for oscillator characteristics only 2 Stabilization time is the interval required for os
104. B INSTRUCTION SET SUB 1 Subtract Register Format Description Operation Exceptions Notes SUB Rn Ri The SUB Subtract Register instruction is used to subtract a 16 bit register value from another 16 bit register value 32 bit subtraction can be achieved by executing SBC instruction in pair with this instruction SUB subtracts the value of register Ri from the value of Rn and stores the result in register Rn The T bit and the V flag are updated based on the result 15 14 13 12 4 8 7 6 5 4 3 0 i olor m Pelo Rn Rn Ri T bit Carry from Rn Ri V flag Overflow from Rn Ri if Rn R6 R7 Z0 Z1 Rn Ri 0 None None ELECTRONES 6 99 INSTRUCTION SET S3CC11B FC11B SUB 2 Subtract Small Immediate Format Description Operation Exceptions Notes 6 100 SUB Rn lt imm 7 gt This form of SUB instruction is used to subtract a 7 bit immediate value from a register It subtracts the value of lt imm 7 gt from the value of register Rn and stores the result in register Rn The T bit and the V flag is updated based on the result 15 14 43 12 4 8 7 6 0 m mmm Rn 7 gt T bit Carry from Rn lt imm 7 gt V flag Overflow from Rn lt imm 7 gt if Rn R6 R7 Z0 Z1 Rn lt imm 7 gt 0 None lt imm 7 gt is an unsigned amount ELECTRONES S3CC11B FC11B INSTRUCTION SET SUB
105. B8 bits Format EFS T An Operation lt 8 An 7 An 7 0 This instruction forces the value of MSB 8 bits of 16 bit Accumulator An with byte sign bit of An register An 7 and stores the result back into the same Accumulator Flags C Reset Z Set if result is zero Reset if not V Reset N MSB of result Notes EFS8T instruction can be executed only when the T flag is set Otherwise No operation is performed Examples EFS8 A EFS8T D of Words 1 ELECTRONES 21 75 CalmMAC1616 EFZ EFZT Force to Zero MSB 8bits Format Operation Flags C Z V N Notes EFZ8T instruction can be executed only when the T flag is set Examples of Words 21 76 EFZ T An An lt 8 0 7 0 S3CC11B FC11B This instruction forces the value of MSB 16 bits of 16 bit Accumulator An with zero and stores the result back into the same Accumulator Reset Set if result is zero Reset if not Reset Reset Otherwise No operation is performed EFZ8 C EFZ8T B 1 ELECTRONES S3CC11B FC11B CalmMAC1616 EINCC EINCCT P Increment with Carry Format EINCC T An Operation An lt C This instruction adds 1 from the value of one of 16 bit Accumulator An if current carry flag is set and stores the result back into the same Accumulator Flags C Set if carry is generated Reset if not 2 Set if result is zero Reset if not V Set if overflow is generated
106. C JPF and JPT are conditional jumps that check the T bit to determine whether or not to jump to the target address JMP unconditionally jumps to the target JSR is an unconditional jum p but saves the return address the immediately following instruction to JSR in the link register A14 At the end of each subroutine JMP A14 will change the program flow back to the original call site 15 14 13 12 4 10 9 8 7 6 5 0 roro p ops ry moder mme Operation lt Mode gt 00 JPF if T bit FALSE PC lt imm 22 gt lt Mode gt 01 JPT if T bit TRUE PC lt imm 22 gt lt Mode gt 10 JMP PC lt imm 22 gt lt Mode gt 11 JSR 14 4 PC lt imm 22 gt Exceptions None Notes These are 2 word instructions where the 16 bit immediate lt imm 22 gt 15 0 follows the instruction word shown above As fetching of a 2 word instruction takes 2 cycles no later instructions will be in processor pipeline when the branch is taken thus no squashing ELECTRONES 6 53 INSTRUCTION SET S3CC11B FC11B LD 1 Load Register Format LD Rn Ri Description The LD Load Register instruction is used to transfer a register value to a register 15 14 13 12 11 8 7 6 5 4 3 0 m fifrfofif Operation Rn Ri R6 R7 20 21 Ri 0 Exceptions None Notes None 6 54 ELECTRONES S3CC11B FC11B INSTRUCTION SET LD 2 Load Register Format LD An Ai D
107. DMI Ai lt disp 16 gt 2 Rn None This is a 2 word instruction where the 16 bit immediate follows the instruction word shown above Unlike 1 word instructions therefore fetching of this instruction takes 2 cycles For memory transfer per word the byte address need to be aligned to be even Thus if Ai lt disp 16 gt is an odd number it will be made even by clearing the least significant bit ELECTRONES S3CC11B FC11B INSTRUCTION SET LDW 7 Load Word Register Indexed Format Description Operation Exceptions Notes LDW An G Ai Rj LDW Ai Rj An The LDW Load Word Register Indexed instruction is used to load 2 word from or to data memory at the location specified by the register Ai and the second register Rj which is an unsigned value 15 14 13 12 4 10 8 7 6 4 3 0 t 0 LDW Ai Rj En Rj Rn DM Ai Rj 2 M 1 LDW Rj An Rj En Rj 2 Rn None For memory transfer per word the byte address needs to be aligned to be even Thus if Ai Rj is an odd number it will be made even by clearing the least significant bit ELECTRONES 6 75 INSTRUCTION SET S3CC11B FC11B MUL Format Description Operation Exceptions Notes 6 76 MUL Mode Dn Di The instruction MUL performs 8x8 multiplication of the least significant byte of Dn and the
108. ENEGT C of Words 1 ELECTRONES 21 101 CalmMAC1616 S3CC11B FC11B ENMSK masking SG Format ENMSK SG imm 4 Operation SG 15 0 SG 15 0 amp mask pattern This instruction masks MSB n bit n 16 imm 4 of SG 15 0 register and stores back the result into the SG 15 0 register Flags Z Set if result is zero Reset if not VS Reset N Reset Notes Examples ENMSK SG 3h of Words 1 21 102 ELECTRONES S3CC11B FC11B ENOP No Operation Format ENOP Operation No operation Flags Notes _ Examples ENOP of Words 1 ELECTRONES CalmMAC1616 21 103 CalmMAC1616 ER Bit Reset Format ER bs Operation Specified bit in bs field lt 0 This instruction sets the specified bit in bs field to O Flags _ Notes _ Examples ER OP ER ME3 of Words 1 21 104 S3CC11B FC11B ELECTRONES S3CC11B FC11B CalmMAC1616 ERESR Restoring Remainder Format ERESR Mi P Operation if NQ 0 Adder output lt MAi 0 else Adder output lt MAi 2 P This In struction adds two times of the P register and one of the MAi accumulator when NQ bit of register is set Else performs no operation It calculates true remainder value of non restoring division Flags VMi Set if result is overflowed to guard bits Reset if not MV Set if guard bit is overflowed Unchanged if not Notes VMi denotes for VMO or VM1 according to Mi Examples ERESR MA1 P
109. ERNAL CODEC OVERVIEW 8 16 bit serial interface for external codec CSIO can interface with voice CODEC 10t The components of each CSIO function block are 8 bit control register CSIOCON 16 bit Data buffer CSIODATAH CSIODATAL Serial data pins CDX CDR Frame sync pin CFS External clock input out CCLK The CSIO module can transmit or receive 16 bit serial data configured by its corresponding control register settings The CSIO module operates with master mode only PROGRAMMING PROCEDURE To program the CSIO modules follow these basic steps 1 Load an 8 bit value to the CSIOCON control register to properly configure the CSIO module 2 The CSIO interrupt request is automatically generated at the end of 16 bit shifting 3 Inthe CSIO interrupt routine read write ADC DAC data 4 Repeat steps 3 to 4 NOTE Voice codec MC145483DW ELECTRONES 20 1 8 16 BIT SERIAL INTERFACE FOR EXTERNAL CODEC S3CC11B FC11B CSIO CONTROL REGISTER CSIOCON The control register for CSIO interface module CSIOCON is located at 4E It has the control settings for the CSIO module 8 16 serial interface for external codec Shift clock selection Short long frame sync type selection Edge selection for shift operation Shift operation transmit receive enable 20 2 ELEGTRONK 5 S3CC11B FC11B 8 16 BIT SERIAL INTERFACEFOR EXTERNAL CODEC CSIOCON sio control Register for Exte
110. ES S3CC11B FC11B INSTRUCTION SET LDB 2 Load Byte Register Large Disp Format Description Operation Exceptions Notes LDB Dn Ai lt disp 16 gt LDB An lt disp 16 gt Di The LDB Load Byte Register Large Displacement instruction is used to load a byte from or to data memory at the location specified by the register Ai and a 16 bit displacement 15 14 18 12 11 10 8 7 6 5 4 3 2 0 mon Aon M 0 LDB Dn Ai lt disp 16 gt Dn DM Ai lt disp 16 gt M 1 LDB An lt disp 16 gt Di DM An lt disp 16 gt Di None This is a 2 word instruction where the 16 bit immediate follows the instruction word shown above Unlike 1 word instructions therefore fetching of this instruction takes 2 cycles ELECTRONES 6 61 INSTRUCTION SET S3CC11B FC11B LDB 3 Load Byte Register Indexed Format Description Operation Exceptions Notes 6 62 LDB Dn LDB G An Rm Di The LDB Load Byte Register Indexed instruction is used to load a byte from or to data memory at the location specified by the register Ai or An and the second register Rj or Rm 15 14 18 12 11 10 6 7 2 0 LDB Dn Ai Rj Dn DMI Ai Rj M 1 LDB Di DM An Rm Di None None ELECTRONES S3CC11B FC11B INSTRUCTION SET LDB 4 Load Byte to R0 Register Disp Forma
111. ES S3CC11B FC11B CalmMAC1616 EMIN 2 Minimum Value Load w One Parallel Load Format EMIN Ai Ci Ci rps Operation if Ci lt Ai Ai Ci Ci rps RP3 lt previous address with RPi register This instruction conditionally loads op value to the one of 16 bit Accumulator Ai and latches the previous address value to the RP3 pointer when op is less than or equal to Ai Otherwise no operation is performed This instruction also stores source operand from data memory to the destination accumulator the same accumulator register Ci RP3 register can not be used as a pointer register of parallel move part Flags C Set if carry is generated Reset if not 2 Set if result is zero Reset if not V Set if overflow is generated Reset if not N Exclusive OR of V and MSB of result Refer to Chapter 2 for more detailed explanation about this convention Notes Flags are generated from the operation Ci Ai Examples EMIN B D D RPO S1 of Words 1 ELECTRONES 21 91 CalmMAC1616 S3CC11B FC11B EMLD 1 _ Multiply and Load Format EMLD Mi XiYi Operation lt P P lt Xi Yi This instruction loads the P register value to the values of 36 bit Multiplier Accumulator MAi At the same time multiplier multiplies Xi register value and Yi register value and stores the result to the P register Flags VMi Set if result is overflowed to guard bits Reset if not MV Set if guard bit is over
112. External P0 1 IRR 10 Interrupt Enable Bit Disable interrupt request Enable interrupt request 41 External P0 0 IRR 9 Interrupt Enable Bit 0 Disable interrupt request 1 Enable interrupt request 0 Serial I O IRR 8 Interrupt Enable Bit Disable interrupt request 1 Enable interrupt request 4 6 ELECTRONES S3CC11B FC11B EXCEP TIONS IMRL Interrupt Mask Register Low 3F0007H Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R R W R W R W Addressing Mode Register addressing mode only 7 Watch Timer IRR 7 Interrupt Enable Bit Disable Interrupt request 1 Enable Interrupt request 6 SIO for External Codec IRR 6 Interrupt Enable Bit Disable Interrupt request 1 Enable Interrupt request 5 CODEC IRR 5 Interrupt Enable Bit Disable Interrupt request Enable Interrupt request 4 Basic Timer Overflow IRR 4 Interrupt Enable Bit isable interrupt request nable interrupt request 3 Timer B Match IRR 3 Interrupt Enable Bit Disable interrupt request 1 Enable interrupt request 2 Timer 1 A Match IRR 2 Interrupt Enable Bit isable interrupt request x nable interrupt request 1 Timer 0 Overflow IRR 1 Interrupt Enable Bit Disable interrupt request fe Enable interrupt request 0 Timer 0 Match or Capture IRR 0 Interrupt Enable Bit Disable interrupt request Enable interrupt request LI ELECTRONES EXCEPTIONS S3CC11B FC11B INTERRUPT PRO
113. Format EABS T An Operation An An This instruction calculates the absolute value of one of 16 bit Accumulator An and stores the result back into the same Accumulator Flags C Set if carry is generated Reset if not Z Set if result is zero Reset if not V Set if overflow is generated Reset if not N Exclusive OR of V and MSB of result Refer to Chapter 2 for more detailed explanation about this convention Notes EABST instruction can be executed only when the T flag is set Otherwise No operation is performed Examples EABS A EABST C of Words 1 ELECTRONES 21 61 CalmMAC1616 S3CC11B FC11B EADD 0 Add Accumulator Format EADD An op op simm 5 simm 16 Am mg mgx Operation An An op This instruction adds the values of one of 16 bit Accum ulators An and op together and stores the result back into the same Accumulator If op is immediate value it is first right adjusted and sign extended to 16 bit value If op is 16 bit register it is zero extended Flags C Set if carry is generated Reset if not Z Set if result is zero Reset if not V Set if overflow is generated Reset if not N Exclusive OR of V and MSB of result Refer to Chapter 2 for more detailed explanation about this convention Notes None Example s EADD A 0486h EADDC A EADD A RPO of Words 1 2 when op is simm 16 21 62 ELECTRONES S3CC11B FC11B EADD Format Ope
114. I O Timing in Transmit Receive Mode Tx at falling SIOCON 4 0 nSCK SI SO Transmit IRQS k Complete LEN Set SIOCON 3 Figure 14 4 Serial I O Timing in Transmit Receive Mode Tx at rising SIOCON 4 1 14 4 ELECTRONES S3CC11B FC11B SSFDC Solid State Floppy Disk Card SSFDC SOLID STATE FLOPPY DISK CARD OVERVIEW S3CC11B FC11B build interface logic for SmartMedia card called as SSFDC solid state floppy disk card The SSFDC interface includes the use of simple hardware together with software to generate a basic control signal or ECC for SmartMedia The built in SSFDC interface logic consists of ECC block and the read write strobe signal generation block The high speed RISC CPU core CalmRISC16 supports high speed control for other strobe signal generation and detection Therefore ALE CLE CE and etc signal should be operated by CPU instruction This mechanism provides the balanced cost and power consumption without the de graduation of SSFDC access speed Physical format is necessary to maintain wide compatibility SmartMedia has a standard physical format System makers and controller manufacturers are requested to conform their products to such specifications For logical format SmartMedia M employs a DOS format on top of physical format See Card Standard Vol 7 and other references for more information With all SmartMedia products physical and logical formatting has been completed at time of s
115. IRQ Return from Interrupt Format RET_IRQ Description The RET IRQ Return from Interrupt instruction is used to finish an IRQ handler and resume the normal program execution When this instruction is executed SSR IRQ saved SR is restored into SR and the program control transfers to SPCH IRQ SPCL IRQ Operation SR SSR IRQ SPCH IRQ SPCL Exceptions None Notes Interrupt is requested through the core signals nIRQ When the request is acknowledged SR and current PC are saved in the designated registers namely SSR_IRQ and SPCH_FIQ SPCL_IRQ assigned for IRQ processing Such bits in SR as IE and TE are cleared and PM is set ELECTRONES 6 87 INSTRUCTION SET S3CC11B FC11B RET SWI Return from Software Interrupt Format RET SWI Description The RET SWI Return from Software Interrupt instruction is used to finish a SWI handler and resume the normal program execution When this instruction is executed SSR FIQ saved SR is restored into SR and the program control transfers to the address A14 link register Operation SR SSR SWI PC A14 Exceptions None Notes Software interrupt is initiated by executing a SWI instruction from applications When SWI instruction is executed SR and current PC are saved in the designated registers namely SSR_SWI and A14 assigned for SWI processing 6 88 ELECTRONES S3CC11B FC11B INSTRUCTION SET RL Rotate Left Format Description
116. Identifier _ 7 6 s 4 3 2 o 7 0 0 0 0 0 0 0 0 Reset Value Read Write R W R W R W R W R W R W R W R W 7 6 P5 3 SEG10 Configuration Bits Schmitt trigger input Push pull output 1 N channel open drain output Alternative function SEG10 output 5 4 3 2 Schmitt trigger input Push pull output 1 o N channel open drain output Alternative function SEG8 output 1 0 Schmitt trigger input r oNemmeonddnou 9 18 ELECTRONES S3CC11B FC11B VO PORTS P5PUR Port 5 Pull Up Resistors Enable Register 3F0036H Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 4 P5 7 s Pull up Resistor Enable Bit O Disable pull up resistor 1 Enable pull up resistor 6 P5 6 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 5 P5 5 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 4 P5 4 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 3 P5 3 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 2 P5 2 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 41 P5 1 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 0 P5 0 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor ELECTRONES 9 1 PORTS S3CC11B FC11B P6CON Port 6 C
117. If the instruction requires a data memory write operation DO bit 11 to bit 8 or D1 bit 15 to bit 12 field of SDi register is selected as an index value Destination Index 1 Destination Index 0 Source Index 1 Source Index 0 Figure 21 8 Pointer Register and Index Register Configuration ELECTRONES 21 15 CalmMAC1616 S3CC11B FC11B Modulo Modifier The two modulo arithmetic units X Y Modulo Logic can update one or two address registers within one instruction cycle They are capable of performing modulo calculations of up to 2 21024 Each register can be set independently to be affected or unaffected by the modulo calculation using the ME bits in the MSRO register Modulo setting values are stored in 13 least significant bits of modulo configuration registers MCO and MC1 respectively The bits 12 to bit 10 of MCO and MC1 register determines maximum modulo size from 8 to 1024 and the bits 9 to bit 0 of modulo control register defines upper boundary of modulo calculation in the current modulo size The lower boundary of modulo calculation is automatically defined by modulo size itself Refer to Figure 21 9 For proper modulo calculation the following constraints must be satisfied M modulo size S step size 1 Only the p LSBs of RPi can be modified during modulo operation where p is the minimal integer that satisfies 2P 2 M RPi should be initiated with a number whose p LSBs are less than M 2 gt 5 The modulo mo
118. LECTRONES S3CC11B FC11B CalmMAC1616 Multiplier The Multiplier unit consists of a 16 by 16 to 32 bit parallel 2 s complement single cycle non pipelined multiplier 4 16 bit input registers X0 X1 Y0 and Y1 a 32 bit output product register P and output shifter amp saturation logic The multiplier can perform 4 quadrant multiplication signed by signed unsigned by signed signed by unsigned and unsigned by unsigned Together with 36 bit adder in MAU the CalmMAC16 can perform a single cycle Multiply Accumulate MAC operation The multiplier only operates when multiply instruction is executed The P register is not updated and the multiplier is not operates after a change in the input registers This scheme reduces power consumption in multiplier PSH1 bit of register indicates whether multiplier output is shifted 1 bit to the left or not If PSH1 bit is set multiplier output is shifted 1 bit to the left This operation can be used in the signed fractional multiplication USM bit of MSR1 register indicates whether multiplier input register is signed or unsigned When USM bit is set X1 and Y1 register is interpreted as an unsigned operand For example if X1 and YO register is selected as multiplier input register unsigned by signed multiplication is performed If X1 and Y1 register is selected unsigned by unsigned multiplication is performed The X or Y register can be read or written via the XB bus and Y register can be wri
119. M5 P9 2 COM4 P9 3 COM3 P9 4 COM2 P9 5 COM1 P9 6 COMO P9 7 ELEGTRONK 5 S3CC11B FC11B LCD CONTROLLER DRIVER LCD DISPLAY REGISTERS 3F0080 3F00A3H are used as LCD data memory These locations can be addressed by 1 bit or 8 bit instructions If the bit value of a display segment is 1 the LCD display is turned on If the bit value is 0 the display is turned off Display RAM data are sent out through the segment pins SEGO SEG35 using the direct memory access DMA method that is synchronized with the 4 cp signal RAM addresses in this location that are not used for LCD display can be allocated to general purpose use 3F0080H 3F0081H 3F0082H 3F0083H 3F0084H 3F0085H 3F0086H 3F0087H 3F0088H 3F0089H 3F009DH 3F009EH 3F009FH SF00A0H 3F00A2H 3F00A3H o N Figure 18 3 LCD Display Register Organization LCD CONTROL REGISTER LCON The LCD control register LCON is used to turn the LCD display on and off LCD frame frequency and control the flow of the current to the dividing resistors in the LCD circuit After a RESET all LCON values are cleared to 0 This turns the LCD display off and stops the flow of the current to the dividing resistors ELECTRONES 18 3 LCD CONTROLLER DRIVER S3CC11B FC11B LCON control Register 3F0072H Reset Value 0 0 _ _ 0 0 0 0 Read Write R W R W R W R W R W R W 7 6 LCD Display Control Bits sapna 0 1 Normal
120. N to 00H This sets Timer 0 to normal interval timer mode selects an input clock frequency of 1 5 4096 and disables Timer 0 counting operation You can clear the Timer 0 counter at any time during normal operation by writing a 1 to TOCON 3 ELECTRONK S 12 3 8 BIT TIMER 0 S3CC11B FC11B BLOCK DIAGRAM TOCON 7 5 Data Bus TOCON 0 Overflow INT 1 14 14096 1 256 8 Bit Up Counter R Clear TOCON 1 116 TOCNT Read Only 1 1 Match Match or Capture INT TOCON 3 2 Match Signal TOCLR TOOVF Timer 0 Data Register Data Bus Figure 12 1 Timer 0 Functional Block Diagram 12 4 ELECTRONES S3CC11B FC11B 8 BIT TIMER 0 Timer 0 Control Register 3F0042H Bit Identifier Reset Value Read Write 7 5 3 2 ELECTRONES 7 0 0 0 _ 0 0 0 0 R W R W R W _ R W R W R W R W Timer 0 Clock Selection Bits ofofo fs J ofo jees oppo pe 1 0 External clock at TOCLK Other values Not used for S3FC11B Bit 4 fxin 128 Timer 0 Operating Mode Selection Bits Interval mode 1 Capture mode capture on rising edge counter running OVF i 1 Capture mode capture on falling edge counter running OVF PWM mode OVF interrupt can occur Timer 0 Counter Clear Bit EN No effect Clear the timer 0 counter when write Timer 0 Counter Enable Bit 0 Disable counting operation 1
121. Notes INSTRUCTION SET OR Small Immediate OR RO lt imm 8 gt The OR OR Small Immediate instruction is used to perform bitwise OR operation on two values in register RO and lt imm 8 gt The result is stored in register RO The T bit is updated based on the result 15 14 13 12 4 10 9 8 7 0 1 mm RO RO lt imm 8 gt T bit RO lt imm 8 gt 7 0 0 None The register used in this operation is fixed to RO Therefore the operand should be placed in RO before this instruction executes lt imm 8 gt is zero extended to a 16 bit value before operation ELECTRONES 6 79 INSTRUCTION SET S3CC11B FC11B OR 3 Format Description Operation Exceptions Notes 6 80 OR Large Immediate OR Rn lt imm 16 gt This type of OR instruction is used to perform bitwise OR operation on two values in register Rn and lt imm 16 gt The result is stored in register R0 The T bit is updated based on the result 15 14 13 12 4 10 9 8 7 6 5 4 3 0 Rn Rn lt imm 16 gt T bit Rn lt imm 16 gt 0 R6 R7 20 21 Rn lt imm 16 gt 0 None This is a 2 word instruction where the 16 bit immediate follows the instruction word shown above Unlike 1 word instructions therefore fetching of this instruction takes 2 cycles ELECTRONES S3CC11B FC11B INSTRUCTION SET POP 1 Load Register from Stack Format Description O
122. P 1414 0 08 no X 5 PRE 0 07 gt 0 20 0 03 0 50 0 08 MAX 1 00 0 05 0 15 REEL 1 00 0 05 1 20 MAX NOTE Dimensions are in millimeters Figure 24 2 100 TOFP 1414 Package Dimensions ELECTRONES 24 3 MECHANICAL DATA S3CC11B FC11B NOTES 24 4 ELECTRONES S3CC11B FC11B S3FC11B FLASH MCU S3FC11B FLASH MCU OVERVIEW The S3FC11B single chip CMOS microcontroller is the FLASH ROM version of the S3CC11B microcontroller It has an on chip FLASH ROM instead of masked ROM The FLASH ROM is accessed by serial data formats The S3FC11B is fully compatible with S3CC1 1B both in function and in electrical characteristics Because of its simple programming requirements the S3FC1 1B is ideal for use as an evaluation for the S3CC11B ELECTRONES 25 1 S3FC11B FLASH MCU S3CC11B FC11B 99 J P0 6 SO 98 FI P0 7 SCK 96 1 9 7 95 L3 COM1 P9 6 88 FI SEG35 P8 4 87 FI SEG34 P8 3 86 1 SEG33 P8 2 85 L3 SEG32 P8 1 84 FI SEG31 P8 0 83 Fa SEG30 P7 7 82 SEG29 P7 6 81 1 SEG28 P7 5 94 COM2 P9 5 93 COM3 P9 4 92 COM4 P9 3 91 1 COM5 P9 2 90 I COM6 P9 1 89 Fa COM7 P9 0 100 1 PO 5 SI VDD3 Vss3 VREFOUT ADGAIN ADINN ADINP AVDD2 SEG27 P7 4 SEG26 P7 3 SEG25 P7 2 SEG24 P7 1 SEG23 P7 0 SEG22 P6 7 SEG21 P6 6 AVss2 SEG20 P6 5 DAOUT SEG19 P6 4 LPF SEG18 P6 3 1 SEG17 P6 2 AVS
123. P5 S3CC11B FC11B ELECTRONES S3CC11B FC11B Open Drain Data Output Disable SEG Output Disable External Interrupt Input ELECTRONES Pull up Resistor ep Figure 1 13 Pin Circuit Type 10 P4 4 P4 7 PRODUCT OVERVIEW Resistor Enable PRODUCT OVERVIEW S3CC11B FC11B NOTES 1 14 ELECTRONES S3CC11B FC11B ADDRESS SPACE ADDRESS SPACE OVERVIEW CalmRISC16 has 21 bit program address lines PA 20 0 equivalent to PC 21 1 which supports up to 32K word of program memory The 32K word program memory space is divided into 24K word internal program memory and 8K word Data Memory Data ROM area CalmRISC16 also has 22 bit data memory address lines DA 21 0 which supports up to 10K byte Memory configuration in CalmRISC16 side Data Memory 10K byte internal data memory Program Memory 24K word internal program memory 8K word data memory Data ROM YROM Memory configuration in CalmMAC24 side Data Memory XMemory area 3K word internal memory 6K byte Y Memory area 2K word internal memory 4K byte Program Memory 24K word internal program memory 8K word data memory Data ROM YROM ELECTRONES 2 1 ADDRESS SPACE S3CC11B FC11B PROGRAM MEMORY Program memory configuration is shown in Figure 2 1 The total size of ROM Program ROM Data ROM is the 32K x 16 bits The program ROM s address is 0000H BFFEH and the data ROM s address is COOOH FFFEH 3FFFFEH
124. R register is sign extended instead of being filled with zeros ESFTD instruction is provided for double precision shift operation With this instruction one can shift 32 bit number stored in two registers Unlike standard logical and arithmetic shift this instruction only updates the SG register with the values that is ORed previous SG register value and shifted out result from barrel shifter The following codes are examples of double precision shift operation Double Precision Left SG SR lt B A SA ESFT A SA Lower Part Shift ESFID B SA Upper Part Shift Double Precision Right SR SG lt B A gt gt SA ESFT B SA Upper Part Shift ESFT A SA Lower Part Shift 21 30 ELECTRONES S3CC11B FC11B CalmMAC1616 ESFT Logical Shift Left Shift Operations Right Shift Operations Figure 21 17 Various Barrel Shifter Instruction Operation ELECTRONES 21 31 CalmMAC1616 S3CC11B FC11B ESFTL instruction is used for bit stream manipulation It links the previously shifted data with the current data The operation of this instruction is the same as logical shift instruction except that the shifted out result is ORed with previous SG register values This ORing process makes it possible to concatenate the previous data and the current data This instruction is valid only when the magnitude of shift amount is greater than 16 The linking process example is as follows Left Link SG SR lt B lt lt A
125. RITY REGISTERS IPRH 3F0008H IPRL 3F0009H xx000 X0 gt Y0 gt Z0 gt X1 gt Y1 gt Z1 x0100 X0 gt YO gt X1 gt 20 gt Y1 gt Z1 01100 gt YO gt X1 gt Y1 gt 20 gt Z1 11100 gt YO gt X1 gt Y1 gt 21 gt 20 0010 gt X1 gt YO gt 20 gt Y1 gt Z1 00110 gt X1 gt Y1 gt YO gt 20 gt Z1 10110 X0 X1 Y1 YO 2Z1 ZO 01010 gt X1 gt YO gt Y1 gt 20 gt Z1 11010 X0 gt X1 gt YO gt Y1 gt Z1 gt Z0 x1110 X0 gt X1 gt Y1 gt Z1 gt YO gt 20 Xx001 X1 gt Y1 gt Z1 gt gt YO gt 20 x0101 X1 gt Y1 gt X0 gt Z1 gt YO gt ZO 01101 X1 gt Y1 gt X0 gt YO gt Z1 gt 20 11101 X1 gt Y1 gt gt YO 20 gt Z1 x0011 X1 gt X0 gt Y1 gt Z1 gt YO gt 20 00111 X1 gt X0 gt YO gt Y1 gt Z1 gt ZO 10111 X1 gt X0 gt YO gt Y1 gt 20 gt Z1 01011 X1 gt X0 gt Y1 gt YO gt Z1 gt ZO 11011 X1 gt gt Y1 gt YO 20 gt Z1 x1111 X1 gt gt YO gt 20 gt Y1 gt Z1 Gjroup Priority 76 5 000 A gt B gt C 001 B gt C gt A 010 A gt B gt C 011 B gt A gt C 00 C gt A gt B 01 C gt B gt A 10 A gt C gt B 1 1 1 1 111 A gt B gt C 1 1 1 1 I IPRL 000009H Group A 0 IRR0 gt IRR1 1 IRR1 gt IRR0 Group B 0 IRR2 gt IRR3 IRR4 1 IRR3 IRR4 gt IRR2 Subgroup B 0 IRR3 gt IRR4 1 IRR4 gt IRR3 Group C
126. Reserved JPF adr 22 adr 22 JMP adr 22 JSR adr 22 LDC Rn Ai Reserved LD Dn Ei LD En Di CMP EQ An Ai LD An Ai LDW Rn Ai disp 16 LDW An disp 16 Ri LDB Dn Ai disp 16 LDB An disp 16 Di LDW An Ai disp 16 LDW QY An disp 16 Ai GE Dn imm 6 ADD An imm 5 SUB An imm 5 an ELECTRONS INSTRUCTION SET pepe asss E gt 3 Ai 6 15 INSTRUCTION SET S3CC11B FC11B Table 6 1 CalmRISC16 Instruction Set Map Continued 15 8 7 0 Cup mene ap mm ppp _ epe KIKIKI m mu won e s o e m epp gt Por mm am mm ne Por ant Am frfefvfofif am ride m mum m mm epp uss mum fof am BSRD eoffset 13 1 Eoffset 13 BRA fee eoffset 8 0 0 0 0 0 EC Eoffset 8 Reserved awe seres BNZD HeofsetS Jifrfofofo i ofo ofi Eoffset 8 Eoffset 8 E Reserved Cid At BRAD ____ Eoffset 11 eoffset 11
127. Rn imm 6 The immediate value is zero extended to 16 bit value The instruction is for signed compare T flag is updated as the result of the instruction ADD SUB An imm 5 The immediate value is zero extended to 22 bit value No flag is updated 6 2 ELECTRONES S3CC11B FC11B INSTRUCTION SET ALUOP REGISTER REGISTER ADD SUB ADC SBC AND OR XOR TST CMP CMPU Rn Ri The instructions perform an ALU operation of which source operands are a pair of 16 bit general registers In the instructions TST CMP CMPU only T flag is updated as the result In the instructions ADD ADC SUB SBC the value of T flag is the carry of the operations and the value of V flag indicates whether overflow or underflow occurs In the instructions AND OR XOR TST the value of T flag indicates whether the result is zero CMP GT GE EQ Rn Ri instructions are for signed comparison and CMPU GT GE Rn Ri instructions are for unsigned comparison ADD SUB An Ri 16 bit general register Ri is zero extended to 22 bit value The result is saved in the 22 bit register An No flag update OCCUIS CMP EQ An Ai The instruction compares two 22 bit registers MUL SS SU US UU Ri The general registers Rn and Ri can be one of RO to R7 The instruction multiplies the lower byte of Rn and the lower byte of Ri and the 16 bit result is saved in Rn The optional field SS SU US and UU indicates whether the source operands are signed value or unsigned value
128. Rn Ei LD En Ri In the instruction LD Rn Ei the 6 bit data in Ei is zero extended to 16 bit data and then transferred to Rn When the destination register is R6 R7 the zero flag Z0 Z1 is updated In the instruction LD En Ri least significant 6 bits of Ri are transferred to En Rn Ri is one of the registers from RO to R7 LD RO SPR LD SPR RO SPR SR SPCL_FIQ SPCH_FIQ SSR_FIQ SPCL IRQ SPCH_IRQ SSR_IRQ SSR SWI The instructions transfer data between SPR Special Purpose Registers and RO No flag update occurs except the case that the destination register is SR LD An PC The instruction moves the value of PC 4 to An 6 4 ELECTRONES S3CC11B FC11B INSTRUCTION SET LD REGISTER DATA MEMORY LD DATA MEMORY REGISTER LDW Rn SP edisp 9 LDW SP edisp 9 Rn The instructions transfer 16 bit data between a general register Rn and the memory location at the address of SP edisp 9 Note SP is another name of A15 edisp 9 is an even positive displacement from 0 to 510 edisp 9 is encoded into an 8 bit displacement value in the instruction map because the LSB is always 0 When the address is calculated the 8 bit displacement field is shifted to the left by one bit and then the result is added to the value of SP Even if the address might be specified as odd in assembly mnemonic the LSB of the address should be truncated to zero for word alignment LDW Rn Ai edisp 5 LDW Ai edisp 5 Rn The instructions tr
129. Rw Locations 3F0025H 3F0027H are not mapped Port 2 control register low P2CONL 3F0029H Port 2 pull up resistors enable register P2PUR 3F002AH Location 3F002BH is not mapped 077 5 2 ELECTRONES S3CC11B FC11B MEMORY MAP Table 5 1 Registers Continued a Register Name Mnemonic Decimal Hex Port 3 pull up resistors enable register 00H Location 3F002FH is not mapped Port 4 control register high Port 4 control register low Port 4 pull up resistors enable register Port 4 interrupt control register Port 5 control register high Port 5 control register low P5CONL 3F0035H Port 5 pull up resistors enable register 0 Location 3F0037H is not mapped Port 6 control register P6CON 3F0038H Location 3F0039H is not mapped Port 7 control register P7CON Location is not mapped Port 8 control register P8CON 3F003CH Location 3F003DH is not mapped Port 9 control register P9CON 3F003EH Location 3F003FH is not mapped Timer 0 counter register TOCNT 3F0040H R Timer 0 data register TODATA 3F0041H Timer 0 control register TOCON 3F0042H 00H R W Location 3F0043H is not mapped TACNT 3F0044H R W R S R R W R W R W R W R W R W 00H OH x Timer B counter register TBCNT 3F0045H 0 Locations 3F004AH 3F004BH are not mapped 0 CSIODATAL 0 RW CSIOCON 0 RW 00H RW R RW R W R W R W R W 0 0 F F 0 0H 0H FH FH
130. S gt Register Specifier 0000 SPCL FIQ 0001 SPCH FIQ 0010 SSR FIQ 0100 SPCL IRQ 0101 SPCH IRQ 0110 SSR IRQ 1010 SSR SWI None None ELECTRONES 6 67 INSTRUCTION SET S3CC11B FC11B LD SR Load status Register Format LD R0 SR LD SR R0 Description LD SR Load Status Register instruction is used to transfer a value to and from SR Only register is used for this operation Operation M 0 LD RO SR RO SR M 1 LD SR RO SR RO Exceptions None Notes None 6 68 ELECTRONES S3CC11B FC11B INSTRUCTION SET LDW 1 Load Word Stack Disp Format Description Operation Exceptions Notes LDW Rn SP lt edisp 9 gt LDW SP lt edisp 9 gt Ri The LDW Load Word Stack Displacement instruction is used to load a word from or to data memory at the location specified by the SP register or A15 and an even 9 bit displacement lt edisp 9 gt from 0 to 510 is encoded into 8 bit displacement by dropping the least significant bit 15 14 13 12 1l 8 7 0 o u men 99 M 0 LDW Rn SP lt edisp 9 gt Rn DM SP lt edisp 9 gt M 1 LDW SP lt edisp 9 gt Ri DMI SP lt edisp 9 gt Ri None For memory transfer per word the byte address need to be aligned to be even Thus if SP lt edisp 9 gt is an odd number it will be made even by clearing the least significant bit lt edisp 9 gt can denote an e
131. S1 SEG16 P6 1 P0 4 SDAT SEG15 P6 0 O1 VDD1 VDD1 551 551 552 XOUT 100 QFP 1420C SEG13 P5 6 XIN SEG12 5 5 TEST VPP SEG11 P5 4 XTin SEG10 P5 3 XTout SEG9 P5 2 nRESET nRESET SEG8 P5 1 PO 2 INT2 SEG7 P5 0 PO 1 INT1 SEG6 P4 7 INT7 PO0 0 INTO SEG5 P4 6 INT6 P1 0 1 00 SEG4 P4 5 INT5 1 1 1 01 SEG3 P4 4 INT4 P1 2 02 SEG2 P4 3 CCLK P1 3 1 03 SEG1 P4 2 CFS P1 4 1 04 SEGO P4 1 CDX PO 3 INT3 SCLK S3FC11B SEG14 P5 7 P2 0 nWE C 34 P2 1 nRE C 35 P2 2 NP 36 P2 3 37 P2 4 ALE C 38 P2 5 CLE 39 P2 6 nCEO 40 P2 7 nCE1 41 P3 0 ADO C 42 P3 1 AD1 C 43 P3 2 AD2 C 44 P3 3 AD3 TOCLK Cj 45 P3 4 TOPWM Cj 46 P3 6 TAOUT O 48 P3 7 TBOUT Cj 49 P4 0 CDR I 50 P3 5 BUZ T1CLK C 47 Figure 25 1 S3FC11B Pin Assignments 100 QFP 1420C 25 2 ELECTRONES S3CC11B FC11B S3FC11B FLASH MCU 98 PO 5 SI 97 3 P0 6 SO 96 PO0 7 SCK 94 I 9 7 93 I 1 9 6 92 2 9 5 913 COM3 P9 4 903 COM4 P9 3 897 COM5 P9 2 885 6 9 1 87 5 COM7 P9 0 86 SEG35 P8 4 8517 SEG34 P8 3 841 SEG33 P8 2 8317 SEG32 P8 1 8217 SEG31 P8 0 81179 SEG30 P7 7 80 SEG29 P7 6 7957 SEG28 P7 5 78 SEG27 P7 4 77 L3 SEG26 P7 3 76 3 SEG25 P7 2 100 5 Vss3 VREFOUT ADGAIN ADININ ADINP AV Db2 AVss2 75H SEG24 P7 1 74E3 SEG23 P7 0 7315 SEG22 P6 7 723 SEG21 P6 6 71E3 SEG20 P6 5 703 SEG19 P6 4 DAOUT 69 SEG18 P6 3 sil 68 SEG17 P6 2 AVDD
132. S3CC11B FC11B CalmRISC 16 Bit CMOS MICROCONTROLLER USER S MANUAL Revision 0 ELECTRONICS Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages S3CC11B FC11B 16 Bit CMOS Microcontroller User s Manual Revision 0 Publication Number 20 S3 CC11B FC11B 102004 2004 Samsung Electronics Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by the cu
133. SBC 1 Subtract with Carry Register Format Description Operation Exceptions Notes 6 92 SBC Rn Ri The SBC Subtract with Carry instruction is used to synthesize 32 bit subtraction If register pairs RO R1 and R2 R3 hold 32 bit values RO and R2 hold the least significant word the following instructions leave the 32 bit result in RO R1 SUB RO R2 SBC Ri SBC subtracts the value of register Ri and the value of the Carry flag stored in the T bit from the value of register Rn and stores the result in register Rn The T bit and the V flag are updated based on the result 15 14 13 12 4 8 7 6 5 4 3 0 ERE m Jofjofiji Rn Rn Ri T bit T bit Carry from Rn Ri T bit V flag Overflow from Rn Ri T bit R6 R7 20 71 Ri T 0 None None ELECTRONES S3CC11B FC11B INSTRUCTION SET SBC 2 Subtract with Carry Immediate Format SBC Rn lt imm 16 gt Description The SBC Subtract with Carry immediate instruction is used to synthesize 32 bit subtraction with an immediate operand If register pair RO R1 holds a 32 bit value RO holds the least significant word the following instructions leave the 32 bit subtraction result with 34157856h in RO R1 SUB RO 7856h SBC Ri 3415h SBC subtracts the value of lt imm 16 gt and the value of the Carry flag stored in the T bit from the value of Rn and stores the result in regis
134. SECO MEE AE med EDIVQ Division Step VMi NQ ERESR Mi lt Mi 2P if NQ 1 21 58 ELECTRONES S3CC11B FC11B CalmMAC1616 Quick Reference Continued ESLA ESRA C ESAT ERND ESLA T An ESRA T ESLA8 T ESRA8 T ESLC T ESRC T EINCC T EDECC T EABS T ENEG T EFS8 T EFZ8 T EEXP T EEXPC T if T 1 instruction is executed Fenton Fag VM Meo MesatuatedM _ Mic __ i i i i i 1 lt 1 lt lt 1 arithmetic V N Z C 1 lt 1 gt gt 1 arithmetic 1 lt 1 lt lt 8 arithmetic 1 lt 1 gt gt 8 arithmetic VM VM VM VM VM ELECTRONES 21 59 CalmMAC1616 S3CC11B FC11B INSTRUCTION SET GLOSSARY This chapter describes the CalmMAC16 instruction set with the details of each instruction The following notations are used for the description Notation interpretation Operand N can be omitted if there is only one operand Typically opi is the destination and source operand and op2 is a source operand N M Mth power of N It is further noted that only the affected flags are described in the tables in this section That is if a flag is not affected by an operation it is NOT specified 21 60 ELECTRONES S3CC11B FC11B CalmMAC1616 EABS EABST Absolute
135. SEG5 COMO ov VLC5 VLC3 VLC4 VLC2 VLC1 Figure 18 7 LCD Signal Waveforms 1 8 Duty 1 4 Bias ELECTRONES 18 9 LCD CONTROLLER DRIVER S3CC11B FC11B 1121 31415 6 7 1 21 31415 61 7 Vict VLC3a VLCA VL C5 Vss 2 Vica Vi cA VLC5 OV VLc5 CMLc4 Vige Vic Figure 18 8 LCD Signal Waveforms 1 8 Duty 1 4 Bias Continued 18 10 ELEGTRONK 5 S3CC11B FC11B LCD CONTROLLER DRIVER a a S E G 5 oomo 1700719 omo WENN came IL NM O0 000 H Figure 18 9 LCD Signal Waveforms 1 8 Duty 1 5 Bias ELECTRONES 18 11 LCD CONTROLLER DRIVER S3CC11B FC11B Figure 18 10 LCD Signal Waveforms 1 8 Duty 1 5 Bias Continued 18 12 ELEGTRONK 5 S3CC11B FC11B BATTERY LEVEL DETECTOR BATTERY LEVEL DETECTOR OVERVIEW The S3CC11B FC11B micro controller has a builtin BLD Battery Level Detector circuit which allows detection of power voltage drop through software Turning the BLD operation on and off can be controled by software Because the IC consumes a large amount of current during BLD operation It is recommended that the BLD operation should be kept OFF unless it is necessary Also the BLD criteria voltage can be set by the software The criteria voltage can be set by matching to one of the 2 kinds of voltage 2 45 V or 2 70 V Vpp reference voltage The BLD block works only
136. a Operation SR SG lt asr lt lt asa This instruction shifts the value of 16 bit asr values by the amount of 7 bit asa If the value of asa is positive left shift operation is performed and if the value of asa is negative right shift operation is performed The 16 bit shifted result is stored into SR register and the 16 bit shifted out result is stored into SG register The other bits of SR and SG register are filled with zeros Flags C Set if last shifted out bit is 1 Reset if not Unchanged when shift amount is 0 Z Set if SR result is zero Reset if not VS Reset N MSB of SR result Notes Examples ESFT A B ESFT SI SA of Words 1 ELECTRONES 21 115 CalmMAC1616 S3CC11B FC11B ESFTA Arithmetic Shift by Barrel Shifter Format ESFTA asr asa Operation SR SG asr lt lt asa This instruction shifts the value of 16 bit asr values by the amount of 7 bit asa If the value of asa is positive left shift operation is performed and if the value of asa is negative right shift operation is performed The 16 bit shifted result is stored into SR register and the 16 bit shifted out result is stored into SG register The remainder MSB bits of SR or SG register are sign extended and the remainder LSB bits are filled with zeros Flags C Set if last shifted out bit is 1 Reset if not Unchanged when shift amount is 0 Z Set if SR result is zero Reset if not VS Set if overflow is generated Reset if not N MSB of
137. a higher than 3F0000H Memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location In this section detailed descriptions of the S3CC11B FC11B control registers are presented in an easy to read format You can use this section as a quick reference source when writing application programs This control register is divided into three areas Control Register 3F007F Timer and Peripheral Control Register 3F0040H Port Register Area 3F0010H 3F000FH System Control Register Area Figure 5 1 Memory Mapped IO Registers ELECTRONES 5 1 MEMORY MAP S3CC11B FC11B Table 5 1 Registers x RegsterName Mnemonic Hex mest AW Locations 3F0000H 3F0001H are not mapped Location is not mapped R so RW Basic timer control register BTCON a c Watchdog timer enable register woten om mw Location 3F000FH is not mapped Pot0dmarser som om aw Port 6 data register 1 Ps RW Pa sro RW Port 9 data register P RW Locations 3F001AH 3F001FH are not mapped Port controlregisterhigh PoconH om Port 0 control register low POCONL 3F0021H oum j Port 0 interrupt state setting register RW Port regster Poon aoza
138. adds the value of 16 bit register Ri and the value of 22 bit register An and stores the result in register An 15 14 13 12 11 10 8 7 6 5 4 3 0 A fififofo f R Operation An An Ri Exceptions None Notes None 6 26 ELECTRONES S3CC11B FC11B INSTRUCTION SET ADD 5 Add Immediate to Extended Register Format ADD An lt imm 16 gt Description This form of ADD instruction is used to add a 16 bit unsigned immediate value to a 22 bit register This instruction adds the value of lt imm 16 gt to the value of An and stores the result in register An 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 9 9 09 09 09 0 1 1 1 1 14 09 a Operation An An lt imm 16 gt Exceptions None Notes This is a 2 word instruction where the 16 bit immediate follows the instruction word shown above Unlike 1 word instructions therefore fetching of this instruction takes 2 cycles ELECTRONES 6 27 INSTRUCTION SET S3CC11B FC11B ADD 6 Add 5 bit Immediate to Extended Register Format Description Operation Exceptions Notes 6 28 ADD An lt imm 5 gt This form of ADD instruction is used to add a 5 bit unsigned immediate value to a 22 bit register This instruction adds the value of 5 bit immediate lt imm 5 gt and the value of 22 bit register An and stores the result in register An 15 14 13 12 11 10 8 7 6 5 4 0 o a Jfofifo An An lt imm 5 gt No
139. after this operation The T bit is updated for later reference 15 14 13 12 11 8 7 6 5 4 3 0 Temp Rn Ri T bit Negative if Mode GE Negative amp amp Zero if Mode GT Carry if lt gt UGE Carry amp amp Zero if lt gt UGT Zero if Mode EQ Mode encoding GE 000 GT 001 UGE 010 UGT 011 and EQ 100 None None ELECTRONES S3CC11B FC11B INSTRUCTION SET CMP 2 Compare Immediate Format CMPmode Rn lt imm 16 gt Description The CMP Compare Immediate instruction is used to compare two values in register Rn and lt imm 16 gt The allowed modes include GE Greater or Equal GT Greater Than UGE Unsigned Greater or Equal UGT Unsigned Greater Than and EQ Equal CMP subtracts the value of lt imm 16 gt from the value of Rn and performs comparison based on the result The contents of Rn is not changed however after this operation The T bit is updated for later reference 15 14 13 12 11 10 8 7 6 5 4 3 0 mode Operation Temp Rn lt imm 16 gt T bit Negative if lt Mode gt GE Negative amp amp Zero if Mode GT Carry if Mode UGE Carry amp amp Zero if Mode UGT Zero if Mode EQ Mode encoding GE 000 GT 001 UGE 010 UGT 011 and EQ 100 Exceptions None Notes This is a 2 word instruction where the
140. ansfer 16 bit data between a general register Rn and the memory location at the address of Ai edisp 5 edisp 5 is an even positive displacement from 0 to 30 edisp 5 is encoded into an 4 bit displacement value in the instruction map because the LSB is always 0 When the address is calculated the 4 bit displacement field is shifted to the left by one bit and then the result is added to the value of Ai Even if the address might be specified as odd in assembly mnemonic the LSB of the address should be truncated to zero for word alignment LDW Rn Ai disp 16 LDW Ai disp 16 Rn The instructions transfer 16 bit data between a general register Rn and the memory location at the address of Ai disp 16 disp 16 is an positive displacement from 0 to FFFFh If the address is odd the LSB of the address is set to zero for word alignment LDW Rn Ai Rj LDW G Ai Rj Rn The instructions transfer 16 bit data between a general register Rn and the memory location at the address of Ai Rj The value of Rj is zero extended to 22 bit value If the address is odd the LSB of the address is set to zero for word alignment LDW An Ai edisp 5 LDW G Ai edisp 5 An The instructions transfer 22 bit data between an address register An and the memory location at the address of Ai edisp 5 edisp 5 is an even positive displacement from 0 to 30 edisp 5 is encoded into an 4 bit displacement value in the instruction map because the LSB is always 0 Wh
141. artial multiplication result An example of different multiplication is in the multiplication of 32 bit by 16 bit numbers where two multiplication and a addition are needed multiplying the 16 bit number with the lower and upper portion of a 32 bit double precision number and addition of each partial product value The signed by signed operation is used to multiply the 16 bit signed number with the upper signed portion of the 32 bit number The signed by unsigned operation is used to multiply the 16 bit signed number with the lower unsigned portion of the 32 bit number After the signed by unsigned operation is executed it is recommended to accumulate the aligned using EADD MAi PSH instruction result of the signed by uns igned operation with the signed by signed operation result For the multiplication of two double precision 32 bit numbers the unsigned by signed operation can be used Note that in all case only upper 32 bit result can be calculated ELECTRONES 21 7 CalmMAC1616 S3CC11B FC11B Division Possibilities Two specific instructions EDIVQ and ERESR instruction are used to implement non restoring conditional add subtract division algorithm The division can be only signed and two operands dividend and divisor must be all positive number The dividend must be a 32 bit operand located in MA register 4 bit extension nibble contains the sign extension of the MA register in 16 bit operation mode The divisor must
142. at changes EI 2 0 value In this case a NOP no operation instruction must be inserted between the branch instruction and the ARU instruction On the other hand in a medium and low speed system the branch instruction can immediately follow any instruction that changes El values The following shows the examples Branching in high speed system EADD A C Update Status Flags amp EI 2 0 ENOP BRA Label1 Branching in medium to low speed system EADD B D Update Status Flags amp EI 2 0 EC1 Label2 In case of branch instruction using EI 3 as a branch condition a ETST cc EC3 instruction must be executed before the branch instruction because only the ETST instruction evaluates the EI 3 pin values The following shows an example of branching with EI 3 Branching with EI 3 EADD Update Status Flags ETST NC EC3 Update EI 3 port value BRA EC3 Label3 21 24 ELECTRONES S3CC11B FC11B CalmMAC1616 STATUS REGISTER 0 MSR0 MSR0 register of three CalmMAC16 status registers MSRO MSR1 MSR2 is used to hold the flags control bits status bits for the ARU and BEU Barrel Shifter and Exponent Unit The contents of each field definitions are described as follows ME3 ME2 ME1 MEO Bit 15 Bit 12 These bits define modulo options of the corresponding pointer register for address modification When this bit is cleared the current bank of corresponding RPi register will be mo
143. ation are prepared In the case of branch or jump instructions the target address is calculated in ID stage In the third stage which is called EX Execution stage ALU operation and data address calculation are executed In the fourth stage which is called MEM Memory stage data transfer from to data memory or program memory is executed In the fifth stage which is called WB Write Back stage a write back to register file can be executed The following figure shows an example of pipeline progress when 3 consecutive instructions are executed ADD 12 ADD R1 RO I3 LD R2 RO In the above exam ple the instruction 12 needs the result of the instruction before 11 completes To resolve this problem the EX stage result of 11 is forwarded to ID stage of 2 Similar forwarding mechanism occurs from MEM stage of 11 to ID stage of I3 The pipeline cannot progress called a pipeline stall due to a data dependency a control dependency or a resource conflict When a source operand of an ALU instruction is from a register which is loaded from memory in the previous instruction 1 cycle of pipeline stall occurs called load stall Such load stalls can be avoided by smart reordering of the instruction sequences CalmRISC16 has 2 classes of branch instructions those with a delay slot and without a delay slot Non delay slot branch instructions incurs a 1 cycle pipeline stall if the branch is taken due to a control dependency F
144. ation operand The 16 bit data location is composed of the page number in the MSB 11 bits of RPDO or RPD1 register and the direct address field the offset in the page in the instruction code The short direct addressing uses RPDO or RPD1 register specified in instruction code as a page value The LSB 5 bits of RPDO or RPD1 register is not used at all ELD A RPDO 3h RPDO Data Loacation 23h Address Generation 0000000001 Before Execution 8010h 0028h 0011h 00011 After Execution 21 36 RPDO 15 5 adr 5 Figure 21 21 Short Direct Addressing Example ELECTRONES S3CC11B FC11B CalmMAC1616 Long Direct Addressing adr 16 The data location one of the 64K data word is one of the source operand or destination operand The 16 bit data location is specified as the second word of the instruction There is no use of the page bits in the RPDi register in this mode ELD 1234h B Before Execution After Execution 8010h 8010h Data Loacation 1234h 0011h 8010h Address Generation 001001000110100 Figure 21 22 Long Direct Addressing Example Short Direct Associated Addressing RPD1 adr 2 The data location one of the 64K data word is one of the source operand or destination operand The 16 bit data location is composed of the page number in the MSB 10 bits of RPD1 register the 2 bit direct address field the offset in the page in the instruction code and destination or source register name itself The sou
145. basic timer generates CPU start signal to indicate that the stabilization interval has elapsed gating the clock signal on to the CPU so that it can resume its normal operation In summary the following events occur during the STOP mode release 1 We assume that in STOP mode a power on reset or an external interrupt occurs to trigger a STOP mode release and oscillation starts 2 If a power on reset occurs the BTCNT will increase at the rate of f950 2048 If an external interrupt is used to release the STOP mode the BTCNT value increases at the rate of the preset clock source 3 Clock oscillation stabilization interval begins and continues until BTCNT becomes 80h When a BTONT is 10h the CPU start signal is generated and the normal CPU operation resumes Watchdog Timer Function The basic timer can also be used as a watchdog timer to detect inadvertent program loops i e infinite loop by system or program operation errors For this purpose instructions that clear the watchdog timer counter register within a given period should be executed at proper points in a program If an instruction that clears the watchdog timer counter register is not executed within the period and the watchdog timer overflows a reset signal is generated so that the system will be restarted Operations of a watchdog timer are as follows 1 Each time BTCNT overflows the overflow signal is sent to the watchdog timer counter WTONT 2 If WDTCNT overflows a
146. be a 16 bit operand located in 16 bit most significant portion of the P register The 16 bit least significant portion of the P register must be zero To obtain a valid result the value of the dividend must be strictly smaller than the value of divisor reading operand as fractional data Else the quotient could not be expressed in the correct format for example quotient greater than 1 for fractional format At the end of algorithm the result is stored in the MA register the same which previously contained the dividend the quotient in the 16 bit LSP the significant bit remainder stored in the 16 MSP of the MA register Typically 32 16 division can be executed with 16 elementary divide operations preceded by 1 initialization instructions This instruction is required to perform initial subtraction operation and possibly followed by one restoring instruction which restores the true remainder in case this last one is useful for the next calculations Note that lower precision can also be obtained by decreasing the number of elementary division step applied The operation of elementary instructions for division is as follows EDIVQ This single cycle instruction is repeatedly executed to generate division quotient bits It calculates one bit of the quotient at a time computes the new partial remainder sets NQ bit of the MSR1 register according to the new partial remainder sign First this instruction calculates the new partial rema
147. can photocopy this form fill it out and then forward it to your local Samsung Sales Representative S3CC11B FC11B MICROCONTROLLER iii Table of Contents Part Programming Model Chapter 1 Product Overview Introductio M l pP 1 1 oos eo HE Tienen 1 1 2 keen edited eMe E EIQUE DHL usha 1 3 ia ctii u ecient ane 1 4 Pini Circuit DIagrams mm i ec erc DU eet dad Ma DE ed rd Load 1 9 Chapter 2 Address Spaces MU r uu II 2 1 Program Memory s usa us Grane Dp Ad SER ERR HRS ERE tenes 2 2 Data sce bet sri n ccn rk ditat e uama Indie 2 4 Chapter 3 Calm16Core Introduction uskadet haath exec te rec cec enu ER T I MOM 3 1 Do tube eue ere pe gin Te 3 1 ce E 3 2 General Registers amp Extension 3 2 Special Registers cute n euet oder cnp ERATES 3 3 Pipeline Struct rezu a mam ee d a ae OUR ideas 3 4 aoc EE 3 5 Chapter 4 Exceptions OVOIVIQW eem oct tegunt buta ace pay See een 4 1 Hardware Reset EIE deans m 4 1 FIQEXCODIUOD s ert Cue SE P Ee aa 4 2 piede eM ut 4 2 Msiodz c nme EE 4 2 SWIExG eBtw
148. card 00 No wait in nWE or nRD signal 01 1 wait in nWE or nRD signal 10 4 wait in nWE or nRD signal 11 8 wait in nWE or nRD signal ELECTRONES 15 3 SSFDC Solid State Floppy Disk Card S3CC11B FC11B SMARTMEDIA ECC COUNT REGISTER ECCNT ECCNT 3F0059H SmartMedia ECC count register 7 0 Count This field acts as the up counter You can know the ECC count number by reading this register This register is cleared by setting the SMCON 0 Start bit or overflow of counter SMARTMEDIA ECC DATA REGISTER ECCDATA ECCX 3F005CH SmartMedia ECC data extension register W ECCL 3F005BH SmartMedia ECC data low register 7 0 Data Data field acts as ECC data register when SMCON 0 Enable bit is set The access instruction to Port 1 executes a 1byte ECC operation The writing to ECCCLR register have all ECC data registers clear to zero ECCH 3F005AH SmartMedia ECC data high register SMARTMEDIA ECC RESULT DATA REGISTER ECCRST ECCRSTH SmartMedia result data register high RAW 00h ECCRSTL SmartMedia result data register low 7 0 Data After ECC compare operation is executed ECC result out to ECC result data register ECCRST ECCRSTH 7 0 have the byte location with correctable error bit ECCRSTL 2 0 have the bit location where is correctable error bit ECCRSTL 4 3 have the error information 00 No error occurred 01 detect 1 bit error but recoverable 10 detect the multipl
149. ch is taken Exceptions None Notes None 6 34 ELECTRONES S3CC11B FC11B INSTRUCTION SET BRA EC Branch on External Condition Format BRA D EC 2 lt eoffset 8 gt Description The BRA EC Branch on External Condition instruction is used to change the program flow when a certain external condition is set A typical usage of this instruction is to branch after a coprocessor operation as shown below COP lt operation gt NOP NOP BRA EC0 OVERFLOW OVERFLOW The BRA EC instruction checks the specified external condition instead of checking the T bit as other branch instructions and branch to the specified program address There can be up to 4 external conditions specified by the lt EC 2 gt field in the instruction 15 14 13 12 11 10 9 8 7 6 0 o o o po o lt c2 Operation if ExternalCondition n True PC PC 2 lt eoffset 8 gt Exceptions None Notes None ELECTRONES 6 35 INSTRUCTION SET S3CC11B FC11B BREAK BREAK Format BREAK Description The BREAK instruction suspends the CalmRISC core for 1 cycle by keeping PC from increasing Processor resumes execution after 1 cycle This instruction is used for debugging purposes only and thus should not be used in normal operating modes A core signal nBRK is asserted low for the cycle Operation No operation with PC suspended for a single cycle Exceptions None Notes None 6 36 ELECTRONES S3CC11B FC11B INSTRUCTION
150. cillating stabilization after a power on occurs or when stop mode is terminated Vpp 0 1 V 0 1 V Figure 23 7 Clock Timing Measurement at X N 23 8 ELECTRONES S3CC11B FC11B ELECTRICAL DATA Table 23 6 Sub Oscillator Frequency 25 C to 85 Vpp 2 0 V to 3 6 V Clock Parameter Test Condition Typ Configuration Crystal XTIN XTOUT Oscillation frequency 1 32 768 kHz Oscillator JJ Memes p pr a External XTN XTOUT input frequency 100 Clock XT y input high and low 15 level width txt NOTES 1 Oscillation frequency and input frequency data are for oscillator characteristics only 2 Stabilization time is the interval required for oscillating stabilization after a power on occurs Vpp 0 1 V 0 1 V Figure 23 8 Clock Timing Measurement at XT jy ELECTRONK S 23 9 ELECTRICAL DATA S3CC11B FC11B Table 23 7 BLD Electrical Characteristics TA 25 C Vpp 2 0 V to 3 6 V Time 0 Table 23 8 PLL Electrical Characteristics 25 C to 85 Vpp 3 0 V to 3 6 V Input Clock Frequency ____ ____ _ 2 048 Output Clock Frequency ____________ 1638 Output Clock Duy 96 w ww J Table 23 9 10 Bit A D Converter Electrical Characteristics 25 to 85 C VDD 3 0 V to 3 6 V Parameter Resolution Total Accuracy Vpp 3 3V ADC clock 2MHz Integral Linearity Error Differen
151. cumulator An to 8 bit right and stores the result back into the same accumulator Flags C Set if last shifted out bit is 1 Reset if not Z Set if result is zero Reset if not V Set if overflow is generated Reset if not N Exclusive OR of V and MSB of result Refer to Chapter 2 for more detailed explanation about this convention Notes ESRAGT instruction can be executed only when the T flag is set Otherwise No operation is performed Examples ESRA8 D ESRA8T B of Words 1 ELECTRONES 21 125 CalmMAC1616 S3CC11B FC11B ESRC ESRCT Arithmetic 1 bit Right Shift Accumulator w Carry Format ESRC T An Operation An lt An gt gt 1 An 15 C This instruction shifts the value of one of 16 bit Accumulator An to 1 bit right with carry i e the carry bit is shifted into MSB of An register and stores the result back into the same accumulator Flags C Set if shifted out bit is 1 Reset if not Z Set if result is zero Reset if not V Set if overflow is generated Reset if not N Exclusive OR of V and MSB of result Refer to Chapter 2 for more detailed explanation about this convention Notes ESRCT instruction can be executed only when the T flag is set Otherwise No operation is performed Examples ESRC A ESRCT B of Words 1 21 126 ELECTRONES S3CC11B FC11B CalmMAC1616 ESUB m Subtract Accumulator Format ESUB An op op simm 16 Am mg mgx Operation An lt An
152. d current PC is pushed in the E14 R14 register Table 4 1 Exceptions Name Address Priority 000000H Exception due to reset release 000002H Exception due to nFIQ signal Maskable by setting FE 000004H HEN Exception due to nIRQ signal Maskable by setting IE 000006H Exception due to TE bit in SR register 000008H Exception due to SWI execution 0000FEH NOTE Break mode due to BKREQ has a higher priority than all the exceptions above That is when BKREQ is active even the exception due to reset release is not executed HARDWARE RESET When nRES an input pin CalmRISC16 core signal is released transition from 0 to 1 JMP addr 22 is automatically executed by CalmRISC16 Among the 22 bit address addr 22 the most significant 6 bits are forced to 0 and the least significant 16 bits are the contents of 000000h i e reset vector address of the program memory In other words JMP 6 h00 PM 000000h instruction is forced to the pipeline The initial value of PM bit is 1 that is in privilege mode and the initial values of other bits in SR register are 0 All other registers are not initialized i e unknown ELECTRONES 4 1 EXCEPTIONS S3CC11B FC11B FIQ EXCEPTION When nFIQ an input pin CalmRISC16 core signal is active transition from 1 to 0 JMP addr 22 instruction is automatically executed by CalmRISC16 The address of FIQ interrupt service routine is in 000002h i e FIQ vecto
153. d data value having maximum magnitude and the same sign as the source MA register If the OPM bit is clear no saturation is performed This bit has not effect on a ESAT instruction which always saturates the MA register value The OPM bit is modified by writing the MSR1 register or ER ES OPM instruction The OPM bit is cleared by a processor res et MV Bit 2 The MV bit is a memorized 36 bit overflow This bit indicates that the guard bits of MA register is overflowed during previous arithmetic operations This bit is set when overflow on guard bits is occurred and is not cleared when this overflow is cleared It is only cleared when ER MV instruction or MSR1 register write instruction is executed VM1 VMO Bit 1 0 These bits indicate arithmetic overflow on MA1 register and MAO register respectively One of these bits is set if an arithmetic overflow 32 bit overflow occurs after an arithmetic operation and cleared otherwise It represents that the result of an operation cannot be represented in 32 bits i e these bits are set when 5 bit value of MA 35 31 register is not all the same in 16 bit mode These bits are modified by writing the MSR1 register or all instructions that write one of MA register 21 12 ELECTRONES S3CC11B FC11B CalmMAC1616 RAM POINTER UNIT The RAM Pointer Unit RPU performs all address storage and effective address calculations necessary to address data operands in data memories In additio
154. data memory space according to the address I 32K word YH YL Y Memory 32 x 2K byte 32K word XH XL X Memory 32 x 2K byte Figure 21 10 CalmMAC16 Data Memory Space Map Each space is divided into three 32K byte XH XL or YH YL region Each space can contain RAM or ROM and can be off chip or on chip The configuration of this region depends on the specific chip configuration Figure 21 10 16 bit data of X memory XH and XL memory 16 bit data of Y memory YH and YL memory can be allocated to any 256K byte region from 4M byte data memory space of CalmRISC16 The X memory space and Y memory space can be mapped in the separated region but CalmMAC16 can access a continuous data space i e looking at the two memory as a single continuous data memory The data memory space of CalmMAC16 may contain slow memories and peripherals as well as fast memories and peripherals When using slow memories additional wait cycles have to be inserted through DBWAIT pin of CalmMAC16 ELECTRONES 21 19 CalmMAC1616 S3CC11B FC11B 3FFFFFh 3FFFFEh 32K word CalmMAC16 Y Memory 1 word 2 bytes YH 32K byte eux v 2M word CalmRISC16 Data Memory 1 word 2 bytes 32K word CalmMAC16 X Memory 1 word 2 bytes XH 32K byte a m 000001h 000000h Figure 21 11 CalmMAC16 Data Memory Allocation 21 20 ELECTRONES S3CC11B FC11B CalmMAC1616 ARITHMETIC UNIT The Arithmetic Unit ARU performs all arithmetic operations on data operan
155. detail A basic familiarity with the information in Part will help you to understand the hardware module descriptions in Part II If you are not yet familiar with the S3CK series microcontroller family and are reading this manual for the first time we recommend that you first read Chapters 1 3 carefully Then briefly look over the detailed information in Chapters 4 5 and 6 Later you can reference the information in Part as necessary Part Il hardware Descriptions has detailed information about specific hardware components of the S3CC11B FC11B microcontroller Also included in Part Il are electrical mechanical It has 20 chapters Chapter 7 PLL Phase Locked Loop Chapter 18 LCD Controller Driver Chapter 8 RESET and Power Down Chapter 19 Battery Level Detector Chapter 9 I O Ports Chapter 20 8 16 Bit Serial Interface for Chapter 10 Basic Timer External Codec Chapter 11 Watch Timer Chapter 21 CaimMAC1616 Chapter 12 8 bit Timer 0 Chapter 22 Program Memory Access Speed Chapter 13 16 Bit Timer 1 8 Bit Timer A amp B Chapter 23 Electrical Data Chapter 14 Serial I O Interface Chapter 24 Mechanical Data Chapter 15 SSFDC Solid State Floppy Disk Card Chapter 25 SSFC11B Flash MCU Chapter 16 10 Bit Analog to Digital Converter Chapter 26 Development Tools Chapter 17 CODEC One order form is included at the back of this manual to facilitate customer order for S3CC11B FC11B microcontrollers the Flash Factory Writing Order Form You
156. dge interrupt Rising edge interrupt 1 P0 1 s Interrupt State Setting Bit Falling edge interrupt Ee Rising edge interrupt 0 P0 0 s Interrupt State Setting Bit Falling edge interrupt 1 Rising edge interrupt 1 ELECTRONES 9 PORTS S3CC11B FC11B P1CON Port 1 Control Register 3F0024H Bit Identifier 7 5 5 4 3 2 Reset Value 0 0 0 0 0 0 Read Write _ _ R W R W R W R W R W R W 7 6 Bits 7 6 5 3 P1 7 07 P1 4 4 Configuration Bits Schmitt trigger input Schmitt trigger input Pull up resistor enable Push pull output N channel open drain output 1 N channel open drain output Pull up resistor enable Schmitt trigger input 1 Schmitt trigger input Pull up resistor enable Push pull output N channel open drain output N channel open drain output Pull up resistor enable NOTE When the SmartMedia control SMCON register is enabled the read or write operation for port 1 activate the ECC block and the pull up resistors should be automatically disabled to reduce current consumption through them The ECC block capture the data on port 1 access and execute ECC operation 9 6 ELECTRONES S3CC11B FC11B VO PORTS P2CONH Port2 Control Register High 3F0028H Bit Identifier _ 5 4 2 o Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 P2 7 nCE1 Configuration Bits
157. dified as specified by the instruction regardless of the modulo options that is specified in MCi registers When this bit is set the current bank of pointer register will be modified using the suitable modulo The MEi bits are cleared by a processor reset The MEi bits can be modified by writing to MSRO register or ER ES instruction 15 14 13 12 11 10 9 peo oF Modulo Enable 0 RPi Modulo Disable Reset Value 1 RPi Module Enable Extended Index Enable 0 No Extension Reset Value 1 SD0 SD3 Extension Accumulator Overflow Protection 0 when Reset Reserved Read as 0 Barrel Shifter Exponent Overflow Flag Accumulator Overflow Flag Reserved Read as 0 Negative Flag Zero Flag Carry Flag Test Flag Figure 21 14 MSR0 Register Configuration ELECTRONES 21 25 CalmMAC1616 S3CC11B FC11B XSD Bit 10 This bit defines current bank of index register for index register read or write operation and the length of index value for address modification When this bit is set the current bank of index register is SDOE and SD3E instead of SDO and SD3 respectively When clear the current index registers are SDO and SD3 reset state During indirect addressing mode pointer register RPi is post modified by index register value If XSD is set the width of index value becomes to 8 bit by concatenating extension index register and normal index register If clear the normal 4 bit index value i
158. difier operation which is a post modification of the RPi register is defined as follows if RPi Upper Boundary in k LSBs and S gt 0 then RPik LSB lt 0 else if RPi Lower Boundary in k LSBs and S lt 0 then RPi k LSB Upper Boundary in k LSBs else RPi k LSB RPi S k LSBs where k is defined by MCi 12 10 The modulo calculation examples are as follows 1 Full Modulo with Step 1 selected by instruction and index register value MCO 000 001 0000000111 Upper Boundary 7 Lower Boundary 0 Modulo Size 8 RPi 0010h 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0010h 0011h 2 Full Modulo with Step 3 selected by instruction and index register value MCO 000 001 0000000111 Upper Boundary 7 Lower Boundary 0 Modulo Size 8 RPi 0320h 0320h 0323h 0326h 0321h 0324h 0327h 0322h 0325h 0320h 0323h 3 Part Modulo with Step 2 selected by instruction and index register value 000 001 0000000101 Upper Boundary 5 Lower Boundary 0 Modulo Size 8 RPi 2014h 2014h 2012h 2010h 2014h 2102h The total number of circular buffer modulo addressing active area is defined by 64K Modulo size i e if current modulo size is 64 the total number of circular buffer is 1024 21 16 ELECTRONES S3CC11B FC11B CalmMAC1616 15 13 12 10 9 0 MCO Modulo Size Upper Boundary Reserved Readable
159. dress of Ai LD REGISTER IMMEDIATE LD Rn imm 8 LD Rn imm 16 LD An imm 22 The instructions move an immediate data to a register In the instruction LD Rn imm 8 the immediate value is zero extended to 16 bit value ELECTRONS 6 7 INSTRUCTION SET S3CC11B FC11B BRANCH INSTRUCTIONS CalmRISC16 has 2 classes of branch instructions with a delay slot and without a delay slot If a delay slot is filled with a useful instruction or an instruction which is not NOP then the performance degradation due to the control dependency can be minimized However if the delay slot cannot be used then it should be NOP instruction which can increase the program code size In this case the corresponding branch instruction without a delay slot can be used to avoid using NOP Some instructions are not permitted to be in the delay slot The prohibited instructions are as follows All 2 word instructions All branch and jump instructions including SWI RET SWI RET RET BREAK instructions When a prohibited instruction is in the delay slot the operation of CalmRISC16 is undefined or unpredictable BSRD eoffset 13 In the instruction called branch subroutine with a delay slot the value PC 4 is saved into A14 register the instruction in the delay slot is executed and then the program sequence is moved to PC 2 eoffset 13 where PC is the address of the instruction BSRD eoffset 13 The immediate va
160. dress used to access data memory is obtained from the addition of two registers A8 and R1 No other registers can be used for this address calculation If you want to use a instruction which cause the change of T flag you must add the nop instruction between two instructions A8 R1 lt bs 3 gt NOP CMP EQ RO R2 ELECTRONES S3CC11B FC11B INSTRUCTION SET BNZD Branch Not Zero with Autodecrement Format Description Operation Exceptions Notes BNZD H lt eoffset 8 gt The BNZD Branch Not Zero with Delay Slot instruction is used to change the program flow when the specified register value does not evaluate to zero After evaluation the value in register is automatically decremented A typical usage of this instruction is as a backward branch at the end of a loop LOOP BNZD R6 LOOP if ZO 0 go back to LOOP ADD R4 3 delay slot In the above example R6 is used as the loop counter After specified loop iterations BNZD is not taken and the control will come out of the loop and R6 will have 1 For a loop with N iterations the counter register used should be initially set to N 1 BNZD has a single delay slot the instruction that immediately follows BNZD will be executed always regardless of whether BNZD is taken or not 15 14 13 12 11 10 9 8 7 6 0 r Ta TTE R6 if Z0 0 PC PC 2 lt eoffset 8 gt 1 ZO R6 1 0 else
161. ds It is a 16 it single cycle non pipelined arithmetic unit The CalmMAC16 is a coprocessor of CalmRISC16 microcontroller So all the logical operation and other bit manipulation operations can be performed in CalmRISC16 Thus the CalmMAC16 has not logical units and bit manipulation units at all The ARU receives one operand from Ai A or B or Ci C or D register and another operand from either the MSB part of MA register the XB bus or from Ai or Ci Operations between the two accumulator registers are possible The source and destination accumulator register of an ARU instruction is always the same The XB bus input is used for transferring one of the CalmMAC16 register content an immediate operand or the content of a data memory location addressed in direct addressing mode or in indirect addressing mode as a source operand The flags in the register are affected as a result of the ARU output But the flags are not affected during data load from data memory location to a accumulator or during CLD instruction In most of the instructions where the ARU result is transferred to one of accumulator registers the flags represent the accumulator register status The detailed block diagram of the Arithmetic Unit is shown in Figure 21 12 The ARU can perform add subtract compare several other arithmetic operations such as increment decrement negate and absolute and some arithmetic shift operations It uses two s complement arithmetic
162. e bit error 11 detect the multiple bit error 15 4 ELECTRONES S3CC11B FC11B SSFDC Solid State Floppy Disk Card SSFDC Interface Control 1 00 1 07 2 ECCX H L ECCCNT ECCRST ECCRST H L vi ED ECCRSTL 5 4 Error Information 00 No error 01 1 bit error in ECCRSTH ECCRSTL 2 0 Randge 0x00 0 0xFF 7 Byte address ECCRSTH 7 0 Bit location ECCRSTL 2 0 10 Multi bit error DBO DB7 11 Multi bit error Figure 15 2 ECC Processor Block Diagram ELECTRONES 15 5 SSFDC Solid State Floppy Disk Card S3CC11B FC11B NOTES 15 6 ELECTRONES S3CC11B FC11B 10 BIT A D CONVERTER 10 BIT ANALOG TO DIGITAL CONVERTER OVERVIEW The 10 bit A D converter ADC module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10 bit digital values The analog input level must lie between the AV pgp and AVss values The A D converter has the following components Analog comparator with successive approximation logic D A converter logic resistor string type ADC control register ADCON10 Four multiplexed analog data input pins ADO AD3 10 bit A D conversion data output register ADDATAH10 ADDATAL10 FUNCTION DESCRIPTION To initiate an analog to digital conversion procedure at first you must set with alternative function for ADC input enable at port 3 the pin set with alternative function can be used for ADC
163. e eto tei ua 5 2 6 1 CalmRISC16 Instruction Set nnne 6 12 6 2 Qui k MEME T 6 17 9 1 Port Data Register 9 1 15 1 Control Register 15 3 19 1 BLDCON Value and Detection 19 2 21 1 Exponent Evaluation and Normalization 21 33 23 1 Absolute Maximum Ratings a 23 1 23 2 D C Electrical Characteristics 1210 ne nennen nenne 23 1 23 3 A C Electrical Characteristics ee bakke 23 5 23 4 Data Retention Supply Voltage in Stop 23 6 23 5 Main Oscillator 23 8 23 6 Sub Osolllator ErequeriCy oet eto EIER 23 9 23 7 BLD El ctrical GharacteristicS eee Q HE eot E voto renske 23 10 23 8 PLL Electrical Characteristics iie eee asa 23 10 23 9 10 Bit A D Converter Electrical Characteristics 23 10 23 10 ADC DAC Electrical Characteristics
164. e used to implement a semaphore mechanism or lock acquisition release CLRSR SETSR TSTSR bit bit FE IE TE ZO Z1 V PM CLRSR instruction clears the corresponding bit of SR SETSR instruction sets the corresponding bit of SR TSTSR tests whether the corresponding bit is zero and stores the result in T flag For example when IE flag is zero TSTSR IE instruction sets the T flag We can clear the T flag by the instruction CMP GT RO RO We can set the T flag by the instruction CMP EQ RO RO 6 10 ELECTRONES S3CC11B FC11B INSTRUCTION SET MISCELLANEOUS INSTRUCTIONS SYS imm 5 The instruction activates the output port NSYSID The 5 is transferred to outside on DA 4 0 The most significant 17 bits remain unchanged The instruction is for system command to outside such as power down modes COP imm 13 The instruction activates the output port nCOPID The imm 13 is transferred to outside on COPIR 12 0 The instruction is used to transfer instruction to coprocessor The imm 13 may be from 200h to 1FFFh CLD Rn imm 5 CLD imm 5 Rn The instruction activates the output port NCOPID nCLDID and CLDWR The least significant 13 bits of the instruction is transferred to outside on COPIR 12 0 The imm 5 is transferred to outside on DA 4 0 The instructions move 16 bit data between Rn and a coprocessor register implied by the imm 5 field CLDWR signal indicates whether the data movement is from CalmRISC16 to c
165. ee Eee vet ete Die in bd Ee e peso 6 58 LD RExt Load Register Extension a a a 6 59 LDB 1 Load Byte Register Disp aspa ted ic eee auqaypa eed epe ribns 6 60 LDB 2 Load Byte Register Large 6 61 LDB 3 Load Byte Register Indexed a a a 6 62 LDB 4 Load Byte to RO Register Disp a mener 6 63 LDC Load GODS mL 6 64 LD PC Load Program Counter ee dele 6 65 LD SvR 1 Load from Saved Register 6 66 S3CC11B FC11B MICROCONTROLLER xix Instruction Mnemonic LD SvR 2 LD SR LDW 1 XX List of Instruction Descriptions Continued Full Instruction Name Page Number Load to Saved Register iii eirca tette em saam e e Eee Een 6 67 Load Status Register e esci eor iter D pi ERES 6 68 Load Word Stack etre ee e ere Re Unete bane edema di 6 69 Load Word Register Small mee 6 70 Load Word Register Disp ai uuu qa ener 6 71 Load Word Register Indexed a a a a nennen 6 72 Load Word Register Small 6 73 Load Word Register 6 74 Load Word Register Indexed
166. emory The bit 15 to bit 12 of MSRO register MEi bit indicates whether the each pointer is updated with modulo arithmetic The bit 15 to bit 12 of MSR2 register BKi bit defines the current bank of each pointer When this bit is set to 1 the pointer register of alternative bank is selected as a address register and the index register of alternative bank is selected as a index value EBK imm 4 Bank definition instruction instruction specifies bank of each pointer and index register Four bit immediate field indicates each pointer and index i e bit 3 of imm 4 specifies the bank of RP3 and SD3 register and bit 2 of imm 4 specifies the bank of RP2 and SD2 register For example if EBK 1110b instruction is executed current bank of RP3 RP2 and RP1 is bank 1 and current bank of RPO is bank 0 When the bank of pointer register is changed the bank of each index register including extended index register is automatically changed The bank of pointer can be changed by executing EBK instruction ER ES BKi instruction or the instruction that writes MSR2 register The RPU can access two data operand simultaneously over XA and YA buses In dual access case RPO or RP1 is selected as a X memory pointer and RP3 is selected as a Y memory pointer regardless of bit 15 of RPO and RP3 All registers in the RPU may be read or written to by the XB as 16 bit operands thus can serve as general purpose register If one of the RPU register is read as a
167. en the address is calculated the 4 bit displacement field is shifted to the left by one bit and then the result is added to the value of Ai Even if the address might be specified as odd in assembly mnemonic the LSB of the address should be truncated to zero for word alignment LDW An Ai disp 16 LDW Ai disp 16 An The instructions transfer 22 bit data between an address register An and the memory location at the address of Ai disp 16 disp 16 is an positive displacement from 0 to FFFFh If the address is odd the LSB of the address is set to zero for word alignment LDW Ai Rj LDW G Ai Rj An The instructions transfer 22 bit data between an address register An and the memory location at the address of Ai Rj The value of Rj is zero extended to 22 bit value If the address is odd the LSB of the address is set to zero for word alignment ELECTRONES 6 5 INSTRUCTION SET S3CC11B FC11B PUSH Rn PUSH Rn Rm PUSH An PUSH An Am The instruction PUSH Rn transfers 16 bit data from the register Rn to the memory location at the address of SP and then decrements the value of SP by 2 The register Rn should not be R15 The operation of PUSH R15 is undefined The instruction PUSH Rn Rm pushes Rn and then Rm The registers Rn and Rm should not be the same The registers Rn and Rm should not be R15 The instruction PUSH An pushes Rn and then En When the extension register En is pushed the value of En is
168. ended Another saturation condition is when moving from register through XB bus This saturation mode is enabled when selected MA register overflows VMi bit at MSR1 register is set and overflow protection bit is enabled OPM bit at MSR1 register is set In this case the saturation logic will substitute a limited data value having maximum magnitude and the same sign as the source register The MA register value itself is not changed at all Saturation values are 7FFFh positive overflow or 8000h negative overflow The last saturation condition is when enabling saturation on multiplier accumulators during arithmetic calculations by setting the OPMA bit of MSR1 register When overflow from the high portion of an MAi accumulator to the extension bits occurs during MAi arithmetic operation and the OPMA bit is set the accumulator is limited to a full scale 32 bit positive 7FFFFFFFh or negative 80000000h value Saturation by Instruction ESAT Instruction amp Sturation by MA Read Read MAiH amp VMi amp OPM Saturation by Arithmetic Operation Arithmetic Instruction on amp amp X0 X1 Y0 Y1 35 3231 MAOMAT MA Guard Region MAiH Figure 21 3 MAU Registers Configuration 21 6 ELECTRONES S3CC11B FC11B CalmMAC1616 ARITHMETIC UNIT The arithmetic unit performs several arithmetic operations on data operands It is a 36 bit single cycle non pipelined arithmetic
169. er output as well as a result of the ARU output When the result is transferred into the barrel shifter output register the flags represent the shifter output register status The C N and Z flag in MSRO register is used common to the ARU and the BEU but the V flag is different The ARU uses the V flag as overflow flag and the BEU uses the VS flag as overflow flag ELECTRONES 21 29 CalmMAC1616 S3CC11B FC11B SHIFTING OPERATIONS Several shift operations are available using the barrel shifter All of them are performed in a single cycle The detailed operations of each shift instruction are depicted in figure 2 16 If 7 bit shift amount value is positive shift left operation is performed and if negative shift right operation is performed After all barrel shifter operation is performed the carry flag has the bit value which is shifted out finally ESFT instruction performs a standard logical shift operation The shifted bit pattern is stored into the 16 bit SR register Shifter Result register and the shifted out bit pattern is stored into the 16 bit SG register Shifter Guard register When shift left operation MSBs of SG register and LSBs of SR register is filled with zeros When shift right operation LSBs of SG register and MSBs of SR register is filled with zeros ESFTA instruction performs a standard arithmetic shift operation The operation is all the same as a logical shift except that the MSBs of SG register or MSBs of S
170. es using a standard exponent valuation instruction EEXP followed by EEXPC instruction The EEXP instruction sets the VS flag when the source operand has the all one value or the all zero value and sets the C flag with the LSB bit value of the source operand The C flag transfer the sign information of higher 16 bit data After EEXP instruction is executed the instruction evaluates the exponent value of lower 16 bit data and carry if the VS flag is set And then the calculated exponent value is added with previous SA register value In this way full double precision exponent calculation can be done Double Precision Exponent Evaluation about A B EEXP A EEXPC B ELECTRONES 21 33 CalmMAC1616 S3CC11B FC11B INSTRUCTION SET MAP AND SUMMARY ADDRESSING MODES Various addressing modes including indirect linear and modulo addressing short and long direct addressing and immediate are implemented in the CalmMAC16 coprocessor Indirect Addressing Mode Indirect Addressing for Single Read Operation RP0 S0 RP0 S1 RP1 S0 RP1 S1 RP2 S0 RP2 S1 RP3 S0 RP3 S1 One of the current bank pointer registers RP0 RP1 RP2 RP3 points to one of the 64K data words The data location content pointed to by the pointer register is the source operand The RPi pointer register is modified with one of two 4 bit or 8 bit source index values S0 or S1 field which reside in the index register after the instructi
171. es next operation of restoring instruction If this bit is set to 0 the next restoring instruction adds 0 to MA register and if this bit is set to 1 adds two times the divisor P register value to the MA The NQ bit is affected when register write operation ER ES instruction or division step EDIVQ instruction is executed The NQ bit is cleared by a processor reset PSH1 Bit 5 This bit defines multiplier output shift operation When this bit is set multiplier output result is 1 bit shifted left This property can be used for fractional format operand multiplication When this bit is clear no shift is executed on the multiplier output The PSH1 bit can be modified by writing to MSR1 register or ER ES PSH1 instruction The PSH1 bit is cleared by a proc essor reset USM Bit 4 The USM bit indicates that the X1 or Y1 register is signed or unsigned as a multiplicand When set selected multiplicand is interpreted as a unsigned number if X1 or Y1 register is selected The other registers X0 YO are always signed numbers The USM bit can be modified by writing to MSR1 register or ER ES USM instruction The USM bit is cleared by a processor reset OPM Bit 3 The OPM bit indicates that saturation arithmetic is provided or not when moving from the higher portion of one of the MA registers through the XB bus When the OPM bit is set Overflow Protection is enabled the saturation logic will substitute a limite
172. escription This form of LD instruction Load Extended Register is used to load 22 bit register value to a 22 bit register 15 14 13 12 1l 10 8 7 6 5 4 3 2 0 Operation An Ai Exceptions None Notes None ELECTRONES 6 55 INSTRUCTION SET S3CC11B FC11B LD 3 Load Short Immediate Format LD Rn lt imm 8 gt Description The LD Load Short Immediate instruction is used to load an 8 bit immediate value to a register 15 14 13 12 11 8 7 0 O oo i Cam I m Operation Rn 15 8 0 Rn 7 0 lt imm 8 gt if Rn R6 R7 Z0 Z1 lt imm 8 gt 0 Exceptions None Notes None 6 56 ELECTRONES S3CC11B FC11B INSTRUCTION SET LD 4 Load Immediate Format Description Operation Exceptions Notes LD Rn lt imm 16 gt This form of LD instruction Load Immediate is used to load a 16 bit immediate value to a register Rn lt imm 16 gt if Rn R6 R7 Z0 Z1 lt imm 16 gt 0 None This is a 2 word instruction where the 16 bit immediate follows the instruction word shown above Unlike 1 word instructions therefore fetching of this instruction takes 2 cycles ELECTRONES 6 57 INSTRUCTION SET S3CC11B FC11B LD 5 Load Large Immediate Format Description Operation Exceptions Notes 6 58 LD An lt imm 22 gt This form of LD instruction Load Large Immediate is used to load a 22 bit immediate value to an e
173. ficant portion MSP of the MA register MAiH or the 16 bit least significant portion LSP of the MA register MAiL can be written by the XB as an operand When register is written MAiL register is forced to zero and extension nibble is sign extended When MAIL register is written MAiH and MAiE are not changed Registers MAiH and MAiL can also be used as general purpose temporary 16 bit data registers ELECTRONES 21 5 CalmMAC1616 S3CC11B FC11B Extension Nibbles Extension nibbles MAOE and MA1E in MSR1 register offer protection against 32 bit overflows When the result of a 36 bit adder output crosses bit 31 it sets VMi flag of MSR1 register MA register Overflow flag Upto 15 overflows or underflows are possible using the extension nibble after which the sign is lost beyond the MSB of the extension nibble setting MV flag of MSR1 Memorized Overflow flag and latching the value Registers MA0E and MA1E can not be accessed independently Those registers are read or written as a part of MSR1 register during MSR1 register read or write instruction Overflow Protection in MA Registers The multiplier accumulator saturation instruction ESAT instruction sets the destination MA register to the plus or minus maximum value if selected MA register overflows VMi bit of MSR1 register is set Saturation values are 7FFFFFFFh positive overflow or 80000000h negative overflow for the MA register and extension nibble is sign ext
174. flowed Unchanged if not Notes VMi denotes for VMO or VM1 according to Mi Examples EMLD MAO X1Y0 of Words 1 21 92 ELECTRONES S3CC11B FC11B CalmMAC1616 Multiply and Load w One Parallel Move Format EMLD Mi XiYi dest src lt dest gt lt src gt Ai Mj Ai MjSR Ai MjSL mgx rps Operation lt P P lt Xi Yi dest lt src This instruction loads the P register value to the one of 36 bit Multiplier Accumulator MAi At the same time multiplier multiplies Xi register value and Yi register value and stores the result to the P register This instruction also stores source operand from data memory or 16 bit higher portion of the MAj register to the destination register Flags Set if result is overflowed to guard bits Reset if not MV Set if guard bit is overflowed Unchanged if not When dest is Ai Z Set if the value to Ai is zero by load Reset if not Set if overflow is generated by load Reset if not N Set if loaded value is negative Notes MjSR 1 bit right shifted MAj 31 16 MjSL 1 bit left shifted MAj 31 16 VMi denotes for VMO or VM1 according to Mi Examples EMLD 1 0 A MA1SR EMLD MA1 X0Y0 X0 RP1 S1 of Words 1 ELECTRONES 21 93 CalmMAC1616 S3CC11B FC11B 3 9 multiply and Load w Two Parallel Moves Format EMLD Mi XiYi Xi rp01s Yi rp3s Operation lt P P lt Xi Yi Xi lt operand1 by
175. ge range e 100 QFP 100 TQFP package Analog to Digital Converter 10 bit resolution e 4 channel analog inputs e 25uS conversion time e 3 0 V 3 6 V operation voltage range Two Power Down Modes e Idle Only CPU clock stops e Stop Selected system clock and CPU clock stop Oscillation Sources Crystal or ceramic for main clock e Programmable oscillation sources for main clock e 32 768 kHz crystal oscillation circuit for sub clock e CPU clock divider circuit divided by 1 2 4 or 8 Instruction Execution Times Main clocks 30 ns at 32 MHz when 1 cycle instructions 60 ns at 32 MHz when 2 cycle instructions e Sub clocks 32 768 kHz 30 52 us when 1 cycle instructions 61 04 us when 2 cycle instructions 1 2 S3CC11B FC11B 3 3V ELECTRONES S3CC11B FC11B BLOCK DIAGRAM XIN Xour XTin XTout T T f VDD1 VDD2 VDD3 VSS1 VSS2 VSS3 AVDD1 AVSS1 gt gt ij P6 0 P6 7 SEG15 SEG22 P ORT6 KY P5 0 P5 7 SEG7 SEG14 P4 0 CDR P4 1 CDX SEGO P4 2 CFS SEG1 P4 3 CCLK SEG2 P4 4 P4 7 INT4 INT7 SEG3 SEG6 PORT5 KY PORT 4 3 P3 0 P3 2 CINO CIN2 P3 3 TOCLK P3 4 TOOUT TOPWM TOCAP P3 5 BUZ T1CLK P3 6 TAOUT P3 7 TBOUT PORTS 3 P2 0 nWE P2 1 nRE P2 2 WP P2 3 R nB P2 4 ALE P2 5 CLE P2 6 nCEO P2 7 nCE1 P1 0 P1 7 1 00 1 07 CalmRISC CPU RAM 196 Bytes Y Memory 4096 Bytes PORT 2 gt X Memory 6144 Bytes Flash ROM PORT
176. he nRESET pin must be held to low level for a minimum time interval after the power supply comes within tolerance For the minimum time interval see the electrical characteristic In summary the following sequence of events occurs during a reset operation All interrupts are disabled The watchdog function basic timer is disabled All Ports are set to input mode Peripheral control and data registers are disabled and reset to their default hardware values The program counter PC is loaded with the program reset address in 00000H When the programmed oscillation stabilization time interval has elapsed the instruction stored in location 00000H is fetched and executed NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering STOP mode Also if you want to use the basic timer watchdog function you can enable it by writing some value other than 1010 0101b to the WDTEN register ELECTRONES 8 1 RESET AND POWER DOWN 8 2 NOTES S3CC11B FC11B ELECTRONES S3CC11B FC11B VO PORTS I O PORTS PORT DATA REGISTERS All ten port data registers have the identical structure shown in Figure 9 1 below Table 9 1 Port Data Register Summary RegisterName Mnemonic Address Reset Vale RW m wow mw Port 1 Data 1 3F0011H R W Por 3 Data Register Pon bas samana
177. herwise no operation is performed This instruction also stores source operand from data memory to the destination accumulator the same accumulator register Ci RP3 register can not be used as a pointer register of parallel move part Flags C Set if carry is generated Reset if not 2 Set if result is zero Reset if not V Set if overflow is generated Reset if not N Exclusive OR of V and MSB of result Refer to Programming MODEL Part for more detailed explanation about this convention Notes Flags are generated from the operation Ai Ci Examples EMAX A D D RP1 S1 of Words 1 ELECTRONES 21 89 CalmMAC1616 EMIN Format Operation Flags C 2 V N S3CC11B FC11B Minimum Value Load EMIN Ai lt op gt lt op gt Ci Ai if op lt Ai Ai op RP3 previous address with RPi register This instruction conditionally loads op value to the one of 16 bit Accumulator Ai and latches the previous address value to the RP3 pointer when op is less than or equal to Ai Otherwise no operation is performed Set if carry is generated Reset if not Set if result is zero Reset if not Set if overflow is generated Reset if not Exclusive OR of V and MSB of result Refer to Chapter 2 for more detailed explanation about this convention Notes Flags are generated from the operation op Ai Examples of Words 21 90 EMIN B D 1 ELECTRON
178. hipment ELECTRONES 15 1 SSFDC Solid State Floppy Disk Card S3CC11B FC11B nCE P2 6 7 a CLE P2 5 au ALE P2 4 R B P2 3 nWE Dedicated Pins nRE Dedicated Pins 1 00 1 07 Dedicated Pins Processor DB0 DB7 Figure 15 1 Simple System Configuration 15 2 ELECTRONES S3CC11B FC11B SSFDC Solid State Floppy Disk Card SSFDC REGISTER DESCRIPTION Description of the register in the SSFDC SmartMedia interface is listed the below table Table 15 1 Control Register Description SMCON 3F0058H RAN SmartMedia control register ECCNT 3F0059H ECC count register ECCH L X 3F005AH R W ECC data register high low extension 3F005BH 3F005CH ECCCLR 3F005DH ECC clear register ECCRSTH L 3F005EH R W ECC result data register low high 3F005FH SMARTMEDIA CONTROL REGISTER SMCON SMCON 3F0058H SmartMedia control register 0 ECC Enable This bit enables or disables the ECC operation in the SmartMedia block When this bit is set as 1 ECC block is activated and ECC operation is done whenever accessing the Port 1 1 Enable 0 Disable 1 Enable SmartMedia interface This bit controls the operation of SmartMedia block When this bit is set as 1 Port 1 is activated as I O data bus of SmartMedia interface SmartMedia control signal is generated whenever accessing the Port 1 3 2 Wait cycle control These bit control the wait cycle insertion when access to SmartMedia
179. iding Registers Connection 18 6 18 5 LCD Signal Waveforms 1 3 Duty 1 3 18 7 18 6 LCD Signal Waveforms 1 4 Duty 1 3 Hee 18 8 18 7 LCD Signal Waveforms 1 8 Duty 1 4 18 9 18 9 LCD Signal Waveforms 1 8 Duty 1 5 Hem 18 11 19 1 Block Diagram for Battery Level 19 1 19 2 Battery Level Detector Circuit and Control Register a 19 2 20 1 SIO Block Diagram for External Codec a enn menn 20 4 20 2 8 Bit SIO Timing Diagram for External 20 5 20 3 16 Bit SIO Timing Diagram for External ee 20 6 xiv S3CC11B FC11B MICROCONTROLLER Figure Number 21 1 21 2 21 3 21 4 21 5 21 6 21 7 21 8 21 9 21 10 21 11 21 12 21 13 21 14 21 15 21 16 21 17 21 18 21 19 21 20 21 21 21 22 21 23 23 1 23 2 23 3 23 4 23 5 23 6 037 23 8 24 1 24 2 25 1 25 2 26 1 List of Figures continued Title Page Number CalmMAC1616 Block Diagram a a eee 21 2 Multiplier and Accumulator Unit Block Diagram mH 21 4 MAU Registers Configuration s
180. inder by adding or subtracting the divisor from the remainder depending on current NQ bit value If current NQ 0 new partial remainder old partial remainder divisor If current NQ 1 new partial remainder old partial remainder divisor This add or subtract operation is performed between MA register and P register Second this instruction shifts one bit left the new partial remainder and moves one bit quotient into the rightmost bit The one bit quotient bit is the inverted value of the new partial remainder sign bit Quotient bit sign of new partial remainder Third EDIVQ updates the MA register with shifted new partial remainder value and updates the NQ bit of MSR1 register with sign value of the new partial remainder This NQ update determines the operation of the next EDIVQ instruction ERESR This single cycle instruction restores the true remainder value In fact due to the non restoring nature of the division algorithm the last remainder has to be restored or not by adding 2 times the divisor depending on the NQ bit of MSR1 register previously computed If NQ 0 No Operation is performed If NQ 1 Adds two times the divisor to the MA register containing the last calculated remainder in the 16 bit most significant portion The new calculated remainder will have to be 16 bit right arithmetical shifted in order to be represented in a usual fractional format 21 8 ELECTRONES S3CC11B FC11B CalmMAC1616
181. ine current banks of the corresponding pointer and index register for address generation and address modification Clear bank 0 pointer and index register is selected Set bank 1 pointer and index register is selected The BKi bits are cleared by a processor reset The BKi bits can be modified by writing to MSR2 register ER ES BKi instruction or EBK instruction The writing to MSR2 and EBK instruction can change the whole four banks of each pointer register and index register On the other hand ER ES instruction changes only one bank of pointer and index register SEC2 SEC1 SECO Bit 11 Bit 0 These bits defines the logic state of the EI 2 0 pin according to status information of CalmMAC16 processor For example if SEC2 value is 00006 the EI 2 pin monitors Z flag value of MSRO register The logic state of the El pin is changed immediately after SECi bit field value is changed or corresponding condition flag bit value is changed The SECi bits can be modified by a instruction writing to the MSR2 register or ESECi instructions 21 28 ELECTRONES S3CC11B FC11B CalmMAC1616 BARREL SHIFTER AND EXPONENT UNIT The Barrel Shifter and Exponent Unit BEU performs several shifting operations and exponent evaluations It contains a 16 bit single cycle non pipelined barrel shifter and 16 bit exponent evaluation unit The detailed block diagram of the Barrel Shifter and Exponent Unit is shown in Figure 21 16 f
182. inot __ o __ O N channel open drain output Not available ELECTRONES 9 3 PORTS S3CC11B FC11B POPUR Port o Pull Up Resistors Enable Register 3F0022H Reset Value 0 0 0 0 0 0 0 0 Read Write R R W R W R W R W R W R W R W 7 P0 7 s Pull up Resistor Enable Bit isable pull up resistor nable pull up resistor 6 P0 6 s Pull up Resistor Enable Bit x isable pull up resistor nable pull up resistor 5 P0 5 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 4 P0 4 s Pull up Resistor Enable Bit 0 1 Disable pull up resistor Enable pull up resistor 3 3 5 Pull up Resistor Enable Bit isable pull up resistor nable pull up resistor 2 0 2 Pull up Resistor Enable isable pull up resistor x m 1 nable pull up resistor 1 P0 1 s Pull up Resistor Enable Bit isable pull up resistor x nable pull up resistor m 0 0 0 Pull up Resistor Enable Bit Disable pull up resistor Enable pull up resistor 9 4 ELECTRONES S3CC11B FC11B VO PORTS POSTA Porto Interrupt State Setting Register 3F0023H Bit Identifier _ 7 s 4 3 2 9 0 0 0 0 0 0 0 Reset Value 0 Read Write R W R W R W R W R W R W R W R W 7 4 Bits 7 4 Not used 3 P0 3 s Interrupt State Setting Bit Falling edge interrupt 1 Rising edge interrupt 2 P0 2 s Interrupt State Setting Bit 0 1 Falling e
183. instructions double precision or more precision arithmetics can be accomplished The following shows one example of multi precision arithmetic 3 cycle Double Precision Addition A B C D EADD B D Lower Part Addition EINCC A Carry Propagation EADD Higher Part Addition EXTERNAL CONDITION GENERATION UNIT CalmMAC16 can generates and send the status information or control information after instruction execution to the host processor CalmRISC16 through EI 3 0 pin Refer to Pin Diagram The CalmRISC16 can change the program sequence according to this information by use of a conditional branch instruction that uses El pin values as a branch condition The El generation block in the ARU selects one of status register value or combination of status register values according to the SECi 120 1 2 field in the MSR2 register for EI 2 0 Refer to MSR2 register configuration EI 3 pin selects one of status register value or combination of status register values according to the test field of ETST cc instruction So the El 2 0 pin is always changes the value if corresponding status register bit value is changed but EI 3 is only changed after executing ETST cc instruction Refer to ETST instruction In a high speed system which operates at full clock speed 32 MHz with CalmRISC16 and CalmMAC16 a branch instruction using EI 2 0 value as a branch condition can not immediately follow the instruction th
184. iplier Accumulator MAi At the same time multiplier multiplies Xi register value and Yi register value and stores the result to the P register This instruction also stores two source operands from data memory one from X memory space and one from Y memory space to the 16 bit Xi register and Yi register respectively Flags VMi Set if result is overflowed to guard bits Reset if not MV Set if guard bit is overflowed Unchanged if not Notes VMi denotes for VMO or VM1 according to Mi Examples EMSB X1YO X0 RP0 S1 0 50 of Words 1 ELECTRONES 21 97 CalmMAC1616 S3CC11B FC11B EMUL _ Format EMLU XiYi Operation P Xi Yi This instruction multiplies Xi register value and Yi register value and stores the result to the P register Flags _ Notes _ Examples EMUL X1Y0 of Words 1 21 98 ELECTRONES S3CC11B FC11B CalmMAC1616 EMUL multiply w One Parallel Move Format EMUL XiYi lt dest gt lt src gt lt dest gt lt src gt Ai Mj Ai MjSR Ai MjSL mgx rps Operation P lt Xi Yi lt dest gt lt lt src gt This instruction multiplies Xi register value and Yi register value and stores the result to the P register This instruction also stores source operand from data memory or 16 bit higher portion of the MAj register to the destination register Flags When dest is Ai Z Set if the value to Ai is zero by load Reset if not Set if overflow
185. is generated Reset if not Exclusive OR of V and MSB of result Refer to Chapter 2 for more detailed explanation about this convention ECP A 0486h ECPC A ECP D RPO 1 2 when op is simm 16 ELECTRONES S3CC11B FC11B CalmMAC1616 2 ECP Um Compare Accumulator w One Parallel Move Format ECP Ai Ci Cj rps Operation Ai Ci Cj lt rps This Instruction compares the values of Accumulator Ai A or B register and Ci C or D register by subtracting Ci from Ai Content of Accumulator Ai is not changed This instruction also stores a source operand from memory or register to the destination register or memory location Flags C Set if carry is generated by addition Reset if not 2 Set if result is zero by addition Reset if not V Set if overflow is generated by addition Reset if not N Exclusive OR of V and MSB of result by addition Refer to Chapter 2 for more detailed explanation about this convention Notes None Examples ECP B D C ORP2 S1 of Words 1 ELECTRONES 21 69 CalmMAC1616 S3CC11B FC11B ECR Clear MA Accumulator Format ECR Mi Operation MAi lt 0 This Instruction clears the value of 36 bit MAi MAO or MA1 accumulator The extension nibble of selected MA accumulator is also cleared Flags 0 Notes VMi denotes for VM0 or VM1 according to Mi Examples ECR MA1 of Words 1 21 70 ELECTRONES S3CC11B FC11B CalmMAC1616 EDECC EDECCT Decrement with Carry
186. ister a nere 6 101 Subtract Large Immediate 6 102 Subtract 5 bit Immediate rrr ay ua a setene sides 6 103 Software 6 104 VIP 6 105 estet 6 106 Test ua kisi 6 107 Test Large Immediate an Il eee at e ask da Ds 6 108 n E 6 109 XOR EP 6 110 XOR Small Immediate pasa tete Severe lie 6 111 XOR Earge Immediate 2 tre ec e Ue mtt pao te ot na 6 112 S3CC11B FC11B MICROCONTROLLER S3CC11B FC11B PRODUCT OVERVIEW INTRODUCTION PRODUCT OVERVIEW The S3FC11B is a calmRISC16 and MAC1616 core based CMOS single chip microcontroller It contains ROM RAM 77 I O pins programmable 8 16 bit timer counters CODEC PLL 4 ch A D converter SSSEG x 8COM LCD controller driver and etc The S3FC11B can be used for dedicated control functions in a variety of applications and is especially designed for application with voice synthesizer voice recognition or etc FEATURES Memory e 24K x 16 bits program memory mtp flash ROM e 8Kx 16 bits data memory mtp flash ROM e 10K x 8 bits data memory excluding LCD RAM 77 Pins e 33 pins e 44 pins Sharing with segment drive o
187. ister The bit field of SDOE and SD3E is the same as other index register SDi The index extension registers are enabled when the XSD bit of MSRO register is set Otherwise those are disabled If the extension index registers are enabled index values for indirect addressing becomes to 8 bit during addressing with RPO and RP3 pointer register and current index register becomes the extended index register instead of the regular index register i e When a index register is read or written by a load instruction SDOE register or SD3E register is selected as a source operand or a destination operand instead of SDO or SD3 register For each of SDO SDOE or SD3 SD3E only one register is accessible at a time 21 18 ELECTRONES S3CC11B FC11B CalmMAC1616 DATA MEMORY SPACES AND ORGANIZATION The CalmMAC16 DSP coprocessor has only data memory spaces The program memory can only be accessed by CalmRISC host processor The data memory space is shared with host processor The CalmRISC has 22 bit data memory address so it can access up to 4M byte data memory space The CalmMAC16 access data memory with 16 bit width It can access upto 64K word word 2 bytes The data space is divided into a lower 32K word X data space and a higher 32K word Y data space When two data memory access are needed in an instruction one is accessed in X data space and the other is accessed in Y memory space When one data memory access is needed the access is occurred in X or Y
188. it Multiplier Accumulator MAi MAO or MA1 register and op together and stores the result back into Multiplier Accumulator MAi The PSH means 16 bit arithmetic right shifted P register value Flags VMi Set if result is overflowed to guard bits Reset if not MV Set if guard bit is overflowed Unchanged if not Notes VMi denotes for VMO or VM1 according to Mi Examples EADD MAO P EADD 1 PSH of Words 1 21 64 ELECTRONES S3CC11B FC11B CalmMAC1616 EADD _ Add Multiplier Accumulator w One Parallel Move Format EADD Mi P dest src dest src mgx rps An rps rpd mga rpd P Operation MAi MAi P dest lt src This instruction adds the values of 36 bit Multiplier Accumulator or register and Product Register P together and stores the result back into Multiplier Accumulator MAi This instruction also stores source operand from memory or register to destination register or memory Flags VMi Set if result is overflowed to guard bits Reset if not MV Set if guard bit is overflowed Unchanged if not Notes VMi denotes for VMO or VM1 according to the destination Mi Examples EADD MAO P YO RP1 S1 EADD RP2 S0 EADD P QRPO DO of Words 1 ELECTRONES 21 65 CalmMAC1616 S3CC11B FC11B EBK Pointer Index Register Bank Select Format EBK imm 4 Operation MSR2 15 12 imm 4 This instruction loads
189. its Schmitt trigger input Push pull output N channel open drain output 1 Alternative function TBOUT output 5 4 3 2 1 0 Alternative function TOOUT TOPWM output 9 10 ELECTRONES S3CC11B FC11B VO PORTS P3CONL Port 3 Control Register Low 3F002DH Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 3 3 ADS TOCLK Configuration Bits Schmitt trigger input TOCK input Push pull output EVEN N channel open drain output Alternative function AD3 input 5 4 P3 2 AD2 Configuration Bits op 4 SSS 3 2 P3 1 AD1 Configuration Bits o ofi ferme 1 0 P3 0 ADO Configuration Bits 0 Senmittiggerinput __ o t Pushpuloupt o O N channel open drain output Alternative f Alternative function ADO input ELECTRONES 9 11 PORTS S3CC11B FC11B P3PUR Port 3 Pull Up Resistors Enable Register 3F002EH Reset Value 0 0 0 0 0 0 0 0 Read Write R z R W R W R W R W R W R W R W 7 P3 7 s Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 6 P3 6 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 5 P3 5 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 4 P3 4 s Pull up Resistor Enable Bit isable pull up resistor nable pul
190. l up resistor 1 m 3 P3 3 s Pull up Resistor Enable Bit isable pull up resistor nable pull up resistor 1 m 2 P3 2 s Pull up Resistor Enable Bit isable pull up resistor nable pull up resistor m 1 P3 1 s Pull up Resistor Enable Bit isable pull up resistor nable pull up resistor m 0 P3 0 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 9 12 ELECTRONES S3CC11B FC11B VO PORTS P4CONH Port4 control Register High 3F0030H Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 P4 7 SEG6 Configuration Bits 0 o Schmitt trigger input ________ EDEN Push pull output N channel open drain output Alternative function SEG6 output 5 4 P4 6 SEG5 Configuration Bits Fe r mswdopu 3 2 P4 5 SEG4 Configuration Bits Neman O 1 0 P4 4 SEG3 Configuration Bits aps o t Puhpuloupt S O N channel open drain output Alternative function SEG3 output ELECTRONES 9 13 VO PORTS 3CC11B FC11B P4CONL Port 4 Control Register Low 3F0031H Bit Identifier 7 6 5 3 2 o Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 P4 3 SEG2 CCLK Configuration Bits Schmitt trigger input Push pull output 1 N channel open drain output Alternative function SEG2 or CCLK output 5 4 3 2 Sch
191. lities The bit reverse addressing is useful for radix 2 FFT Fast Fourier Transform calculations The CalmMAC16 DSP coprocessor does not support the bit reverse addressing itself But it supports the bit field reverse capabilities in the form of instruction The instruction selects a source address pointer and performs bit reverse operation according to the bit field specified in bit 15 to bit 13 of MC1 register Refer to Figure 21 9 The result bit pattern is written to the current bank RP3 register In this way RP3 has a bit reversed address value of source pointer value Note that the data buffer size is always a power of 2 up to 2 Index Extension When an instruction with indirect addressing is executed the current value of selected address pointer register RPi provides address on XA and YA buses Meanwhile the current address is incremented by the value contained into the selected index value contained into the selected bit field of selected index register and stored back into RPi at the end of instruction execution The 4 bit index values can be considered as a signed number so the maximum increment value is 7 0111b and the maximum decrement value is 8 1000b If the 4 bit index value is insufficient for use the index values can be extended to 8 bit values when RPO or RP3 register is selected as an address pointer register In this case all index values are extended to 8 bit by concatenating with SDOE or SD3E reg
192. lmRISC16 When the external condition corresponding to EC 2 is set the program branches to the target address BRAD has a delay slot The even offset eoffset 8 is encoded to 7 bit signed offset in instruction map by dropping the least significant bit 6 8 ELECTRONES S3CC11B FC11B INSTRUCTION SET BNZD R6 R7 eoffset 8 In the branch instruction the target address is PC 2 eoffset 8 The immediate value eoffset 8 is sign extended to 22 bit and then added to PC 2 BNZD R6 eoffset 8 instruction branches to the target address if ZO flag is cleared BNZD R7 eoffset 8 instruction branches if Z1 flag is cleared Before the branch operation the instruction decrements R6 R7 updates Z0 Z1 flag according to the decrement result and then executes the instruction in the delay slot The instruction is used to manage loop counter with just one cycle overhead In the end of the loop the value of R6 R7 is 1 When the instruction in the delay slot read the Z0 Z1 flag the result after the decrement is read The even offset eoffset 8 is encoded to 7 bit signed offset in instruction map by dropping the least significant bit JMP JPT JPF JSR addr 22 The target address of the instructions is addr 22 JMP always branches to the target address JPT branches to the target address if the T flag is set JPF branches if the T flag is cleared JSR always branches to the target address with saving the return address PC 4 into A14 The instructions are 2
193. loaded into memory CalmRISC16 LINKER Calm8LINK The CalmRISC16 Linker combines Samsung object format files and library files and generates absolute machine code executable hex programs or binary files for CalmRISC16 MCU and its MAC1616 and MAC2424 coprocessors It generates the map file which shows the physical addresses to which each section and symbol is bounded start addresses of each section and symbol and size of them It runs on WINDOWS95 compatible operating systems ELECTRONICS 26 1 DEVELOPMENT TOOLS S3CC11B FC11B EMULATION PROBE BOARD CONFIGURATION JTAG10 JTAG20 osc1 N 00000 0000000000 o 000006 Voc 6000000 ON Sub 000 X TAL osc X TAL Main X TAL User Vss al FF Y ROM 0 b Figure 26 1 Emulation Probe Board Configuration 20 pin normal Pitch 2 54mm JTAG RXD ETCK MCLK MCLK HN NN MC SM 6 18 20 NOTE 10 pin is not used 26 2 ELECTRONICS S3CC11B FC11B DEVELOPMENT TOOLS USE CLOCK SETTING FOR EXTERNAL CLOCK MODE Proper crystal and capacitors for main clock should be inserted into pin socket on the IE Board as follows Y2 aer For sub clock mode a crystal 32 768 kHz and capacitors should be inserted into pin socket on the IE Board as follows SUB CLOCK SETTING XTIN ATOU L X Tal NOTE The value of resistor is 0 KQ THE LOWPASS FILTER FOR PLL R MLPF 20k C C 10
194. lue eoffset 13 is sign extended to 22 bit and then added to PC 2 In general the 13 bit offset field appears as a label in assembly programs If the instruction in the delay slot reads the value of A14 the value PC 4 is read The even offset eoffset 13 is encoded to 12bit signed offset in instruction map by dropping the least significant bit BRA BRAD BRT BRTD BRF BRFD eoffset 11 In the branch instructions the target address is PC 2 eoffset 11 The immediate value eoffset 11 is sign extended to 22 bit and then added to PC 2 The D in the mnemonic stands for a delay slot In general the 11 bit offset field appears as a label in assembly programs BRA and BRAD instructions always branch to the target address BRT and BRTD instructions branch to the target address if T flag is set BRF and BRFD instructions branch to the target address if T flag is cleared BRAD BRTD BRFD instructions are delay slot branch instructions therefore the instruction in the delay slot is executed before the branch to the target address or the branch decision is made The even offset eoffset 11 is encoded to 10 bit signed offset in instruction map by dropping the least significant bit BRA BRAD EC 2 eoffset 8 In the branch instructions the target address is PC 2 eoffset 8 The immediate value eoffset 8 is sign extended to 22 bit and then added to PC 2 The EC 2 field indicates one of the 4 external conditions from ECO to EC3 input pin signals to Ca
195. lue of 36 bit Multiplier Accumulator MAi and stores the result back into the same Multiplier Accumulator MAi This instruction also stores source operand from memory or register to destination register or memory Flags VMi Set if result is overflowed to guard bits Reset if not MV Set if guard bit is overflowed Unchanged if not Notes VMi denotes for VMO or VM1 according to Mi Examples ESUB MAO P YO RP1 S1 ESUB MA1 P C RP2 S0 ESUB MA1 P RP0 D0 of Words 1 21 130 ELECTRONES S3CC11B FC11B ETST rest Format Operation Flags T Notes Examples of Words ETST cct op op T EC3 if cct is true lt op gt lt 1 else lt op gt lt 0 CalmMAC1616 This instruction sets the T flag of MSRO register or EC 3 output port of CalmMAC16 to 1 if condition specified in cct field is evaluated to truth Else resets op This instruction must be executed before executing the conditional instructions or branch instruction with EC3 as a condition code Set reset according to the condition ETST GT EC3 ETST NEG T ELECTRONES 21 131 CalmMAC1616 S3CC11B FC11B NOTES 21 132 ELECTRONES S3CC11B FC11B PROGR AM MEMORY ACCESS SPEED PROGRAM MEMORY ACCESS SPEED OVERVIEW The 0 had better be set logic 1 when the CPU clock is under 10 MHz It will be helped to reduction current consumption In order to enable Y Data ROM 11 is set to 1
196. mitt trigger input Push pull output N channel open drain output Alternative function SEG0 or CDX output 1 0 9 14 1 Push pull output 1 El N channel open drain output Not available Schmitt trigger input CDR input ELECTRONES S3CC11B FC11B VO PORTS P4PUR Port 4 Pull Up Resistors Enable Register 3F0032H Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 P4 7 s Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 6 P4 6 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 5 P4 5 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 4 P4 4 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 3 P4 3 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 2 P4 2 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 1 P4 1 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 0 P4 0 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor ELECTRONES 9 1 PORTS S3CC11B FC11B PAINT port 4 Interrupt Control Register 3F0033H Bit Identifier 5 4 3 2 0 0 0 0 0 0 0 0 Reset Value Read Write R W R W R W R W R W R W R W R W 7 P4 7 s Interrupt State Setting Bit 0 Falling edge interrupt 1
197. mory Flags VMi if result is overflowed to guard bits Reset if not Notes VMi denotes for VMO or VM1 according to destination Multiplier Accumulator Examples ELD MAO P X0 RP0 S1 ELD A RP1 S0 ELD P RP3 D1 A of Words 1 ELECTRONES 21 81 CalmMAC1616 S3CC11B FC11B ELD Load Other Registers or Memory Format ELD lt dest gt lt src gt lt dest gt lt src gt mg1 rps srg rps Pi rps rpd An rpd mg1 rpd srg rpd Pi rpui rpd1 adr 2 rpd1 adr 2 rpui rpdi adr 5 An adr 16 An mgx simm 16 mg simm 16 SA simm 5 mgid mgis mg2d mg2s sdid sdis srgd srgs mg An mgx An Pi mg1 mgl Pi Operation dest src This instruction load src value to dest If the width of immediate is less than the width of dest the immediate field is sign extended and if the width of src is more than the width of dest LSB part of src is written to dest Flags VMi Set if result is overflowed to guard bits Reset if not Notes VMi denotes for VMO or VM1 according to destination Mi if dest is Mi 21 82 ELECTRONES S3CC11B FC11B ELD NM Load Other Registers or Memory Continued Examples ELD 00 B ELD RPD1 5h RP2 ELD MCO 0486h ELD RPD1 MCO ELD XO Y1 of Words 1 2 when dest or src is adr 16 or imm 16 ELECTRONES CalmMAC1616 21 83 CalmMAC1616 S3CC11B FC11B ELD 6 _ Dual Load Forma
198. n Ai lt edisp 5 gt LDW Ai lt edisp 5 gt An The LDW Load Word Register Displacement instruction is used to load 2 word from or to data memory at the location specified by the register Ai and a 5 bit even displacement from 0 to 30 edisp 5 is encoded to 4 bit number by dropping the least significant bit 15 14 13 12 4 10 8 7 6 4 3 0 a 9 dv M 0 LDW An Ai lt edisp 5 gt En edisp 5 Rn edisp 5 2 1 LDW Ai lt edisp 5 gt An lt edisp 5 gt En DMI Ai lt edisp 5 gt 2 Rn None For memory transfer per word the byte address need to be aligned to be even Thus if Ai lt edisp 5 gt is an odd number it will be made even by clearing the least significant bit lt edisp 5 gt can denote an even number from 0 to 30 ELECTRONES 6 73 INSTRUCTION SET S3CC11B FC11B LDW 6 Load Word Register Disp Format Description Operation Exceptions Notes 6 74 LDW An Ai lt disp 16 gt LDW Ai lt disp 16 gt An The LDW Load Word Register Large Displacement instruction is used to load 2 word from or to data memory at the location specified by the register Ai and a 16 bit displacement M 0 LDW An Ai lt disp 16 gt En lt disp 16 gt Rn lt disp 16 gt 2 M 1 LDW Ai lt disp 16 gt An DM Ai lt disp 16 gt En
199. n it supports latching of the modified register in maximum minimum operations and bit reverse address generation This unit operates in parallel with other resources to minimize address generation overhead The RPU performs two types of arithmetics linear or modulo The RPU contains four 16 bit indirect address pointer registers RPO RP3 also referred to RPi for indirect addressing two 16 bit direct address pointer registers RPDO RPD1 also referred to RPDi for short direct form addressing four 16 bit indirect index registers SDO SD3 also referred to SDi and its extensions SDOE and SD3E and two 16 bit modulo configuration registers MCO and MC1 also referred to MCi for modulo control The MCO register has effect on RPO and RP1 pointer register and the MC1 register has effect on RP2 and register In addition it contains four alternative bank pointer register RPOB RP3B four alternative index registers SDOB SD3B and two alternative bank extension index register SDOBE and SD3BE supported by an individual bank exchange All indirect pointer registers RPi and direct pointer registers RPDi can be used for both XA and YA for instructions which use only one address register In this case the X memory and Y memory can be viewed as a single continuous data memory space the bit 14 to bit O of RPi register and RPDi register defines address for X or Y memory and the bit 15 determines whether the address is for X memory or Y m
200. n specified by lt imm 13 gt Certain coprocessor operations set external conditions upon which branches can be executed see BRECn instructions The lt imm 13 gt should be greater or equal to 0x200 15 14 13 12 0 1 1 Perform a coprocessor operation by placing signals core output pins as follows Core output signal COPIR 12 0 lt imm 13 gt Core output signal nCOPID LOW None None ELECTRONES 6 47 INSTRUCTION SET S3CC11B FC11B DECC Decrement with Carry Format DECC Rn Description The DECC Decrement with Carry instruction is used to synthesize 32 bit decrement If register pair R0 R1 holds a 32 bit value R0 holds the least significant word the following instructions leave the 32 bit decremented value in R0 R1 DEC RO l this is implemented by ADD RO 1 DECC R1 DECC decrements the value of Rn by 1 only if the Carry flag stored in the T bit is clear and stores the result back in register Rn The T bit and the V flag are updated based on the result 15 14 13 12 11 10 9 8 7 6 5 4 3 0 Operation Rn Rn 1 T bit T bit Carry from Rn 1 T bit V flag Overflow from Rn 1 T bit if Rn R6 R7 20 21 1 T 0 Exceptions None Notes None 6 48 ELECTRONES S3CC11B FC11B INSTRUCTION SET DT Decrementand Test Format DT Rn Description The DT Decrement and Test instruction is used to decrement the value of a specified register and
201. n ARU The V bit indicates that the result of an arithmetic operation can not be represented in 16 bit accumulator register The V bit can be modified simultaneously by writing to MSRO register instruction N Bit 3 The N bit is a sign flag for ARU or BEU operation result This bit is set if ARU or BEU operation result value is a negative value and cleared otherwise The N flag is the same as the MSB of the output if current operation does not generate overflow If overflow is occurred during instruction execution the value of N flag is the negated value of the MSB of the output The N bit can be modified by instructions writing to MSRO register Z Bit 2 The Z bit is a zero flag for ARU or BEU operation result This bit is set when ARU or BEU operation result value is zero and cleared otherwise The Z bit can be modified by instructions writing to MSRO register explicitly Bit 1 The C bit is a carry flag for ARU or BEU operation result This bit is set when ARU or BEU operation generates carry and cleared otherwise The C bit is not affected by ELD instruction because this instruction does not generate carry all the times The C bit can be modified by instructions writing to MSRO register explicitly T Bit 0 The T bit is a test flag that evaluates various conditions when ETST cc T instruction is executed This flag value can be used as a condition during executing a conditional instruction instructions that have a suffix T
202. n XSD 0 Before Execution After Execution X0 3456h Y1 9ABCh RP1 no modulo 1001h RP3 no modulo 8001h Data in 1001h 4321h Data in 8001h A987h SD1 1F1Fh SD3 2E2Eh Figure 21 19 Indirect Addressing Example Dual Read Operation Indirect Addressing for Write Operation RP0 D0 RP0 D1 RP1 D0 1 01 RP2 D0 RP2 D1 RP3 D0 RP3 D1 One of the current pointer registers RPO RP1 RP2 RP3 points to one of the 64K data words The data location content pointed to by the pointer register is the destination operand The RPi pointer register is modified with one of two 4 bit or 8 bit destination index values DO or D1 field which reside in the index register after the instruction is executed The destination index values are sign extended to 16 bit and added to 16 bit pointer value in RPi register The RP1 and register can only use 4 bit source index value The RPO and register can use extended 8 bit source index value if XSD bit of MSRO register is set ELECTRONES 21 35 CalmMAC1616 ELD RP1 D0 B RP1 no modulo Data Loacation 20h SD1 Figure 21 20 Indirect Addressing Example Write Operation Direct Addressing Mode Short direct Addressing RPDO adr 5 RPD1 adr 5 Before Execution 8010h 0020h 0011h 1819h After Execution 8010h 0018h 8010h 1819h S3CC11B FC11B The data location one of the 64K data word is one of the source operand or destin
203. n when BNZD instruction with R6 is executed e 71 zero flag of R7 set when R7 equals zero and used as the branch condition when BNZD instruction with R7 is executed PM privilege mode bit PM 1 for privilege mode and PM 0 for user mode e flag set clear as a result of an ALU operation FE IE TE and PM bits can be modified only when PM 1 privilege mode The only way to change from user mode to privilege mode is via interrupts including SWI instructions The reserved bit of SR from bit 7 to bit 14 can be used for other purposes without any notice Hence programmers should not depend on the value of the reserved bits in their programming The reserved bits are read as 0 value ELECTRONES 3 3 Calm16Core S3CC11B FC11B PIPELINE STRUCTURE CalmRISC16 has a 5 stage pipeline architecture It takes 5 cycles for an instruction to do its operation In a pipeline architecture instructions are executed overlapped hence the throughput is one instruction per cycle Due to data dependency control dependency and 2 word instructions the throughput is about 1 2 on the average The following diagram depicts the 5 stage pipeline structure x F p a mu w In the first stage which is called IF Instruction Fetch stage an instruction is fetched from program memory In the second stage which is called ID Instruction Decoding stage the fetched instruction is decoded and the appropriate operands if any for ALU oper
204. ne lt imm 5 gt is an unsigned amount ELECTRONES S3CC11B FC11B INSTRUCTION SET AND 1 AND Register Format AND Rn Ri Description AND AND Register instruction is used to perform bitwise AND operation on two values in registers Rn and Ri The result is stored in register Rn The T bit is updated based on the result 15 14 13 12 11 8 7 6 5 4 3 0 m Operation Rn Rn amp Ri T bit Rn amp Ri 0 R6 R7 20 71 flag Rn amp Ri 0 Exceptions None Notes None ELECTRONES 6 29 INSTRUCTION SET S3CC11B FC11B AND 2 AND Small Immediate Format Description Operation Exceptions Notes 6 30 AND RO lt imm 8 gt The AND AND Small Immediate instruction is used to perform an 8 bit bitwise AND operation on two values in register RO and lt imm 8 gt The result is stored in register RO The T bit is updated based on the result 15 14 43 12 1l 10 9 8 7 0 RO RO amp lt imm 8 gt T bit amp lt imm 8 gt 7 0 0 None The register used in this operation is fixed to RO Therefore the operand should be placed in RO before this instruction executes lt imm 8 gt is zero extended to a 16 bit value before operation ELECTRONES S3CC11B FC11B INSTRUCTION SET AND 3 AND Large Immediate Format Description Operation Exceptions Notes AND Rn lt imm 16 gt
205. ng power down mode STOP mode Figure 7 1 Phase Locked Loop Circuit Diagram ELECTRONES 7 1 PLL Phase Locked Loop S3CC11B FC11B PLLCON PLL Data Register 3F0076H Bit Identifier NEHME ajaa Reset Value _ 0 0 Read Write _ R W R W 7 2 Bits 7 2 41 fx Selection Bit ES Select fxin Select fout Note Where fxin is the main oscillator clock and fout is the PLL clock 0 PLL Enable Bit 0 Disable PLL 0 Enable PLL PLLDATA PLL pata Register 3F0077H Reset Value _ 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W 7 Bits7 6 5 Pre Scaler Bits fxin 2 N 0 1 and 2 4 2 Feedback Divider fvco N 8 N 0 2 4 6 1 0 Post Scaler Bits fvco N 1 N 0 1 2 and 3 7 2 ELECTRONES S3CC11B FC11B OSCCON oscillator Control Register Bit Identifier Reset Value Read Write 7 4 CLKCON clock Control Register Bit Identifier Reset Value Read Write 7 2 ELECTRONES PLL Phase Locked Loop 3F0003H __ 7 6 5 4 2 3 0 0 0 0 _ _ _ RW R W R W R W Bits 7 4 Not used Main Oscillator Control Bit Main oscillator RUN Main oscillator STOP BE Sub Oscillator Control Bit Sub oscillator RUN Sub oscillator STOP Bit 1 Not used System Clock Source Selection Bit Select main oscillator for system clock 1 Select sub oscillator for system clock 3F000
206. nstruction sets the 36 bit MAi accumulator to the plus or minus maximum value when selected MAi register overflows When no overflow occur the MAi register is not changed Flags VMi Reset Notes VMi denotes for VMO or VM1 according to Mi Examples ESAT MAO of Words 1 21 112 ELECTRONES S3CC11B FC11B CalmMAC1616 ESDO ESD1 ESD2 ESD3 source Destination Index Load Format ESDO ns imm 4 ESD1 ns imm 4 ESD2 ns imm 4 ESD3 ns imm 4 Operation Secified SDi register bit field in ns field lt imm 4 This instruction loads 4 bit immediate value to the specified bit field of current bank SDi register Only 4 bit field of 16 bit value is changed Flags _ Notes If XSD bit of MSR0 register is 1 the selected register is the extended index registers SD0E and SD3E Else the selected register is the regular index register SD0 and SD3 Examples DO DO 3h ESD1 S1 Fh of Words 1 ELECTRONES 21 113 CalmMAC1616 S3CC11B FC11B ESEC0 ESEC1 ESEC2 El Selection Field Load Format ESECO stimm 4 ESEC1 imm 4 ESEC2 imm 4 Operation Specified 1 0 2 field of MSR2 register lt imm 4 This instruction loads 4 bit immediate value to the specified bit field of MSR2 register Only 4 bit field of 16 bit value is changed Flags _ Notes _ Examples ESECO 8h ESEC1 Fh of Words 1 21 114 ELECTRONES S3CC11B FC11B CalmMAC1616 ESFT Logical Shift by Barrel Shifter Format ESFT asr as
207. nto the writing mode When 12 5 V is applied FLASH is in writing mode and when 3 3 V is applied FLASH is in reading mode When FLASH is operating hold GND Chip initialization Logic power supply pin Vpp should be tied to 3 3 V during programming Vep TEST 100 QFP 19 Power supply for FLASH ROM cell writing indicates that FLASH 25 4 ELECTRONES S3CC11B FC11B DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easyto use development support system in turnkey form The development support system is configured with a host system debugging tools and support software For the host system any standard computer that operates with windows95 98 NT XP as its operating system can be used One type of debugging tool including hardware and software is provided the effective cost and powerful in circuit emulator InvisibleMDS for CalmRISC16 Samsung also offers support software that includes debugger Compiler Assembler and a program for setting options CalmSHINE IDE INTEGRATED DEVELOPMENT ENVIR ONMENT CalmRISC16 Samsung Host Interface for In circuit Emulator CalmSHINE is a multi window based debugger for CalmRISC16 CalmSHINE provides pull down pop up and tool bar menus mouse support function hot keys syntax highlight tool tip drag and drop and context sensitive hyper linked help It has an advanced multiple windowed user interface that emphasizes ease of use Each window can be sized
208. on at the address of Ai disp 16 disp 16 is a positive displacement from 0 to FFFFh The general register Rn is one of RO to R7 In the instruction LDB Rn Ai disp 16 the bit data is zero extended to 16 bit data and then written into Rn In the instruction LDB Ai disp 16 the least significant byte of Rn is transferred to the memory LDB RO A8 disp 8 LDB A8 disp 8 Rn The instructions transfer 8 bit data between the general register RO and the memory location at the address of A8 disp 8 disp 8 is a positive displacement from 0 to 255 In the instruction LDB A8 disp 8 the 8 bit data is zero extended to 16 bit data and then written into RO In the instruction LDB A8 disp 8 RO the least significant byte of RO is transferred to the memory LDB Rn Ai Rj LDB Ai Rj Rn The instructions transfer 8 bit data between the general register Rn and the memory location at the address of Ai Rj The value of Rj is zero extended to 22 bit value The general register Rn is one of the 8 registers from RO to R7 In the instruction LDB Rn Ai Rij the 8 bit data is zero extended to 16 bit data and then written into RO In the instruction LDB Ai Rj Rn the least significant byte of Rn is transferred to the memory 6 6 ELECTRONES S3CC11B FC11B INSTRUCTION SET LD REGISTER PROGRAM MEMORY LDC Rn Ai The instruction transfers 16 bit data to Rn from program memory at the ad
209. on is executed The source index values are sign extended to 16 bit and added to 16 bit pointer values in RPi register The RP1 and RP2 register can only use 4 bit source index value The RPO and RP3 register can use extended 8 bit source index value if XSD bit of MSRO register is set Indirect Addressing for Dual Read Operation i 0 1 and RP3 Si i 0 1 RP1 Si i 0 1 and RP3 Si 0 1 One of the current bank pointer registers RPO or RP1 points to one of the lower 32K data words X data memory and the current bank RP3 pointer register points to one of the upper 32K data words Y data memory The data location contents pointed to by the pointer registers are the source operands The pointer registers are modified with one of two 4 bit 8 bit source index values 50 or S1 field which reside in the index register after the instruction is executed The source index values are sign extended to 16 bit and added to 16 bit pointer values in pointer registers The RP1 register can only use 4 bit source index value The RPO and RP3 register can use extended 8 bit source index value if XSD bit of MSRO register is set EADD A RP0 S1 When XSD 1 Before Execution After Execution 8010h RPO no modulo 0010h Data Loacation 10h 0011h SDOE 0122h SDO F333h Figure 21 18 Indirect Addressing Example Single Read Operation 21 34 ELECTRONES S3CC11B FC11B CalmMAC1616 ELD X0 RP1 S0 Y1 RP3 S1 Whe
210. on is forced to the pipeline The initial value of PM bit is 1 that is in privilege mode and the initial values of other bits in SR register are 0 All other registers are not initialized i e unknown When nFIQ an input pin CalmRISC16 core signal is active transition from 1 to 0 UMP addr 22 instruction is automatically executed by CalmRISC16 The address of FIQ interrupt service routine is in 000002h i e FIQ vector address of the program memory i e JMP 6 h00 PM 000002h The return address is saved in SPCH_FIQ SPCL FIQ register pair and the SR value is saved in SSR FIQ register PM bit is set FE IE and TE bits are cleared When RET FIQ instruction is executed SR value is restored from SSR FIQ and the return address is restored into PC from SPCH FIQ SPCL_FIQ When nIRQ signal an input CalmRISC16 core is active transition from 1 to 0 JMP 6 h00 PM 000004h instruction is forced to the instruction pipeline The return address is saved in SPCH SPCL register pair and the SR value is saved in SSR IRQ register PM bit is set IE and TE bits are cleared When RET IRQ instruction is executed SR value is restored from SSR IRQ and return address is restored to PC from SPCH_IRQ SPCL_IRQ When bit is set interrupt happens and JMP 6 h00 PM 000006h instruction is executed right after each instruction is executed interrupt uses the saved registers of IRQ
211. ontrol Register 3F0038H Reset Value _ 0 0 0 0 Read Write _ _ _ _ R W R W R W R W 7 4 Bits 7 4 3 2 P6 7 SEG22 P6 4 SEG19 Configuration Bits Alternative function SEG18 SEG15 signal output 9 20 ELECTRONES S3CC11B FC11B VO PORTS P7CON Port 7 Control Register 3F003AH Reset Value _ _ 0 0 0 0 Read Write R W R W R W R W 7 4 Bits 7 4 3 2 P7 7 SEG30 P7 4 SEG27 Configuration Bits Schmitt trigger input oja Schmitt trigger input Pull up resistor enable 1 Push pull output Alternative function SEG30 SEG27 signal output 1 0 P7 3 SEG26 P7 0 SEG23 Configuration Bits KEE Schmitt trigger input fo i Schmitt trigger input Pull up resistor enable 1 Push pull output Alternative function SEG26 SEG23 signal output ELECTRONES 9 21 S3CC11B FC11B PORTS P8CON Port 8 Control Register 3F003CH Reset Value _ _ 0 0 0 0 Read Write _ _ _ _ R W R W R W R W 7 4 Bits 7 4 3 2 P8 4 SEG35 Configuration Bits EN Schmitt trigger input Schmitt trigger input Pull up resistor enable 1 0 Schmitt trigger input Schmitt trigger input Pull up resistor enable Alternative function SEG31 SEG34 signal output ELECTRONES S3CC11B FC11B VO PORTS P9CON Port 9 Control Register 3F003EH Bit Identifier 7 5 5 4 3 2 Oo Reset Value _ _ 0 0 0 0 0 0 Read Write _ _ R W R W R W R W R W R W 7 6 Bits 7 6 5 4 9
212. onu LL 4 2 Break Exception nt usss ia re bat ente et tel es tau id bua Fe ee etu tute a Ln Eoo jamt 4 2 Interrupt Sources edere orte tee ctt eder 4 3 Interrupt Str etUre uu Rte bete De i 4 4 Interrupt Control Register unica eiie EU TER Potes ceo ae oe dea 4 5 Interrupt Masking Register u nana uqu 4 5 Interrupt Proirity RegisI rz eee an yQ isuu mapu 4 5 Interrupt Prority Registers 3F0008H IPRL 9 4 8 Interr pt Id Register eret te e ee EA LL 4 9 S3CC11B FC11B MICROCONTROLLER Table of Contents continued Chapter 5 Memory Map OVOIVIQW ea fece uet SU 5 1 Chapter 6 Instruction Set Al Instructions s u tei o e e eR ER Ies ua x gU Ind arc TEE idae rer 6 1 ALUOP Register Immediate eve qne 6 2 ALWOP Register Register ee Tete Lan EE distet a dE Den PER nu usaq 6 3 ee ori Edere Eae Lits 6 4 ED Register Register oc Ladies o d Eee mete delet ee se eu peu o Ev E UC ske 6 4 LD Register Data Memory LD Data Memory Register a e 6 5 LD Register Program
213. oprocessor The register Rn is one 8 registers from RO to R7 NOP No operation BREAK The software break instruction activates nBRK signal and holds PA for one cycle It s for debugging operation ELECTRONK S 6 11 INSTRUCTION SET S3CC11B FC11B CALMRISC16 INSTRUCTION SET MAP Table 6 1 CalmRISC16 Instruction Set Map 8 15 7 0 AD Anam mer __ sumam m fil LD Rnfimm8 0001 tow me aise sea LDW aan nd 2 Ri ara 9 aloo iwmemem 102107 Low Gian eps 11 LDB Dn IAi disp 01 10 isp onewa LDW An QN disp4 howmew n EN KE e m vm emir womm m m SBC Rn Ri AND Rn Ri E mST OR Rn Ri OR RNA Ri 3 i 1 GE Rm 1 Ra Ri wu GE Ra 1 oo m m EQR 1111100 t o ojo m ram frfofofofofofo m frfofofofofofo sj1 sjs o m 6 12 ELECTRONES S3CC11B FC11B INSTRUCTION SET Table 6 1 CalmRISC16 Instruction Set Map Continued INCC Rn rm 5 5 5 5 5 5 5 5 5 SBC imm 16 AND Rn imm 16 OR Rn imm 16 XOR Rn imm 16 TST Rn imm 16 Dd GT Rn imm 16
214. or branch instructions with a delay slot no cycle waste is incurred if the delay slot is filled with a useful instruction or non NOP instruction Pipeline stalls due to resource conflicts occurs when two different instructions access at the same cycle the same resource such as the data memory and the program memory LDC data load from program memory instruction causes a resource conflict on the program memory Bit operations such as BITR and BITS read modify write instructions cause a resource conflict on the data memory 3 4 ELECTRONES S3CC11B FC11B Calm16Core INTERRUPTS In CalmRISC16 there are five interrupts RESET FIQ IRQ TRQ SWI The RESET FIQ and IRQ interrupts correspond to external requests TRQ and SWI interrupts are initiated by an instruction therefore in a deterministic way The following table shows a summary of interrupts Name Pron Address RESET 000000h Hardware Reset FQ 8 000002h Fast Interrupt Request ma 5 000004h Interrupt Request TRQ 000006h Trace Request SWI 000008h Software Interrupt 0000feh When nRES an input pin CalmRISC16 core signal is released transition from 0 to 1 UMP addr 22 is automatically executed by CalmRISC16 Among the 22 bit address addr 22 the most significant 6 bits are forced to 0 and the least significant 16 bits are the contents of 000000h i e reset vector address of the program memory In other words JMP 6 h00 PM 000000h instructi
215. p Resister of 1 1 CDR P4 0 CDR P4 0 P Enable Pull Up Resister of CDR P4 0 NOTE The pull up resistor of CDR P4 0 is automatically controlled as the above timing diagram when the pin is selected as input with pull up resistor and SIO for external codec is enabled Figure 20 3 16 Bit SIO Timing Diagram for External Codec 20 6 ELEGTRONK 5 S3CC11B FC11B CalmMAC1616 CalmMAC1616 INTRODUCTION CalmMAC16 is 16 bit high performance fixed point DSP coprocessor for CalmRISC16 microcontroller CalmMAC16 is designed for the mid to high end audio applications which require low power consumption and portability It mainly includes a 16 bit arithmetic unit ARU a barrel shifter amp exponent unit BEU a 16 bit x 16 bit multiplier accumulation unit MAU and a RAM pointer unit RPU for data address generation Main datapaths are constructed to 16 bit width for audio applications CalmMAC16 is designed to be the DSP coprocessor for CalmRISC16 microcontroller It receives 13 bit instruction code and command information from CalmRISC16 via special coprocessor interface and sends internal status information to host processor CalmRISC16 through external condition port ARCHITECTURE FEATURES 16 bit barrel shifting with support for multi precision capability 16 bit exponent evaluation with support for multi precision capability 4data address RAM pointers with post modification amp modulo capability 4 index
216. p resistor of CDR P4 0 is automatically controlled as the above timing diagram when the pin is selected as input with pull up resistor and SIO for external codec is enabled Long Frame Sync Timing SIO INT for External Interval Time 256 fcsio 1 1 14 Interval Time 256 csio i I Disable Pull Up Resister of A Disable Pull Up Resister of y CDR P4 0 CDR P4 0 Enable Pull Up Resister of CDR P4 0 NOTE The pull up resistor of CDR P4 0 is automatically controlled as the above timing diagram when the pin is selected as input with pull up resistor and SIO for external codec is enabled Figure 20 2 8 Bit SIO Timing Diagram for External Codec ELECTRONES 8 16 BIT SERIAL INTERFACE FOR EXTERNAL CODEC S3CC11B FC11B Short Frame Sync Timing CFS CDX CDR SIO INT for External Codec 1 nterrupt Interval Time 256 fcsio I Disable Pull Up Resister of Disable Pull Up Resister of gt CDR P4 0 CDR P4 0 Enable Pull Up Resister of CDR P4 0 NOTE The pull up resistor of CDR P4 0 is automatically controlled as the above timing diagram when the pin is selected as input with pull up resistor and SIO for external codec is enabled Long Frame Sync Timing SIO INT for External Codec Interval Time 256 fcsio i 1 amp interrupt Interval Time 256 fcsio 1 1 1 Disable Pull Up Resister of Disable Pull U
217. peration Exceptions Notes POP Rn Rm POP Rn The POP instruction load one or two 16 bit data from software stack to general registers In the instruction of POP Rn Rm there are some restrictions on Rn and Rm Rn and Rm should not be R15 If Rn is one of the 8 registers from RO to R7 Rm should also be one of them If Rn is one of the registers from R8 to R14 Rm should also be one of them For example POP R7 R8 is illegal If Rn is the same as Rm pop operation occurs only once POP Rn is equivalent to Rn 15 14 13 12 4 8 7 6 5 4 3 2 0 fifififofo f if Rn Rm POP Rn Rn DM SP 2 SP SP 2 else Rn DM SP 2 Rm DM SP 4 SP SP 4 None None ELECTRONES 6 81 INSTRUCTION SET S3CC11B FC11B POP 2 Load Register from Stack Format Description Operation Exceptions Notes 6 82 POP An Am POP An The POP instruction load one or two 22 bit data from software stack to extended registers In the instruction of POP An Am there are some restrictions on An and Am Anand Am should not be A15 If Anis the same as Am pop operation occurs only once An is equivalent to POP An 15 14 43 12 4 10 8 7 6 5 4 3 2 0 if An Am POP An En lower 6 bits of DM SP 2 Rn DM SP 4 SP SP 4 else En lower 6 bits of DM SP 2 Rn DM SP 4 Em
218. ponents of the CalmMAC16 are e Multiplier Accumulator Unit MAU Multiplier Input Registers Output Register Multiplier Accumulators Saturation Logic Multiplier Accumulator Shifter 36 bit Arithmetic Unit Status Register e Arithmetic Unit ARU Accumulator Saturation Logic Accumulator Shifter 16 bit Arithmetic Unit Status Registers e Barrel shifter amp Exponent detection Unit BEU 16 bit Exponent Detector 16 bit Barrel Shifter Input Registers Output Registers e RAM Pointer Unit RPU 2 Modulo Address Generator Bit Reverse Generator Indirect Address Pointers Index Registers Extended Index Registers Direct Pointers Modulo Configuration Registers Alternative Bank Pointers Alternative Bank Index Registers Alternative Bank Extended Index Registers ELECTRONES X1 YO Y1 P MAO MA1 MSR1 A B C D MSR0 MSR2 SA SI SG SR RP0 RP1 RP2 RP3 SD0 SD1 SD2 SD3 SD0E SD3E RPD0 RPD1 MC0 MC1 RP0 RP1 RP2 RP3 SD0 SD1 SD2 SD3 SD0E SD3E 21 3 CalmMAC1616 S3CC11B FC11B MULTIPLIER AND ACCUMULATOR UNIT The Multiplier and Accumulator Unit contains two main units the Multiplier Unit and the Accumulator Unit The detailed block diagram of the Multiplier and Accumulator Unit is shown in Figure 21 2 YB 15 0 XB 15 0 Shifter Shifter 16 x 16 Multiplier 36 bit Adder Saturation Figure 21 2 Multiplier and Accumulator Unit Block Diagram 21 4 E
219. put and software assignable pull ups 76 83 S3CC11B FC11B dud Shared Pins AD3 TOCLK TOOUT TOPWM TO CAP BUZ T1CLK TAOUT TBOUT CDR CDX SEGO CFS SEG1 CCLK SEG2 INT4 INT7 SEG3 SEG6 SEG7 SEG13 SEG14 SEG15 SEG22 SEG23 SEG30 ELECTRONES S3CC11B FC11B PRODUCT OVERVIEW Table 1 1 S3CC11B FC11B Pin Description Continued Type Description Circuit Shared Pins Type P8 0 P8 4 Same general characteristics as port6 84 88 SEG31 82 86 SEG35 P9 0 P9 7 Same general characteristics as port6 89 96 COM7 COMO 87 94 ADINN __ Analog negative input pin in NO _ o VO ADINP Analog positive input pin ADGAIN Analog input gain control pin VREFOUT Vref output pin DAOUT COMO COM7 NES LCD common data output pins SEGO I O LCD segment data output pins 9 SEG1 SEG2 SEG3 SEG6 SEG7 SEG13 I O LCD segment data output pins P5 7 P6 0 P8 4 VLC1 LCD power supply pins INTO INT2 I O External interrupt input pins P0 0 P0 2 INT3 P0 3 INT4 INT7 P4 4 4 7 4 wa vO 4 VO E O PLL loop filter pin fe P9 7 P9 0 94 87 P4 3 CCLK P4 4 P4 7 INT4 INT7 P5 0 P5 6 a NEN Digtal to analog convener ouputpin 9 E SEG14 SEG15 SEG35 TBOUT 49 47 P3 7 s so wo data outpu
220. put can be used for normal I O or TOCLK function A D Converter Control Register ADCON10 51H R W EOC bit is read only Start or disable bit 0 Disable operation 1 Start operation A D input pin selection bits This bit is cleared automatically 00 ADO after End of Conversion Always logic zero 01 AD1 10 AD2 AD3 Clock Selection bits 00 fxx 16 01 fxx 8 10 fxx 4 11 fxx 1 End of conversion bit 0 Not complete Conversion 1 Complete Conversion Figure 16 1 A D Converter Control Register ADCON10 16 2 ELECTRONICS S3CC11B FC11B 10 BIT A D CONVERTER owe sm Figure 16 2 A D Converter Data Register ADDATAH10 ADDATAL10 INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block the analog input voltage level is compared to the reference voltage The analog input level must remain within the range AVss to Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step The reference voltage level for the first conversion bit is always 1 2 AVper BLOCK DIAGRAM ADCON10 2 1 ADCON10 4 5 Select one input pin of the assigned pins Clock Selector ADCON10 0 AD C Enable To ADCON10 3 EOC Flag Analog Comparator Input Pins AD0 AD3 P3 0 P3 3 Successive Approximation Logic amp Register ADCON10 0 AD C Enable
221. r 0 W OI III TqNTIII e TT T i RPD1 101 RPD1 15 0 sdi Mnemonic Encoding Description 30 00 Current bank SDO 15 0 register 500 or SDOE Current bank SD2 15 0 register Current bank SD3 15 0 register SD3 or SD3E 21 40 ELECTRONES S3CC11B FC11B CalmMAC1616 A 15 0 register C 15 0 register D 1 D 15 0 register A 15 0 register B 15 0 register C 15 0 register D 15 0 register Mnemonic Encoding Description 0000 Current bank RPO 15 0 register RPO Current bank SD1 15 0 register set O Current bank SD2 15 0 register set 0 SDO 1 1100 Current bank SDO 15 0 register set 1 SD1 1 1101 Current bank SD1 15 0 register set 1 Current bank SD3 15 0 register set 0 Current bank SD2 15 0 register set 1 SD2 1 1111 Current bank SD3 15 0 register E ELECTRONES 21 41 set 1 CalmMAC1616 S3CC11B FC11B mga Mnemonic Encoding MAO 00 MA0 35 0 MAQ 31 16 register MA1 MA1 35 0 MA1 81 16 register Mnemonic Encoding Description YO 00 Y0 15 0 register 21 42 ELECTRONES S3CC11B FC11B CalmMAC1616 Encoding 00000 MAO 35 0 MAO 31 16 register MAOL 00001 MAO 15 0 register MA1 00010 MA1 35 0 MA1 31 16 register MA0 H H MA0SL 00101 Arithmetic left one bit shifted MA0 31 16 register Arithmetic right one bit shifted MA1 31 16
222. r CLD Dn lt imm 5 gt it is stored in Dn When data item is written to coprocessor it should be prepared in Di 15 14 43 12 4 10 9 8 4 3 2 0 pt 0 DA 4 0 lt imm 5 gt nCLDID 0 CLDWR 0 Dn lt imm 5 gt M 1 write DA 4 0 lt imm 5 gt nCLDID 0 CLDWR 1 lt imm 5 gt Di None This instruction has a delay slot because this instruction is 2 cycle instruction ELECTRONES S3CC11B FC11B INSTRUCTION SET CLRSR Clear SR Format CLRSR bs 3 Description The CLRSR Clear SR instruction is used to clear a specified bit in SR as follows CLRSR FE IE TE Z0 Z1 PM To clear the T bit one can do as follows CMP GT RO RO To turn ona specified bit in SR the SETSR instruction is used 15 14 13 12 1l 10 9 8 7 6 5 4 3 2 1 0 3 gt Operation SR lt bs 3 gt 0 Exceptions None Notes None ELECTRONES 6 39 INSTRUCTION SET S3CC11B FC11B CMP 1 Compare Register Format Description Operation Exceptions Notes 6 40 CMPmode Rn Ri The CMP Compare Register instruction is used to compare two values in registers Rn and Ri The allowed modes include GE Greater or Equal GT Greater Than UGE Unsigned Greater or Equal UGT Unsigned Greater Than and EQ Equal CMP subtracts the value of Ri from the value of Rn and performs comparison based on the result The contents of Rn and Ri are not changed
223. r address of the program memory i e JMP 6 h00 PM 000002h The return address is saved in SPCH FIQ SPCL_FIQ register pair and the SR value is saved in SSR FIQ register PM bit is set FE IE and TE bits are cleared When RET FIQ instruction is executed SR value is restored from SSR FIQ and the return address is restored into PC from SPCH FIQ SPCL_FIQ But the FIQ is not used in the S3CC11B IRQ EXCEPTION When nIRQ signal an input pin CalmRISC16 core is active transition from 1 to 0 JMP 6 h00 PM 000004h instruction is forced to the instruction pipeline The return address is saved in SPCH IRQ SPCL register pair and the SR value is saved in SSR IRQ register PM bit is set IE and TE bits are cleared When RET IRQ instruction is executed SR value is restored from SSR IRQ and return address is restored to PC from SPCH SPCL_IRQ TRQ EXCEPTION When TE bit is set interrupt happens and JMP 6 h00 PM 000006h instruction is executed right after each instruction is executed interrupt uses the saved registers of IRQ that is SPCH IRQ SPCL IRQ register pair and SSR IRQ to save the return address and SR respectively PM bit is set IE TE bits are cleared SWI EXCEPTION When SWI imm 6 instruction is executed the return address is saved in the register A14 and the value of SR is saved in SSR SWI Then the program sequence jumps to the address imm 6 4 PM bit is set IE
224. ration Multiplie register CalmMAC1616 Add Accumulator w One Parallel Move 1 EADD Ai Mi lt dest gt lt src gt lt dest gt lt src gt mgx rps Mi rps rpd mga rpd P 2 EADD Ai Ci Cj rps 1 Ai lt Ai Mi dest lt src 2 Ai Ai Ci Cj lt rps This instruction adds the values of 16 bit Accumulator Ai A or B register and higher 16 bit part of r Accumulator MAi MAO or 1 register or the value of 16 bit Accumulator Ci C or D together and stores the result back into Accumulator Ai This instruction also stores a source operand from memory or register to the destination register or memory location Flags C Z V N about th Notes Examples of Words Set if carry is generated by addition Reset if not Set if result is zero by addition Reset if not Set if overflow is generated by addition Reset if not Exclusive OR of V and MSB of result by addition Refer to Chapter 2 for more detailed explanation is convention Set if result is overflowed to guard bits Reset if not VMi denotes for VMO or VM1 according to Mi if dest is Mi EADD A MAO X0 RP0 S1 EADD B MA1 RP1 S0 EADD A MA1 RP3 D1 MAO EADD B D C RP2 S1 1 ELECTRONES 21 63 CalmMAC1616 S3CC11B FC11B EADD Multiplier Accumulator Format EADD Mi lt op gt lt op gt P PSH Operation MAi MAi op This instruction adds the values of 36 b
225. rce or destination register will be one of a set of pointer register RPO RP3 two sets of index register SDO 0 SD3_0 and SDO 1 SD3 1 and two sets of modulo control register MCO 0 MC1 0 and MCO 1 MC1 1 One of 16 registers itself specifies 4 bit address field With this addressing mode user can keep up to 4 sets of pointer registers 8 set of index registers and 8 set of modulo control registers at one time The short direct associated addressing uses only RPD1 register as a page value The LSB 6 bits of RPDO register is not used at all ELECTRONES 21 37 CalmMAC1616 S3CC11B FC11B ELD RPD1 3H SD0_0 Before Execution After Execution SD0 8010h 8010h RPD1 0088h 0088h Data Location 00a3h 0011h 8010h 15 6543 1 Address Generation 0000000010 11 1000 LHL RPD1 15 6 adr 2 SDO 0 Figure 21 23 Short Direct Associated Addressing Example Immediate Mode Short Immediate form I imm 4 form imm 5 The form I is used for 4 bit register field load ESDi instruction EBK instruction and instruction or masking pattern generation in ENMSK instruction The form II is used for one of the source operands The 5 bit value is right justified and sign extended to the 16 bit operand when the destination register has 16 bit width If the destination register has 16 bit width it is sign extended to the 16 bit operand Long Immediate imm 16 The long immediate form is used for one of the
226. rcuit 4 P0 4 P0 7 P1 4 7 4 0 1 8 Pin Circuit Type 5 0 3 aaa 1 9 Pin Circuit Type 6 P9 0 P9 9 ETE 1 10 Pin Circuit Type 7 acide ap e oec spa hu unda de Rue aga 1 11 Pin Circuit Type 7 P6 P7 P8 1 12 Pin Circuit Type 9 P4 1 P4 3 1 13 Pin Circuit Type 10 P4 4 P4 7 a 2 1 Program Memory Configuration 2 2 Data Memory mee 3 1 Register Structure 15 16 4 1 Interrupt Sources IRQ a a 4 2 Interrupt Sp S fedt eer taxe d et 4 3 Interrupt Priority Register 11 5 1 Memory Mapped 5 7 1 Phase Locked Loop Circuit Diagram 7 2 System Clock Circuit Diagram a m 7 3 External Loop Filter for PLL4 a a 9 1 Port Data Register Structure 10 1 Basic Timer amp Watchdog Timer Block 11 1 Watch Timer Block Diagram 12 1 Timer 0 Functional Block
227. register Cure bank Rorisojregsr O OO OOOO 1 1 01111 MC1 15 0 register so 01000 Current bank SD0 15 0 SD0E register 0 2 01010 Current bank SD2 15 0 register 3 01011 Current bank SD3 15 0 SD3E register 01100 SA 6 0 register x S 01101 SI 15 0 register e sa om PM wo no nae pan mm Bouea NOTE Grayed Field read only register RP RP RP MC MC SD 50 SD SD SA SI SG SR P H PL amis ELECTRONES 21 43 CalmMAC1616 S3CC11B FC11B MCO 15 0 register 1 MC1 15 0 register srg Mnemonic Encoding sa m seo asr Eoi m e er SR 11 SR 15 0 register asa gt fu 21 44 ELECTRONES S3CC11B FC11B CalmMAC1616 0101 MSRO 13 Encoding Deseription 1011 SR 15 0 register ELECTRONES 21 45 CalmMAC1616 S3CC11B FC11B Encoding emodO Mnemonic Encoding Mnemonic Encoding Description P H register 21 46 ELECTRONES S3CC11B FC11B CalmMAC1616 ELECTRONES 21 47 CalmMAC1616 S3CC11B FC11B Wnemomie ESLC T 0101 Arithmetic shift left 1 bit with Carry EINCC T 0110 Increment with Carry ea mm me gt _
228. registers with 2 extended index registers up to 8 bit index value 2 direct address RAM pointers for short direct addressing Min Max instruction with pointer latching and modification Division step in single cycle Conditional instruction execution capability Four Quaarant fractional integer 16 x 16 bit multiplication in single cycle 16 x 16 bit multiplication and 36 bit accumulation in a single cycle 16 bit arithmetic operation 2 32 bit multiplier accumulator with 4 bit guard 2 32K x 16 bit data memory spaces TECHNOLOGY FEATURES 0 35u triple metal CMOS technology 12ns cycle time at 3 0V 125C Worst Process condition Fully static design ELECTRONES 21 1 CalmMAC1616 S3CC11B FC11B BLOCK DIAGRAM Status Control Registers Interface Logic pd n 16 bit Exponent Detector 16 bit Barrel Shifter Figure 21 1 CalmMAC1616 Block Diagram The block diagram shows the main blocks that compose the CalmMAC16 Multiplier Accumulator Unit MAU Arithmetic Unit ARU Barrel shifter amp Exponent detection Unit BEU RAM Pointer Unit RPU Status Registers Interface Unit 21 2 ELECTRONES S3CC11B FC11B PROGRAMMING MODEL CalmMAC1616 In this chapter the important features of each unit in CalmMAC16 are discussed in details How the data memories are organized is discussed and data memory addressing modes are explained The major com
229. rnal Codec 3F004EH Reset Value _ 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W 7 Bit 7 6 8 16 Bit Serial I O Selection Bit elect 8 bit serial interface for external codec 1 elect 16 bit serial interface for external codec 5 3 Shift Clock Selection Bits He eio fesio fxin 8 fosio fxin 10 2 Frame Sync Type Selection Bit Select short frame sync type 1 Select long frame sync type Shift Clock Edge Selection DX at rising edges DR at falling edges 1 DX atfalling edges DR at rising edges 0 Shift Operation Control Bit Disable shift operation SIO for external codec 1 Enable shift operation SIO for external codec T ELECTRONES 20 8 16 BIT SERIAL INTERFACE FOR EXTERNAL CODEC S3CC11B FC11B CSIODATAH L Transmit Buffer CDR P4 0 CSIOCON 5 3 CSIOCON 2 CSIOCON 6 8 16 bit Frequency Timing and Shifter Dividing Control Circuit MSB CSIODATAH L Edge Selection Receive Buffer CSIOCON 0 CFS P4 2 CCLK P4 3 Figure 20 1 SIO Block Diagram for External Codec 20 4 ELECTRONES S3CC11B FC11B 8 16 BIT SERIAL INTERFACEFOR EXTERNAL CODEC Short Frame Sync Timing CDR SIO INT for External Codec Interval Time 256 fcsio Interrupt Interval Time 256 fcsio Disable Pull Up Resister of Disable Pull Up Resister of CDR P4 0 CDR P4 0 Enable Pull Up Resister of CDR P4 0 NOTE The pull u
230. rom A B C D 16 bit Exponent Figure 21 16 Barrel Shifter and Exponent Unit Block Diagram BARREL SHIFTER The barrel shifter performs standard arithmetic and logical shift and several special shift operations It is a 32 bit left and right single cycle non pipelined barrel shifter The barrel shifter receives the source operand from either one of the 16 bit two Ai A or B accumulator registers or 16 bit SI register It also receives the shift amount value from either one of the 16 bit two Ai accumulator registers or 7 bit SA register Because the maximum amount of shift is from 32 right shift 32 bit to 32 left shift 32 bit 7 bit shift amount is sufficient When Ai register is used as the shift amount register 7 LSBs of 16 bit register value are only valid If the shift value is greater than 32 or less than 32 the shifter generates the same result as shift 32 bit or shift 32 bit The amount of shifts is only determined by a value in the one of these three register and can not be determined by a constant embedded in the instruction opcode immediate shift amount is not supported The barrel shifter takes 16 bit input operand and 7 bit amount value and generates 32 bit shifted output values The destination of shifted value is two 16 bit shift output register SG and SR register The SG register holds the value of shifted out and the SR register holds the shifted 16 bit values The flags are affected as a result of the barrel shift
231. ruction ADC RO RO produces a single bit Rotate Left with Carry 17 bit rotate through the carry on RO ADC adds the value of register Rn and the value of the Carry flag stored in the T bit and the value of register Ri and stores the result in register Rn The T bit and the V flag are updated based on the result ELECTRONES 6 21 INSTRUCTION SET S3CC11B FC11B ADC 2 Add with Carry Immediate Format ADC Rn lt imm 16 gt Description The ADC Add with Carry Immediate instruction is used to synthesize 32 bit addition with an immediate operand If register pair RO R1 holds a 32 bit value RO holds the least significant word the following instructions leave the 32 bit sum with 87653456h in RO R1 ADD RO 3456h ADC R1 8765h ADC adds the value of register Rn and the value of the Carry flag stored in the T bit and the 16 bit immediate operand and stores the result in register Rd The T bit and the V flag are updated based on the result 15 14 43 12 1l 10 9 8 7 6 5 4 3 0 o ooo o o rL LT 3 Operation Rn Rn lt imm 16 gt T bit T bit Carry from Rn lt imm 16 gt T bit V flag Overflow from Rn lt imm 16 gt T bit if Rn R6 R7 Z0 Z1 flag Rn lt imm 16 gt 0 Exceptions None Notes This is a 2 word instruction where the 16 bit immediate follows the instruction word shown above Unlike 1 word instructions therefore fetching of ADC Rn lt imm 16 gt takes 2 cycles
232. s applied The XSD bit can be modified by writing to MSRO register or ER ES XS D instruction The XSD bit is cleared by a processor reset OP Bit 9 The OP bit indicates that saturation arithmetic in the ARU is provided or not when overflow is occurred during arithmetic operation The overflow protection can be applied to all of the four accumulator registers If this bit is set the saturation logic will substitute a limited value having maximum magnitude and the same sign as the source accumulator register during overflow If clear no saturation is performed and overflow is not protected by the CalmMAC16 The OP bit can be modified by writing to MSRO register or ER ES OP instruction The OP bit is cleared by a processor reset vs Bit 6 The VS bit is a overflow flag for BEU Barrel Shifter and Exponent Unit This bit is set if arithmetic overflow is occurred during shift operation or exponent evaluation on BEU registers When the instructions which performs BEU operation writes this bit as a overflow flag instead of V bit The VS bit indicates that the result of a shift operation can not be represented in 16 bit SR register or the source value of an exponent operation is all zero or all one The VS bit can be modified by writing to MSRO register instruction V Bit 5 The V bit is a overflow flag for ARU accumulators This bit is set if arithmetic overflow is occurred during arithmetic operation on a destination accumulator register i
233. s overflowed to guard bits Reset if not MV Set if guard bit is overflowed Unchanged if not Notes VMi denotes for VMO or VM1 according to the current MA bank Examples EMAD X1YO X0 RP0 S1 Y0 RP3 S0 of Words 1 ELECTRONES 21 87 CalmMAC1616 S3CC11B FC11B EMAX Maximum Value Load Format EMAX Ai lt op gt lt op gt Gi Ai Operation if op gt Ai Ai op RP3 previous address with RPi register This instruction conditionally loads op value to the one of 16 bit Accumulator Ai and latches the previous address value to the RP3 pointer when op is greater than or equal to Ai Otherwise no operation is performed Flags Set if carry is generated Reset if not 2 Set if result is zero Reset if not V Set if overflow is generated Reset if not N Exclusive OR of V and MSB of result Refer to Chapter 2 for more detailed explanation about this convention Notes Flags are generated from the operation Ai lt op gt Examples EMAX A C of Words 1 21 88 ELECTRONES S3CC11B FC11B CalmMAC1616 EMAX 2 Maximum Value Load w One Parallel Move Format EMAX Ai Ci Ci rps Operation if Ci gt Ai Ai lt Ci Ci rps RP3 previous address with RPi register This instruction conditionally loads Ci value to the one of 16 bit Accumulator Ai and latches the previous address value to the RP3 pointer when lt op gt is greater than or equal to Ai Ot
234. s the reference data value is less than or equal to lt the counter value and then the pulse is held to Low level for as long as the data value is greater than gt the counter value One pulse width is equal to x 256 Capture Mode In capture mode a signal edge that is detected at the TOCAP pin opens a gate and loads the current counter value into the TO data register You can select the rising or falling edges to trigger this operation Timer 0 also gives you capture input source the signal edge at the TOCAP pin You select the capture input by setting the value of the Timer 0 capture input selection bit in the port control register Both kinds of Timer 0 interrupts can be used in capture mode the Timer 0 overflow interrupt is generated whenever a counter overflow occurs the Timer 0 match capture interrupt is generated whenever the counter value is loaded into the TO data register By reading the captured data value in TODATA and assuming a specific value for the Timer 0 clock frequency you can calculate the pulse width duration of the signal that is being input at the TOCAP pin 12 2 ELECTRONES S3CC11B FC11B 8 BIT TIMER 0 TIMER 0 CONTROL REGISTER TOCON You use the Timer 0 control register TOCON to Select the Timer 0 operating mode interval timer capture mode PWM mode e Select the Timer 0 input clock frequency e Clear the Timer 0 counter TOCNT Enable the Timer 0 counter A reset clears TOCO
235. s used in normal mode 2 3 4 Every value in this table is measured when bits 1 0 of the clock control register CLKCON 1 0 is set to 11B 5 If the fout PLL s output clock is used for the system clock the current consumption is added by 0 2mA 1MHz at Vpp 3 3V and the current through PLL block 6 Thecurrent is added a little when Y ROM is enabled ELECTRONK S 23 3 ELECTRICAL DATA S3CC11B FC11B CPU Clock 32 MHz 3 0V 3 6V Figure 23 1 Operating Voltage Range 23 4 ELECTRONES S3CC11B FC11B ELECTRICAL DATA Table 23 3 A C Electrical Characteristics Parameter Symbol Conditions Min Typ Max Unit low width TN Vpp 3 3 V width TA 25 C to 85 2 0 V to 3 6 V Figure 23 2 Input Timing for External Interrupts Ports 0 Ports 4 Figure 23 3 Input Timing for nRESET ELECTRONK S 23 5 ELECTRICAL DATA S3CC11B FC11B Table 23 4 Data Retention Supply Voltage in Stop Mode TA 25 C to 85 Data retention supply VpppR voltage Data retention supply Ipppr Vpppr 1 5 V current BENEA ERES RESET Occur HEN n Oscillation 4 Stop Mode 4 Stabilization Time Normal Data Retention Mode Operating Mode Execution of STOP Instruction NOTE is the same as 2048 x 32 x 1 fxx Figure 23 4 Stop Mode Release Timing When Initiated by a nRESET 23 6 ELECTRONES S3CC11B FC11B ELECTRICAL D
236. size and small power consumption together 9 8 ELECTRONES S3CC11B FC11B VO PORTS P2PUR Port 2 Pull Up Resistors Enable Register 3F002AH Bit Identifier _7 6 5 4 3 2 fa 0 0 0 0 0 0 0 Reset Value 0 Read Write R W R W R W R W R W R W R W R W 4 P2 7 s Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 6 P2 6 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 5 P2 5 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 4 P2 4 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 3 P2 3 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 2 P2 2 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 41 P2 1 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 0 P2 0 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor NOTE When the SmartMedia control SMCON register is enabled the pull up resistors should be automatically disabled to reduce current comsuption through them 1 ELECTRONES 9 PORTS S3CC11B FC11B P3CONH Port 3 Control Register High 3F002CH Bit Identifier _ 7 6 5 4 3 2 9 7 0 0 0 0 0 0 0 0 Reset Value Read Write R W R W R W R W R W R W R W R W 7 6 P3 7 TBOUT Configuration B
237. stomer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics microcontroller business has been awarded full ISO 14001 certification BVQ1 Certificate No 9330 All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives Samsung Electronics Co
238. system reset signal is generated As the reset signal sets WDTCON as A5H and this value disables the watchdog timer ELECTRONES 10 1 BASIC TIMER S3CC11B FC11B BTCON Basic Timer Control Register Bit Identifier Reset Value Read Write 6 4 10 2 gt 5 5 3 2 E 1 1 1 0 0 R W R W R W R W R W Basic Timer Clock Selection Bits fofolme _ off 0 fxx 128 1 1 1 fxx 2048 Bits 3 2 Basic Timer Counter Clear Bit Don t care Clear basic timer counter Watchdog Timer Counter Clear Bit Don t care 1 Clear watchdog timer counter ELECTRONES S3CC11B FC11B BASIC TIMER WDTEN Watch Dog Timer Enable Register 3F000EH Bit Identifier 5 5 3 2 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 0 Watch dog Timer Enable Bits 10100101 Disable watch dog timer Other values Enable watch dog timer ELECTRONES 10 3 BASIC TIMER S3CC11B FC11B BASIC TIMER amp WATCHDOG TIMER BLOCK DIAGRAM Reset or Stop BTCON 6 54 9 Data BUS fxx 2048 fxx 1024 fxx 256 8 BIt Basic Counter fxx 128 read only fxx 32 TR fxx 16 CPU Start Signal bod power down release fxx 2 OVF 3 bit Watchdog BTCON O STOP IDLE The basic timer counter is cleared to when 1 is written to BTCON 1
239. t ELD Xi rp01s Yi rp3s Operation Xi lt operand1 by rp01s Yi lt operand2 by rp3s This instruction loads two operands from data memory one from X memory space and the other from Y memory space to the specified 16 bit Xi and Yi register respectively Flags Notes _ Examples ELD X0 RP1 S1 Y1 RP3 S0 of Words 1 21 84 ELECTRONES S3CC11B FC11B CalmMAC1616 EMAD 4 multiply and Add Format EMAD Mi XiYi Operation MAi MAi P P Xi Yi This instruction adds the values of 36 bit Multiplier Accumulator MAi and P register together and stores the result back into Multiplier Accumulator MAi At the same time multiplier multiplies Xi register value and Yi register value and stores the result to the P register Flags VMi Set if result is overflowed to guard bits Reset if not MV Set if guard bit is overflowed Unchanged if not Notes VMi denotes for VMO or VM1 according to Mi Examples EMAD X1Y0 of Words 1 ELECTRONES 21 85 CalmMAC1616 S3CC11B FC11B EMAD 2 _ Multiply and Add w One Parallel Move Format Operation Flags VMi MV EMAD Mi XiYi dest src lt dest gt lt src gt Ai Mj Ai MjSR Ai MjSL mgx rps lt P P lt Xi Yi dest lt src This instruction adds the values of 36 bit Multiplier Accumulator MAi and P register together and stores the result back into Multiplier Accumulator MAi At the same time
240. t LDB R0 A8 lt disp 8 gt LDB A8 lt disp 8 gt A8 Description LDB Load Byte to RO Register Displacement instruction is used to load a byte from or to data memory at the location specified by the register A8 and an 8 bit displacement 15 14 13 12 4 10 9 8 7 0 Operation M 0 LDB A8 lt disp 8 gt RO DM A8 lt disp 8 gt M 1 LDB A8 lt disp 8 gt RO DM A8 lt disp 8 gt RO Exceptions None Notes This single word instruction allows a user to access a wider range of data memory than the LDB 1 instruction by providing a larger displacement at the expense of the restrictions that only the RO and A8 registers are used for data transfer and address computation ELECTRONES 6 63 INSTRUCTION SET S3CC11B FC11B LDC Load Code Format LDC Rn Ai Description The LDC instruction is used to transfer a register value from the program memory The program memory address is specified by the 22 bit register An LDC is useful to look up the data stored in program memory such as the coefficient table for certain numerical algorithms 15 14 13 12 1 8 7 6 5 4 3 2 0 Pi m Operation Rn PM Ai Exceptions None Notes None 6 64 ELECTRONES S3CC11B FC11B INSTRUCTION SET LD PC Load Program Counter Format LD An PG Description The LD PC Load Program Counter instruction is used to transfer
241. t SYS lt imm 5 gt Description The SYS System instruction is used for system peripheral interfacing using DA 4 0 and nSYSID core signals 15 14 13 12 11 10 9 8 7 6 5 4 0 rfofofifrfififofolfofi Operation core output signal DA 4 0 lt imm 5 gt DA 21 5 unchanged core output signal nSYSID LOW Exceptions None Notes None ELECTRONES 6 105 INSTRUCTION SET S3CC11B FC11B TST 1 Test Register Format TST Rn Ri Description TST TST Register instruction is used to determine if many bits of a register are all clear or if at least one bit of a register is set TST performs a comparison by logically ANDing the value of register Rn with the value of Ri T bit is set according to the result 15 14 13 12 4 8 7 6 5 4 3 0 m Operation Temp Rn amp Ri T bit Rn amp Ri 0 Exceptions None Notes None 6 106 ELECTRONES S3CC11B FC11B INSTRUCTION SET TST 2 Test Small Immediate Format TST R0 lt imm 8 gt Description This type of TST instruction is used to determine if many bits of a register are all clear or if at least one bit of a register is set TST performs a comparison by logically ANDing the value of register Rn with the value of Ri T bit is set according to the result 15 14 13 12 4 10 9 8 7 0 lt imm 8 gt Operation Temp n Rn amp lt imm 8 gt T bit Rn amp lt imm 8 gt 7 0
242. t Tx at falling edges Rx at rising edges 1 Rx at falling edges Tx at rising edges 3 Serial I O Counter Clear and Shift Start Bit No effect 1 Clear 3 bit counter and start shifting This bit is automatically cleared to logic zero immediately after starting shift 2 Serial Shift Operation Enable Bit Disable shifter and clock counter Enable shifter and clock counter 1 0 Bits 1 0 Not used 14 2 ELECTRONK S S3CC11B FC11B SERIAL INTERFACE SIO PRE SCALER REGISTER SIOPS The values stored in the SIO pre scaler registers SIOPS lets you determine the SIO clock rate baud rate as follows Baud rate Input clock Pre scaler value 1 or SCLK input clock where the input clock is fxx 4 SIO Pre scaler Register SIOPS 6DH R W Baud rate fxx 4 SIOPS 1 Figure 14 1 SIO Pre scaler Register SIOPS BLOCK DIAGRAM 3 Bit Counter Serial INT CLEAR SIOCON 7 SIOCON 3 Shift Clock Source Select SIOCON 4 SIOCON 2 Edge Select Shift Enable SIOCON 5 SCK gt Mode Select so Po 6 SIOPS CK g Bit SIO Shift Buffer 5 fxin 2 gt 8 Bit P S SIODATA Prescaled Value 1 SIOPS 1 4 SIOCON 6 LSB MSB First Mode Select SI P0 5 Figure 14 2 SIO Functional Block Diagram ELECTRONES 14 3 SERIAL INTERFACE 3CC11B FC11B SERIAL TIMING DIAGRAMS Transmit IRQS N Complete Set SIOCON 3 Figure 14 3 Serial
243. t Shift Unsigned Multiplication Control 0 Signed Reset Value 1 Unsigned X1 Y1 MA Overflow Protection 0 when Reset Memorized Overflow Flag 0 when Reset MA1 Overflow Flag MAO Overflow Flag Figure 21 6 MSR1 Register Configuration MA1E MAOE Bit 15 12 Bit 11 8 These four bit nibbles are used as guard bits for MA registers These bits are updated when MA register write operation is occurred These bits are also written during MSR1 register write operation ELECTRONES 21 11 CalmMAC1616 S3CC11B FC11B OPMA Bit 7 The OPMA bit indicates that saturation arithmetic is provided or not when arithmetic operation on one of the MA registers When the OPMA bit is set Overflow Protection is enabled and overflow is occurred during arithmetic operation the saturation logic will substitute a limited data value having maximum magnitude and the same sign as the source MA register If the OPMA bit is clear no saturation is perfo rmed This bit has not effect on a ESAT instruction which always saturates the MA register value The OPMA bit is modified by writing the MSR1 register or ER ES instruction The OPMA bit is cleared by a processor reset NQ Bit 6 This bit defines next operation of division step When this bit is clear the next division instruction subtracts P register from MA register and when this bit is set the next division instruction adds P register value from MA register It also defin
244. tensions None None ELECTRONES 6 43 INSTRUCTION SET S3CC11B FC11B CMPEQ 2 Compare Equal Small Immediate Format CMP EQ Dn lt imm 8 gt Description The CMP EQ Compare Equal Small Immediate instruction is used to compare two values in register Dn and lt imm 8 gt lt imm 8 gt is zero extended to 16 bits before comparison This instruction is a restricted form of more general CMPmode instructions for an 8 bit equality comparison between a register value and an immediate value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I o o o we Operation T bit Dn lt imm 8 gt 0 Dn refers to registers RO R8 Exceptions None Notes None 6 44 ELECTRONES S3CC11B FC11B INSTRUCTION SET CMPEQ 3 Compare Equal Large Immediate Format Description Operation Exceptions Notes CMP EQ An lt imm 22 gt The CMP EQ Compare Equal Large Immediate instruction is used to compare two values in register An and lt imm 22 gt This instruction is a restricted form of more general CMPmode instructions for a 22 bit equality comparison between a register value and an immediate value 15 14 13 12 4 10 8 7 6 5 0 pt Aa ijo T bit Zero from An lt imm 22 gt An refers to registers from A8 to A15 with their 6 bit extensions None This is a 2 word instruction where the 16 bit immediate lt imm 22 gt 15 0 follows the instruction word sho
245. ter Rd The T bit and the V flag are updated based on the result 15 14 13 12 11 10 9 8 7 6 5 4 3 0 m Operation Rn Rn lt imm 16 gt T bit T bit Carry from Rn lt imm 16 gt T bit V flag Overflow from Rn lt imm 16 gt T bit R6 R7 Z0 Z1 Rn lt imm 16 gt T 0 Exceptions None Notes This is a 2 word instruction where the 16 bit immediate follows the instruction word shown above Unlike 1 word instructions therefore fetching of this instruction takes 2 cycles ELECTRONES 6 93 INSTRUCTION SET S3CC11B FC11B SETSR setsR Format Description Operation Exceptions Notes 6 94 SETSR bs 3 The SETSR Set SR instruction is used to set a specified bit in SR as follows SETSR FE IE TE V Z0 Z1 PM To set the T bit one can do as follows CMP EQ RO RO To clear a specified bit in SR the CLRSR instruction is used 15 14 13 12 1l 10 9 8 7 6 5 4 3 2 0 SR lt bs 3 gt 1 None None ELECTRONES S3CC11B FC11B INSTRUCTION SET SLB shift Left Byte Format SLB Rn Description The SLB Shift Left Byte instruction shift the value of Rn left by 8 bit and stores the result back in Rn The low 8 bit positions are filled with O s T bit is updated as a result of this operation Operation SR 15 8 Rn 7 0 and Rn 7 0 8 h00 T bit Rn 8 before shifting Exceptions None Notes None
246. ternal Condition Generation 21 24 Status Register 0 rice diete store deett o ies aa rut Atferd 21 25 Status Register 2 MSR2 I eee Ritt 21 27 Barrel Shifter and Exponent 21 29 Barrel Shili ka MR EET 21 29 Shiftinig XOperatloris esc ave Dia 21 30 u p ea eee eis 21 33 Instruction Set Map and 21 34 Addressing Modesta Q ee tt bader ete teen eas 21 34 Instruction Ooa ITALE ee EO su p usa 21 39 Quick T 21 55 Instruction Set LEE 21 60 Etre MI ka kak eng 21 60 x S3CC11B FC11B MICROCONTROLLER Table of Contents continued Chapter 22 Program Memory Access Speed OVOIVIOW sxe ua o rese o coste once as valine Chapter 23 Electrical Data Chapter 24 Mechanical Data OVEIVICW ea HND Chapter 25 S3FC11B Flash MCU Chapter 26 Development Tools nuy u cesset Dei be UA Qu aska CalmSHINE IDE Integrated Development In Gireuit
247. test it This instruction provides a compact way to control register indexing for loops The T bit and the V flag are updated based on the result Operation Rn Rn 1 T bit Rn 1 0 V flag Overflow from Rn 1 R6 R7 20 71 1 0 Exceptions None Notes None ELECTRONES 6 49 INSTRUCTION SET S3CC11B FC11B EXT Sign Extend Format Description Operation Exceptions Notes 6 50 EXT Rn The EXT Sign Extend instruction is used to sign extend an 8 bit value in Rn This instruction copies Rn 7 to Rn 15 8 All bits from Rn 15 to Rn 8 Rn 7 R6 R7 20 71 Result 0 None None ELECTRONES S3CC11B FC11B INSTRUCTION SET INCC increment with Carry Format Description Operation Exceptions Notes INCC Rn The INCC Increment with Carry instruction is used to synthesize 32 bit increment If register pair RO R1 holds a 32 bit value RO holds the least significant word the following instructions leave the 32 bit incremented value in RO R1 INC RO will be replaced by ADD 1 INCC R1 INCC increments the value of Rn by 1 only if the Carry flag stored in the T bit is set and stores the result back in register Rn The T bit and the V flag are updated based on the result 15 14 43 12 4 10 9 8 7 6 5 4 3 0 Rn Rn T bit T bit Carry from Rn T bit V flag Overflow from Rn T bit R6 R7
248. th Delay 5 eee 6 37 CLD Coprocessor Load oie Extent ciere chewed Eee hatu a Du En 6 38 CLRSR A deu bdo tI eg 6 39 CMP 1 i cese nv oerte cue nn DR 6 40 CMP 2 Compare Immediate ect ert Shanes a Rene Hina 6 41 CMP 3 Compare Short 6 42 CMPEQ 1 Compare Equal Extended 6 43 CMPEQ 2 Compare Equal Small Immediate a 6 44 CMPEQ 3 Compare Equal Large Immediate 6 45 COM 6 46 MU 6 47 DECC Decrement with Carry ke DEM eni 6 48 DT Decrement and TeSt Lee aa HL RE PE Ep ieee 6 49 EXT EE 6 50 Increment with a amet ende Hands kam 6 51 JMP 1 Jump REGISTER 22 u Ou in ee Pub ede waqa uwa a 6 52 JMP 2 JUMP Immediate rii ite rec inet er ettet a eet aee 6 53 LD 1 Register sana ace sd DIC eI DM 6 54 LD 2 Load Register u rtr ede ta Ente Neate dis 6 55 LD 3 Load Short Immediate be tet ted eee toe EE CE Deed 6 56 LD 4 my here met eene etae o asss 6 57 LD 5 Load Large Immediate ss
249. that is SPCH IRQ SPCL IRQ register pair and SSR IRQ to save the return address and SR respectively PM bit is set IE TE bits are cleared When SWI imm 6 instruction is executed the return address is saved in the register A14 and the value of SR is saved in SSR_SWI Then the program sequence jumps to the address imm 6 4 PM bit is set IE and TE bits are cleared SWI 0 and SWI 1 are prohibited because the addresses are reserved for other interrupts When RET SWI instruction is executed SR is restored from SSR_SWI and the return address is restored to PC from A14 NOTES 1 6 h00 is defined as 00 or zero in 6 bits 2 imm 6 is defined as 6 bit immediate number ELECTRONES 3 5 Calm16Core S3CC11B FC11B NOTES 3 6 ELECTRONES S3CC11B FC11B EXCEP TIONS EXCEPTIONS OVERVIEW Exceptions in CalmRISC16 are listed in the table below Exception handling routines residing at the given addresses in the table are invoked when the corresponding exception occurs The starting address of each exception routine is specified by concatenating 0H leading 4 bits of 0 and the 16 bit data in the exception vector listed in the table For example the interrupt service routine for starts from 0H PM 000002H Note that means concatenation and PM stands for the 16 bit content at the address of the program memory When an IRQ or FIQ occurs current PC is pushed in the SPC_IRQ SPC FIQ on an exception And if SWI is execute
250. the value of PC into a 22 bit register An This instruction provides a way to implement position independent code PIC on CalmRISC16 even in the absence of general virtual memory support After executing this instruction An will be used to compute a PC relative location of a data item or a code section Operation 4 Exceptions None Notes None ELECTRONES 6 65 INSTRUCTION SET S3CC11B FC11B LD SvR 1 Load trom Saved Register Format LD SPCL LD RO SPCH LD RO SSR Description LD SvR Load from Saved Register instructions are used to transfer a value from the specified interrupt register e g SSR_FIQ Only RO register is used for this data transfer 15 14 43 12 4 10 9 8 7 6 5 4 3 0 Operation RO specified saved register Encoding for RS Register Specifier 0000 SPCL FIQ 0001 SPCH FIQ 0010 SSR FIQ 0100 SPCL IRQ 0101 SPCH IRQ 0110 SSR IRQ 1010 SSR_SWI Exceptions None Notes None 6 66 ELECTRONES S3CC11B FC11B INSTRUCTION SET LD SvR 2 Load to Saved Register Format Description Operation Exceptions Notes LD SPCL R0 LD SPCH R0 LD SSR_ RO The LD SvR Load to Saved Register instructions are used to transfer a value to the specified interrupt register e g SSR_FIQ Only R0 register is used for this data transfer 15 14 13 12 11 10 9 8 7 6 5 4 3 0 lt specified saved register gt RO Encoding for lt R
251. tial Linearity Error Offset Error of Top Offset Error of Bottom Conversion Time 1 Analog Input Voltage Analog Input Impedance Analog Input Current Analog Block Current NOTES 1 Conversion time is the time required from the moment a conversion operation starts until it ends 2 lapcis an operating current during A D conversion 23 10 ELECTRONES S3CC11B FC11B ELECTRICAL DATA Table 23 10 14 bit ADC DAC Electrical Characteristics TA 0 C to 70 Vp 3 0 V to 3 6 V Vss 0 V Resolution Input sine wave 1 kHz Measurement Bandwidth 20 Hz 4 kHz fs 8 kHz Signalto Noise THD 70 75 Ratio ee C s m we ELECTRONK S 23 11 ELECTRICAL DATA S3CC11B FC11B NOTES 23 12 ELECTRONES S3CC11B FC11B MECHANICAL DATA OVERVIEW The S3CC11B FC11B microcontroller is currently available in a 100 pin QFP and TQFP package ELECTRONES M ECHA NICAL DATA 24 1 MECHANICAL DATA S3CC11B FC11B 23 90 0 30 20 00 0 20 100 QFP 1420C 010 17 90 0 30 14 00 0 20 q 5 0 05 MIN lt 2 65 0 10 3 00 MAX room 0 80 0 20 SIII NOTE Dimensions are in millimeters Figure 24 1 100 QFP 1420C Package Dimensions 24 2 ELECTRONES S3CC11B FC11B M ECHA NICAL DATA 16 00 0 20 0 073 0 127 0 037 0000000000000029002000000 lil 8 L r3 e 100 TQF
252. tion SA exponent An This instruction evaluates the exponent value of one of 16 bit Accumulator An and stores the result back into 7 bit SA register Flags C Set if LSB of source An accumulator is 1 Reset if not Z Set if exponent evaluation result is zero Reset if not VS Set if the value of source An accumulator is all zeroes or all ones Reset if not N Reset Notes EEXPT instruction can be executed only when the T flag is set Otherwise No operation is performed Examples EEXP A EEXPT C of Words 1 ELECTRONES 21 73 CalmMAC1616 S3CC11B FC11B EEXPC EEXPCT Exponent Value Evaluation with Carry Format EEXPC T An Operation if VS 1 SA exponent C An else no operation This instruction evaluates the exponent value which concatenates carry and one of 16 bit Accumulator An adds the result with SA register value and stores the added result back into 7 bit SA register It can be used for multi precision exponent evaluation Flags C Set if LSB of source An accumulator is 1 Reset if not Z Set if exponent evaluation result is zero Reset if not VS Set if the value of carry and source An accumulator is all zeroes or all ones Reset if not N Reset Notes EEXPCT instruction can be executed only when the T flag is set Otherwise No operation is performed Examples EEXPC D EEXPCT B of Words 1 21 74 ELECTRONES S3CC11B FC11B CalmMAC1616 EFS EFST p Force to Sign MS
253. tpin 2907 5800 i 44 6 44 10 5 10 4 4 4 4 4 4 4 4 TOOUT Timer0 s interval output pin 46 P3 4 TOPWM TOCAP TOPWM Timer0 s PWM output 4 P3 4 T0OUT TOCAP NOTE The parentheses are a pin number of 100 TQFP package E ELECTRONES 1 7 PRODUCT OVERVIEW S3CC11B FC11B Table 1 1 S3CC11B FC11B Pin Description Continued Type Description Circuit Shared Pins Type TOCAP 05 Capture input pin 4 46 44 P3 4 TOOUT TOPWM TOCLK TimerO s external clock input pin 5 43 P3 3 AD3 nWE ___ Write enable pin 4 32 a7 41 39 P2 7 26 33 1 0 P1 7 nWE RE WP ALE CLE CLE Command latch enable pin Chip enable 0 pin nCE1 Chip enable 1 pin 1 00 7 Smartmedia interface lines I VO VO VO VO VO VO VO VO VO AD0 AD2 Analog input pins for A D converter 42 44 P3 0 P32 A Analog power pins for PLL block VO D VO 9 VO VO 551 552 P4 3 SEG2 5 6 18 19 Analog power pins for CODEC block L 18 17 16 15 Crystal oscillator pins for sub clock Main oscillator pins 4 System reset pin 2 3 R X S 19 17 13 14 64 63 2 1 99 100 Power input pins for CPU Power input pins for peripheral block Power input pins for peripheral block NOTE The parentheses pin number of 100 TQFP package lt lt Q Input pin for test must be connected to V ss
254. tten via YB when dual load instruction is executed The 16 bit most significant portion MSP of the P register PH or the 16 bit least significant portion LSP of the P register PL can be written through the XB as an operand When MSP of the P register is written LSP of the P register is forced to zero When LSP of the P register is written MSP of the P register is not changed Overflow Protection in Multiplier The only case the multiplier overflow occurs is when multiplying 8000h by 8000h in signed by signed fractional multiplication These case means 1 1 the result should be normally 1 which overflows fractional format Thus in this particular case the multiplier saturation block forces the multiplier result to 7FFFFFFFh after internal 1 bit shift to the left and write this value to the product register P Saturation Condition 31 amp Proa 30 amp PSH1 amp SX SY Prod product result PSH1 Fractional Indication SX Signed X operand SY Signed Y operand Multiplier Accuulators Each MAi i 0 1 is organized as two regular 16 bit registers MAOH MAOL MA1H MA1L and two 4 bit extension nibble MAOE in MSR1 register The MAi accumulators can serve as the source operand as well as the destination operand of MA relevant instructions 36 bit full data transfer between two MA accumulators is possible through ELD and ELD MA1 instructions The 16 bit most signi
255. unit The arithmetic unit receives one operand from MAi and another operand from P register The source and destination MA accumulator of arithmetic instruction is always the same The arithmetic unit can perform positive or negative accumulate add subtract shift and several other operations all of them in a single cycle It uses two s complement arithmetics Some flags VMi MV flag are affected as a result of the arithmetic unit output value The flags represent the MA register status Rounding Provision Two rounding operations are enabled inside the CalnMAC16 the first one concerns the whole 32 bit accumulator the second concerns a higher 16 bit portion of MAi register MAiH or a higher 16 bi portion of P register PRN during 16 bit arithmetic operation in ARU The first rounding facility is provided by the ERND instruction It can be applied only to a multiplier accumulator The rounding operation is always a two s complement rounding operation If bit 15 of is 1 1 is added in bit 16 position of MA register the result is stored register and MAIL is not changed If bit 15 of MAIL is 0 and MAIL register remain unchanged The second rounding is provided as a form of source operand MAiRN or PRN When the source operand of 16 bit arithmetic operation in ARU is specified as MAiRN the rounded value of 16 bit higher portion of register is read as a source operand When the source operand
256. user must select fx 2 as CODEC input clock 17 2 ELECTRONES S3CC11B FC11B CODEC CDCON copEc control Register 3F0064H Bit Identifier 6 TE Reset Value 0 0 0 0 0 0 0 Read Write R W R W R W R W _ R W R W R W 7 A D Converter Enable Bit Disable A D converter Enable A D converter 6 D A Converter Enable Bit Disable D A converter Enable D A converter 5 Codec Frequency Dividing Circuit Enable Bit 0 Disable codec frequency dividing circuit Enable codec frequency dividing circuit 4 Mute Control Bit EN Enable mute Low out Disable mute Data out 3 Bit 3 2 0 Codec Input Clock Selection Bits 1 0 fosgs fxin 3 op _ EDD CIIM NR sr CIAM RN op popem foses fxin 10 ELECTRONES 17 3 CODEC S3CC11B FC11B Codec INT ADGAIN ADDATAH ADINN Decimal ADINP gt A Modulator ADDATAL VREFOUT Voltage Reference Interpolation Postfiter gt A Modulator gt Filter CDCON 7 CDCON 6 Enable Codec INT z CDCON 5 DADATAL NOTES 1 The CODEC interupt is generated every 1 fs interval and the ADDATA is updated at that time 2 The interrupt generation is started in a group delay after enabling the A D converter Figure 17 1 CODEC Block Diagram 17 4 ELECTRONES S3CC11B FC11B CODEC ADGAIN GND AVREFOUT R2 Voltage Gain Example R2 2xR1 R1 100 1 gt 10 R2 200 kQ
257. ut low leakage 0 current All Output pins Pull up resistor Vin 0 V Vpp 3 3 V Ty 25 Ports 0 9 LCD Voltage Dividing Resistor VLCD COMi Voltage Drop i 0 7 VLCD SEGx Voltage Drop x 0 39 Middle Output Vpp 2 4V to 3 6V 1 5 bias 0 8V 550 2 0 8Vpp 0 8Vpg 0 2 Voltage 1 LCD clock 0Hz Vic 0 6 0 2 0 6Vpp 0 2 0 40 2 0 4Vpp 0 2 0 2Vpp 0 2 0 2Vpp 0 2 NOTE Itis middle output voltage when LCD controller driver is 1 8 duty and 1 5 bias 23 2 ELECTRONES S3CC11B FC11B ELECTRICAL DATA Table 23 2 D C Electrical Characteristics Continued TA 25 C to 85 C Vpp 2 0 V to 3 6 V Supply Ippi 2 Vpp 3 3 V 10 20 MHz 16 0 32 0 Current 1 Crystal oscillator 4 MHz 4 0 fx foyr 2 048 MHz Xtal 32 768 MHz 8 0 Ipp2 2 Idle mode 20 MHz 1 0 2 0 Vpp 3 3 V 10 4 MHz 0 4 0 8 Crystal oscillator 60 100 20 2 0 10 Stop mode 0 2 Vpp 3 3 V 10 TA 25 C 3 Vpp 3 3 V 10 32 kHz crystal oscillator 3 mode 6 0 Vpp 3 3 V 10 32 kHz crystal oscillator UA uA 1 Supply current does not include current drawn through internal pull up resistors PWM PLL or external output current loads Ipp1 and Ipp2 include power consumption through sub clock oscillation and main oscillator is in normal mode NOTES Ipp3 are current when main clock oscillation stops and the sub clock i
258. utput SSFDC Interface Logic e Two selection pins nCEO nCE1 8 Bit Basic Timer e Programmable interval timer e 8 kinds of clock source e Watchdog timer s clock source overflow of 8 bit counter Watchdog Timer e System reset when 3 bit counter overflow One 8 Bit Timer Counter 0 e Programmable interval timer e External event counter function e PWM function and capture function ELECTRONES One 16 Bit Timer Counter 1 e One 16 bit timer counter mode e Two amp bit timer counters A B mode Watch Timer e nterval time 3 91ms 0 255 0 55 and 1S at 32 768 kHz e 0 5 1 2 4 kHz selectable buzzer output LCD Controller Driver 36 segments and 8 common terminals e 3 4 and 8 common selectable e Internal resistor circuit for LCD bias 8 Bit Serial Interface e Four programmable operating modes 8 16 Bit Serial Interface for External Codec e I nternal External clock source selectable Two programmable operating modes 1 1 PRODUCT OVERVIEW FEATURES Continued Battery Level Detector Operating Voltage Range e Programmable low voltage detector e 20Vto3 6V Two criteria voltage 2 45 V 2 70 V Operating Temperature Range Phase Locked Loop PLL e 25 C to 85 e Programmable clock synthesizer Current Consumption Codec e Sub idle current 6 0 uA at Vpp e 14 bit A D converter 14 bit D A converter 3 6kHz 11 kHz sampling frequency Package Type e 3 0 V 3 6 V operating volta
259. ven number from 0 to 510 ELECTRONES 6 69 INSTRUCTION SET S3CC11B FC11B LDW 2 Load Word Register Small Disp Format Description Operation Exceptions Notes 6 70 LDW Rn Ai lt edisp 5 gt LDW An lt edisp 5 gt Ri The LDW Load Word Register Displacement instruction is used to load a word from or to data memory at the location specified by the register Ai and a 5 bit even displacement from 0 to 30 edisp 5 is encoded to 4 bit number by dropping the least significant bit 15 14 13 12 1l 8 7 6 4 3 0 o o u 09 lt M 0 LDW Rn Ai lt edisp 5 gt Rn DM Ai lt edisp 5 gt M 1 LDW An lt edisp 5 gt Ri DM An lt edisp 5 gt Ri None For memory transfer per word the byte address need to be aligned to be even Thus if Ai lt edisp 5 gt is an odd number it will be made even by clearing the least significant bit lt edisp 5 gt can denote an even number from 0 to 30 ELECTRONES S3CC11B FC11B INSTRUCTION SET LDW 3 Load Word Register Disp Format Description Operation Exceptions Notes LDW Rn Ai lt disp 16 gt LDW An lt disp 16 gt Ri The LDW Load Word Register Large Displacement instruction is used to load a word from or to data memory at the location specified by the register Ai and a 16 bit displacement 15 14 13 12 4 8 7 6 5 4 3 2 0 mom nom
260. width for 1 word instructions e 5 Stage pipeline e 32 bit instruction width for 2 word instructions e Load Store instruction architecture Registers Delayed branch support e Sixteen 16 bit general registers ClanguagelOS suport e Eight 6 bit extension registers e 22 bit Program Counter e Bit operation for I O process 16 bit Status Register SR Instruction Execution Time e Five saved registers for interrupts instruction cycle for basic instructions Address Space 2M word for Program Memory e 4M byte for Data Memory ELECTRONES 3 1 Calm16Core S3CC11B FC11B REGISTERS In CalmRISC16 there are sixteen 16 bit general registers eight 6 bit extension registers a 16 bit Status Register SR a program counter PC and five saved registers GENERAL REGISTERS amp EXTENSION REGISTERS The following figure shows the structure of the general registers and the extension registers Registers for Byte Address Registers i i Link Register Stack Pointer Figure 3 1 Register Structure in CalmRISC16 The general registers from RO to R15 can be either a source register or a destination register for almost all ALU operations and can be used as an index register for memory load store instructions e g LDW R3 A8 R2 The 6 bit extension registers from E8 to E15 are used to form a 22 bit address register from A8 to A15 by concatenating with a general register from R8 to R15
261. wn above Unlike 1 word instructions therefore fetching of CMP EQ imm 22 takes 2 cycles ELECTRONES 6 45 INSTRUCTION SET S3CC11B FC11B COM Complement Format COMmode Rn Description The COM Complement instruction is used to compute 1 s or 2 s complement of a register value Operation Exceptions Notes 6 46 Rn Utilizing various modes 32 bit complement operation can be done If register pair RO R1 holds a 32 bit value RO holds the least significant word the following instructions leave the 32 bit 2 s complement in RO R1 COM RO 2 s complement COMC R1 2 s complement with carry COM computes the 1 s complement of the value of register Rn COM2 computes the 2 s complement and COMC computes the 2 s complement value when T bit has been set If T bit is clear COM is equivalent to COM 15 14 43 12 4 10 9 8 7 6 5 4 1 3 0 if Mode 00 COM T bit Rn 0 if lt Mode gt 01 COM2 Rn Rn 1 T bit Carry from Rn 1 if Mode 10 COMC Rn T bit T bit Carry from Rn T Encoding of Mode 00 COM 01 COM2 10 COMC R6 R7 20 71 Zero flag of the result None None ELECTRONES S3CC11B FC11B INSTRUCTION SET COP Coprocessor Format Description Operation Exceptions Notes COP imm 13 The COP Coprocessor instruction is used to perform a coprocessor operatio
262. word instructions JMP JPT JPF JSR Ai The target address of the instructions is the value of Ai JMP always branches to the target address JPT branches to the target address if the T flag is set JPF branches if the T flag is cleared JSR always branches to the target address with saving the return address PC 2 into A14 SWI imm 6 RET SWI RET IRQ RET FIQ refer to the section for interrupts RETD The instruction branches to the address in A14 after the execution of the instruction in the delay slot When there is no useful instruction adequate to the delay slot JMP A14 can be used instead of ELECTRONK S 6 9 INSTRUCTION SET S3CC11B FC11B BIT OPERATION The bit operations manipulate a bit in SR register or in a memory location BITR BITS BITC BITT A8 R1 imm 3 The source as well as the destination is the 8 bit data in the data memory at the address A8 R1 The imm 3 field chooses a bit position among the 8 bits BITR resets the bit imm 3 of the source and then writes the result to the destination the same memory location BITS sets the bit imm 3 of the source and then writes the result to the destination BITC complements the bit imm 3 of the source and then writes the result to the destination BITT does not write any data to the destination T flag indicates whether the bit imm 3 of the source is zero In other words when the bit imm 3 of the source is zero T flag is set BITR and BITS can b
263. xtended register An 14 13 12 10 1 15 11 8 7 6 5 0 ijo lt imm 22 gt This is 2 word instruction where the 16 bit immediate lt imm 22 gt 15 0 follows the instruction word shown above Unlike 1 word instructions therefore fetching of this instruction takes 2 cycles ELECTRONES S3CC11B FC11B INSTRUCTION SET LD RExt Load Register Extension Format LD Dn Ei LD En Di Description LD RExt Load Register Extension instructions are used to transfer a register value to and from a 6 bit extension register 15 14 13 12 11 10 8 7 6 5 4 3 2 0 o oo eo o see Operation M 0 LD Dn Ei Dn Ei zero extended to 16 bits M 1 LD En Di En Di lower 6 bits only Exceptions None Notes None ELECTRONES 6 59 INSTRUCTION SET S3CC11B FC11B LDB 1 Load Byte Register Disp Format Description Operation Exceptions Notes 6 60 LDB Dn Ai lt disp 4 gt LDB An lt disp 4 gt Di The LDB Load Byte Register Displacement instruction is used to load a byte from or to data memory at the location specified by the register Ai and a 4 bit displacement 15 14 13 12 11 10 8 7 6 4 8 0 M 0 LDB Dn Ai lt disp 4 gt Dn DM Ai lt disp 4 gt 1 LDB An lt disp 4 gt Di DM An lt disp 4 gt Di None None ELECTRON
264. zero extended to 16 bit data The register An should not be A15 The instruction PUSH An Am pushes An and then Am The registers An and Am should not be the same POP Rn POP Rn Rm POP An POP An Am The instruction POP Rn increments the value of SP by 2 and then transfers 16 bit data to the register Rn from the memory location at the address of SP The register Rn should not be R15 The operation of POP R15 is undefined The instruction POP Rn Rm pops Rn and then Rm The registers Rn and Rm should not be the same The registers Rn and Rm should not be R15 The instruction POP An pops En and then Rn When the extension register En is popped the least significant 6 bits are transferred to En The register An should not be A15 The instruction POP An Am pops An and then Am The registers An and Am should not be the same LDB Rn Ai disp 4 LDB Ai disp 4 Rn The instructions transfer 8 bit data between the general register Rn and the memory location at the address of Ai disp 4 disp 4 is a positive displacement from 0 to 15 The general register Rn is one RO to R7 In the instruction LDB Rn Ai disp 4 the 8 bit data is zero extended to 16 bit data and then written into Rn In the instruction LDB Ai disp 8 Rn the least significant byte of Rn is transferred to the memory LDB Rn Ai disp 16 LDB Ai disp 16 Rn The instructions transfer 8 bit data between the general register Rn and the memory locati

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