NAND Flash Boot for the Freescale MPC5121e
Contents
1. SET REG32 r4 CFG MDDRC SYS CFG EN DDR SYS CONFIG r3 SET REG32 r4 CFG MDDRC TIME CFGO DDR TIME CONFIGO r3 SET REG32 r4 CFG MDDRC TIME CFG1 DDR TIME CONFIGI r3 SET REG32 r4 CFG MDDRC TIME CFG2 DDR TIME CONFIG2 r3 Initialize DDR SET REG32 r4 CFG MICRON NOP DDR COMMAND r3 stw r4 DDR COMMAND r3 stw r4 DDR COMMAND r3 stw r4 DDR COMMAND r3 stw r4 DDR COMMAND r3 stw r4 DDR COMMAND r3 stw r4 DDR COMMAND r3 stw r4 DDR COMMAND r3 stw r4 DDR COMMAND r3 stw r4 DDR COMMAND r3 stw r4 DDR COMMAND r3 SET REG32 r4 CFG MICRON PCHG ALL DDR COMMAND r3 irc n CFG MICRON NOP DDR COMMAND r3 SET REG32 r4 CFG MICRON RFSH DDR COMMAND r3 stw r5 pi us AND r3 SET REG32 r4 CFG MICRON RFSH DDR COMMAND r3 stw ro YE d AND r3 SET RE G32 r4 CFG MICRON INIT DEV OP DDR COMMAND r3 stw r5 ori AND r3 SET REG32 r4 CFG MICRON EM2 DDR COMMAND r3 stw 55 pae AND r3 SET REG32 r4 CFG MICRON PCHG ALL DDR COMMAND r3 SET REG32 r4 CFG MICRON EM2 DDR COMMAND r3 SET REG32 r4 CFG MICRON EM3 DDR COMMAND r3 SET REG32 r4 CFG MICRON EN DLL DDR COMMAND r3 SET REG32 r4 CFG MICRON INIT DEV OP DDR COMMAND r3 SET REG32 r4 CFG MICRON PCHG ALL DDR COMMAND r3 SET REG32 r4 CFG MICRON RFSH DDR COMMAND r3 SET REG32 r4 CFG2. NAND Flash Boot for the Freescale MPC5121e Rev 0 Freescale Semiconductor 18 NAND Flash Boot Software num pages while num pages 0 out bel6 ul6 CFG NAND BASE NFC FLASH CMD NAND CMD READCACHEND out bel6 ul6 CFG HAND BASE NFC NF CFG2 NEC CMD wait op mjmdone return NAND Flash Boot for the Freescale MPC5121e Rev 0 14 Freescale Semiconductor ADS512101 Top Board Layout Appendix A ADS512101 Top Board Layout uou jeuleqiH aeu youms JOMOd sqa1 Jes uos J MOd Ay v LY oLYYN wm o me a J aan mm mmc Xutd Der OLOF ees 8d u991c gzr ved Ezd uj eur1 s en ania vzr Gel Eld e 9vir ido Ben eat Sd O J MOd g za z CT 7 775 1 1 b j un 1 1 1 1 1 E 1 1 Ei ine s 1 1 E Lir 1 1 1 Sh i ol eun i I 1 I 1 i 1 ab ein orm 1 Afi 1 1 1 ul d gO mn ut a I p 9090 7 en el 2 FIN 1 d Xu Tm S JeMog e ug sia VlVd Zld Old9 Odl 8W3 d i wagt 141 021 I I i E ueeJosuonor L d Jamod gen FAG or jeujeu3 Lr niii M I m som ao ka Ocd EA unii zen Hd4 11 1 BURN mmm Hm uH mu ool Jewog XIV bYMd ONVO n asn Zid I i lOd vid UJO9 20 UOOI IS MMM 00Zt LOb 0tv Hd erly OO siuBeip puejuBi peoy Jeu 674 XLS sseudx3 exuin uolls v0 3LziGsav lads SC
3. size 1 gt gt 16 define SET MEM BASE r b lis r b h ori r r b 81 N define SET REG32 r v offset mr lis r v h ori fcr VOLN Stw r offset mr N define SET REG16 r v offset mr li r V N sth r offset mr N text globl version string version_string ascii U BOOT VERSION ascris toy O DATE erh TIME DR ascii CONFIG IDENT STRING ascii 2K NAND BOOT O0 EXC OFF SYS RESET globl start Start from here after reset power on Start boot cold Save msr contents mfmsr r5 lis r4 CONFIG DEFAULT IMMRGh Set IMMR area to our preferred location mfspr r6 MBAR lis r3 CFG IMMRGh ori r3 r3 CFG_IMMR 1 cmpw r3 r6 beq 1f it has already been set to what we want it to be nice to chk if coming out of the BDI stw r3 IMMRBAR r4 mtspr MBAR r3 IMMRBAR is mirrored into the MBAR SPR 311 isync lee lis r4 START REG CFG FLASH BASE ori r4 r4 STOP REG CFG FLASH BASE CFG FLASH SIZE stw r4 LPBAW r3 stw r4 LPCSOAW r3 isync Initialise the machine bl cpu early init isync The SRAM window has a fixed size 256K so only the start addressis necessary NAND Flash Boot for the Freescale MPC5121e Rev 0 8 Freescale Semiconductor NAND Flash Boot Software lis r3 CFG _IMMRG h ori r3 r3 CFG IMMRG1 lis r4 START REG CFG SRAM BASE amp Oxff00 stw r4 SRAMBAR
4. tm iil 9id cm o u 1u6ipioeg GOT 6ld fsd SVLF fidO Zd Q Dao IUM IWOd33 NAND Flash Boot for the Freescale MPC5121e Rev 0 15 Freescale Semiconductor How to Reach Us Home Page www freescale com Web Support http www freescale com support USA Europe or Locations Not Listed Freescale Semiconductor Inc Technical Information Center EL516 2100 East Elliot Road Tempe Arizona 85284 1 800 521 6274 or 1 480 768 2130 www freescale com support Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French www freescale com support Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor China Ltd Exchange Building 23F No 118 Jianguo Road Chaoyang District Beijing 100022 China 86 10 5879 8000 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center 1 800 441 2447 or 1 303 675 2140 Fax 1 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Document Number AN3845 Rev 0 05 2009 Information in this document is provided solely to enable system and s
5. MICRON INIT DEV OP DDR COMMAND r3 SET REG32 r4 CFG MICRON OCD DEFAULT DDR COMMAND r3 SET REG32 r4 CFG MICRON PCHG ALL DDR COMMAND r3 stw r5 DDR_CO AND r3 Start MDDRC SET REG32 r4 CFG MDDRC TIME CFGO RUN DDR TIME CONFIGO r3 SET REG32 r4 CFG MDDRC SYS CFG RUN DDR SYS CONFIG r3 isync blr 5 2 nandload c u boot 2008 10 nand spl board ads5121 nandload c C Copyright 2009 NAND Flash Boot for the Freescale MPC5121e Rev 0 NAND Flash Boot Software Freescale Semiconductor 11 NAND Flash Boot Software Martha Marx Silicon Turnkey Express mmarx silicontkx com See file CREDITS for list of people who contributed to this project This program is free software you can redistribute it and or modify it under the terms of the GNU General Public License as published by the Free Software Foundation either version 2 of the License or at your option any later version This program is distributed in the hope that it will be useful but WITHOUT ANY WARRANTY without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE See the GNU General Public License for more details You should have received a copy of the GNU General Public License along with this program if not write to the Free Software Foundation Inc 59 Temple Place Suite 330 Boston MA 02111 1307 USA F X F OX Xo F F X F Xo F F F xXx F x F OF include lt common h gt include lt mpc512x h g
6. personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part RoHS compliant and or Pb free versions of Freescale products have the functionality and electrical characteristics as their non RoHS compliant and or non Pb free counterparts For further information see http www freescale com or contact your Freescale sales representative For information on Freescale s Environmental Products program go to http www freescale com epp Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by Power org Freescale Semiconductor Inc 2009 All rights reserved t 2 freescale semiconductor
7. settings At the u boot prompt enter these commands use the u boot NAND flash driver to erase part of the NAND Flash nand erase 0 44000 use tftp to do a network transfer of the u boot nand bin image from the host server to the board tftp 300000 u boot nand bin use the u boot NAND Flash driver to program the u boot nand bin image nand write 300000 0 To initialize the bad block table in a NAND flash use this command before attempting to erase or program the NAND flash from u boot initialize NAND Flash bad block table nand bad To program u boot nand bin using a JTAG NAND flash programmer set the NAND flash programmer to program the binary image at an offset of 0x0000 0000 The NAND flash programmer must support the NAND flash part and configuration which is described in Section 2 ADS512101 Board Preparation 4 2 Files Modified in U boot version u boot 2008 10 Files that are modified to support the NAND flash driver in u boot are 1 board ads5121 ads5121 c 2 drivers mtd nand Makefile 3 drivers mtd nand fsl nfc nand c 4 include configs ads5121 h Files that are modified to support NAND flash boot in u boot are 1 Makefile 2 board ads5121 ads5121 c 3 board ads5121 config mk 4 cpu mpc512x start S 5 include configs ads5121 h 6 include mpc512x h 7 nand spl board ads5121 Makefile NAND Flash Boot for the Freescale MPC5121e Rev 0 Freescale Semiconductor 5 NAND Flash Boot Software 8 nand spl b
8. CGRP LUT1 MU DRAMPRIOM LUT TABLE1 MAIN UP SET REG32 r4 CFG MDDRCGRP LUT1 ML DRAMPRIOM LUT TABLE1 MAIN LOW r3 SET REG32 r4 CFG DDRCGRP LUT2 U DRAMPRIO UT TABLE2 MAIN UP SET REG32 r4 CFG DDRCGRP LUT2 1 DRAMPRIO UT TABLE2 MAIN LOW r3 SET REG32 r4 CFG DDRCGRP LUT3 U DRAMPRIO UT TABLE3 MAIN UP SET REG32 r4 CFG DDRCGRP_LUT3 1 DRAMPRIO UT TABLE3 MAIN LOW r3 SET REG32 r4 CFG MDDRCGRP LUT4 MU DRAMPRIOM LUT TABLE4 MAIN UP SET REG32 r4 CFG MDDRCGRP LUT4 ML DRAMPRIOM LUT TABLE4 MAIN LOW r3 SET REG32 r4 CFG DDRCGRP LUTO AU DRAMPRIOM LUT TABLEO ALT UP SET REG32 r4 CFG DDRCGRP LUTO AL DRAMPRIOM LUT TABLEO ALT LOW SET REG32 r4 CFG MDDRCGRP LUT1 AU DRAMPRIO UT TABLE1 ALT UP SET REG32 r4 CFG MDDRCGRP LUT1 AL DRAMPRIOM LUT TABLE1 ALT LOW SET REG32 r4 CFG MDDRCGR P LUT2 AU DRAMPRIOM LUT TABLE2 ALT UP SET REG32 r4 CFG DDRCGRP LUT2 AL DRAMPRIOM LUT TABLE2 ALT LOW SET REG32 r4 CFG DDRCGRP LUT3 AU DRAMPRIO jUT TABLE3 ALT UP SET REG32 r4 CFG DDRCGRP LUT3 AL DRAMPRIO UT TABLE3 ALT LOW SET REG32 r4 CFG MDDRCGRP_LUT4 AU DRAMPRIO UT TABLE4 ALT UP SET REG32 r4 CFG MDDRCGRP LUT4 AL DRAMPRIO UT TABLE4 ALT LOW Initialize MDDRC NAND Flash Boot for the Freescale MPC5121e Rev 0 r3 10 Freescale Semiconductor
9. Freescale Semiconductor Document Number AN3845 Application Note Rev 0 05 2009 NAND Flash Boot for the Freescale MPC5121e by Gene Fortanely Applications Engineering Microcontroller Solutions Group 1 Introduction indians 1 Introducllol 2 iste tottus cd dabentiaid ne b EE I Ren 1 This document describes the procedures needed to 2 ADS512101 Board Preparation ssseses gt 2 perform NAND flash boot with a Freescale MPC5121e Boga uaaa laaa aont S The hardware platform used in this example is a Silicon R e a TER 9 0 090 E 6 0 09 R TRA TS 3 Turnkey Express ADS512101 rev 4 board v UE EET EU keete 4 U Boot NAND Flash Boot Software 3 4 1 Adding NAND Flash Boot Support to U boot 4 Refer to the latest silicon and board documentation for i Bon eee updates to the information in this document This 4 3 Description of the nand spl Directory Source Code 6 document was written using the information in 5 NAND Flash Boot Software ee 6 51 RHEIN ogos soens n se P OQ PU RE ME RCREE TS 6 1 Freescale document MPC5121ERM MPC5121e 52 Nanded cc iccicdceiccvensheceadsas aves 11 Appendix A ADS512101 Top Board Layout 15 Microcontroller Reference Manual Rev 3 October 2008 2 Silicon Turnkey Express document ADS512101UM ADS512101 Advanced Development System User s Manual Rev 1 1 September 4 2008 3 Freescale document AN3765 Porting Linux for the MPC5121e Rev 0 12 2008 ey oe
10. PS selects the NAND flash page size and is dependent on the value selected for ROMLOC 1 0 e NFC DBW selects the NAND flash data port size e BMS selects where the e300 will fetch the first instruction either at address 0x0000 0000 or at address Oxfff0 0000 Further information regarding these four RCWHR fields is also included in section 26 6 1 Modes of Operation of the NFC chapter of the MPC5121e Microcontroller Reference Manual Section 4 6 7 NFC Initialization Sequence describes the steps that must be performed by the initial bootloader software when booting from NAND flash This section also describes the functionality that can be deferred until the software is executing from DRAM Here is a summary of the functionality that must be implemented in the NAND flash boot 1 Configure the IMMR reset vector 2 Configure the DRAM amp NFC clock dividers The default NFC clock values work fine but increasing the clock speed will decrease boot time 3 Configure the NFC parameters 4 Initialize DRAM Initialization should include DRAM access window as well as timings and initialization 5 Copy the system software image to DRAM The example code in this document uses a software loop to copy the image from NFC RAM to DRAM However DMA can also be used to copy the image with the added benefit of decreased boot time NAND Flash Boot for the Freescale MPC5121e Rev 0 2 Freescale Semiconductor U Boot NAND Flash Boot Softwar
11. U Boot NAND Flash Boot Software u boot refer to Freescale application note AN3765 Porting Linux for the MPC5121e section 2 1 u boot Source Code from DENX for further instructions on how to obtain configure and build u boot 4 1 Adding NAND Flash Boot Support to U boot To add NAND flash boot support to the u boot version u boot 2008 10 source code tree you must apply two patches Copy the two patch files available with this document e u boot 2008 10 ADS5121 NFC NAND Flash Driver 20090130 patch e u boot 2008 10 ADS5121 NAND Flash Boot 20090130 patch to the base directory of your u boot 2008 10 source code tree Then apply the two patch files in this order 1 NAND flash driver patch 2 NAND flash boot patch Apply the patches like this patch file containing ADS5121 NAND flash driver support patch p1 lt u boot 2008 10 ADS5121 NFC NAND Flash Driver 20090130 patch patch file containing ADS5121 NAND flash boot support patch p1 lt u boot 2008 10 ADS5121 NAND Flash Boot 20090130 patch Once you have applied the patches build a NAND flash boot u boot image by entering the commands remove derived files make clean config u boot to build an ADS5121 NAND flash boot u boot image make ADS5121_nand_config make an ADS5121 NAND flash boot u boot image make Once the make command has successfully completed executing the u boot images will exist They are located in the base director
12. bel6 ul6 CFG HAND BASE out bel6 ul6 CFG HAND BASE wait op mjmdone out bel6 ul6 CFG HAND BASE out bel6 ul6 CFG HAND BASE wait op mjmdone out bel6 ul6 CFG NAND BASE wait op mjmdone out bel6 ul6 CFG NAND BASE wait op mjmdone out bel6 ul6 CFG NAND BASE wait op mjmdone out bel6 ul6 CFG HAND BASE wait op mjmdone out bel6 ul6 CFG HAND BASE out bel6 ul6 CFG HAND BASE wait op mjmdone unsigned long i j int K int num pages NUMPAGES unsigned long mem idx Y o do NFC NF CFG2 NFC C unsigned long 0x100 unsigned long CFG NAND U BOOT DST readout a page and copy to mem cache mode means w Af out bel6 ul6 CFG MAN RAM BUFFER ADDR ESS RBA 4 out bel6 ul6 CFG MAN Wait for operation to wait op mjmdone for j xi SE u32 CFG NAND BASE TWO K k lt TWO K 4 i NAND Flash Boot Software 2 2 D CMD READO D 0 DDR DDR DDR DDR DDR D CMD READCACH D T ER can skip the address cycle D BASE NFC RAM BUF ADDR complete j D BASE NFC NF CFG2 NFC OUTPUT k 0 k put exception vectors at 0x0 vector size is Ox13ff if i gt mem idx amp amp mem idx lt 4 u32 CFG NAND U ROOT DST TWO K 0x100 u32 0x1400
13. e 6 Perform absolute jump from NFC RAM to the DRAM system software image where additional system initialization can be performed A relative branch should not be used 3 2 UO Control Chapter 22 IO Control of the MPC5121e Microcontroller Reference Manual describes the muxing and configuring of the pads See the notes at the end of table 22 10 Pad IO Control Register Table which point out that the default slew rates for the LPC and NFC signals depend on the designated boot source The LPC EMB pins which are not used during NAND flash boot are by default configured to the slowest slew rate This behavior may need to be modified to meet the needs of your system 3 3 NAND Flash Boot Chapter 26 NAND Flash Controller NFC of the MPC5121e Microcontroller Reference Manual describes the NAND flash boot process Section 26 6 1 Modes of Operation describes the Reset Configuration register RCWHR settings that must be set to reflect the hardware environment specifically the NAND flash page size NFC PS NAND flash bus width NFC_DBW and selecting the NAND flash as the boot ROM ROMLOCT 1 0 Section 26 6 2 Booting From a NAND Flash Device describes the boot process This information describes the behavior of the MPC5121e silicon when the NAND flash is the boot ROM The NFC ECC engine can correct four or eight symbols in an NFC page If an unrecoverable number of symbol errors occur in the first NFC page then s
14. ers HIDO also contains cache control EE lis r3 CFG HIDO INIT h ori r3 r3 CFG HIDO INIT 1 SYNC mtspr HIDO r3 blr dram init SET MEM BASE r3 CFG IMMR IOCTL BASI SET REG32 r4 IOCTRL MUX DDR IOCTL M SET MEM BASE r3 CFG IMMR 3 r3 3 r3 r3 r3 r3 r3 r3 3 r3 t3 r3 13 r3 SET REG32 r4 CFG DDR BASE amp OxFFFFF000 DDR LAW BAR r3 SET REG32 r4 0x0000001c DDR LAW AR r3 lwz r0 DDR LAW AR r3 isync SET MEM BASE r3 CFG IMMR MDDRC BASE OFFSET SET REG32 r4 CFG MDDRC SYS CFG EN DDR SYS CONFIG r3 SET REG32 r4 CFG MDDRCGRP PM CFG1 DRAMPRIOM PRIOMAN CONFIG1 r3 SET REG32 r4 CFG MDDRCGRP PM CFG2 DRAMPRIOM PRIOMAN CONFIG2 r3 SET REG32 r4 CFG MDDRCGRP HIPRIO CFG DRAMPRIOM HIPRIO CONFIG r SET REG32 r4 CFG DDRCGRP LUTO U DRAMPRIOM LUT TABLEO MAIN UP SET REG32 r4 CFG DDRCGRP_LUTO 1 DRAMPRIOM LUT TABLEO MAIN LOW r3 SET REG32 r4 CFG MDDR
15. f I Freescale Semiconductor Inc 2009 All rights reserved e reescaie semiconductor ADS512101 Board Preparation 2 ADS512101 Board Preparation Verify your board is working The board ships with a version of u boot software in the NOR flash U boot should boot from NOR flash and give you a command prompt on the UARTO serial port The UARTO serial port is configured to 115 200 baud 8 data bits 1 stop bit and no hardware handshaking The factory default for all eight of the SW3 positions is to be on To make the board boot from NAND flash you must put SW3 position 2 to off See the 4DS512101 Advanced Development System User s Manual for further information including a board layout diagram that shows the location of SW3 The board layout diagram is included in this document as Appendix A ADS512101 Top Board Layout The ADS512101 uses a Hynix HY27UG088G 5 D M 1 GB NAND flash which has a x8 bus width and is arranged into 2k 64 pages 3 MPC5121e Microcontroller Configuration 3 1 Reset Chapter 4 Reset ofthe MPC5121e Microcontroller Reference Manual describes the reset process Four fields in the Reset Configuration Word High Register RCWHR affect the NAND flash boot and they must be set accordingly See section 4 7 2 Reset Configuration Word High Register RCWHR for further information regarding these four fields e ROMLOC 1 0 selects the boot device A value of 01 or 11 will select a NAND boot e NFC
16. oard ads5121 config mk 9 nand spl board ads5121 dram h 10 nand spl board ads5121 nandload c 11 nand spl board ads5121 nandstart S 12 nand spl board ads5121 nfc h 13 nand spl board ads5121 u boot lds 4 3 Description of the nand spl Directory Source Code The nand spl secondary program loader directory contains the source to build the image that is automatically loaded into the first page ofthe NAND flash This first page is automatically loaded into the MPC5121e NFC memory during reset The u boot 2008 10 nand spl board ads5121 directory contains the two source code files used to build the nand spl image These two source files are also included below in Section 5 NAND Flash Boot Software The files are 1 nandstart S First code to execute Performs early initialization calls nandload function and jumps to the fully loaded u boot image once it is in DRAM 2 nandload c Contains code that reads the entire u boot image as NAND flash pages and writes them to DRAM 5 NAND Flash Boot Software The initial bootloader software to execute in support of NAND flash boot on the MPC5121e should focus on following the algorithm described in the MPC5121e Microcontroller Reference Manual section 4 6 7 NFC Initialization Sequence This initial bootloader software must configure the hardware platform including the DRAM so that the entire system software can be copied from NAND flash to DRAM This initial bootloader software is limi
17. oftware implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where
18. oftware cannot do anything If an unrecoverable number of symbol errors occur in any of the following NFC pages then software can issue an error status ignore the unrecoverable page or read a duplicate copy ofthe page Duplicate pages require that the NAND flash be programmed accordingly 4 U Boot NAND Flash Boot Software U boot is a bootloader software available from www denx de A u boot that supports NAND flash boot for the MPC5121e was developed in early 2009 using u boot version u boot 2008 10 Four source code files are available with this document and can be downloaded in a zip file that should appear with this application note on freescale com The first two files are patch files used to create a complete u boot source code tree with NAND flash boot support The other two files are a subset of the u boot source code tree but provide easy access to these two key files The files are e u boot 2008 10 ADS5121 NFC NAND Flash Driver 20090130 patch e u boot 2008 10 ADS5121 NAND Flash Boot 20090130 patch e nandstart S e nandload c Obtain u boot version u boot 2008 10 as this is the basis of the software for this document This version of software will only provide support for a NOR flash u boot image for the ADS512101 board Verify you are able to successfully build and run a NOR flash u boot image on your board If you are unfamiliar with NAND Flash Boot for the Freescale MPC5121e Rev 0 Freescale Semiconductor 3
19. r3 According to MPC5121e RM configuring local access windows should be followed by a dummy read of the config register that was modified last and an isync x lwz r4 SRAMBAR r3 isync r3 BOOTFLAG mr A35 VET bl dram init r3 BOOTFLAG mr r3 X21 lis rl CFG INIT RAM ADDR CFG GBL DATA OFFSET Gh ori rl rl CFG INIT RAM ADDR CFG GBL DATA OFFSET G1 copy the full U Boot into DDR bl nandload and jump to it jump uboot SET MEM BASE r10 CFG NAND U BOOT START mtlr rio isync blr NOTREACHED nand boot does not return This code initialises the machine it expects original MSR contents to be in r5 cpu_early init Initialize machine status enable machine check interrupt fed 3 MSR_KERNEL Set ME and RI flags rlwimi r3 r5 0 25 25 preserve IP bit ifdef DEBUG fendif rlwimi r3 r5 0 21 22 debugger might set SE BE bits mtmsr r3 SYNC mtspr SRR1 r3 Mirror current MSR state in SRR1 lis r3 CFG IMMRGh Disable the watchdog lwz r4 SWCRR r3 Check to see if it s enabled for disabling once disabled by s w NAND Flash Boot for the Freescale MPC5121e Rev 0 Freescale Semiconductor 9 NAND Flash Boot Software it s not possible to re enable it Fu andi r4 r4 0x4 beq 1f xor r4 r4 r4 stw r4 SWCRR r3 Initialize the Hardware Implementation dependent Regist
20. re Foundation either version 2 of the License or at your option any later version This program is distributed in the hope that it will be useful but WITHOUT ANY WARRANTY without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE See the GNU General Public License for more details You should have received a copy of the GNU General Public License along with this program if not write to the Free Software Foundation Inc 59 Temple Place Suite 330 Boston MA 02111 1307 USA U Boot NAND Boot Startup Code for MPC5121 Embedded Boards define DEBUG include config h include lt mpc512x h gt include lt version h gt include dram h include nfc h define CONFIG 521X1 needed for Linux kernel header files include ppc asm tmpl include ppc defs h include asm cache h include lt asm mmu h gt ifndef CONFIG IDENT STRING define CONFIG IDENT STRING MPC512X endif Floating Point enable Machine Check and Recoverable Interr aA undef MSR KERNEL ifdef DEBUG define MSR KERNEL MSR FP MSR RI else define MSR KERNEL MSR FP MSR ME MSR RI endif Macros for manipulating CSx START STOP define START REG start start gt gt 16 NAND Flash Boot for the Freescale MPC5121e Rev 0 NAND Flash Boot Software Freescale Semiconductor EN NAND Flash Boot Software define STOP REG start size start
21. t include lt version h gt define CONFIG 521X1 needed for Linux kernel header files include ppc asm tmpl include ppc defs h include asm bitops h include asm io h include lt asm cache h gt include lt asm mmu h gt include nfc h L This function polls the NFC to wait for the basic operation to complete by checking the INT bit of config2 register Qmax retries number of retry attempts Ki static void wait op mjmdone void int i int max retries 10000 ul6 output ul6 temp while 1 max retries output in_bel6 ul6 CFG NAND BASE NFC NF CFG2 temp output if output amp NFC_INT out_bel6 ul6 CFG NAND BASE NEC NF CFG2 break else for i 1000 i gt 0 i NAND Flash Boot for the Freescale MPC5121e Rev 0 0x0 12 Freescale Semiconductor if temp gt 0x8ffa if max_retries lt 0 max retries return void nandload void nand init break 10000 NFC NFC CFG 0x000 NFC SPAS 0x0020 NFC NF CFG1 0x0cb NFC FLASH CMD NAN NFC NF CFG2 NFC C NFC FLASH ADDR Ox NFC NF CFG2 NFC A NFC NF CFG2 NFC A NFC NF CFG2 NFC A NFC NF CFG2 NFC A NFC NF CFG2 NFC A NFC FLASH CMD NAN out bel6 ul6 CFG HAND BASE out bel6 ul6 CFG NAND BASE out bel6 ul6 CFG NAND BASE out
22. ted in size to either 2 KB or 4 KB An alternative initial bootloader software algorithm that can be used to bypass the limit of a single NAND flash page of 512 bytes or 2 KB involves loading intermediate initial software or even the entire system software into the MPC5121e 128 KB on chip SRAM The following code provides example code that performs the algorithm described in the MPC5121e Microcontroller Reference Manual section 4 6 7 NFC Initialization Sequence This code is from the u boot bootloader software See Section 4 U Boot NAND Flash Boot Software for further information regarding u boot 5 1 nandstart S u boot 2008 10 nand spl board ads5121 nandstart S C Copyright 2009 Martha Marx Silicon Turnkey Express mmarx silicontkx com Based on original start S done by S Copyright C 1998 Dan Malek lt dmalek jlc net gt Copyright C 1999 Magnus Damm kieraypcOl p y kie era ericsson se NAND Flash Boot for the Freescale MPC5121e Rev 0 6 Freescale Semiconductor X Xo X Xo X OX F Xo F F Xo F F F xk X ox Copyright C 2000 2001 2002 2007 Wolfgang Denk lt wd denx de gt start S for mpc512x was originally based on the MPC83xx code See file CREDITS for list of people who contributed to this project This program is free software you can redistribute it and or modify it under the terms of the GNU General Public License as published by the Free Softwa
23. y of your u boot 2008 10 source code tree and in the nand sp sub directory nand spl u boot spl 2k bin the 2 KB image that is loaded as the first page from the NAND flash into the NFC internal RAM buffer This image should be programmed into offset 0x0000_0000 of the NAND flash u boot bin the remaining portion of u boot which is copied into DRAM by nand spl u boot spl 2k bin This image should be programmed into offset 0x0000_0800 of the NAND flash u boot nand bin a concatenation of the two files listed above nand spl u boot spl 2k bin and u boot bin If you wish to flash program the entire u boot software in one operation then this image should be programmed into offset 0x0000 0000 of the NAND flash NAND Flash Boot for the Freescale MPC5121e Rev 0 4 Freescale Semiconductor U Boot NAND Flash Boot Software To make your board boot from NAND flash you need to program the u boot nand bin image using a JTAG NAND flash programmer or a u boot that has NAND flash programming capability You must also configure your board to boot from NAND flash as described in Section 2 ADS512101 Board Preparation To program u boot nand bin using a u boot that has NAND flash programming capability the network settings must be configured appropriately Refer to Freescale application note AN3765 Porting Linux for the MPC5121e section 2 2 u boot Source Code from Freescale for further instructions on configuring the network
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