Home
Analog Devices AD9648-125EBZ datasheet: pdf
Contents
1.
2.
3.
4.
5.
6. Figure 28 Power Plane Layer 4 Rev 0 Page 23
7. Figure 25 Top Side Rev 0 Page 20 of 36
8. Figure 29 Ground Plane Layer 5 Rev 0 Page 24 of 36 08168 029 NEI ab ops
9. D E 3 000000 I 000000 D
10. Figure 27 Power Plane Layer 3 Rev 0 Page 22 of 36 08168 027
11. 0606000 666006 666000 1 Figure 30 Bottom Side Rev 0 Page 25 of 36 ORDERING INFORMATION BILL OF MATERIALS Table 1 AD9268 Family BOM Item Qty Reference Designator Description Value Manufacturer Part No 1 1 Not applicable PCBZ 2 9 C101 C132 C133 C134 C135 C136 Capacitor ceramic NP0 10 uF Panasonic ECJ 2FB0J106M C145 C419 C514 3 12 C102 C103 C104 C106 C124 C126 Capacitor 0603 X5R 4 7 uF Panasonic ECJ 1VB0J475M C127 C128 C129 C130 C144 C146 4 7 C105 C117 C119 C121 C123 Capacitor ceramic 10 000 pF Panasonic ECJ 0EB1E103K C125 C143 multilayer X7R 0402 5 68 C116 C118 C120 C122 C149 C150 Capacitor ceramic 0402 0 1 uF Panasonic ECJ 0EX1C104K C151 C152 C153 C154 C204 C206 C207 C208 C209 C211 C301 C302 C403 C404 C405 C406 C407 C417 C418 C420 C426 C503 C504 C505 C506 C507 C515 C516 C523 C601 C602 C603 C606 C607 C609 C701 C702 C710 C711 C712 C713 C714 C715 C716 C717 C718 C719 C720 C721 C723 C724 C730 C731 C801 C802 C803 C804 C805 C806 C807 C808 C809 6 6 C138 C139 C141 C142 C147 C148 Capacitor ceramic chip 22 uF Murata GRM21BR60J226
12. Figure 26 Ground Plane Layer 2 Rev 0 Page 21 of 36 08168 026 O lt lt ee 9 92 O D
13. UNO BEN LTEN UND XITITZMZIN 2 ONO Vier CU JE UND STA TOIT E gt FAEN anr a js ITEN HAAT s dm stew MIDTNE ings 1 9 88 EZT MSI poti JUOH NId NJIdO LINU SSO JUOH IdS 6 8 e nes YA Aus eck ano C2 ANO 1 45 4 4 NJdO dHOD S OML Saa 9 8 BEER 1NA 1 35 AO IdS S v v ETEN dis Bia 2 26 0 S20 N3dOZG3 Sod 2 LE x LS 1na oias OQ T r Zole AT OTUS 300 FAS Sat EY r lt dct TTEN 3 T rd 222 gt TZEN poi ne 4 Tao m T BA T ED AYALINOYIO IdS ING 2 RE a ods gaga OUS B5d4 INO 2 OW 52 ES 9993 ING s pag FOS EN 21135 35614 i INO 2 STV IS VII IOS COEM 2233 2 oas VOEN OUS asn 2 D gs3 aso asn EBEN a Pa ES MIS COE A DS ASN 2 x IOS TOE IdS Or IOS Figure 18 SPI Interface Circuit Rev 0 Page 13 of 36 610 89180 AN9 Naa zara danaky ns vices 1 INO Err Ina INO E INA 04 HNDLE 2 ano ENIdHY stra 2 TTE 5077 Eer P zaouszesay 8 ING Wa ma ded 30
14. A 5 3 L IMT TLOY PRE 2 t t sne WHO WHO saga tsgede 5555 pranjem Loan 335 SS ong 4 rna 8088 na vest 98 Y HLA BU MT Ze KA Dar bi GUJE Auer WHO 699 INO 892604 Lan 225 9 pe Asa age BEES 259 TSO 85 Baso A18 asar z anto 5 vesi 3 5 5 625 2 8 5 52 ue 5 2 854 e so 5555 INA sayo 335 aho 335 mum ddS 865 85 b z 86852 234 GND m 3 2 oer a 2 E ENIdHP nie oja tig ED H 1 aq ER 8 Dm d A ANIBd1004 ZBPO Ol SHOISIC3H WHO TIH JONUHD ING oja 5 S mna ano cava icir W 5 2 duon T S E v TaSar TOS aaa 2 4 o o vcsSu ALAY 854 Dono GT FAHD AMIT YDOHTO INANT OH LING 447 Figure 20 Channel B Analog Input Circuits Rev 0 Page 15 of 36 8 k k 2 x x x 859909 3 x x 699909 A x x x 8SZ509 A 0 x x x 892604 A x x x x 5925609 x x x x Tseedu 9 x x x x Tezedu x x x x vacede zuuser zuwsar 2 28 zuues zuuprl zue o k k k 30 985 2 6 JHUJIHOH x 30285 0330S 1on OHd HILUW OL TOSA 15 82 ONS A ING 415 442 335 ANG HBA T 129 vION me INO LIES H 6 ms 2 635 CE 2 2 20 CT 2
15. 27 Array Math We Average 124 Bit Processor E Bit Shifter i Complex Waveform Merger i Complex Waveform Splitter Data Router wl FFT uk FFT Analysis m ela amp m F E Graph 09268 FFT Z Hilbert Transform Q I vs Q 53 Input Formatter A Inverse FFT Inverse Sinc X Logic Analysis Mixer 25 Output Formatter Peak Hold 38 Power Phase 4 Resampler Resolution Formatter 3f Scalar Math Stop JH Subset II Waveform Analysis TL Window Routine X DC Corr Z3 X QEC 08168 008 Figure 8 VisualAnalog Main Window Setting Up the SPI Controller Software After the ADC data capture board setup is complete set up the SPI Controller software using the following procedure 1 Open the SPI controller software by going to the Start menu or by double clicking the SPIController software desktop icon If prompted for a configuration file select the appropriate one If not check the title bar of the window to determine which configuration is loaded If necessary choose Cfg Open from the File menu and select the appropriate file based on your part type Note that the CHIP ID 1 field should be filled to indicate whether the correct SPI controller configuration file is loaded see Figure 9 CER SPiController 1 0 45 3 USB Ezusb 0 CS 1 AD9268 1681 125
16. INO ang NO mo ZHNOGT DE me avro T 2 INA sata ano anzz anez Easa ZvT2 7 2 INO 8 R I a uer DCK aLa STE v i ER STR Ata a7 T zara NG a INO 4113 awa A R nid sia E INO 2 A zl na 5 ule B age toS aana e 1 RS aha emm JETA ano B lalao 2014 zl a ws 8992 d ao uton cega 2222 sz xr Sarar ana men ge LETO T 58125 ues SER ma gs s dii ST s Lasn m Blo INO TT green 02 INO pel yes 88 ELLEN SLE soar ans ZHNOGT Easa zmo 3 553 ST 8 Sorta S 5 8 erp SHE 50628 E is H 8 E Sr 1 Es ma mal 5 k INO 3 ZE Elton zm gWe 23 z 2 5 8 asr BRT 8 8 8 sara me GE mbi T SE 65926 E K o ina 100054 6 um Silo wale ach 55 ano T 807 Bc oss SEAN y E terece 518 a SSSSSS smeli 2 498 ue Ze GE 888587 aqa zimo E SE DER ur se 2 2 u fak 8 sanga SCT 3 amag Xfm d ano es Sp E PTT M ats 1 E vam L S0153 sara le adi 24 2049822 13002 kz ef T A E m me zm ATdans 825 anzz L anez H 5 I 816 se e SNIHOLIMS 4vTO T BvTO o 2 Se ao zi TE asis 8 8515 Zarar ve Tranon HO LdO ZHumaT STU 3 NG Cora mino 5 1 e moo wi DE SEL T 25 5 EDTJ bg t K aQ Ha 9 tg Earn Ba 82 Q SesE TES Sz 24 8 1 2044822109 LS 8 ER dU oe i 7 i T 1 sto 8 eleg S JFF BTE S ER ZHNO
17. 5 Evaluation Board Software Quick Start Procedures 7 Configuring the Board sse 7 Using the Software for Testing sse 7 Evaluation Board Schematics and Artwork 11 Ordering Information a a rentre tete 26 Bill of Materials ente 8 8 26 ESD Caution 34 Rev 0 Page 2 of 36 EVALUATION BOARD HARDWARE The AD9268 AD9258 AD9251 AD9231 and AD9204 evaluation board provides all of the support circuitry required to operate these parts in their various modes and configurations Figure 2 shows the typical bench characterization setup used to evaluate the ac performance of the AD9268 AD9258 AD9251 AD9231 or AD9204 It is critical that the signal sources used for the analog input and clock have very low phase noise 1 ps rms jitter to realize the optimum performance of the signal chain Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is necessary to achieve the specified noise performance The AD9268 AD9258 AD9251 AD9231 and AD9204 evaluation board covers two general part families The boards are populated slightly differently between the two families The AD9268 and AD9258 are one set of parts supported by this evaluation board and are referred to as the AD9268 family in this document The AD9251 AD9231 and AD9204 are the seco
18. o ant o INO Ina ING E 6T saa eg End 5 POTUJEGOU EMS Tru ETPO sar E HIRE 8 eu s2caqe JE v ING INA INT po 4 51 9371000 Il weem A 442621 9T 94 5 oda dees HNGLZ 225 2 O3N NIN NIGH T soa inon PIPI 2 vipa ES i ER gara zero Sos zl poor ING 2 9I3NO2 31114 0238 530 MO SINJINOGHOD SAT 1238802 BWI SN3010H 32H1d 3 9 COT 353 Tarn Volost Kl MS INT INO aio INO ano r r INO cia 9385 lo 138 too ja IN ano A g 3 8 P aue IND c TN 5 1 TIN 10 8 108 0 9 80 52T MSL E E Cer Ind ob E s Pu ssegau Sse o dedus os t 8 d u E t EN SLEBOH Cs DE ANI SO HH IONOI dO LS mut Cr 5 809 Bu 46 niva LE Te sscgay me Ju 422135 01 035 SI ouzavaH sui Z 479 PAA ina mal mai ina my a HOTS ABTS ABTS HOT ME a Tab vi v v Cord s zvu azvu 6 98 8 8 8 gunn Tavdl ee EE aand vara D E ais ie EL ING ano 7 T T na 3 SNE t IMT T109 s 49 LNT D s ERT Seru mm 4860 225 ND Aha 62 8 bart 3 s WHO WHO ES ddcc TS2604 INT ING v T i imo 3m ING dS 66 LCE vavo 2 4422 WHO BT atro T HN T govo 9998 won Sint z ral E anto Quar 3119924 WHO s ga ING 892604 Sora It k Amt e S E vOv earH BOKYA Dit 4UNTU EBvL Evo very ING se 335 mie SS 4 3gs a sara
19. SMA ST edge mount Rev 0 Page 26 of 36 Item Qty Reference Designator Description Value Manufacturer Part No 23 1 J205 Connector PCB TSW 102 08 G D Samtec TSW 102 08 G D header 4 pos ST 24 2 J301 J701 Connector PCB header TSW 104 08 T D Samtec TSW 104 08 T D 8 pos double row 25 1 J302 Connector PCB header TSW 103 08 G T Samtec TSW 103 08 G T ST male 9 pos 26 3 J403 J503 J605 Connector PCB TSW 102 08 G S Samtec TSW 102 08 G S header 2 pos 27 1 J404 Connector PCB TSW 105 08 G D Samtec TSW 105 08 G D header ST 10 pos 28 2 JP101 JP103 Res jumper 00 Panasonic ERJ 6GEYOROOV SMD 0805 SHRT 29 3 JP 503 L402 L501 Res film SMD 0603 00 Panasonic ERJ 3GEYOR00V 30 4 L403 L404 L503 L504 Inductor ferrite bead 10 Q 100 MHz Murata BLM18BA100SN1 31 1 P101 Connector PCB power PJ 002AH SMT CUI Inc PJ 002AH SMT jack surface mount 32 2 P102 P103 Connector PCB Z5 531 3625 0 Wieland Z5 531 3625 0 header 6 pos 33 3 P901 P902 P903 Connector PCB 6469169 1 Tyco Electronics 6469169 1 60 pin RA connector 34 1 R101 Res film SMD 0402 3000 Panasonic ERJ 2GEJ301X 35 1 R102 Res prec thick 147 Panasonic ERJ 2RKF1473X film chip R0402 36 1 R103 Res prec thick 28 kQ Panasonic ERJ 2RKF2802X film chip R0402 37 1 R104 Res prec thick 100 Panasonic ERJ 2RKF10R0X film chip R0402 38 2 R112 R114 Res prec thick 18 7 KQ Panasonic ERJ 2RKF1872X film chip R0402 39 2 R113 R115 Res chip SMD 0402 15 k
20. C 09248 C AD9251 CJ AD9258 C 0925 12 DL DL m Average FFT Two Tone DLJ Average Two Tone Before using the software for testing configure the evaluation board as follows 1 Connect the evaluation board to the data capture board as shown in Figure 1 and Figure 2 2 Connect one 6 V 2 5 A switching power supply such as the CUI Inc EPS060250UH PHP SZ supplied to the AD9268 AD9258 AD9251 AD9231 or AD9204 board 3 Connect one 6 V 2 5 A switching power supply such as the CUI EPS060250UH PHP SZ supplied to the HSC ADC EVALCZ board 4 Connectthe HSC ADC EVALCZ board J6 to the PC with a USB cable 5 Onthe ADC evaluation board confirm that three jumpers are installed on J302 one between Pin land Pin 2 one between Pin 4 and Pin 5 and one between Pin 8 and Pin 9 to connect the SPI bus to the DUT 6 Ifusing an AD9251 family board ensure that J605 OSC EN has a jumper installed to use the on board 50 MHz 65 MHz 80 MHz Valpey Fisher V FAC3 oscillator If using an AD9268 family board make sure a low jitter sample clock is applied at J602 7 Onthe ADC evaluation board use a clean signal generator with low phase noise to provide an input signal to the desired A and or B channel s Use a 1 m shielded RG 58 50 Q coaxial cable to connect the signal generator For best results use a narrow band band pass filter with 50 Q terminations and an appropriate center f
21. 26 3 J403 J503 J605 Connector PCB TSW 102 08 G S Samtec TSW 102 08 G S header 2 pos 27 1 J404 Connector PCB TSW 105 08 G D Samtec TSW 105 08 G D header ST 10 pos 28 2 JP101 JP103 Res jumper SMD 00 Panasonic ERJ 6GEYOROOV 0805 SHRT 29 7 JP503 L402 L403 L404 L501 L503 L504 Res film SMD 0603 00 Panasonic ERJ 3GEYOR00V 30 1 P101 Connector PCB power PJ 002AH SMT CUI Inc PJ 002AH SMT jack surface mount 31 2 P102 P103 Connector PCB Z5 531 3625 0 Wieland Z5 531 3625 0 header 6 pos 32 3 P901 P902 P903 Connector PCB 6469169 1 Tyco Electronics 6469169 1 60 pin RA connector 33 1 R101 Res film SMD 0402 300 Q Panasonic ERJ 2GEJ301X 34 1 R102 Res prec thick 147 kQ Panasonic ERJ 2RKF1473X film chip R0402 35 1 R103 Res prec thick 28 Panasonic ERJ 2RKF2802X film chip R0402 36 1 R104 Res prec thick 100 Panasonic ERJ 2RKF10R0X film chip R0402 37 2 R112 R114 Res prec thick 18 7 ko Panasonic ERJ 2RKF 1872X film chip R0402 38 2 R113 R115 Res chip SMD 0402 15 kQ Panasonic ERJ 2RKF 1502X 39 8 R206 R208 R209 R309 R316 R317 Res prec thick 10 kQ Panasonic ERJ 2RKF 1002X R801 R802 film chip R0402 40 2 R207 R733 Res prec thick 57 60 Panasonic ERJ 2RKF57R6X film chip R0402 41 13 R121 R123 R310 R311 R312 R422 Res prec thick 1 00 ko Panasonic ERJ 2RKF1001X R522 R614 R704 R705 R706 R707 R709 film chip R0402 42 5 R105 R106 R313 R314 R315 Res prec thick 100 ko Panasonic ERJ 2RKF1003X film chip
22. C111 C113 C519 Capacitor chip mono 100 pF Murata ceramic COG 0402 GRM1555C1H101JD01D 72 C112 Capacitor ceramic 0402 1500 pF Panasonic ECJ 0EB1H152K 73 C137 C140 Capacitor ceramic N A N A SMD 0603 74 C408 C409 C411 C508 C509 C511 Capacitor ceramic NPO 5 pF Panasonic ECJ E1H050CCQ 75 C201 C202 C412 C413 C414 C415 Capacitor ceramic 0402 0 1 uF Panasonic ECJ 0EX1C104K C416 C421 C427 C512 C513 C521 C522 C601 C703 C704 C708 C709 76 C422 C423 Capacitor ceramic 1200 pF Panasonic ECJ 0EB1E122K multilayer X7R 0402 77 C424 Capacitor ceramic 2 7 pF Samsung CLO5C2R7CBNC 78 C425 Capacitor mono 20 pF Murata ceramic COG 0402 GRM1555C1H200JZ01D 79 C517 C518 Capacitor ceramic 1000 pF Panasonic ECU E1E102KBO 80 C520 Capacitor ceramic 39 pF Phy Comp Yageo 0402CG390J9B200 81 E104 E106 E108 E116 E117 E118 E119 Inductor ferrite bead 100 MHz Panasonic EXC ML20A390U 82 J401 J502 J601 J702 J703 J704 Connector PCB SMA SMA J P X ST EM1 Samtec SMA J P X ST EM1 ST edge mount 83 JP102 JP104 Res jumper SMD 00 Panasonic ERJ 6EYOROOV 0805 SHRT 84 L101 L102 Inductor SM 2 2 uH TOKO FDV0630 2R2M 85 L401 L502 Res film SMD 0603 0Q Panasonic ERJ 3GEYOROOV 86 L405 L505 Inductor SM 100 nH Coilcraft 0603CS R10XGLU Rev 0 Page 32 of 36 Item Qty Reference Designator Description Value Manufacturer Part No 87 L406 L407 Inductor SM 1 uH Coilcraft 0
23. MHz Figure 15 Typical FFT AD9268 AD9258 Troubleshooting Tips If the FFT plot appears abnormal do the following e Ifyou see a normal noise floor when you disconnect the signal generator from the analog input be sure you are not overdriving the ADC Reduce the input level if necessary 9 In VisualAnalog click the Settings button in the Input Formatter block Check that Number Format is set to the correct encoding offset binary by default Repeat for the other channel If the FFT appears normal but the performance is poor check the following e Make sure an appropriate filter is used on the analog input e Make sure the signal generators for the clock and the analog input are clean low phase noise e Change the analog input frequency slightly if noncoherent sampling is being used 9 Make sure the SPI config file matches the product being evaluated Ifthe FFT window remains blank after Run is clicked do the following e Make sure the evaluation board is securely connected to the HSC ADC EVALCZ board e Make sure the FPGA has been programmed by verifying that the DONE LED is illuminated on the HSC ADC EVALCZ board If this LED is not illuminated make sure the U4 switch on the board is in the correct position for USB CONFIG e Make sure the correct FPGA program was installed by selecting the Settings button in the ADC Data Capture block in VisualAnalog Then select the FPGA tab and verify that the proper FPGA bin
24. 105 MHz Valpey Fisher LSTTL compatible VFAC3BHL 105MHZ 68 1 Y601 80 for 80 model U201 IC clock OSC ACMOS 80 MHz Valpey Fisher LSTTL compatible VFAC3BHL 80MHZ 69 C108 C109 Capacitor ceramic 10 000 pF Panasonic ECJ OEB1E103K multilayer X7R 0402 70 C110 Capacitor ceramic 2200 pF Phycomp Yageo CC0402KRX7R9BB222 71 C111 C113 C519 Capacitor ceramic 100 pF Murata mono cer COG 0402 GRM1555C1H101JD01D 72 C112 Capacitor ceramic 0402 1500 pF Panasonic ECJ 0EB1H152K 73 C137 C140 Capacitor cer SMD 0603 N A N A 74 C408 C409 C410 C411 C508 C509 Capacitor ceramic NPO 5 pF Panasonic ECJ E1H050CCQ C510 C511 75 C201 C202 C412 C413 C414 C415 Capacitor ceramic 0402 0 1 HF Panasonic ECJ 0EX1C104K C416 C421 C427 C512 C513 C521 C522 C610 C703 C704 C708 C709 76 C422 C423 Capacitor ceramic 1200 pF Panasonic ECJ OEB1E122K multilayer X7R 0402 77 C424 Capacitor ceramic 2 7 pF Samsung CLO5C2R7CBNC 78 C425 Capacitor mono 20 pF Murata ceramic COG 0402 GRM1555C1H200JZ01D 79 C517 C518 Capacitor ceramic 1000 pF Panasonic ECU E1E102KBO 80 C520 Capacitor ceramic 39 pF Phycomp Yageo 0402CG390J9B200 81 E104 E106 E108 E116 E117 E118 E119 Inductor ferrite bead 100 MHz Panasonic EXC ML20A390U 82 4401 J502 J601 J702 J703 J704 Connector PCB SMA J P X ST EM1 Samtec SMA J P X ST EM1 SMA ST edge mount 83 JP102 JP104 Resistor jumper 00 Panasonic ERJ GEYOROOV SMD 0805 SHRT 84 L101 L102 Induct
25. 27 of 36 Item Qty Reference Designator Description Value Manufacturer Part No 55 3 U101 U104 U105 IC ADI low dropout ADP1708ARDZ R7 Analog Devices Inc CMOS line regulator ADP1708ARDZ R7 56 2 U102 U106 IC ADI low dropout ADP1706ARDZ 3 3 R7 Analog Devices Inc CMOS line regulator ADP1706ARDZ 3 3 R7 57 1 U103 IC ADI low dropout ADP1706ARDZ 1 8 R7 Analog Devices Inc CMOS line regulator ADP1706ARDZ 1 8 R7 58 1 U201 Generic LFCSP64 9X9 AD9268BCPZ 125 or Analog Devices Inc 9PAD1 8X1 8 footprint AD9258BCPZ 125 AD9268BCPZ 125 or AD9258BCPZ 125 59 1 U301 IC TinyLogic UHS NC7WZ07P6X Fairchild Semiconductor dual buffer NC7WZ07P6X 60 3 U302 U703 U803 ICTinyLogic NC7WZ16P6X Fairchild Semiconductor UHS dual buffer NC7WZ16P6X 61 1 401 IC ultralow AD8375ACPZ Analog Devices Inc distortion IF VGA AD8375ACPZ 62 1 U501 IC 2 6 GHz ultralow ADL5562 PRELIM Analog Devices Inc distortion RF IF diff amp ADL5562 63 1 U701 IC ADI 12 output CLK AD9517 ABCPZ Analog Devices Inc generator with integrated AD9517 4BCPZ 1 6 GHZ VCO 64 2 U801 U802 IC TTL low voltage 74VCX162827MTDX Fairchild Semiconductor 20 bit buffer 74VCX162827MTDX 65 1 VR101 IC ADI dual configurable ADP2114_PRELIM Analog Devices Inc synchronous stepdown ADP2114 dc to dc regulator 66 1 Y601 125 for 125 model U201 IC clock OSC ACMOS 125 MHz Valpey Fisher LSTTL compatible VFAC3BHL 125MHZ 67 1 Y601 105 for 105 model U201 IC clock OSC ACMOS
26. 53a 8 DZ Deano sora anz L 526 ago T ma ano 22 wa Zem Ud AE UMS TEL s de e oas tkr NN rani 3 raid Ge orgs ras ER A EF DEE ome er as l EE Sauer une CHE ano mo vao 38 48 s uslno alno ER Set Tra sino n sino V ina g Gre vsino sino 1 DEEN 1 6 vino na a z Kaka M NOTO TN ING ING Slo DE tino ECKER 8 67 5 57 cud Ge zen Pi Kees 6728 158 gaz 228 12 X I2 HBA w vu N T LYS 52 8 E DEI N T1n0 703d no ou SI T1no 03d 5E m our a I i ZE Ca Hg NOTRE gt no ne s E DOS HI I ES m ZAJNONONIJOH Gp or 37 nouas 605 1 NDD DOY T Lasu razo ano GC pa B2 26 sa 7226 a l XSd8TZMLON pe EN r ISCH 728 ana z 55 Paa cada il MISBBELXI HS 202 AD 25 z 1 381 2 32 13 Glo M 1233 Figure 22 Optional AD9517Clock Input Circuit Rev 0 Page 17 of 36 20 89180 e e UH WHO 22 WHO Deel WHO HHO B22 1S260H XOLHLZBESTXINVL 834 A A WHO cc WHO 22 WHO zc WHO z2 892604 Le vOSNH OSNH COSNH TOSNH amoo Z bal guo o az asta 0 2 a
27. 7 T 66 92 825 t bs ako GND V 3 a sc i 8 s SERA eg 18 z za Zu E D 8 ING on S 1NIMdiOO4 Zera OL SMOISIS3M WHO JONAHO dopauae u m ano Dome T 8 E 7 sat RER Taro 235 Tad 9 o o 5 8 TANI gue TOYL 00000 6ST202 HTHU Aal IMOdID lfldNI DO TONG 1 13 330 UNNI e IOdNI Figure 19 Channel A Input Circuits Rev 0 Page 14 of 36 020 89180 Mea r G ndug ne rA cesr ana ano INA INO INO poo zav HNSE HNST oe d See etsy dei ING voan k k sl BA e anta o 3019 ces Basi 8 52 Lu Jes g 1naNI C T 5 Sur DC 58 INA Sla Du ETSO T wA 2259 EI n Pee ma U NTA Sun TESTI 4 6 ESCH EM 6 eT Y d iuo INA 6 52 6159 8 58 kabi z don Ina Lou HNEB 77140 dije a INA 235 Tad ees m ar merle 2 v e F Ina INO ier ma T 558 ING 2 58 IN AAA HNSE HNST a o mg ant 9 585 5 4 dg de 1esn S tz E atsa sasa 2182 EIS vTSH sd 58 ba TEEN WI T3td 2955109 5 52 Sd OIJNOO HALILI OINIGMI 80 4 SINJNOGHOD Y GINA 1238802 JOVIL GASTON 389 CITH ISH T c GHD INANI SO JNU IUNOI LdO 6 ano 301 252 et ZEN g ana won MINI GL A ING ano
28. A7 EZBNA astr asia plex as 8860 0 Sr 1HdHO 336 SOSNH ouo sero ST sarr Sg obra YL MISZEOLXI NS ope E usqo e Coop gore K 290 USI O T 335 S v m 5288 een E upo UBIT usta BEN S nn ano 12859 ka MEI vE0 0 aT Coon LD 335 JAMHHI 336 Ate E 5 ana Tee pyr 5082 ven sir g uo ger s 8026 saro Cous T SNY si Ns H TINNGHOI L DE E SH Ge oi s INN ro ly Ut 8 mum M M T gana anta 3 a Lanta Lanta 28 5 538 3 35 ano vago w8 gt cago Taso Figure 23 Output Buffer Circuits Rev 0 Page 18 of 36 vc0 89180 T 69T69v9 43093H 501 13 T 69T69v9 301 34 20 dd co6d T 6ST69r9 d3de3H 2 T90 126 T 69T6eSrg GNO ONO 313344 0N d Cu Q m 4 158 DCH OC 294 goa SH og EH i ii i Tod 6d T 69T69r9 dd JUHJH DITId TOH 2 6d T 69T69v9 ONO dd JUHIH 531 Id DI 698 god 29H goa Sod DA ET cod Tod T 6d T 69T6979 lata 58 SE reu c ka 2 88 m Ed 5 0 H EC ER Ta 6d 1 69169r9 ata lea EN r fu 5 LU I 9G Mad o FU m EU gu ra cObd T 69169v9 lara lea EE r EU S pa 8201 I D ga 37 za ma TOO6d pu SLEBOH cO SLSBOU Qo
29. SLEBOUH T 69T69r9 831334 ON Id 218 6a sa Za Sa ES ra EH ES TE 6d T 69TE9ry9 33043hH DT Id uta ea sa 2H Sd SHE vd Ed cu TS 206d T 6916979 9309 H 2 1 DI ed lea 2H SE SH va EH ca Ta T26d 69T69y9 2 2 80 ES u 82 grid O E 59 gera o 23 gara o m 80 0 x EU S4c8aqu B p a m JED gr _o 1 g om a 22 ged o TO Blies 6d T 69T69v3 aTo 80 IECH 2 go aptd o c DI 8 0 9 E 88 0 E agu o 2 TI garo m JED Groo z azaro TI 89 c06d T 69T69y7S MIDSTBOdJ 2 5 946 4 160 o 5 LI MIOSTESA 85 ras gsn oqs gsn D Vo OSC Odd A n Eo ZO TO T 6d T 69T69v9 33043H DITId 59 TO 6d T 69T69y9 93093H 2 ld co6d T 69T6Sv9 943063H DT Id PIE BY gy Z9 zi eo x o io T di di di T T T 6d gu Lu gu 22 EU CH Oty BETO O grid o 46070 0 usq o vedo gra o Sg WI o SSTOTO SETITO artt o gea o gag o asao HCOo atao ASI 43d4 E5 HS 859372715604 Figure 24 FIFO Board Connector Rev 0 Page 19 of 36
30. can be enabled by adding a jumper on J403 The Channel B input is also set up with an optional input path through the ADL5562 ultralow distortion RF IF differential amplifier Similar to Channel A the amplifier is included on the board at U501 however the input output related components 0 1pF 0 1pF 0 1pF BEAD 100 100MHz BEAD 100 100MHz are not included Users should see the ADL5562 data sheet for additional information on this part and for configuring the inputs and outputs The ADL5562 is also normally held in power down mode and can be enabled by adding a jumper on J503 The ADL5562 on the Channel B input can also be substituted with the ADA4937 or the ADA4938 to allow evaluation of these parts with the ADC VREF VREF is set by default to 1 0 V with SENSE connected to AGND through a jumper connecting Pin 4 and Pin 6 on Header J201 This causes the ADC to operate with the internal reference in the 2 0 V p p differential full scale range The AD9251 family operates with a fixed 1 0 V reference For the AD9268 family the reference voltage can be changed to 0 5 V fora 1 0 V p p full scale range by moving the SENSE pin jumper connection on J201 from Pin 4 through Pin 6 to Pin 3 through Pin 4 this connects the SENSE pin to the VREF pin For the AD9268 family to use the programmable reference mode a resistor divider can be set up by installing R204 and R205 The jumper on J201 should be removed for this mode of operat
31. is set to the following configuration MO ON M1 OFF M2 OFF If the configuration is successful you will see the DONE light T Do not show this message again EG 8 d o 08168 006 Figure 6 VisualAnalog Default Configuration Message To change features to settings other than the default settings click the Expand Display button located on the bottom right corner of the window to see what is shown in Figure 8 Detailed instructions for changing the features and capture settings can be found in the AN 905 Application Note VisualAnalog Converter Evaluation Tool Version 1 0 User Manual After the changes are made to the capture settings click Collapse Display see Figure 7 VisualAnalog Canvas AD9268 FFT Edit View Canvas Tools Window Help 08168 007 Figure 7 VisualAnalog Window Toolbar Collapsed Display Rev 0 Page 7 of 36 File Edit View Canvas Tools Window Help visualAnalog Canvas AD9268 FFT lol xl E s 8 9988 Components E Board Interfaces ADC Data Capture E FIFO4 x Interface ps Miscellaneous Comment 5 Models Input Formatteti Data fouer Window Routine a D 6 Window Blackman Harris z M ADC Model ami Generic Model 51 89 Processes Input Formatter Window Routine Window Blackman Hartis amp
32. of 36 08168 028
33. supplies be used for both analog and digital domains An additional supply is also required to supply 1 8 V for digital support circuitry on the board DVDD This should also have a 1 A current capability and can be combined with DRVDD with little or no degradation in performance To operate the evaluation board using the SPI and alternate clock options a separate 3 3 V analog supply is needed in addition to the other supplies This 3 3 V supply or 3V CLK should have a 1 A current capability Two additional supplies 5V AMPVDD and 3V AMPVDD are used to bias the optional input path amplifiers and optional VREF buffer If used these supplies should each have 1 A current capability A second optional power supply configuration allows replacing the LDOs that supply the AVDD and DRVDD rails of the ADC with the ADP2114 step down dc to dc regulator Using this switching controller in place of the LDO regulators to power the AVDD and DRVDD supplies of the ADC allows customers to evaluate the performance of the ADC when powered by a more efficient regulator INPUT SIGNALS When connecting the clock and analog source use clean signal generators with low phase noise such as the Rohde amp Schwarz SMA or HP 8644B signal generators or an equivalent Use a 1 m shielded RG 58 50 Q coaxial cable for connecting to the evaluation board Enter the desired frequency and amplitude see the Specifications section in the data sheet of the respective pa
34. 251BCPZ xx Analog Devices Inc 9PAD1_8X1_8 footprint AD9231BCPZ xx or AD9251BCPZ xx AD9204BCPZ xx AD9231BCPZ xx or AD9204BCPZ xx 58 1 U301 IC TinyLogic UHS NC7WZ07P6X Fairchild Semiconductor dual buffer NC7WZ07P6X 59 3 U302 U703 U803 IC TinyLogic UHS NC7WZ16P6X Fairchild Semiconductor dual buffer NC7WZ16P6X 60 1 U401 IC ultralow AD8375ACPZ Analog Devices Inc distortion IF VGA AD8375ACPZ 61 1 U501 IC 2 6 GHz ultralow ADL5562 PRELIM Analog Devices Inc distortion RF IF diff amp ADL5562 PRELIM 62 1 U701 IC ADI 12 output CLK AD9517 4BCPZ Analog Devices Inc generator with integrated AD9517 4BCPZ 1 6 GHz VCO 63 2 U801 U802 IC TTL low voltage 74VCX162827MTDX Fairchild Semiconductor 20 bit buffer 74VCX162827MTDX 64 1 VR101 IC ADI dual configurable ADP2114 PRELIM Analog Devices Inc synchronous stepdown ADP2114 PRELIM dc to dc regulator 65 1 Y601 80 for 80 model U201 IC clock OSC ACMOS 80 MHz Valpey Fisher LSTTL compatible VFAC3BHL 80MHZ 66 1 Y601 65 for 65 model U201 IC clock OSC ACMOS 65 MHz Valpey Fisher LSTTL compatible VFAC3BHL 65MHZ 67 1 Y601 40 for 40 model U201 IC clock OSC ACMOS 40 MHz Valpey Fisher LSTTL compatible VFAC3BHL 40MHZ 68 1 Y601 20 for 20 model U201 IC clock OSC ACMOS 20 MHz Valpey Fisher LSTTL compatible VFAC3BHL 20MHZ 69 C108 C109 Capacitor ceramic 10 000 pF Panasonic ECJ OEB1E103K multilayer X7R 0402 70 C110 Capacitor ceramic 2200 pF Phy Comp Yageo CC0402KRX7R9BB222 71
35. 6 Res film SMD 0402 300 Q Panasonic ERJ 2GEJ301X 107 R417 R418 R419 R420 R421 Res prec thick 10 kQ Panasonic ERJ 2RKF 1002X film chip R0402 108 R512 R513 Res prec thick 40 2 Q Panasonic ERJ 2RKF40R2X film chip R0402 109 R613 Res film SMD 0402 1000 Panasonic ERJ 2GEJ101X 110 T403 T503 XFMR RF ADT1 1WT Mini Circuits ADT1 1WT 111 T404 XFMR RF TC3 1T Mini Circuits TC3 1T 112 T505 T602 XFMR RF 1 1 MABA 007159 000000 M A Com 6 pin special MABA 007159 000000 113 TP101 TP102 TP402 TP601 Connector PCB BLK Components Corp TP801 TP802 TST PNT black TP 104 01 00 114 TP9 TP401 TP701 TP702 Connector PCB WHT Components Corp TP703 TP704 TP705 TST PNT white TP 104 01 09 115 U702 IC ADI ultrafast SIGe ECL ADCLK905BCPZ WP Analog Devices Inc clock data buffers ADCLK905BCPZ WP 116 CR201 IC ADI 1 2 V micropower AD1580ARTZ Analog Devices Inc precision shunt voltage AD1580ARTZ reference 117 U202 IC ADI single supply AD822BRZ Analog Devices Inc rail to rail low power AD822BRZ FET input op amp Do not install Rev 0 Page 33 of 36 ESD CAUTION A ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation o
36. 603LS 102XGLB 88 L408 L409 L410 L411 Inductor SM 270 nH Coilcraft 0603CS R27XGLW 89 L508 L509 Chip inductor 15 nH Coilcraft 0603CS 15NXGLU 90 L510 L520 Chip inductor 36 nH Coilcraft 0603CS 36NXGLU 91 L521 L522 Inductor SM 82 nH Coilcraft 0603CS 82NXGLU 92 R107 Res chip SMD 0402 27 kQ Panasonic ERJ 2RKF2702X 93 R108 Res prec thick 10 5 kO Panasonic ERJ 2RKF1052X film chip R0402 94 R109 Res chip SMD 0402 4 75 KQ Panasonic ERJ 2RKF4751X 95 R110 R111 Res chip SMD 0402 15ko Panasonic ERJ 2RKF1502X 96 R116 R117 Res chip SMD 0603 N A N A 97 R118 Res chip SMD 0402 13 kQ Yageo 9C04021A1302FLHF3 98 C501 JP401 JP402 JP501 JP502 R120 Res film SMD 0402 00 Panasonic ERJ 2GEOROOK R122 R124 R125 R126 R127 R305 R306 R307 R308 R405 R407 R410 R411 R413 R414 R415 R423 R505 R507 R510 R511 R514 R515 R516 R517 R519 R520 R521 R603 R604 R605 R607 R608 R721 R722 R731 R732 99 R518 Res prec thick 1 00 ko Panasonic ERJ 2RKF1001X film chip R0402 100 R201 Res prec thick 2ko Panasonic ERJ 2RKF2001X film chip R0402 101 R202 Res VAR 3 8 inch 10 kQ Bourns Inc 3299W 1 103 SQ top adj 102 R204 R205 Res chip SMD 0402 N A N A 103 R401 R402 R501 R502 R601 Res prec thick 57 60 Panasonic ERJ 3EKF57R6V film chip R0603 104 R406 R506 R719 R720 Res prec thick 49 9 Q Panasonic ERJ 2RKF49R9X film chip R0402 105 R412 Res prec thick 1300 Panasonic ERJ 2RKF1300X film chip R0402 106 R41
37. 8 IDUNOS 30 HOLYTIYIOSO HIEN TUNOILAO Taw k k ATONE 4 WHO ING 916 6 8 52 4 ING dd8881 TI91SNI Ina 892604 A 2195 EIER 229 TOSL Ene Doan JH L mo NG eg D DIS Ita 2628 anono 5 5 SLA do E AMdHHD iue aT Q coSl a H y Sa am zi SEA root E Z409 EISH ATEN 5 g o CO c FIMT T105 a ANT G e 2 LA ao ane 2 7 T 9094 od T a 1NG HO3N NOILUNIWHIL JUNOIIJO 5 P na 2 m RARS o NI 1915X A NTEETEZ SWSH EI E ano INANI X20709 458 42 3225 MGB D D 1224 ens A Wa 9252 TISA 6294 ag ING 4 ad 2 a INT gash a mer T8 ki T 5298 mesa Tasr SS NIMID AALIMONID NIO NIYA Z XWX Figure 21 Default Clock Path Input Circuits Rev 0 Page 16 of 36 3 A 8 ano s va LEJ R 8 axo EE a ST DE Amt e ant o OO TEGA 8125 122 anta mg a 3 m 8 min NP arum S 3 52 873 9 22 1129 STS sess UTA gt d 5 407 e 20 5 UL ME EN mx E S Ll 8 O S149 2122 pon 3 ER E Kate 3 a A ano x KSI 830 H ET d dWNd dOHUHO T Tif6
38. ANALOG DEVICES Evaluation Board User Guide UG 003 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 Fax 781 461 3113 www analog com Evaluating the AD9268 AD9258 AD9251 AD9231 AD9204 Analog to Digital Converters FEATURES Full featured evaluation board for the AD9268 AD9258 AD9251 AD9231 AD9204 SPI interface for setup and control External on board oscillator or AD9517 clocking options Balun transformer or amplifier input drive options LDO regulator or switching power supply options VisualAnalog and SPI controller software interfaces EQUIPMENT NEEDED Analog signal source and antialiasing filter Sample clock source if not using the on board oscillator 2 switching power supplies 6 0 V 2 5 A CUI EPS060250UH PHP SZ provided PC running Windows 98 2nd ed Windows 2000 Windows ME or Windows XP USB 2 0 port recommended USB 1 1 compatible AD9268 AD9258 AD9251 AD9231 or AD9204 evaluation board HSC ADC EVALCZ FPGA based data capture kit SOFTWARE NEEDED VisualAnalog SPI controller DOCUMENTS NEEDED AD9268 AD9258 AD9251 AD9231 or AD9204 data sheet HSC ADC EVALCZ data sheet AN 905 Application Note VisualAnalog Converter Evaluation Tool Version 1 0 User Manual AN 878 Application Note High Speed ADC SPI Control Software AN 877 Application Note Interfacing to High Speed ADCs via SPI AN 835 Application Note Understanding ADC Testing and Evalu
39. CJ OEB1E182K multilayer X7R 0402 11 1 C706 Capacitor ceramic 0 033 uF Panasonic 0402YD333KAT2A 12 1 C707 Capacitor ceramic 0402 1500 pF Panasonic ECJ 0EB1H152K 13 1 C722 Capacitor ceramic 0 22 UF Panasonic ECJ OEBOJ224K 14 5 CR101 CR102 CR104 CR105 CR106 Diode recovery rectifier S2A TP Micro Commercial Components Corp S2A TP 15 1 CR103 LED green LNJ308G8TRA green Panasonic LNJ308G8TRA surface mount 16 1 CR601 Diode Schottky HSMS 2812BLK Avago Technologies dual series HSMS 2812BLK 17 3 CR701 CR801 CR802 LED red surface mount SML LXTO805IW TR Lumex SML LXTO805IW TR 18 12 E101 E102 E103 E105 E107 E109 Inductor ferrite bead 100 MHz Panasonic EXC ML20A390U E110 E111 E112 E113 114 E115 19 1 F101 Fuse polyswitch 1 6A Tyco Electronics PTC device MINISMDC160F 2 20 1 FL101 Filter noise suppression BNX016 01 Murata BNX016 01 LC combined type 21 1 J201 Connector PCB Berg TSW 103 08 G D Samtec TSW 103 08 G D header double STR male 6 pos 22 7 J203 J402 J501 J602 Connector PCB SMA SMA J P X ST EM1 Samtec SMA J P X ST EM1 ST edge mount 23 1 J205 Connector PCB header TSW 102 08 G D Samtec TSW 102 08 G D 4 pos ST 24 2 J301 J701 Connector PCB header TSW 104 08 T D Samtec TSW 104 08 T D 8 pos double row 25 1 J302 Connector PCB TSW 103 08 G T Samtec TSW 103 08 G T header ST male 9 pos Rev 0 Page 30 of 36 Item Qty Reference Designator Description Value Manufacturer Part No
40. ME39L 7 3 C107 C203 C205 Capacitor ceramic 1 uF Panasonic ECJ 0EF0J105Z 8 27 C401 C402 C502 JP403 R203 R301 R302 Res film SMD 0402 00 Panasonic ERJ 2GEOROOK R303 R304 R424 R425 R524 R525 R526 R606 R609 R610 R611 R612 R708 R715 R723 R727 R728 R729 R803 R804 9 1 C604 Capacitor ceramic 1000 pF Panasonic ECU E1E102KBQ 10 1 C705 Capacitor ceramic 1800 pF Panasonic ECJ 0EB1E182K multilayer X7R 0402 11 1 C706 Capacitor ceramic 0 033 uF Panasonic 0402YD333KAT2A 12 1 C707 Capacitor ceramic 0402 1500 pF Panasonic ECJ 0EB1H152K 13 1 C722 Capacitor ceramic 0 22 uF Panasonic ECJ 0EBOJ224K 14 5 CR101 CR102 CR104 CR105 CR106 Diode recovery rectifier S2A TP Micro Commercial Components Corp S2A TP 15 1 CR103 LED green LNJ308G8TRA Panasonic LNJ308G8TRA surface mount green 16 1 CR601 Diode Schottky HSMS 2812BLK Avago Technologies dual series HSMS 2812BLK 17 3 CR701 CR801 CR802 LED red surface mount SML LXTO805IW TR Lumex SML LXTO805IW TR 18 12 E101 E102 E103 E105 E107 E109 Inductor ferrite bead 100 MHz Panasonic E110 E111 E112 E113 E114 E115 EXC ML20A390U 19 1 F101 Fuse polyswitch 1 6A Tyco Electronics PTC device MINISMDC160F 2 20 1 FL101 Filter noise suppression BNX016 01 Murata BNX016 01 LC combined type 21 1 J201 Connector PCB Berg TSW 103 08 G D Samtec TSW 103 08 G D header double STR male 6 pos 22 4 J203 J402 J501 J602 Connector PCB SMA J P X ST EM1 Samtec SMA J P X ST EM1
41. MSspiR03 cig AD9268 16Bit 1 25MSspSl03 cal Me Coto Heb mig ci are Global ADOBme 0 ADC A ADCB CHIP PORT Cem DEVICE INDEXA ADC I 158 Ft e FB Read 16t s n CHIP GRADE 2 125 MSPS 08168 009 6 15 2009 1051 52 AM Figure 9 SPI Controller CHIP ID 1 Box 2 Click the New DUT button in the SPIController window see Figure 10 SPiContreller 1 0 45 3 USB Ezusb 0 CS 1 AD9268 16Bit 125M5spIRD3 cfg AD9268 168 125MSspiR03 cal C Ble Config NEW DUT BUTTON NM 0 OE HE ADCBass 0 ADCA ADC B CHIP PORT CF6I0 DEVICE INDEX Q ADC r 158 Fint ES Ko pm Resi Siem Dual 16 b 5 A CHIP GRADE 2 e 1555 5 8 671572003 1051 52 AM 5 Figure 10 SPI Controller New DUT Button In the ADCBase 0 tab of the SPIController window find the CLOCK DIVIDE B box see Figure 11 If using the clock divider use the drop down box to select the correct clock divide ratio if necessary See the appropriate part data sheet the AN 878 Application Note High Speed ADC SPI Control Software and the AN 877 Application Note Interfacing to High Speed ADCs via SPI for additional information 8 0 45 3 z USD zu 0 CS AD9268 1 6001 125M5SpiROJ PR Ges Arben ACCA ece TEST MSA 1 DAC CMDS DRIVE STREMGTAJSI 8 1968 Ch De Nest Spr r TO Ch De See Enab
42. Q Panasonic ERJ 2RKF 1 502X 40 8 R206 R208 R209 R309 R316 R317 Res prec thick 10 kQ Panasonic ERJ 2RKF 1002X R801 R802 film chip R0402 41 2 R207 R733 Res prec thick 57 6 Q Panasonic ERJ 2RKF57R6X film chip R0402 42 13 R121 R123 R310 R311 R312 R422 R522 Res prec thick 1 00 ko Panasonic ERJ 2RKF1001X R614 R704 R705 R706 R707 R709 film chip R0402 43 5 R105 R106 R313 R314 R315 Res prec thick 100 kQ Panasonic ERJ 2RKF1003X film chip R0402 44 5 R403 R404 R503 R504 R741 Res film SMD 0402 330 Panasonic ERJ 2GEJ330X 4 R408 R409 R508 R509 Res film SMD 0402 66 5 Q Panasonic ERJ 2RKF66R5X 46 1 R602 Res prec thick 57 6 Q Panasonic ERJ 3EKF57R6V film chip R0603 47 1 R710 Res prec thick 4 12 kQ Panasonic ERJ 2RKF4121X film chip R0402 48 1 R711 Res prec thick 5 11 kO Panasonic ERJ 2RKF5111X film chip R0402 49 8 R714 R716 R725 R730 R738 R739 Res prec thick 200 Q Panasonic ERJ 2RKF2000X R805 R806 film chip R0402 50 2 R726 R740 Res film SMD 0402 1000 Panasonic ERJ 2GEJ101X 51 2 R734 R736 Res prec thick 1300 Panasonic ERJ 2RKF1300X film chip R0402 52 2 R735 R737 Res prec thick 82 5 Q Panasonic ERJ 2RKF82R5X film chip R0402 53 9 RN801 RN802 RN803 RN804 RN805 Res NTWRK 8 pin 4 res 220 CTS 742C083220JCT RN806 RN807 RN808 RN809 surface mount 54 5 T401 T402 T501 T502 T602 XFMR RF 1 1 6 pin special MABA 007159 000000 M A Com MABA 007159 000000 Rev 0 Page
43. R0402 43 9 R403 R404 R408 R409 R503 Res film SMD 0402 330 Panasonic ERJ 2GEJ330X R504 R508 R509 R741 44 1 R602 Res prec thick 57 60 Panasonic ERJ 3EKF57R6V film chip R0603 1 R710 Res prec thick 4 12 kQ Panasonic ERJ 2RKF4121X film chip R0402 46 1 R711 Res prec thick 5 11 KQ Panasonic ERJ 2RKF5111X film chip R0402 47 8 R714 R716 R725 R730 R738 Res prec thick 200 Q Panasonic ERJ 2RKF2000X R739 R805 R806 film chip R0402 48 2 R726 R740 Res film SMD 0402 100 O Panasonic ERJ 2GEJ101X 49 2 R734 R736 Res prec thick 1300 Panasonic ERJ 2RKF1300X film chip R0402 50 2 R735 R737 Res prec thick 82 5 Q Panasonic ERJ 2RKF82R5X film chip R0402 51 9 RN801 RN802 RN803 RN804 RN805 Res network 8 pin 4 res 220 Q CTS 742C083221JCT RN806 RN807 RN808 RN809 surface mount 52 4 T401 T402 T501 T502 XFMR RF 1 1 MABA 007159 000000 M A Com 6 pin special MABA 007159 000000 53 1 T601 XFMR RF ADT1 1WT Mini Circuits ADT1 1WT 54 3 U101 U104 U105 IC ADI low dropout ADP1708ARDZ R7 Analog Devices Inc CMOS line regulator ADP1708ARDZ R7 55 2 U102 U106 IC ADI low dropout ADP1706ARDZ 3 3 R7 Analog Devices Inc CMOS line regulator ADP1706ARDZ 3 3 R7 56 1 U103 IC ADI low dropout ADP1706ARDZ 1 8 R7 Analog Devices Inc CMOS line regulator ADP1706ARDZ 1 8 R7 Rev 0 Page 31 of 36 Item Qty Reference Designator Description Value Manufacturer Part No 57 1 U201 Generic LFCSP64 9X9 AD9
44. ZT SIR j zino al 5 ino NI D I 68 et 25 22 vita na e s H sain 8 gira 24 E 208 8 130 STE 2219 38 m a E E ana i 6 65 6 19 dano SES alo 546545 oe nG sue SITA E JTA S zano 816 lare nawa re Sk ino wi sie zelo Ew ST zata Naj 3 Le aans ana earn ES 3 85 632 gana 2di E EE Ta ako O sese TES SZ 5 oe S Slo gle lone I Is E T ano 5 8 Lap ETE BE E 3 STE 9 295 T n os ina DS fase E vn a zip 65 v9 SNId Gana aana g SE NIT 358 285515 x u tora Be vi TETT 24 2099801 TANG 8 2 ana TE 97119 m E 2 RH Y SBHOLIU 0938 ATdANns aanw ana G ns ina oe 69 ya SkIA dana E NG E 58 82 3 UN i D STE vue ab ov 087 NE DL SY d 8 RP lu x NIA lt Mises 10113 Wag Tata ldNI A lddris H3MOd Figure 16 Board Power Input and Supply Circuits Rev 0 Page 11 of 36 Figure 17 DUT and Related Circuits 8 A A E ANO awe 8 2 S a S lo x on tn ne k ZZ STE SIS ganga 1 1 ganya sous uovubosu pu 885 NEBOODEE BE 59553 55599Ga8 un Di bi ki ti ti ano ano ES lt m OPO TO TO TO IN NU JO TU o EEN o Wa al ed s
45. a differential signal that is clipped by CR601 before entering the ADC clock inputs The AD9251 evaluation board family is by default set up to be clocked through the transformer coupled input network from the crystal oscillator Y601 This oscillator is a low phase noise oscillator from Valpey Fisher VFAC3 BHL 40MHz VFAC3 BHL 65MHz VFAC3 BHL 80MHz If a different clock source is desired remove J605 to disable the oscillator from running and connect the external clock source to the SMA connector J602 labeled ENCODE The default clock input circuit on the AD9268 family evaluation boards uses a similar circuit to the AD9251 family but uses a higher bandwidth 1 1 impedance ratio balun T602 that adds a very low amount of jitter to the clock path The clock input is again 50 terminated and ac coupled to handle single ended sine wave types of inputs The balun converts the single ended input to a differential signal that is clipped before entering the ADC clock inputs The AD9268 board family is set by default to use an external clock generator An external clock source capable of driving a 50 Q terminated input should be connected to J602 This family is shipped from Valpey Fisher with a low phase noise oscillator installed The oscillator frequency is set to match the rated speed of the part 125 MHz 105 MHz or 80 MHz for the AD9268 family To enable the oscillator install J605 and to connect it into the clock path add a 0 O res
46. adj 10 ka Bourns Inc 3299W 1 103 102 R204 R205 Resistor chip SMD 0402 N A N A 103 R401 R402 R501 R502 R601 Res prec thick 57 60 Panasonic ERJ 3EKF57R6V film chip R0603 104 R406 R506 R719 R720 Res prec thick 49 9 Q Panasonic ERJ 2RKF49R9X film chip R0402 105 R412 Res prec thick 1300 Panasonic ERJ 2RKF1300X film chip R0402 106 R416 Res film SMD 0402 300 Q Panasonic ERJ 2GEJ301X 107 R417 R418 R419 R420 R421 Res prec thick 10 kQ Panasonic ERJ 2RKF1002X film chip R0402 108 R512 R513 Res prec thick 40 2 Q Panasonic ERJ 2RKF40R2X film chip R0402 109 R613 Res film SMD 0402 1000 Panasonic ERJ 2GEJ101X 110 T403 T503 XFMR RF ADT1 1WT Mini Circuits ADT1 1WT 111 T404 XFMR RF TC3 1T Mini Circuits TC3 1T 112 T505 XFMR RF 1 1 MABA 007159 000000 M A COM 6 pin special MABA 007159 000000 113 T601 XFMR RF ADT1 1WT Mini Circuits ADT1 1WT 114 TP101 TP102 TP402 TP601 TP801 Connector PCB Black Components Corp TP802 TST PNT BLK TP 104 01 00 115 TP9 TP401 TP701 TP702 TP703 Connector PCB White Components Corp TP704 TP705 TST PNT WHT TP 104 01 09 116 U702 IC ADI ultrafast SIGe ECL ADCLK905BCPZ WP Analog Devices Inc clock data buffers ADCLK905BCPZ WP 117 CR201 IC ADI 1 2 V micropower AD1580ARTZ Analog Devices Inc prec shunt voltage ref AD1580ARTZ 118 U202 IC ADI single supply AD822BRZ Analog Devices Inc rail to rail low power AD822BRZ FET input op amp Do not install Rev 0 Page 29
47. ation GENERAL DESCRIPTION This document describes the AD9268 AD9258 AD9251 AD9231 and AD9204 evaluation board which provides all of the support circuitry required to operate the AD9268 AD9258 AD9251 AD9231 or AD9204 in their various modes and configurations The application software used to interface with the devices is also described The AD9268 AD9258 AD9251 AD9231 and AD9204 data sheets provide additional information and should be consulted when using the evaluation board All documents and software tools are available at http www analog com fifo For additional information or questions send an email to highspeed converters analog com TYPICAL MEASUREMENT SETUP we M H ra NA NM vi K R x i MK 08168 001 Figure 1 AD9268 and AD9251 Family Evaluation Board and HSC ADC EVALCZ Data Capture Board Please see the last page for an important warning and disclaimers Rev 0 Page 1 of 36 TABLE OF CONTENTS JA Equipment Needed eee sum ee s base Software Needed READER ie Drei Documents Needed aa ANAN General Description Typical Measurement Setup aaa Revision History sse Evaluation Board Hardware EEN Power Supplies eite re tee eis Input Signals AS NE ua Ryu REVISION HISTORY 11 09 Revision 0 Initial Version Output Signals e RR 3 Default Operation and Jumper Selection Settings
48. d fed od S 000000000000000 NUANWUNFNDOAHEDE Er ING AS p p p D S pp e ty GWN zuazesay ous 55 o o Ss ans Ip yaa Eg 940 ATTO ST atta 3 2 ssa pg HE gata Er geta ano ma sn 555590 2 s TIZ ved Den asa Sach eara Er asa 119 Ganda Ganda a20 gr ala 2029 HIIO BTTO a90 TI aod l ganya 00 5 Ka be HETO x CONYO GT vera S2604 6205 es ng w sela rra a Se EVO 8 gra ano semp aie vsta 55 0 892615 aza f aeu 9 guo gr YYO Ged g aza E PEN oi ingrolas EE 520 0105 HIU S ata erg m S v b R me p 840 158 EGO god ka ina aso gg 862 ONAS E T INANI ONAS Cr Zp 830 72 ro 222 Eger Z HDIH OL 1ndino E ap NMdd 4719 vn A NMOq ammod CT a DP PIS So lt lt zz lt lt 2 eer oorzroornm 2 Nad A ganga ao ben 2 BIRR Be Paw Uno INO INO Jnr a 8 28 280 zazI Ina T 222E Z or 3 ZZ 4 S p 51 EH D 2 Ge 2 3H 1x3 e E 8 8 li i r E N ans zazn UNO Ant OT UND ING ING 2 Jogy s MZ ant g 27 Amt o ant N9LHM T Tago T 69 La ui vazo I1NOTWON NE ONO zorana 22 0 4 Sac vac ING ING L1 JON IBNeHd3lcx3 LA NO I LdO g o ga ear msi H 9 KS JJNTIXJ O y 26 25 F set syan CE Ce Tang ina CT rer Rev 0 Page 12 of 36
49. file is selected for the part If VisualAnalog indicates that the FIFO Capture timed out do the following e Make sure all power and USB connections are secure e Probe the DCOA signal at RN801 Pin 2 on the evaluation board and confirm that a clock signal is present at the ADC sampling rate Rev 0 Page 10 of 36 EVALUATION BOARD SCHEMATICS AND ARTWORK 910 89180 alfals fn uo ano ME ME 2 4 TeTdL ano oe ant a anat 5T0 ETO ZHWQOT eg Gre ETIJ oe oe A anta DEM oe ESTO SETO m gt gana 2 a113 A an i oe 201 8 4 anat STO TUIS I 24227 aanza z 1 T113 ano mei anto net 5 2 EETO ZHW T A ano aane 1na 27 atta E mei anta anat 85 2 ZETO 24207 Droe 8 E z 3 eara E mei anto 087 5719 SpTo zuer DE M z 1 stra INANI Aq YAMOd 3 HUIMHU A
50. h the jumper removed the data format is set to offset binary To set the data format to twos complement a jumper should be added on J302 between Pin 5 and Pin 6 Switching Power Supply Optionally the ADC on the board can be configured to use the ADP2114 dual switching power supply to provide power to the DRVDD and AVDD rails of the ADC To configure the board to operate from the ADP2114 the following changes must be incorporated see the Evaluation Board Schematics and Artwork and Bill of Materials sections for specific recommendations for part values Install R120 and R122 to enable the ADP2114 Install R107 and R109 Install R110 R111 C108 and C109 Install R108 R118 C110 C111 C112 and C113 Install L101 L102 E116 and E117 Install R125 and R127 Remove JP101 and JP103 and install JP102 and JP104 Remove E103 E105 and E107 and install E104 E106 and E108 Qo pu 71 E Making these changes enables the switching converter to power the ADC Using the switching converter as the ADC power source is more efficient than using the default LDOs Rev 0 Page 6 of 36 EVALUATION BOARD SOFTWARE QUICK START PROCEDURES This section provides quick start procedures for using the AD9268 AD9258 AD9251 AD9231 and AD9204 evaluation board Both the default and optional settings are described CONFIGURING THE BOARD VisualAnalog New Canvas New Existing Recent Categories Templates
51. ion See the data sheet of the part for additional information on using the programmable reference mode A separate unpopulated external reference option using the AD1580 reference and the AD822 amplifier is also included on the evaluation board To enable the external reference populate CR201 U202 R202 R201 C201 and C202 with the values shown in the Evaluation Board Schematics and Artwork section and Bill of Materials section The J201 jumper should be placed between Pin 4 and Pin 2 to set the reference input to the external reference mode RBIAS RBIAS has a default setting of 10 kO R206 to ground and is used to set the ADC core bias current Note that using a resistor value other than a 10 kO 196 resistor for RBIAS may degrade the performance of the device FERRITE AD9268 AD9258 FERRITE 08168 031 Figure 3 Default Analog Input Configuration of the AD9268 Family 0 1pF 0 1pF AD9251 AD9231 AD9204 08168 032 Figure 4 Default Analog Input Configuration of the AD925 Family Rev 0 Page 5 of 36 Clock Circuitry The default clock input circuit on the AD9251 evaluation board family uses a simple transformer coupled circuit using a high bandwidth 1 1 impedance ratio transformer T601 that adds a very low amount of jitter to the clock path The clock input is 50 Q terminated and ac coupled to handle single ended sine wave types of inputs The transformer converts the single ended input to
52. istor at C610 R602 should also be removed to remove the 50 termination from the output of the oscillator A differential LVPECL clock driver output can also be used to clock the ADC input using the AD9517 U701 To place the AD9517 into the clock path populate R607 and R608 with 0 Q resistors and remove R609 and R610 to disconnect the default clock path inputs In addition populate R731 and R732 with 0 O resistors and remove R611 and R612 to disconnect the default clock path outputs and insert the AD9517 LVPECL Output 3 The AD9517 must be configured through the SPI controller software to set up the PLL and other operation modes Consult the AD9517 data sheet for more information about these and other options PDWN To enable the power down feature add a shorting jumper across J205 at Pin 1 and Pin 2 to connect the PDWN pin to DRVDD OE To disable the outputs using the OE pin add a shorting jumper across J205 at Pin 3 and Pin 4 to connect the OE pin to DRVDD Non SPI Mode For users who want to operate the DUT without using SPI remove the shorting jumpers on J302 This disconnects the CS SCLK DES and SDIO DCS pins from the SPI control bus allowing the DUT to operate in non SPI mode In this mode the SCLK DFS and SDIO DCS pins take on their alternate functions to select the data format and enable disable the DCS With the jumpers removed DCS is disabled to enable DCS add a shorting jumper on J302 between Pin 2 to Pin 3 Wit
53. le ema PHASEDR T Cb Dod f es Prae Dein ges 48 g a lt zess 6 zi 08168 011 Figure 11 SPI Controller CLOCK DIVIDE B Box Rev 0 Page 8 of 36 Si SPiCentroller 1 0 45 3 USB Ezsnb 0 CS 1 AD9268_169 r_125WSspRR03 ot AD9268 16 125MSapiDI cal Ces Note that other settings can be changed on the ADCBase 0 page see Figure 11 and the ADC A and ADC B pages see Figure 12 to set up the part in the desired mode The ADCBase 0 page settings affect the entire part whereas the settings on the ADC A and ADC B pages affect the selected channel only See the appropriate part data sheet the AN 878 Application Note High Speed ADC SPI Control Software and the AN 877 Application Note Interfacing to High Speed ADCS via SPI for additional information on the available settings Adjusting the Amplitude of the Input Signal The next step is to adjust the amplitude of the input signal for each channel as follows l Adjustthe amplitude of the input signal so that the fundamental is at the desired level Examine the Fund Power reading in the left panel of the VisualAnalog Graph AD9268 Average FFT window See Figure 14 gt Graph AD9268 Average FFT 6 15 2009 1 49 25 PM Fle m Js ele ele ES EHRE S 5M 12M 18M 24M 30M 36M 42M 48M 54M GOM 1 49 25 PM Sa
54. mple Frequency 125 MHz Samples 16354 SNR 77 246 8 Tie Gei p sig ci m e Cat Acten ACCA soc DOWN MODE S TEST OW Mr Et Pra Dn Pe Fa Quo Test Mode Map 158 He Free L nos E Feefotegge Paanan F fentit DITAER ENDA noma ll icc Dapa weit Sunde Dua Fo Is 48127 Deeg Enable Bar Ll 08168 012 Figure 12 SPI Controller Example ADC A Page Click the Run button in the VisualAnalog toolbar see Figure 13 gt VisualAnalog Canvas AD9268 FFT 08168 013 Figure 13 Run Button Encircled in Red in VisualAnalog Toolbar Collapsed Display 2 3 SNRFS 7825 8 SINAD 76 981 Bc DC Power 54 538 665 Ham 3 Power 97 384 Bc 4 Power 10045 dBc Ham 5 Power 112 726 Bc Ham 6 Power 113353 Bc Worst Other Frequency 54 817 MHz Worst Other Power 37 5935 BFS Noise Hz 156 209 dBFS Hz Average Bin Nose 117 384 dBFS THO 89 256 Bc SFOR 90432 Bc 08168 014 Rev 0 Page 9 of 36 Figure 14 Graph Window of VisualAnalog Repeat this procedure for Channel B Click the disk icon within the Graph window to save the performance plot data as a csv formatted file See Figure 15 for an example 125MSPS 70 1MHz 1dBFS SNR 76 5dB 77 5dBFS SFDR 88 0dBc THIRD HARMONIC SECOND HARMONIC AMPLITUDE dBFS 08168 015 FREQUENCY
55. nd series of parts supported by this evaluation board and are referred to as the AD9251 family See the Evaluation Board Software Quick Start Procedures section to get started and see Figure 16 to Figure 30 for the complete schematics and layout diagrams These diagrams demonstrate the routing and grounding techniques that should be applied at the system level when designing application boards using these converters POWER SUPPLIES This evaluation board comes with a wall mountable switching power supply that provides a 6 V 2 A maximum output Connect the supply to the rated 100 V ac to the 240 V ac wall outlet at 47 Hz to 63 Hz The output from the supply is provided through a 2 1 mm inner diameter jack that connects to the printed circuit board PCB at P101 The 6 V supply is fused and conditioned on the PCB before connecting to thelow dropout linear regulators default configuration that supply the proper bias to each of the various sections on the board The evaluation board can be powered in a nondefault condition using external bench power supplies To do this the E101 E102 E114 E103 E105 and E107 ferrite beads can be removed to disconnect the outputs from the on board LDOs This enables the user to bias each section of the board individually Use P102 and P103 to connect a different supply for each section A 1 8 V supply is needed with a 1 A current capability for DUT AVDD and DRV DD however it is recommended that separate
56. of 36 Table 2 AD9251 Family BOM Item Qty Reference Designator Description Value Manufacturer Part No 1 1 Not applicable PCBZ 2 9 C101 C132 C133 C134 C135 C136 Capacitor ceramic NPO 10 uF Panasonic ECJ 2FB0J106M C145 C419 C514 3 12 C102 C103 C104 C106 C124 C126 Capacitor 0603 X5R 4 7 uF Panasonic ECJ 1VB0J475M C127 C128 C129 C130 C144 C146 4 7 C105 C117 C119 C121 C123 Capacitor ceramic 10 000 pF Panasonic ECJ OEB1E103K C125 C143 multilayer X7R 0402 5 68 C116 C118 C120 C122 C149 C150 Capacitor ceramic 0402 0 1 uF Panasonic ECJ 0EX1C104K C151 C152 C153 C154 C204 C206 C207 C208 C209 C211 C301 C302 C403 C404 C405 C406 C407 C417 C418 C420 C426 C503 C504 C505 C506 C507 C515 C516 C523 C602 C603 C606 C607 C609 C610 C701 C702 C710 C711 C712 C713 C714 C715 C716 C717 C718 C719 C720 C721 C723 C724 C730 C731 C801 C802 C803 C804 C805 C806 C807 C808 C809 6 6 C138 C139 C141 C142 C147 C148 Capacitor ceramic chip 22 uF Murata GRM21BR60J226ME39L 7 3 C107 C203 C205 Capacitor ceramic 1 uF Panasonic ECJ 0EF0J105Z 8 28 C401 C402 C502 C604 JP403 R203 Res film SMD 0402 00 Panasonic ERJ 2GEOROOK R301 R302 R303 R304 R424 R425 R524 R525 R526 R606 R609 R610 R611 R612 R708 R715 R723 R727 R728 R729 R803 R804 9 2 C410 C510 Capacitor ceramic NPO 22 pF Panasonic ECU E1H220J 10 1 C705 Capacitor ceramic 1800 pF Panasonic E
57. or sm 2 2 uH TOKO FDV0630 2R2M Rev 0 Page 28 of 36 Item Qty Reference Designator Description Value Manufacturer Part No 85 L401 L502 Res film SMD 0603 00 Panasonic ERJ 3GEYOR00V 86 L405 L505 Inductor SM 100 nH Coilcraft 0603CS R10XGLU 87 L406 L407 Inductor SM 1 uH Coilcraft 0603LS 102XGLB 88 L408 L409 L410 L411 Inductor SM 270 nH Coilcraft 0603CS R27XGLW 89 L508 L509 Chip inductor 15 nH Coilcraft 0603CS 15NXGLU 90 L510 L520 Chip inductor 36 nH Coilcraft 0603CS 36NXGLU 91 L521 L522 Inductor SM 82 nH Coilcraft 0603CS 82NXGLU 92 R107 Resistor chip SMD 0402 27 kQ Panasonic ERJ 2RKF2702X 93 R108 Res prec thick film 10 5 KQ Panasonic ERJ 2RKF 1052X chip 80402 94 R109 Resistor chip SMD 0402 475 kQ Panasonic ERJ 2RKF4751X 95 R110 R111 Resistor chip SMD 0402 15 kQ Panasonic ERJ 2RKF 1502X 96 R116 R117 Resistor chip SMD 0603 N A N A 97 R118 Res film SMD 0402 13 kO Yageo Corp 9C04021A1302FLHF3 98 C501 JP401 JP402 JP501 JP502 R120 Res film SMD 0402 0Q Panasonic ERJ 2GEOROOX R122 R124 R125 R126 R127 R305 R306 R307 R308 R405 R407 R410 R411 R413 R414 R415 R423 R505 R507 R510 R511 R514 R515 R516 R517 R519 R520 R521 R603 R604 R605 R607 R608 R721 R722 R731 R732 99 R518 Res prec thick 1 00 kO Panasonic ERJ 2RKF1001X film chip R0402 100 R201 Res prec thick 2ko Panasonic ERJ 2RKF2001X film chip R0402 101 R202 Res VAR 3 8 SQ top
58. r loss of functionality Rev 0 Page 34 of 36 NOTES Rev 0 Page 35 of 36 NOTES Evaluation boards are only intended for device evaluation and not for production purposes Evaluation boards are supplied as is and without warranties of any kind express implied or statutory including but not limited to any implied warranty of merchantability or fitness for a particular purpose No license is granted by implication or otherwise under any patents or other intellectual property by application or use of evaluation boards Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Analog Devices reserves the right to change devices or specifications at any time without notice Trademarks and registered trademarks are the property of their respective owners Evaluation boards are not authorized to be used in life support devices or systems 2009 Analog Devices Inc All rights reserved Trademarks and ANALOQ registered trademarks are the property of their respective owners UG08168 0 11 09 0 DEVICES www analog com Rev 0 Page 36 of 36
59. requency Analog Devices uses TTE Allen Avionics and K amp L band pass filters USING THE SOFTWARE FOR TESTING Setting Up the ADC Data Capture After configuring the board set up the ADC data capture using the following steps 1 Open VisualAnalog on the connected PC The appropriate part type should be listed in the status bar of the VisualAnalog New Canvas window Select the template that corresponds to the type of testing to be performed see Figure 5 where the AD9268 is shown as an example CI 09282 CI 09287 ADS268 CJ 09289 C3 09800 CI AD9627 CJ ADS627 11 C3 09840 J Quad CH Octal 3 Mat CI Other Check for Updates AD 9268 16 Bit 80 105 125 MSPS Dual device found p lal BS Logic EJ 8 a 9 a 5 lt Open Cancel 08168 005 Figure 5 VisualAnalog New Canvas Window After the template is selected a message appears asking if the default configuration can be used to program the FPGA see Figure 6 Click Yes and the window closes VisualAnalog i VisualAnalog will now attempt to program the on board FPGA with a default file for the AD9268 Please click Yes to program the FPGA If you prefer to use the current FPGA configuration click No Before clicking Yes please make sure the HSC ADC EVALC is powered with the correct supply and that the board is connected to the computer Also make sure the dipswitch 14 on the HSC ADC EVALC
60. rt When connecting the analog input source use of a multipole narrow band band pass filter with 50 O terminations is recommended Analog Devices Inc uses TTE and K amp L Microwave Inc band pass filters The filters should be connected directly to the evaluation board If an external clock source is used it should also be supplied with a clean signal generator as previously specified Typically most Analog Devices evaluation boards can accept 2 8 V p p or 13 dBm sine wave input for the clock OUTPUT SIGNALS The default setup uses the Analog Devices high speed converter evaluation platform HSC ADC EVALCZ for data capture The CMOS output signals from Channel A and Channel B are buffered through U801 and U802 and are routed through P903 and P902 respectively to the FPGA on the data capture board Rev 0 Page 3 of 36 WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz SWITCHING POWER SUPPLY SWITCHING POWER SUPPLY SIGNAL GENERATOR ANALOG FILTER KENT d PC RUNNING e VISUALANALOG ity AND SPI CONTROLLER USER SOFTWARE tad CLOCK SOURCE 08168 002 Figure 2 Evaluation Board Connection Rev 0 Page 4 of 36 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS This section explains the default and optional settings or modes allowed on the AD9268 AD9258 AD9251 AD9231 AD9204 Rev C evaluation board Power Circuitry Connect the switching power
61. supply that is supplied in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P101 Analog Input The A and B channel inputs on the evaluation board are set up for a double balun coupled analog input with a 50 Q impedance For the AD9268 family the default analog input configuration supports analog input frequencies of up to 250 MHz see Figure 3 This input network is optimized to support a wide frequency band See the AD9258 and A D9268 data sheets for additional information on the recommended networks for different input frequency ranges For the AD9251 family the default analog input configuration supports analog input frequencies of up to 150 MHz see Figure 4 The nominal input drive level is 10 dBm to achieve 2 V p p full scale into 50 Q At higher input frequencies slightly higher input drive levels are required due to losses in the front end network Optionally the Channel A input on the board can be configured to use the AD8375 digitally variable gain amplifier DVGA The AD8375 component is included on the evaluation board at U401 However the path into and out of the AD8375 can be configured in many different ways depending on the application therefore the parts in the input and output path are left unpopulated Users should see the AD8375 data sheet for additional information on this part and for configuring the inputs and outputs The AD8375 by default is held in power down mode but
62. vrd o gg 8516 T a ra o gg siro 6T Laun 335 ees aero 37 INT az H amp 1 0 5T eege A vaeni ST Lan 33S Tip Jah 235 851 Wg ara 896 er vci gM vad v gNy asaro TOSNH Jon 335 ara o or ari 2 NV aza aero g dee Sg VOSNH 82 0 I EC E ws ata o S did GET ENG vg HSI 8 T gea aoro g SE DER E ssr VE vza zl 5 6 1MUHO 335 OW zasn NINE 1ugH2 335 gol ey aba Sw vot Wz ven 6028 7 328n3 48 4 335 OWN e e e gana 4 335 HAI g asa V 7 vui SV era 6 8 aT anta L anto Lana Lanta NH eee oe 8282 2085 9283 5085 gar 7 Vg aoa d 1HBHO 335 OH 1H8H2 33S hn ee vsa u i ala 6 DENIS 1HUHO 335 vor 9 WE esa SAILING INdiNO Com Lou 336 Jm 335 aano Vy aod mw 5 sarr 2 Vg oun EE POENG 1HUHD 336 Io 335 uri Bg vat BH aoe ved ene dd 456 413 335 92 zw aora SOSNSH NE SE 458 43 335 I ws XOLWLZSZSTXING 2 19286 E S e 950 GETI CSR ana LENY S ENG 1HUHO 335 erre wrr gE yata dedu n LSNA IE LINOdID lo OW a T 141 gt i ag SR 456843 336 vioo 6 ustao gg 1 335 ash 3 E GETO AS pg serr g vera Sagana P 4 43 336 WE setao Eg wena 5 9 2 STI DNS aria il MISZBG XI NS X9AITZMZIN 6 gal Loo 335 oun 2 49 But z mews Jo 336 m HTC O STI 9 v BETO Sen sasa 7 to o
Download Pdf Manuals
Related Search
Related Contents
Nova Double Fryer User`s Manual User Guide Introduction to Computer Data Acquisition Dell™ 2007FP Flachbildschirm VGN-Z series - Sony Europe Guía del Usuario e-STUDIO170F Service Manual Copyright © All rights reserved.
Failed to retrieve file