UM10751 OM13488 8-bit GPIO Daughter Card User Manual
Contents
1. FELD edf T Zdf e os daan ROUND3 2 ADDR A1 HOUNT PRD ROUND3 2 H2 MOUNT PAD H1 Fm BOARD UM10751 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 1 0 11 October 2013 12 of 16 NXP Semiconductors UM10751 6 Legal information 6 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 6 2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on to2. 9 Table 3 CN2 Fm Board 10 Table 4 CNA Tester 10 UM10751 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 1 0 11 October 2013 15 of 16 NXP Semiconductors UM10751 9 Contents OM13488 8 bit GPIO User Manual 3 1 3 2 4 1 4 2 4 3 4 4 4 5 5 1 5 2 5 3 6 1 6 2 Introduction 3 Features of the OM13488 8 bit GPIO Daughter Cardi tk annona ada RAES 4 Pin Configuration of 8 bit GPIO Devices 4 Power Supply 56 5 Reset Interrupt and Address pins selection 5 Board 6 Power Supply 5 6 PCA8574 PCA8574A PCA9534 PCA9554A PCA9554B PCA9554C PCA9554 PCA9674A PCA9674 PCAL9554B PCAL9554C PCF8574 PGF8574A deii et prede d C eins 6 PGCA9070 toii eut EO RE 7 PCA9672 PCAL9538A PCA9538A PCA9538 7 PCAL6408A 8 Connector Pinout esses 9 CN1 Target Board Connector 9 CN2 Fm Development Board Connector 9 CN4 Tester Connector ssssusss 10 Legal inform
3. domain to a higher or lower I O voltage JP2 and JP4 may be set to the same or different voltages or left open and external voltage sources connected to TP1 and TP2 Unfortunately there is a slight labeling issue on this board Device pin 1 is the VDDI power supply and is permanently connected to JP2 which selects between VDDP and ground Use a wire to jumper between pin 2 of JP1 to pin 3 of JP10 which is the board VDDI See the datasheet for more details on voltage level translation Note that the 10K pull up resistors SDA and SCL R5 and R6 are connected to VDDP which may cause incorrect current readings if two different supplies are used To configure the function pins apply jumpers between pins 2 amp 3 on JP9 and JP11 to configure device pin 3 as RST and device pin 13 as INT There is a slight labeling issue on this board Device pin 2 is the only address pin and JP10 should jumper pins 1 and 2 to route the address to JP7 A1 instead of AO Then apply a jumper to JP7 to configure the desired address Logic high or logic low are labeled on the board Leave JP8 open All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 1 0 11 October 2013 8 of 16 NXP Semiconductors UM10751 OM13488 8 bit GPIO User Manual TESTER GNO 135 7 FM 0 6ND O o6 noooo L 4 died oo unpnmea 244 oo hd 10
4. eo Ground Board Connection U1 pin 14 U1 pin 15 JP3 pin 3 JP3 pin 3 JP3 pin 3 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 1 0 11 October 2013 10 of 16 jenuew 95 L0c 19003120 LL O L e sjeurejosip jeBej 1oe qns si 3ueuinoop siu ui PapiAosd uoneuuojul y 9L JO LL LSZOLWN 9 syu Iv EL0Z dXN PKG VARIABLES FOR PINS 1 2 3 Jpg 1 7 8 2 PINL3 JPg 3 JP10 1 s 81 JP18 2 elt 1 10 3 JPA1 4 B2 1 11 2 PIN 1 11 3 gee BESET vPIN3 YY PAN 8 bit Tlemplate c1 180 Template for GPIO package NXP SEMICONDUCTORS TITLE GPIO 8bit sept 5 Document Number Q M 41 3 4 8 8 Date 10 1 2013 1 06 06 PM Sheet 1 2 jenuel 49SN Old9 13 d 8 88v LINO LSZOLINN SJOJONPUODIWIAS dXN NXP Semiconductors U M1 0751 OM13488 8 bit GPIO User Manual Ed daa AS aaan gS T Edf Q3t5 DtI9ST2 1811 lz 86 PM z EL Ans LIIS EIC EE rl ne aaan NH9215193085T2 15S1 1 06 GPIO 8bit sept 5 NXP SEMICONDUCTORS Date 10 1 2013 1 TITLE Tdf 2 Tdf T Tdf I2C TESTER ssa ons 8d g T 8df Soe N T a a a
5. information provided in this document is subject to legal disclaimers OM13488 8 bit GPIO User Manual Evaluation products This product is provided on an as is and with all faults basis for evaluation purposes only NXP Semiconductors its affiliates and their suppliers expressly disclaim all warranties whether express implied or statutory including but not limited to the implied warranties of non infringement merchantability and fitness for a particular purpose The entire risk as to the quality or arising out of the use or performance of this product remains with customer In no event shall NXP Semiconductors its affiliates or their suppliers be liable to customer for any special indirect consequential punitive or incidental damages including without limitation damages for loss of business business interruption loss of use loss of data or information and the like arising out the use of or inability to use the product whether or not based on tort including negligence strict liability breach of contract breach of warranty or any other theory even if advised of the possibility of such damages Notwithstanding any damages that customer might incur for any reason whatsoever including without limitation all damages referenced above and all direct or general damages the entire liability of NXP Semiconductors its affiliates and their suppliers and customer s exclusive remedy for all of the foregoing shall be
6. limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars US 5 00 The foregoing limitations exclusions and disclaimers shall apply to the maximum extent permitted by applicable law even if any remedy fails of its essential purpose NXP B V 2013 All rights reserved User manual Rev 1 0 11 October 2013 13 of 16 NXP Semiconductors U M1 0751 OM13488 8 bit GPIO User Manual 7 List of figures Fig 1 Pin Configuration 8 bit GPIO Devices 5 Fig 2 Power Jumpers and External Power Test Points6 Fig 3 Jumper configuration for PCA8574 PCA8574A PCA9534 PCA9554A PCA9554B PCA9554C PCA9554 PCA9674A PCA9674 PCAL9554B PCAL9554C PCF8574 PCF8574A 7 Fig 4 Jumper Configuration for PCA9670 7 Fig 5 Jumper Configuration for PCA9672 PCAL9538A PCA9538A PCA9538 sse 8 Fig 6 Jumper Configuration for PCA L 64068 9 UM10751 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 1 0 11 October 2013 14 of 16 NXP Semiconductors U M1 0751 OM 13488 8 bit User Manual 8 List of tables Table 1 Devices Supported by OM13488 8 bit lC Daughter Card ec renvoie 3 Table 2 Target Board Connector Pinout
7. pin 3 as addresses Apply a jumper between pins 2 amp 3 on JP9 to configure device pin 13 as INT Then apply jumpers to JP1 JP7 and JP8 to configure the desired lC address Logic high or logic low is labeled on the board All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 1 0 11 October 2013 6 of 16 NXP Semiconductors U M1 0751 OM13488 8 bit GPIO User Manual O GND O Unonea 7 44 qp eda oo 8 bit GPIO E Ori 3485 nev ia E Fig 3 Jumper configuration for PCA8574 PCA8574A PCA9534 PCA9554A PCA9554B PCA9554C PCA9554 PCA9674A PCA9674 PCAL9554B PCAL9554C PCF8574 PCF8574A 4 3 PCA9670 The PCA9670 implements three address pins and RST This configuration ignores the power supply setup but normally only JP4 with a jumper between pins 2 amp 3 need be applied to power the device at 3 3V To configure the function pins apply jumpers between pins 1 amp 2 on JP9 JP10 and JP11 to configure pin 2 and pin 3 as addresses and pin 13 as RST Then apply jumpers to JP1 JP7 and JP8 to configure the desired lC address Logic high or logic low is labeled on the board UDDR a 2 46 oo eraa oo 8 Sar GPIO T Pia eats ae p m a 328 Fig 4 Jumper Configuration for PCA9670 4 4 PCA9672 PCAL9538A PCA9538A PCA9538 The PCA9672 and PC
8. 3303 Target board for I O visualization Jumper configuration of device lC address LED indicators for power and INT E Scope ground connection loop 3 Pin Configuration of 8 bit GPIO Devices The different 8 bit GPIO devices pin configurations differ only slightly between devices See Fig 1 for a description of the different pinouts UM10751 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 1 0 11 October 2013 4 of 16 NXP Semiconductors UM10751 OM13488 8 bit GPIO User Manual PCA L 9554B amp C PCA8574 74A PCA9674 74A PCF8574 74A PCA9670 vem RESET m o v 5 5 w N e lt n n Fig 1 Pin Configuration 8 bit GPIO Devices PCA L 9554B amp C PCA L 9538 PCA9672 PCA L 6408 PCA L 6408 PCA L 9538 PCA9672 PCA8574 PCA9674 PCF8574 PCA9670 z 5 UU is 6 J RI gt RESET o v 5 A 3 1 UM10751 Power Supply Setup Power supply voltages may be selected from the tester connector CN4 or the Fm board CN2 If one selects Fm CN2 either 3 3V or 5V can be chosen Additionally the PCA L 6408 device implements two power supplies which are separately chosen i e one can be 3 3V and the other 5V for voltage level translation evaluation Both of these power supplies can be supplied externally by using TP1 and TP2 near the tester connector CN4 See the sc
9. 48 00 oo aie g bit EVE 99 oo e 4 oo on lz a RD 0M134 3 ng 1 9 TSTR sada OO y a o IN yoo RST So S o on 4110 a2 0 PIN PIN2 PINAR Bo zo ao Qo oo iloj iid AST AL 2 ing Fig 6 Jumper Configuration for PCA L 6408 5 Connector Pinouts 5 1 CN1 GPIO Target Board Connector UM10751 5 2 The OM13303 GPIO Target Board consists of eight LEDs and eight switches and connects directly to the 8 bit GPIO board through CN1 The switches and LEDs permit easy exercise of the I O functionality of the device under test The LEDs light red when the voltage on that channel is below VCC x 0 3V and lights green when the voltage is above VCC x 0 7V The LEDs remain off when the voltage is between those two levels Table 2 Target Board Connector Pinout CN1 Pin Number Function Board Connection 1 VDD VDDP 2 Ground GND 3 100 U1 pin 4 4 101 U1 pin 5 5 102 U1 pin 6 6 103 U1 pin 7 7 104 U1 pin 9 8 105 U1 pin 10 9 106 U1 pin 11 10 107 U1 pin 12 CN2 Fm Development Board Connector The OM13488 can connect directly to the OM13320 Fm Development kit via CN2 This connector provides power signals and other ancillary signals Note The connector on the Fm board is a male shrouded 14 pin type while the connector on the GPIO board is female 18 pin The reason lies with the shroud around the 14 pin connector To ensure correct mating of the female with the m
10. A9538 series implement two address pins RST and INT This configuration ignores the power supply setup but normally only JP4 with a jumper between pins 2 amp 3 need be applied to power the device at 3 3V UM10751 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 1 0 11 October 2013 7 of 16 NXP Semiconductors U M1 0751 UM10751 OM 13488 8 bit User Manual To configure the function pins apply jumpers between pins 2 amp 3 on JP9 and JP11 to configure device pin 3 as RST and pin 13 as INT Apply a jumper between pins 1 amp 2 on JP10 to configure device pin 2 as an address Then apply jumpers to JP1 and JP7 to configure the desired lC address Logic high or logic low are labeled on the board Leave JP8 open TESTER GNO 13527 noooo e 2 ad 5 un onpea 2 4 amp ee o9 w eiaa 5 99 oo 8 bit GPIO oe 4 09 oo oon 22 BRD OM 3488 acy 1 a woe 45 unn 9 S9 on 2 PINAB So Xo So 99 11 AL A2ig Fig 5 Jumper Configuration for PCA9672 PCAL9538A PCA9538A PCA9538 4 5 PCAL6408A PCA6408A The PCA L 6408A devices are level translating Agile 1 0 Expanders with two power supplies one address pin RST and INT The two power supplies may operate at different voltages to translate from the l C bus voltage
11. UM10751 OM13488 8 bit GPIO Daughter Card User Manual Rev 1 0 11 October 2013 User manual Document information Info Content Keywords Fm Development Kit OM13320 GPIO OM13303 Abstract Installation guide and User Manual for the OM13488 8 bit GPIO Daughter Card that connects to OM13320 Fm Development Kit This board permits easy and simple evaluation of most of NXP s 8 bit IC portfolio of products NXP Semiconductors U M1 0751 OM13488 8 bit GPIO User Manual Revision history Rev Date Description 1 0 20131011 Initial Release Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com UM10751 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 1 0 11 October 2013 2 of 16 NXP Semiconductors UM10751 1 Introduction OM13488 8 bit GPIO User Manual UM10751 The OM13488 8 bit IC Daughter Card connects to the OM13320 Fm Development kit and permits easy evaluation of most of NXP s 8 bit GPIO portfolio of products Table 1 lists the supported devices The OM13488 8 bit C Daughter Card is shipped with no GPIO device soldered to the board The user must purchase the device he is interested in evaluating in a TSSOP16 package the ordering part number suffix should be PW and the package de
12. ale two pin positions on both of the female sides are unused All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 1 0 11 October 2013 9 of 16 NXP Semiconductors UM10751 UM10751 OM13488 8 bit GPIO User Manual Board Connection No connect No connect SCL Bus 1 to U1 pin 14 SDA Bus 2 not used Interrupt to INT LED and JP9 pin 3 JP9 pin 1 JP11 pin 3 JP3 pin 1 JP2 pin 3 and JP4 pin 3 JP2 pin 3 and JP4 pin 3 JP3 pin 1 JP9 pin 1 JP11 pin 3 Interrupt to INT LED and JP9 pin 3 SDA Bus 1 to U1 pin 15 SCL Bus 2 not used No connect Table 3 2 Fm Board Connector CN2 Pin Number Function 1 2 3 SCL 4 SDA2 5 INT 6 RESET 7 5V 8 3 3V 9 GND 10 GND 11 3 3V 12 5V 13 RESET 14 INT 15 SDA 16 SCL2 17 18 No connect 5 3 CN4 Tester Connector Generation inspection and logging of l C Bus data is easily achieved with third party development tools from Total Phase www totalphase com There are two tools called Aardvark and Beagle that direct connect to this board through CN4 Note Since SDA and SCL are both connected to the device under test the Aardvark and the Fm Development board cannot be used simultaneously The Beagle a bus sniffer does not have any issues Table 4 CN4 Tester Connector CN4 Pin Number Function SCL Ground SDA 5V 5V 5V OMAN 0 gt
13. ation eene 13 19 19 List of figures eene 14 List of tables erret nne 15 Contents sissies 16 Please be aware that important notices concerning this document and the product s described herein have been included in the section Legal information NXP B V 2013 All rights reserved For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 11 October 2013 Document identifier UM10751
14. en 5V and 3 3V for a second power supply needed for PCA L 6408A If the device under test is not PCA L 6408A leave this jumper open JP4 selects between 5V and 3 3V for the main power supply on pin 16 of the device under test Add a jumper between pins 2 amp 3 for 3 3V or 1 amp 2 for 5V For external power supply operation do not jumper JP2 JP3 and JP4 and connect a voltage source to TP2 for the main power supply connected to pin 16 of the device under test Connect another external voltage source to TP1 if the device under test is PCA L 6408A See the schematic section at the end of this document for more details TESTER quias 4 a O GND O noooo o e NM unpnea 2 4 amp Sol Weide gJ S bit GPIO oor 53 BRD OM13488 acu 1 a alol unnt o RSTO El amp ilo a20RIN130O PIN2 O PIN3 o o iio ig RmRSTIB file 2 1 Fig 2 Power Jumpers and External Power Test Points PCA8574 PCA8574A PCA9534 PCA9554A PCA9554B PCA9554C PCA9554 PCA9674A PCA9674 PCAL9554B PCAL9554C PCF8574 PCF8574A The PCA8557 A PCA9534 PCA L 5554x PCA9674 A implement three address pins and INT This configuration ignores the power supply setup but normally only JP4 with a jumper between pins 2 amp 3 need be applied to power the device at 3 3V To configure the function pins apply jumpers between pins 1 amp 2 on JP10 and JP11 to configure device pin 2 and
15. hematic section at the end of this document for more details The jumpers for power supply selection are JP2 JP3 and JP4 Reset Interrupt and Address pins selection The Reset Interrupt and Address pins are used in combinations on various devices The selection matrix on the 8 bit GPIO board sends pins 2 3 and 13 to determine if the pins are address or function on JP9 JP10 and JP11 Then if they are determined address pins JP1 JP7 and JP8 tie them to logic high or low If they are determined to be function pins the other position of JP9 JP10 and JP11 tie them to the correct connector function pins See the schematic section at the end of this document for more details The logic high level for the address pins is VDDP All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 1 0 11 October 2013 5 of 16 NXP Semiconductors U M1 0751 OM13488 8 bit GPIO User Manual 4 Board Jumper Set Up UM10751 4 1 4 2 Power Supply Jumpers The power supply selections for the OM13488 is very flexible and allows for detailed analysis and evaluation of all the NXP 8 bit GPIO devices JP3 labeled PWR selects between 5V supplied from the tester connector CN4 jumper between pin 2 and 3 labeled TSTR and the Fm board connector CN2 jumper between pin 1 and 2 If 3 3V or external power operation is desired no jumper is required JP2 selects betwe
16. ll be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities UM10751 All
17. rt including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications wi
18. signation should be SOT403 1 These leaded packages should be relatively easy to solder to the board with a low wattage fine tipped soldering iron Table 1 Devices Supported by OM13488 8 bit lC GPIO Daughter Card Device Description Orderable Part Number Low voltage 8 bit I C bus and SMBus I O PCA6408A expander with interrupt output reset and PCA6408APW configuration registers 2r PCA8574A Remote 8 bit I O expander for I C bus with PCA8574APW interrupt D P f PCA8574 Remote 8 bit I O expander for I C bus with PCA8574PW interrupt 4 12 PCA9534 8 bit C bus and SMBus low power I O port PCA9534PW with interrupt ae ae PCASS38A Low voltage 8 bit I C bus I O port with PCASS38APW interrupt and reset bit I2C PCA9538 8 bit C bus and SMBus low power I O port PCA9538PW with interrupt and reset hie Br PCA9554A 8 bit 1 C bus and SMBus I O port with PCA9554APW interrupt a bit I2C PCA9554B Low voltage 8 bit C bus and SMBus low PCA9554BPW power I O port with interrupt weak pull up bit I2C PCA9554C Low voltage 8 bit C bus and SMBus low PCAQSSACPW power I O port with interrupt weak pull up Pacuv PCAO554 8 bit 1 C bus and SMBus I O port with PCAOSS4PW interrupt bi 20 PCA9670 Remote 8 bit I O expander for Fm I C bus PCA9670PW with reset bi 20 PCA9672 Remote 8 bit I O expander for Fm I C bus PCA9672PW with interrupt and reset bi 2C PCA9674A Remote 8 bit I O expander for Fm I C bus PCA9674APW with interrup
19. t bi 20 PCA9674 Remote 8 bit I O expander for Fm I C bus PCA9674PW with interrupt E i bit I2C PCALGA08A Low voltage translating 8 bit I C bus SMBus PCALGA0BAPW expander with interrupt output reset All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 1 0 11 October 2013 3 of 16 NXP Semiconductors U M1 0751 OM 13488 8 bit User Manual Device Description Orderable Part Number and configuration registers Low voltage 8 bit I C bus and SMBus low PCAL9538A power I O port with interrupt reset and PCAL9538APW Agile I O Low voltage 8 bit I C bus SMBus low power PCAL9554B I O port with interrupt weak pull up and PCAL9554BPW Agile I O Low voltage 8 bit I C bus SMBus low power PCAL9554C I O port with interrupt weak pull up and PCAL9554CPW Agile I O PCF8574 Remate 8 bit I O expander for lC bus with PCF8574PW interrupt PCF8574A Remote 8 bit I O expander for l C bus with PCF8574APW interrupt The pin configuration of these devices varies only a bit and the different pin selections are made via jumpers 2 Features of the OM13488 8 bit GPIO Daughter Card Direct connection to OM13320 Fm Development kit Footprint fora TSSOP16 package user solderable Jumper configuration accommodates most NXP 8 bit GPIO Flexible power supply configuration 3 3V 5V or external supply Direct connection to OM1
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