2E16G - Jive
Contents
1. VCCSYN provides power to the VCC pin when the part is powered down Power VCCSYN from the same supply as VCC with appropriate filtering as shown in the manual 4 Serial RTS operation In the hardware flow control mode of operation the first assertion of RTSx after enabling the RxRTS bit MR1 register bit 7 does not have to be done manually If a FIFO position is available RTSx is enabled immediately when the RxRTS bit is set 5 Serial Transmitter Disabling The character in the temporary holding register will be lost if the transmitter is disabled Wait for TxRDY before disabling the transmitter 6 Recognition of DONEx as an input during single address transfers has been modified to cause channel termination after the current transfer Previous silicon would typically run another transfer but could also stop after the current transfer if the channel was forced off the bus by interrupt activity or other bus masters 2nd DMA channel or external bus request Effective mask F77J rev C 7 The tDICL min specification 27 has been changed from 5ns min to 8ns min on the MC68340FE16VC MC68340RP16VC and MC68340PV16VC only Effective mask F77J rev C 8 The PLL lock counter has been modified for external clock with VCO mode to increase the clock delay to lock from 328 to 1864 clocks This delay applies to PLL locking for both power on reset and exit from LPSTOP if the VCO was turned off This means that power up reset wil2. 1 Select a channel 2 ISM value which prevents stopping channel 2 when channel 1 is to be initialized In general channel 2 s ISM should be greater than or equal to channel 1 s interrupt level or any other interrupt source which vectors to code used to initiate channel 1 Setting channel 2 s ISM to 7 avoids the problem entirely 2 Use channel 2 only for single address transfers 6 SIM External Clock with VCO mode When using external clock with VCO mode with an XFC capacitor in the 0 01 0 1uF range the SIM may not reliably detect VCO lock on powerup As a result the part never releases RESET even though the EXTAL input clock and CLKOUT are in phase Workaround Use a smaller XFC capacitor for frequencies gt 1MHz start with a capacitance value of 10000pf F_MHz Example for 16 0MHz the recommended XFC capacitance is approximately 10000pf 16 0 625pf An external POR circuit should be used for all external clock applications to guarantee RESET remains asserted until after VCC stabilizes For an external reset after POR the SLOCK bit may not be set This is only a problem with the assertion of the SLOCK lock indication the VCO and CLKOUT remain phase locked to the input clock both during and after the external reset 7 DMA DONEx Input In dual address mode if DONEx is asserted by an external device to stop the channel only the read portion of the last transfer will complete If DONEx is asserted before the first DMA transfer after
3. AA MOTOROLA Chip Errata 68340 Integrated Processor with DMA 10 06 95 Copyright C 1995 Motorola Contents of this document are intended only for the internal use of Motorola customers designing with this product This errata list applies to the following 68340 mask sets Mask Processing Part Number Geometry Suffix 2E16G 0 8u TBA 1F77J 0 8u KGN G67F 0 65u MEM The mask set for each part is encoded into the device topside markings for example the following markings indicate a device from the 1F77J mask manufactured in the 2nd week of 1995 MC68340FE16C 1F77J QEAQ9502 The errata are organized by mask set from oldest to newest with each errata listed under the last mask set that it applies to When working with 1D75M silicon for instance the errata for all prior revisions do not apply the errata shown for 1D75M and later do apply unless otherwise specifically noted The above mask list does not include masks which were never released to production or sampled 1 SIM BKPT DSCLK The 68340 SIM latches BKPT DSCLK on the rising edge of CLKOUT instead of on the falling edge This incorrect latching does not allow hardware breakpoints to reliably work for fast terminated accesses above 16 MHZ 2 CPU32 MOVEM DMA arbitration during a MOVEM to memory which is followed by an instruction that writes across the IMB can cause the MOVEM instruction to write incorrect data on the last move when it resumes operation
4. a channel is started single or dual address the channel will run 2 transfers before stopping 8 LPSTOP and External Clock with VCO When using external clock with VCO mode the CPU will not reliably exit LPSTOP if the SYNCR is programmed to turn off the VCO when in LPSTOP Workaround Program the SYNCR to enable the VCO in LPSTOP 9 DMA Bus Error If the last transfer of a DMA module bus tenure is terminated with an externally generated bus error the following CPU bus cycle may not be internally terminated by the SIM or may be bus errored An internal BERR assertion by the SIM s bus timeout circuit does not cause this problem 1 SIM Autovectored IACK and BR If BR is asserted during an autovectored IACK cycle AS will negate 1 2 clock early Workaround Decode the IACK address range A19 amp FC2 amp FC1 amp FCO amp AS and use the resulting signal to force BR high during IACK cycles 2 SIM Show Cycles and BR If show cycles and external arbitration are enabled and BR is asserted immediately before the clock edge from which DS asserts for a show cycle the show cycle will be truncated The data bus drive time for the show cycle will overlap the front end of the alternate master bus tenure by one clock data will tristate from the clock falling edge one clock after the falling edge BG asserts from MC68340 Errata 10 06 95 Copyright 1995 Motorola pg 2 Workarounds 1 Disable show cycles when alternate master bus activ
5. 90Hz 2400 154kHz 134 5 8660Hz 4800 309kHz 150 9650Hz 7200 465kHz 200 12 9kHz 9600 621kHz 300 19 3kHz 19200 1 26MHz 600 38 5kHz 38400 2 56MHz 1050 67 3kHz 76800 8 29MHz 1200 76 9kHz Note See text for other minimum system frequency considerations Table 1 Minimum CLKOUT Frequency vs Baud Rate The minimum CLKOUT frequency is calculated using the following formula CLKOUT min 1 1 baud_rate sample_rate Tsetup Thold 2 50 38400 baud 1 1 baud_rate 32 30ns 2 or 76 8K baud 1 1 baud_rate 48 30ns 2 TsetuptThold 30ns Sample_rate 48 for 76 8Kbaud 32 for others Note that with this revision replacing the serial crystal with a lower subfrequency 1 8432MHz for example no longer affects the minimum CLKOUT frequency for a specific baud rate since the selected baud clock is now synchronized Also the logic for the CTSx inputs uses the 1200baud clock as a sample clock CLKOUT Fmin should be kept above 76 9KHz to avoid affecting CTSx sampling end MC68340 Errata 10 06 95 Copyright 1995 Motorola pg 5
6. The data in the CPU register which is being moved is not affected Workaround Place a NOP instruction after each MOVEM to memory 3 Serial Transmitter Auto RTS operation RTSx will negate after the last character in the shift register is transmitted even if the transmitter has not been disabled 4 DMA Early Termination If CCR2 is written and BTC2 lt 0000 000F and a request is pending for channel 1 and the BTC1 value following the transfer will be xxxx xxx0 then channel 1 may terminate early after completion of the pending transfer DONE1 for external request modes asserts for the transfer and the DONE flag in CSR1 is set Workarounds a Avoid starting or stopping channel 2 with byte counts less than 10 if channel 1 is active b Disable channel 1 activity while writing CSR2 This can be done in software by raising the interrupt mask in the CPU32 s SR register above the ISM level in the DMA MCR1 register MC68340 Errata 10 06 95 Copyright 1995 Motorola pg 1 c If the device connected to channel 1 can ignore the early DONE1 assertion reset CSR1 and set the CCR1 start bit to restart the channel 5 DMA Configuration Error If a pending interrupt or an increase in the CPU status register interrupt priority mask bits forces DMA channel 2 off the bus in the middle of a multi cycle DMA transfer e g dual address and the CCR1 STR bit is then set to start channel 1 a channel 1 configuration error will result Workarounds
7. ains preliminary information on a functional improvement for the serial module implemented in the 68340 beginning with the F77J mask The relaxed clock specifications shown are preliminary and subject to change Change description The serial module internal clock synchronization has been revised to relax CLKOUT minimum frequency requirements when using the internal baud rate generators The revised CLKOUT requirements are a relaxation of the current specifications no change to existing designs will be required to accommodate this feature Previously a minimum 8 3MHz CLKOUT frequency was required to use the internal baud rate generators with the default 3 6864MHz serial crystal In the new serial module the serial clock synchronization has been modified to allow the minimum CLKOUT frequency to be scaled depending on the maximum baud rate selected Operation and specifications for external clocking via SCLK are not affected by this change Table 1 below shows the resulting minimum CLKOUT frequency for each programmable baud rate Note that applications using the VCO clock modes crystal and external clock with VCO are restricted to a 131KHz minimum CLKOUT frequency An errata exists which also limits CLKOUT to 100KHz for external clock without VCO mode refer to the silicon errata for each part baud CLKOUT baud CLKOUT rate Fmin rate Fmin 50 3250Hz 1800 116kHz 75 4850Hz 2000 129kHz 110 70
8. he MC68340 electrical specifications list a maximum 5ns skew between EXTAL and CLKOUT for external clock with PLL mode Skew between these 2 edges may exceed 5ns For operating frequencies gt 10MHz the EXTAL to CLKOUT skew is 9 5ns maximum CLKOUT falling edge may occur between 5ns before and 9ns after the corresponding EXTAL falling edge For frequencies less than 10MHz the maximum skew is 10ns Note that the PLL locks falling edges not rising of the EXTAL clock input and CLKOUT MC68340 Errata 10 06 95 Copyright 1995 Motorola pg 3 68340 Integrated Processor with DMA NOTES These notes describe silicon operation which is different from the original documented operation of the 68340 These are permanent features future documentation revisions will reflect this operation 1 JTAG DONEx The JTAG dma ctl scan bit bit 83 documented in the original User s Manual and implemented in silicon revisions through D75M is extraneous and IEEE 1149 1 non compliant Silicon revisions after xD75M do not support this bit and all subsequent bits are shifted forward one position Rev 1 of the User s Manual documents the revised D97R and later JTAG scan chain 2 PIT Background Mode If Background Debug Mode is entered and exited while the PIT is running and the FRZ1 bit in the SIM MCR is set the PIT value may decrement by an extra count shortening the timeout period This will typically only affect emulation 3 VCCSYN Power
9. ity is possible 2 Delay BG assertion to the system by one clock or delay the alternate master from driving the data bus for one clock after BG asserts 1 SIM Loss of Crystal without Limp Mode If a loss of crystal occurs while the VCO is set to a low operating frequency 131 KHz the part may lock up and not enter limp mode 2 CPU System Clock Minimum Frequency The minimum operating frequency for all clock modes is 100kHz 3 DMA DONEx input This errata item applies only to masks 1F77J and G67F If DONEx is recognized asserted before or after the DACKx signal has been asserted or negated respectively the channel will block further recognition of DREQx but will not clear the STR bit in the DMACCR register or set any of the channel termination status bits in the DMACSR register This specific device functionality is not guaranteed and may change on future mask sets Workarounds a Assert DONEx after DACKx has been asserted and before DACKx is negated b Since DONEx as an input is used to signal that the current DMA transfer is the last peripheral devices that signal a done termination when there are no more DMA transfers required can either initiate a dummy DMA transfer with DONEx asserted or generate an interrupt directly to the CPU For the direct interrupt the interrupt service routine can then clear the DMA channel and initialize it for the next transfer 4 Clock skew for external clock with PLL mode T
10. l be slightly longer and that the SLOCK bit in the SYNCR register will be set slightly later following a reset Effective mask F77J rev C 9 The appearance of CLKOUT following RESET has been changed if the VCO was turned off during LPSTOP If CLKOUT was turned off during LPSTOP it will not resume toggling upon exiting LPSTOP until the PLL has achieved lock If CLKOUT was selected to be the EXTAL input during LPSTOP it will not switch back to the VCO output upon exiting LPSTOP until the PLL has achieved lock These changes affect both crystal and direct drive mode All clock switches will still be clean no short duration highs lows Effective mask F77J rev C 10 JTAG I O control change Following JTAG test reset not functional reset all I O and output pins will be set to input or high impedance states This was not previously true for some pins Note that most automated vector generators and most programmers don t rely on the reset to determine their direction anyway Effective mask F77J rev C 11 CPU minimum frequency requirements for using the serial module baudrate generator have been relaxed This means that customers can run the device below 8MHz for baud rates below 76 8K baud Please refer to the attached description for more detailed information Effective mask F77J rev C MC68340 Errata 10 06 95 Copyright 1995 Motorola pg 4 Serial Module Clocking Change Preliminary Information Note This document cont
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