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PAC-Designer Software User Manual

1. i Yoages 1 Supply i Type DAC Codes DAC Range ADC j Trim Attenuator bit pial Configuration Error Dialog messages amp Diagnostics Examples or Feedback Components Trim Interface resistor values Profiled Mode l Options 12 PAC Designer Software User Manual DESIGNING POWER MANAGER Devices Design Entry Modifications to existing DC DC library files must be made from within the DC DC Library Builder Changes in the desired target voltages or supply selection are done from the Trim Configuration dialog box It is strongly advised that library files not be modified while trim cells are being configured because this can create confusion and make it difficult to detect errors in your work If a discrete supply is to be used at several different voltages a separate library entry for each unique output voltage should be created The Library Builder stores its files in the DCtoDC_Library directory which is located under the main PAC Designer install directory The Trim Configuration dialog box import facility launches a file browser in order to make it possible to import library files created in earlier versions of PAC Designer or library files that have been stored elsewhere The Trim Configuration dialog box provides the ability to re do the trim calculations with a minimum amount of parameter re entry Target voltages need to be re entered only if th
2. OK Cancel Print File Export Cursor 1 L Btn 0 Y Cursor 2 R Btn 0 Y 10ms Div me 4 gt fu The results are plotted based on the parameters entered The actual data points can then be exported to a csv file to be used in a spreadsheet if needed The Plot window also supports cursor measurements and printing Using the Platform Manager I2C Utility The Platform Manager 12C design utility is opened from the Design Utilities dialog box This utility allows you to drive the I2C interface with the Lattice ispDownload Cable You must first set up the device with PAC Designer and program in the I Os and features needed to communicate with the 12C The 12C Utility dialog box shows the different functions which can be controlled by 12C Importing Data to a PAC Designer Schematic You can import several types of data in several formats to a PAC Designer schematic To import data to a PAC Designer schematic 1 Choose File gt Import PAC Designer Software User Manual 67 DESIGNING PLATFORM MANAGER DEVICES Design Entry The Import Dialog Box opens Under Import What select a data type The available data types listed in this box are device dependent Under In the format select the desired import file format Under Import From click Browse to navigate to the file that you want to import into your PAC Designer schematic Click OK Exporting Data from a PAC Designer Schemati
3. This utility allows you to drive the I2C interface with the Lattice ispDownload Cable You must first set up the device with PAC Designer and program in the I Os and features needed to communicate with the 12C Main Screen 12C Utility ispopPAC POWR1220AT8 version shown ispPAC POWR1220ATS8 I2C Utility in lol xj Fie view Options Help l2C Address 1h VMON Voltages and Comparator Status Margin and Trim DACs Set View Inputs View All Registers Set View Outputs Device Reset We Senis SMB Alert Reset The main screen shows the different functions which can be controlled by 12C The operation of the full features are described in an Application Note AN6067 Power Manager I2C Utility Importing Data to a PAC Designer Schematic You can import several types of data in several formats to a PAC Designer schematic To import data to a PAC Designer schematic 1 Choose File gt Import The Import Dialog Box opens 2 Under Import What select a data type The available data types listed in this box are device dependent Under In the format select the desired import file format Under Import From click Browse to navigate to the file that you want to import into your PAC Designer schematic 5 Click OK PAC Designer Software User Manual 29 DESIGNING POWER MANAGER DEVICES Design Entry Exporting Data from a PAC Designer Schematic You can export several types of data in s
4. To simulate the design with the exported HDL 1 Before running simulation with Active HDL copy and reference the powr VHDL and ovi_powr Verilog simulation libraries gt Copy library files from lt PAC Designer_install_path gt active hdl Vlib to lt Active HDL_install_path gt Vlib Add the following lines to the lt Active HDL_install_path gt Vlib library cfg file powr SACTIVEHDLLIBRARYCFG powr powr 1lib ovi_powr SACTIVEHDLLIBRARYCFG ovi_powr ovi_powr lib Create a test file for the exported HDL netlist Create an Active HDL project add the HDL and the test file to it and run simulation Simulating a Platform Manager Design with Lattice Logic Simulator To simulate a design with Lattice Logic Simulator it must first be entered or edited using both the schematic pages and the LogiBuilder sequence editor Next a stimulus file should be created or edited using the Waveform Editor The stimulus file is used by the simulator which produces a graphical output that is viewed using the Waveform Viewer To start Lattice Logic Simulator from within PAC Designer 1 In LogiBuilder choose Tools gt Run PLD Simulator The Launch Simulator Dialog Box opens In the Stimulus File box browse to the desired stimulus file Click OK PAC Designer will remember this stimulus file and future simulations can be initiated by clicking the PLD Simulator button on the toolbar without bringing up the Launch Simulator
5. To exit PAC Designer gt choose File gt Exit Process Flow Here is a quick look at the PAC Designer process flow ispClock 1 2 3 Configure ispClock functions by editing the schematic Confirm clock functions using the ispClock design utilities Download the design to the device connected to the PC parallel port The ispClock devices use an IEEE1149 1 JTAG boundary scan compliant serial interface Power Manager 1 2 3 4 Configure Power Manager functions by editing the schematic Design and simulate PLD core logic with LogiBuilder and the simulator Confirm power supply rise time using the HVOUT simulator design utility Download the design to the device connected to the PC parallel port Power Manager devices use an IEEE1149 1 JTAG boundary scan compliant serial interface Exporting Importing Data PAC Designer can export alternative forms of schematic and plot data This information can be used for design documentation importing into third party software such as a spreadsheet for graphing or as in the case of svf file JTAG serial vector format data to program or read from devices in a JTAG serial chain PAC Designer supports several types of data which may be exported or imported in several formats The data types supported by PAC Designer for export import are device dependent Data Exported As Import Export Schematic JEDEC File Yes Yes Serial Vector Format No Yes Formatted Text No
6. nosy E monr A ov z Joorsv von z Jaan IV B umon _B uv nosy z mons A ov v Joorsv aj WMONe w vmons nes ws Vv L m Me Y mono A ov nosy z 9 vona mons v vmono_B ov v osv m MONIA ov oor E vono x monio M a M0n10_8 uv four z MoN A fov z Joorsv v monn x mon monne w gt oov A B MONIA fov 7 Joorsv wrote 7 vonn IV E vmon12 e uv nosy External pins can also be physically swapped in the CPLD Inputs High Voltage Outputs and CPLD Open Drain Outputs tabs of the Logic O Assignment Dialog Box Device Pin Swapping CPLD Inputs In the CPLD Inputs Tab of the Logic I O Assignment dialog box the CPLD input pins can be swapped Simply use the pull down menus and make sure there are no duplicated pin names Any digital input can be swapped with any other CPLD input PAC Designer Software User Manual 61 DESIGNING PLATFORM MANAGER DEVICES Design Entry Logic I O Assignment Pin Normal L true 0 false RC Register Normal L true O false Pin Normal L true O false Pin Normal 1 true O false Pin Normal 1 true 0 false 1 Device Pin Swapping High Voltage Outputs In the High Voltage Outputs Tab of the Logic I O Assignment dialog box the HVOUT pins can be swapped Simply use the pull down menus and make sure there are no duplicated pin names Any HVOUT can be swapped with any other HVOUT CPLD Nod
7. 2 high voltage FET driver outputs 12 open drain digital outputs 4 digital inputs 24 macrocell PLD 4 programmable timers On chip clock generator 20 programmable threshold comparators with window 10 VMON pins 2 high voltage FET driver outputs 12 open drain digital outputs 4 digital inputs PAC Designer Software User Manual ISPPAC DEVICE SUMMARY Table 1 ispPAC Device Summary Continued Device LA is PAC POWR1014 gt Automotive Grade gt LA isoPAC POWR1014A_ gt Automotive Grade gt gt ispPAC POWR6AT6 gt v ispPAC CLK5510 ispPAC CLK5520 v ispPAC CLK5610 gt ispPAC CLK5620 gt Applications Power supply monitoring Power supply start up shut down sequencing Power supply monitoring Power supply start up shut down sequencing 12C A D and control interface Power supply trim and margin Power supply monitor and control Precision clock generator Frequency multiplication amp division Precision clock generator Frequency multiplication amp division Zero delay buffer Features gt vv v vvvrvivvy vvvrvivvrvvvviyvyYvVv V vv vV Vv 24 macrocell PLD 4 programmable timers On chip clock generator 20 programmable threshold comparators with window 10 VMON pins 2 high voltage FET driver outputs 12 open drain digital outputs 4 digital inputs 24 macrocell PLD 4 programmable timers On chip clock generator 20 programmable threshold
8. includes WaitFor_Timer or Start_Timer instructions Reason This is a software limitation The ABEL code generator can deal with only one timer in any one instruction Remedy Insert any other instruction between the two instructions A No Operation instruction NOP may be used if no additional functionality is desired between the timer instructions Error 4 Goto IffhenElse attempts to branch to a step that does not exist Reason The Delete instruction function adjusts current Goto positions but does not protect against this error If you deleted enough instructions the Goto could be left pointing to empty space Warning 5 Un initialized Step numbers in IfThenElse instruction Reason If Then Goto 0 Else Goto 0 with step numbers all zero probably means un initialized step numbers and most likely was not the intent Symptom This would typically result in an endless loop in your design PAC Designer Software User Manual 37 DESIGNING POWER MANAGER Devices LogiBuilder Warning 6 Program may not terminate falls off the end Reason Last instruction is not a Goto or IffhenElse that performs a Goto self or Goto a_previous_step Discussion Most users will not get this error because End Program instruction is always present Users that must optimize code by removing the End Program instruction will be susceptible to this error Currently we do not allow removal of that instr
9. 1 Choose File gt Design Examples This opens the dialog box shown below in Figure 7 Figure 7 Opening a Design Example Design Examples Directory Files ispClock5406D 1 Dual FOB PAC Title ispClock5406D 2 ZDB PAC ispClock5410D 1 Dual FOB PAC ispClock5410D 2 ZDB PAC ispPAC CLK5304S_Demo PAC Author ispPAC CLK53085_Demo PAC ispPAC CLK53125_Demo PAC C A PAC DesignerS3 E xamples Fan out Buffer Implementation with ispClock5406D Subject ispClock5406d as a dual Fan out Buffer Lattice Applications Group Device ispPAC CLK5406D ispPAC CLK53165_Demo PAC ispPAC CLK5320S_Demo PAC ispPAC CLK56104_Demo PAC ispPAC CLK56204_Demo PAC Comments This design implements Dual fanout buffer Bank 0 to 1 distribute teh clock from Ref amp POWR1014 02 1 SSt_Seq_RG_Supervisor P POWR1014 1 SSt_Seq_RG_Supervisor PAC POWR10144 02 2 HS Controller PAC PO WR10144 2 HS Controller PAC PO WR10144 3_PCle_HS_Seq_RG_Sup PAC PO WR10144 3_PCle_HS_Seq_RG_Sup_501 PO WR1220478 1 SSt_Seq_RG_Sup_Trm PA PO WR12204T8 2_cPCI_HS_Seq_RG_Sup P PO WR12204T 8 3 L _HS_Seq_T_M PAC PO WR122047 8 3 L _HS_Seq_T_M_50 PAC PO WRE605 1_RG MI PAC POWR605 2_RG MI WDT PAC POWR605 3 Supervisor_Reset_ WDT_StrapS PO WRE607 1_RG_MI PAC PO WRE607 2 AG_MR_WDT PAC PO WR607 3 Dual_RG_MR_WDT PAC PO WR607 3 Dual_RG_MR_WDT_50 PAC POWRE07 4 neaative48V hotswap PAC Bank2 to Bank distribute the clock from RefB Outputs are configured as LYDS Outputs from B
10. 5M0 Step 8 Halt end of program Exception 1D Boolean Expression Outputs Exception Handler Comment lt end of exception table gt SMO Equation Supervisory Logic Equation Macrocell Configuration lt end of supervisory logic table gt PAC Designer Software User Manual 145 POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Sequence Control At step 1 the program waits for the calibration process to complete with all supplies tuned off At step 2 the 1 8V supply is turned on and simultaneously the Timer 1 5ms is also started The Sequence Controller waits at step 2 for 5ms after turning on the 1 8V supply and jumps to Step 3 At step 3 the 1 2V supply is turned on and simultaneously the Timer 1 is restarted The Sequence Controller waits for the 1 8V and 1 2V supplies to reach regulation within 5ms If both supplies reach regulation within 5ms the Sequence Controller jumps to step 4 where it waits for 200ms and jumps to step 5 At step 5 the Sequence Controller halts with the reset signal released The sequence error flag is cleared The circuit board functions normally However at step 3 if the supplies did not reach regulation levels before 5ms the step times out and jumps to step 6 to begin the shutdown operation The code jumps to step 7 At step 7 both the supplies are turned off and the Seq_err flag is turned on indicating that the board failed to sequence Start Stop Timer Instructi
11. DRV_12V_FET Source Current 12 5 X 12C Register u Sink Current 100 u Open Drain Logic Output Charge Pump Output PLD Voltage 12C Register Sink Current 100u4 vf Open Drain Logic Output The dialog box shown in Figure 16 can be used to associate the physical pin to a logical pin name the output pin control HVOUT pin s voltage source current and sink current In addition each pin can be configured as a MOSFET driver or a logical open drain output gt Pin Name This is the name of the hardware pin in the datasheet To associate this pin with a different user defined name change the HVOUT pin name using the pull down menu User Defined Name This is the logical pin name used in the power management algorithm Digital Control From The radio buttons in this field determine whether the logic equations within the PLD or the register bits in the 12C register control the actual HVOUT pin Output Setting The radio buttons determine whether the output pin is configured as a high voltage pin or as an open drain logic output pin If the output pin is configured as a charge pumped high voltage pin its properties can be further changed gt Voltage The output voltage can be set to 12V 10V 8V or 6V gt Source Current Determines the turn on slew rate This can be set to 12 5uA 25uA 50A or 100A The lower the current setting the slower the ramp rate Sink Current Det
12. Procedures Using the ispClock Frequency Checker The ispClock Frequency Checker verifies that the operating frequencies of the phase detector and the VCO will be within the recommended limits for a given profile Using this utility is simple from the schematic window click the Frequency Checker button The Frequency Checker will calculate the operating frequencies of the phase detector and VCO based on the REF Frequency that has been input into the schematic If these parameters are within recommended limits for the ispClock device you will see an information window that says Current profile is realizable within recommended device operating limits If either of these parameters should fall outside its set of recommended operating limits the Frequency Checker will suggest changes such as using a different M divider setting that could be made to bring the design into the recommended limits The Frequency Checker only checks the profile that is active in PAC Designers schematic window when you start the utility If you intend to use more than one profile you must run the Frequency Checker individually on each profile that you want to check Using the ispClock Frequency Synthesizer The ispClock Frequency Synthesizer allows you to configure an ispClock schematic to implement a requested set of input and output frequencies This utility will choose interconnections and individual divider parameters to realize the set of frequencies in the
13. Selecting an item from the dialog box will transfer you to the appropriate schematic or window for editing 60 PAC Designer Software User Manual DESIGNING PLATFORM MANAGER Devices Design Entry Swapping Device Pins PAC Designer allows you to swap external physical pins while the design is being worked on and still being edited This can be done to correct or simplify board layout Device Pin Swapping Analog Input Settings In the Analog Input Settings Dialog Box the external pin names are listed in the first column under Pin Name These names represent the physical external pins of the package You can use the pull down menus to swap VMONs in this first column This only swaps the physical external pins Names used inside LogiBuilder are not affected Analog Input Settings nx Pin Name Schematic Net Name Logical Signal Name Monitoring Type Trip Point Selection 64 us Glitch Filter Window hlode Inp_5V_OK ov baw a v r voni 7 input 5w v v Cancel l Inp_5 _Over_LTP fuv 7 Jaatv x Jinp_3v3_0K ov z sav vonz x input 3 3 IV Iv Inp_38_Over_LTP uv v zas Bra 3v3 _0K ov Uy sav z vons z Board 33V IV IV 3rd_o _Over_LTP fuv z feas z Bra 2150K ov kow d vuona z Board 2 5 V IV 3rd_2 6_Over_LTP uv z e mons z Bra 180K ov X Jrscav aj WMONS w Board 1 8 V 7 anew v e ew a mons A oyo v Joorsv z one z vmone M E wmon uv
14. Setting the Step bus Radix The wave form viewer can display the step number in decimal binary octal or hex decimal formats To set the step bus radix 1 Choose Options gt Bus Radix The Bus Radix Dialog Box opens 2 Select the format desired Using Markers You can place a marker on a specific event in the simulation output To place a marker in the Waveform Viewer 1 Choose Object gt Place Marker or 94 PAC Designer Software User Manual DESIGNING PLATFORM MANAGER DEVICES Waveform Viewer Results Click the Place Marker tool in the toolbar as shown below BA Waveform Viewer DESIGN1_VMON1_6K File Edt View Object Tools Options Jump Help slal a A p A n 2 750 000 0 ns 2 Click the Query cursor on a waveform The software places a marker vertical line at that location 3 To hide remove the marker choose Object gt Hide Marker After the first marker is placed use the menu or tool to place a second marker The difference in time between the two is displayed in the status bar at the bottom of the window as shown below The time from VMONT7 tripping to HVOUT7 turning on is displayed as 4 21 ms The additional 110 us results from the step latency This additional delay can become quite significant if the PLD Clock Frequency were to be lowered using either the ispPAC POWR604 Clock and Timer Settings dialog box or the ispPAC POWR1208 ispPAC POWR1208P1 Clock and Timer S
15. 2 From the list select ispPAC CLK_Freq_Calculator exe ispPAC CLK_Freq_Synthesizer exe or ispPAC CLK_Skew_Editor exe ispPAC CLK5400D 5600 only 3 Click OK Alternatively these utilities may be started from the menu bar by clicking on the appropriate button He starts the Frequency Checker Fa starts the Frequency Calculator Hey starts the Frequency Synthesizer starts the Skew Editor this functionality is available for isoPAC CLK5400D 5600 only Using the ispClock Frequency Calculator The ispClock Frequency Calculator allows you to read a configuration from PAC Designer and calculate the output frequencies for that configuration You may also modify the divider settings so as to be able to quickly examine alternative designs when a suitable design has been found you may also write that configuration back to PAC Designer To use the ispClock Frequency Calculator 1 In the ispClock Frequency Calculator Window enter desired input frequency in MHz in the Input Frequency box 2 You may also change divider configurations by selecting an entry in the M N and V divider combo boxes 3 You may also change the feedback source by selecting a suitable choice in the Feedback Source box 4 Transfer your design to a specified profile in the active PAC Designer schematic by clicking Write to Schematic 5 When you finish click Exit 102 PAC Designer Software User Manual DESIGNING ISPCLOCK DEVICES
16. PAC Designer Software User Manual DESIGNING PLATFORM MANAGER Devices Design Entry Return to the LogiBuilder Sequence and Supervisory Logic Window and enter a minimal sequence using the timers and outputs you plan to use in ABEL Choose Tools gt Compile LogiBuilder Design or click the compile button on the toolbar to generate an ABEL template from which your custom ABEL design can be built from Choose View gt ABEL Source to open an ABEL Source Window Choose Edit gt Enable ABEL Editing to enable the edit window and disable the LogiBuilder window Make changes to the ABEL source to implement the desired design Choose Tools gt Compile ABEL or click the compile button on the toolbar to compile the design Note If syntactical or other ABEL errors are in the design the compilation will fail and an error report will be displayed Choose Tools gt Run PLD Simulator or click the simulator button on the toolbar to simulate the design from ABEL Note The default stimulus file should be edited to reflect the input signals and basic design Entering Supervisory Equations You enter supervisory equations for a Platform Manager device from the Supervisory Logic panel of the LogiBuilder Sequence and Supervisory Logic window Supervisory equations are combinatorial or registered logic independent of sequence controller logic To enter supervisory equations 1 From the top level schematic window config
17. last segment on the list For instance if the initial segment t1 was defined to be LOW then t2 will be HIGH t3 will be LOW and so on Each new segment is created by entering its duration into the Segment Duration box and clicking Add Segment Any segment listed in the Edit Waveform dialog box may be deleted by selecting it from the list and clicking Delete Segment When this operation is performed the states of all subsequent waveform segments will invert The duration of any segment listed in the Edit Waveform dialog box may be changed To do this select the segment and enter its desired duration in the Segment Duration box Then click Change Segment When you finish making changes to the segment list click OK to commit the changes to the waveform Waveform Editor Stimulus This section contains concepts procedures and user interface description on the Waveform Editor PAC Designer Software User Manual 87 DESIGNING PLATFORM MANAGER Devices Waveform Editor Stimulus Graphical Waveform Files The Waveform Editor is a graphical application that is used to create and edit wdl files Each waveform is given a user defined name and then edited to show transitions The Waveform Editor uses a data model called the Waveform Description Language WDL The language represents a waveform as a sequence of signal states separated by time intervals The language also has constructs that let you express the waveform pattern
18. 2 counter after 10 seconds Digital Timing Simulation Using PAC Designer To simulate a design with Lattice Logic Simulator the design must first be entered or edited using both the schematic windows and the LogiBuilder Sequence Editor Next a stimulus file should be created or edited using the Waveform Editor The stimulus file is used by the simulator which produces a graphical output that is viewed using the Waveform Viewer 164 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION Digital Timing Simulation Using PAC Designer To start Lattice Logic Simulator from within PAC Designer 1 In LogiBuilder choose Tools gt Run PLD Simulator The Launch Simulator Dialog Box opens 2 Inthe Stimulus File box browse to the desired stimulus file 3 Click OK The PAC Designer software will remember this stimulus file Future simulations can be initiated by clicking the PLD Simulator button on the toolbar without bringing up the Launch Simulator dialog box The Waveform Editor is a graphical application that is used to create and edit wdl files Each waveform is given a user defined name and then edited to show transitions The Waveform Editor uses a data model called the Waveform Description Language WDL The language represents a waveform as a sequence of signal states separated by time intervals The language also has constructs that let you express the waveform pattern hierarchically However it is no
19. 43 86 166 pattern repeating 48 91 setting default time scale 47 90 starting 45 88 starting automatic ABEL import 42 85 zooming in and out 44 88 Waveform Viewer adding signals to display 49 92 adding step to display 49 93 functional logic simulation 48 92 printing results 52 95 using markers 51 94 R reserved words 13 56 S schematics creating 99 downloading data 114 editing 99 editing symbols 16 58 editing with cursor feedback 18 60 100 editing ispClock 100 editing Platform Manager 59 editing Power Manager 17 entry 12 54 97 186 PAC Designer Software User Manual
20. Instruction Outputs Int Comment SMO Step 0 Begin Startup Sequence no ispPAC POWR12204T8 reset SMO Step 1 Wait For AGOOD SMO Step 2 HVOUT2 1 OUTS 0 Output instruction demonstration SMO Step 3 Begin Shutdown Sequence SMO Step 4 Halt end of program lt Exception ID Boolean Expression Outputs Exception Handler Comment lt end of exception table gt i SMO Equation Supervisory Logic Equation Macrocell Configuration Comment lt end of supervisory logic table gt The check box next to the exceptions can be checked to indicate whether this instruction can be interrupted by the exception condition or not In this example the output instruction can be interrupted The Comment section can store any text that will appear in the Comment section of the Sequence Controller at that step Wait for Instruction The Wait for instruction type includes three sub types gt Wait for lt Boolean gt Causes the sequence controller to stall at that step until the Boolean expression becomes true The Sequence Controller jumps to the next step after the Boolean expression becomes true gt Wait for lt Timeout Value gt Starts the timer and waits at that step until the timer expires The Controller proceeds to the next step after the timer expires gt Wait for lt Boolean gt with Timeout Starts the timer and waits for the Boolean condition to become true until the timer expires If t
21. Measure Voltage and Current Feed Individually on 12V 5V amp 3 3V Supplies Through 12C v v v V Interface to CompactPCI Backplane Logic Signals gt Sequence On Board DC DC Converters Monitor all Supplies for Faults amp Generate Brown out interrupt Shut Down All Supplies in Reverse Order The power management block diagram is shown in Figure 5 Here the ispPAC POWR1220AT8 device is used to implement hot swap sequencing and reset generation functions 118 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION Creating Opening a Design File Figure 5 CompactPCI Design 12V 05 BRD 12V 4 C s v1 a V2 75K inn v3 EDY M 1 xry pa 1 4 nai BRD 3V3 a o p zs a 5 L N CPU_Rst BD_Sel_b s 2 Rs 2 9 Q Alert_b a Brown_Out PCILRST_b ispPAC POWR1220AT8 tes Orv as si gt y BRD VEE The top left and the bottom left portions of Figure 5 performs the hot swap function The top right portion of the diagram is used to sequence supplies on the board and the right side of the diagram interfaces to the board reset supervision and other control functions Creating Opening a Design File To create a new file Choose File gt New This opens a dialog box Figure 6 that enables device selection PAC Designer Software User Manual 119 POWER MANAGER EXAMPLE IMPLEMENTATION Creating Opening a Design File Figure 6 Selecting a Device for a New D
22. PLDCLK pin HighZ Timers Timer 106 50ms Timer2 147 46ms gt Timer3 205ms gt Timer 0 032ms The Clocks amp Timers dialog box can be used to configure three sections of the Power Manager device Master Clock Source Configures the device as a standalone master or a slave by selecting the radio button options Standalone Runs the device on its internal 8MHz oscillator The MCLK pin is tristated gt Master In this state this Power Manager device is a master and sources the main 8MHz clock for all the devices The clock source is still its internal 8 MHz oscillator gt Slave This mode enables the Power Manager device to receive the clock sourced from another master gt PLD Buffered Clock Output This radio button setting determines whether the 250KHz clock output pin is tristated or not gt Timers This section enables time delay setting between 32 microseconds to 2 seconds 122 steps for each of the timer through the pull down menu Click OK to update the configuration and transition to the main schematic via the intermediate schematic shown on Figure 17 Configuring the I2C Block In the main schematic Figure 8 double click the 12C block above the ADC block at the top of the schematic to navigate to the following dialog box shown in Figure 19 132 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION Implementing Power Management Algorithm in
23. Pin Name This is the name of the pin in the datasheet This is a pull down menu that enables associating any VMON pin to a schematic net This feature can be used to accommodate changes required by the layout stage for example gt Schematic Net Name Enter the name of the schematic This can be any alphanumeric character gt Logical Signal Name There are two programmable threshold comparators associated with each of the VMON pins The names specified here will be used in the power management algorithm All names should begin with a letter No spaces are allowed To concatenate two words use the _ underscore No other special characters are allowed gt Monitoring Type Over Voltage Under Voltage monitoring selection Each of the comparator can be used to monitor an over voltage OV or an under voltage UV event The difference between the OV and the UV setting is location of hysteresis For example the OV comparator trips exactly at the set threshold trip point when the voltage excursion is from PAC Designer Software User Manual 123 POWER MANAGER EXAMPLE IMPLEMENTATION Configuring Digital Inputs low to high Once tripped the voltage has to drop below the hysteresis level to toggle the comparator back If under voltage is set then the comparator trips during the input voltage high to low excursion and the hysteresis is applied during the low to high excursion Trip Point Selection This is a
24. Yes PAC Designer Software User Manual INTRODUCTION TO PAC DESIGNER Exporting Importing Data Data Exported As Import Export SPICE Netlist No Yes LogiBuilder PAC File Yes Yes Margin Trim PAC File Yes Yes Plot Data Formatted Text Yes Yes For Power Manager and Platform Manager devices you can also export digital elements timers and the PLD core to a Verilog or VHDL file for functional simulation See Simulating a Power Manager Design with Aldec Active HDL for details 4 PAC Designer Software User Manual sm LATTICE Chapter 2 E SEMICONDUCTOR ispPAC Device Summary Table 1 ispPAC Device Summary Device Applications Features ispPAC POWR604 Power supply monitoring gt 8 macrocell PLD Power supply start up shut gt 2 programmable timers down sequencing gt On chip clock generator gt 6 programmable threshold comparators gt 4 open drain digital outputs gt 4 digital inputs ispPAC POWR605 Power supply monitoring gt 16 macrocell PLD Power supply start up shut gt 4 programmable timers down sequencing gt On chip clock generator gt 6 programmable threshold comparators 2 digital inputs 5 digital pins that can be configured as inputs or open drain outputs Low ICC power down mode ispPAC POWR607 Power supply monitoring 16 macrocell PLD Power supply start up shut 4 programmable timers down sequencing On chip clock generator 6 programmable threshold comparators 2 high volt
25. a Resistor Open uF v H Trimmed Margined Output Yoltage with Trim Resistor Connected jo Vv fo v fo y Trim Resistor in ohms Required to ohms oS Set Output Voltage as Above es g ohms Comment Save configurations to library file Murata_1 2_POL Save These supplies have a trim pin This pin is used to margin the supply up by 5 10 or margin the supply down by 5 10 Nominal Output Voltage is the normal operating voltage of the DC DC converter when its trim pin is open This is its normal operating state Next there are two fields under the headings Example 1 R to GND Example 2 R to GND and Example 3 R to Vout Examples 1 and 2 are conditions used to generate a margin voltage that is different from the nominal voltage Different target voltages will require different resistor values These values are provided in the DC DC converter 172 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION Creating a DC DC Converter Library Entry datasheet usually in a table format Some datasheets provide a formula to calculate these resistors Enter the values of the target output voltage and the values of the target resistors that are connected between Trim and GND pins into the required fields The third column requires the value of the resistor to be connected between the trim pin and the Vout pin of the DC DC to achieve the corresponding output voltage Enter the resistor value and
26. arrete A Mot 03_D scrcte_3 Vouk 12_D screte_1 2 out 11_D serete_1 2 out 12_D serete_3 Vouk 14_Piog_ II_S ir_0 0 2 ou 15_Piog_ 4_3vin_0 3 30u 15_Ping_ inx_P in_ 8 3 Wout 17_Piog_ n_S ir_ 0 2 Wou Commert P amp C Designer will create a library file for your DC DC Converter File name Murata_1 2_POL Cancel Next Zancel 2 The Select the DC DC Converter Type dialog box Figure 62 shows four types of DC DC converters 170 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION Creating a DC DC Converter Library Entry Figure 62 Selecting the DC DC Converter Type Select DC DC Converter Type Select the type of DC DC Converter C DC DC Converter with Trim up amp Trim Down Supply MV DC DC Converter e DC DC Converter with Programmable c Programmable DC DC Converter with Output Voltage Rtrim Connected to Vout lt Back Cancel a DC DC Converter with Trim up amp Trim down Supply This DC DC converter usually is available as a module with a fixed voltage These supplies can be margined up and down by connecting a resistor to GND or to VOUT b DC DC Converter with Programmable Output Voltage The output voltage of these DC DC converters is set by connecting a resistor from trim pin to ground The value of the resistor determines the output voltage c Programmable DC DC Converter with Rtrim Connected to Vout The output voltage of thes
27. can be created using any of the input or output signals by the following process PAC Designer Software User Manual 139 POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Sequence Control 1 Double click the required input signal to transfer it to the Boolean Expression window First double click the Core_1V2_over_LTP signal Click an operator button Click AND Double click the 1O_1V8_over_LTP signal At this point the dialog box shown in Figure 26 will be as shown in Figure 27 Figure 27 Entering a Boolean Expression Boolean Expression Editor Boolean Expression Core_1 2_over_LTP AND I0_1 8_over_LTAl Cancel OR NOT xOR Double click to add available items to expression Core_1 2_0K Click OK to return to the Edit Wait for Bool properties dialog box as shown in Figure 28 Figure 28 Edit Wait For Bool Properties Dialog Box Showing the Newly Added Logic Equation Edit Wait For Bool properties Instruction Preview Instruction Outputs Wait for Core_1 2_over_LTP AND IO_1V8_over_LTP Cancel Output Control Instruction is interruptible by an exception Comment Next click Output Control to open the Edit Output properties dialog box shown in Figure 29 This is the same dialog box as that of the Output instruction Here the core supply 1 2V enable and IO supply 1 8V enable signal are turned on 140 PAC Designer Software User Manual POWER MANAGER EXAMPLE I
28. components This topic describes how to edit them Cursor feedback provides visual cues to aid the editing Symbols are also known by name and can be edited by name Single Throw switch feedback resistor To Close Drag from active contact indicated by cursor to close the connection To Open Drag from active contact indicated by cursor to open the connection Edit Dialog Box Double click over active area indicated by cursor Multiple Throw switch Interconnect to Input Stage To Close Drag from Input Stage input to an terminal wire indicated by cursor To Open Drag from connected terminal wire back to Input Stage input Edit Dialog Box Double click over active area indicated by cursor Circuit components caps input stage gain and so on 58 PAC Designer Software User Manual DESIGNING PLATFORM MANAGER Devices Design Entry Edit Dialog Box Double click over active area indicated by cursor Editing a Platform Manager Schematic The Platform Manager device main schematic contains function blocks that can be edited by double clicking any given block Analog Inputs The Analog Inputs are comparator inputs each with a programmable threshold trip point the outputs of the comparators feed into the CPLD of the Sequencer Block Clock and Timers Three programmable timers can be set independently to a wide variety of durations in the range of 032ms to 1 966s An internal oscillator BMHZz i
29. dialog box Automatic ABEL Import Waveform Editor This section introduces how to automatically import ABEL files with the Waveform Editor 84 PAC Designer Software User Manual DESIGNING PLATFORM MANAGER DEVICES Automatic ABEL Import Waveform Editor Graphical Waveform Files The Waveform Editor is a graphical application that is used to create and edit wdl files Each waveform is given a user defined name and then edited to show transitions The Waveform Editor uses a data model called the Waveform Description Language WDL The language represents a waveform as a sequence of signal states separated by time intervals The language also has constructs that let you express the waveform pattern hierarchically However you do not have to be familiar with the Waveform Description Language to use the Waveform Editor Zooming In and Out Click the Zoom In button on the toolbar or the Zoom In button on the toolbar to activate the zoom cursor You can also choose View gt Zoom In and View gt Zoom Out to activate the zoom cursor Waveform Editor DESIGN1 Fie Edt View Object Tools Options Jump Help CLK_IN 1 Place the zoom cursor over the time of interest and click to zoom in or out Repeated clicks will continue to zoom in or out To cancel the zoom in cursor right click 11 500us Y Starting the Waveform Editor In order to start the Waveform Editor from a project that has been saved an ABEL file must
30. down and turn all supplies off This instruction turns on the 1 2V supply and starts the 5ms timer simultaneously After that it waits for the 1 2V and 1 8V assuming the 1 8V was turned on previously supplies to reach regulation If the supply turns on before the timer expires the Sequence Controller moves to the next step If the 5ms timer expires the program jumps to shut down routine Figure 36 shows a program with this new instruction Figure 36 Program Using the Wait for Boolean with Timeout Instruction PAC Designer Design1 PAC Sequence and Supervisory Logic DER Eile Edit view Tools Options Window Help ax oe se NDB A 4 Hr sem Ge El at 2 gt Pas A a a Ea Sequencer Instruction Outputs ooo dtn Comment o o SMO Step 0 Begin Startup Sequence ispPAC POWR12204T8 reset SMO Step 1 Wait for AGOOD Core_1 2_En 0 IO_1 8_En 0 Reset_CPU 0 Start with all supplies turned off and SMO Step 2 Wait For 5 12ms using timer 1 1O_1V8_En 1 Turn 1 8V and wait For Sms SMO Step 3 Wait for Core_1 2_over_LTP AND IO_1 8_over_LTP Core_1V 2_En 1 If 1 2 supply does not If Timeout turn on within 5 ms jump Then Goto 6 to shut down and turn alls SMO Step Wait For 212 99ms using timer 2 SMO Step 5 Halt Reset_CPU 1 Seq_Err 0 Realse reset and keep the system on SMO Step 6 Begin Shutdown Sequence smo Step 7 Core _1V2_En 0 10 1 8 En 0 Seq Err 1 There was a supply Fault shut all su
31. exist ABEL files are usually produced by compiling a LogiBuilder design ABEL files may also be generated by the user either in PAC Designer or using a stand alone text editor The Waveform Editor scans the ABEL file to determine the names of the input and output signals in use If the project has not been saved then an ABEL file can be selected manually after the editor has been started by choosing File gt Import ABEL Design To start the Waveform Editor Choose Tools gt Run Waveform Editor or PAC Designer Software User Manual 85 DESIGNING PLATFORM MANAGER DEVICES Automatic ABEL Import Waveform Editor gt Click the Waveform Editor button on the PLD Toolbar as shown below PAC Designer Design1 PAC Sequence Controller Zj File Edt View Tools Options Window Help Da S H SQ RAB ALA Ae seo pos ogie E BF E Step 0 Begn Startup Sequence spPAC PWR1 208 reset Step 1 Wait for VMON1 Wait for VMON to cross threshold Step 2 Wait for 4 086ms using timer 1 Wait 4 mili seconds Step 3 HVOUT1 1 Tum HYOUT1 on Step 4 Begn Shutdown Sequence lt end ol peogam gt Importing an ABEL File The Waveform Editor looks at the contents of the ABEL file for the current design in order to determine the names of the input stimulus signals This occurs automatically when the Waveform Editor is launched from a PAC design that has been previously saved If the Waveform Editor is launched from a design that has not
32. file Edit view Tools Options Window Help E x ARa a e Cee PHS ogo E BA Ea EY ea a E pi IF lt booleanExpr gt lt no outputs sp Starts at step 0 lt end of exception table gt Equation Supervisory Logic Equation i Macrocell Configuration lt gt 4 To configure the exception condition double click EO and edit the dialog box as shown in Figure 48 Figure 48 Exception Properties Dialog Box Exception properties Expression which triggers the exception Cancel Edit Exception will make sequencer go to Step 0 Jump only occurs when instruction is Interruptible Outputs controlled by expression Outputs are active at all times interruptible flag is ignored Me I Change this output signal Set Value Asynchronously set to 1 when expression is true RS FF Asynchronously set to 0 when expression is true RS FF Synchronously follows expression D FF Synchronously follows inverse of expression D FF Emulation Comment PAC Designer Software User Manual 157 POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Exception Conditions The first step is to enter the exception condition Boolean equation To do this click Edit on the top section of the dialog box to open the Boolean expression builder shown in Figure 27 The next step is to identify the step that the Sequence Controller should jump to when the Boolean condition becomes
33. flag is ignored TIMER3_GATE v V Change this output signal Set Value Asynchronously set to 1 when expression is true RS FF Asynchronously set to 0 when expression is true R S FF Synchronously follows expression D FF C Synchronously follows inverse of expression D FF Emulation Comment nal is latched into Latched_ wWDT_Trig Node 158 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Exception Conditions In this figure the logic expression is WDT_Trig signal The exception condition location is not used as there is no exception function specified In the outputs controlled by the expression section the Latched_WDT_Trig node is selected The selected logical operator is Synchronously follows the expression D FF This operation converts the Latched_WDT_Trig into a D FF with its data connected to the WDT Trig signal and is clocked by the 250kHz clock that is clocking the Sequence Controller Now the original logic expression in the exception logic EO shown in Figure 46 is modified to recognize the falling edge of the WDT_Trig signal instead of just logic 0 Figure 50 shows the modified logic in the exception condition EO Figure 50 Exception Condition Modified to Trigger at the Falling Edge of WDT Trig PAC Designer Figure_40_Exception condition PAC Sequence and Supervisory Logic file Edit view Tools Options Window Help D gug i SF
34. frequency is unknown the Frequency Synthesizer can also be used to suggest a suitable value Skew Editor The Skew Editor provides a graphical interface for configuring the relative edge skews of all of the devices outputs Design Examples The PAC Designer software provides a library of pre configured designs for example use Choose File gt Design Examples The Design Examples Dialog Box contains a list of pre configured designs When you click a design in the list a description of the design appears on the right side of the dialog box You can open the schematic and use it as is or you can edit the schematic 98 PAC Designer Software User Manual DESIGNING ISPCLOCK DEVICES Procedures Procedures This section provides step by step procedures for completing tasks you can perform in designing ispClock designs Creating a New Schematic You can create a new schematic or open an existing schematic To create a new schematic 1 Choose File gt New The New Dialog Box opens 2 Select the schematic for the ispPAC device you wish to design 3 Click OK The device schematic window is displayed Editing a Schematic You can edit a schematic using several techniques including Double Click You can double click over each symbol in the Schematic Window to invoke the appropriate dialog box to edit the item See Editing Schematic Symbols Click and Drag to Connect wires Feedback Drag from the point furthe
35. layout Device Pin Swapping Analog Input Settings In the Analog Input Settings dialog box the external pin names are listed in the first column under Pin Name These names represent the physical external pins of the package You can use the pull down menus to swap VMONs in this first column This only swaps the physical external pins Names used inside LogiBuilder are not affected PAC Designer Software User Manual 19 DESIGNING POWER MANAGER DEVICES Design Entry Analog Input Settings for a aor rear fore oe sore eos aor ery mone f fons CIE C jone one jwow C ono vonn aonn wont on Inp_5 _Over_LTP Inp_3 3_Over_LTP Brd_33_OK ard_3V8_Over_LTF Brd_2 5_OK Srd_2 8_Over LTP Brd_1 8_OK 3rd_1 v8_Ower_LTP WMONG_A WMIONG_B MON _B MIONS_A MONS_B VMONS A IONS_B MON 10_B MONTT_8 TATTLE CEL lhl th lhl External pins can also be physically swapped in the Digital Inputs High Voltage Output Settings and Logic Outputs dialog boxes 20 PAC Designer Software User Manual DESIGNING POWER MANAGER Devices Design Entry Device Pin Swapping Digital Inputs Digital Inputs mo agm ne z fing ns g n o moam s a fins fns fing ec e Q O o Q e In this dialog box the digital input pins can be swapped Simply use the pull down menus and make sure there are no duplicated pin names Any digit
36. or gt Select the symbol from the list and press Enter A secondary dialog box specific to the symbol will appear Zoom Use standard Windows style zoom Editing Schematic Symbols PAC schematics contain SPST and SPMT switches and components This topic describes how to edit them Cursor feedback provides visual cues to aid the editing Symbols are also known by name and can be edited by name Single Throw switch feedback resistor To Close Drag from active contact indicated by cursor to close the connection To Open Drag from active contact indicated by cursor to open the connection Edit Dialog Box Double click over active area indicated by cursor Multiple Throw switch Interconnect to Input Stage PAC Designer Software User Manual DESIGNING POWER MANAGER Devices Design Entry To Close Drag from Input Stage input to an terminal wire indicated by cursor To Open Drag from connected terminal wire back to Input Stage input Edit Dialog Box Double click over active area indicated by cursor Circuit components caps input stage gain and so on Edit Dialog Box Double click over active area indicated by cursor Editing a Power Manager Schematic The Power Manager device main schematic contains function blocks that can be edited by double clicking any given block Analog Inputs The Analog Inputs are comparator inputs each with a programmable threshold trip point the outputs of the
37. oscilloscope display Windows 95 98 and ME only 112 PAC Designer Software User Manual DEVICE PROGRAMMING Procedures 6 Click Test The test can take from microseconds to minutes depending on the count and the speed of the processor 7 When the test is completed click OK in the Parallel Port Options dialog box 8 Click OK in the Cable and I O Port Setup dialog box Setting Security Options A bit can be set inside a device to prevent all future upload or verify operations from yielding valid data The security bit provides an option to prevent unauthorized access to a device Once set and loaded to a device by a download operation the only way it can be removed is by reprogramming the device To set security options 1 Choose Edit gt Security The Security Dialog Box opens Select Secure Device Against Reading Click OK Setting UES Bits in an ispPAC Device Within ispPAC devices bits are made available for storing user specific information These are called User Electronic Signature UES bits These bits can be used to store device configuration design related data or any information you want to remain with the individual device Note Once the security bit has been set UES bits can no longer be accessed To set UES bits in a PAC device 1 Choose Edit gt Symbol The UES Editor opens This Editor can also be accessed by double clicking the UES text at the bottom of the design entry schema
38. pull down menu used to select the actual trip point from a table of 368 trip points The step size of these trip points are spaced at 0 5 of the nominal voltage value that is monitored gt 64 us Glitch Filter Each of the monitoring comparator can be configured to ignore supply glitches narrower than 64 microseconds by checking the associated box This means that the output of the comparator will transition only if the changed status remains active for a period longer than 64 microseconds If this box is not checked then the comparator output will toggle within 16 microseconds from the time the voltage transitions through the appropriate trip point gt Window Mode There are two comparators associated with each VMON pin Comparator A and Comparator B To use the window mode the Comparator B threshold should be lower than the threshold setting of comparator A The window mode output will replace the comparator A output The window output is logical high if the Comparator B output is high and the Comparator A output is Low After entering the values into all required fields of the dialog box click the OK button to update the design and transition into the intermediate schematic with two comparators per analog input Figure 9 Position the cursor outside the schematic region until the cursor becomes an up arrow Click the left mouse button to transition to the main schematic shown in Figure 8 Configuring Digital Inputs Starting at
39. resistor values is a two step process 1 Create a DC DC Converter Library using the DC DC converter s feedback and trim section characteristics This uses a few parameters commonly specified in a DC DC converter datasheet 2 Attach aDC DC converter to a Trim Cell Calculate the resistors for a given output trim and margin voltage specification for that DC DC converter Creating a DC DC Converter Library Entry To create a DC DC converter library entry 1 To create a DC DC converter library entry open the POWR1220AT8 design and click the DC DC button on the Margin toolbar to open the DC DC Converter Model Selection dialog box In the dialog box click New enter the name of the DC DC module for example Murata_1V2_POL and click Next to open the Select DC DC Converter Type dialog box PAC Designer Software User Manual 169 POWER MANAGER EXAMPLE IMPLEMENTATION Creating a DC DC Converter Library Entry Figure 61 Adding a DC DC Converter into the Library PAC Designer Design1 DAR File Edit View Tools Options Window Help Dae he Aaa Design1 Schematic r nnn DC DG Converter Model Selection DC DC Liba clder C FAC DesigreS2 D CtcD gt _Lbrarv Browse Select DAD Cenverter Manufarcuier and Vode fit_Ping INNA Wout New 02_Piog_3Vin_0 26Youl a 03_Piog_Svin_0 3 6y oul Delste 04_Pioo_12 n_0 75 5 CVout 05_Fised_A vin_1 9 ou O3_Fised_S 5 in_1 Bvuut Uf Hed 5 5 in 3 3Vout Rename MRD
40. sen hc EE ca f V m f step Sequencer Instruction Outputs mt Comment SMO Step 0 Begin Startup Sequence no ispPAC POWR 1220476 resq SMO Step 1 Wait for 4GOOD Core_1V2_En 1 10_1V8 no Start with all supplies turne SMO Step 2 Wait for Core_1 2_OK AND IO_1V8_OK Core_1V2_En 1 10_1V8 no Turn on all supplies and wai SMO Step 3 Wait for 212 99ms using timer 2 no Start reset pulse stretch SMO Step 4 Reset_CPU 1 no Release CPU Reset SMO Step 5 Start timer 3 524 29ms no This starts the timer and tut SMO Step 6 IF NOT Core_1 2_OK OR NOT IO_1V 8_OK WDT_Intr 1 Wait For supply Fault or Then Goto 6 watrchdog tiemr expiration Else IF Timer 3 Then Goto 4 with WDT_Intr 0 Else Goto 7 SMO Step 7 Reset_CPU 0 SMO Step 8 Halt end of program j Exception ID Exception Handler Comment IF NOT WDT_Trig AND Latched_WDT_Trig lt no outputs sp Starts at step 4 Activated at the Falling edge of WDT E i IF WDT_Trig Latched_WDT_ not used WDT Trig signal is latched into Latch lt end of exception table gt lt SMO Equation Supervisory Logic Equation Macrocell Configuration lt end of supervisory logic table gt The logic expression EO now looks at condition when the WDT_Trig signal is low and the Latched_WDT_Trig signal at logic high This condition is true for 4 microseconds and occurs only at the falling edge of the WDT_Trig signal PAG Designer Software User Manual 159 POWER MANAGER EX
41. supervisory equations are combined together during the compile process 74 PAC Designer Software User Manual DESIGNING PLATFORM MANAGER Devices LogiBuilder Importing HDL Modules to a Platform Manager Design The LogiBuilder allows you to add previously defined HDL code modules to a Platform Manager design by using the Import Sub Module command on the Options menu This command is available when the FPGA Sequence and Supervisory Logic window is active The HDL code modules can be IP cores or user created files To import HDL code modules 1 Inthe Platform Manager top level schematic window double click the FPGA Logic block to open the Sequence and Supervisory Logic FPGA Window 2 Choose File gt Import Sub Module gt Configure Sub Module The Module Definition Dialog Box opens 3 Inthe Module Name box enter a module name The name will be used to instantiate the module in the top level design 4 Click Port Mapping to open the Module Port Mapping Dialog Box Click Add to add a port for the module Double click the Port Name Port Direction and Signal Name cells to enter port name direction and signal name You can click Add again to add more ports or click Remove to remove the added ports When you finish click OK to go back to the Module Definition dialog box 5 Click Browse Navigate to the file that contains the module to be added to the design and click Open The file location will appear in the Fil
42. the signals that were defined in the stimulus file The names of the waveforms that are added to the display are stored in a wav file so that the added waves will be displayed the next time you start the Waveform Viewer This timing example shown in Figure 57 was created from the POWR607 1_RG_MI PAC example file in PAC Designer PAC Designer Software User Manual 165 POWER MANAGER EXAMPLE IMPLEMENTATION Digital Timing Simulation Using PAC Designer Figure 57 Waveform Viewer Showing the Simulation Stimulus fa Waveform Viewer POWR607 1_RG_ MI File Edit View Object Tools Options Jump Help sla S eleen 22 2 Time 388 0 us You can edit and modify waveforms with the Edit Waveform dialog box The contents of the dialog box will change based on which waveform is selected You can launch this dialog box by double clicking a signal in the Waveform Editor or by choosing Edit gt Waveforms and then double clicking the signal name in the Waveform Editor dialog box as shown below Figure 58 Edit Waveform Dialog Box Edit monza waveform i x Waveform Name VMON2 A Initial State t1 Index Level Duration Total Time Cancel HIGH Low Delete Segment Add __AddSegment Segment D watin O 0 us _Change Segment Segment When the dialog box is first opened no parts of the waveform for its signal are defined The waveform is built by appending segments to the end of the list Th
43. to the entire design Creating and Editing an ABEL Design You can create and edit an ABEL design for a Platform Manager device To create and edit an ABEL design 1 From the top level schematic window configure the user defined inputs and outputs set the VMON trip points and configure the clock and timer settings 2 Double click the CPLD Logic block to display the Sequence and Supervisory Logic PLD Window 3 Choose View gt Pins definitions or click the pins button on the toolbar to display the Logic I O Assignment Dialog Box to configure the logic level of the input pins and the type and power up state of the output pins 4 Return to the LogiBuilder Sequence and Supervisory Logic Window and enter a minimal sequence using the timers and outputs you plan to use in ABEL 5 Choose Tools gt Compile LogiBuilder Design or click the compile button on the toolbar to generate an ABEL template from which your custom ABEL design can be built from PAC Designer Software User Manual 73 DESIGNING PLATFORM MANAGER DEVICES LogiBuilder Choose View gt ABEL Source to open an ABEL Source Window Choose Edit gt Enable ABEL Editing to enable the edit window and disable the LogiBuilder window Make changes to the ABEL source to implement the desired design Choose Tools gt Compile ABEL or click the compile button on the toolbar to compile the design Note If syntactical or other ABEL errors are in the des
44. us Change Segment PAC Designer Software User Manual 43 DESIGNING POWER MANAGER DEVICES Waveform Editor Stimulus When the dialog box is first opened no parts of the waveform for its signal are defined The waveform is built by appending segments to the end of the list The state of the first segment is defined by the options under Initial State To create the first segment set the option as appropriate type in the duration of this initial state in the Segment Duration box and click Add Segment The state of subsequent segments is always the opposite of the state of the last segment on the list For instance if the initial segment t1 was defined to be LOW then t2 will be HIGH t3 will be LOW and so on Each new segment is created by entering its duration into the Segment Duration box and clicking Add Segment Any segment listed in the Edit Waveform dialog box may be deleted by selecting it from the list and clicking Delete Segment When this operation is performed the states of all subsequent waveform segments will invert The duration of any segment listed in the Edit Waveform dialog box may be changed To do this select the segment and enter its desired duration in the Segment Duration box Then click Change Segment When you finish making changes to the segment list click OK to commit the changes to the waveform Waveform Editor Stimulus This section contains concepts procedures and user interface descr
45. you may need to enter timing information for the simulation using the Timing Options dialog box This dialog box is used to set the resolution of the time scale that is placed at the top of the edit window To set simulation timing values 1 Choose Options gt Timing Values The Timing Options dialog box opens 90 PAC Designer Software User Manual DESIGNING PLATFORM MANAGER DEVICES Waveform Viewer Results 2 Select the time units you want Timing Options Fa Time units 10 C me Coi C us Con ing C oom ps Repeating a pattern You can repeat a waveform pattern with the Select dialog box To repeat a pattern 1 Select the entire waveform as shown below 2 Double click a row to select first the Low segment then the entire waveform 3 Type in the number of times to repeat the waveform in the Repeat box If the simulation time is unknown select the Repeat Forever box and the pattern will be repeated for the maximum duration of either the simulator or the Waveform Viewer 0 10 000 Jalie E Scale nH Repeat eooc I Foreves Waveform Viewer Results This section contains concepts procedures and user interface description on the Waveform Viewer PAC Designer Software User Manual 91 DESIGNING PLATFORM MANAGER DEVICES Waveform Viewer Results Functional Logic Simulation Waveform Viewer When the simulation is complete the results are stored in a binary fi
46. 0 PAC Designer Software User Manual DESIGNING PLATFORM MANAGER Devices LogiBuilder OUTPUT The OUTPUT instruction is used to turn on or turn off the Platform Manager devices output signals A single OUTPUT instruction can be used to simultaneously change the status of any number of output signals WAIT FOR lt Boolean Expression gt The WAIT FOR lt Boolean expression gt instruction suspends execution of the sequence until the specified expression becomes TRUE WAIT FOR lt Boolean Expression gt with Timeout The WAIT FOR lt Boolean expression gt with Timeout instruction suspends execution of the sequence until the specified expression becomes TRUE or the selected timer expires WAIT FOR lt time gt USING TIMER lt 1 4 gt The WAIT FOR lt time gt instruction is used to specify a fixed delay in the execution sequence The value of lt time gt is determined by which timer TIMER1TIMER4 is specified IF lt Boolean Expression gt THEN GOTO lt step x gt ELSE GOTO lt step y gt The IF THEN GOTO instruction provides the ability to modify sequence flow depending on the state of inputs If lt Boolean expression gt is TRUE the next step in the sequence will be lt step x gt otherwise the next step will be lt step y gt IF lt Boolean Expression gt THEN GOTO lt step x gt ELSE If Timer lt n gt GOTO lt step y gt ELSE GOTO lt step z gt This instruction provides the ability to modify sequence flow depending on th
47. 1 POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Sequence Control Figure 42 Using If Then Else with Timeout in a Hot Swap Application PAC Designer POWR1014A 02 2 HS Controller PAC Sequence and Supervisory Logic DER T Eile Edit view Tools Options Window Help A x Deed JED a gt ps St Ea Pin Definitions Step Sequencer Instruction Outputs m Comment SMO Step 0 Begin Startup Sequence yes ispPAC POWR1014 reset SMO Step 1 Wait for AGOOD no SMO Step 2 Turn_MOSFET_On_Fully 0 Start_HotSwap_ With SOA 0 no Do not start the Hot swap until thes SMO Step 3 Start timer 1 106 50ms no Start the Debounce Timer Set timer SMO Step 4 IF Inp_3 3_OK AND Inp_5 _OK no 5 and 3 3 Supplies are Then Goto 4 Stable for Debounce Else If Timer 1 period So start HotSwap Then Goto 5 Else Goto 1 SMO Step 5 Start_HotSwap_With_SO4 1 SMO Step 6 Wait For Brd_3V 3_OK AND Brd_S _OK or 2 05ms using Timer 2 Ensure 3 3 and 5 turn on TF Timemit within snecified time Exception ID Boolean Expression Outputs Exception Handler Comment SMO Equation Supervisory Logic Equation Macrocell Configuration EQO H5_3V3_MOSFET _Drive D NOT I_3V3_Over_50A_Li Output registered D flip flop Hot swap in SOA or Turn the MOSFE E i HS_5 _MOSFET_Drive D NOT I_SV_Over_SOA_Limit Output registered D flip flop Hot swap 5V supply or fully turn on EQ2 HS_3 3_MOSFET_Drive ar I_3V3_Over_Current OR I Output regi
48. 1 260 TargetVoutSP3 1 140 TargetVoutSP4 1 200 RealizedVoutSPl 1 198 RealizedVoutSP2 1 256 RealizedVoutSP3 1 140 RealizedVoutSP4 1 198 VdacCodeSP1 2 000 VdacCodeSP2 6 000 VdacCodeSP3 10 000 180 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION Creating a DC DC Converter Library Entry VdacCodeSP4 2 000 Vref 0 752 Rbuffer 2561546 920 Rfb 14467007 127 Rin 1000000000 000 Invert 1 IsProgrammable 1 IsModule 1 IsRtGnd 1 Rseries 2400000 000 Rpdni 10000000 000 Rpup2 10000000 000 Rpdn2 10000000 000 Rpupl 10000000 000 BPZVoltage 0 600 BrickName Murata_OKYT3 D12 xml BrickFilename TargetVdacCodesMax 110 EIAStdIdx 1 oOSeETAStdIdx 1 AttenuationCrossoverVoltage 1 900 axDeltaVoutPercent 5 000000 RpdnOption 0 Ropen 10000000 000000000000000 BPZSel 0 000000000001056 ResistorComputationAlgorithm 1 MarginTrimCell_end PAC Designer Software User Manual 181 POWER MANAGER EXAMPLE IMPLEMENTATION Creating a DC DC Converter Library Entry 182 PAC Designer Software User Manual RECOMMENDED REFERENCES Appendix Recommended References The following documents which are available on the Lattice website provide more detailed information about the PAC Designer software and applicable devices Reference Manual ABEL HDL Reference Manual PAC Designer Application Notes Using PAC Designer s Power Manager Waveform Editor AN6054 Using the HVOUT Simulator
49. AGER EXAMPLE IMPLEMENTATION Creating a DC DC Converter Library Entry calculated using a formula in the datasheet The two examples columns are also completed using the same table or the formula in the datasheet of the DC DC converter Note that one of the voltage values selected should be the maximum output voltage and the second voltage value should correspond to the minimum voltage These voltage values need not be the actual output voltage used in the circuit board Finally enter the DC DC converter model name for example Murata_OKYT3_D12 and save the file c Programmable Voltage with Resistor Connected from Trim Pin to Vout Figure 66 shows the dialog box that appears when Programmable DC DC Converter with Rtrim Connected to Vout is selected in Figure 62 Figure 66 Setting Reference Voltage Current for the DC DC Converter DC DC Converter Internal Vref Voltage Please enter the internal Vref voltage which is the trim pin output voltage with pin open You can enter either Vref 0 7525 Y DC DC Corwerter lt Back Cancel All DC DC converters use some form of reference voltage or current to set the output voltage The value of the reference voltage Vref is shown either in the specifications section of the datasheet or in its output voltage calculation formula Sometimes the datasheet shows the architecture of the error amplifier with the value of Vref PAC Designer Software User Manual 175 POWER M
50. AMPLE IMPLEMENTATION LogiBuilder Supervisory Logic LogiBuilder Supervisory Logic This section is provided to add additional logic functions that are independent of the sequence control into the CPLD part of the Power Manager device In some cases the Supervisory Logic section can be used to implement power management functions taking up fewer CPLD resources In this example the supervisory logic equations are being used to implement a 10 second duration timer using the hardware timers This long duration timer is required for monitoring the initialization section of the processor program on the circuit board This section describes the timer operation to facilitate understanding of long duration timer function implemented in the Supervisory Logic section Hardware Timer Architecture Implemented in Power Manager Device When Timer_gate is at logic high the hardware timer in the Power Manger counts down from a preloaded value programmable from 32us to 2 seconds to 0 and generates a Logic 1 on the Timer_TC signal as shown in Figure 51 Figure 51 Power Manager Timer Operation Programmable Timer Timer Gate 32us to 2 Sec Timer TC Timer Gate Timer TC rT oe Programmed Time Delay If the gate signal toggles to zero while the timer is counting down the timer delay value gets reloaded and the count down restarts There is a special mode of operation of the timer where the timer gate is connected to an inverte
51. ANAGER EXAMPLE IMPLEMENTATION Creating a DC DC Converter Library Entry In some cases the DC DC converters use current reference instead of voltage reference The current reference value is accompanied by a parallel resistor Again some DC DC converter data sheets show the equivalent circuit in the error amplifier section After entering the Vref or lref amp Rref values click Next to get the dialog box shown in Figure 67 Figure 67 Configuring the Programmable Voltage DC DC Converter Library Entry DC DC Converter Datasheet Example Configurations Va Vout DC DC Converter Nominal Output Voltage With Trim Resistor Open 0 8 Y Values from the DC DC Converter Datasheet Example Configuration Equations Example1 Example2 Example3 R to Vout R to Vout R to Yout Output Voltage with Trim bs bs iy Resistor Open ja v K Trimmed Margined Output Yoltage with Trim Resistor Connected jo V fo V y Trim Resistor in ohms Required to 0 ohms 0 ohms ohms Set Output Voltage as Above Comment Save configurations to library file POL_XYZ Save lt Back Cancel The output voltage of these types of DC DC converters is determined by the resistor connected from their trim pin to GND To complete this dialog box refer to the DC DC converter datasheet for a table that maps the output voltage to the resistor values connected between the trim pin and Vout In some cases the DC DC datasheet provides a formula for calcu
52. Al S sw rs ge E EA E Step 0 Begn Startup Sequence ispPAC PWR1208 reset Wavetoim Editor Step 1 Wait for VMON1 Wait for VMON to cross threshold Step 2 Wait for 4 056me using timer 1 Wait 4 mili seconds Step 3 HVOUT1 1 Tum HYOUT1 on Step 4 Begn Shutdown Sequence lt end olpeogam gt Importing an ABEL File The Waveform Editor looks at the contents of the ABEL file for the current design in order to determine the names of the input stimulus signals This occurs automatically when the Waveform Editor is launched from a PAC design that has been previously saved If the Waveform Editor is launched from a design that has not been saved an ABEL file must be manually selected To do this select File gt Import ABEL Design This will launch a file browser dialog box Select the desired ABEL file and click the Open button Creating and Editing Waveforms You can edit and modify waveforms with the Edit Waveform dialog box The contents of the dialog box will change based on which waveform is selected This dialog box may be launched by double clicking a signal in the Waveform Editor or by choosing Edit gt Waveforms and then double clicking the signal name in the Waveform Editor Dialog Box The Edit Waveform dialog box is shown below Edit MON2_A Waveform i Ed Waveform Name vM 0N2_A Index Level Duration Total Time Cancel Initial State t1 HIGH Low Delete Segment Add Segment Segment Duration 0
53. B port gt Ifthe parallel port option is selected the Parallel Port Options Dialog Box opens Ensure that the correct port is selected in the Parallel Port drop down box Ifthe USB port is selected the USB Settings Dialog Box opens Select the USB cable options and appropriate address method Note If you switch between the parallel port and the USB port you should close the PAC Designer and re open the design to update the port and cable settings 3 Click OK in the Parallel Port Options dialog box or the USB Settings dialog box 4 Click OK in the Cable and I O Port Setup dialog box Testing the Parallel Port Connection You can use the Parallel Port Options dialog box test the cable for signal integrity or write pulses to see if you have selected the correct port You will need an oscilloscope to test the signal from the selected device pin To test the parallel port connection parallel port cable interface only 1 With the device connected to your computer with a download cable and applied power choose Options gt Cable and I O Port Setup The Cable and I O Port Setup Dialog Box opens 2 Click I O port address The Parallel Port Options Dialog Box opens 3 Choose TCK TMS or TDI in the Pin drop down box depending on which pin you would like to test using an oscilloscope 4 Choose from 30 to 30 000 000 in the Pulse Count drop down box Select the Disable CPU interrupts during test option for a more stable
54. Else If Timer 1 Then Goto 0 Else Goto 0 Edit Boolean Expression Output Control On Condition Goto Sequencer step Step 0 v with Dutputs Timeout if above condition is not satisfied by this time Timer2 212 99ms timeout Edit Timeout properties Timer 3 1966 08ms timeout Timer 4 1966 08ms timeout On Timeout Goto Sequencer step Step 0 v with Dutputs Else Goto Sequencer step Step 0 X with Dutputs F Instruction is interruptible by an exception Comment The test Boolean function along with the outputs to be toggled during the step is entered as described from Figure 25 to Figure 28 The instruction first tests the Boolean condition to be true If the Boolean condition is true then it branches to the step indicated by the pull down menu next to On Condition Go to Sequencer step If the Boolean condition is false the instruction tests the timer expiry If the timer has expired the Sequence Controller branches to the step indicated by the pull down menu next to On Timeout Goto Sequencer step If the timer has not expired the Sequence Controller branches to the step selected by the pull down menu next to Else Goto Sequencer step Each branch condition can be set to toggle different sets of outputs independently through the Output Control button The following sequence control program Figure 42 uses the If Then Else with Timeout instruction PAC Designer Software User Manual 15
55. LogiBuilder Figure 19 Configuring the I2C Address amp Controlling the Inputs Outputs 12C Configuration 12C Address Oh Cancel 1 0 pins can connect to PLD or be controlled by 12C reads writes HVOUT1 PLD output drives pin PLD output drives pin PLD output drives pin PLD output drives pin PLD output drives pin PLD output drives bin PLD 1 0 connected to pin 12C interface connected to pin 12C Alert Response I SMB Alert on OUTS PLD output on OUTS is disabled This dialog box is used to set the 12C address of the device between 0 and 7E The 12C address is then programmed into the device and the PWOR1220AT8 device responds to that address The Input and output pin control through 12C can also be set from this dialog box in addition to the input and output block dialog boxes The POWR1220AT8 device supports the SMBAlert mechanism and this can be enabled by selecting the option Navigate to the main schematic by clicking the OK button Implementing Power Management Algorithm in LogiBuilder After configuring all inputs and outputs the next step is to implement the power management algorithm For that begin by double clicking the Sequence Controller block at the middle of the schematic Figure 8 The software navigates to the LogiBuilder window shown in Figure 20 PAC Designer Software User Manual 133 POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Sequence Control Figure 20 LogiBuilder Window fo
56. LogiBuilder The PAC Designer LogiBuilder Sequence Controller window allows you to create control sequences and define logic functions When complete the circuit can be simulated saved or downloaded to a Platform Manager device To design a control sequence with LogiBuilder 1 Ina Platform Manager Schematic window double click the CPLD Logic or FPGA Logic block to display the Sequence and Supervisory Logic window 2 Inthe sequence upper portion of the window highlight step 1 and choose Edit gt Insert Instruction to display the Insert Step Dialog Box 3 In the dialog box choose an instruction type and click OK Repeat as necessary to add logic steps 4 For each logic step choose Edit gt Modify Instruction Parameters to display the appropriate Edit dialog box 5 Select the desired logic properties in the Edit dialog box and click OK 6 To add exceptions in the exceptions lower portion of the window highlight lt end of exception table gt and choose Edit gt Add Exception Repeat as necessary to add exceptions 7 For each exception choose Edit gt Modify Exception Parameters to display the Exception Properties Dialog Box 8 Select the desired exception properties and click OK 9 When the logic sequence is complete compile your control sequence by choosing Tools gt Compile LogiBuilder Design Editing Pin Settings with LogiBuilder Pin names are set at the schematic level You can make edits to Plat
57. Logic I O Four banks of pins on the device can be individually configured to behave as either digital inputs outputs input outputs clock or reset with a wide variety of operating modes drive strength register type etc The mode setting for each pin is stored in non volatile memory PAC Designer Software User Manual 59 DESIGNING PLATFORM MANAGER Devices Design Entry FPGA Logic This block supplies additional logic capability that can be used to create additional supervisory and sequencing logic IP cores and user customized logic can also be added to this section of the device FTimer This block provides additional timers that can be defined by the user Utility IP This block allows you to configure additional logic modules like the Closed Loop Trim Fault Logger IP Using Cursor Feedback to Edit a Platform Manager Schematic When the cursor changes to a down arrow the block can be pushed into for editing Double clicking a block within the top level schematic allows you to navigate the schematic hierarchy To return to the top level place the cursor towards the top of the schematic when it changes to an up arrow double click When the cursor changes over a given block to the edit arrow with brackets then double clicking will invoke a secondary dialog box for text entry such as a table or parameter change The schematic blocks can also be edited through the use of the Edit gt Symbol command
58. MPLEMENTATION LogiBuilder Sequence Control Figure 29 Turning on 1 2V and 1 8V Supplies Using the Edit Output Properties Dialog Box Edit Output properties Outputs a Cancel J Change this output signal this instruction Pin Type Registered JK type flip flop Set Value Tumon Assert Tum off Deassert Exceptions r Comment Next click OK The Wait for Boolean instruction gets updated as shown in Figure 30 Figure 30 Wait for lt Boolean gt Instruction Getting Updated Edit Wait For Bool properties Instruction Preview Instruction Outputs Wait for Core_1 2_over_LTP AND IO_1 8_over_LTP Core_1V2_En Edit Boolean Expression Output Control Comment Turn on 1 2 and 1 8 supplies and wait for them to reach regulation Enter the comment and indicate whether this instruction is interruptible via exception condition and click OK The Step 3 in the Sequence Control section is modified as shown in Figure 31 PAC Designer Software User Manual 141 POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Sequence Control Figure 31 Sequence Control Section Showing the Updated Wait for lt Boolean gt Instruction PAC Designer Design1 Sequence and Supervisory Logic File Edit view Tools Options Window Help eas QaQlnas IF se te i as Be EA et i E f ro Sequencer Instruction Lowes Lim comen Comment SMO Step 0 Begin Star
59. OOD ispPAC POWR1220A4TS reset Core_1 2_En 0 IO_1 8_En 0 Reset_CPU 0 Start with all supplies turned off and Wait For 5 12ms using timer 1 Core_1 2_En 1 Turn 1 2 supply and wait For 5 12 ms Wait for 212 99ms using timer 2 10_1 8_En 1 Turns on 1 8 and waits For 200 ms Reset_CPU 1 Begin Shutdown Sequence Halt end of program Exception ID_ Boolean Expression Outputs Exception Handler lt end of exception table gt SMO Equation Supervisory Logic Equation Macrocell Configuration Comment lt end of supervisory logic table gt At step 1 the Sequence Controller is waiting for the AGOOD signal or waiting for the completion of the analog calibration While waiting 1 2V 1 8V supplies are turned off and the reset to CPU is active When the AGOOD signal becomes active the Sequence Controller jumps to step 2 As soon as the code enters step 2 the 1 2V supply is turned on and the 5ms timer Timer 1 is also turned on The Sequence Controller waits until the 5ms timer expires and jumps to step 3 At step 3 the 1 8V supply is turned on and Timer 2 200ms is started simultaneously The Sequence Controller waits at step 3 for 200ms until the timer 2 expires and jumps to step 4 At step 4 the CPU reset is released The Sequence Controller transitions through step 5 without any action and stops at step 6 Wait for lt Boolean gt with Timeout Application The Wait for Boolean instruction wa
60. OSFET Library The MOSFET library holds the model for the FETs You can modify the parameters for the FETs and these are stored in the library for later use 26 PAC Designer Software User Manual DESIGNING POWER MANAGER Devices Design Entry MOSFET Library IRLMS 2002 IRLR 7833 IRLR8103 PAC Designer Software User Manual 27 DESIGNING POWER MANAGER Devices Design Entry Simulation Output Plot Screen H OUT Simulator irtual Scope ry OK Cancel Print File Export Cursor 1 L Btn 0 Y Cursor 2 R Btn 0 v 10ms Div me 4 gt fu The results are plotted based on the parameters entered The actual data points can then be exported to a csv file to be used in a spreadsheet if needed The Plot window also supports cursor measurements and printing Using the PowerManager_I2CUtility The Power Manager 12C design utilities are opened from the Design Utilities dialog box A separate 1 C software utility is available for each I C capable Power Manager Device Design Utilities _ x HR ispPAC CLK_Freq_Synthesizer exe ispPAC CLK_Skew_Editor exe ispPAC E xtractFromPacFiles exe ispP4C10_Biquad exe ispPAC20_Biquad exe Power anager_1220_ 12C_Utility exe PowerM anager HYVOUT_Sim exe PowerManager WaveformEditor exe z m Description PAC Designer Designer Utilites 28 PAC Designer Software User Manual DESIGNING POWER MANAGER Devices Design Entry
61. PAC Designer Software User Manual zas LAT TICE SEMICONDUCTOR June 2014 Copyright Copyright 2014 Lattice Semiconductor Corporation This document may not in whole or part be copied photocopied reproduced translated or reduced to any electronic medium or machine readable form without prior written consent from Lattice Semiconductor Corporation Trademarks Lattice Semiconductor Corporation L Lattice Semiconductor Corporation logo L stylized L design Lattice design LSC CleanClock Custom Mobile Device DiePlus E CMOS ECP5 Extreme Performance FlashBAK FlexiClock flexiFLASH flexiMAC flexiPCS FreedomChip GAL GDX Generic Array Logic HDL Explorer iCE Dice iCE40 iCE65 iCEblink iCEcable iCEchip iCEcube iCEcube2 iCEman iCEprog iCEsab iCEsocket IPexpress ISP ispATE ispClock issDOWNLOAD ispGAL ispGDS ispGDX ispGDX2 ispGDXV isoGENERATOR ispJTAG ispLEVER ispLeverCORE ispLSI isoMACH ispPAC isp TRACY isp TURBO ispVIRTUAL MACHINE ispVM ispXP ispXPGA ispXPLD Lattice Diamond LatticeCORE LatticeEC LatticeECP LatticeECP DSP LatticeECP2 LatticeECP2M LatticeECP3 LatticeECP4 LatticeMico LatticeMico8 LatticeMico32 LatticeSC LatticeSCM LatticeXP LatticeXP2 MACH MachxO MachxXO2 MachXO3 MACO mobileFPGA ORCA PAC PAC Designer PAL Performance Analyst Platform Manager ProcessorPM PURESPEED Reveal SensorExtender SiliconBlue Silicon Forest Speedlocked Speed Loc
62. T1 0 HVOUT2 0 HVOUT3 0 HVOUT4 0 SMBA_ no SMO Step 3 Wait for RESET_ALL no Wait for r SMO Step 4 Wait for VM4_5V_OK LED_OUT6 0 LED_OUT yes Wait for5 SMO Step 5 Wait for 1048 58ms using timer 3 yes SMO Step 6 Wait for VM10_3V_OK LED_OUT6 1 LED_OUT yes Wait for3 m r Exception D Exception Handler If NOT R20SLIDER_MA lt nooutputss Starts at step 23 If a Slide Pot is out of range inturr If NOT RESET_ALL lt no outputs s Starts at step 2 Inturrupt on press of Reset Button lt end of exception tabl Comment 82 PAC Designer Software User Manual DESIGNING PLATFORM MANAGER Devices Functional Logic Simulation Figure 4 tive HDL C aDesi File Edit Search View Workspace Design Simulation Waveform Tools Window Help D x Brs x ry Ss SOMMER wT Ome B 5sg Pi e 100ns EA m a gt C ge Design Browse HH s S Blom QS w Q QQ Ql war we ue owl Met 444M Igy LPTM10_12107_DevKitDemol tf Name alue 7 480 1 2490 5 5 54 2503 2 us R AGOOD i Workspace work 1 design s work pow Fl JUU UU UU UU UU Uv UU UU UU Ue Lg Add New File L 6X Add New Library ao el ed 0 ee eri work library KD wo a OO O OOI Hih Multiple Unit if a ENA MODULE Sy All Verilog per MR eS i M Sroot Gis LPTM10_12107_DevKitDemol_cpld i m Hex2SegmentDecode HE LCD301_HexDisplay HEN PlatformDemo b LED OUTE LPTM10_12107_DevKitDemo1_tf g E l
63. Utility to Estimate FET Ramp Times AN6070 ispPAC POWR1220AT8 I2C Hardware Verification Utility AN6067 ispClock Application Notes Interfacing ispClock5600A with Reference Clock Oscillators AN6079 Using a Low Cost CMOS Oscillator as a Reference Clock for SERDES Applications AN6080 Power Manager Application Notes Adding More Hysteresis to ispPAC POWR1208 Analog Comparators AN6045 Controlling Power MOSFETs Using the isoPAC POWR604 AN6050 Controlling and Monitoring Power One Bricks and SIPs with Lattice Power Manager Devices AN6056 Extending the VMON Input Range of Power Platform Manager Devices AN6041 High side Current Sensing Techniques for Power Manager Devices AN6049 Implementing Power Supply Sequencers with Power Manager Devices and PAC Designer LogiBuilder AN6042 Interfacing Power Manager Devices with Modular DC to DC Converters AN6046 Interfacing the Trim Output of Power Manager II Devices to DC DC Converters AN6074 Monitoring and Controlling Negative Power Supplies with Power Manager Devices AN6051 Optimizing the Accuracy of isoPAC Power Manager Timers AN6076 PAG Designer Software User Manual 183 RECOMMENDED REFERENCES Power Supply Linear Sequencing Using the isoPAC POWR604 AN6053 Powering Up and Programming the ispPAC POWR1014 A AN6075 Powering Up and Programming the ispPAC POWR1220AT8 AN6073 Powering Up and Programming the ispPAC POWR607 AN6078 Powering Up and Programming t
64. VCO are within rated limits Frequency Synthesizer Calculates a device configuration that produces the desired output frequencies based on input and output frequency Skew Editor Provides a graphical interface for configuring the relative edge skews of device outputs Power Manager Platform Manager Design Utilities HVOUT Simulator Simulates the rise time of a power supply driven by an N Channel MOSFET and the HVOUT drivers of a Power Manager or Platform Manager device 12C Utility Drives 12C interfaces with the Lattice ispDownload Cable LogiBuilder Design Entry A tabular user interface for creating Power Manager PLD core power supply sequence controller logic based on conditional events and timer delays LogiBuilder produces ABEL HDL source files Functional Simulator A logic simulator for the digital logic targeted to the Power Manager or Platform Manager PLD core Waveform Editor A graphical editor for creating digital test patterns for the Power Manager or Platform Manager PLD core simulator The Waveform Editor produces Waveform Description Language WDL source files Starting PAC Designer The procedure for starting and exiting PAC Designer is the same as for other Windows based applications PAC Designer Software User Manual INTRODUCTION TO PAC DESIGNER Process Flow To start PAC Designer From the Windows Start menu button choose Programs gt Lattice PAC Designer gt PAC Designer
65. Waveform Editor Zooming In and Out Click the Zoom In button on the toolbar or the Zoom In button on the toolbar to activate the zoom cursor You can also choose View gt Zoom In and View gt Zoom Out to activate the zoom cursor Waveform Editor DESIGN Fie Edt View Object Tools Options Jump Help Place the zoom cursor over the time of interest and click to zoom in or out Repeated clicks will continue to zoom in or out To cancel the zoom in cursor right click 11 500 us 0 y KNIZ Starting the Waveform Editor In order to start the Waveform Editor from a project that has been saved an ABEL file must exist ABEL files are usually produced by compiling a LogiBuilder design ABEL files may also be generated by the user either in PAC Designer or using a stand alone text editor The Waveform Editor scans the ABEL file to determine the names of the input and output signals in use If the project has not been saved then an ABEL file can be selected manually after the editor has been started by choosing File gt Import ABEL Design To start the Waveform Editor Choose Tools gt Run Waveform Editor or Click the Waveform Editor button on the PLD Toolbar as shown below 42 PAC Designer Software User Manual DESIGNING POWER MANAGER DEVICES Automatic ABEL Import Waveform Editor PAC Designer Design PAC Sequence Controller Z File Edt View Tools Options Window Help Do AS 4 S QING
66. YS file is missing or has been moved 3 Registry settings are missing or incorrect Error See Help for Details Search for PACUTAG SYS Cause This is typically due to an incompletely installed driver Refer to Installing the PACUTAG SYS Device Driver WinNT 2000 for details You must restart your PC after PAC Designer installation to let the driver start Remedy Re boot Windows manually install the driver or re install PAC Designer Error Upload successful however PAC Designer needed to coerce some entries to be within legal range Explanation The device read into PAC Designer contains entries that would be illegal values within PAC Designer For example 3 bit fields that describe interconnect can define unused states and Gain values like 15 are also illegal Cause Typically the device was erased incorrectly by a means other than PAC Designer Error File could not be opened Explanation File was not found Cause File name misspelled or directory not present Error Can t Zoom in any farther Explanation PAC Designer limits the zoom factor Error Zoom All cannot zoom to fit given data instead it will zoom to limits of all possible data Explanation PAC Designer cannot zoom to fit if the Y axis does not change such as when the Phase does not change at all for the duration of the data set About UES Bits All ispPAC devices provide uncommitted spare bits in their E2 memory for custome
67. _Pump_Stre Output registered D flip flop EQ1 Charge_Pump_Stretch D TIMER4_TC Node registered D flip flop EQ2 DRV_12V_FET D NOTI_12V_Over_SOA Output registered D flip flop EQ3 TIMER1_GATE D Enable_HotSwap AND Output registered D flip flop EQ 4 DRV_3V3_FET D Brd_5V_OK AND NOT I Output registered D flip flop EQ5 DRV_SV_FET D Brd_12V_OKAND NOT I Output registered D flip flop EQ6 DRV_3V3_FET ar NOT Enable_HotSwap Output registered D flip flop EQ7 DRV_SV_FET ar NOT Enable_HotSwap Output registered D flip flop EQ8 DRV_12V_FET ar NOT Enable_HotSwap Output registered D flip flop lt end of supervisory logic table gt Retrigger 12V MOSFET Char Need to Keep MOSFET Gate Operates MOSFET in SOA Be If Supplies Dont Turn on wit 3 3V MOSFET starts Hotswa 5V MOSFET starts hotswap Turn off MOSFET in case of f Turn off SV MOSFET before Note the upper sections contain the details for state machine SMO This is because the SMO tab above the logic equations has been selected Clicking the SM1 tab would open a similar view for the SM1 state machine The MSM Manager dialog box is used to add or delete state machines To open the dialog box make sure the Sequence and Supervisory Logic window is open and the Sequencer Instructions table or the Exceptions table is active and then choose Edit gt Multiple State Machines Multiple state machines are supported fo
68. a dialog box that will let you change the mode to JK Error 23 Not used Error 24 IN_OUTs marked as Inputs cannot be used as outputs change mode in Pins Window PAC Designer Software User Manual 39 DESIGNING POWER MANAGER DEVICES Functional Logic Simulation Reason The operating mode of the pin has not been properly set to support an OUTPUT instruction Double click the IN_OUT pin in the schematic window or go to the PINS window and set up the pin as an output Functional Logic Simulation After the design has been entered compiled and fitted it can be simulated Functional simulation is used to verify the correctness of the design but does not simulate gate delays or analog transient analysis A stimulus file is used to tell the simulator how and when the input signals change state To simulate a Power Manager design use either of the following methods gt Simulating a Power Manager Design with Aldec Active HDL gt Simulating a Power Manager Design with Lattice Logic Simulator Simulating a Power Manager Design with Aldec Active HDL You can export digital elements timers and the PLD core of a Power Manager device to a Verilog or VHDL file and then use the exported HDL to perform functional simulation in Aldec Active HDL To export HDL 1 Make sure you have successfully compile the design in LogiBuilder If not choose Tools gt Compile LogiBuilder Design Note Do not delete any intermediate fi
69. age FET driver outputs 2 digital inputs vvvrvvvviy 5 digital pins that can be configured as inputs or open drain outputs v Low ICC power down mode PAC Designer Software User Manual 5 ISPPAC DEVICE SUMMARY Table 1 ispPAC Device Summary Continued Device ispPAC POWR1208 gt ispPAC POWR1208P 1 gt ispPAC gt POWR1220AT8 02 gt gt gt ispPAC POWR1014 02 gt ispPAC POWR1014A gt 02 k gt Applications Power supply monitoring Power supply start up shut down sequencing Power supply monitoring Power supply start up shut down sequencing Trim and margin with DACs 12C A D and control interface Power supply monitoring Power supply start up shut down sequencing Power supply monitoring Power supply start up shut down sequencing 12C A D and control interface Features vvrvrvivrvvrovrv vy iv vvvrvi yv Vv VK vvvrvivvy v 16 macrocell PLD 4 programmable timers On chip clock generator 12 programmable threshold comparators 4 high voltage FET driver outputs 4 open drain digital outputs 4 digital inputs 48 macrocell PLD 4 programmable timers On chip clock generator 24 programmable threshold comparators with window 12 VMON pins 4 high voltage FET driver outputs 16 open drain digital outputs 6 digital inputs 24 macrocell PLD 4 programmable timers On chip clock generator 20 programmable threshold comparators with window 10 VMON pins
70. ailable only for the ispPAC CLK5600 and ispPAC CLK5400D families skew control adjustments on ispPAC CLK5510 and ispPAC CLK5520 are made through the skew manager utility To use the ispClock Skew Editor 1 In the ispClock Skew Editor Window move the mouse over the waveform edge you wish to move Holding the left mouse button down drag the edge to the position you want it Release the left button when done Repeat for other waveforms Waveforms may be inverted by selecting the Invert options to the right of the waveform display Click Write to Schematic to transfer skew Settings to PAC Designer 4 When you finish click Exit You may read a configuration from PAC Designer by clicking the Read from Schematic button Importing Data to a PAC Designer Schematic You can import several types of data in several formats to a PAC Designer schematic To import data to a PAC Designer schematic 1 Choose File gt Import The Import Dialog Box opens Under Import What select a data type The available data types listed in this box are device dependent Under In the format select the desired import file format Under Import From click Browse to navigate to the file that you want to import into your PAC Designer schematic Click OK 104 PAC Designer Software User Manual DESIGNING ISPCLOCK DEVICES Procedures Exporting Data from a PAC Designer Schematic You can export several types of data in sever
71. al input can be swapped with any other digital input PAC Designer Software User Manual 21 DESIGNING POWER MANAGER DEVICES Design Entry Device Pin Swapping High Voltage Output Settings i High Yoltage Output Settings pwouve vourz pos z voor vo 5wa wv o 125u m iou F jv 125uA Z How F wo 125w iou gt In this dialog box the HVOUT pins can be swapped Simply use the pull down menus and make sure there are no duplicated pin names Any HVOUT can be swapped with any other HVOUT 22 PAC Designer Software User Manual DESIGNING POWER MANAGER DEVICES Design Entry Device Pin Swapping Logic Outputs x Pin Name User Defined Name Digital Control From fours Enss ooo PLD 12C Register Cancel _ jure Env o PLD C 12C Register ourz CPU_Resetb PLD 120 Register ours x Brown _OutIntb PLD f 12C Register purs x jours PLD I2C Register juro journo PLD 12C Register jomi x jomi ts PLD C 12C Register punz four2 PLD 12C Register juns founs PLD C 12C Register jums founs O PLD 12C Register uns fours PLD 12C Register june foume PLD 12C Register pun x jour ts PLD 12C Register juns x jouis PLD 12C Register puns x jons ooo PLD I2C Register jouta fouro O PLD C 12C Register In this dialog box the OUT pins can be
72. al Logic Simulation 2 Configure the CPLD and FPGA logic according to the PAC Designer design flows 3 Open the CPLD or FPGA logic sessions or open both of them by double clicking the logic block in the main design window 4 From the LogiBuilder window choose Tools gt Create Stimulus Compile LogiBuilder Design Run Waveform Editor Run Simulator Create Stimulus Design Utilities Download All uence and Supervisory Logic CPLD Upload Verify Read IDCODE T2 0 HVOUT3 0 HVOUT4 0 SMBA_ Auto Calibrate j ep ait Tor K SMO Step 5 Wait for 1048 58ms using timer 3 SMO Step 6 Wait for VML0_3V_OK 4 m Exception ID Boolean Expression Outputs Exception Handler E0 If NOT R20SLIDER_MA lt no outputs s Starts at step 23 E1 E NAT RESET AlI dnn ntnite e Starte at ctan PAC Designer opens the Connection between CPLD and FPGA dialog box 5 Select any connections to be added that will link from the CPLD section to the FPGA section of the Platform Manager and then click OK Connections are optional but they can only be added to the stimulus file by using this dialog box 6 Choose Tools gt Run Simulator gt Aldec Active HDL Simulator At this point PAC Designer automatically creates all the files and directories required to support the Aldec simulator It also opens the initial timing simulation 7 After configuring the display remember to save the c
73. al formats from a PAC Designer schematic To export data from a PAC Designer schematic 1 Choose File gt Export The Export Dialog Box opens 2 Under Export What select a data type The available data types listed in this box are device dependent Under In this format select the desired export file format 4 If you want to export the data to a file select File and then click Browse to navigate to the file to which you want to export data 5 If you want to export the data to your computers Clipboard memory select Clipboard 6 Click OK PAC Designer Software User Manual 105 DESIGNING ISPCLOCK DEVICES Procedures 106 PAC Designer Software User Manual SHEILATTICE Chapter 6 E SEMICONDUCTOR Device Programming A defining feature of the ispPAC product family is in system programmability which allows devices to be programmed in circuit on the application board This provides an alternative to traditional methods such as pre assembly machine programming PAC Designer is capable of all programming requirements when properly connected to an in circuit device The hardware programming interface is the IEEE 1149 1 1990 JTAG test access port TAP To program a device no special programming voltages or conditions must exist other than a standard 5V power connection and access to a four wire serial JTAG interface All programming operations require a PC properly connected to a powered circuit contai
74. alue above which the resistor is treated as an open circuit This field can be used to force the algorithm to minimize the number of resistors to the equivalent circuit To do that first calculate the resistors using the default values Change the Open External Resistor s Threshold field to a value slightly higher than the series PAC Designer Software User Manual 179 POWER MANAGER EXAMPLE IMPLEMENTATION Creating a DC DC Converter Library Entry resistor value and click OK The software automatically calculates the new resistors and the associated DAC values Vbpz Selection Usually it is best left as auto In some cases by forcing the Vbpz values to one of the other voltages 0 6V 0 8V 1V or 1 25V the number of resistors can be reduced After calculating the resistor values for all Trim Cells the software automatically saves all the values in to the PAC file To generate a report file of all resistors connected to all Trim Cells do the following 1 Choose File gt Export to open the Export dialog box Figure 71 Figure 71 Generating a Report File for Margin and Trim Export What Margin Trim Sa In this format Formatted Text Export To File SERS Clipboard 2 Under Export What select Margin Trim 3 Click Browse to select the export file and click OK The output text file format is as shown below MarginTrimCell Idx 0 TrimCellNumberl TargetVoutSP1l 1 200 TargetVoutSP2
75. alues Other than that this is essentially a marker step and does not perform any other useful task This step can be deleted gt Wait for AGOOD This is one of the Wait for instruction types Immediately after power on the PWOR1220ATS8 initiates analog calibration process After the completion the analog section activates the AGOOD signal internally All comparator outputs are valid only after the AGOOD signal is at logic HIGH In this step the Sequence Controller waits for the completion of analog calibration before proceeding with the next steps gt Begin Shut Down Sequence This step performs two functions marker step indicating that the power shut down sequence is found after that step and when you double click this step it automatically allows insertion of an instruction into that step and the shut down sequence marker moves to the next step For example in Figure 20 the Begin Shut Down sequence marker is at step 2 By double clicking step 2 you can insert an instruction at step 2 and the Begin Shut Down sequence marker moves one step down to step 3 This marker can be deleted to reduce the number of steps Halt End of Program This instruction is a special case of the Go to instruction where the sequence jumps to the same step as that of the instruction In this case the Halt instruction is at step 3 When the Sequence Control enters this step it stays at this step for ever However if the Interruptible flag was se
76. ank 0 to Bank 1 are skewed using Time Skew Bloc Outptus are controlled using the OEw signal routed to User 3 pin 2C is not enabled Open File Close 120 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION Configuring Analog Inputs 2 Select POWR1220AT8 2_cPCIl_HS Seq RG_Sup PAC and click Open File The software opens the schematic page shown below in Figure 8 Figure 8 CompactPCI Design in POWR1220AT8 8 File Edit Yiew Tools Options Window Help kb Haaa Hf Jeol S EF x Ibs oy Configuring Analog Inputs Analog inputs of the Power Manager device can be accessed by clicking the Analog Inputs block shown at the top left corner of Figure 8 and the software will open the schematic interface shown in Figure 9 PAC Designer Software User Manual 121 POWER MANAGER EXAMPLE IMPLEMENTATION Configuring Analog Inputs Figure 9 Analog Inputs Schematic Interface x Eg FM Fie Edit View Tools Options Window Help D LEERE Ye sD S eas y Ei i a rae 1 Double click to go back to the main schematic page This is the next level in the hierarchy that shows the comparators and the associated voltage thresholds for each analog input The outputs of the comparator are connected to window logic and then to a glitch filter The output of the glitch filter is connected to the on chip CPLD The power management algorithm is implemented in the CPLD T
77. ar to simulate the design from ABEL Note The default stimulus file should be edited to reflect the input signals and basic design Entering Supervisory Equations You enter supervisory equations for a Power Manager device from the Supervisory Logic panel of the LogiBuilder Sequence and Supervisory Logic window Supervisory equations are combinatorial or registered logic independent of sequence controller logic To enter supervisory equations 1 From the top level schematic window configure the user defined inputs and outputs set the VMON trip points and configure the clock and timer settings 2 Double click the Sequence Controller block to display the Sequence and Supervisory Logic window 3 Choose View gt Pins definitions or click the pins button on the toolbar to display the Pin Definitions Window to configure the logic level of the input pins and the type and power up state of the output pins 4 Return to the LogiBuilder Sequence and Supervisory Logic window Double click on the lt end of supervisory logic table gt marker to insert an equation place holder 6 Double click on the equation place holder to display the Supervisory Logic Equation Entry Dialog Box to edit the equation settings 7 Click OK Note LogiBuilder sequencing exceptions and supervisory equations are combined together during the compile process LogiBuilder Error Messages Error 0 Instruction at step zero cannot be a WaitFo
78. arning 12 Not used Warning 13 Not used Error 14 Supervisory Logic equation has empty Boolean Expression Reason BoolExpr not present You can close edits without supplying a BoolExpr the error will be flagged when the compile is attempted Warning 15 Supervisory Logic equations assign same output more than once Reason More than one supervisory logic equation has been written for an output pin The compiler will OR these equations together PAC Designer Software User Manual 77 DESIGNING PLATFORM MANAGER DEVICES LogiBuilder Error 16 This type of assignment is not supported by current pin configuration Reason LogiBuilder checks logic assignments in the Supervisory window Errors are trapped by LogiBuilder so that generated ABEL code is always correct See the Type checked assignments table page 4 Error 17 Output cannot be set Asynchronously by an Supervisory equation unless assigned by an instruction Reason The ABEL language used to implement the PLD requires this Error 18 State variable must be D type FF Use Pins window to change type Reason This error typically occurs if you choose to re define the standard state variable allocation and use OUTs which are defined as JK Simply change the type of the OUT from JK to D using the pins window Error 19 State variable cannot be used as an output Reason This error typically occurs if you choose to re define the standard state variable allocation and
79. been saved an ABEL file must be manually selected To do this select File gt Import ABEL Design This will launch a file browser dialog box Select the desired ABEL file and click the Open button Creating and Editing Waveforms You can edit and modify waveforms with the Edit Waveform dialog box The contents of the dialog box will change based on which waveform is selected This dialog box may be launched by double clicking a signal in the Waveform Editor or by choosing Edit gt Waveforms and then double clicking the signal name in the Waveform Editor Dialog Box The Edit Waveform dialog box is shown below 86 PAC Designer Software User Manual DESIGNING PLATFORM MANAGER Devices Waveform Editor Stimulus Edit MON2_4 Waveform Re Xi Waveform Name VMON2 A m Initial State t1 Index Level Duration Total Time o Cancel HIGH LOW Delete Segment __Add Segment _ __Add Segment _ Segment Duration 0 0 us _Change Segment Segment When the dialog box is first opened no parts of the waveform for its signal are defined The waveform is built by appending segments to the end of the list The state of the first segment is defined by the options under Initial State To create the first segment set the option as appropriate type in the duration of this initial state in the Segment Duration box and click Add Segment The state of subsequent segments is always the opposite of the state of the
80. c You can export several types of data in several formats from a PAC Designer schematic For Platform Manager devices you can also export digital elements timers and the PLD core to a Verilog or VHDL file for functional simulation See Simulating a Platform Manager Design with Aldec Active HDL for details To export data from a PAC Designer schematic 1 Choose File gt Export The Export Dialog Box opens Under Export What select a data type The available data types listed in this box are device dependent Under In this format select the desired export file format If you want to export the data to a file select File and then click Browse to navigate to the file to which you want to export data If you want to export the data to your computers Clipboard memory select Clipboard Click OK Creating and Editing an ABEL Design You can create and edit an ABEL design for a Platform Manager device To create and edit an ABEL design 1 From the top level schematic window configure the user defined inputs and outputs set the VMON trip points and configure the clock and timer settings Double click the CPLD Logic block to display the Sequence and Supervisory Logic PLD Window Choose View gt Pins definitions or click the pins button on the toolbar to display the Logic I O Assignment Dialog Box to configure the logic level of the input pins and the type and power up state of the output pins 68
81. c such as the FET HVOUT block resistors and capacitor This will open up dialog boxes to change the circuit parameters Main Screen for the FET Simulator H OUT Simulator Close _ simuste imulate Print Double clicking the circuit elements within the schematic will bring up dialog boxes for each parameter Once you have configured the set up hit the Simulate button and the results will be plotted The results can also be exported to a coma separated file to be used in a spreadsheet for other analysis or comparing different ramp rates with different FETs Dialog Boxes for the Simulator The dialog boxes for the HVOUT Simulator allow you to change the circuit parameters HYOUT oltage x Enter the HYOUT Charge Pump Output Voltage fi 0 Volts 8 to 12 Cancel 64 PAC Designer Software User Manual DESIGNING PLATFORM MANAGER DEVICES Design Entry HYOUT Current Supply Yoltage xi a MOSFET Library The MOSFET library holds the model for the FETs You can modify the parameters for the FETs and these are stored in the library for later use PAC Designer Software User Manual 65 DESIGNING PLATFORM MANAGER DEVICES Design Entry MOSFET Library Add New a IR LMS 2002 IRLA7833 IRLR8103V 66 PAC Designer Software User Manual DESIGNING PLATFORM MANAGER Devices Design Entry Simulation Output Plot Screen H OUT Simulator irtual Scope ry
82. changes to these materials specifications or information or to the products described herein at any time without notice LSC makes no commitment to update this documentation LSC reserves the right to discontinue any product or service without notice and assumes no obligation to correct any errors contained herein or to advise any user of this document of any correction if such be made LSC recommends its customers obtain the latest version of the relevant information to establish before ordering that the information being relied upon is current PAC Designer Software User Manual Type Conventions Used in This Document Convention Meaning or Use Bold lt ltalic gt Ctrl L Courier Items in the user interface that you select or click Text that you type into the user interface Variables in commands code syntax and path names Press the two keys at the same time Code examples Messages reports and prompts from the software Omitted material in a line of code Omitted lines in code and report examples Optional items in syntax descriptions In bus specifications the brackets are required Grouped items in syntax descriptions Repeatable items in syntax descriptions A choice between items in syntax descriptions PAC Designer Software User Manual PAC Designer Software User Manual me LATTICE MsEMICONDUCTOR Chapter 1 Chapter 2 Chapter 3 Contents Introduction to PAC Designer 1 Ge
83. cle to cycle period and phase jitter Programmable input and output termination Supports differential standards LVPECL LVDS MLVDS HSTL SSTL Independently programmable skew PAC Designer Software User Manual ISPPAC DEVICE SUMMARY Table 1 ispPAC Device Summary Continued Device ispPAC CLK5410D gt gt h Platform Manager LPTM10 1247 amp LPTM10 12107 vvrvrvrvrvvyvy V Applications Differential zero delay universal fan out buffer 10 differential outputs Frequency multiplication amp division Zero delay buffer Hot swap controller Power supply OR ing Voltage monitoring Sequence control Trimming amp margining Power on configuration Reset distribution Fault logging System interface Features vv v vvvveyv vvvrovvy 50MHz to 400MHz Low cycle to cycle period and phase jitter Programmable input and output termination Supports differential standards LVPECL LVDS MLVDS HSTL SSTL Independently programmable skew 48 macrocell PLD 4 programmable timers On chip clock generator 24 programmable threshold comparators with window 12 VMON pins 4 high voltage FET driver outputs 12 open drain digital outputs 4 digital inputs 8 Margin Trim outputs 91 digital I O s 640 LUT FPGA 10 PAC Designer Software User Manual Saas LAT TICE E SEMICONDUCTOR Design Entry Chapter 3 Designing Power Manager Devices This section illustrates Power Manager de
84. comparators feed into the CPLD of the Sequencer Block Digital Inputs The Digital Inputs are general purpose inputs for the logic The voltage thresholds can be set for lower voltage logic using the VDDinp pin Logic Outputs The Logic Outputs are open drain outputs that come from the CPLD General Purpose I O Pins isoPAC POWR607 only Five pins on the device can be individually configured to behave as either digital inputs or open drain logic outputs The mode setting for each pin is stored in non volatile memory When one of these pins is used as an input the open drain output circuit is disabled On the other hand when one of these pins is used as an output the feedback for that pin s macrocell is taken from the output routing pool rather than the pin High Voltage Outputs The HVOUT pins can be used as FET gate drivers and have a programmable drive levels for both voltage and current The HVOUTs can also be set independently to be used as digital outputs in open drain mode Timer and Oscillator The Timer and Oscillator functions are programmable The hardware timers can be programmed for different time delays Clock and Timers ispPAC POWR607 only Four programmable timers can be set independently to a wide variety of durations in the range of 32s to 1 966s PAC Designer Software User Manual 17 DESIGNING POWER MANAGER Devices Design Entry Sequence Controller The Sequence Controller Block is the section suppo
85. comparators with window 10 VMON pins 2 high voltage FET driver outputs 12 open drain digital outputs 4 digital inputs Closed loop trim control Static trim settings 12C interface Differential VMON sense lines 10 bit ADC 8 bit trim DACs 10 320 MHz output Low cycle to cycle and period jitter Programmable input and output termination Supports LVCMOS LVTTL LVPECL LVDS HSTL and SSTL standards E2CMOS memory stores up to four user selectable profiles Independently programmable skew and slew rate control on each output 10 320MHz output Low cycle to cycle and period jitter Programmable input and output termination Supports LVCMOS LVTTL LVPECL LVDS HSTL and SSTL standards E2CMOS memory stores up to four user selectable profiles Independently programmable skew and slew rate control on each output PAC Designer Software User Manual ISPPAC DEVICE SUMMARY Table 1 ispPAC Device Summary Continued Device ispPAC CLK5610A gt ispPAC CLK5620A gt ispPAC CLK5304S gt ispPAC CLK5308S gt ispPAC CLK5312S gt Applications Enhanced zero delay clock generator Frequency multiplication amp division Zero delay buffer Zero delay universal fan out buffer 4 single ended outputs Frequency multiplication amp division Zero delay buffer Zero delay universal fan out buffer 8 single ended outputs Frequency multiplication amp division Zero delay buffer Zero dela
86. d Timer TC signal In this case the timer TC signal generates a 4 microsecond pulse train separated by the time delay programmed into the Timer in this case it is 2 seconds The connection and the output waveforms are shown in Figure 52 160 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Supervisory Logic Figure 52 Generating a Train of Pulses 4us Wide and Separated by 2 Seconds Programmable Timer Timer Gate 2 Sec Timer TC Timer Gate 2 Sec Timer TC 4 Hes Ten Second Timer Implementation Using the Supervisory Logic Section Refer to Figure 53 To insert a new supervisory equation EQO double click lt end of supervisory logic table gt or place the cursor on the last line in the Supervisory Logic window and press the Insert key Figure 53 Supervisory Logic Section in LogiBuilder PAC Designer 2 Minute Timer PAC Sequence and Supervisory Logic Eile Edit Yiew Tools Options Window Help D gig sep Pis A Ga SMO Step 0 Begin Startup Sequence SMO Step 1 Wait for AGOOD SMO Step 2 Begin Shutdown Sequence SMM Sten 3 Halt fend nf nronram Equation Supervisory Logic Equation Macrocell Configuration Comment EQO HYOUT1 lt booleanExpr gt Output registered JK flip flop lt end of supervisory logic table gt Supervisory Logic section of the LogiBuilder lt Loading data into list view The supervisory equation representation is divid
87. different inputs and perform different functions depending on the inputs For example the Sequence Controller can monitor supply voltages and branch to shut down routine and poll for an input condition and jump back to monitor voltages The If Then Else instruction can be configured using the dialog box shown in Figure 39 148 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Sequence Control Figure 39 Conditional Branch IffhenElse Dialog Box Conditional branch IfThenElse Instruction Preview Instruction Outputs IF Core_1V2_OK AND IO_1V8_OK Then Goto 4 Else Goto 6 Edit Boolean Expression Output Control Then Goto v with Outputs Else Goto Step 6 v with Outputs Instruction is interruptible by an exception Comment If the supplies are OK jump to check the reset input If the suppleis are Faulty jump to shut down The Boolean expression is set by clicking Edit Boolean Expression as shown in the Figure 27 In this case the sequence engine is monitoring for the core voltage of 1 2V and the IO supply of 1 8V If either supply is faulty the sequence control jumps to the shutdown section of the sequence control program step 6 Otherwise it jumps to the next step step 4 It is possible to change any output during the branch transition by clicking with Outputs associated with the Then and the Else branches The following sequence control program Figure 40 uses two I
88. e Analog Inputs CPLD inputs CPLD Open DrainOutputs High Voltage Outputs Margin Trim Misc CPLD Signals ISU oc Reaiter charge Pump Output PLD Open Drain Logic Ou N RC Register Charge Pump Output Charge Pump Output Device Pin Swapping CPLD Open Drain Outputs In the CPLD Open Drain Outputs Tab of the Logic I O Assignment dialog box the OUT pins can be swapped Simply use the pull down menus and make 62 PAC Designer Software User Manual DESIGNING PLATFORM MANAGER Devices Design Entry sure there are no duplicated pin names Any OUT pin can be swapped with any other OUT pin Logic O Assignment CPLD Node Analog Inputs CPLD Inputs CPLD Open Drain Outpus High Voltage Outputs Margin Trim Misc CPLD Signals aje Pin Name User Defined Name Digital Control From Reset Level Output Type 2 OUT10 PLD Don t care Registered K type flip OUT OUT11 PLD Don tcare Registered JK type fip OUT OUT12 PLD Don t care Registered Jk type fip OUT OUT13 PLD Don t care Registered JK type fip OUT ouT14 PLD Don t care Registered K type fip OUT OUTI5 PLD Don t care Registered K type fip OUT OUTI6 PLD Don t care Registered K type fip OUT OUT17 PLD Don t care Registered Jk type fip i i i i OUT OUT18 PLD Don t care Registered Jk type fip OUT OUT19 PLD Don t care Registered Jk type fip QUT20 PLD Don t care Registered Jk type fip OUTS PLD Don t care Reg
89. e Location box 6 Click OK to close the Module Definition dialog box Once the module has been successfully defined using the above steps it must be enabled so that it is added to the HDL file To enable the module choose Options gt Import Sub Module gt Enable Sub Module The new code will be added to the HDL file upon successful compilation The added module can be removed from the code To remove the added module choose Options gt Import Sub Module gt Disable Sub Module and then recompile the design to remove the code LogiBuilder Error Messages Error 0 Instruction at step zero cannot be a WaitFor_Timer or Start_Timer instruction Reason Timer_Gate signal must have a low level then a high level for timer to operate To do this for an instruction at step N the instruction at step N 1 must set Timer_Gate 0 then Instruction N can set Timer_Gate 1 Therefore N cannot be zero PAC Designer Software User Manual 75 DESIGNING PLATFORM MANAGER DEVICES LogiBuilder Discussion With the default LogiBuilder program template you cannot get this error because Begin Startup Sequence instruction is always present But users who choose to optimize code by removing the Begin Startup Sequence instruction will be susceptible to this error Error 1 WaitFor_Timer or Start_Timer instruction cannot be branch target of a Goto or IfThenElse Error 2 WaitForTimer instruction cannot be branch target of an
90. e state of inputs with an additional timeout feature If lt Boolean expression gt is TRUE the next step in the sequence will be lt step x gt otherwise if Timer lt n gt has expired the next step will be lt step y gt If lt Boolean expression gt is FALSE and Timer lt n gt has not expired then the next step will be lt step z gt This instruction only checks the values of lt Boolean expression gt and Timer lt n gt it does not start or reset the timer GOTO lt step x gt The GOTO instruction forces the sequence to jump to lt step x gt Start Timer This instruction starts the selected timer The status of the timer must be checked using another instruction or combinational logic Stop Timer This instruction stops and resets the selected timer NOP The NOP instruction does not affect any of the outputs or the sequence of execution It is effectively a single cycle delay HALT The HALT instruction stops execution of the sequence PAC Designer Software User Manual 71 DESIGNING PLATFORM MANAGER DEVICES LogiBuilder BEGIN SHUTDOWN SEQUENCE The BEGIN SHUTDOWN SEQUENCE instruction signals to LogiBuilder that any instructions past this point will not be interrupted by jumps specified in exceptions This feature allows code used for handling exceptions not to be interfered with by other exceptions that may occur This instruction may be deleted from a sequence but not inserted Designing Control Sequences with
91. e DC DC converters is set by connecting a resistor from its trim pin to its Vout terminal The value of the resistor determines the output voltage d The Discrete implementation represents a class of DC DC converters whose output voltage is determined by two resistors one between the Vout terminal to the feedback node and the second between the feedback node and the ground Refer to the DC DC converter datasheet to select the type of DC DC converter and click Next PAC Designer Software User Manual 171 POWER MANAGER EXAMPLE IMPLEMENTATION Creating a DC DC Converter Library Entry 3 Configure the DC DC converter in the subsequent dialog boxes The below sub steps describe how to use the dialog boxes to configure different types of DC DC converter a Fixed Voltage DC DC Converter with Trim up and Trim down Supply Figure 63 shows the dialog box that appears when DC DC Converter with Trim up amp Trim Down Supply is selected in Figure 62 This type of DC DC converter is usually a module and is designed to provide a fixed voltage Figure 63 Creating Library Element for a Fixed Voltage DC DC Converter DC DC Converter Datasheet Example Configurations ai DC DC Example Converter 3 Example 1 amp 2 Nominal Output Voltage With Trim Resistor Open fol Yy Values from the DC DC Converter Datasheet Example Configuration Equations Example1 Example2 Example3 R to GND R to GND R to Yout Output Voltage with Trim a a
92. e are 16 bits accessible to you The bits are non volatile Margin and Trim Block isoPAC POWR1220AT8 only The Margin Trim Block sets up all the modes for the trim circuitry to adjust DC DC power supplies It allows control of all the DAC settings and modes for margining and trimming 12C Control Block isoPAC POWR1014A only This block allows you to set several modes for the device pins and the I2C address Using Cursor Feedback to Edit a Power Manager Schematic When the cursor changes to a down arrow the block can be pushed into for editing Double clicking a block within the top level schematic allows you to navigate the schematic hierarchy To return to the top level place the cursor towards the top of the schematic when it changes to an up arrow double Click PAC Designer Software User Manual DESIGNING POWER MANAGER Devices Design Entry When the cursor changes over a given block to the edit arrow with brackets then double clicking will invoke a secondary dialog box for text entry such as a table or parameter change y The schematic blocks can also be edited through the use of the Edit gt Symbol command Selecting an item from the dialog box will transfer you to the appropriate schematic or window for editing Swapping Device Pins PAC Designer allows you to swap external physical pins while the design is being worked on and still being edited This can be done to correct or simplify board
93. e desired supply type is changed Reserved Words None of these words should be used as a pin name in PAC Designer Async_reset Case Clk_in Declarations Device Else Enable End Endcase Equations External Flag Functional_block Fuses Goto If In Interface Istype Library Macro Module Node Options Pin Pld_clk Property Reset State State_diagram State_register PAC Designer Software User Manual 13 DESIGNING POWER MANAGER DEVICES Design Entry Sync_reset Tmr_clk Test_vectors Then Title Trace Truth_table When With Invalid Characters Do not use any of the following characters in a name 1 amp ta gt lt 25 gt Design Examples The PAC Designer software provides a library of pre configured designs for example use Choose File gt Design Examples The Design Examples Dialog Box contains a list of pre configured designs When you click a design in the list a description of the design appears on the right side of the dialog box You can open the schematic and use it as is or you can edit the schematic Design Mapping Table The following table shows mapping details for importing an ispPAC POWR1014 A design into an ispPAC POWR1220AT8 device Table 2 Design Mapping Source Device ispPAC POWR1014 A VMON 1 to 10 pins Thresholds coarse and fine settings Pin names Logical names Glitch filter setting per pin Window comparator setting Input 1 to 4 pins Pi
94. e sequence will be lt step x gt otherwise if Timer lt n gt has expired the next step will be lt step y gt If lt Boolean expression gt is FALSE and Timer lt n gt has not expired then the next step will be lt step z gt This instruction only checks the values of lt Boolean expression gt and Timer lt n gt it does not start or reset the timer GOTO lt step x gt The GOTO instruction forces the sequence to jump to lt step x gt Start Timer This instruction starts the selected timer The status of the timer must be checked using another instruction or combinational logic Stop Timer This instruction stops and resets the selected timer NOP The NOP instruction does not affect any of the outputs or the sequence of execution It is effectively a single cycle delay HALT The HALT instruction stops execution of the sequence BEGIN SHUTDOWN SEQUENCE The BEGIN SHUTDOWN SEQUENCE instruction signals to LogiBuilder that any instructions past this point will not be interrupted by jumps specified in exceptions This feature allows code used for handling exceptions not to be interfered with by other exceptions that may occur This instruction may be deleted from a sequence but not inserted PAC Designer Software User Manual 33 DESIGNING POWER MANAGER Devices LogiBuilder Designing Control Sequences With LogiBuilder The PAC Designer LogiBuilder Sequence Controller window allows you to create control sequences and de
95. e state of the first segment is defined by the options under Initial State To 166 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION Implementing Multiple State Machines create the first segment set the option as appropriate type in the duration of this initial state in the Segment Duration box and click Add Segment The state of the subsequent segments is always the opposite of the state of the last segment on the list For instance if the initial segment t1 was defined to be low then t2 will be high t3 will be low and so on Each new segment is created by entering its duration into the Segment Duration box and clicking Add Segment Any segment listed in the Edit Waveform dialog box may be deleted by selecting it from the list and clicking Delete Segment When this operation is performed the states of all subsequent waveform segments will invert The duration of any segment listed in the Edit Waveform dialog box may be changed To do this select the segment and enter its desired duration in the Segment Duration box Then click Change Segment When you finish making changes to the segment list click OK to commit the changes to the waveform Implementing Multiple State Machines The LogiBuilder supports multiple state machines for power up sequence and control for some Power Manager devices The state machines are defined separately but can interact through nodes or common logic functions Each sta
96. ed into 4 parts the equation number automatically generated the logic equation a Boolean expression assigned to an output pin or node type of assignment Combinatorial D type T Type Asynchronous Preset and Asynchronous Reset and a comment line for documentation PAC Designer Software User Manual 161 POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Supervisory Logic To enter the actual supervisory logic equation double click the newly introduced supervisory equation to open the dialog box shown in Figure 54 Figure 54 Supervisory Logic Equation Entry Dialog Box Supervisory Logic Equation Entry Output Macrocell TIMER1_GATE Output registered D flip flop Type of assignment OUTs D lt BoolExpr gt D input Boolean Expression NOT TIMER1_TC Comment Generating a pulse train of dus wide seprate To enter a supervisory logic equation select the output that should be controlled by the logic equation Here the output selected is the Timer_Gate of timer 1 To generate a pulse train that is 4us wide and spaces 2 seconds apart the Timer_Gate1 should be connected to its Timer_TC through an inverter Figure 52 So select type of assignment as D type Next click the Edit button to open the Boolean Expression Editor shown in Figure 26 Here the assigned Boolean expression is Not Timer1_TC Click OK The LogiBuilder window gets updated as shown in Figure 55 162 PAC Designer Software Us
97. edcount _ LED_OUT8 mnan ened SS ee 4 ralaj B Fies Structure amp Resources amp ptm10 dem platformde Ellptm10_121 Et Iptm10 1 2 2 KERNEL Kernel process initialization done Allocation Simulator allocated 2633 kB elbread 1025 elab2 1262 kernel 345 sdf 0 jo 11 16 AM Wednesday June 15 2011 Simulation has been initialized Selected Top Level LPTM10 12107 DevKitDemoi tf LPTM10_ 12107 DevKitDemo1 tf 5 add wave a run 100 ms a KERNEL stopped at time 100 ms gt amp Console To export HDL 1 Make sure you have successfully compile the design in LogiBuilder If not choose Tools gt Compile LogiBuilder Design Note Do not delete any intermediate files generated during the compiling process 2 In PAC Designer or LogiBuilder choose File gt Export The Export Dialog Box opens Under Export What select VHDL File or Verilog File 4 Under Export To select File and then click Browse to specify the file name and directory By default the system uses the vho extension name for VHDL file and vlg for Verilog file You can also change them to v and vhd as you like 5 Click OK The Verilog or VHDL file in gate level is generated in the specified directory PAC Designer Software User Manual 83 DESIGNING PLATFORM MANAGER DEVICES Automatic ABEL Import Waveform Editor
98. een stored elsewhere The Trim Configuration dialog box provides the ability to re do the trim calculations with a minimum amount of parameter re entry Target voltages need to be re entered only if the desired supply type is changed PAC Designer Software User Manual 55 DESIGNING PLATFORM MANAGER Devices Design Entry Reserved Words None of these words should be used as a pin name in PAC Designer Async_reset Case Clk_in Declarations Device Else Enable End Endcase Equations External Flag Functional_ block Fuses Goto If In Interface Istype Library Macro Module Node Options Pin Pld_clk Property Reset State State_diagram State_register Sync_reset Tmr_clk Test_vectors Then Title Trace Truth_table When With Invalid Characters Do not use any of the following characters in a name 1 amp ta gt lt 25 gt 56 PAC Designer Software User Manual DESIGNING PLATFORM MANAGER Devices Design Entry Design Examples The PAC Designer software provides a library of pre configured designs for example use Choose File gt Design Examples The Design Examples Dialog Box contains a list of pre configured designs When you click a design in the list a description of the design appears on the right side of the dialog box You can open the schematic and use it as is or you can edit the schematic Procedures This section provides step by step procedures for completing ta
99. efined Name Digital Control From a e E ee ours PLD C 12C Register Cancel joure Envib PLD 12C Register fout7 EN V2b PLD 12C Register outs JENy3b oO PLD 12C Register outs x local PCLRstb PLD C 12C Register ouro aetb PLD 12C Register ouri Brown Ow N PLD 12C Register jouT12 EPU_RestN PLD 12C Register ums Drv VEE FET PLD 12C Register jouis ooms PLD 12C Register fouTis oons oo PLD 12C Register ouie foume PLD 12C Register ouri fouTi7 PLD 12C Register ours jouTig8 ooo PLD 12C Register ours oumas o PLD 12C Register ourz oura PLD 12C Register With this dialog box Figure 14 the output pin location its logical name and the signal source can be configured In a POWR1220AT8 device there are 20 digital open drain outputs Pin Name This is the datasheet pin name Use this field to associate the logical pin name with any of the logical outputs gt User Defined Name This is the logical name used by the power management algorithm to toggle the corresponding output pin Any user defined name can be associated with any logical pin through the use of the Pin Name field gt Digital Control From The radio buttons determine whether the PLD output or a register bit controlled by 12C interface drives the physical pin If an output is driven by the I2C register the PLD outputs are ignored and vice versa After updating the requisite outputs click OK
100. ematics The cursor changes as follows depending on the operation X a The cursor changes to reflect the operation in progress Normal inactive WA Over a component Double click to edit Over an switch contact Drag to start editing a connection wea In process of making a connection and over a valid target p Releasing now will make or remove the connection In process of making a connection but not over a valid target Releasing now will abort the action In process of selecting a zoom rectangle Releasing now will cause the zoom to occur Pressing lt esc gt now will abort the zoom and leave the screen unchanged Starting a Design Utility You can use a design utility to modify your schematic To start a design utilities 1 With a device schematic open in the Main Window choose Tools gt Design Utilities The Design Utilities dialog box opens 2 From the list select the desired design utility When a selection is highlighted in the list a description of the design utility is displayed in the Design Utilities dialog box 3 Click OK Starting the ispClock Design Utilities You can use an ispClock design utility to modify your ispClock schematic PAC Designer Software User Manual 101 DESIGNING ISPCLOCK DEVICES Procedures To start an ispClock design utility 1 With an ispClock schematic open in the Main Window choose Tools gt Design Utilities The Design Utilities dialog box opens
101. enter a minimal sequence using the timers and outputs you plan to use in ABEL Choose Tools gt Compile LogiBuilder Design or click the compile button on the toolbar to generate an ABEL template from which your custom ABEL design can be built from Choose View gt ABEL Source to open an ABEL Source Window Choose Edit gt Enable ABEL Editing to enable the edit window and disable the LogiBuilder window Make changes to the ABEL source to implement the desired design 30 PAC Designer Software User Manual DESIGNING POWER MANAGER Devices Design Entry 10 Choose Tools gt Compile ABEL or click the compile button on the toolbar to compile the design Note If syntactical or other ABEL errors are in the design the compilation will fail and an error report will be displayed Choose Tools gt Run PLD Simulator or click the simulator button on the toolbar to simulate the design from ABEL Note The default stimulus file should be edited to reflect the input signals and basic design Entering Supervisory Equations You enter supervisory equations for a Power Manager device from the Supervisory Logic panel of the LogiBuilder Sequence and Supervisory Logic window Supervisory equations are combinatorial or registered logic independent of sequence controller logic To enter supervisory equations 1 From the top level schematic window configure the user defined inputs and outputs set the VMON trip point
102. ep Sequencer Instruction Outputs mmt Commer SMO_Step 0 Begin Startup Sequence no ispPAC HR s lt gt Exception ID Boolean Expression Outputs Exception Handler Comment lt end of exception table gt SMO Equation Supervisory Logic Equation Macrocell Configuration Comment TIMER1_GATE D NOT TIMER1_TC Output registered D flip flop Generating a pulse train ol BitO T TIMER1_TC Node registered T flip flop Bit 0 of the counter Bit1 T TIMER1_TC AND BitO Node registered T flip flop Bit 1 of the counter Bit2 T TIMER1_TC AND BitO AND Bit1 Node registered T flip flop Bit 2 of the counter Ten_Second_out D Bit2 AND NOT Bit AND BitO AND T Output registered D flip flop 10 second timer output BitO ar Ten_Second_out Node registered T flip flop Reset counter to restart c Bitl ar Ten_Second_out Node registered T flip flop Restart counter Bit2 ar Ten_Second_out Node registered T flip flop Restart counter lt end of supervisory logic table gt Eq0 Generates pulse train 4us wide and 2 seconds apart Eq1 Bit 0 of the counter that counts the 2 second pulse train Eq2 Bit 1 of the counter that counts the 2 second pulse train Eq3 Bit 2 of the counter that counts the 2 second pulse train Eq4 Ten_second_out signal generating a 4us pulse once in 10 seconds Eq5 Restarts the bit 0 counter after 10 seconds Eq6 Restarts the bit 1 counter after 10 seconds Eq7 Restarts the bit
103. er Vref Comment Save configurations to library file POL_With_Feedback_Node Save The dialog box is completed by entering the Rfb and Rin values calculated for a given output voltage and Vref which is found in the datasheet Note that the number of resistors used for controlling these types of DC DC converters can be minimized by using the actual voltage that is used on the board PAC Designer Software User Manual 177 POWER MANAGER EXAMPLE IMPLEMENTATION Creating a DC DC Converter Library Entry 4 Once the library entry is created the next step is to associate the DC DC converter from the library to the trim pin This is done using the following procedure a Start with the POWR1220AT8 schematic b Double click the Margin Trim Block c Double click the Trim Cell of interest for example Trim Cell 1 d Set options in the dialog box shown in Figure 69 to design the resistor network Figure 69 Calculating the Resistor Network for a DC DC Converter Trim 1 Configuration Schematic Net Name Trim OK DC DC Converter Murata_OKYT3 D12 Import DC DC Cancel Profile 0 Mode Closed Loop Trim X Target Voltage Realized Voltage DAC Code DAC Current Voltage Profile 0 0 0 1 2 y 1 198 2 0 03 uA Options Voltage Profile 1 0 1 1 26 y 1256V 6 0 03 uA Voltage Profile 2 1 0 1 14 Vo 1440 10 0 03 u Error Details Voltage Profile 3 1 1 1 2 Yy 1 198 2 0 03 uA DAC Output Ran
104. er selectable profiles Independently programmable skew and slew rate control on each output PAC Designer Software User Manual ISPPAC DEVICE SUMMARY Table 1 ispPAC Device Summary Continued Device ispPAC CLK5316S gt ispPAC CLK5320S gt ispPAC CLK5406D gt Applications Zero delay universal fan out buffer 16 single ended outputs Frequency multiplication amp division Zero delay buffer Zero delay universal fan out buffer 20 single ended outputs Frequency multiplication amp division Zero delay buffer Differential zero delay universal fan out buffer 6 differential outputs Frequency multiplication amp division Zero delay buffer Features Yv vV V vv v vv v V 8MHz to 267MHz Low cycle to cycle period and phase jitter Programmable input and output termination Supports input standards LVCMOS LVTTL LVPECL LVDS HSTL SSTL differential HSTL and differential SSTL standards E2CMOS memory stores up to four user selectable profiles Independently programmable skew and slew rate control on each output 8MHz to 267MHz Low cycle to cycle period and phase jitter Programmable input and output termination Supports input standards LVCMOS LVTTL LVPECL LVDS HSTL SSTL differential HSTL and differential SSTL standards E2CMOS memory stores up to four user selectable profiles Independently programmable skew and slew rate control on each output 50MHz to 400MHz Low cy
105. er Manual POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Supervisory Logic Figure 55 Supervisory Equation to Generate a Pulse Train 4us and 2 Seconds Apart PAC Designer 2 Minute Timer PAC Sequence and Supervisory Logic file Edit view Tools Options Window Help Oo ee NA 3 Ye ED Pa E Ste 0 Begin Startup Sequence no ispPAC meen m Lenan a lt Exception ID eee ee Exception Handler lt end of exception table gt SMO Equation Supervisory Logic Equation Macrocell Configuration Comment EQo TIMER1_GATE D NOT TIMER1_TC Output registered D flip flop Generating a pulse train ol lt end of supervisory logic table gt lt Loading data into list view A 10 second timer requires a 3 bit counter that counts the 4us pulses The 3 bit counter is implemented three internal nodes BitO Bit1 and Bit2 The method to create nodes is described later Nodes are internal variables and are not output to pins The Ten_second_Out pin generates a 4 microsecond wide signal once every 10 seconds The supervisory equations are shown below in Figure 56 PAC Designer Software User Manual 163 POWER MANAGER EXAMPLE IMPLEMENTATION Digital Timing Simulation Using PAC Designer Figure 56 10 second Timer Implementation Using Supervisory Logic Equations PAC Designer 2 Minute Timer PAC Sequence and Supervisory Logic DE file Edit view Tools Options Window Help X s
106. ermines how fast the MOSFET is turned off when the output pin switches to Logic 0 This can be set to 100A 250uA 130 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION Configuring Timers 500uA or 3000A The higher the current the faster the MOSFET turn off process Click OK to jump to the intermediate schematic Figure 15 and double click the blank space to navigate to the main schematic Figure 8 Configuring Timers The power management algorithm requires long duration timers The Power Manager device implements four hardware timers which can be configured independently Double click the Timer block in between the Logic Outputs block and the Logic Inputs block at the bottom to navigate to an intermediate schematic shown in Figure 17 Figure 17 Clock amp Timers Schematic Interface FI Fie Edit View Tools Options Window Help xX D LEERE Ye ueo S Double click to go back to the main schematic page The above figure shows four timers and the clock source Double click any Timer block to navigate to Clocks amp Timers dialog box shown in Figure 18 PAC Designer Software User Manual 131 POWER MANAGER EXAMPLE IMPLEMENTATION Configuring Timers Figure 18 Clocks amp Timers Dialog Box Clocks amp Timers Master Clock Source 8MHz GR Pea Internal OSC MCLK pin used as output Cancel C Slave External OSC PLDCIk Buffered Output PLDCLK pin Enabled
107. esign Create a new document ispPAC CLK5410D ispPAC CLK5406D ispPAC CLK56204 ispPAC CLK56104 ispPAC CLK53205 ispPAC CLK53165 ispPAC CLK53125 ispPAC CLK53085 ispPAC CLK53045 ispPAC POWR 1220478 ispPAC PO WR 122047 8 02 ispPAC POWR 10144 ispPAC POWR10144 02 ispPAC POWR1014 ispPAC POWR1014 02 L4 ispPAC POWR 10144 L4 ispPAC POWR1014 ispPAC POWREATE ispPAC POWR1208P1 ispPAC POWR 1208 ispPAC POWREO Zero Delay Universal Fan out Buffer Differential Zero Delay Universal Fan out Buffer Differential Enhanced Zero Delay Clock Generator with Universal Fan out Buffer Cancel Enhanced Zero Delay Clock Generator with Universal Fan out Buffer Zero Delay Universal Fan out Buffer Single ended Zero Delay Universal Fan out Buffer Single ended Zero Delay Universal Fan out Buffer Single ended Zero Delay Universal Fan out Buffer Single ended Zero Delay Universal Fan out Buffer Single ended Supply Sequencing Monitoring Measurement Trimming and Margining Supply Sequencing Monitoring Measurement Trimming and Margining 12 Supply Sequencing Monitoring and Measurement Supply Sequencing Monitoring and Measurement 12 Supply Sequencing Monitoring Supply Sequencing Monitoring 124 Supply Sequencing Monitoring and Measurement Supply Sequencing Monitoring Supply Measurement Trimming and Margining Supply Sequencing Precision Monitoring Supply Sequencing Monitoring Supply Sequencing Monitoring To open a file
108. ession styles are provided to ease the definition of logic and produce the most compact implementation in the Power Manager device Sequencer Instructions Defines a step by step instruction for controlling Power Manager outputs When compiled sequencer instructions implement a digital logic state machine within the Power Manager s PLD core Exceptions Define equations that will trigger sequence controller exceptions to modify outputs and jump out to an alternative sequence step Exceptions can be selectively applied to any sequencer step When compiled exception instructions are merged with the digital logic state machine of the Power Manager s PLD core Supervisory Equations Define combinatorial and registered logic independent of the sequencer control logic When compiled supervisory equations are concurrent to the digital logic state machine of the Power Manager s PLD core LogiBuilder Sequence Controller Instruction Set LogiBuilder provides the following instructions for designing control sequences START STARTUP SEQUENCE The START STARTUP SEQUENCE instruction signals to LogiBuilder that any instructions past this point may be interrupted by jumps specified in exceptions This instruction may be deleted from a sequence but not inserted Exceptions are automatically enabled following this point OUTPUT The OUTPUT instruction is used to turn on or turn off the Power Manager devices output signals A si
109. ettings dialog box S Waveform Viewer DESIGN1_VMON1_6K BEE Fle Edt View Object Toots Opiom Jump Help Sia 8 12110 Sa ez 1 000 000 2 000 000 3 000 000 4 000 000 4 gt Time 4 210 000 0 ns Delta 4 110 000 0 ns Strong 1 Simulation States Printing the Results You can print the results of your simulation and zoom in on a portion of the waveforms To print the results 1 Choose File gt Print or Click the Print button from the toolbar to display the Print Waveforms Dialog Box PAC Designer Software User Manual 95 DESIGNING PLATFORM MANAGER DEVICES Waveform Viewer Results Edit the Start Time End Time or Time Scale as needed to zoom in ona portion of the waveforms 96 PAC Designer Software User Manual sm LATTICE Chapter 5 E SEMICONDUCTOR Concepts Designing ispClock Devices This section contains concepts procedures and user interface description on designing ispClock devices This section describes ispClock design concepts Schematic Entry Schematic entry consists of making internal connections and choosing parametric circuit values on an ispPAC device schematic window When complete the circuit can be simulated saved or downloaded to an isoPAC device As an alternative to complete configuration standard circuit functions are available from a library of stored designs The PAC Designer schematic window provides access to all configurable ispPAC d
110. everal formats from a PAC Designer schematic For Power Manager devices you can also export digital elements timers and the PLD core to a Verilog or VHDL file for functional simulation See Simulating a Power Manager Design with Aldec Active HDL for details To export data from a PAC Designer schematic 1 Choose File gt Export The Export Dialog Box opens Under Export What select a data type The available data types listed in this box are device dependent Under In this format select the desired export file format If you want to export the data to a file select File and then click Browse to navigate to the file to which you want to export data If you want to export the data to your computers Clipboard memory select Clipboard Click OK Creating and Editing an ABEL Design You can create and edit an ABEL design for a Power Manager device To create and edit an ABEL design 1 From the top level schematic window configure the user defined inputs and outputs set the VMON trip points and configure the clock and timer settings Double click the Sequence Controller block to display the Sequence and Supervisory Logic Window Choose View gt Pins definitions or click the pins button on the toolbar to display the Pin Definitions Window to configure the logic level of the input pins and the type and power up state of the output pins Return to the LogiBuilder Sequence and Supervisory Logic Window and
111. evice elements through its graphical user interface All input and output pins are represented Static or non configurable pins such as power ground VREF OUT and the serial digital interface are purposely omitted Any element in the schematic window can be accessed through mouse operations as well as by menu commands ispClock Design Utilities There are four design utilities available for the isoClock devices gt Frequency Calculator gt Frequency Checker PAC Designer Software User Manual 97 DESIGNING ISPCLOCK DEVICES Concepts gt Frequency Synthesizer Skew Editor isoPAC CLK5400D 5600 only Frequency Calculator The ispClock Frequency Calculator will read a configuration from PAC Designer and calculate all output frequencies for a given reference input frequency Frequency Checker The ispClock Frequency Checker will read a configuration from PAC Designer and decide whether the operating frequencies of the phase detector and the VCO are within rated limits If these parameters are outside their frequency limits the Frequency Checker will make suggestions on how you could change the configuration to keep the VCO and phase detector frequencies within limits Frequency Synthesizer The ispClock Frequency Synthesizer lets you enter a set of desired output frequencies and an optional input frequency and will calculate a device configuration that produces the desired output frequencies If the input reference
112. evices This section illustrates Platform Manager designs It includes six sub sections Design Entry LogiBuilder Functional Logic Simulation Automatic ABEL Import Waveform Editor Waveform Editor Stimulus v vV vV V V Y Waveform Viewer Results This section contains concepts procedures and user interface description on designing Platform Manager devices Concepts This section describes Platform Manager design concepts Schematic Entry Schematic entry consists of making internal connections and choosing parametric circuit values on an ispPAC device schematic window When complete the circuit can be simulated saved or downloaded to an isoPAC device As an alternative to complete configuration standard circuit functions are available from a library of stored designs PAC Designer Software User Manual 53 DESIGNING PLATFORM MANAGER DEVICES Design Entry The PAC Designer schematic window provides access to all configurable ispPAC device elements through its graphical user interface All input and output pins are represented Static or non configurable pins such as power ground VREF OUT and the serial digital interface are purposely omitted Any element in the schematic window can be accessed through mouse operations as well as by menu commands Schematic Entry Platform Manager Devices The PAC Designer schematic window provides access to all configurable Platform Manager device elements through its
113. exception Reason If you insert or delete an instruction that is the target of a Goto and now this error is possible you are not warned at that time Technical Reason Same as step zero above Timer_Gate signal must have a low level then a high level for timer to operate To do this for an instruction at step N the instruction at step N 1 must set Timer_Gate 0 then Instruction N can set Timer_Gate 1 Therefore N cannot be zero Remedy Insert an additional instruction before the timer based instruction and make that the branch target Error 3 Instructions that start a timer may not follow one another This includes WaitFor_Timer or Start_Timer instructions Reason This is a software limitation The ABEL code generator can deal with only one timer in any one instruction Remedy Insert any other instruction between the two instructions A No Operation instruction NOP may be used if no additional functionality is desired between the timer instructions Error 4 Goto IffhenElse attempts to branch to a step that does not exist Reason The Delete instruction function adjusts current Goto positions but does not protect against this error If you deleted enough instructions the Goto could be left pointing to empty space Warning 5 Un initialized Step numbers in IffhenElse instruction Reason If Then Goto 0 Else Goto 0 with step numbers all zero probably means un initialized step numbers and most likely was n
114. f Then Else instructions to poll the supply fault and input reset signal and performs different functions depending on the input conditions PAC Designer Software User Manual 149 POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Sequence Control Figure 40 Sequence Controller Polling Digital Input and Supply Fault PAC Designer Design1 PAC Sequence and Supervisory Logic DSR Eile Edit View Tools Options Window Help o x Step Dele Sequencer Instruction Je Ge EFI Outputs wes Comment SMO Step 0 SMO Step 1 SMO Step 2 SMO Step 3 SMO Step 4 SMO Step 5 SMO Step 6 SMO Step 7 Begin Startup Sequence Wait for AGOOD Start timer 1 5 12ms ispPAC POWR 1220478 reset Core_1 2_En 0 IO_1 8_En 0 Reset_CPU 0 Start with all supplies turned off and Core_1 2_En 1 IO_1V8_En 1 This starts the timer and turns the su If Core_1 2_OK AND IO_1V8_OK If the supplies are OK jump Then Goto 4 Else Goto 6 If Reset_in to check the reset input If the suppleis are Faulty This Checks for the reset Then Goto 3 with Reset_CPU 1 input and changes the CPU Else Goto 3 with Reset_CPU 0 reset signal depending ont Begin Shutdown Sequence no Core_1 2_En 0 10_1 8 En 0 Seq Err 1 no There was a supply Fault shut all su Halt fend of program no Exception ID Boolean Expression Outputs Exception Handler SMO lt end of exception table gt Equation S
115. fine logic functions When complete the circuit can be simulated saved or downloaded to a Power Manager device To design a control sequence with LogiBuilder 1 In a Power Manager Schematic Window double click the Sequence Controller block to display the Sequence and Supervisory Logic window 2 Inthe sequence upper portion of the window highlight step 1 and choose Edit gt Insert Instruction to display the Insert Step Dialog Box 3 In the dialog box choose an instruction type and click OK Repeat as necessary to add logic steps 4 For each logic step choose Edit gt Modify Instruction Parameters to display the appropriate Edit dialog box 5 Select the desired logic properties in the Edit dialog box and click OK 6 To add exceptions in the exceptions lower portion of the window highlight lt end of exception table gt and choose Edit gt Add Exception Repeat as necessary to add exceptions 7 For each exception choose Edit gt Modify Exception Parameters to display the Exception Properties Dialog Box 8 Select the desired exception properties and click OK 9 When the logic sequence is complete compile your control sequence by choosing Tools gt Compile LogiBuilder Design Editing Pin Settings with LogiBuilder Pin names are set at the schematic level You can make edits to pin settings with the Pin Definitions window To edit pin settings with LogiBuilder 1 Choose View gt Pin Definitions 2 I
116. first step is to select the timer used for implementing the timeout delay It is possible to change the value of the time delay from this dialog box by clicking Edit Timeout properties to go to the Clocks amp Timers dialog box shown in Figure 18 It is possible to enable outputs along with this step For example in Figure 33 the Timer 1 5 12ms duration is started and the 1 2V core supply is also turned on The Sequence Controller waits in that step till the Timer 1 expires Figure 33 Wait for Timeout to Turn on the Supply amp Wait for 5 12ms 5 12ms timeout 1966 08ms timeout Cancel 1966 08ms timeout cancel 1966 08ms timeout Edit Timeout properties Outputs Output Control Instruction is interruptible by an exception Comment Tum 1 2 supply and wait for 5 12 ms By clicking OK and adding another Wait for timeout instruction and an Output instruction the Sequence Controller program is shown in Figure 34 PAC Designer Software User Manual 143 POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Sequence Control Figure 34 Program to Turn on Supplies in a Sequence amp Release Reset PAC Designer Design1 PAC Sequence and Supervisory Logic DER T file Edit view Tools Options Window Help or xX Dele Step Sequencer Instruction se Ge FE Outputs s Comment SMO Step 0 SMO Step 1 SMO Step 2 SMO Step 3 SMO Step 4 SMO Step 5 SMO Step 6 Begin Startup Sequence Wait for AG
117. form Manager pin settings with the Logic I O Assignment Dialog Box To edit pin settings with LogiBuilder 1 Choose View gt Pin Definitions 2 Inthe Logic I O Assignment Dialog Box click a tab that you want to edit 3 In the appropriate tab make editable changes and click OK 72 PAC Designer Software User Manual DESIGNING PLATFORM MANAGER Devices LogiBuilder Viewing Messages Errors in LogiBuilder You can view messages and errors in LogiBuilder To view messages and errors gt Choose View gt Messages Errors The Messages Error Window opens Editing Multiple State Machines The LogiBuilder supports multiple state machines for power up sequence and control for some Platform Manager devices The state machines are defined separately but can interact through nodes or common logic functions Each state machine is built up in a separate tab in the Sequence and Supervisory Logic window The logic for the full design is then compiled and fitted to generate a single JEDEC file You can use the MSM Manager Dialog Box to add or delete state machines To open the dialog box make sure the Sequence and Supervisory Logic window is open and the Sequencer Instructions table or the Exceptions table is active and then choose Edit gt Multiple State Machines Multiple state machines are supported for the Sequencer Instructions table and the Exceptions table only The settings in the Supervisory Equations table always apply
118. fter the first marker is placed use the menu or tool to place a second marker The difference in time between the two is displayed in the status bar at the bottom of the window as shown below The time from VMONT7 tripping to HVOUTT7 turning on is displayed as 4 21 ms The additional 110 us results from the step latency This additional delay can become quite significant if the PLD Clock Frequency were to be lowered using either the ispPAC POWR604 Clock and Timer Settings dialog box or the ispPAC POWR1208 ispPAC POWR1208P1 Clock and Timer Settings dialog box PAC Designer Software User Manual 51 DESIGNING POWER MANAGER DEVICES Waveform Viewer Results E Waveform Viewer DESIGN1_VMON1_6K Fie Edt View Obiect Toots Options Jump Help Biel Ea 12 2 1 000 000 2 000 000 3 000 000 4 000 000 alal al 21 410 l D TIMERI_GATE step 4 Time 4 210 000 0 ns Delta 4 110 000 0 ns Strong 1 Simulation States Printing the Results You can print the results of your simulation and zoom in on a portion of the waveforms To print the results 1 Choose File gt Print or Click the Print button from the toolbar to display the Print Waveforms Dialog Box 2 Edit the Start Time End Time or Time Scale as needed to zoom in ona portion of the waveforms 52 PAC Designer Software User Manual Saa LAT TICE E SEMICONDUCTOR Design Entry Chapter 4 Designing Platform Manager D
119. ge BPZ Voltage 0 60 ispPAC POWR RpupDAC in ohms Open RpdnDAC in ohms Open Rseries in ohms a 2400000 Reseries RpupSupply in ohms Open H E 2 7 RednSupply in ohms Open Schematic Net Name The actual name of the pin in the schematic DC DC Converter Select the appropriate DC DC converter from the library by clicking Import DC DC In this example Murata_OKY3_D12 is selected Profile 0 mode The pull down menu selects the operating mode of the Trim Cell closed loop trim trim using 12C interface with an external microcontroller and EECMOS value open loop trimming Voltage Profile 0 The nominal operating voltage of the DC DC converter Voltage Profile 1 One of the margining profiles It can be the margin up or margin down value 178 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION Creating a DC DC Converter Library Entry Voltage Profile 2 The other margin profile Again this can be the margin down or margin up voltage value Voltage Profile 3 An additional profile provided for convenience In some cases this can be used for additional margin testing After entering the required voltage values click Calculate The software calculates the resistors to be placed between the Trim Cell output and the DC DC converter trim pin Calculated DAC code values along with the DAC currents for each of the profiles are also shown When you click OK these va
120. graphical user interface All input and output pins are represented Some of the non configurable pins such as the serial digital interface are purposely omitted Any element in the schematic window can be accessed through mouse operations as well as by menu commands The schematic for the Platform Manager device is hierarchical as it contains other schematic or text entry windows within a given block These blocks are edited by double clicking a given section You can navigate between the different blocks with simple click and edit features Platform Manager Design Utilities There are two design utilities available for the Platform Manager devices gt HVOUT Simulator Allows you to simulate the rise time of a power supply driven by an N Channel MOSFET and the HVOUT drivers on the Platform Manager devices gt 12C Utility IC capable devices only Allows you to drive the 12C interface with the Lattice isoDownload Cable Trimming and Margining Power Supplies Setting up the trim and margin capabilities of LPTM10 1247 and LPTM10 12109 involves two different tools within PAC Designer The DC DC Library Builder is used to define the voltage adjustment characteristics of the power supply or supplies that you wish to use The Trim Configuration Dialog Box is then used to configure each trim channel for the desired power supplies and output voltages This arrangement provides the convenience of being able to re use a single power supply i
121. he equivalent circuit in the error amplifier section After entering the Vref or lref amp Rref values click Next to get the dialog box shown in Figure 65 Figure 65 Configuring the Programmable Voltage DC DC Converter Library Entry DC DC Converter Datasheet Example Configurations Va DC DC Converter Nominal Output Yoltage With Trim Resistor Open 0 7525 y Values from the DC DC Converter Datasheet Example Configuration Equations Example Example2 Example3 R to GND R to GND R to Vout Output Voltage with Trim Resistor Open W jo zs v o v Trimmed Margined Output Voltage with Trim Resistor Connected fi y 5 v v Trim Resistor in ohms Required to ohms Set Output Voltage as Above 41424000 iia 1472 ae Comment Save configurations to library file Murata_OKYT3 D12 lt Back Finish Cancel The output voltage of these types of DC DC converters is determined by the resistor connected from their trim pin to GND To complete this dialog box refer to the DC DC converter datasheet for a table that maps the resistor values connected between the trim pin and GND to the desired output voltage values In some cases the DC DC datasheet provides a formula for calculating the output voltage for a given trim resistor The first field is the output voltage of the DC DC converter when the trim pin is open This is usually one of the entries in the table or is 174 PAC Designer Software User Manual POWER MAN
122. he Boolean condition becomes true within that time period the Sequence Controller jumps to the next step However if the timer expires before the Boolean 138 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Sequence Control expression becomes true the Controller jumps to a different location determined by the instruction Wait for lt Boolean gt Application This instruction is used to turn a supply on and hold the Sequence Controller at a step for a power supply to reach its regulation levels This instruction is first inserted as raw into a step using the Insert key on the keyboard Double click the raw Wait for lt Boolean gt instruction to open the following dialog box Figure 25 for configuring the Wait for lt Boolean gt instruction Figure 25 Edit Wait For Bool Properties Dialog Box Edit Wait For Bool properties Instruction Preview Instruction Outputs Wait For lt BooleanExpr gt Edit Boolean Expression Output Control Instruction is interruptible by an exception Comment In the dialog box click Edit Boolean Expression to open the following dialog box Figure 26 Figure 26 Boolean Expression Editor Boolean Expression Editor Boolean Expression AND OR NOT Double click to add available items to expression Core_1 2_over_LTP 10_1 8_OK 10_1 8_over_LTP VMON3_A VMON3_B VMON4 A VMON4 B Any Boolean function
123. he ispPAC POWR1208 AN6047 Programmable Comparator Options for isoPAC POWR1220AT8 AN6069 Programming the ispPAC POWR1220AT8 in a JTAG Chain Using the ATDI Pin AN6068 Simulating Power Supply Sequences for Power Manager Devices Using PAC Designer LogiBuilder AN6044 Stable Operation of DC DC Converters with Power Manager Closed Loop Trim AN6077 Using PAC Designer s Power Manager Waveform Editor AN6054 Using Power MOSFETs with Power Manager Devices AN6048 Using ispVM System to Program ispPAC Devices AN6062 Using the ABEL Tools of PAC Designer with Power Manager Devices AN6052 Using the HVOUT Simulator Utility to Estimate MOSFET Ramp Times AN6070 Using Power Platform Management Device HVOUTs to Drive MOSFETs AN6043 Development Kits and Hardware ispClock5620A Evaluation Board AN6072 ispClock5312S Evaluation Board User s Guide EB32 ispClock5620 Evaluation Board isoPAC CLK5620 EV1 AN6064 Power Manager II Hercules Development Kit EB57 Platform Manager Development Kit EB58 ProcessorPM Development Kit EB45 POWR1014A Breakout Board Evaluation Kit EB64 isoPAC POWR607 Evaluation Board User s Guide EB28 ispPAC POWR1220ATE I2C Hardware Verification Utility User s Guide AN6067 184 PAC Designer Software User Manual Saa LAT TICE E SEMICONDUCTOR index A auto calibrate 114 Cc capabilities 1 D data downloading 114 exporting from schematic 105 exporting importing 3 import
124. hierarchically However you do not have to be familiar with the Waveform Description Language to use the Waveform Editor Zooming In and Out Click the Zoom In button on the toolbar or the Zoom In button on the toolbar to activate the zoom cursor You can also choose View gt Zoom In and View gt Zoom Out to activate the zoom cursor Waveform Editor DESIGN1 Fie Edt View Object Tools Options Jump Help Place the zoom cursor over the time of interest and click to zoom in or out Repeated clicks will continue to zoom in or out To cancel the zoom in cursor right click 11 500us Y Starting the Waveform Editor To generate or edit a stimulus file choose Tools gt Design Utilities Then select Waveform Editor from the Design Utilities list Opening the Default Stimulus file To open the default stimulus file gt Inthe Waveform Editor choose File gt Open The New Dialog Box opens PAC Designer copies a default stimulus file into the _PLDFiles folder and names it with the design name 88 PAC Designer Software User Manual DESIGNING PLATFORM MANAGER Devices Waveform Editor Stimulus Adding a Signal To add a signal 1 Choose Edit gt New Wave or Click the New Wave button on the toolbar as shown below to display the Add New Wave Dialog Box g Waveform Editor DESIGN1 He Edt View Object Tools Options Jump Help olele S elel oleae al 5 900 ns CLK_IN 2 Type in
125. iBuilder so that generated ABEL code is always correct See the Type checked assignments table page 4 Error 17 Output cannot be set Asynchronously by an Supervisory equation unless assigned by an instruction Reason The ABEL language used to implement the PLD requires this Error 18 State variable must be D type FF Use Pins window to change type Reason This error typically occurs if you choose to re define the standard state variable allocation and use OUTs which are defined as JK Simply change the type of the OUT from JK to D using the pins window Error 19 State variable cannot be used as an output Reason This error typically occurs if you choose to re define the standard state variable allocation and use OUTs Error 20 State variable cannot be used as a timer Reason This error typically occurs if you use the standard state variable allocation and use the timers that are reserved for state variables Error 21 Not enough macrocells for State Variable Reason This message shows up when automatic state variable allocation is used in multiple state machine design if your design is too full You will need to make your design smaller by using fewer LogiBuilder steps fewer supervisory logic equations fewer outputs or fewer timers Error 22 StartTimer requires Timer to be in JK mode Reason The timer macrocell is in D flip flop or combinatorial mode Go to the PINS window and double click the macrocell You will then see
126. ialog box either double click the name in the Nets list or highlighting the name and click the Show button Adding the Step bus to the Display Adding a waveform that displays the sequencer step is useful in debugging designs It combines the step counter outputs into one waveform To the step bus to the display 1 Choose Edit gt Show Waves or Click the Show Waves button of the toolbar as shown below to display the Show Waveforms Dialog Box BA Waveform Viewer DESIGN1_VMON1T_6K File Edt View Object Tools Options Jump Help elal S APL A B Bis 22 2 450 000 0 ns Double click D in the Instances list Click the Bus button to extend the dialog box Highlight each of the step counter flip flop outputs and click Add Net s Rename the bus name to step as shown below Click the Save Bus button Click the Show button Sm or ee IN PAC Designer Software User Manual 93 DESIGNING PLATFORM MANAGER DEVICES Waveform Viewer Results Show Waveforms Ea Net Name JO STATE_FFO Bus Name E en z row Bus lt lt Add Nets New Bus TE Instances Bus Members Move Up The following figure illustrates what a view will look like when the step waveform is added FA Wavetoen Viewer DESIGNI_VMON1_6K pa Mave ia Ee EA Yen Diha Teh Di Aro Help 1 000 000 2 000 000 3 000 000 5 000 000 D TIMERI_GATE steph Dik Time 0 000 0 ns BUS 1
127. ible with Windows NT 4 0 It uses no Windows 2000 specific features The PAC Designer Setup Program copies PACUTAG SYS and will edit the registry for you but your system may be modified at a later time rendering the PACUTAG SYS not found if PACUTAG were removed for instance This topic is provided for those cases Manual install requires editing the registry and should only be done by experienced users Others should re install PAC Designer to get the driver working again Registry Edit REGEDIT4 HKEY_LOCAL_MACHINE SYSTEM CurrentControlSet Services PacJtag ErrorControl dword 00000000 Start dword 00000001 Type dword 00000001 ImagePath System32 DRIVERS pacjtag sys PAC Designer Software User Manual 111 DEVICE PROGRAMMING Procedures Setting JTAG Interface Options Devices and chain files are programmed using a download cable connected to your computer The Cable and I O Port Setup Dialog Box allows you to set options so that your download cable functions properly PAC Designer supports the parallel port and the USB port for the download interface To set JTAG interface options 1 With the device connected to your computer with a download cable and applied power choose Options gt Cable and I O Port Setup The Cable and I O Port Setup dialog box opens 2 Click Change The Change Programming Cable Interface Dialog Box opens displaying options for parallel port or US
128. ign the compilation will fail and an error report will be displayed Choose Tools gt Run PLD Simulator or click the simulator button on the toolbar to simulate the design from ABEL Note The default stimulus file should be edited to reflect the input signals and basic design Entering Supervisory Equations You enter supervisory equations for a Platform Manager device from the Supervisory Logic panel of the LogiBuilder Sequence and Supervisory Logic window Supervisory equations are combinatorial or registered logic independent of sequence controller logic To enter supervisory equations 1 From the top level schematic window configure the user defined inputs and outputs set the VMON trip points and configure the clock and timer settings Double click the CPLD Logic or FPGA Logic block to display the Sequence and Supervisory Logic window Choose View gt Pins definitions or click the pins button on the toolbar to display the Logic I O Assignment Dialog Box to configure the logic level of the input pins and the type and power up state of the output pins Return to the LogiBuilder Sequence and Supervisory Logic window Double click on the lt end of supervisory logic table gt marker to insert an equation place holder Double click on the equation place holder to display the Supervisory Logic Equation Entry Dialog Box to edit the equation settings Click OK Note LogiBuilder sequencing exceptions and
129. iles the design and can simulate the sequence or control events Three types of expression styles are provided to ease the definition of logic and produce the most compact implementation in the Platform Manager device Sequencer Instructions Defines a step by step instruction for controlling Platform Manager outputs When compiled sequencer instructions implement a digital logic state machine within the Platform Manager s PLD core Exceptions Define equations that will trigger sequence controller exceptions to modify outputs and jump out to an alternative sequence step Exceptions can be selectively applied to any sequencer step When compiled exception instructions are merged with the digital logic state machine of the Platform Manager s PLD core gt Supervisory Equations Define combinatorial and registered logic independent of the sequencer control logic When compiled supervisory equations are concurrent to the digital logic state machine of the Platform Manager s PLD core LogiBuilder Sequence Controller Instruction Set LogiBuilder provides the following instructions for designing control sequences START STARTUP SEQUENCE The START STARTUP SEQUENCE instruction signals to LogiBuilder that any instructions past this point may be interrupted by jumps specified in exceptions This instruction may be deleted from a sequence but not inserted Exceptions are automatically enabled following this point 7
130. imulus file Inthe Waveform Editor choose File gt Open The New Dialog Box opens PAC Designer copies a default stimulus file into the _PLDFiles folder and names it with the design name Adding a Signal To add a signal 1 Choose Edit gt New Wave or Click the New Wave button on the toolbar as shown below to display the Add New Wave Dialog Box PAC Designer Software User Manual 45 DESIGNING POWER MANAGER DEVICES Waveform Editor Stimulus g Waveform Editor DESIGNT plela a He ele ale 5 900 ns 0 5 000 CLK_IN 2 Type in the name of the signal or waveform 3 Select an option in the Polarity box to indicate polarity 4 Click Add 0 10 000 000 20 000 000 CURLIN WY RESET VMONI 1 Add New Wave x Polatity Input C TesPt C Bide C Gobd C uput Potem Ads vMoNni Changing a signal level You can edit and modify waveforms with the Select dialog box The contents of the dialog box will change based on where and which waveform is selected using the mouse To change a signal level 1 Select the waveform you wish to change 2 Choose Object gt Edit Mode to display the Selected Dialog Box as shown below 3 Click the desired state in the States box 0 10 000 000 20 000 CuLIN WM Selected Bit Pulse High xf Valie sose m Hepes E ju Forever 46 PAC Designer Software User Manual DESIGNING POWER MANAGER Devices Wavefo
131. in the schematic window can be accessed through mouse operations as well as by menu commands The schematic for the Power Manager device is hierarchical as it contains other schematic or text entry windows within a given block These blocks are edited by double clicking a given section You can navigate between the different blocks with simple click and edit features Power Manager Design Utilities There are two design utilities available for the Power Manager devices gt Power Manager HVOUT Simulator Allows you to simulate the rise time of a power supply driven by an N Channel MOSFET and the HVOUT drivers on the Power Manager devices gt Power Manager 12C Utility I7C capable devices only Allows you to drive the 12C interface with the Lattice ispDownload Cable Trimming and Margining Power Supplies Setting up the trim and margin capabilities of isoPAC POWR1220AT8 and ispPAC POWREATE involves two different tools within PAC Designer The DC DC Library Builder is used to define the voltage adjustment characteristics of the power supply or supplies that you wish to use The Trim Configuration Dialog Box is then used to configure each trim channel for the desired power supplies and output voltages This arrangement provides the convenience of being able to re use a single power supply in several different trim channels or projects without having to re enter its parameters each time The flow is illustrated below H Target
132. ing to schematic 104 uploading 114 DC DC Library Builder 169 design examples 98 120 design mapping 14 design utilities ispClock 97 Platform Manager 54 Power Manager 12 starting 101 starting isoClock 101 starting Platform Manager 63 starting Power Manager 24 device pin swapping 19 61 device summary 5 download cable overview 107 specifications 109 driver installing 111 E error messages device programming 109 LogiBuilder 36 75 viewing in LogiBuilder 34 73 example 98 exporting data 3 H HVOUT pins configuring 129 HVOUT_Sim utility 24 64 l I2CUtility 28 67 implementation example 117 importing data 3 ispClock design utilities 97 editing schematics 100 starting design utilities 101 using Frequency Calculator 102 using Frequency Checker 103 using Frequency Synthesizer 103 using Skew Editor 104 ispPAC device summary 5 J JTAG interface options 112 L LogiBuilder editing pin settings 34 72 error messages 36 75 exception conditions 155 156 implementing power management algorithm 133 overview 32 70 sequence controller instruction set 32 70 supervisory logic 160 viewing messages errors 34 73 PAC Designer Software User Manual 185 INDEX M multiple state machines 167 P PACJTAG SYS device driver installing 111 parallel port connection testing 112 pin settings 34 72 pin swapping 19 61 Platform Manager design utilities 54 editing schematics 59 editing schematics with cur
133. inue to zoom in or out To cancel the zoom in cursor right click 11 500 us 0 CLK_IN itp Adding Signals to the Display You can add signals to the display from the Edit menu or from the Show Waveforms button of the toolbar To add a signal to the display 1 Choose Edit gt Show Waves or Click the Show Waves button of the toolbar as shown below to display the Show Waveforms Dialog Box BA Waveform Viewer DESIGN1_VMON1T_6K Fie Edt View Object Tools Options Jump Help sla a AeA 2 8 2l 21 450 000 0 ns E 2 Inthe Show Waveforms dialog box either double click the name in the Nets list or highlighting the name and click the Show button Adding the Step bus to the Display Adding a waveform that displays the sequencer step is useful in debugging designs It combines the step counter outputs into one waveform To the step bus to the display 1 Choose Edit gt Show Waves PAC Designer Software User Manual 49 DESIGNING POWER MANAGER DEVICES Waveform Viewer Results or Click the Show Waves button of the toolbar as shown below to display the Show Waveforms Dialog Box FA Waveform Viewer DESIGN1_VMON1_6K File Edt View Object Tools Options Jump Help lel a eeen 2 B 212 2 e Double click D in the Instances list Click the Bus button to extend the dialog box Highlight each of the step counter flip flop outputs and click Add Net s Rename the bus name
134. ion Cancel State Machine Encoding Binary C Gray Flip Flop Synthesis Default D T Type C D Type C T Type Select the Allow deletion of the last Halt instruction option and you will no longer be prevented from deleting any Halt instruction 154 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Exception Conditions LogiBuilder Exception Conditions So far the sequence control window of the LogiBuilder was described The next section of the LogiBuilder window is Exception Condition Exception conditions are used to interrupt the Sequence Controller flow to enable the sequence control program to respond differently to an external stimulus without looking for it in the main sequence code The Exception Condition section of the LogiBuilder window is shown in the Figure 46 To show the use of the exception conditions the watchdog timer design in Figure 44 is modified to monitor for supply failure while monitoring for watchdog timer as shown in Figure 46 Figure 46 Exception Condition Section in LogiBuilder PAC Designer Figure_40_Exception condition PAC Sequence and Supervisory Logic BEE file Edit view Tools Options Window Help 21 AX D eH seo Ge EFI PINS St Ga Sequencer Instruction Outputs mt Comment SMO Step 0 Begin Startup Sequence no ispPAC POWR 1220478 rese SMO Step 1 Wait for AGOOD Core_1Y2_En 1 IO_1 8 no Start with a
135. ion of the physical pin can be changed by changing the Pin Name field gt Input From This associates the logical signal name specified in the User Defined Name field to either a physical pin or an internal register Note IN1 is controlled by the JTAG register or the external pin IN2 to IN6 can be controlled by 12C register Changing pin allocation also changes the register bit associated with that input Click the OK button to navigate back to the schematic shown in the Figure 11 From there navigate back to the main schematic shown in Figure 8 by double clicking the blank space in the schematic shown in Figure 11 Configuring Digital Outputs Double click the Logic Outputs block on the bottom right side of the schematic shown in Figure 8 to navigate to the next level schematic shown in Figure 13 126 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION Configuring Digital Outputs Figure 13 Logic Outputs Schematic Interface x Eg o F File Edit View Tools Options Window Help D LEERE Ye ueo G gt gt gt gt gt gt a gt gt gt Double click to edit this symbol To configure logic outputs in a dialog box Figure 14 click any output buffer in the schematic shown in Figure 13 PAC Designer Software User Manual 127 POWER MANAGER EXAMPLE IMPLEMENTATION Configuring Digital Outputs Figure 14 Logic Outputs Dialog Box Logic Outputs Pin Name User D
136. iption on the Waveform Editor Graphical Waveform Files The Waveform Editor is a graphical application that is used to create and edit wdl files Each waveform is given a user defined name and then edited to show transitions The Waveform Editor uses a data model called the Waveform Description Language WDL The language represents a waveform as a sequence of signal states separated by time intervals The language also has constructs that let you express the waveform pattern hierarchically However you do not have to be familiar with the Waveform Description Language to use the Waveform Editor Zooming In and Out Click the Zoom In button on the toolbar or the Zoom In button on the toolbar to activate the zoom cursor You can also choose View gt Zoom In and View gt Zoom Out to activate the zoom cursor 44 PAC Designer Software User Manual DESIGNING POWER MANAGER Devices Waveform Editor Stimulus Waveform Editor DESIGN File Edt View Object Tools Options Jump Help __ econ VMs Place the zoom cursor over the time of interest and click to zoom in or out Repeated clicks will continue to Zoom in or out To cancel the zoom in cursor right click 0 11 500us Y CLK_IN Wey Starting the Waveform Editor To generate or edit a stimulus file choose Tools gt Design Utilities Then select Waveform Editor from the Design Utilities list Opening the Default Stimulus file To open the default st
137. ispClock hardware If a suitable configuration cannot be found it will report the closest realizable configuration and allow you to choose another set of frequencies to attempt to configure the device for To use the ispClock Frequency Synthesizer 1 In the ispClock Frequency Synthesizer Window enter desired output frequencies in MHz in the Requested Output Frequency boxes 2 Select the desired output frequency tolerance from the Acceptable Tolerance list The default value is 0 01MHz 3 Enter the input reference frequency in MHz in the Input Frequency box Alternatively you can allow the Wizard to specify an input frequency by selecting the Suggest Input Frequency option 4 Click Synthesize to begin the search for a configuration In the event that the Wizard cant find a configuration that matches all of your requirements it will indicate this and present the closest match found 5 Transfer your design to a specified profile in the active PAC Designer schematic by clicking Write to Schematic 6 When you finish click Exit PAC Designer Software User Manual 103 DESIGNING ISPCLOCK DEVICES Procedures Using the ispClock Skew Editor The ispClock Skew Editor allows you to graphically configure an ispClock schematic to implement a requested set of output skews This utility allows you to drag clock edges and invert them to achieve a desired set of phase relationships among the devices outputs This tool is av
138. istered Ik type fip DUTE nan Dant anra Manictarad W huma fi Starting a Design Utility You can use a design utility to modify your schematic To start a design utility 1 With a device schematic open in the Main Window choose Tools gt Design Utilities The Design Utilities dialog box opens 2 From the list select the desired design utility When a selection is highlighted in the list a description of the design utility is displayed in the Design Utilities dialog box 3 Click OK Starting the Platform Manager Design Utilities To start a Platform Manager design utility 1 With a Platform Manager schematic open in the Main Window choose Tools gt Design Utilities The Design Utilities dialog box opens 2 From the list select the exe for HVOUT Simulator or 12C Utility 3 Click OK PAC Designer Software User Manual 63 DESIGNING PLATFORM MANAGER Devices Design Entry Using the PowerManager_HVOUT_Sim Utility The PowerManager_HVOUT_Sim Utility allows you to simulate the rise time of a power supply driven by an N Channel MOSFET and the HVOUT drivers on a Platform Manager device This simulator uses parameters from the MOSFET data sheet to build a model the circuit is then simulated based on inputs from the user interface To edit any values on the schematic within the utility simply double click the different circuit elements on the schemati
139. it elements on the schematic such as the FET HVOUT block resistors and capacitor This will open up dialog boxes to change the circuit parameters 24 PAC Designer Software User Manual DESIGNING POWER MANAGER Devices Design Entry Main Screen for the FET Simulator H OUT Simulator Close _ Simulate imulate Print Double clicking the circuit elements within the schematic will bring up dialog boxes for each parameter Once you have configured the set up hit the Simulate button and the results will be plotted The results can also be exported to a coma separated file to be used in a spreadsheet for other analysis or comparing different ramp rates with different FETs Dialog Boxes for the Simulator The dialog boxes for the HVOUT Simulator allow you to change the circuit parameters xi Enter the H OUT Charge Pump Output Voltage f 0 Volts 8 to 12 Cancel xi Enter the H OUT Charge Pump Output Source Current 0 5 u 0 5 to 400 Cancel PAC Designer Software User Manual 25 DESIGNING POWER MANAGER DEVICES Design Entry Enter the Yoltage of the supply that is connected to the Drain of the MOSFET fi 8 Volts 0 5 to 6 0 Cancel Load Resistance Enter an equivalent resistance that OK represents the load a fi ohms 0 001 to 100 000 Cancel External Capacitor Ei Use an external capacitor for very slow ramp rates fo pF 0 0 to 1 000 000 Cancel M
140. ith the sequence control logic LogiBuilder Sequence Control The Sequence Control section is the top window of the LogiBuilder window shown in Figure 20 There are 5 columns in this section gt Step This is the step number of a given instruction This step number is used by the branching instructions 134 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Sequence Control Sequencer Instruction There are basically six different instruction types Output Wait for If Then Else Go to Start Stop Timer and NOP Each of these instructions along with its application is described later Outputs This section specifies only the output pins that are toggled Interruptible If this is marked as No the exception condition is ignored If it is marked Yes then any of the exception condition if becomes true can force a branch to the exception routine gt Comment Enter comment for documentation Entering Power Management Algorithm into the Sequence Controller The power management algorithm is entered into the Sequence Controller by inserting an instruction at a given step The next step is to double click that new instruction to open a dialog box and enter the required parameters in it To introduce a new instruction at any step highlight that step number and press the Insert key The software opens a dialog box shown in Figure 21 Figure 21 Inserting a New Sequence Cont
141. its for the Boolean function to become true indefinitely For example if a power supply fails to turn on the Sequence Controller can be stuck at that Wait for Boolean instruction Some devices cannot withstand being left partially turned on for a very long period of time To deal with such cases Wait for Boolean with Timeout instruction is used This instruction turns on a supply and waits for a fixed period of time for it to turn on If the supply fails to turn on the Sequence Controller times out and jumps to shut down that section of the design This instruction is edited by the Edit Wait For Bool with Timeout properties dialog box shown in Figure 35 144 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Sequence Control Figure 35 Edit Wait For Bool with Timeout Properties Dialog Box Edit Wait For Bool with Timeout properties Instruction Preview Instruction Outputs Wait for Core_1 2_over_LTP AND I0_1 V8_over_LTP or 5 Core_1V2_En Cancel If Timeout Then Goto 6 Edit Boolean Expression Output Control Timeout if above condition is not satisfied by this time Timer2 212 99ms timeout _Edit Timeout properties A seniai Timer 3 1966 08ms timeout Timer 4 1966 08ms timeout On Timeout Goto Sequencer step Step 6 with Outputs Instruction is interruptible by an exception Comment If 1 2v supply does not turn on within 5 ms jump to shut
142. king SuperBIG SuperCOOL SuperFAST SuperWIDE sysCLOCK sysCONFIG sysDSP sysHSI sysl O sysMEM The Simple Machine for Complex Design TracelD TransFR UltraMOS and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and or other countries ISP Bringing the Best Together and More of the Best are service marks of Lattice Semiconductor Corporation Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies Disclaimers NO WARRANTIES THE INFORMATION PROVIDED IN THIS DOCUMENT IS AS IS WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY KIND INCLUDING WARRANTIES OF ACCURACY COMPLETENESS MERCHANTABILITY NONINFRINGEMENT OF INTELLECTUAL PROPERTY OR FITNESS FOR ANY PARTICULAR PURPOSE IN NO EVENT WILL LATTICE SEMICONDUCTOR CORPORATION LSC OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER WHETHER DIRECT INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OF OR INABILITY TO USE THE INFORMATION PROVIDED IN THIS DOCUMENT EVEN IF LSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION OR LIMITATION OF CERTAIN LIABILITY SOME OF THE ABOVE LIMITATIONS MAY NOT APPLY TO YOU LSC may make
143. lating the output voltage for a given trim resistor The first field is the output voltage of the DC DC converter when the trim pin is open This is usually one of the entries in the table or is calculated using a formula in the datasheet The two examples columns are also completed using the same table or the formula in the datasheet of the DC DC converter Note that one of the voltage values selected should be the maximum output voltage and the second voltage value should be minimum 176 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION Creating a DC DC Converter Library Entry voltage These voltage values need not be the actual output voltage used in the circuit board Finally enter the DC DC converter model name for example POL_XYZ and save the file d Creating a Library Entry for a Discrete DC DC Converter These types of DC DC converters are common when they are realized using switcher ICs switching and filter elements The output voltage is programmed by connecting two resistors Rfb and Rin The output voltage of the DC DC converter is calculated using the formula Vout Rfb Vref Rin Vref is the DC DC converter reference voltage When the DC DC converter used is of this type the dialog box shown in Figure 68 is used to create the library entry Figure 68 Creating a Library Entry for a Discrete DC DC Converter DC DC Converter Discrete Entry Values internal to the DC DC Convert
144. le bin and the Waveform Viewer application is launched automatically The Waveform Viewer starts with the design bin file loaded and displays the signals that were defined in the stimulus file The names of the waveforms that are added to the display are stored in a wav file so that the added waves will be displayed next time the Waveform Viewer is started Zooming In and Out Click the Zoom In button on the toolbar or the Zoom In button on the toolbar to activate the zoom cursor You can also choose View gt Zoom In and View gt Zoom Out to activate the zoom cursor Waveform Editor DESIGN Fie Edk View Object Tools Options Jump Help __ econ UMMM Place the zoom cursor over the time of interest and click to zoom in or out Repeated clicks will continue to zoom in or out To cancel the zoom in cursor right click 11 500us 8 y EKN WL Adding Signals to the Display You can add signals to the display from the Edit menu or from the Show Waveforms button of the toolbar To add a signal to the display 1 Choose Edit gt Show Waves or Click the Show Waves button of the toolbar as shown below to display the Show Waveforms Dialog Box 92 PAC Designer Software User Manual DESIGNING PLATFORM MANAGER DEVICES Waveform Viewer Results FA Waveform Viewer DESIGN1_VMON1_6K Da ES ee Oise Toot titre ome tia el S 2ean 2 S 2l 2 450 000 0 ns 700 000 2 Inthe Show Waveforms d
145. les generated during the compiling process 2 In PAC Designer or LogiBuilder choose File gt Export The Export Dialog Box opens Under Export What select VHDL File or Verilog File Under Export To select File and then click Browse to specify the file name and directory By default the system uses the vho extension name for VHDL file and vlg for Verilog file You can also change them to v and vhd as you like 5 Click OK The Verilog or VHDL file in gate level is generated in the specified directory To simulate the design with the exported HDL 1 Before running simulation with Active HDL copy and reference the powr VHDL and ovi_powr Verilog simulation libraries 40 PAC Designer Software User Manual DESIGNING POWER MANAGER DEVICES Automatic ABEL Import Waveform Editor gt Copy library files from lt PAC Designer_install_path gt active hdl Vlib to lt Active HDL_install_path gt Vlib Add the following lines to the lt Active HDL_install_path gt Vlib library cfg file powr SACTIVEHDLLIBRARYCFG powr powr 1lib ovi_powr SACTIVEHDLLIBRARYCFG ovi_powr ovi_powr lib Create a test file for the exported HDL netlist Create an Active HDL project add the HDL and the test file to it and run simulation Simulating a Power Manager Design with Lattice Logic Simulator To simulate a design with Lattice Logic Simulator it must first be entered or edited using both the schematic page
146. ll supplies turne SMO Step 2 Wait For Core_1 2_OK AND IO_1V 8_OK Core_1Y2_En 1 IO_1 8 no Turn on all supplies and wai SMO Step 3 Wait For 212 99ms using timer 2 no Start reset pulse stretch SMO Step 4 Reset_CPU 1 no Release CPU Reset SMO Step 5 Start timer 3 524 29ms no This starts the timer and tur SMO Step 6 IF NOT Core_1 2_OK OR NOT IO_1V8_OK WDT_Intr 1 Wait for supply Fault or Then Goto 6 watrchdog tiemr expiration Else If Timer 3 Then Goto 4 with WDT_Intr 0 Else Goto 7 SMO Step 7 Reset_CPU 0 no SMO Step 8 Halt end of program no lt Exception ID Boolean Expression Outputs Exception Handler IF NOT WDT_Trig lt no outputs sp Starts at step 4 lt end of exception table gt Exception Condition section of the LogiBuilder SMO Equation Supervisory Logic Equation Macrocell Configuration Comment lt end of supervisory logic table gt The sequence control in Figure 46 is as follows Step 0 Start up marker Step 1 Waits for the calibration with all supplies turned off and with reset CPU active Step 2 Turns on the 1 2V and 1 8V supplies and waits for them to reach regulation levels PAG Designer Software User Manual 155 POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Exception Conditions Step 3 Waits for 200ms Step 4 Releases CPU reset to complete the reset pulse stretch function Step 5 Starts Restarts the 500ms watchdog timer Step 6 Monito
147. lues are stored into the source file The Options button opens the following dialog box Figure 70 for fine tuning the calculated resistor values Figure 70 Optimizing Resistor Values Trim Configuration Options ElA Resistor Standard Maximum DAC Code Range 1 127 Max Supply Adjustment Range Attenuation Crossover Voltage Open External Resistor s Threshold 10000000 Vbpz Selection Auto EIA Resistor Standard Limits the resistor selection to EIA 12 ElA24 EIA48 EIA96 EIA192 It also provides a method to calculate the exact resistor values The selection of this option depends on design requirements Maximum DAC Code Range Used to provide additional headroom in the DAC code for maximum voltage variation This is to account for the errors in resistor values and the DC DC converter inaccuracies Max Supply Adjustment Range This is the maximum margin voltage range with respect to the nominal value that is specified on profile 0 If the design requires margining of 10 this value is set to 10 Attenuation Crossover Voltage The maximum input voltage for the ADC is 2 048V If this ADC is used for measuring voltage higher than the Attenuation Crossover Voltage the on chip 1 3 attenuator should be turned on This allows the maximum voltage input to the ADC to increase to 6 144V This entry sets the voltage at which the attenuator should be switched on Open External Resistor s Threshold The maximum resistor v
148. m 3 Type in the number of times to repeat the waveform in the Repeat box If the simulation time is unknown select the Repeat Forever box and the pattern will be repeated for the maximum duration of either the simulator or the Waveform Viewer 0 10 000 Selected Entire Pattern CLK_IN EG Scale nH Repeat eooc I Foreve Waveform Viewer Results This section contains concepts procedures and user interface description on the Waveform Viewer Functional Logic Simulation Waveform Viewer When the simulation is complete the results are stored in a binary file bin and the Waveform Viewer application is launched automatically The Waveform Viewer starts with the design bin file loaded and displays the signals that were defined in the stimulus file The names of the waveforms that are added to the display are stored in a wav file so that the added waves will be displayed next time the Waveform Viewer is started Zooming In and Out Click the Zoom In button on the toolbar or the Zoom In button on the toolbar to activate the zoom cursor You can also choose View gt Zoom In and View gt Zoom Out to activate the zoom cursor 48 PAC Designer Software User Manual DESIGNING POWER MANAGER DEVICES Waveform Viewer Results Waveform Editor DESIGN File Edt View Object Tools Options Jump Help Place the zoom cursor over the time of interest and click to zoom in or out Repeated clicks will cont
149. n names JTAG control bit setting 12C setting ispPAC POWR1014A only Target Device ispPAC POWR1220AT8 Mapped to VMON 1 to 10 of ispPAC POWR1220AT8 The actual threshold voltage in the target device may be shifted by a few mill volts Same pin names as source Same logical names as source Same glitch filter setting per pin as source Same window comparator setting as source Mapped to IN1 to 4 of ispPAC POWR1220AT8 Same pin names as source Same JTAG control bit setting for IN1 pin as source Same 12C setting for IN2 to 4 as source PAC Designer Software User Manual DESIGNING POWER MANAGER DEVICES Design Entry Table 2 Design Mapping Continued Source Device ispPAC POWR1014 A 12C address ispPAC POWR1014A only Timers 1 4 MCLK amp PLD clock setting Output 3 to 14 Output pin names 12C control setting of the output pin SMBAlert setting HVOUT 1 2 Output type charge pump digital output HVOUT output voltage setting HVOUT source current setting Target Device ispPAC POWR1220AT8 Same I2C address as source Same Timers 1 4 setting as source MCLK and PLD clock setting Mapped to output 5 16 of ispPAC POWR1220AT8 Same output pin names as source Same 12C control setting of the output pin as source Same SMBAlert setting as source Mapped to HVOUT 1 2 of ispPAC POWR1220AT8 Output type charge pump digital output setting maintained HVOUT output voltage setting maintained HVOUT source current setting mai
150. n several different trim channels or projects without having to re enter its parameters each time The flow is illustrated below 54 PAC Designer Software User Manual DESIGNING PLATFORM MANAGER Devices Design Entry H Target et W Voltages PE _ _ Supply 4 Type DAC Codes A DAC Range A ADC F i Attenuator bit DC DC Library DC DC 4 BM nid Builder Libary iota Error Files ialog messages amp ao el Diagnostics Trim gt Examples or Trim Interface resistor values Feedback Components FA Y i Profiled Mode j Options Modifications to existing DC DC library files must be made from within the DC DC Library Builder Changes in the desired target voltages or supply selection are done from the Trim Configuration dialog box It is strongly advised that library files not be modified while trim cells are being configured because this can create confusion and make it difficult to detect errors in your work If a discrete supply is to be used at several different voltages a separate library entry for each unique output voltage should be created The Library Builder stores its files in the DCtoDC_Library directory which is located under the main PAC Designer install directory The Trim Configuration dialog box import facility launches a file browser in order to make it possible to import library files created in earlier versions of PAC Designer or library files that have b
151. neral Capabilities of PAC Designer 1 Starting PAC Designer 2 Process Flow 3 Exporting Importing Data 3 ispPAC Device Summary 5 Designing Power Manager Devices 11 Design Entry 11 Schematic Entry 11 Procedures 15 LogiBuilder 32 LogiBuilder Sequence Controller Instruction Set 32 Designing Control Sequences With LogiBuilder 34 Editing Pin Settings with LogiBuilder 34 Viewing Messages Errors in LogiBuilder 34 Editing Multiple State Machines 35 Creating and Editing an ABEL Design 35 Entering Supervisory Equations 36 LogiBuilder Error Messages 36 Functional Logic Simulation 40 Simulating a Power Manager Design with Aldec Active HDL 40 Simulating a Power Manager Design with Lattice Logic Simulator 41 Automatic ABEL Import Waveform Editor 41 Graphical Waveform Files 41 Zooming Inand Out 42 Starting the Waveform Editor 42 Importing an ABEL File 43 Creating and Editing Waveforms 43 Waveform Editor Stimulus 44 PAC Designer Software User Manual CONTENTS Chapter 4 Graphical Waveform Files 44 Zooming Inand Out 44 Starting the Waveform Editor 45 Opening the Default Stimulus file 45 Adding a Signal 45 Changing a signal level 46 Changing the duration of asignal 47 Setting the default time scale 47 Repeating a pattern 48 Waveform Viewer Results 48 Functional Logic Simulation Waveform Viewer 48 Zooming Inand Out 48 Adding Signals to the Display 49 Adding the Step bus to the Display 49 Setting the Ste
152. ngle OUTPUT instruction can be used to simultaneously change the status of any number of output signals WAIT FOR lt Boolean Expression gt The WAIT FOR lt Boolean expression gt instruction suspends execution of the sequence until the specified expression becomes TRUE 32 PAC Designer Software User Manual DESIGNING POWER MANAGER Devices LogiBuilder WAIT FOR lt Boolean Expression gt with Timeout The WAIT FOR lt Boolean expression gt with Timeout instruction suspends execution of the sequence until the specified expression becomes TRUE or the selected timer expires WAIT FOR lt time gt USING TIMER lt 1 4 gt The WAIT FOR lt time gt instruction is used to specify a fixed delay in the execution sequence The value of lt time gt is determined by which timer TIMER1TIMERA is specified IF lt Boolean Expression gt THEN GOTO lt step x gt ELSE GOTO lt step y gt The IF THEN GOTO instruction provides the ability to modify sequence flow depending on the state of inputs If lt Boolean expression gt is TRUE the next step in the sequence will be lt step x gt otherwise the next step will be lt step y gt IF lt Boolean Expression gt THEN GOTO lt step x gt ELSE If Timer lt n gt GOTO lt step y gt ELSE GOTO lt step z gt This instruction provides the ability to modify sequence flow depending on the state of inputs with an additional timeout feature If lt Boolean expression gt is TRUE the next step in th
153. ning an ispPAC device To communicate with the ispPAC device an appropriately configured download cable must be installed between a parallel port of the PC and the JTAG serial port of the ispPAC device Setup of the parallel printer port and the driver that constrains programming times is accessed through the Cable and I O Port Setup Dialog Box The software installation procedure uses operating system information to configure PAC Designer accordingly The printer port is assigned to be compatible with a majority of computers but is not tested by the install procedure Download Cable Overview When programming devices from a PC using PAC Designer a properly configured cable between the PC parallel port and the programmable device is required The Lattice isoDOWNLOAD Cable for the PC provides compatible PAC Designer Software User Manual 107 DEVICE PROGRAMMING Download Cable Overview with all Lattice in system programmable parts This appendix details the configuration of the cable and includes pin connector and schematic information The isoDOWNLOAD Cable for the PC is designed to facilitate in system programming of all Lattice Semiconductor ISP devices on a printed circuit board directly from the parallel port of a PC With in system programmability hardware functions can be programmed and modified in real time on the system board to provide additional product features shorten system design and debug cycle time enhance produc
154. not employ an M divider N Divider This divider divides the feedback signal before feeding it to the phase detector It may be programmed for division ratios ranging from 1 to 32 The ispPAC CLK5312S does not employ an N divider VCO and Loop Filter This block allows you to select a loop filter for performance optimization Lock Detect This block allows you to specify the operating mode for the LOCK output pin You may select between either phase lock or frequency lock mode and may also specify the number of cycles the loop must be locked before the LOCK signal is asserted Skew Manager This block allows you to program timing skews delays for each output V Dividers These dividers divides the output of the VCO before feeding it to output drivers They may be programmed for division ratios ranging from 2 to 64 in even steps On ispPAC CLK53128S the V divider settings range from 1 to 32 Output Banks These blocks allow you to specify the output logic standard polarity skew rate and series impedance for each output Using Cursor Feedback to Edit Schematics Each ispPAC device has an schematic specific to the device The Schematic Window can be edited and supports three editing styles 100 PAC Designer Software User Manual DESIGNING ISPCLOCK DEVICES Procedures gt Double click gt Click and drag gt Menu keyboard based symbolic name entry Cursor Feedback The cursor provides feedback when editing sch
155. ntained HVOUT sink current setting Entire LogiBuilder program HVOUT sink current setting maintained Mapped to entire LogiBuilder program of ispPAC POWR1220AT8 Procedures This section provides step by step procedures for completing tasks you can perform in designing Power Manager designs Creating a New Schematic You can create a new schematic or open an existing schematic To create a new schematic 1 Choose File gt New The New Dialog Box opens Select the schematic for the ispPAC device you wish to design Click OK The device schematic window is displayed Editing a Schematic You can edit a schematic using several techniques including Double Click You can double click over each symbol in the Schematic Window to invoke the appropriate dialog box to edit the item See Editing Schematic Symbols PAC Designer Software User Manual 15 DESIGNING POWER MANAGER Devices Design Entry Click and Drag to Connect wires Feedback Drag from the point furthest from the resistor to close the connection IA Inputs Drag from Instrumentation Amp input to an input or output terminal wire Disconnect wires Connections can be opened by dragging the wire back to its starting point Menu Entry gt Choose Edit gt Symbol The Edit Symbol dialog box opens This shows a list of all symbols seen on the schematic To edit a symbol double click the desired symbol on the list and choose the Edit button
156. nthe Pin Definitions Window double click the pin that you want to edit 3 Inthe Pin Definition Dialog Box make editable changes and click OK Viewing Messages Errors in LogiBuilder You can view messages and errors in LogiBuilder 34 PAC Designer Software User Manual DESIGNING POWER MANAGER Devices LogjiBuilder To view messages and errors Choose View gt Messages Errors The Messages Error Window opens Editing Multiple State Machines The LogiBuilder supports multiple state machines for power up sequence and control for some Power Manager devices The state machines are defined separately but can interact through nodes or common logic functions Each state machine is built up in a separate tab in the Sequence and Supervisory Logic window The logic for the full design is then compiled and fitted to generate a single JEDEC file You can use the MSM Manager Dialog Box to add or delete state machines To open the dialog box make sure the Sequence and Supervisory Logic window is open and the Sequencer Instructions table or the Exceptions table is active and then choose Edit gt Multiple State Machines Multiple state machines are supported for the Sequencer Instructions table and the Exceptions table only The settings in the Supervisory Equations table always apply to the entire design Creating and Editing an ABEL Design You can create and edit an ABEL design for a Power Manager device To create and edi
157. o configure the analog inputs double click any of the comparators to open the dialog box shown in Figure 10 122 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION Configuring Analog Inputs Figure 10 Analog Input Settings Dialog Box Analog Input Settings Pin Name Schematic Net Name Logical Signal Name luonitoring Type Trip Point Selection 64 us Glitch Filter Window hlode Brd_12 _OK ov oy 3 236V x meea WMONI 7 ard 12 Volts Iv v Cancel Brd_12 _Over_Min A lt 4 Brd_3V3_OK WON2 7 Brd 3 3 ae wv Vv Brd_3 V3_Over_LTF 1_12 V_Over_Currer WMONS 7 ISENSE 12 _12 V_Over_SOA_ _3 3_Owver_Currer Sense 3 3V _343_Over_SOA_ VI_OK VA_Ower_LTP v2_0K V2_Ower_LTP VB_OK V83_Over_LTP WONSA WMONS_B WONI A WONS _B WMONID_A WMON10_B Brd_5 v_OK rd Sos Brd_5 _Ower_LTP _5 _Over_Current Sense SV 15V _Over_S0A Li S lt i Q 4 S lt i lt 4 ON4 ow c lt i Q lt 4 i 4 z 4 Q lt 4 c lt i Q lt 4 uv 7 lt 4 c lt i lt 4 Cc lt i lt 4 G lt i Q lt 4 G lt i Q lt 4 a w m T mon weit wa jaan diel elds 4 oo i4 o 4 ONI v G lt 4 The following parameters of each of the analog inputs can be accessed through the dialog box shown in Figure 10 The names of these parameters are shown on top of each of the columns gt
158. on Application The previously described Wait for Timeout instruction starts the timer and waits for it to expire in that same step In some cases you may want to just start the timer at one step and check on it at a completely different step For example you can implement a watchdog timer function where a timer is started at one of the steps and the sequence control can monitor for timer expiry at a different step while performing different functions There are 2 sub types of timer control instructions Start Timer The Start Timer instruction is used to start a given timer through the dialog box shown in Figure 37 146 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Sequence Control Figure 37 Start Timer Dialog Box Start Timer Timeout Timer 2 Timer 3 Timer 4 5 12ms timeout 212 99ms timeout 1966 08ms timeout 1966 08ms timeout Edit Timeout properties Outputs Core_1V V2_En 1 Instruction is interruptible by an exception Comment Output Control This starts the timer and turns the supply on simulatanioush Select the timer that should be started in the top section of the dialog box you can change the timer value by clicking Edit Timeout properties It is also possible to alter any output status In this case the Timer 1 is started and the 1 2V supply is turned on at the same time The Sequence Controller jumps to the next step Re executi
159. on of Start Timer during a sequence control algorithm stops and restarts the same timer Note The Stop Timer instruction step cannot be a target of branch instruction Stop Timer The Stop Timer instruction stops the timer It can be configured using the following dialog box Figure 38 PAC Designer Software User Manual 147 POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Sequence Control Figure 38 Stop Reset Timer Dialog Box Stop Reset Timer Timeout 5 12ms timeout 212 99ms timeout Cancel 1966 08ms timeout 1966 08ms timeout Edit Timeout properties Outputs Output Control Instruction is interruptible by an exception Comment If Then Else Instruction There are 2 types of If Then Else instructions gt lf Then Else This instruction checks for a Boolean expression If it is true it goes to the step indicated by the Then section If the Boolean expression is false it jumps to a different branch indicated by the Else section This instruction is used to control the flow of the sequence control program Along with that this instruction can also activate different outputs depending the Boolean logic status gt lf Then Else with Timeout This instruction in addition to functioning like the instruction above checks on a timer expiry and provides a third branch address with another output control section If Then Else Application This instruction can be used to poll
160. onal Logic Simulation After the design has been entered it can be simulated Functional simulation is used to verify the correctness of the design but does not simulate gate delays or analog transient analysis A stimulus file is used to tell the simulator how and when the input signals change state When the Aldec Active HDL simulation tool is used for a Platform Manager design the CPLD and FPGA portions can be simulated at the same time When the Lattice Logic Simulator is used only the CPLD portion of the design can be simulated To simulate a Platform Manager design use either of the following methods gt Simulating a Platform Manager Design with Aldec Active HDL gt Simulating a Platform Manager Design with Lattice Logic Simulator Simulating a Platform Manager Design with Aldec Active HDL This procedure requires that the licensed Diamond software and all its components have been installed on the user s computer before PAC Designer The components include all of the following in addition to the base Diamond for Windows gt FPGA support for MACHXO MACHXO2 and Platform Manager Synplify Pro for Lattice gt Active HDL Lattice Edition gt Programmer Drivers To simulate a Platform Manager design with Aldec Active HDL 1 Create a new Platform Manager design or open a previous one by choosing File gt New or File gt Open PAC Designer Software User Manual 79 DESIGNING PLATFORM MANAGER Devices Function
161. onfiguration file for easy recall the next time the simulator is used Further documentation is available in the Aldec Active HDL online Help that accompanies the tool Choose Help gt Online Documentation You can export digital elements timers and the PLD core of a Platform Manager device to a Verilog or VHDL file and then use the exported HDL to perform functional simulation in Aldec Active HDL 80 PAC Designer Software User Manual DESIGNING PLATFORM MANAGER Devices Functional Logic Simulation Figure 2 Wait for AGOOD HVOUT1 0 HVOUT2 0 HVOUT3 0 HVOUT4 Wait for RESET_ALL Wait for VM4_5V_OK Wait for 1048 58ms using timer 3 PAC Designer Software User Manual 81 DESIGNING PLATFORM MANAGER Devices Functional Logic Simulation Figure 3 File Edit View Options Window Help D Sug m E Pma Run Waveform Editor Compile LogiBuilder Design Run Simulator Aldec Active HDL Simulator Cre nie Lattice Gate Level Simulator Design Utilities g E amp 07_DevKitDemol PAC File List Manager Download All Upload C aDesigns LPTM10_12107_Dev_Kit_Demo1 PTM10_12107_DevKitDemo1 PAC Verify Read IDCODE PlatformDemo Auto Calibrate e pee apee Supervisory Logic CPLD Ca n fos step Sequencer Instruction Outputs Int Commen SMO Step 0 Begin Startup Sequence no CPLD Log g SMO Step1 Wait for AGOOD no SMO Step 2 HVOU
162. ot the intent Symptom This would typically result in an endless loop in your design Warning 6 Program may not terminate falls off the end Reason Last instruction is not a Goto or IffhenElse that performs a Goto self or Goto a_previous_step 76 PAC Designer Software User Manual DESIGNING PLATFORM MANAGER Devices LogiBuilder Discussion Most users will not get this error because End Program instruction is always present Users that must optimize code by removing the End Program instruction will be susceptible to this error Currently we do not allow removal of that instruction Error 7 lffhenElse instruction is missing BoolExpr Error 8 At least one OUTPUT instruction is required with at least one write Reason The ABEL language used to implement the PLD requires at least one output Remedy Declare and assign at least one output of the device in the LogiBuilder Sequencer Instruction Error 9 OUTPUT instructions must use macrocells configured as JK Reason Macrocells configured as JK provide the expected set bit and it stays set behavior If the macrocell were to be configured as D setting it would only last for one clock Error 10 Exception has empty Boolean Expression Error 11 Output cannot be set asynchronously by an exception unless assigned by an instruction or supervisory equation Reason The ABEL language used to implement the PLD requires this W
163. p bus Radix 51 Using Markers 51 Printing the Results 52 Designing Platform Manager Devices 53 Design Entry 53 Concepts 53 Procedures 57 LogiBuilder 70 LogiBuilder Sequence Controller Instruction Set 70 Designing Control Sequences with LogiBuilder 72 Editing Pin Settings with LogiBuilder 72 Viewing Messages Errors in LogiBuilder 73 Editing Multiple State Machines 73 Creating and Editing an ABEL Design 73 Entering Supervisory Equations 74 Importing HDL Modules to a Platform Manager Design 75 LogiBuilder Error Messages 75 Functional Logic Simulation 79 Simulating a Platform Manager Design with Aldec Active HDL 79 Simulating a Platform Manager Design with Lattice Logic Simulator 84 Automatic ABEL Import Waveform Editor 84 Graphical Waveform Files 85 Zooming In and Out 85 Starting the Waveform Editor 85 Importing an ABEL File 86 Creating and Editing Waveforms 86 Waveform Editor Stimulus 87 Graphical Waveform Files 88 Zooming In and Out 88 Starting the Waveform Editor 88 Opening the Default Stimulus file 88 Adding a Signal 89 Changing a signal level 89 Changing the duration of a signal 90 Setting the default time scale 90 Repeating a pattern 91 Waveform Viewer Results 91 vi PAC Designer Software User Manual CONTENTS Functional Logic Simulation Waveform Viewer 92 Zooming Inand Out 92 Adding Signals to the Display 92 Adding the Step bus to the Display 93 Setting the Step bus Radi
164. pears to verify that the device equals the schematic If the device does not equal the schematic the Verify dialog box states that verification failed Performing Auto Calibrate on a Device You can perform an auto calibrate on a device using the Auto Calibrate command 114 PAC Designer Software User Manual DEVICE PROGRAMMING Procedures To perform auto calibrate on a device With the device connected to your computer with a download cable and applied power choose Tools gt Auto Calibrate The device is auto calibrated PAC Designer Software User Manual 115 DEVICE PROGRAMMING Procedures 116 PAC Designer Software User Manual sas LATTICE Chapter E SEMICONDUCTOR Power Manager Example Implementation Designs in any of the Power Manager devices can be implemented using the PAC Designer software tool In addition the PAC Designer software provides tools to simulate the power management design download the design into a device through parallel port or USB and toggle registers in the device dynamically during device operation The PAC Designer software can be downloaded from the Lattice Web site free of charge This section demonstrates the implementation of a complete Power Manager Design example using the PAC Designer Software Design Example Implementation Steps Designing with the PAC Designer software involves in the following main steps 1 Create Open power management design Config
165. ption Handler lt end of exception table gt SM0 Equation Supervisory Logic Equation Macrocell Configuration lt end of supervisory logic table gt Step 0 No action PAC Designer Software User Manual 153 POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Sequence Control Step 1 Waits for the calibration to complete and sets the watchdog timer output to logic 1 Step 2 NOP does nothing Step 3 Starts a 500ms timer Step 4 If WDT_Trig signal is 0 restarts the 500ms timer If the timer expires sets the interrupt to logic 0 and restarts the timer If the WDT_Trig signal is at logic high waits at the same step until the trigger reaches 0 or the timer expires As you see the NOP instruction provides a method to restart the timer by overcoming the limitation of no direct jump allowed to a timer control instruction Halt Instruction The Halt instruction stops the execution of the sequence The last Halt instruction is normally prevented to preserve a fail safe stopping point for a sequence In cases where sequence flow is controlled by other means the last Halt instruction in the sequence window can be deleted You can enable the deletion of the last halt instruction by choosing Options gt LogiBuilder Options in a LogiBuilder window Figure 45 The following dialog box will open Figure 45 Allowing Deletion of the Last Halt Instruction LogiBuider options x Sequence Optimizat
166. r Manual POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Sequence Control Figure 43 Edit Goto Instruction Properties Dialog Box Edit Goto instruction properties x Step number Step 0 z Cancel Outputs Output Control Instruction is interruptible by an exception Comment The target Goto step can be set using the Step number pull down menu You can set the outputs also along with this instruction NOP Instruction The NOP instruction basically does nothing This instruction is necessary to enable a branch to terminate in a step previous to a timer control instruction such as the Wait For Timeout Start Stop Timer or If Then Else with Timeout instructions Figure 44 Watchdog Timer Implementation PAC Designer Design1 PAC Sequence and Supervisory Logic DAR T Eile Edit View Tools Options Window Help GF x Ose OS 4e Qlanrng Pale i er El YY e f step Sequencer Instruction Outputs rt Comment l SMO Step 0 Begin Startup Sequence no ispPAC POWR 1220478 reset SMO Step 1 Wait For AGOOD WDT_Intr 1 no Start with all supplies turned off and SMO Step 2 NOP no SMO Step 3 Start timer 3 524 29ms no This starts the timer and turns the su SMO Step 4 If NOT WDT_Trig WDT_Intr 1 no Wathcdog timer Then Goto 2 Else If Timer 1 Then Goto 2 with WDT_Intr 0 Else Goto 4 SMO Step 5 Halt end of program Exception 1D Boolean Expression Outputs Exce
167. r Sequence and Supervisory Logic PAC Designer Design3 Sequence and Supervisory Logic BEE File Edit view Tools Options Window Help S kg _ J Pis bsi EL EA Ga step Sequencer Instruction oups mt Comment SMO Step 0 Begin Startup Sequence no ispPAC POWR12204T8 0 SMO Step 1 Wait for AGOOD no SMO Step 2 Begin Shutdown Sequence no SMO Step 3 Halt end of program no Exception ID Boolean Expression Outputs Exception Handler lt end of exception table gt SMO Equation Supervisory Logic Equation Macrocell Configuration Comment lt end of supervisory logic table gt This window is divided into 3 sections Sequence Control Enter a sequence of events and actions in the power management algorithm There can be more than one sequence control algorithms Each of these sequence control algorithms executes in parallel The sequence control algorithm is made up of a number of steps Each of these steps contains an instruction The sequence control engine executes each of the instructions using the 250KHz PLD clock Some of the instructions get executed in one clock cycle or 4us while some instructions require many cycles gt Exception Control This can be considered as an interrupt to the sequence control flow Each sequence control algorithm has a separate Exception Control section gt Supervisory Logic Equation This enables implementation of logic made up of equation that can run in parallel w
168. r Software User Manual vii CONTENTS Configuring Timers 131 Implementing Power Management Algorithm in LogiBuilder 133 LogiBuilder Sequence Control 134 Entering a Program into the Sequence Controller 135 Sequencer Instructions 136 LogiBuilder Exception Conditions 155 Creating an Exception Condition 156 LogiBuilder Supervisory Logic 160 Digital Timing Simulation Using PAC Designer 164 Implementing Multiple State Machines 167 Creating a DC DC Converter Library Entry 169 Appendix Recommended References 183 Index 185 viii PAC Designer Software User Manual sae LATTICE Chapter l E SEMICONDUCTOR Introduction to PAC Designer PAC Designer is the complete design environment for Lattice Semiconductor Power Manager Platform Manager and ispClock PAC Designer permits real time design of analog circuits using the Lattice ispPAC family of components With PAC Designer you can configure and interrogate any of the ispPAC products using its intuitive point and click features Your design can be quickly downloaded to the device where it is stored permanently Each isoPAC product includes proprietary on chip circuitry to store your design in its EZCMOS memory Design Examples Included with the software are many design examples for Power Manager Platform Manager and ispClock devices A brief description of each example is included in the Design Examples dialog box which you can access from the File menu More comple
169. r Spacing rise Eight Positions _ Veo 5Volts TDO RJ 45 Connector 25 pin a Positions Parallel a Port Adapter Olaf 6 Snp acitor NC To ncpLug System Board TMS GND Note Capacitor Recommended on System Board Error Messages The following is a listing of various possible programming error messages and their causes Error Simulation not executed Current Input and Output Node selections cause output to be zero Explanation The simulation output was zero because there was a break in the signal path from Input to Output Cause Typically Input selection in Simulator Options dialog box was not connected to an input Error PACJTAG virtual device driver VxD is not loaded in memory Possible Causes gt The PACJUTAGVXD file is missing or has been moved gt Registry settings are missing or incorrect Error See Help for Details Search for PACUTAG SYS Cause This is typically due to an incompletely installed driver Refer to Installing the PACUTAG SYS Device Driver WinNT 2000 for details You must restart your PC after PAC Designer installation to let the driver start Remedy Re boot Windows manually install the driver or re install PAC Designer PAC Designer Software User Manual 109 DEVICE PROGRAMMING About UES Bits Error Kernel Mode driver is not loaded in memory Possible Causes 1 You must reboot after installation for the driver to be loaded 2 The PACJUTAG S
170. r the Sequencer Instructions table and the Exceptions table only The settings in the Supervisory Equations table always apply to the entire design Figure 60 shows the MSM Manager dialog box opened using the POWR1220AT8 2_cPCI_HS_Seq_RG_Sup PAC example design 168 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION Creating a DC DC Converter Library Entry Figure 60 MSM Manager Dialog Box MSM Manager Ea State Machines SM 0 cPCI Hotswap Controller Add SM SM 1 On Board Management Delete SM State Machine Name Open 3rd SM Cancel To add a state machine selecting the place where you want to enter the next state machine enter the name for the new state machine and click Add SM The window for sequence control will open Note that the additional state machine has been created and opened for code edit After the editing the design can be recompiled and processed as discussed elsewhere in this manual Designing Trimming and Margining Networks Using PAC Designer Determining the required resistor topology involves finding a solution for a number of nodal equations and an understanding of the error amplifier architecture of the DC DC converter In addition the design can be iterated until the solution yields standard resistor values The PAC Designer software automates the process of determining the resistor topology while using standard resistors in the resistor network Calculating the
171. r use These User Electronic Signature UES bits can be written to and read out through the JTAG programming interface and provide you with a means of recording custom identification information into individual isoPAC 110 PAC Designer Software User Manual DEVICE PROGRAMMING Procedures devices This customization feature can be used in several ways On the level of the individual ispPAC devices the UES bits can be used to identify differently programmed versions or revision levels At the board assembly level the isoPAC s UES bits can be used to record a lot id or date code to facilitate production tracking and provide field traceability Additionally the UES bits can be used to store miscellaneous option calibration or other system parameters in systems employing low cost micro controllers that lack internal EECMOS Memory To be able to read the UES bits the electronic security fuse must not be programmed Procedures This section provides step by step procedures for completing device programming tasks Installing the PACUTAG SYS Device Driver WinNT 2000 The setup program installs the PACUTAG SYS device driver Use this topic if you need to install it manually for any reason Note Administrative privileges are required for the installation of any device drivers on Windows NT and Windows 2000 The JTAG Interface for Windows NT 4 0 and Windows 2000 is implemented with PACUTAG SYS a kernel mode device driver compat
172. r_Timer or Start_Timer instruction 36 PAC Designer Software User Manual DESIGNING POWER MANAGER Devices LogiBuilder Reason Timer_Gate signal must have a low level then a high level for timer to operate To do this for an instruction at step N the instruction at step N 1 must set Timer_Gate 0 then Instruction N can set Timer_Gate 1 Therefore N cannot be zero Discussion With the default LogiBuilder program template you cannot get this error because Begin Startup Sequence instruction is always present But users who choose to optimize code by removing the Begin Startup Sequence instruction will be susceptible to this error Error 1 WaitFor_Timer or Start_Timer instruction cannot be branch target of a Goto or IfThenElse Error 2 WaitForTimer instruction cannot be branch target of an exception Reason If you insert or delete an instruction that is the target of a Goto and now this error is possible you are not warned at that time Technical Reason Same as step zero above Timer_Gate signal must have a low level then a high level for timer to operate To do this for an instruction at step N the instruction at step N 1 must set Timer_Gate 0 then Instruction N can set Timer_Gate 1 Therefore N cannot be zero Remedy Insert an additional instruction before the timer based instruction and make that the branch target Error 3 Instructions that start a timer may not follow one another This
173. rm Editor Stimulus Changing the duration of a signal You can make coarse adjustments of a transition by clicking and dragging with the mouse A precise duration can be edited using the Selected dialog box The contents of the dialog box will change based on where and which waveform is selected using the mouse To change the duration of a signal 1 Select the waveform you wish to change 2 Choose Object gt Edit Mode to display the Selected Dialog Box as shown below 3 Enter the new value in the Duration edit window 0 10 000 000 20 000 LKN WLLL MMMM Selected Bit Pulse High x Setting the default time scale Before drawing the waveforms you may need to enter timing information for the simulation using the Timing Options dialog box This dialog box is used to set the resolution of the time scale that is placed at the top of the edit window To set simulation timing values 1 Choose Options gt Timing Values The Timing Options dialog box opens 2 Select the time units you want Timing Options xj ime unts 10 ms Coi C us Coo Cis 9001 C ps Save As Detauts PAC Designer Software User Manual 47 DESIGNING POWER MANAGER Devices Waveform Viewer Results Repeating a pattern You can repeat a waveform pattern with the Select dialog box To repeat a pattern 1 Select the entire waveform as shown below 2 Double click a row to select first the Low segment then the entire wavefor
174. rol Instruction at a Given Step Insert Step Insert a Sequence Controller Step Wait for lt Boolean condition gt Wait for lt timeout value gt Wait for lt Boolean condition gt with Timeout Halt lf Then Else lf Then Else with Timeout Goto Start Timer You can set parameters of the instruction after it is created After inserting an instruction it can be customized to perform the required function For example Figure 21 shows the Outputs instruction highlighted Click the OK button this outputs instruction will get inserted at that step After inserting that step double click that instruction to open a new dialog box in which you can select all the outputs that should be turned on or off Introducing the expressions into Exception condition and Supervisory Equations sections are similar The steps are as follows Select the line on which the expression should be entered and double click it to open a dialog box Customize it and close the dialog box Entering a Program into the Sequence Controller When the LogiBuilder window is launched the Sequence Controller starts with four instructions gt Begin Startup Sequence The sequencer enters the first step when the device is powered on The first time when the control enters this step all PAC Designer Software User Manual 135 POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Sequence Control outputs are reset to their respective power on reset v
175. rs for failure of the 1 2V and 1 8V supplies as well as watchdog timer fault If a power supply fault is detected the Sequence Controller jumps to shut down with the reset activated If the watchdog timer expired toggles the WDT_Intr output signal jumps back to step 4 restates the watchdog timer at step 5 and resumes fault monitoring at step 6 So how the watchdog timer is re triggered This is handled by the exception condition The step 6 has the interruptible flag enabled This means that the exception condition can interrupt the sequence control flow The watchdog trigger input is being monitored by the exception condition EO The EO is monitoring for a low going pulse of the watchdog timer When it happens the sequence control program is forced to jump to step 4 the step before the restart of watchdog timer and the code restarts the time in step 5 and jumps to step 6 to resume monitoring for voltage fault and the expiration of the watchdog timer Creating an Exception Condition To create an exception condition double click lt end of exception table gt or select the end of exception table and press the Insert key The LogiBuilder inserts a raw exception condition as shown in Figure 47 156 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Exception Conditions Figure 47 Exception Condition Fresh Entry E0 PAC Designer Design2 Sequence and Supervisory Logic DER
176. rted by the CPLD The editing within this block is done with LogiBuilder a built in utility of PAC Designer Comparator Buffer ispoPAC POWR604 and ispPAC POWR1208 P1 only The COMP BUFF block represents the outputs of the comparators and serve as expansion to drive other circuits Vmon Inputs amp ADC isoPAC POWR6ATE only The Vmon Inputs and Analog to Digital Converter ADC inputs are the analog front end of the device The values read by the ADC are used by the closed loop trim control logic and may be read at any time through 12C No user programmable settings are contained in these blocks of the schematic window Control Logic ispPAC POWR6ATE only This block represents the circuitry that makes closed loop trimming possible Double clicking the block allows the closed loop trim DAC update time to be set 12C ispPAC POWRG6ATE only This block allows configuration of the devices I2C and SMBUS capabilities Trim Cell 1 6 isoPAC POWR6ATE only These blocks allow each trim cell to be configured by inputting the desired supply output voltages selecting power supplies from the DC DC library and setting the trim cells modes of operation When all of these parameters have been entered the bottom part of this dialog box displays the resistor values needed to interface the Trim Cell Digital to Analog Converter ADC to the power supply UES The UES is for storing user defined information such as board revision or code revision Ther
177. s and configure the clock and timer settings Double click the Sequence Controller block to display the Sequence and Supervisory Logic window Choose View gt Pins definitions or click the pins button on the toolbar to display the Pin Definitions Window to configure the logic level of the input pins and the type and power up state of the output pins Return to the LogiBuilder Sequence and Supervisory Logic window Double click on the lt end of supervisory logic table gt marker to insert an equation place holder Double click on the equation place holder to display the Supervisory Logic Equation Entry Dialog Box to edit the equation settings Click OK Note LogiBuilder sequencing exceptions and supervisory equations are combined together during the compile process PAC Designer Software User Manual 31 DESIGNING POWER MANAGER Devices LogiBuilder LogiBuilder LogiBuilder is a utility within PAC Designer software that allows you to define a power supply sequence controller and monitor or other control circuits using the Power Manager devices The tools within the LogiBuilder include a set of instructions to build the sequence based on conditional events and timer delays The overall entry simplifies the design process to menu selections as opposed to writing complex code Once the set of instructions are entered the user compiles the design and can simulate the sequence or control events Three types of expr
178. s and the LogiBuilder sequence editor Next a stimulus file should be created or edited using the Waveform Editor The stimulus file is used by the simulator which produces a graphical output that is viewed using the Waveform Viewer To start Lattice Logic Simulator from within PAC Designer 1 In LogiBuilder choose Tools gt Run PLD Simulator The Launch Simulator Dialog Box opens In the Stimulus File box browse to the desired stimulus file Click OK PAC Designer will remember this stimulus file and future simulations can be initiated by clicking the PLD Simulator button on the toolbar without bringing up the Launch Simulator dialog box Automatic ABEL Import Waveform Editor This section introduces how to automatically import ABEL files with the Waveform Editor Graphical Waveform Files The Waveform Editor is a graphical application that is used to create and edit wdl files Each waveform is given a user defined name and then edited to show transitions The Waveform Editor uses a data model called the Waveform Description Language WDL The language represents a waveform as a sequence of signal states separated by time intervals The PAC Designer Software User Manual 41 DESIGNING POWER MANAGER DEVICES Automatic ABEL Import Waveform Editor language also has constructs that let you express the waveform pattern hierarchically However you do not have to be familiar with the Waveform Description Language to use the
179. s available and is divided by 32 to source the timers Alternately an external pin can be selected as the input to the divide by 32 block ADC The ADC block is the front end of the analog functions of the Platform Manager and is used by the margin trim block This block is not editable Margin and Trim Block The Margin Trim Block sets up all the modes for the trim circuitry to adjust DC DC power supplies It allows control of all the DAC settings and modes for margining and trimming CPLD Inputs The CPLD Inputs are general purpose inputs for the logic The voltage thresholds can be set for lower voltage logic using the VDDinp pin CPLD Logic This block contains the logic for use as supervisory and sequencing instructions Analog Interface The analog interface provides the connections within the Platform Manager device This block is not directly editable but is automatically configured as the design requires High Voltage Outputs The HVOUT pins can be used as FET gate drivers and have a programmable drive levels for both voltage and current The HVOUTs can also be set independently to be used as digital outputs in open drain mode CPLD Open Drain Outputs The CPLD Open Drain Outputs block contains the outputs from the CPLD These can be configured in a variety of modes UES The UES is for storing user defined information such as board revision or code revision There are 16 bits accessible to you The bits are non volatile
180. signs It includes six sub sections Design Entry LogiBuilder Functional Logic Simulation Automatic ABEL Import Waveform Editor Waveform Editor Stimulus vvvrvv YV Waveform Viewer Results This section contains concepts and procedures for designing Power Manager devices Schematic Entry Schematic entry consists of making internal connections and choosing parametric circuit values on an ispPAC device schematic window When complete the circuit can be simulated saved or downloaded to an isoPAC device As an alternative to complete configuration standard circuit functions are available from a library of stored designs The PAC Designer schematic window provides access to all configurable ispPAC device elements through its graphical user interface All input and output pins are represented Static or non configurable pins such as power ground VREF OUT and the serial digital interface are purposely omitted Any element in the schematic window can be accessed through mouse operations as well as by menu commands PAC Designer Software User Manual 11 DESIGNING POWER MANAGER Devices Design Entry Schematic Entry Power Manager Devices The PAC Designer schematic window provides access to all configurable Power Manager device elements through its graphical user interface All input and output pins are represented Some of the non configurable pins such as the serial digital interface are purposely omitted Any element
181. sks you can perform in designing Platform Manager designs Creating a New Schematic You can create a new schematic or open an existing schematic To create a new schematic 1 Choose File gt New The New Dialog Box opens 2 Select the schematic for the ispPAC device you wish to design 3 Click OK The device schematic window is displayed Editing a Schematic You can edit a schematic using several techniques including Double Click You can double click over each symbol in the Schematic Window to invoke the appropriate dialog box to edit the item See Editing Schematic Symbols Click and Drag to Connect wires Feedback Drag from the point furthest from the resistor to close the connection IA Inputs Drag from Instrumentation Amp input to an input or output terminal wire Disconnect wires Connections can be opened by dragging the wire back to its starting point Menu Entry Choose Edit gt Symbol PAC Designer Software User Manual 57 DESIGNING PLATFORM MANAGER DEVICES Design Entry The Edit Symbol dialog box opens This shows a list of all symbols seen on the schematic To edit a symbol double click the desired symbol on the list and choose the Edit button or Select the symbol from the list and press Enter A secondary dialog box specific to the symbol will appear Zoom Use standard Windows style zoom Editing Schematic Symbols PAC schematics contain SPST and SPMT switches and
182. sor feedback 60 entering supervisory equations 69 simulating with Aldec Active HDL 79 simulating with Lattice Logic Simulator 84 starting design utilities 63 swapping device pins 61 trimming and margining power supply 54 Platform supply trimming and margining 54 Power Manager algorithm in LogiBuilder 133 analog inputs 121 design mapping 14 design utilities 12 digital inputs 124 digital outputs 126 editing schematics 17 editing schematics with cursor feedback 18 entering supervisory equations 31 I2C block configuring 132 implementation example 117 implementation steps 117 LogiBuilder sequence control 134 135 simulating with Aldec Active HDL 40 simulating with Lattice Logic Simulator 41 starting design utilities 24 swapping device pins 19 timers configuring 131 trimming and margining power supply 12 169 power supply trimming and margining 12 PowerManager_HVOUT_Sim utility 24 64 PowerManager_I2CUtility 28 67 process flow 3 security options 113 SPMT SPST switches editing 16 58 starting PAC Designer 2 state machines editing 35 73 stimulus file opening default file in Waveform Editor 45 88 summary of ispPAC devices 5 supervisory equations entering 31 69 T timers parameters 132 timing simulation 164 tutorial 1 U UES bits overview 110 setting 113 WwW Waveform Editor ABEL file import 43 86 165 adding a signal 45 88 changing a signal level 46 89 changing signal duration 47 90 creating and editing waveforms
183. st from the resistor to close the connection IA Inputs Drag from Instrumentation Amp input to an input or output terminal wire Disconnect wires Connections can be opened by dragging the wire back to its starting point Menu Entry Choose Edit gt Symbol The Edit Symbol dialog box opens This shows a list of all symbols seen on the schematic To edit a symbol double click the desired symbol on the list and choose the Edit button or gt Select the symbol from the list and press Enter A secondary dialog box specific to the symbol will appear PAC Designer Software User Manual 99 DESIGNING ISPCLOCK DEVICES Procedures Zoom Use standard Windows style zoom Editing an ispClock Schematic The ispClock main schematic contains function blocks that can be edited by double clicking any given block User Pins isoCLK5406D and ispCLK5410D only This allows you to select specific functions to be routed to the user pins such as output enables 12C interface signals LOCK etc Input Buffers The Input Buffers provide the option of selecting among several logic input standards and feed the input or M divider Two input buffers are provided on the ispClock and the outputs of these buffers is selected by a multiplexer M Divider This divider divides the input reference signal before feeding it to the phase detector It may be programmed for division ratios ranging from 1 to 32 The ispPAC CLK5312S does
184. stered D flip flop Trip Both MOSFETs if Any Current E EQ3 HS_5 _MOSFET_Drive ar I_3 3_Over_Current OR I_ Output registered D flip flop Trip Both MOSFETs if Any Current E User names logic polarity output type When a circuit board is plugged into a backplane during initial stages of contact there will be a contact bounce The backplane has two supplies 3 3V and 5V During the contact bounce period the 5V and 3 3V supplies will be intermittent This routine waits until the contact bounce settles and then proceeds with the hot swap event Step 0 Marker Step 1 Waits for the calibration Step 2 Initialization of various outputs Step 3 100ms timer is started using the Start Timer instruction Step 4 The If Then Else with Timeout instruction checks to see if the 5V and 3 3V supplies are within limits If not the program jumps to restart the timer Notice that the program branches to a step previous to that of the Start Timer instruction If the supplies are within tolerance the code waits at the same step until the timer expires When the timer expires the code jumps to the next step This instruction ensures that the backplane voltage is continuously on for 100ms before jumping to the hot swap portion of the code Go to Instruction This is a branch control instruction The target jump location can be specified using the dialog box shown in Figure 43 152 PAC Designer Software Use
185. swapped Simply use the pull down menus and make sure there are no duplicated pin names Any OUT pin can be swapped with any other OUT pin Starting a Design Utility You can use a design utility to modify your schematic To start a design utility 1 With a device schematic open in the Main Window choose Tools gt Design Utilities The Design Utilities dialog box opens 2 From the list select the desired design utility PAC Designer Software User Manual 23 DESIGNING POWER MANAGER Devices Design Entry When a selection is highlighted in the list a description of the design utility is displayed in the Design Utilities dialog box 3 Click OK Starting the Power Manager Design Utilities To start a Power Manager design utility 1 With a Power Manager schematic open in the Main Window choose Tools gt Design Utilities The Design Utilities dialog box opens 2 From the list select PowerManager_HVOUT_Sim exe or PowerManager_I2CUtility exe 3 Click OK Using the PowerManager_HVOUT_Sim Utility The PowerManager_HVOUT_Sim Utility allows you to simulate the rise time of a power supply driven by an N Channel MOSFET and the HVOUT drivers on the Power Manager devices This simulator uses parameters from the MOSFET data sheet to build a model the circuit is then simulated based on inputs from the user interface To edit any values on the schematic within the utility simply double click the different circu
186. t lt SMO Equation Supervisory Logic Equation Macrocell Configuration Comment lt end of supervisory logic table gt The next step is to configure the raw Output instruction through a dialog box Figure 23 that can be opened by double clicking the raw Output instruction Figure 23 Configuring the Output Instruction in a Dialog Box Edit Output properties Outputs a Cancel Mi I Change this output signal this instruction Pin Type Registered JK type flip flop Set Value Tumon Assert Tur off Deassert Exceptions Instruction is interruptible by an exception Comment Output instruction demonstration The top window shows all outputs of the Power Manager device Any output can be turned on asserted set to logic high or turned off deasserted set to logic low through the radio button In Figure 23 the HVOUT2 output is turned PAC Designer Software User Manual 137 POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Sequence Control on and the OUT5 output is turned off When the OK button is clicked the step 2 of the sequence control output is changed to show Figure 24 the operation on HVOUT2 and OUTS signals There is no limit to the number of instructions that can be turned on or off in a given instruction Figure 24 Output Instruction Configured at Step 2 PAC Designer Design1 Sequence and Supervisory Logic T Eile Edit Yiew Tools Options Window Help Sequencer
187. t an ABEL design 1 From the top level schematic window configure the user defined inputs and outputs set the VMON trip points and configure the clock and timer settings 2 Double click the Sequence Controller block to display the Sequence and Supervisory Logic Window 3 Choose View gt Pins definitions or click the pins button on the toolbar to display the Pin Definitions Window to configure the logic level of the input pins and the type and power up state of the output pins 4 Return to the LogiBuilder Sequence and Supervisory Logic Window and enter a minimal sequence using the timers and outputs you plan to use in ABEL 5 Choose Tools gt Compile LogiBuilder Design or click the compile button on the toolbar to generate an ABEL template from which your custom ABEL design can be built from Choose View gt ABEL Source to open an ABEL Source Window 7 Choose Edit gt Enable ABEL Editing to enable the edit window and disable the LogiBuilder window 8 Make changes to the ABEL source to implement the desired design PAC Designer Software User Manual 35 DESIGNING POWER MANAGER Devices LogiBuilder 9 Choose Tools gt Compile ABEL or click the compile button on the toolbar to compile the design Note If syntactical or other ABEL errors are in the design the compilation will fail and an error report will be displayed 10 Choose Tools gt Run PLD Simulator or click the simulator button on the toolb
188. t manufacturability and simplify field upgrades Using PAC Designer software the design is entered in a graphical user interface GUI Once the design is completed you can immediately download the configuration to the ispPAC device while it is soldered to the board The software automatically generates the necessary timing and signals for the JTAG interface to the ispPAC device This quick and efficient implementation allows designers immediate access for the design checkout and debug Updates can be made at any time using this download method Multiple JTAG devices can be daisy chained together in a JTAG chain The data is shifted through each device with the appropriate programming commands and data Programming of ispPAC products can be done with ISP Daisy Chain Download ispDCD software using the Serial Vector Format SVF option Programming can also be executed directly from within the PAC Designer software 108 PAC Designer Software User Manual DEVICE PROGRAMMING Download Cable Specifications Download Cable Specifications The ispDOWNLOAD Cable is 6 feet in length One end is connected to the standard parallel port of a PC with a DB25 connector The other end consists of an in line row 1 inch header with eight interface connections Vcc and ground must be applied at the cable end connected to the target board The following figure shows cable pinouts Front View of AMP Connector Pinout AMP Connector 100 Cente
189. t necessary to be familiar with the Waveform Description Language to use the Waveform Editor In order to start the Waveform Editor from a project that has been saved an ABEL file must exist ABEL files are usually produced by compiling a LogiBuilder design ABEL files may also be generated by the user either in PAC Designer or using a stand alone text editor The Waveform Editor scans the ABEL file to determine the names of the input and output signals in use If the project has not been saved then an ABEL file can be selected manually after the editor has been started by choosing File gt Import ABEL Design To start the Waveform Editor choose Tools gt Run Waveform Editor or click the Waveform Editor button on the PLD Toolbar The Waveform Editor looks at the contents of the ABEL file for the current design in order to determine the names of the input stimulus signals This occurs automatically when the Waveform Editor is launched from a PAC design that has been previously saved If the Waveform Editor is launched from a design that has not been saved an ABEL file must be manually selected To do this select File gt Import ABEL Design This will launch a file browser dialog box Select the desired ABEL file and click Open When the simulation is complete the results are stored in a binary file bin and the Waveform Viewer application is launched automatically The Waveform Viewer starts with the design bin file loaded and displays
190. t to Yes then an exception condition can transfer it to another step Sequencer Instructions This section describes the instructions supported by the LogiBuilder Output Instruction Action This instruction controls the output pins of the Power Manager device The output status is maintained until it is changed again either through another output instruction or through the output section of any other instruction Purpose This is used functions such as turning a supply on off or activating deactivating a supervisory signal or turning a MOSFET on off The Output instruction is inserted into a sequence control step through the Insert key on the keyboard and selecting the raw Output instruction Figure 22 shows the Sequence Controller with the raw Output instruction at step 2 136 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Sequence Control Figure 22 Sequence Controller with Raw Output Instruction at Step 2 PAC Designer Design1 Sequence and Supervisory Logic Eile Edit view Tools Options Window Help Osa v e HH a Sequencer Instruction Outputs Int Comm SMO Step 0 Begin Startup Sequence no ispPA SMO Step 1 Wait for AGOOD no SMO Step 2 lt no outputs specified gt no SMO Step 3 Begin Shutdown Sequence no SMO Step 4 Halt end of program no lt Exception ID Boolean Expression Outputs Exception Handler Comment lt end of exception table g
191. te information is available in the Design_Examples_PPT pdf file located in the Examples folder of the PAC Designer installation directory Literature Much more information including application notes and development kits is available from the Lattice website See the Recommended References on page 183 for a full list of these documents General Capabilities of PAC Designer Design iterations are quick and easy with PAC Designer Just change the design schematic compile the sequence logic confirm the operation using a design utility or simulator and download to the device Likewise any part which is not read protected can be interrogated to reveal the stored configuration PAC Designer Software User Manual 1 INTRODUCTION TO PAC DESIGNER Starting PAC Designer Edit Multiple Designs PAC Designer can edit multiple designs at once Each design is stored in a separate file Hierarchical Design Entry A schematic block diagram allows easy access to configure each major function of Power Manager Platform Manager and ispClock devices The block diagram produces configuration data for the isp VM programming interface ispClock Design Utilities Frequency Calculator Reads a configuration from PAC Designer and calculates all output frequencies for a given reference input frequency Frequency Checker Reads a configuration from PAC Designer and decides whether the operating frequencies of the phase detector and the
192. te machine is built up in a separate tab in the Sequence and Supervisory Logic window The logic for the full design is then compiled and fitted to generate a single JEDEC file Figure 59 shows the POWR1220AT8 2_cPCI_HS_Seq_RG_Sup PAC example file from PAC Designer with the Sequence and Supervisory Logic window open PAC Designer Software User Manual 167 POWER MANAGER EXAMPLE IMPLEMENTATION Implementing Multiple State Machines Figure 59 Sequence and Supervisory Logic Window Showing an Example Design E POWR1220AT8 2_cPCI_HS_Seq_ RG Sup PAC Sequence and Supervisory Logic Wait for AGOOD AND NOT BD_Sel_b Shut_12V_Down 0 Local_PCI_Rst_b 0 Alert_b If Brd_12V_OK AND Brd_3V3_OK AND Brd_5V_OK Then Goto 3 Else If Timer 1 Then Goto 7 Else Goto 2 Drv_VEE_FET 1 Wait for 106 50ms using timer 1 Local_PCI_Rst_b 1 Alert_b 1 Wait for NOT Brd_12V_OK OR NOT Brd_3V3_OK OR Shut_12V_Down 1 Enable_HotSwap 0 Halt end of program SMO Step 0 SMO Step 1 SMO Step 2 SMO Step 3 SMO Step 4 SMO Step 5 SMO Step 6 SMO Step 7 SMO Step 8 lt end of exception t SM0 cPCl Hotswap SM1 On Board Wait for Board Sel signal to become acti no Enable the Hotswap operation no 12V 3 3V and 5V should be stable by this time Otherwise shut down no no Walit for VEE to settle no Release Local PCI Reset and Alert Signal no Look for faults no EQO TIMER4_GATE D NOT Charge
193. the main schematic page click the Digital Inputs block to open the secondary schematic shown in Figure 11 124 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION Configuring Digital Inputs Figure 11 Digital Inputs Schematic Interface x Eg Oy f File Edit View Tools Options Window Help gt D SUSARA ee Double click to go back to the main schematic page This diagram shows six input buffers receiving the input from the input pin or the internal 12C register Click any input buffer to open a dialog box shown in Figure 12 PAC Designer Software User Manual 125 POWER MANAGER EXAMPLE IMPLEMENTATION Configuring Digital Outputs Figure 12 Digital Inputs Dialog Box Digital Inputs Pin Name User Defined Name Input From ED Sel b 3 Pin Cancel JTAG Register Pin 12C Register PCILRST_b Pin 12C Register IN3 IN4 Pin 12C Register Pin 12C Register Pin 12C Register This dialog box enables the configuration of input pin location name of the input pin for use in power management logic and the signal source gt Pin Name This is the name of the physical pin in the datasheet Any pin can be assigned to the logical pin name in this dialog box it is called User Defined Name through the pull down menu gt User Defined Name This is the logical name used by the power management algorithm implemented in the CPLD The default associat
194. the name of the signal or waveform Select an option in the Polarity box to indicate polarity Click Add 0 10 000 000 20 000 000 en A e d dd Polatity le Input C Test Pt C Dutput C Potem Changing a signal level You can edit and modify waveforms with the Select dialog box The contents of the dialog box will change based on where and which waveform is selected using the mouse To change a signal level 1 2 Select the waveform you wish to change Choose Object gt Edit Mode to display the Selected Dialog Box as shown below Click the desired state in the States box PAC Designer Software User Manual DESIGNING PLATFORM MANAGER Devices Waveform Editor Stimulus 0 10 000 000 20 000 MMM Selected Bit Pulse High x CLK_IN Changing the duration of a signal You can make coarse adjustments of a transition by clicking and dragging with the mouse A precise duration can be edited using the Selected dialog box The contents of the dialog box will change based on where and which waveform is selected using the mouse To change the duration of a signal 1 Select the waveform you wish to change 2 Choose Object gt Edit Mode to display the Selected Dialog Box as shown below 3 Enter the new value in the Duration edit window 0 10 000 000 20 000 CUuIN WLLL Selected Bit Pulse High xf Setting the default time scale Before drawing the waveforms
195. tic screen 2 Inthe Bit Number Bit Value list scroll down to each UES bit line that you wish to change and click Toggle to change the bit from 0 to 1 or vice versa 3 Click OK PAC Designer Software User Manual 113 DEVICE PROGRAMMING Procedures Downloading Schematic Data to a Device You can download a schematic from PAC Designer to a device using a download cable attached to your computers parallel port To download a schematic from PAC Designer to a PAC device gt With the device specific schematic window open choose Tools gt Download The schematic data is downloaded to the device through the download cable A verify is performed and the Verify Dialog Box appears to verify that the device equals the schematic Uploading Data from a Device to a Schematic You can upload a schematic from a PAC device to a PAC Designer schematic using a download cable attached to your computers parallel port To upload data from a PAC device to a PAC Designer schematic gt With the device specific schematic window open choose Tools gt Upload The schematic data is uploaded from the device to the schematic through the download cable Verifying a Device Schematic You can verify that the device data equals the open schematic window in PAC Designer To verify a device schematic With the device specific schematic window open choose Tools gt Verify A verify is performed and the Verify Dialog Box ap
196. to navigate to the schematic shown in Figure 13 and navigate to the main schematic page by double clicking the blank space in the schematic 128 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION Configuring HVOUT Pins MOSFET Driver Pins Configuring HVOUT Pins MOSFET Driver Pins Double click the block called High Voltage Outputs located above the Logic Outputs block to navigate into an intermediate schematic that shows FET driver blocks Figure 15 Double click any FET Driver block to navigate to the dialog box Figure 16 that can be used to configure each of the HVOUT pins Figure 15 High Voltage Outputs Schematic Interface x 8 EA Fie Edit View Tools Options Window Help D LEERE ar oo ie Double click to edit this symbol PAC Designer Software User Manual 129 POWER MANAGER EXAMPLE IMPLEMENTATION Configuring HVOUT Pins MOSFET Driver Pins Figure 16 High Voltage Output Settings Dialog Box High Voltage Output Settings Pin Name User Defined Name Digital Control From Output Setting H OUT1 X Charge Pump Output Cancel f PLD Voltage v C 12C Register Source Current 25u v Sink Current 100ui v Open Drain Logic Output Charge Pump Output HVOUT2 DRV V FET vou Voltage v R 120 Register Source Current 25u4 v Sink Current Ou v Open Drain Logic Output Charge Pump Output PLD Voltage HYVOUT3 HVOUTS zl HVOUTS Source Current 125u4 v
197. to step as shown below Click the Save Bus button Click the Show button aap srarero e se SSCS Show Bus lt lt Add Nets New Bus Delete ai Nets Bus Members D STATE_FF3 D STATE_FF2 D STATE FFI AIO OR Ge G2 IN Remove Reverse Move Up CA The following figure illustrates what a view will look like when the step waveform is added FA Waveloen Viewer DESIGNI_VMON1_6K Ee Ede View Otiect Tools Ostions luro Hep EA F 1 000 000 D TIMERI_GATE Time 0 000 0 ns BUS 1 rile 50 PAC Designer Software User Manual DESIGNING POWER MANAGER DEVICES Waveform Viewer Results Setting the Step bus Radix The wave form viewer can display the step number in decimal binary octal or hex decimal formats To set the step bus radix 1 Choose Options gt Bus Radix The Bus Radix Dialog Box opens 2 Select the format desired Using Markers You can place a marker on a specific event in the simulation output To place a marker in the Waveform Viewer 1 Choose Object gt Place Marker or Click the Place Marker tool in the toolbar as shown below BA Waveform Viewer DESIGN1_VMON1_6K Fie Edt View Object Tools Options Jump Help slul a Aleen 2 aA 2 2 Click the Query cursor on a waveform The software places a marker vertical line at that location 3 To hide remove the marker choose Object gt Hide Marker A
198. true It is possible to toggle an output during the exception condition The output value can be changed asynchronously similar to activating the asynchronous set or reset of a D flip flop or synchronously similar to changing the D input of the D flip flop The next example shows how the output control can be used in a design In the example shown in Figure 46 the exception condition looked into a low going signal of watchdog trigger input This design has one problem If the processor hung with the WDT_Trig stuck at logic 0 the watchdog trigger mechanism does not recover For that the exception condition is modified to trigger only on the falling edge of the WDT_Trig input in its logic equation To capture the falling edge of the WDT Trig signal a second exception condition is used The second exception condition latches the trigger signal into another register Latch_Wdt_Trig an internal node The procedure to creating an internal node is described later in this section Figure 49 shows the Exception properties dialog box to implement latching of the WDT Trig signal Figure 49 Exception Properties Dialog Box Showing the Latching of the WDT Trig Signal into a Node Exception properties Expression which triggers the exception WDT_Trig Edit Exception will make sequencer goto notused v Jump only occurs when instruction is Interruptible Outputs controlled by expression Outputs are active at all times interruptible
199. tup Sequence ispPAC POWR12204T8 reset SMO Step 1 Wait For AGOOD no SMO Step 2 HVOUT2 1 Core_1V2_ En 0 es Output instruction demonstrat SMO Step 3 Wait For Core 1V2 over LTP AND IO_1V8 over LTP Core 1V2 En 1 IO 1v8 En 1 10 Turn on 1 2 and 1 8 supplies SMO Step 4 Begin Shutdown Sequence no SMO Step 5 Halt end of program no j 2 Exception 1D_ Boolean Expression Outputs Exception Handler lt end of exception table gt SM0 Equation Supervisory Logic Equation Macrocell Configuration Comment lt end of supervisory logic table gt When the Sequence Controller executes step 3 it first turns on core supply 1 2V and IO supply 1 8V and waits until the output voltages of both supplies reach the regulation levels Wait for lt Timeout Value gt Application This instruction is used for functions such as wait a certain period for a supply to stabilize after turn on or time based sequencing or to extend the reset pulse after all supplies are turned on This instruction is edited by using the following dialog box shown in Figure 32 142 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Sequence Control Figure 32 Edit Wait for Timeout Properties Dialog Box 1966 08ms timeout 1966 08ms timeout 1966 08ms timeout 1966 08ms timeout Edit Timeout properties Outputs Output Control Instruction is interruptible by an exception Comment The
200. uction Error 7 IffhenElse instruction is missing BoolExpr Error 8 At least one OUTPUT instruction is required with at least one write Reason The ABEL language used to implement the PLD requires at least one output Error 9 OUTPUT instructions must use macrocells configured as JK Reason Macrocells configured as JK provide the expected set bit and it stays set behavior If the macrocell were to be configured as D setting it would only last for one clock Error 10 Exception has empty Boolean Expression Error 11 Output cannot be set asynchronously by an exception unless assigned by an instruction or supervisory equation Reason The ABEL language used to implement the PLD requires this Warning 12 Not used Warning 13 Not used Error 14 Supervisory Logic equation has empty Boolean Expression Reason BoolExpr not present You can close edits without supplying a BoolExpr the error will be flagged when the compile is attempted Warning 15 Supervisory Logic equations assign same output more than once Reason More than one supervisory logic equation has been written for an output pin The compiler will OR these equations together 38 PAC Designer Software User Manual DESIGNING POWER MANAGER Devices LogiBuilder Error 16 This type of assignment is not supported by current pin configuration Reason LogiBuilder checks logic assignments in the Supervisory window Errors are trapped by Log
201. upervisory Logic Equation Macrocell Configuration Comment lt end of supervisory logic table gt Step 1 The sequence control program waits for the analog calibration Step 2 Both 1 2 and 1 8V supplies are turned on and the program waits for 5ms Step 3 If the supplies are faulty jumps to the shutdown program turns off both supplies flags error and goes to halt If the supplies are OK then jumps to step 4 Step 4 If the Reset_in signal is at logic 1 then Reset_CPU logic 1 else Reset_CPU signal Logic 0 If Then Else with Timeout Application This instruction assumes that the timer is started beforehand using the Start Timer instruction This instruction is used to monitor a number of events with one watchdog timer For example in a circuit board a number of supplies can be turned on and these supplies should all be stable within a certain period of time If they fail to turn on the shutdown function is initiated This instruction can also be used to implement a watchdog timer in a system The If Then Else with Timeout instruction can be configured using the following dialog box Figure 41 150 PAC Designer Software User Manual POWER MANAGER EXAMPLE IMPLEMENTATION LogiBuilder Sequence Control Figure 41 Edit IffhenElse with Timeout Properties Dialog Box Edit IffhenElse with Timeout Properties Instruction Preview Instruction Outputs If lt booleanE xpr gt hae Then Goto 0
202. ure analog input signals Configure digital inputs Configure digital output pins Configure HVOUT pins MOSFET driver outputs Configure Timer values Configure I2C address Implement power management algorithm using the LogiBuilder o o M o 0n gt U iy Simulate the design and iterate through steps 2 through 6 10 Download the design into a Power Manager device and verify the design When the PAC Designer software is installed the set up utility also installs a number of design examples You can access these examples by choosing PAC Designer Software User Manual 117 POWER MANAGER EXAMPLE IMPLEMENTATION Design Example Implementation Steps File gt Design Examples in the PAC Designer software Details of the design examples are described in lt pac designer_install_path gt Examples Design Examples ppt The following sections will describe each of the designing steps in detail using the following design example gt POWR1220AT8 2_cPCI_HS_ Seq _RG_Sup PAC Complete board power management for a CompactPCI add on card The features of this design example are listed below Design CompactPCI Board Power Management Including Hot swap gt 12V 5V and 3 3V Hot swap Controller LTC4245 IC gt Operate MOSFETs in Safe Operating Area SOA Short Circuit Protection Individually On Each Supply Rail Sequence Supplies 12V 5V 3 3V amp 12V In That Order Protection Against Over Current Faults During Operation
203. ure the user defined inputs and outputs set the VMON trip points and configure the clock and timer settings Double click the CPLD Logic or FPGA Logic block to display the Sequence and Supervisory Logic window Choose View gt Pins definitions or click the pins button on the toolbar to display the Logic I O Assignment Dialog Box to configure the logic level of the input pins and the type and power up state of the output pins Return to the LogiBuilder Sequence and Supervisory Logic window Double click on the lt end of supervisory logic table gt marker to insert an equation place holder Double click on the equation place holder to display the Supervisory Logic Equation Entry Dialog Box to edit the equation settings PAC Designer Software User Manual 69 DESIGNING PLATFORM MANAGER DEVICES LogiBuilder LogiBuilder 7 Click OK Note LogiBuilder sequencing exceptions and supervisory equations are combined together during the compile process LogiBuilder is a utility within PAC Designer software that allows you to define a power supply sequence controller and monitor or other control circuits using the Platform Manager devices The tools within the LogiBuilder include a set of instructions to build the sequence based on conditional events and timer delays The overall entry simplifies the design process to menu selections as opposed to writing complex code Once the set of instructions are entered the user comp
204. use OUTs Error 20 State variable cannot be used as a timer Reason This error typically occurs if you use the standard state variable allocation and use the timers that are reserved for state variables Error 21 Not enough macrocells for State Variable Reason This message shows up when automatic state variable allocation is used in multiple state machine design if your design is too full You will need to make your design smaller by using fewer LogiBuilder steps fewer supervisory logic equations fewer outputs or fewer timers Error 22 StartTimer requires Timer to be in JK mode Reason The timer macrocell is in D flip flop or combinatorial mode Go to the PINS window and double click the macrocell You will then see a dialog box that will let you change the mode to JK Error 23 Not used Error 24 IN_OUTs marked as Inputs cannot be used as outputs change mode in Pins Window 78 PAC Designer Software User Manual DESIGNING PLATFORM MANAGER Devices Functional Logic Simulation Reason The operating mode of the pin has not been properly set to support an OUTPUT instruction Double click the IN_OUT pin in the schematic window or go to the PINS window and set up the pin as an output Error 33 RESET signal is not defined Reason For the Platform Manager design the FPGA requires an I O pin to reset its internal state machine Remedy In the FPGA Logic I O section select an I O Direction as RESET IN Functi
205. voltage values in the required fields Again these values can be found in the DC DC converter datasheet After entering these values enter the necessary comments that describe the use of the DC DC converter and click Finish In this case the software creates a library element called Murtata_1V2_POL b Programmable Voltage with Resistor Connected from Trim Pin to GND Figure 64 shows the dialog box that appears when DC DC Converter with Programmable Output Voltage is selected in Figure 62 Figure 64 Setting Reference Voltage Current for the DC DC Converter DC DC Converter Internal Vref Voltage Please enter the internal Vref voltage which is the trim pin output voltage with pin open You can enter either Vref 0 7525 Y DC DC Corwerter lt Back Cancel All DC DC converters use some type of reference voltage or current to set the output voltage The value of the reference voltage Vref is PAC Designer Software User Manual 173 POWER MANAGER EXAMPLE IMPLEMENTATION Creating a DC DC Converter Library Entry shown either in the specifications section of the datasheet or in its output voltage calculation formula Sometimes the datasheet shows the architecture of the error amplifier with the value of Vref In some cases the DC DC converters use current reference instead of voltage reference The current reference value is accompanied by a parallel resistor Again some DC DC converter data sheets show t
206. x 94 Using Markers 94 Printing the Results 95 Chapter 5 Designing ispClock Devices 97 Concepts 97 Schematic Entry 97 ispClock Design Utilities 97 Design Examples 98 Procedures 99 Creating a New Schematic 99 Editing a Schematic 99 Editing an ispClock Schematic 100 Using Cursor Feedback to Edit Schematics 100 Starting a Design Utility 101 Starting the ispClock Design Utilities 101 Using the ispClock Frequency Calculator 102 Using the ispClock Frequency Checker 103 Using the ispClock Frequency Synthesizer 103 Using the ispClock Skew Editor 104 Importing Data to a PAC Designer Schematic 104 Exporting Data from a PAC Designer Schematic 105 Chapter6 Device Programming 107 Download Cable Overview 107 Download Cable Specifications 109 Error Messages 109 About UES Bits 110 Procedures 111 Installing the PACUTAG SYS Device Driver WinNT 2000 111 Setting JTAG Interface Options 112 Testing the Parallel Port Connection 112 Setting Security Options 113 Setting UES Bits in an isoPAC Device 113 Downloading Schematic Data to a Device 114 Uploading Data from a Device to a Schematic 114 Verifying a Device Schematic 114 Performing Auto Calibrate on a Device 114 Chapter 7 Power Manager Example Implementation 117 Design Example Implementation Steps 117 Creating Opening a Design File 119 Configuring Analog Inputs 121 Configuring Digital Inputs 124 Configuring Digital Outputs 126 Configuring HVOUT Pins MOSFET Driver Pins 129 PAC Designe
207. y universal fan out buffer 12 single ended outputs Frequency multiplication amp division Zero delay buffer Features vv vV V Yv vV V vv v vvv v V 4 400MHz output Low cycle to cycle period and phase jitter Programmable input and output termination Supports LVCMOS LVTTL LVPECL LVDS HSTL SSTL differential HSTL and differential SSTL standards E2CMOS memory stores up to four user selectable profiles Independently programmable skew and slew rate control on each output 8MHz to 267MHz Low cycle to cycle period and phase jitter Programmable input and output termination Supports input standards LVCMOS LVTTL LVPECL LVDS HSTL SSTL differential HSTL and differential SSTL standards E2CMOS memory stores up to four user selectable profiles Independently programmable skew and slew rate control on each output 8MHz to 267MHz Low cycle to cycle period and phase jitter Programmable input and output termination Supports input standards LVCMOS LVTTL LVPECL LVDS HSTL SSTL differential HSTL and differential SSTL standards E2CMOS memory stores up to four user selectable profiles Independently programmable skew and slew rate control on each output 8MHz to 267MHz Low cycle to cycle period and phase jitter Programmable input and output termination Supports input standards LVCMOS LVTTL LVPECL LVDS HSTL SSTL differential HSTL and differential SSTL standards E2CMOS memory stores up to four us

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