Diamond Systems Corporation
Contents
1. PC 104 BUS Onyx MM User Manual v1 4 2009 Diamond Systems Corporation 4 2 Board Drawing 2 NOnana 14 TET a H O 32054 JS nm Te eT 208 mi fic mi i i m m i T mi ne Im mi 82055 32 ani 1 i E r nea mi JG BASE ota 1m W ee Serera ST R765432 050000 emy sees 000000 mt ii J O0O0000DODO um a 00000 0 00 6 mi z 15 A No hh C5 Es O CO D a oO o OO O O oa OO oo OO oa OO oo OO oO OO 0 qn UL ey Item Description J1 PC 104 bus connector J3 Digital I O ports 1A 1B 1C J4 Digital I O ports 2A 2B 2C J5 Counter timer signals J6 Board base address configuration J7 Interrupt O configuration J8 Interrupt 1 configuration J9 Interrupt 2 configuration Onyx MM User Manual v1 4 2009 Diamond Systems Corporation 3 I O Header Pinouts J3 Digital I O Header for 82C55 1 J4 Digital I O Header for 82C55 2 Each of these headers is identical in pinout They provide 24 digital I O lines 5 and ground Pin 1 of J3 is in the upper right corner of the board and pin 1 of J4 is in the lower left corner A7 Gnd A6 Gnd A5 Gnd A4 Gnd A3 Gnd A2 Gnd A1 Gnd AO Gnd C7 Gnd C6 Gnd C5 Gnd C4 Gnd C3 Gnd C2 Gnd C1 Gnd CO Gnd B7 Gnd B6 Gnd B5 Gnd B4 Gnd B3 Gnd B2 Gnd B1 Gnd BO Gnd 5 Gnd J5 Counter Timer and Interrupt Header This header is a 14 pin header with all counter timer signals the external interrupt pin 5 and ground2. 1 Enabled Onyx MM User Manual v1 4 O 2009 Diamond Systems Corporation 8 Counter Timer Circuit Schematic The schematic below illustrates the counter timer configuration and how the counter timer input configuration register controls it See the control register description on page 13 O 5 L K IN J5 1 O 5 L K IN 1 J5 2 o 5 LOK IN 2 J5 7 4MHz OSCILLATOR Onyx MM User Manual v1 4 26 JS 11 LOK COUNTER IN GATE OUT J5 5 COUNTER 1 IN GATE OUT J5 6 COUNTER 2 IN GATE 2 35 9 GATE OUT OUT 2 J5 11 UNDERLINE INDICATES CONTROL REGISTER BIT PARENTHESES INDICATE I 0 HEADER AND PIN NO 2009 Diamond Systems Corporation 9 Interrupt Circuit Schematic The schematic below illustrates the interrupt circuit configuration and how the interrupt configuration register controls it See the control register description on page 13 INT J 82CSS 1 BIT CU J3 31 OUT JS S SACA 5 INT 1 J8 82CS5 2 BIT Ca J4 31 OUT 1 J5 6 SACL INT 2 J9 EXTERNAL INT J59 QUT 2 JS 11 SAC2 INTE2 UNDERLINE INDICATES CONTROL REGISTER BIT J5 11 PARENTHESES INDICATE 1 0 HEADER AND PIN NO Onyx MM User Manual v1 4 O 2009 Diamond Systems Corporation 15 10 Specifications Counter Timer Circuitry Chip Counter timers Maximum input frequency On board oscillator Signal type Input voltage all inputs Low High Input current
3. 4 DIAMOND SYSTEMS CORPORATION ONYX MM XT PC 104 Format Counter Timer Digital O Module User Manual V1 4 qa Te eat AUT DA Ne J o 4 rT See ee oe A i 140047 REV A UJ 06 14 08 AAA SOFIO 2 Y AJU 1PO00pL AE ETTER e882 e822 eee oe P 1 pate eeeeeteeeeee _ 118 dieibiutac n 5 F SECeeceaaes SSCCCLECESE gcecceceeece Nal eee EEES _ d y m _ E 7 ee sawm _ La se lt en Pesna e ae namm _ olas a a aT ene ese eee A E E E E fm TI amp amp amp a E A E E INP _ ia 114 mit i ninio RRITE IRT AAA gijeeeeceeeneee eee e eee e ops VSL RABRBRABRABRAREREASRER EER EE EF fe _ _ es ss ee eee ee k _ ee oe ee 1838 DIAMOND SYSTEMS COFF ONYX HM U3 Copyright 2009 Diamond Systems Corporation 1255 Terra Bella Avenue Mountain View CA 94043 USA Tel 650 810 2500 Fax 650 810 2525 techinfo diamondsystems com Table of Contents 10 General INfOrnnation and Features sessa a idas 3 Board DraWINd att A AAA AA 5 VO EAGER PINOS toi a rial iii 6 Base Address GONIgura lO a 7 MeruUptCOMIQUAMON dana 8 A A rt eter ert metre acre Mor Pe tte eet rr ment a Tey anor Ree ety See oer ee 9 FEGISIEMGOSIIMIMOMS ezine eee teenth sealants 10 Counter Timer Circuit Schematic cccccccceeececeeeeeeeeeeeeeesaeeaeeeeeeeeeeeaaeaauec
4. 832 Open Open Inst Open Inst Inst 350 848 Open Open Inst Open Inst Open 360 864 Open Open Inst Open Open Inst 380 896 Open Open Open Inst Inst Inst 390 912 Open Open Open Inst Inst Open 3A0 928 Open Open Open Inst Open Inst 3C0 960 Open Open Open Open Inst Inst 3E0 992 Open Open Open Open Open Inst Onyx MM User Manual v1 4 O 2009 Diamond Systems Corporation 7 5 Interrupt Configuration Each interrupt signal has its own configuration jumper block The jumper block configures the interrupt level and the 1K Ohm pull down resistor A pull down resistor is required on each active interrupt line on the PC 104 bus Only one resistor should be installed per interrupt level for the entire system J7 Interrupt 0 J8 Interrupt 1 J9 Interrupt 2 Position Function Open Jumper R 1K Ohm Resistor No pulldown Pulldown max 1 per level 7 IRQ7 6 IRQ6 Install only one jumper in each header 5 IRQ5 in any of these 6 locations 4 IRQ4 to select the interrupt level 3 IRQ3 2 IRQ2 All three interrupt sources can be set to the same level if desired However only one pulldown resistor should be installed for each interrupt level Onyx MM User Manual v1 4 2009 Diamond Systems Corporation 8 6 Register Map Base Function Comments 0 DIO port 1A 0 3 are 82C55 1 registers 1 DIO port 1B 2 DIO port 1C 3 DIO port 1 configuration register 4 DIO port 2A 4 7 are 82C55 2 registers 5 DIO port 2B 6 DIO port 2C 7 DIO port 2 configuration r
5. Do sox eco ms wo we at wo co SC Select Counter M MODE SC1 SCO 0 o SelectCountero 0 1 Selectcountert a Select Counter 2 Read Back Command See Read Operations RW Read Write RW1 RWO Counter Latch Command see Read no 0 Binary Counter 16 bits 1 Read Write least significant byte only 1 Binary Coded Decimal BCD Counter 4 Decades Read Write most significant byte only 1 1 Read Write least significant byte first then most significant byte Onyx MM User Manual v1 4 O 2009 Diamond Systems Corporation 12 The registers described below are built in to the Onyx MM circuitry and are separate from the 82C55 and 82C54 chips In the register maps below blank locations are unused See the accompanying schematic diagrams on the following pages Base 12 Counter timer input configuration register Bit Name 21 S20 Counter 2 input select S21 S20 Input source 0 0 In2 0 1 4MHz oscillator 1 X Out1 S11 S10 Counter 1 input select S11 S10 Input source 0 0 Int 0 1 4MHz oscillator 1 X Outo SO Counter 0 input select 0 Ind 1 4MHz oscillator Base 14 Interrupt configuration register SRC2 Interrupt Source 2 0 External interrupt pin 1 Counter 2 output SRC1 Interrupt source 1 0 Bit CO from 82C55 2 base 6 bit 0 1 Counter 1 output SRCO Interrupt source 0 0 Bit CO from 82C55 1 base 2 bit 0 1 Counter 0 output INTE2 0 Interrupt enable signals 0 Disabled
6. In O In 1 Gate 0 Gate 1 Out 0 Out 1 In 2 External Interrupt Gate 2 Gnd Out 2 Gnd 5 Gnd Onyx MM User Manual v1 4 2009 Diamond Systems Corporation 4 Base Address Configuration ONYX MM s base address is set with header J6 located at the lower right corner of the board Each of the six pairs of pins on J6 corresponds to a different address bit A pair left open is equal to a 1 and a pair with a jumper installed is equal to a 0 The header is used to select address bits 9 4 resulting in an 16 byte I O decode The leftmost pair selects address bit A9 and the rightmost pair selects address bit A4 Although any 16 byte location is selectable certain locations are reserved or may cause conflicts The table below lists recommended base address settings for ONYX MM The default setting is 300 Hex Open means an open position and Inst means a position with a jumper installed Base Address Header J6 Position Hex Decimal 9 8 7 6 5 4 220 544 Open Inst Inst Inst Open Inst 240 576 Open Inst Inst Open Inst Inst 250 592 Open Inst Inst Open Inst Open 260 608 Open Inst Inst Open Open Inst 280 640 Open Inst Open Inst Inst Inst 290 656 Open Inst Open Inst Inst Open 2A0 672 Open Inst Open Inst Open Inst 2B0 688 Open Inst Open Inst Open Open 2C0 704 Open Inst Open Open Inst Inst 2D0 720 Open Inst Open Open Inst Open 2E0 736 Open Inst Open Open Open Inst 300 768 Default Open Open Inst Inst Inst Inst 330 816 Open Open Inst Inst Open Open 340
7. Output voltage all outputs Low High Output current Pullup resistors 82C54 2 3 16 bits wide 10MHz 4MHz 01 100 ppm TTL 0 5V min 0 8V max 2 0V min 5 5V max 200LA max low 211A max high 0 0V min 0 4V max 3 0V min Vcc 0 4V max 2 5mA max each line 10KL all input lines Digital I O Circuitry Chip Number of I O lines Direction Input voltage Low High Output voltage Low High Output current Pullup resistors 82C55A x2 48 All lines programmable for input or output in groups of 4 8 0 5V min 0 8V max 2 0V min 5 5V max 0 0V min 0 4V max 3 0V min Vcc 0 4V max 2 5mA max each line 10K all lines Interrupt Circuitry No of interrupts Pull down resistor Interrupt levels General Dimensions Power supply Vcc Card type Temperature range Onyx MM User Manual v1 4 3 1KO resistor selectable via jumper on each interrupt 2 7 3 550 x 3 775 5 0VDC 10 200mA typical all outputs open 8 bit PC 104 bus compliant 40 85 C operating and storage 2009 Diamond Systems Corporation 16
8. eeseeesaeaaseeeeeeeessaaageneeeeess 14 IE TFUPEGICUNE SCO Mal G soo 0 esis oli 15 Jo a eh et i a 16 Onyx MM User Manual v1 4 2009 Diamond Systems Corporation 2 1 General Information and Features ONYX MM is a PC 104 compliant I O module with 48 digital I O lines 3 16 bit counter timers and 3 interrupts It is an 8 bit module so it does not contain the 16 bit expansion bus connector This connector is available as an option by requesting the B16 suffix when ordering Three right angle pin headers are provided for I O Two identical 50 pin 2x25 headers contain 24 digital I O lines each and 5 ground and a third 14 pin 2x7 header provides the counter timer signals external interrupt pin and 5 ground J2 with 24 digital I O lines is on the right side of the module in the standard PC 104 I O position J3 with 24 additional digital I O lines is on the left side of the module and J4 with the counter timer and interrupt signals is on the top edge of the module The bottom edge of the module is defined as the edge with the PC 104 ISA bus connectors All I O signals are TTL compatible The boards operate on 5V power supply only Digital 1 O 48 TTL digital I O lines are provided by 2 82C55 chips 24 per chip Each line can source 2 5mA in a logic O state and sink 2 5mA in a logic 1 state I O lines are unbuffered e there is a direct connection between the 82C55 and the I O header Bit CO of each 82C55 can be used to gen
9. egister 8 Counter timer O data 8 11 are 82C54 registers 9 Counter timer 1 data 10 Counter timer 2 data 11 Counter timer mode configuration register 12 Counter timer input configuration register 13 maps to register 12 14 Interrupt configuration register 15 maps to register 14 Note that locations 12 and 13 both map to the same physical register on Onyx MM Likewise locations 14 and 15 both map to the same physical register on the board Onyx MM User Manual v1 4 O 2009 Diamond Systems Corporation 9 7 Register definitions Base 0 Digital I O Register A 82C55 no 1 1A7 1A0 Digital I O port 1A port A on 82C55 no 1 Base 1 Digital I O Register B 82C55 no 1 1B7 1B0 Digital I O port 1B port B on 82C55 no 1 Base 2 Digital I O Register C 82C55 no 1 1C7 1C0 Digital I O port 1C port C on 82C55 no 1 Base 4 Digital I O Register A 82C55 no 2 Bit Name 2A7 2A0 Digital I O port 2A port A on 82C55 no 2 Base 5 Digital I O Register B 82C55 no 2 Bit Name 2B7 2B0 Digital I O port 2B port B on 82C55 no 2 Base 6 Digital I O Register C 82C55 no 2 Bit Name 207 200 Digital I O port 2C port C on 82C55 no 2 Onyx MM User Manual v1 4 O 2009 Diamond Systems Corporation Base 3 Digital I O Configuration Register 82C55 no 1 Base 7 Digital l O Configuration Register 82C55 no 2 These control registers determine the direction and mode of the 82C55 digi
10. erate an interrupt on the PC bus see Interrupts below All digital I O lines are connected to 5V through 10K pull up resistors Digital I O lines are accessed through two 50 pin headers J3 and J4 with 24 lines one 82C55 on each header See page 8 for I O header pinouts Counter Timer I O Onyx MM contains three 16 bit counter timers provided by an 82C54 chip Each counter timer has an input pin a gate pin and an output pin The input pin responds to positive edges The gate pin is active high a counter will count whenever its associated gate pin is high and will not count when the gate pin is low The input and gate pins are connected to 5V through 10K pull up resistors Counter timer I O lines are accessed through a 14 pin header J5 See page 8 for the pinout of J5 An on board oscillator provides a 4MHz clock that can be used to drive any counter Each counter has a maximum input rate of 10MHz Programmable features include input source selection and counter cascading Counter 0 input can be either INO from the I O header or 4MHz Counter 1 input can be either IN1 4MHz or Counter 0 output Counter 2 input can be either IN2 4MHz or Counter 1 output All three counter outputs can be programmed to generate PC bus interrupts as described below With appropriate configuration two or three counters can be cascaded to form a 32 bit or 48 bit counter and the output of this cascaded counter can generate an in
11. tal I O lines The diagram below comes from the 82C55 chip datasheet which is included at the back of this manual Base 3 is the control register for chip 1 and Base 7 is the control register for chip 2 Most applications use the simple I O configuration in which bit 7 is set to 1 and the Mode is set to 0 for all ports Here is a list of common configuration register control bytes Configuration Byte Hex Decimal Port A 9B 155 Input 92 146 Input 99 153 Input 90 144 Input 8B 139 Output 82 130 Output 89 137 Output 80 128 Output bad Ge E E Ee i ea E Onyx MM User Manual v1 4 Port B Port C both halves Input Input Input Output Output Input Output Output Input Input Input Output Output Input Output Output GROUP B PORT C LOWER 1 INPUT 0 OUTPUT PORT B 1 INPUT 0 OUTPUT MODE SELECTION 0 MODE 0 1 MODE 1 GROUP A PORT C UPPER 1 INPUT 0 OUTPUT PORT A 1 INPUT 0 OUTPUT MODE SELECTION 00 MODE 0 01 MODE 1 1X MODE 2 MODE SET FLAG 1 ACTIVE 2009 Diamond Systems Corporation 11 Base 8 Counter Timer 0 Data D7 DO Divisor bits 7 0 or 15 8 Base 9 Counter Timer 1 Data D7 DO Divisor bits 7 0 or 15 8 Base 10 Counter Timer 2 Data Bit Name D7 DO Divisor bits 7 0 or 15 8 Base 11 Counter Timer Configuration The diagram below is from the 82C54 datasheet which is included at the back of this manual D7 Dg Ds D4 D3 Do Dy
12. terrupt Onyx MM User Manual v1 4 O 2009 Diamond Systems Corporation 3 Interrupts ONYX MM provides a means to generate up to three active high interrupt signals on the PC 104 bus Three pin headers are provided to select interrupt levels for each interrupt signal Interrupt levels 2 through 7 are available on each header To enable interrupt sharing a 1KQ pull down resistor can be jumpered to each interrupt line and interrupt signals are driven by tristate drivers When an interrupt is pending the interrupt line is driven high and when it is not pending the output is in high impedance mode and the 1KQ resistor pulls it down to a logic O state Interrupt sources are programmable Interrupts can be generated from both digital I O and counter timer signals as follows Interrupt no 1 Bit CO from 82C55 1 or Counter O output Interrupt no 2 Bit CO from 82C55 2 or Counter 1 output Interrupt no 3 External interrupt pin or Counter 2 output Interrupts are enabled and disabled under software control by manipulating a control register Block Diagram ONYX MM BLOCK DIAGRAM DATA uN gt D ca TRANSCEIVER O 5 10K 82055 24 DIGITAL DIGITAL 1 0 1 0 O 5 ADDR 10K INTERFACE 24 CTRL LOGIC LOO DIGITAL O 1 0 COUNTER C5 OUTPUTS 3 INTERRUPTS O O O O LLLI ool lool loo COUNTER COUNTER AND INPUTS Od Oo aig INTERRUPT DO ERE ate CONFIGURATION COUNTER ool lool joo LOGIC GATES OO OO LT EXTERNAL TRIGGER
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