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1. Ug File Edit View Project Tools Run Scripts Window Help ri a ty Cr a Bbe iv 35 Debug 2 0 oa 22030 e 47370 Im Registers ev Variables Se Breakpoi 4 evm6678Trace coxml Code Composer Studio Device Debugging Identity Name 4 2 Group1 4 gf Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 0 Suspended SW Breakpoint 7 2 intrinsicCFilter Breakpoint intrinsicC filters float int float at intrinsicCFilters c 47 0x0CO019F4 0x20202020 no symbols are defined for 0x20202020 2 Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 1 Disconnected 2 Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 2 Disconnected 2 Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 3 Disconnect e Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 4 Disconnected 2 Blackhawk XDS560v2 USB System Trace Emulator_0 C66xx_5 Disconnected b General 2 Blackhawk XDS560v2 USB System Trace Emulator_0 C66xx_6 Disconnected b d Analysis Views e Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 7 Disconnect gt e C C 4 amp Debug Se Breakpoints Cache Control Panel Debug F testth E _c_int000 at tmp TI_MKLIBIwBz8I SRC boot c 87 0xc006720 EE Disassembly 35 3 Executables 36 ES x 37 total sum hif2 sum hif2 sum lof2 sum _lof2 T oues 38 output total sum D Memory Browser 39 B3 MMU Page Table 40 BA Modules 4
2. 0 ccc cece cnn nee eee ne ene hehe hes heh heh hahere 2 5 CCS Debug Window for evm6678Trace cexml 0 6 ne ene een nee e teen semen 2 6 C6000 Compiler Include Options 0 cece cece hee he he he he eee enn 3 3 Verify Successfu l o t Build iuit erre ER ES De S EE gay ELANASE taa TARNEN UU 4 3 CCS Debug Select and Group Cores sssssssssssesessesessesee hehehe heh hehe e hes 4 4 SRIOSingleSRIO R n Results 5 y EIE EE E I ETE bie Rex e cag XOU ER ee EE 4 5 GCS Projectes etico E eo Re Ren E aa Wi INO vk o Rd eor soot entere AR lds 5 2 CCS Debug IntrinsicCFilters Breakpoint 6 cece ccc cee cece cent Ime he he hee heh en 6 3 GES Debug Show View x cose e e ac peer EH da coats REA 6 4 CCS Debug IntrinsicCFilters Cache ak 6 5 CCS Debug IntrinsicCFilters L1D Cache Lines OK 6 6 CCS Debug IntrinsicCFilters L1D Cache Last Line Aki 6 7 CCS Debug IntrinsicCFilters LTD Cache Lines ek 6 8 CCS Deb g MPAX Utilities e Le E reat be mg NEE ane ote E A E E ge ide diy ER bak NE ER ness 7 6 Trace System Control Setting wi Aug d eee e re t ERN Eee er ex n E oss Baek owes E EST 7 7 Trace System Control Settings Select Receiver ooooooooccccoccoccconccnccr corr eem hehe e rene en 7 8 Breakpoint Properties Default Configuration 0c cece cece een eee he hs eee 7 9 Breakpoint Properties Example Configuration 0 0 cece cece erence e hehehe 7 10 Breakpoint Properties Address Mas
3. 10 Select Build properties choose C6000 Compiler gt Include Options and ensure that include paths are setup as shown in Figure 2 1 Figure 2 1 C6000 Compiler Include Options Configuration Debug Active Add dir to include search path include path T CG TOOL ROOTJ incude S PDK INSTALL PATHj ti drv srio example SRIOLoopbackDiolsr 11 Clickthe OK button to save the project properties and close the Properties window End of Procedure 2 2 Procedure 2 3 Build the Project Step Action 1 In Project Explorer select the SRIO LoopbackDiolsrexampleproject project 2 Build the project e Select the CCS menu option Project gt Build Project OR e Right click on the project in Project Explorer and select Build Project OR e Click on the hammer icon 3 CCSwill now attempt to compile and link the project This may take a few minutes to complete 4 Please direct your attention to the CCS Console On a successful build you will see no errors generated in the Problems window NOTE There may be warnings and the following message should display in the Console window Finished building target SRIO LoopbackDioIsrexampleproject out Build Finished QUESTIONS Was the file SRIO LoopbackDioIsrexampleproject out generated Note From the CCS Edit perspective check the Binaries or Debug directory From the CCS Debug perspective check the Console End of Procedure 2 3 TMS320TCI66x Ke
4. Was the compiler able to schedule the software pipeline What are the general reasons that the compiler might not schedule the software pipeline Note Think about cases that can cause randomness in the execution timing What reason can you see that the compiler might not be able to schedule the software pipeline Note Think about the inline function 4 Replacethe regular function with the intrinsic function in all the loops Look at the definition of the regular function and see what intrinsic it uses 5 Rebuild the code load and run 6 Lookatthe intrinsicCFilter asm QUESTIONS Did the compiler schedule the software pipeline Record the optimized project cycles time for natural C function and for intrinsic function with software pipeline End of Procedure 5 5 5 6 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x 5 3 Instructions Doc ID 122222 Chapter 5 Optimization Procedure 5 6 Align the Data Step Action 1 In the intrinsicCFilter c code the data is read from the memory QUESTIONS e What is the alignment of the input data e What is the alignment of the filter coefficients in the stack Note Find the pragma that aligns the data Consider other ways to align the data on a 64 bit boundary 2 Change the code to tell the compiler that the data is loaded from aligned memory the amemX intrinsic tells the compiler that the dat
5. gt Trace Trace Breakpoint Properties amp Breakpoint Properties vv Properties Values 4 Hardware Configuration 4 Type Trace a STM Trace Type CP_Tracer Transaction Monitor MSMC 0 4 Function Transaction Statistics b Statistics Type Address Range Filter false EMU Trigger Filter false Sample Window 65535 Display Settings 4 Miscellaneous Group Default Group Name Trace All settings under this are handled by the target without intruding on the target s execution Edit Property a Cen TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 7 9 Product Release MCSDK 2 x 7 3 Instructions Chapter 7 Using MPAX to Define Private Core Memory in DDR Doc ID 122222 7 To configure a Breakpoint Properties value click on the value line to the right of the each value to access a pull down menu of options The trace for this example is configured as follows 7a STM Trace Type CP Tracer 7b Transaction Monitor DDR3 7c Function Transaction Logging This will open a new dialogue box to choose what to log 7d Transaction Master gt GEM Select only the GEM tab this will open the next level which GEM to follow Ze All GEMs should remain active So select all the GEM from 0 to 7 7f Atthis point the window appears as shown in Figure 7 5 Figure 7 5 Breakpo
6. STM Library and System Trace The goal of this exercise is to demonstrate the usage of STM library to collect real time information into system trace and present it on CCS 8 2 Project Files The following files are used in this exercise Initialization c StmMain c System trace c System trace h TraceNoRTSC D cmd TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 8 1 Product Release MCSDK 2 x 8 3 Instructions Chapter 8 STM Library and System Trace Doc ID 122222 8 3 Instructions The list of processes used in this example are as follows e Procedure 8 1 Build and Run the Project e Procedure 8 2 Connect to the EVM e Procedure 8 3 Load the Program and Configure the Trace e Procedure 8 4 Run the Program Note This exercise requires a mezzanine card with a trace emulator on the target platform Procedure 8 1 Build and Run the Project Step Action S 1 Open CCS Create new project through the CCS menu item File gt New gt CCS Project Enter stm_example as a Project Name Click the check box to Use default location a uh Y N Set the Family to C6000 and Variant to Generic C66xxx Device as shown in Figure 8 1 8 2 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x Doc ID 122222 Figure 8 1 8 3 Instructions Chapter 8 STM Library and System Trace CCS Project Properties ul it CCS Project ee Crea
7. recommended TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 1 1 Product Release MCSDK 2 x 1 3 EVM Configuration Preparations Table 1 1 Doc ID 122222 Before you begin set the EVM to no boot mode as shown in Table 1 1 No Boot Dipswitch Settings DIP SW3 DIP SW4 DIP SW5 DIP SW6 Boot Mode Pin 1 2 3 4 Pin 1 2 3 4 Pin 1 2 3 4 Pin 1 2 3 4 No boot off on on on on on on on on on on on on on on on End of Table 1 1 Note A dditional EVM switch settings are available at the following link http processors wiki ti com index php TMDXEVM6678L EVM Hardware Setup Boot Mode Dip Switch Settings Procedure 1 1 Create a New Target in CCS Step Action 1 Launch CCS by double clicking the icon on the desktop Note As CCS initializes a pop up will appear with a default workspace Replace the default workspace with C ti workspace 2 Create a new target configuration 2a Select the CCS menu option View gt Target Configurations 2b Select User Defined 2c Right click and select New Target Configuration 3 Enterthe name of the new target configuration in the File Name text box 3a Setthe File name based on the EVM model model ccxml For example EVM6678LE ccxml 3b Leave the Location the default value C Documents_and_Settings student ti CCSTargetConfigurations 3c Click the Finish button The
8. you can get the STM and all advanced debug library from the following address https gforge ti com gf project ctoolslib frs action FrsReleaseBrowse amp frs package id 92 e Ifyou do not have MCSDK release load the library from gforge address from above and put it in directory C tiMCSDK_3_0_0_11 ctoolslib_1_0_0_3 packages ti STMLib e After installing the STM library the directory C tiMCSDK_3_0_0_11 ctoolslib_1_0_0_3 packages ti STMLib includes multiple sub directories as shown in Figure 8 2 Figure 8 2 STM Lib Directory Structure gt OSDisk C ti MCSDK 3 01 12 gt ctoolslib 1 0 2 0 packages ti STMLib gt brary v Share with Burn New folder Name Date modified Type Ji dec 8 1 2033 0PM _ File folder Ji include 8 1 2013 3 40 PM File folder de lib 8 1 2013 3 40 PM File folder de projects 8 1 20133 40PM File folder Ui src 8 1 2013 3 40 PM File folder STMLib_5 0_Manifest htm 2 5 2013 10 38 PM HTML Document 13 Setthe properties for the Debug configuration Right click on the project Select Properties 13a Choose Build click on the Environment tab and click the Add button to add the path to add a variable with Name as STM BOOT and Value as C tiMCSDK_3_0_0_11 ctoolslib_1_0_0_3 packages ti STMLib 13b Choose C6000 Compiler gt Optimization and set verify the following properties e Optimization level 0 e Optimize for code size 0 13c Choose C6000 C
9. 0 V inputComplex 9 Lines L1D cache 0x00800280 Ox0080028F 10 0 v inputComplex 10 Lines L1D cache 0x008002C0 Ox008002FF 11 0 V inputComplex 4 11 Lines L1D cache 0x00800300 0x0080033F 12 0 V inputComplex 4 12 Lines L1D cache 0x00800340 0x0080037F 13 0 v inputComplex 13 Lines L1D cache 0x00800380 Ox008003BF 14 0 V inputComplex 4 14 Lines L1D cache 0x008003C0 0x008003FF 15 0 V inputComplex 4 15 Lines L1D cache 0x00800400 0x0080043F 16 0 V s E inputComplex 4 16 Lines L1D cache 0x00800440 0x0080047F 17 0 V inputComplex 17 Lines L1D cache 0x00800480 0x008004BF 18 0 V inputComplex 4 18 Lines L1D cache 0x008004C0 Ox008004FF 19 0 V inputComplex 19 Lines L1D cache 0x00800500 Ox0080053F 20 0 v inputComplex 20 Lines L1D cache 0x00800540 0x0080057F 21 0 V inputComplex 21 Lines L1D cache 0x00800580 Ox008005BF 22 0 V s inputComplex 22 Lines L1D cache 0x008005c0 Ox008005FF 23 0 V S E inputComplex 23 Lines L1D cache 0x00800600 0x0080063F 24 0 V a x inputComplex 24 Lines L1D cache 0x00800640 0x0080067F 25 0 D inputComplex 25 Lines L1D cache 0x00800680 Ox008006BF 26 0 V 5 inputComplex 26 Lines L1D cache 0x008006C0 0x008006FF 27 0 v z inputComplex 27 Lines L1D cache 0x00800700 0x0080073F 28 0 V S B inputComplex 4 28 Lines L1D cache 0x00800740 0x0080077F 29 0 D gt E inputComplex 4 29 Lines L1D cache 0x00800780 0x008007BF 30 0 V E inputComple
10. 2 Loadthe SRIOSingleSRIO out to all cores in the group 2a From the Run menu select Load OR 2b Clickthe Load icon 4 4 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x 4 Instructions Doc ID 122222 Chapter 4 SRIO Type 11 3 Runthe code in one of the following ways 3a PressF8 3b From the Run menu select Resume 3c Clickon the Resume icon green arrow The output results appear as shown in Figure 4 3 SRIOSingleSRIO Run Results Figure 4 3 liv Hr we n He Mre PRE a 6607 ro ei 0 E 3 B24 a E mazanin ccxml Code Composer Studio Device Debugging a ER Group p Blackhawk XDS560v2 USB Mezzanine Emulator_0 C66xx_0 Running p Blackhawk XDS560v2 USB Mezzanine Emulator 0 C66xx 1 Running p Blackhawk XDS560v2 USB Mezzanine Emulator 0 C66xx 2 Running s9 Blackhawk XDS560v2 USB Mezzanine Emulator 0 C66xx 3 Running p Blackhawk XDS560v2 USB Mezzanine Emulator 0 C66xx 4 Running p Blackhawk XDS560v2 USB Mezzanine Emulator 0 C66xx 5 Running Ee Debug 3 p Blackhawk XDS560v2 USB Mezzanine Emulator 0 C66xx 6 Running p Blackhawk XDS560v2 USB Mezzanine Emulator 0 C66xx 7 Running E Console 22 mazanin ccxml CIO C66xx_ Debug Core System Initialization for CPPI amp QMSS C66xx_ C66xx_8 This is Core 6 at this point ALL cores finished create and bind C66xx_1 fft
11. 4 Configure the CSSTM O0 Trace Control Step Action Note These instructions are for CCS V5 3 For CCS V5 4 follow the instructions in Chapter 8 on page 8 1 From the Tools menu in the debug prospective choose Trace control The Trace System Control window see below opens Click on the CSSTM 0 tab As shown in Figure 7 2 set Port width to 4 pin place a check mark next to Synchronize with target set the buffer size 512kB is sufficient for this example and select Circular buffer Figure 7 2 Trace System Control Setting MU Trace System Control mee CSSTM 0 66x 0 C66 1 C6 amp x 2 C66 3 C66 4 C6 amp x 5 C66 6 C66 7 Trace Settings 4pin v Port width STA Buffersize Stop onfull Circular Je Synchronize with target About Data Viewer Receiver OK Cancel Apply TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 7 7 Product Release MCSDK 2 x 73 Instructions Chapter 7 Using MPAX to Define Private Core Memory in DDR Doc ID 122222 4 Clickon the Receiver button to open the Select Receiver window as shown in Figure 7 3 4a Choose where the trace data will go Choose 560 V2 Trace Note You can use the EB as well but the ETB is small 32K only and then you have to read it from the ETB 4b Click OK on the dialogue box and then click Apply and wait for the programming to be done Figure 7 3 Trace System Control Settings Select Receiver um u CEA kd
12. 80005800 C66xx 4 fft size 32 output 80003000 real 80008000 imag 80006000 C66xx 5 fft size 128 output 80003800 real 80008400 imag 80006400 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 4 5 Product Release MCSDK 2 x 4 3 Instructions Chapter 4 SRIO Type 11 4 Observe the results then suspend the run 4a From the Run menu choose Suspend OR 4b Click on the Suspend icon the yellow pause lines End of Procedure 4 4 Doc ID 122222 4 6 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x Chapter 5 Optimization 5 1 Purpose The goal of this exercise is to demonstrate some basic optimization techniques This exercise works on any KeyStone EVM board It may also be used with the simulator in conjunction with the estimated cycle count 5 2 Project Files The following files are used in this lab e firMain c e intrinsicCFilters c e linker cmd e naturalCFilters c e test h e utilities c 5 3 Instructions In the first part of the exercise you will build load and run a project on the EVM without optimization In the second part you will enable optimization and analyze the results The list of processes used in this example are as follows e Procedure 5 1 Build and Run the Project e Procedure 5 2 Connect to the EVM e Procedure 5 3 Load and Run the Program e Procedure 5 4 Compiler Optimization e Procedure 5 5 En
13. Addr 0x100 Master GEMO Write Access XID 0x3 Addr 0x100 Master GEMO Write Access XID 0x4 Addr 0x100 Master GEMO Write Access XID 0x5 Addr 0x100 Master GEMO Write Access XID 0x6 Addr 0x100 Master GEMO Write Access XID 0x7 Addr 0x100 Master GEMO Write Access XID 0x8 Addr 0x100 Master GEMO Write Access XID 0x9 Addr 0x100 Master GEMO Write Access XID 0xa Addr 0x100 Master GEMO Write Access XID 0xb Addr 0x100 Master GEMO Write Access XID 0xc Addr 0x100 Master GEMO Write Access XID 0xd Addr 0x100 Master GEMO Write Access XID 0xe Addr 0x100 Master GEMO Write Access XID 0xf Addr 0x100 Master GEMO Write Access XID 00 Addr 0x100 Master GEMO Write Access XID 0x1 Addr 0x100 Master GEMO Write Access XID 0x2 Addr 0x100 Master GEMO Write Access XID 0x3 Addr 0x100 Masterz GEM Write Access XID 0x2 Addr 0x110 Master GEM1 Write Access XID 0x3 Addr 0x110 Master GEM1 Write Access XID 0x4 Addr 0x110 Master GEM1 Write Access XID 0x5 Addr 0x110 Master GEM1 Write Access XID 0x6 Addr 0x110 Master GEM1 Write Access XID 0x7 Addr 0x110 Master GEM1 Write Access XID 0x8 Addr 0x110 Master GEM1 Write Access XID 0x9 Addr 0x110 Master GEM Write Access XID 0xa Addr 0x110 Master GEM1 Write Access XID 0xb Addr 0x110 Master GEM1 Write Access XID 0xc Addr 0x110 Master GEM Write Access XID 0xd Addr 0x110 7 14 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release
14. Counter 81 C66xx 0 Debug Core 0 Free Counter 72 C66xx 0 Debug Core 0 DIO with Interrupts example completed successfully End of Procedure 2 5 QUESTIONS 1 Using a text editor look at the CFG file and determine how the project includes the SRIO module a What other modules are needed Hint QMSS and CPPI are needed for SRIO b The CFG file specifies CORE 0 and CORE 1 Is this important to the execution of the application 3 Load the OUT file and run it on Core 1 a Does it run b Look at the main function and explain why TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x 3 1 Purpose 3 2 Instructions Chapter 3 HyperLink Communication The purpose of this exercise is to demonstrate how to build an application that uses the HyperLink interface on KeyStone C66x devices Note Not all KeyStone devices include HyperLink Refer to the data manual for your device before proceeding Note Not all KeyStone EVMs include a HyperLink interface on the board An expansion module may be required Refer to the Quick Start Guide for your EVM before proceeding Begin by importing HyperLink example code from the MCSDK and running it in loopback mode on a single C66x EVM In this example the same C66x EVM acts as both the sender and the receiver of packets Only one C66x EVM is required for this part of the exercise The second part demon
15. Instructions Chapter 5 Optimization Doc ID 122222 Procedure 5 3 Load and Run the Program Step Action 1 Enable the Clock by selecting the CCS menu option Run gt Clock gt Enable 2 Select Core 0 and load the out file created earlier in the lab 2a Select the CCS menu option Run Load Load Program 2b Click Browse project 2c Select optimization out by unwrapping the OptimizationDebug and click OK 2d Click OK to load the application to the target Core 0 3 Runthe application by selecting the CCS menu option Run Resume C66xx 0 C66xx 0 A successful run should produce a console output as shown below Record the cycles time for both natural C and intrinsic C versions C66xx 0 natural C code size 32768 time 3889442 C66xx 0 intrinsic C code size 32768 time 2809073 C66xx 0 no error was found C66xx 0 DONE Note If the time shows zero you have not enabled the clock see above End of Procedure 5 3 Procedure 5 4 Compiler Optimization Step Action 1 Move back to the CCS Edit perspective 2 Youwill now set the properties for the Release configuration This suppresses all debug features and enables the highest time optimization 2a Right click on the Optimization project Select Build Configurations gt Set Active gt Release 3 Right click on the Optimization Project Select Properties 3a Choose Build click on the Environment tab and click the Add button to add the path to add a variable with Na
16. behavior and determine why the higher results start at 8K and not at 4K 6 1 1 Why the Debug Version is Used For the purpose of reading data from L1 cache the optimization is not important This would not be the case if the optimized code in the release writes out intermediate results and then reads it later and the debug version does not But this is not the case Both versions read and write the same information Thus for this exercise the debug version is used with non optimization and full symbolic debug turned on TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 6 1 Product Release MCSDK 2 x 6 2 Instructions Chapter 6 Using Advanced Debug 6 2 Instructions 6 2 Doc ID 122222 First you will look at the cache behavior when the number of elements is 4K Next you will do the same with 16K elements Lastly you will look at the 8K elements use the information derived from the previous two tasks to draw a conclusion The list of processes used in this example are as follows Procedure 6 1 View the 4K Case Procedure 6 2 Looking at the Cache Lines for 4K Case Procedure 6 3 View the Cache Lines for 16K Case Procedure 6 4 View the Cache Lines for 8K Case Procedure 6 1 View the 4K Case Step Action 1 Change the number of elements in the test h file as follows define NUMBER OF ELEMENTS 4096 Rebuild the code Launch the debugger connect Core 0 to the emulator
17. ccxml file will now open in a GUI based view with the Basic tab active A Define the new target configuration by selecting the connection type in the Basic Tab Aa Locate your EVM model Table 1 2 and set the properties accordingly Table 1 2 EVM Emulator Types EVM Model Emulator Type Device EVM6657L Texas Instruments XDS100v2 USB Emulator TMS320C6657 EVM6657LE Blackhawk XDS560v2 USB Mezzanine Card TMS320C6657 EVM6678L Texas Instruments XDS100v1 USB Emulator TMS320C6678 EVM 6678LE Blackhawk XDS560v2 USB Mezzanine Card TMS320C6678 End of Table 1 2 4b The Connection drop down menu identifies the emulator type as shown in the table above For example Blackhawk XDS560v2 USB Mezzanine Card 4c Boardor Device identifies the TI processor device as shown in the table above For example TMS320C6678 4d Under Save Configuration click the Save button 1 2 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x 1 3 EVM Configuration Doc ID 122222 Preparations 5 Configure setup on the Advanced Tab 5a Clickthe Advanced tab at the bottom of the screen 5b Select Core 0 on the target device e TMS320C6657 0 gt IcePick_C_0 gt Subpath_1 gt C66XP 0 OR e TMS320C6678 0 gt IcePick D subpath 0 gt C66x_0 5c You will now see a sub window called Cpu Properties that allows you to choose an initialization script 5d Locate the appropriate GEL file t
18. gt MU Trace System Control d 1 eS CSSTM 0 C6 amp x 0 C66 1 C amp amp 2 C6603 CBG0_4 Cp 5 CBG0_6 C660 7 Trace Settings 4pin v Port width 512kB y Buffer size Stop onfull Circular Y Synchronize with target About Data Viewer Receiver OK Cancel Apply 4 End of Procedure 7 4 7 8 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x Doc ID 122222 7 3 Instructions Chapter 7 Using MPAX to Define Private Core Memory in DDR Procedure 7 5 Add and Configure the Trace Location Step Action 1 uu 5 WN 6 From the View tab open a Breakpoint window Note Trace points are currently CCS5 version 5 3 x defined from the Breakpoint window Load the code to all the cores From the Debug menu go back and select the CSSTM 0 trace Go to the Breakpoint window right click and select Breakpoint You can define either a breakpoint or a trace point Select Trace point A trace breakpoint will be added to the window To configure the trace right click on the trace and choose Properties The Breakpoint Properties window is opened as shown in Figure 7 4 Figure 7 4 Breakpoint Properties Default Configuration Ae iT to Been a 2 7 E L aut Registers 9 Variables 99 Breakpoints 3 X REX sr Studio Device Debugging Identity Name Condition Count
19. in DDR There is no hardware coherency between DDR and the internal memory of the core L2 and L1D Thus the user must maintain the coherency using invalidate writeback and writeback invalidate This example solves the cache coherency problem by disabling the cache Disabling the cache is done using the MAR registers The MAR registers are described in the C66 CorePac User s Guide Chapter 4 4 7 2 3 Usage of EDMA to Move Data to and from Private Memory Data can be moved in and out of private memory using the EDMA When a core reads or writes to the DDR the data goes via the master port of the core into the MSMC through the core MPAX registers When EDMA reads or writes data to the DDR the data goes via the TeraNet port The TeraNet port that connects to the DDR has 16 sets of MPAX registers that correspond to 16 privilege IDs Each set has 8 registers 8 more MPAX registers are connected to the shared L2 memory inside the MSMC The privilege ID of EDMA transform is inherited from the master who initiates the transform So if Core 0 with Privilege ID 0 initiates EDMA transform the privilege ID is 0 If Core 7 initiates the EDMA transform the EDMA privilege ID is 7 If the EDMA is used with the DDR private memory then the MPAX registers of each privilege ID should be configured similarly to the core MPAX In this example EDMA is not used 7 2 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Releas
20. 1 End of filter 1 El Pin Connect 42 f 43 a4 45 Second filter coefficients are 1 4 1 4 1 2 1 2 n C zeg S 47 p_in float2 t inputComplex 48 filter size 4 MSc 6 4 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x Doc ID 122222 6 2 Instructions Chapter 6 Using Advanced Debug 2 Select Cache and double click to open the Cache window as shown in Figure 6 3 Figure 6 3 CCS Debug IntrinsicCFilters Cache 4K AL hl testh E _c int000 at tmp TI MKLIBIwBz81 SRC boot c 87 0xc006720 35 36 37 38 39 40 41 42 43 total sum hif2 sum hif2 sum _lof2 sum _lof2 sum output total sum p End of filter 1 y p Second filter ad d p_in _float2_t inputComplex filter_size 4 _ftof2 25 0 25 x 1 _ftof2 5 0 5 ls ftof2 0 25 0 25 fiMeinc intrinsicCFitersc 23 coefficients are 1 4 1 4 1 2 1 2 1 4 1 4 1 2 1 2 1 Cache Tag RAM Read complete 1536 Cache Lines read from target 33 after filtering Cahe Line Start Ads LineEndAdrs Set Way Vaid Dirty LRUWay Symbols In Cache L1D cache 0x00800000 OXDOBDZFFF Ow Vo LID cache 0x00808CCO Ox00808DBF 1 V D L LID cache 0x00808F00 Ox0080903F Nu D LID cache 0x0080A000 OXDOBOAD3F 128 1 V D L LD cache 0x0080A1CO OXDOBOAJFF 135 1 V E Le L1D cache 0x0080A280 Ox0080A2EF 13
21. 14000 3f e Core 5 0x815000 3f e Core 6 0x816000 3f e Core 7 0x817000 3f Note Bits 6 and 7 are not used and may read as non zero The example configures the MPAX registers in two ways either with CSL functions or with direct register manipulations The user can switch between the two ways or even use both of them A printf shows the values of the MPAX registers 7 2 5 MAR Registers Next consider the MAR registers For this example the logical memory starts on 16M boundary and the size is 16M So one MAR register controls the cache ability of the complete private memory MAR registers control the logical addresses not the physical address If the private memory was larger multiple MAR registers will be used And if the logical memory boundary was not aligned on 16M bytes a more complex scheme has to be developed For the example case the MAR registers disable the cache and prefetch for all addresses starting in MAR 140 0x9000 0000 to MAR 159 0xa000 0000 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x 7 3 Instructions Doc ID 122222 Chapter 7 Using MPAX to Define Private Core Memory in DDR 7 3 Instructions The list of processes used in this example are as follows e Procedure 7 1 Run the Example Code e Procedure 7 2 Connect to the Non debuggable Devices Esp CCTMS 0 e Procedure 7 3 Load the Code to the 8 Cores e Procedure 7 4 Configur
22. 4 CCS Debug Trace Configuration Show All Cores File Edit View Project Tools Run Scripts Window Help riv id gt m m ot 22 2 4 xs evm6678Trace ccxml Code Coi a g Blackhawk XDS560v2 USB S main int at StmMain Disconnect Target Ctrl Alt D c int00 at boot c 87 0y Enable Global Breakpoints x Blackhawk XDS560v2 USB S Enable Halt On Reset x9 Blackhawk XDS560v2 USB Sj x Blackhawk XDS560v2 USB S x9 Blackhawk XDS560v2 USB s x9 Blackhawk XDS560v2 USB S Hide core s x Blackhawk XDS560v2 USBS x Blackhawk XDS560v2 USB d Show ali cons Connect Target Ctrl Alt C Enable OS Debugging Open GEL Files View Group core s Sync group core s Ungroup core s Rename Remove All Terminated Relaunch Edit evm6678Trace ccxml Edit Source Lookup Terminate and Remove Terminate Disconnect All Ge Le StmMain c 33 de 25 3 4 5 E fltineluda sudArinmintimali A Deamartiar EE 3 Nondebuggable devices will appear as shown in Figure 8 5 Figure 8 5 Non Debuggable Devices Not Connected 4 2 Non Debuggable Devices Blackhawk XDS560v2 USB System Trace Emulator_0 IcePick_D Blackhawk XDS560v2 USB System Trace Emulator 0 CS DAP DebugSS Disconnected Xe Blackhawk XDS560v2 USB System Trace Emulator 0 CSSTM 0 Disconnected a Blackhawk XDS560v2 USB System Trace Emulator_0 TETB_STM Disconnected 4 Selectthe Non Debuggable device group right click and connect Ta
23. 4d Place a check mark on Copy projects into workspace 4e Clickthe Finish button The SRIO_LoopbackDiolsrexampleproject project should now appear in the CCS Project Explorer on the left hand side of your screen End of Procedure 2 1 Procedure 2 2 Verify and Set Project Properties Step Action 1 In Project Explorer right click on SRIO LoopbackDiolsrexampleproject and select Properties 2 Select General properties 3 Choosethe Main tab and set verify the Device properties as follows Family C6000 e Variant Generic C66x Device Select Build properties 5 Choose C6000 Compiler gt Processor Options and set verify the following properties e Configuration Debug e Target processor version 6600 e Application binary interface eabi Note Different version of CCS may have slightly different GUI The Application binary interface tab may be part of the main window and not the processor option window Select Build properties 7 Choose C6000 Compiler gt Optimization and set verify the following properties e Optimization level 0 e Optimize for code size 0 8 Select Build properties 9 Choose C6000 Compiler 2 Debug Options and set verify the following properties e Debugging model Full symbolic debug 2 2 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x 22 Instructions Doc ID 122222 Chapter 2 CCS Basics SRIO Loopback
24. 60v2 USB Mezzanine Emulator 0 C66xx 3 Disconnected Unknown Blackhawk XDS560v2 USB Mezzanine Emulator 0 C66xx 4 Disconnected Unknown 60 E a stadh Unknown El Connect Target Ctrl Alt C Disconnect Target Ctri Alt D Enable Global Breakpoints Enable Halt On Reset Enable OS Debugging Open GEL Files View Hide core s Show all cores E Console 33 ECT mazanin coxml Ungroup corets C66xx 0 GEL Outpu Rename C66xx 0 GEL Outpu C66xx 1 GEL Outpu Remove All Terminated C66xx 1 GEL Outpu Relaunch C66xx 2 GEL Outpu C 6xx 2 GEL Outpu Terminate and Remove a Terminate Disconnect All Properties 4 C66xx 5 GEL Output Setup Memory Map C66xx 5 GEL Output Setup Memory Map Done C6exx 5 Ttt size 12 utpUt seinen real suuu cuo imag sevesceo cmd_tile contigPkg compiler opt srio drv c A C66xx_2 fft size 128 output 80002000 real 80007800 imag 80005800 C66xx_1 fft size 64 output 80001800 real 80007400 imag 80005400 C66xx 6 fft size 32 output 80004000 real 80008800 imag 80006800 Finished building srio drv c Building target SRIOSingleSRIO out C66xx 1 fft size 32 output 80001800 real 80007400 imag 80005400 Invoking C6000 Linker C66xx_2 fft size 64 output 80002000 real 80007800 imag 80005800 C ti ccs ccsv5 tools compiler c6000 bin cl x mv6600 g C66xx 1 fft size 128 output 80001800 real 80007400 imag 80005400 define LITTLE ENDIAN define TMS320C6600 C66xx 4 fft size 128 ou
25. 8 1 V S L L symbols Double click to view cache line detail LID cache 0x0080A300 OXBASKF 140 0 v OD L L1D cache 0x0080A440 OXDOB0A47F 145 0 V D L LIP cache 0x0C0005CO 0x0C0007DF 0 v TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x 6 5 6 2 Instructions Chapter 6 Using Advanced Debug Doc ID 122222 3 Double click on the Cache tab to enlarge the window Then double click on any line of the L1D to display all L1D lines as shown in Figure 6 4 Figure 6 4 CCS Debug IntrinsicCFilters L1D Cache Lines 4K rij ggicmi mWg w b5e El Console Memory Map EB Table G Cache Tag RAM Read complete 1536 Cache Lines read from target 33 after filtering Cache Line Start Adrs Line End Adrs Set Way Valid Dirty LRUWay Symbols In Cache LiD cache 0x00800000 0x0080003F 0 0 v z inputComplex 0x00800000 L1D cache 0x00800040 0x0080007F 1 0 V inputComplex 1 Line L1D cache 0x00800080 Ox008000BF 2 0 V inputComplex 4 2 Lines L1D cache Ox008000CO Ox008000FF 3 0 V inputComplex 3 Lines L1D cache 0x00800 100 0x0080013F 4 0 V inputComplex 4 Lines L1D cache 0x00800 140 0x0080017F 5 0 V inputComplex 5 Lines L1D cache 0x00800 180 0x008001BF 6 0 v S inputComplex 6 Lines L1D cache 0x008001CO Ox008001FF 7 0 v E inputComplex 7 Lines L1D cache 0x00800200 0x0080023F 8 o V inputComplex 8 Lines L1D cache 0x00800240 0x0080027F 9
26. 8F 26 o v L inputComplex 538 Lines L1D cache 0x008086C0 Ox008086FF 27 0 v L inputComplex 539 Lines L1D cache 0x00808700 0x0080873F 28 0 v L inputComplex 540 Lines L1D cache 0x00808740 0x0080877F 29 o v E L inputComplex 541 Lines L1D cache 0x00808780 Ox0080875F 30 o D z L inputComplex 542 Lines L1D cache 0x008087C0 Ox008087F 31 0 v S L inputComplex 543 Lines End of Procedure 6 3 QUESTIONS e Why does the first entry address start with 0x00808000 e What is the last cache line that has the inputComplex vector e How many bytes were read from the inputComplex vector How do you know e What is the number of elements that were read from the inputComplex vector 6 8 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x Doc ID 122222 6 2 Instructions Chapter 6 Using Advanced Debug Procedure 6 4 View the Cache Lines for 8K Case Step Action 1 Change the number of elements in the test h file to 8K 2 Repeatallthe previous steps as defined in Task 1 and Task 2 3 Build load and run the code to the break point End of Procedure 6 4 QUESTIONS Examine the cache e What is the first entry address What does it mean e What is the last cache line that has the inputComplex vector e How many bytes were read from the inputComplex vector How do you know e What is the number of elements that were read from the inputComplex vector Finding the Bu
27. CPUs Memory Throughput and Access Analysis PC Trace Not applicable on selected CPUs Custom PC Trace Not applicable on selected CPUs Custom System Trace Open File Analysis Dashboard Import Configuration TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x 8 7 8 3 Instructions Chapter 8 STM Library and System Trace Doc ID 122222 6 TheHardware Trace Analysis Configuration window appears as shown in Figure 8 8 Figure 8 8 Hardware Trace Analysis Configuration X Hardware Trace Analysis Configuration DEE a X Memory Throughput and Access Analysis Configuration Graphs the memory access throughput MB s and or the number of bus cycles spent waiting to access memory Name Instrumentation Type Cores Transport Type Memory Throughput and Access Analysis System Trace CSSTM 0 560 V2 Trace e i gt Receiver Transport Settings gt Data Collection Settings Advanced Settings O e 1 Open File gt Analysis Dashboard 2 Import Configuration runtime Log h Zens spannen Mam haa 7 Chose 560 V2 Trace as the transport type and click Start Shortly several windows will open Enlarge the Trace Viewer CSSTM_0 window End of Procedure 8 3 Procedure 8 4 Run the Program Step Action 1 Runthe application by selecting the CCS menu option Run gt Resume 2 The Trace Viewer CSSTM 0 window appears as sho
28. D 122222 11 Noother filtering will be used So both the Address Range Filter and EMU Trigger Filter should be marked false Click OK 12 TheBreakpoint Properties window should now be configured as shown in Figure 7 7 Figure 7 7 Breakpoint Properties Example Configuration Complete Breakpoint Properties amp Breakpoint Properties X vw Properties Values e TE SS O false 4 EventFilter 4 Transaction Type CPU Data Access v true CPU Instruction Ac false DMA Access false Access Type Any 4 Export Configuration Export Access Status lv true Export New Request E iv true Export Last Burst Event false Address Mask Export Bits 29 20 Address Range Filter O false EMU Trigger Filter CO false 4 Miscellaneous i Group Default Group Name Trace 3 4 D d gt All settings under this are handled by the target without intruding on the target s execution Edit Property m Q ok J _ caca End of Procedure 7 5 Procedure 7 6 Start Display Step Action 1 Fromthe Tools menu on the Debug perspective choose Trace Analyzer then Open Trace Connection and select Blackhawk XDS560v2 USB System Trace or your emulator as shown in Figure 7 8 Figure 7 8 Choosing the Trace Analyzer Pin Connect ar E FE CCS Debug Debug ES Port Connect Se y R Wo amp e 7 E i Registers Dir Variables 9o Breakpoints 23 METE TY ESAS S
29. F 4 0 v z L inputComplex 516 Lines L1D cache 0x00808140 0x0080817F 5 0 v S L inputComplex 517 Lines L1D cache 0x00808180 Ox0080818F 6 0 v e Lo rou i L1D cache 0x008081C0 OxO08081FF 7 0 v L ro meest M L1D cache 0x00808200 Ox0080823F 8 0 v a Lo ro LD cache 0x00808240 0x0080827F 9 0 v S L inputComplex 521 Lines L1D cache 0x00808280 Ox0080828F 10 o v S L inputComplex 522 Lines L1D cache 0x008082CO Ox008082FF 11 o v L inputComplex 523 Lines L1D cache 0x00808300 Ox0080833F 12 0 v a L inputComplex 524 Lines L1D cache 0x00808340 0x0080837F 13 0 v L inputComplex 525 Lines L1D cache 0x00808380 Ox0080838F 14 o v S L inputComplex 526 Lines L1D cache 0x008083C0 Oxo0s083FF 15 o v L inputComplex 527 Lines L1D cache 0x00808400 Ox0080843F 16 0 v L inputComplex 528 Lines L1D cache 0x00808440 0x0080847F 17 0 D L inputComplex 529 Lines L1D cache 0x00808480 Ox0080848F 18 0 v L inputComplex 530 Lines L1D cache Ox008084CO Ox008084FF 19 0 v L inputComplex 531 Lines L1D cache 0x00808500 0x0080853F 20 o v L inputComplex 532 Lines L1D cache 0x00808540 0x0080857F 21 o v L inputComplex 533 Lines L1D cache 0x00808580 Ox008085BF 22 0 v L inputComplex 534 Lines L1D cache 0x008085C0 Ox008085FF 23 0 D L inputComplex 535 Lines L1D cache 0x00808600 Ox0080863F 24 o v L inputComplex 536 Lines L1D cache 0x00808640 Ox0080867 25 o v L inputComplex 537 Lines L1D cache 0x00808680 Ox008086
30. I Write Access XID 0x2 Addrathil0 DOR New Request GE 3 3071306 H 128 CPT racer CPT New Request Marter G MI Write Access XIDzOx3 Addr 0x3 10 Dos New Request GE 6 71312 H 128 CPT racer CPT New Request Master GEMI Write Access XID Ol Addr 0 110 DOR New Request GE 3 End of Procedure 7 7 7 3 2 Additional Considerations The time unit in the tracer is in tracer ticks driven from an 87 5MHZ clock So each time unit is 1 87 5 microsecond e Ifthe load is done when the trace is open the trace will log the loading procedure To prevent this load the code before configuring the CCSTM If you want to run the code again load it again and re configure the CCSTM_0 e Playa little more with the CCSTM configuration to see what other values can be traced e Play with the address bits to see how they can affect the trace values e Ifthe trace file is large you have to wait until after the system is stopped for the data to reach the console A percentage value will indicate how much of the trace is already moved to the console You will not see this in the previous example since the trace is short TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 7 15 Product Release MCSDK 2 x 7 3 Instructions Chapter 7 Using MPAX to Define Private Core Memory in DDR Doc ID 122222 7 16 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x 8 1 Purpose Chapter 8
31. IOSingleSRIO out C6000 1e E bioMain pp 2 bioUtilityAndGlobals pp B ecsObjs opt 3 cesSres opt id ice 792 c Berane loshin E Console 2 e HHRIME H 7B E fftRoutines pp CDT Build Console SRIOSingleSRIO cmd file configPkg compiler opt srio drv c n 2 3 E gen twiddle fft1616 pp Finished building srio drv c E initialization pp makefile Building target SRIOSingleSRIO out Invoking C6000 Linker C ti ccs ccsv5 tools compiler c6000 bin clex mv6608 g define LITTLE ENDIAN define TMS320C6600 define TMS320C6600 diag warning 225 abi eabi z RIOSingleSRIO map warn sections e ti ccs ccsv5 tools compiler c6000 1lib i C ti ccs dsplib c66x 3 0 0 8 lib 1 ti ccs ccsv5 tools compiler c6000 include reread libs rom model o SRIOSingleSRIO out 1 configPkg linker cmd srio drv obj slaveTask obj requestProcessingData obj qmss drv obj qmss device P multicoreLoopback osal obj masterTask obj initialization obj gen twiddle fftl6x16 0bj fftRoutines obj device srio loopback obj cppi device obj bioUtilityAndGlobals obj bioMain obj l libc a ldsplib ae66 Ej masterTask pp B multicoreLoopback osal pp objects mk Ej qmss devicepp EB qmss drv pp requestProcessingData pp slaveTask pp sources mk gt stio_drv pp E SRIOMutticore fft 1 map E SRIOSingleSRIO map subdir rules mk s
32. LOOPBACK Comment out this line Ensure that the baud rate is set to 6 25 Gbaud i e the line tde ine hyplnk EXAMPLE SERRATE 06p250 isuncommented Build the code load to both targets and run the generated out file on Core 0 only Modify the example code for hyplnk exampleProject 3a 3b Open hyplnkLLDCfg h Change the Baud Rate to a higher rate 4 Build the code load to both targets and run on Core 0 only Note The two systems must have the same rate End of Procedure 3 7 QUESTION 1 Whatis the highest transfer rate that can be achieved using this example 2 Lookatthe errata documentation and identify the theoretical limit of HyperLink transfer Why is this the case Note The maximum length of the board to board connection should be 4 inches Thus the physical cable connection is not as efficient as a hard wired connection TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 3 5 Product Release MCSDK 2 x 3 2 Instructions Chapter 3 HyperLink Communication Doc ID 122222 3 6 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x 4 1 Purpose SRIO Type 11 The purpose of this exercise is to demonstrate usage of Type 11 SRIO using an example application imported into CCS from the MCSDK 4 2 Project Files The following files are used in this lab 4 3 Instructions bioInclude h bioMain c bioUtilityAndGlobals c device_srio
33. LRU Way Symbols In Cache L1D cache OXDOSO3ECO Ox00803EFF 251 0 v inputComplex 251 Lines L1D cache 0x00803F00 0x00803F3F 252 D V inputComplex 252 Lines L1D cache 0x00803F40 0x00803F7F 253 D V inputComplex 253 Lines L1D cache 0x00803F80 Ox00803FBF 254 D V inputComplex 4 254 Lines L1D cache 0x00803FCO Ox00803FFF 255 0 v inputComplex 4 255 Lines L1D cache 0x00808CCO Ox00808CFF 51 1 V D L L1D cache Ox00808D00 Ox00808D3F 52 1 V D E L1D cache 0x00808D40 Ox00808D7F 53 1 V D L PESAJE 0x00808080 Cache line starts at 000808040 P E L1D cache 0x00808F00 1 V e L1D cache 0x00808F40 Ox00808F7F 61 D V D L L1D cache 0x00808F80 Ox00808FBF 62 V D L L1D cache Ox00808FCO Ox00808FFF 63 D v D L L1D cache 0x00809000 0x0080903F 64 1 v D L _sys_memory 0x00809000 L1D cache 0x0080A000 Ox0080A03F 128 1 v D L _ftable 0x0080A000 L1D cache 0x0080A 1CO 0x0080A1FF 135 1 Vv L _ftable 7 Lines End 0x0080A 1DF _stream 0x L1D cache 0x0080A280 Ox0080A2BF 138 1 v S E _device 0x0080A280 L1D cache 0x0080A300 Ox0080A33F 140 D v D L TI_enable_exit_profile_output 0x0080A300 m L1D cache 0x0080A440 0x0080A47F 145 D V D L _tmpnams 5 Lines End 0x0080A45F parmbuf L1P cache Ox0CO005CO OxOCO005DF 46 D V _getarg_diouxp 0x0C0005C0 L1P cache Ox0C0005E0 O0xO0COO05FF 47 0 V _getarg_diouxp 1Line L1P cache 0x0C000600 0x0C00061F 48 0 V _getarg_diouxp 2 Lines L1P cache Ox0C000620 Ox0COO063F 49 0 v _getarg_
34. Link Communication 10 Select Build properties choose C6000 Compiler gt Include Options and ensure that include paths are setup as shown in Figure 3 1 Figure 3 1 C6000 Compiler Include Options Include Options Configuration Debug Active Add dir to include search path include path T S PDK INSTALL PATH S PDK INSTALL PATHJ ti csl src intc S PDK INSTALL PATH ti drv hyplnk example common 11 Clickthe OK button to save the project properties and close the Properties window End of Procedure 3 2 Procedure 3 3 Loopback Mode Step Action 1 Lookforthe following line in hypinkLLDCfg h and verify that it is uncommented define hyplnk EXAMPLE LOOPBACK When uncommented this define ensures that the example runs in loopback mode on a single EVM End of Procedure 3 3 Procedure 3 4 Build the Project Step Action 1 In Project Explorer select the hyplnk exampleProject project 2 Build the project 2a Select the CCS menu option Project Build Project OR 2b Right click on the project in Project Explorer and select Build Project 3 CCSwill now attempt to compile and link the project This may take a few minutes to complete 4 Please direct your attention to the CCS Console On a successful build you will see no errors generated in the Problems window NOTE There may be warnings and the following message should display in the Console window Linking Finished building target h
35. MCSDK 2 x Doc ID 122222 6 7 3 Instructions Chapter 7 Using MPAX to Define Private Core Memory in DDR The full Trace Display should appear as shown in Figure 7 11 Figure 7 11 Trace Display Results Full Frame KS Tem Toc Rum Sermpts Window Help ek e Or pre p n Sz CCS Bebog mp CCS eae a D Memory Browser D 3 Showing 162 Samples all data Stopped by user upload complete Receiver Clock 87 5 MHz Trace Data Rate 200 0145875 MHz amp Ja gt Glan alr Delta Time Time Function Start Mate Ei Master Name Channel Number Module Date Message Des Domain Class 0 0 3 3 H 128 CP Tracer CPT New Request Master GEMO Write Access XID 0 0 Addratxi00 DDR New Request GE 5 D o 128 CPTracer CPT New Request Master GEMO Write Access XIDz0x1 Addrz0x100 DOR New Request GE 5 B o 128 CPTracer CPT New Request Master GEMO Write Access XIDe 2 Addr 0 100 DOR New Request GE 6 19 0 128 CPTracer CPT New Request Masterz GEMO Write Access XID 0x3 Addr 0 100 DOR New Request GE E 5 a H 128 CPTracer CPT New Request Masterz GEMO Wree Access XID Ov Addr 0 300 Dos New RequestGE 3 n 0 128 CPTracer CPT New Request Masters GEMO Write Access IDs 0x5 Addrs O00 DDR New Request GE 6 33 H 18 CPTracer CPT New Request Masterz GEMO Write Access XID Oxh Addr 0x100 DOR New Request GE 5 3 0 128 CP Tracer CPT New Request Master GEMO Write Access XID 07 Addrs d 00 DOR New Request GE 5 a 0 18 CPT racer CPT New Request Mast
36. Project should now appear in the CCS Project Explorer on the left hand side of your screen End of Procedure 3 1 QUESTIONS Expand the hyplnk exampleProject folder and double click on hypinkLLDCfg h to view the file and answer the following 1 How many lanes are configured 2 What is the baud rate HINT 01p250 means 1 25GBaud Procedure 3 2 Verify and Set Project Properties Step Action 1 In Project Explorer right click on hyplnk exampleProject and select Properties 2 Select General properties 3 Choose the Main tab and set verify the Device properties as follows Family C6000 e Variant Generic C66x Device Select Build properties 5 Choose C6000 Compiler gt Processor Options and set verify the following properties e Configuration Debug e Target processor version 6600 e Application binary interface eabi Note In different versions of CCS the Application binary interface tab is located in the main tab Select Build properties 7 Choose C6000 Compiler gt Optimization and set verify the following properties e Optimization level 0 e Optimize for code size 0 8 Select Build properties 9 Choose C6000 Compiler 2 Debug Options and set verify the following properties e Debugging model Full symbolic debug 3 2 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x 3 2 Instructions Doc ID 122222 Chapter 3 Hyper
37. TMS320TCI66x Keystone Multicore Workshop Lab Manual Publication Number SPRP820 Publication Date April 2014 I3 TEXAS INSTRUMENTS Texas Instruments Incorporated 20450 Century Boulevard Germantown MD 20874 USA Copyright and Contact Information Copyright and Contact Information Document Copyright Software Copyright Contact Information General Publication Title TMS320TCI66x Keystone Multicore Workshop Lab Manual Publication Number SPRP820 Revision A 2014 Texas Instruments Incorporated All Rights Reserved Reproduction adaptation or translation without prior written permission is prohibited except as allowed under the copyright laws Product Name TMS320TCI66x Product Release MCSDK 2 x O 2014 Texas Instruments Incorporated All Rights Reserved 20450 Century Boulevard Germantown MD 20874 Voice 301 515 8580 Fax 301 515 7687 Web www ti com Broadband Voice over IP Sales Information E mail mktgsupport list ti com Applications Engineering For Registered Customers Only E mail tech supportati com The Telogy Software Applications Engineering group is available to all customers who need technical assistance with a Telogy product technology or solution Inquiries are categorized according to the urgency of the issue as follows Priority Level 4 P4 You need information or assistance about Telogy product capabilities product installation or basic product configura
38. View Project Tools Run Scnpts Window Help br ox dr r 35 Debug X Target Configurations lt x t Pr Vanables Of Express tud e Es Projects User Defined 4 Usethe target configuration that you created in Preparations on page 1 1 To create a new target configuration follow Create a New Target in CCS on page 1 2 5 Launch the target configuration as follows 5a Selectthe target configuration ccxml file 5b Right click and select Launch Selected Configuration 6 This will bring up the Debug window 6a Select Core 0 C 6x 0 6b Right click and select Connect Target End of Procedure 8 2 Procedure 8 3 Load the Program and Configure the Trace Step Action Note These instructions are for CCS V5 4 For CCS V5 3 follow the instructions in Chapter 7 Using MPAX to Define Private Core Memory in DDR on page 7 1 1 Select Core O and load the out file created earlier in this exercise 1a Select the CCS menu option Run Load Load Program 1b Click Browse project 1c Select by unwrapping the stmSimpleExample gt Debug and click OK 1d Click OK to load the StmSimpleExample out application to the target Core 0 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 8 5 Product Release MCSDK 2 x 8 3 Instructions Chapter 8 STM Library and System Trace Doc ID 122222 2 As shown in Figure 8 4 select the top line in the debug window right click and select Show all cores Figure 8
39. _loopback c ExampleSRIO cmd fftRoutines c gen twiddle fft16x16 c initialization c masterTask c multicoreLoopback_osal c requestProcessingData c slaveTask c SRIOMulticore_fft_1 cfg First you will import the example project from MCSDK to CCS Next you will build an application from the project and load it to the EVM Finally you will run the project and observe the results The list of processes used in this example are as follows Procedure 4 1 Import the Project Procedure 4 2 Build the Project Procedure 4 3 Connect to the EVM Procedure 4 4 Load and Run TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 4 1 Product Release MCSDK 2 x 4 3 Instructions Chapter 4 SRIO Type 11 Doc ID 122222 Procedure 4 1 Import the Project Step Action 1 Open CCS 2 Once CCS starts verify that the perspective is set to CCS Edit 3 Importthe project 3a Select the CCS menu option Project Import Existing CCS Eclipse Project 3b SetSelect search directory to point to where the project files for this exercise are located on your computer 3c From the list of Discovered projects place a check mark in the box next to SR OSingleSRIO 3d Place a check mark on Copy projects into workspace 3e Clickthe Finish button End of Procedure 4 1 Procedure 4 2 Build the Project Step Action 1 In Project Explorer select the SRIOSingleSRIO project 2 Clean the project by right clicking on the proje
40. a REM ERR UR ERE RS 5 3 Procedure 5 3 LO AMI R n th Progtarri ii e 2 EL eR M is 5 4 Procedure 5 4 Compiler Optimization S mr ebe RR eR De S EE Eed Eed e es riesce RET ada 5 4 Procedure 5 5 Enable Software Pipelining o terre dee awa A NEEN NEE NEE eee eRe EU 5 6 Procedure 5 6 Alita ovre EN ee o reus 5 7 Procedure 5 7 Enable the MUST ITERATE Pragma ehe heh hehe heh hehe ehe hee 5 7 Procedure 5 8 Cache Considera EEN EAE RC A AA EE I TRI SpA Ee S 5 8 Procedure 6 1 View the Cases cota s eet aa geen ER HEU eI e Ue ERE ULP E ERN e S VI 6 2 Procedure 6 2 Looking at the Cache Lines for 4K Case 6 4 Procedure 6 3 View the Cache Lines for 16K Case 2 2 0 eee cece ee cee ree eee he mH ehe he heme e hene 6 8 Procedure 6 4 View the Cache Lines for 8K Case 2 eee cee eee cee eee ene cent nee he hh he hse eee ehe 6 9 Procedure 7 1 RUN the Example Code es visa ciet eR EU Walesa Red V VERS LECCE VE E EN ERE VER Gales 7 5 Procedure 7 2 Connect to the Non debuggable Devices Esp CCTMS_0 cee cece eee teen e eee mh me hen 7 6 Procedure 7 3 Loadthe Code to tlie 8 Cores icine e ese em te a Xe p dieere E EN CU E Atene 7 7 Procedure 7 4 Configure the CSSTM O Trace Control 7 7 Procedure 7 5 Add and Configure the Trace Location 7 9 Procedure 7 6 Start DIA 01E EE 7 12 Procedure 7 7 Enable the Trace Point and Run 7 13 Procedure 8 1 Build aridiR rthe Project cese ee e desee n agen A uereg 8 2 Procedure 8 2 Connect to the EVM exse oar FERIIS d
41. a is aligned on 64 bit 3 Rebuild the code load and run Record the optimized project cycle time for natural C function and for intrinsic function with software pipeline and aligned load End of Procedure 5 6 Procedure 5 7 Enable the MUST_ITERATE Pragma Step Action 1 Uncomment the code to enable the pragmas that tell the compiler the minimum number of iterations and the divisor 2 Rebuild the code load and run Record the optimized project cycle time for natural C function and for intrinsic function with software pipeline aligned load and MUST_ITERATE pragma End of Procedure 5 7 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 5 7 Product Release MCSDK 2 x 5 3 Instructions Chapter 5 Optimization Doc ID 122222 Procedure 5 8 Cache Considerations Step Action 1 In test h change the number of elements to 2K 4K 8K and 16K 2 In Table 5 1 record the cycle counts for each case Table 5 1 Clock Values amp Cycle Counts Size Multiply for 32K Clock Value Cycles for 32K 32K 1 16K 2 8K 4 4K 8 2K 16 End of Table 5 1 QUESTION Why the non linear jump in performance Note Think about cache trashing End of Procedure 5 8 5 3 1 Cache Analysis QUESTION Think about the data size and the fact that float complex requires 8 bytes single precision What is the actual size of the data Note To understand better the cache
42. able Software Pipelining e Procedure 5 6 Align the Data e Procedure 5 7 Enable the MUST ITERATE Pragma e Procedure 5 8 Cache Considerations TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 5 1 Product Release MCSDK 2 x 5 3 Instructions Chapter 5 Optimization Doc ID 122222 Procedure 5 1 Build and Run the Project Step Action 1 OpenCCS 2 Create new project through the CCS menu item File gt New gt CCS Project 3 Enter Optimization as a Project Name A Clickthe check box to Use default location 5 Setthe Family to C6000 and Variant to Generic C66xxx Device as shown in Figure 5 1 Figure 5 1 CCS Project Settings Se New CCS Project Sme CCS Project Create a new CCS Project Project name optimization Output type Executable Use default location Location C Users a0270985 WorkSpaces temp optimization Device Family C6000 Variant select or type filter text connection Advanced settings Project templates and examples type filter text Creates an empty project fully initialized for the selected device 4 E Empty Projects gj Empty Project f Empty Project with main c f Empty Assembly only Project f Empty RTSC Project 4 E Basic Examples f Hello World b E IPC and I O Examples Note The screen shots may reflect different location for the project Then press Finish to create the new pro
43. and load the code from the debug configuration the one with no optimization and full symbolic debug From the Run menu in the Debug perspective enable the Clock Open the file intrinsicCfilters c and put a breakpoint after the first filter TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x Doc ID 122222 6 2 Instructions Chapter 6 Using Advanced Debug 6 Runthe code and verify that it stopped at this breakpoint which should appear as shown in Figure 6 1 Figure 6 1 CCS Debug IntrinsicCFilters Breakpoint PES File Edit View Project Tools Run Scripts Window Help D eg Ox oe Sne e i Debug 5i Bll m3 3 9 el 7 697 B a Kai evm6678Trace ccxml Code Composer Studio Device Debugging 4 G9 Group1 4 gf Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 0 Suspended SW Breakpoint intrinsicC filters float int float at intrinsicCFilters c 47 0x0COO19F4 0x20202020 no symbols are defined for 0x20202020 2 Blackhawk XDS560v2 USB System Trace Emulator_0 C66xx_1 Disconnected e Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 2 Disconnected e Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 3 Disconnected 2 Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 4 Disconnected 2 Blackhawk XDS560v2 USB System Trace Emulator_0 C66xx_5 Disconnected 2 Blackhawk XDS560v2 USB System Trace Emulator_0 C66xx_6 Disconnected e Blackhaw
44. apter 2 CCS Basics SRIO Loopback 4 Then select the CCS menu option Run gt Suspend OR Click on the two yellow bars next to the green arrow The expected output on the console should appear as follows C66xx 0 Executing the SRIO DIO example on the DEVICE C66xx 0 Debug Core 0 System Initialization for CPPI amp QMSS C66xx 0 Debug Core 0 Queue Manager and CPPI are initialized C66xx 0 Debug Core 0 Host Region 0x8268f0 C66xx 0 Debug Core 0 SRIO Driver has been initialized C66xx 0 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk C66xx 0 DIO Socket Example with Interrupts Core 0 C66xx 0 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk C66xx 0 Debug Core 0 Starting the DIO Data Transfer Src 0 0x 1081b100 Dst 0 0x 1081b200 C66xx 0 Debug Core 0 Starting the DIO Data Transfer Src 8 0x 1081c100 Dst 8 0x 1081c200 C66xx 0 Debug Core 0 DIO Socket 0 Send for iteration 0 C66xx 0 Debug Core 0 ISR Count 1 C66xx 0 Debug Core 0 DIO Socket 2 Send for iteration 2 C66xx 0 Debug Core 0 ISR Count 9 C66xx 0 Debug Core 0 Transfer Completion without Errors 9 C66xx 0 Debug Core 0 Transfer Completion with Errors 0 C66xx 0 Debug Core 0 DIO Transfer Data Validated for all iterations C66xx 0 Debug Core 0 DIO Data Transfer WRITE with Interrupts Example Passed C66xx 0 kkkkxkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkk
45. as Instruments Silicon and Telogy Software Documents The following Texas Instruments Telogy Software produced documents are provided with TNETVxxxx Release x x e DSP Module Software Architecture e MXP Operating Environment Reference GuideMXP Operating Environment User s Manual Document Conventions This document uses the following conventions e Commands and keywords are in boldface font e Arguments for which you supply values are in italic font e Terminal sessions and information the system displays are in screen font e Information you must enter isin boldface screen font e Elements in square brackets are optional TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A GV Product Release MCSDK 2 x Preface Notes use the following conventions NOTE Means reader take note Notes contain helpful suggestions or references to material not covered in the publication The information in a caution or a warning is provided for your protection Please read each caution and warning carefully CAUTION Indicates the possibility of service interruption if precautions are not taken WARNING Indicates the possibility of damage to equipment if precautions are not taken 9 vi TMS320TCI66x Keystone Multicore Workshop Lab Manual BookID SPRP820 A Product Release MCSDK 2 x Contents Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Contents Copyright a
46. ave Memory ino A EES Load Memory 3 Fill Memory x 0 Suspended di RTOS Object View ROV k RTOS Analyzer t was reached 2 x 1 Suspended lii System Analyzer D KE ESCH was reached a Image Analyzer xx 2 Suspended Profile D Trace Analyzer Open Trace Connection In New View lt Blackhawk XDS560v2 USB System Trace Emulator_0 C66xx_0 is not traceable gt Trace Control Open Trace File In New View Blackhawk XDS560v2 USB System Trace Emulator 0 CSSTM 0 XDAIS Tools gt Open Trace Connection See 2 TheTrace window will appear End of Procedure 7 6 7 12 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x 7 3 Instructions Doc ID 122222 Chapter 7 Using MPAX to Define Private Core Memory in DDR Procedure 7 7 Enable the Trace Point and Run Step Action 1 If you have not already done so enable the Trace point in the Breakpoint window 2 Runthe code on all 8 cores 3 Waitfor the printfto verify that all cores are done 4 Stop Run on all of the cores It may take several seconds for all the data to get into the CCS Once it is there the results will appear as shown in Figure 7 9 Figure 7 9 Trace Results T OCS Debug COR CREE File Edit View Proyect Tools Rum Sempts Window Help ri e Dr 9 Die s t3 S gt CCS Edi 3 Debug amp o DDD e Se S gt O Mt regates H Variables 3 ORBE A GEI det a BD e m 678Trace coml Code Composer S
47. ct and selecting Clean Build 3 Build the project 3a Select the CCS menu option Project Build Project OR 3b Right click on the project in Project Explorer and select Build Project A CCSwill now attempt to compile and link the project This may take a few minutes to complete 4 2 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x 43 Instructions Doc ID 122222 Chapter 4 SRIO Type 11 5 Verify that the executable out was built by looking at the debug directory assuming the build configuration is debug configuration as shown in Figure 4 1 Figure 4 1 Verify Successful out Build File Edit View Navigate Project Run Scripts Window Help Ces Zeen Beie Se E Target Configurations ES CCS Debug 15 exampleTest 15 largeFIR_Energy S SRIO_LoopbackDiolsrexampleproject 4 3 SRIOSingleSRIO Active Debug 2 Binaries E Includes 4 Debug configPkg si bioMain obj C6000 le ls bioUtilityAndGlobals obj C6000 le ei cppi_device obj C6000 1e i device srio loopback obj C6000 le si fftRoutines obj C6000 le si gen twiddle fftl6x16 obj C6000 1e si initialization obj C6000 1e si masterTask obj C6000 1e la multicoreLoopback_osal obj C6000 1e i qmss device obj C6000 le si qmss drv obj C6000 1e lar requestProcessingData obj C6000 1e s slaveTask obj C6000 1e si srio_drv obj C6000 1e O SR
48. d set verify the following properties e Debugging model Full symbolic debug 11d Choose C6000 Compiler gt Include Options Under the Add dir to include search path add the following two paths e PDK_ROOT packages ti csl e S PDK_ROOTY packages Note This ensures that any include references in the project s source files to header files located at these paths will be interpreted accurately Click the OK button to save the project properties and close the Properties window Right click on the project and select Build Project A successful build will generate the following output on the console Linking Finished building target optimization out Build Finished End of Procedure 5 1 Procedure 5 2 Connect to the EVM Step Action 1 Click the Open Perspective available right top corner of the CCS 2 Switchtothe Debug Perspective by selecting the CCS menu option Window Open Perspective CCS Debug 3 Selectthe CCS menu option View Target Configurations Select the target configuration you created 4 Launchthe target configuration as follows 4a Selectthe target configuration ccxml file 4b Right click and select Launch Selected Configuration 5 This will bring up the Debug window 5a Select Core 0 C 6x 0 5b Right click and select Connect Target End of Procedure 5 2 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 5 3 Product Release MCSDK 2 x 5 3
49. diouxp 3 Lines L1P cache 0x0C000640 OxO0COO065F 50 D V _getarg_diouxp 4 Lines End of Procedure 6 2 QUESTIONS e What is the last cache line that has the inputComplex vector e How many bytes were read from the inputComplex vector e What is the number of elements that were read from the inputComplex vector TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 6 7 Product Release MCSDK 2 x 6 2 Instructions Chapter 6 Using Advanced Debug Doc ID 122222 Procedure 6 3 View the Cache Lines for 16K Case Step Action 1 Changethe number of elements in the test h file to 16K define NUMBER OF ELEMENTS 16384 Repeat all the previous steps as defined in Task 1 and Task 2 Build load and run the code to the break point The cache lines should be the same or similar to those shown in Figure 6 6 Figure 6 6 CCS Debug IntrinsicCFilters L1D Cache Lines 16K ri oy Mr a Dbe i e El Console Memory Map EB Table Cache Tag RAM Read complete 1536 Cache Lines read from target 989 after filtering Cache Line Start Adrs Line End Adrs Set Way Valid Dirty LRU Way Symbols In Cache L1D cache 0x00808000 Ox0080803F 0 0 D L inputComplex 512 Lines L1D cache 0x00808040 Ox0080807F 1 0 v L inputComplex 513 Lines L1D cache 0x00808080 OxO080808F 2 0 v s L inputComplex 514 Lines L1D cache 0x008080C0 OxO08080FF 3 0 v L inputComplex 515 Lines L1D cache 0x00808100 Ox0080813
50. e MCSDK 2 x Doc ID 122222 7 2 Overview Chapter 7 Using MPAX to Define Private Core Memory in DDR 7 2 4 Platform Configuration and the Memory Map Projects that use RTSC must define the platform The platform defines what memories are used in the execution In addition to L1 L2 and the MSMC memory the external memory DDR is defined Usually DDR is defined as 2G bytes memory for the 6678 EVM In the example you will reduce the size of DDR to 1G You will then use the other 1G for private memories The default settings of the MPAX registers for all cores are as follows e Register O value is 0000001E 000000BF gt correspondent to 2G mapping of internal memory into itself e Register 1 value is 8000001E 800000BF gt maps the 2G external memory 8000 0000 to ffff ffff into the 36 bit range 8 0000 0000 to 8 7fff ffff e Register 2 value is 2100000b 100000ff gt Maps again 4K starting at address 0x21000000 to address 1 0000 0000 This is the DDR EMIF configuration registers Note that if the same memory range is defined in multiple MPAX registers the higher MPAX register translation is used e Registers 3 to 15 values are 00000000 00000080 which basically points to empty memory regions In this example the first DDR are divided into two parts e A shared 256M DDR starting at logical address 0x8000 0000 to address Ox8fff ffff physical address 8 0000 0000 to address 8 Offf ffff e A private 16M DDR for each core The lo
51. e Emulator_0 C66xx_1 Disconnected Unknown Xe Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 2 Disconnected Unknown 2 Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 3 Disconnected Unknown Xe Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 4 Disconnected Unknown Xe Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 5 Disconnected Unknown Xe Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 6 Disconnected Unknown 2 Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 7 Disconnected Unknown 7a Select Core 0 C 6x 0 7b Right click and select Connect Target End of Procedure 2 4 Procedure 2 5 Load and Run the Program Step Action 1 Select Core 0 and load the out file created earlier in the lab 1a Select the CCS menu option Run Load Load Program 1b Click Browse project 1c Apop up will appear with the projects names 1d Select SRIO_LoopbackDiolsrexampleproject le Click Debug then select SR O LoopbackDiolsrexampleproject out and click OK 1f Click OK to load the application to the target Core 0 2 Run tbe application by selecting the CCS menu option Run gt Resume OR Click on the green arrow 3 Once the program completes successfully you will see the message Debug Core 0 DIO with Interrupts example completed successfully 2 6 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x Doc ID 122222 2 2 Instructions Ch
52. e the CSSTM_0 Trace Control e Procedure 7 5 Add and Configure the Trace Location e Procedure 7 6 Start Display e Procedure 7 7 Enable the Trace Point and Run Note This exercise requires a mezzanine card with a trace emulator on the target platform Procedure 7 1 Run the Example Code Step Action 1 Load MPAX registerDemo from c temp lab directory and look at its properties Make sure that all the relative paths exist in your system symbols 2 Choose how you want to configure the MPAX register using CSL or direct register manipulation or both Change the if in two places to 0 or 1 3 Rebuild the project Connect EVM6678 and start the debugger Connect all the cores and load the code to all the cores 5 Runall the cores The printing will tell you when each core is done A delay function staggers the cores When all cores print the done statement they are all in infinite loop Pause all the cores 7 Repeatthe following for each of the cores 7a Select a single core 7b Open a memory view window View gt memory 7c Lookat address 0x9000 0000 for all cores This is external memory 7d Corezero will have values start at O 1 2 etc Ze Core 1 will have values 0x0002 0000 and incrementing by 1 7f Core 2 will have the first value 0x0004 0000 and incrementing by 1 7g Core3 4 5 6 and 7 will have first values 0x0006 0000 0x0008 0000 0x000a 0000 0x000c 0000 and 0x000e 0000 respectively C
53. erz GEMO Write Access XIDz 098 Addrz 01100 oR New Request GE 4 a H 128 CPT racer CPT New Request Master GEMO Write Access XID 0 9 Addrati00 DDR New Request GE 5 5 H 128 CPT racer CPT New Request Maier GEMO Write Access XID 0xx Addr 0x100 Dos New Request GE 5 Di H 128 CPTracer CRT New Request Masters GEMO Write Access XID 0xb Addr 0 100 DOR New Request GE 5 H 128 CP Tracer CPT New Request Masterz GEMO Write Access XIDzOxc AddrzOx100 DDR New Request GE 4 e H 128 CPTracer CPT New Request Masterz GEMO Wree Access ID Onc Addr 0 100 Dos New RequestGE 5 n 9 128 CPTracer CPT New Request Masters GEMO Write Access ID One Addrs DA DDR New RequestGE 5 Li H 18 CPT racer CPT New Request Master GEMO Witte Access Hieft Addr 0x300 DOR New Request GE 6 sa 0 128 CPT racer CPT New Request Masters GEMO Write Access XID 0 0 Addr 0 100 DDR New Request GE 3 85 H M8 CPT racer CPT New Request Masterz GEMD Write Access XIDz 0x Addr 0x100 DOR New Request GE 5 E H 128 CP Tracer CPT New Request Master GEMO Write Access XID 0x2 Addrati00 DDR New Request GE 6 96 H 128 CPT racer CPT New Request Maier GEMO Write Acces XID 0x3 Addrz0x100 Dos New Request GE 3071128 2071224 H 18 CPTracer CPT New Request Masters GEMI Write Access XID 0 2 Addr nd10 DDR New Request GE 5 3021228 H 128 CPT racer CPT New Request Marter G MI Write Access XIDz x3 Addr 0x3 10 Dos New Request GE 397123 0 128 CPTracer CPT New Request Master GEMI Wree Acce
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55. essary expertise to create and implement safeguards which anticipate dangerous consequences of failures monitor failures and their consequences lessen the likelihood of failures that might cause harm and take appropriate remedial actions Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety critical applications In some cases TI components may be promoted specifically to facilitate safety related applications With such components TI s goal is to help enable customers to design and create their own end product solutions that meet applicable functional safety standards and requirements Nonetheless such components are subject to these terms No TI components are authorized for use in FDA Class III or similar life critical medical equipment unless authorized officers of the parties have executed a special agreement specifically governing such use Only those TI components which TI has specifically designated as military grade or enhanced plastic are designed and intended for use in military aerospace applications or environments Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer s risk and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use TI has specifically designated certain components as meeting ISO TS16949 re
56. est Mas 8382 7 The MAR registers for logical wiren mm mg vo attt ttft 4 3 2 e 18 CP Teecer CPT New Request Mas oif 1 6 3 o 18 CPTrcer CPT New Request Mas 141 lvtlarPtr volatile uint 2 t 0x88000020 a 5 3 o 128 CPTeacer CPT New Request Mas 142 In gt 4 Um E Console 13 Ff GEL Files ES Table BB Duration Summary ALL D Cache mot DA eu 678 Trace comb C10 c66xx_3 Unsigned value gt 00613000 C669 4 Unsigned Value gt 00614000 c66xx 5 Unsigned Value gt 00815009 C66xx_3 MPAX register 4 gt 813000bf 90000017 C66xx 4 MPAX register 4 gt B14000bf 90000017 c nxx 5 meax register 4 gt siseeebf 99000017 C66xx 3 MPAX register 4 gt S1I000bf 90000017 C66xx 4 MPAX register 4 gt 8140Q0bf 90000017 C66xx 5 MPAX register 4 gt 615000bf 90000017 dl C66x_3 Core 3 is Done gt 3 C66xx_4 Core 4 45 Done gt 4 o 8 Ucenses 5 Double click on the Trace Display window to enlarge it as shown in Figure 7 10 Focus on the central part of the window and notice how each core writes to a different physical address TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 7 13 Product Release MCSDK 2 x 7 3 Instructions Chapter 7 Using MPAX to Define Private Core Memory in DDR Doc ID 122222 Figure 7 10 Trace Display Results Core Details Master GEMO Write Access XID 0x0 Addr 0x100 Master GEMO Write Access XID 0x1 Addr 0x100 Master GEMO Write Access XID 0x2
57. eu une exo dde i eden ee tse E die Re VIE ER MON 8 5 Procedure 8 3 Load the Program and Configure the Trace 8 5 Procedure 8 4 Runthe Program ere E S eh gee dE ge eds A A ea a Len ees E RES NV ERU UON ds 8 8 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A xi Product Release MCSDK 2 x List of Procedures xii TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x Preparations 1 1 Introduction The exercises in this manual were developed for delivery in a classroom environment but have been adapted for use in a personal lab environment Variations in network configuration software installation software version and Host PC configuration could result in different outcomes 1 2 Software The exercises in this manual require the following software installations e Multicore Software Development Kit MCSDK Version 2 x or later e Code Composer Studio CCS Version 5 x or later For more information refer to the BIOS MCSDK Getting Started Guide http processors wiki ti com index php BIOS MCSDK 2 0 Getting Started Guide 1 3 EVM Configuration All exercises in this manual were designed for use on the TMS320C6678 Lite evaluation modules from Texas Instruments While these procedures have not been tested on the TMS320C6657 and the EVMK2H they should also work on those devices For labs requiring a mezzanine card with a trace emulator the TMS320C6678LE is
58. g You should now understand that the number of elements as defined in test h is not the number of elements that are actually read from the input vector Can you suggest a bug fix in firMain c that will fix the problem Write your answer below TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 6 9 Product Release MCSDK 2 x 6 2 Instructions Chapter 6 Using Advanced Debug Doc ID 122222 6 10 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x Using MPAX to Define Private Core Memory in DDR 7 1 Purpose A typical multicore scenario uses multiple cores to run the same code but requires different data and configuration structures Downloading the same execution code for multiple cores is very efficient However since each core has its own configuration and data structures these values must reside in the private memory of each core Namely L2 SRAM or in LID SRAM if the complete L1 D is not configured as cache However the size of L2 is limited to 512K bytes for C6678 and 1024K bytes for C6670 In addition L2 is usually partitioned into L2 cache and L2 RAM so that the available L2 RAM size is smaller In many cases the amount of private data does not fit into the available L2 RAM This exercise presents a simple way to configure part of the external DDR as a private memory such that each core sees only its own data and structures TMS320TCI66x Keyst
59. gical address starts at 0x9000 0000 to 0x97ff ffff with physical address depends on the core number as follows Core0 gt 8 1000 0000 to 8 10ff OTT Core 1 gt 81100 0000 to 8 11ff ffff Core2 gt 8 1200 0000 to 8 12ff ffff Core3 gt 8 1300 0000 to 8 13ff ffff Core4 gt 8 1400 0000 to 8 14ff ffff Core 5 8 1500 0000 to 8 15ff ffff Core 6 8 1600 0000 to 8 16ff ffff Core 7 81700 0000 to 8 17ff ffff To perform the translation MPAX Register 4 will be used The high 32 bits of the register has the base logical address 5 bytes and one minus the log base 2 of the size Since the size of the private memory is 16M 2 24 the size is 23 or 10111b 0x17 Thus the high 32 bit of MPAX register number 3 should be 0x90000017 bit 5 to 11 are reserved The law 32 bit of MPAX 3 has the physical address 6 bytes and 2 bytes of the permission value In this example full permission values are given to the user and Supervisor Thus the permission value is 0011 1111b or 0x3f TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 7 3 Product Release MCSDK 2 x 7 2 Overview Chapter 7 Using MPAX to Define Private Core Memory in DDR Doc ID 122222 7 4 The physical address part of the law 32 bit depends on the core number Based on the values from above the law 32 bits are e Core 0 gt 0x810000 3f e Core 1 gt 0x811000 3f e Core 2 0x812000 3f e Core 3 gt 0x813000 3f e Core 4 0x8
60. gure 2 2 6a Select the target configuration ccxml file 6b Right click and select Launch Selected Configuration Figure 2 2 Launch Target Configuration CCS Edit Code File Edit View Navigate j Run Scripts Window Help F3 da 4 4 S bi a A v a Be m cov Project Explorer i El Ej abortQ at CH x d E Can tfinda r Locate the fi type filter text u e Projects View Disass 4 z User Defined 8 DAC com Locate File 2 KeplerDSP ccxml 2 KeplerNoGel ccxml 2 ShannonSimulator ccxml Shannon 6678 ccxml TCI6638 ccxml gj TI v100 ccxml 2 TwoMezzanine6678 ccxml c6678MPAX4 ccxml evm6678Trace c evmWithLinux cexn New Target Configuration Import Target Configuration X Delete Delete Rename F2 amp Refresh FS ai Launch Selected Configuration Set as Default Link File To Project Properties TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 2 5 Product Release MCSDK 2 x 2 2 Instructions Chapter 2 CCS Basics SRIO Loopback Doc ID 122222 7 This will bring up the Debug window as shown in Figure 2 3 Figure 2 3 CCS Debug Window for evm6678Trace ccxml File Edit View Project Tools Run Scripts Window Help ri dee wl a gt 2 B Debug E d a 4 Kai evm6678Trace ccxml Code Composer Studio Device Debugging e Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 0 Disconnected Unknown a Blackhawk XDS560v2 USB System Trac
61. hen click Open e For EVM6657L LE select Cati ccsv5 ccs_base emulation boards evmc6657I gel evmc6657I gel e For EVM6678L LE select Cati ccsv5 ccs_base emulation boards evmc6678l gel evmc6678l gel 5e Click the Save button End of Procedure 1 1 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 1 3 Product Release MCSDK 2 x 1 3 EVM Configuration Preparations Doc ID 122222 1 4 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x 2 1 Purpose Chapter 2 CCS Basics SRIO Loopback The purpose of this exercise is to demonstrate how to build and run a very basic Code Composer Studio CCS project on the C6678 EVM The Direct IO Loopback example delivered with the MCSDK is used to help illustrate these concepts 2 2 Instructions In this exercise you will import a sample project from the MCSDK into CCS build the sample application code connect to the EVM load the code run the application and verify the results The list of processes used in this example are as follows Procedure 2 1 Import the Example Project Procedure 2 2 Verify and Set Project Properties Procedure 2 3 Build the Project Procedure 2 4 Connect to the Target EVM Procedure 2 5 Load and Run the Program Procedure 2 1 Import the Example Project Step Action Launch CCS by double clicking the icon on the desktop 1 Note As CCS initializes a
62. int Properties Example Configuration X Properties for a E I i 1 03 Breakpoint Properties e Breakpoint Properties X vw Properties Values 4 Transaction Monitor DDR3 a Function Transaction Logging a Transaction Master SRIO_CPPI false 4 GEM v true GEMO sl true DEM sl true GEM2 sl true GEM3 iv true GEM4 true GEMS lv true GEM6 iv true i GEM7 M true GEMO CFG false GEM1 CFG false GEM2 CFG O false i GEM3 CFG false 3 al 7 r F All settings under this are handled by the target without intruding on the target s execution l O 8 Scroll down in the window to Event Filter Transaction Type and set Only CPU access to true 9 Export Configuration should be set to true for Status and New Requests 7 10 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x Doc ID 122222 7 3 Instructions Chapter 7 Using MPAX to Define Private Core Memory in DDR 10 Address mask In this example you want to see the physical addresses The trace can show only 10 bits of address So you want to choose the right bits Of course you can run the trace multiple times with each trace covering a different set of bits All of the writes are into DDR3 and that the physical addresses always start at 8 1N00 0000 where N is the core number So the 10 bits that you are going to choose f
63. issue you should consider performing the cache debug exercise in this document 5 3 2 Change the Code to Speed Up to 32K Change the code to increase the speed to 32K and take full advantage of the cache Note Break the data into chunks and call each routine multiple times Make sure to keep the sum between calls as well as the pointer to the data 5 8 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x Chapter 6 Using Advanced Debug 6 1 Purpose In the optimization exercise the number of cycles is non linear with the number of elements When the number of elements is 8K the code is much faster than if the number of elements is 16K Per element the numbers are normalized Recall that the data resides in L2 memory and that L1 D is configured as all cache The data is read from L2 memory and is put into the L1 cache for reusability The obvious explanation is that when the number of elements is 16K the cache is trashed during the first filter So the second filter has a cache miss The same is true for the third filter and the fourth The elements in the optimization exercise are floating point complex single precision numbers So each element requires 8 bytes Single precision is 32 bits equal to 4 bytes and floating point complex doubles the number of bytes to 8 In this exercise you will use the debug features in Code Composer Studio CCS to better understand the cache
64. ject Then in the Project Explorer view right click on the newly created optimization project and click on Add Files Browse to the project directory you created for this exercise and select all required files as outlined at the beginning of this exercise then click Open 5 2 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x Doc ID 122222 10 11 12 13 5 3 Instructions Chapter 5 Optimization When prompted how files should be imported into the project leave it as default of Copy File Remove the main c file that is created by default when you created the new project Examine the code in firMain c to understand the functions that are being called The generateData function generates the data sets to be operated on Functions naturalCFilters and intrinsicCfilters execute filters on the generated data The former is implemented completely in C while the latter takes advantage of compiler intrinsics Set the properties for the Debug configuration Right click on the project Select Properties 11a Choose Build click on the Environment tab and click the Add button to add the path to add a variable with Name as PDK ROOT and Value as C ti mcsdk pdk_C6678_1_1_2_5 11b Choose C6000 Compiler gt Optimization and set verify the following properties e Optimization level 0 e Optimize for code size 0 11c Choose C6000 Compiler gt Debug Options an
65. k Export Bits ocre 7 11 Breakpoint Properties Example Configuration Complete 0 cece ccc ence ene e eee mene 7 12 Choosing the Trace Analyzer c eerte e EE Heb ERR E e RAD SNE NEEN NEUE eee aes 7 12 Trac Result ve IDEE e Nd xe 7 13 Trace Display Results Core Details 7 14 Trace Display Results Full Frame 7 15 CCS Project Properties Age dere NEE deen E SO ES RA BAUER Rus reo nus ER RUOTE Ie os 8 3 STM Hib Directory Structures NN Ae E A EEN AE Eun Ud 8 4 CES T rget Corifig rations A ERE ee UE RN ERE EUR Re ENT 8 5 CCS Debug Trace Configuration Show All Cores isses hehehe he hehehe 8 6 Non Debuggable Devices Not Connected sssssssssssssessssesee esee een ees hehe eene 8 6 Non Debuggable Devices Connected eee e hen hes see hehe ee 8 6 Enable Hardware Trace Anahyzer eese hehehe hs hes sehe eee ne 8 7 Hardware Trace Analysis Configuration ocooooccoccconccnonnnnccnc hehe e heh he hs hene 8 8 Trace Viewer CSSTM La de NEE cepe NEE ood ria ege mede du esi ode eia E UY Cels e Ears elis 8 8 TMS320TCI66x Keystone Multicore Workshop Lab Manual BookID SPRP820 A Product Release MCSDK 2 x List of Procedures List of Procedures Procedure 1 1 Created New Target in CCS uer erre UE e rr er De TREE ge A ERREUR ZA reeL EEN enemas 1 2 Procedure 2 1 Import the Example Project ocio e ebbe LIEST RN EIE TQUE Weep eee SUR NE TENE 2 1 Procedure 2 2 Verify and Set Project Properties oo
66. k XDS560v2 USB System Trace Emulator 0 C66xx 7 Disconnected Unknown Unknown Unknown Unknown Unknown Unknown Unknown DI Registers Dir Variables 9o Break Identity Name ne os Y 2 intrinsicCFilter Breakpoint P test h _c_int000 at tmp TI_MKLIBIwBz81 SRC boot c 87 0xc006720 firMain c L i intrinsicCFilters c 23 35 36 37 total sum _hif2 sum _hif2 sum _lof2 sum _lof2 sum 38 output total_sum 39 48 41 End of filter 1 42 43 44 45 Second filter coefficients are 1 4 1 4 1 2 1 2 1 4 1 4 1 2 1 2 46 hs d 22 47 in float2 t inputComplex as filter size 4 49 B se x ftof2 0 25 25 51 x 1 _ftof2 5 5 52 xf2 ftof2 0 25 0 25 4 L El Console 32 Memory Map BB Table EB Table D Cache evm6678Trace coxml CIO natural C code size 4096 time 481057 End of Procedure 6 1 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x 6 3 6 2 Instructions Chapter 6 Using Advanced Debug Procedure 6 2 Doc ID 122222 Looking at the Cache Lines for 4K Case Step Action 1 Left clickon the View tab in the Debug perspective In the pull down menu choose Other Anew window will open as shown in Figure 6 2 Figure 6 2 CCS Debug Show View CCS Debug optimizi
67. kkkkkkkkkkkkkkkkkkkkkkkkkkk C66xx 0 DIO Socket Example with Interrupts Core 0 C66xx 0 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk C66xx 0 Debug Core 0 Starting the DIO Data Transfer Src 0 0x 1081b100 Dst 0 0x 1081b200 C66xx 0 Debug Core 0 Starting the DIO Data Transfer Src 8 0x 1081c100 Dst 8 0x 1081c200 C66xx 0 Debug Core 0 DIO Socket 0 Send for iteration 0 C66xx 0 Debug Core 0 ISR Count 10 C66xx 0 Debug Core 0 DIO Socket 1 Send for iteration 0 C66xx 0 Debug Core 0 ISR Count 11 C66xx 0 Debug Core 0 DIO Socket 2 Send for iteration 0 C66xx 0 Debug Core 0 ISR Count 12 C66xx 0 Debug Core 0 DIO Socket 0 Send for iteration 2 C66xx 0 Debug Core 0 ISR Count 16 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 2 7 Product Release MCSDK 2 x 2 2 Instructions Chapter 2 CCS Basics SRIO Loopback Doc ID 122222 C66xx 0 Debug Core 0 DIO Socket 1 Send for iteration 2 C66xx 0 Debug Core 0 ISR Count 17 C66xx 0 Debug Core 0 DIO Socket 2 Send for iteration 2 C66xx 0 Debug Core 0 ISR Count 18 C66xx 0 Debug Core 0 Transfer Completion without Errors 9 C66xx 0 Debug Core 0 Transfer Completion with Errors 0 C66xx_0 Debug Core 0 DIO Transfer Data Validated for all iterations C66xx 0 Debug Core 0 DIO Data Transfer READ with Interrupts Example Passed C66xx 0 Debug Core 0 Allocation
68. load the application to the target Core 0 Run the application by selecting the CCS menu option Run Resume The program attempts to send and receive tokens via the HyperLink interface in loopback mode So the same device acts as both the send and receive side A successful run should produce the following console output for each iteration C66xx 0 Checking statistics C66xx 0 About to pass 65536 tokens iteration 1 C66xx 0 this is not an optimized example C66xx 0 Link Speed is 4 6 25 Gbps C66xx 0 Passed 65536 tokens round trip read write through hyplnk in 9278 Mcycles C66xx 0 Approximately 141574 cycles per round trip C66xx 0 this is not an optimized example Multiple iterations are performed and the program will go on indefinitely until manually stopped Once you have verified that the program has executed successfully select the CCS menu option Run Suspend End of Procedure 3 6 34 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x Doc ID 122222 3 2 Instructions Chapter 3 HyperLink Communication Procedure 3 7 Board to board HyperLink Step Action A second C66x EVM is required perform this portion of the lab You will need a HyperLink cable and optional a 2 EVM breakout card 1 Modify the example code for hyplnk exampleProject so it can be run on two EVMs 1a 1b 1c 1d Open hyplnkLLDCfg h Search for define hyplnk EXAMPLE
69. me as PDK ROOT and Value as C ti mcsdk pdk_C6678_1_1_2_5 Note The path and platform may differ for your local devices 3b Select C6000 Compiler gt Optimization and set verify the following properties e Optimization level 3 3c Choose C6000 Compiler gt Debug Options and ensure that e Debugging model Suppress all symbolic debug generation 3d Choose C6000 Compiler gt Include Options Under the Add dir to include search path add the following two paths e S PDK ROOTJ packages ti csl e S PDK_ROOTYpackages Note This ensures that any include references in the project s source files to header files located at these paths will be interpreted accurately Click the OK button to save the project properties and close the Properties window 5 Right click on the project and select Build Project A successful build will generate the following output on the console Linking Finished building target optimization out Build Finished 5 4 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x Doc ID 122222 5 3 Instructions Chapter 5 Optimization 6 Enable the Clock by selecting the CCS menu option Run gt Clock gt Enable if you have done in the previous section of this lab you can ignore this step 7 Select Core 0 and load the out file created earlier in the lab 7a 7b 7c 7d Select the CCS menu option Run Load Load Program Click Br
70. nd Contact Information 9 ii Notices and reet ORE MERE OR n E ule Conteh VENE EV IEEE iii Release History sedet pee pute nee Davalos tot obit ea She Duchess et eres tre Perte ue e Cnt Ek ee es aia Cels iv Preface ase V EER SS A Saa GV Aboutthis DOCU sie RENE Eed SIE EEN US TES SERIE ETUR GV About the DOCUMENT RE Ae cau ENEE TEEN Raney ah bans aa NEE Neben e EREX EE dagen GV Texas Instruments Silicon and Telogy Software Documents GV Document Conventions ANN ERS te PA Se EEN ESA AE Eeer e e e SEENEN e g v Listof Tables ues decla ondas M cR E VER INE PETI chu DI XCUM CA MEE Voce ee ix LICEU PE GX Uer 9 xi Preparations 1 1 A eoe Core epe eue pec eee pU gu D VPE De rie eae a 1 1 PA EE 1 1 T3 EVM Configuration 24 or e pias ativan etuer Aaa Pda peiores ud Par eat Pues ver 1 1 CCS Basics SRIO Loopback 2 1 2 PUL le ET 2 1 KN e IECH 2 1 HyperLink Communication 3 1 351 PURPOSES reu et retento rs ences eite e vi itu cag wanes cael aa wala saan sana ie etre 3 1 3 2 In Str CtlOns cus ceder hte n er eae Sod ea edi Un e Di oie Y ERA Cien en des 3 1 SRIO Type 11 4 1 Al Purposes oz vet eret exte ves Dele Me Vati dou ne tue See V Ere d EHE Ee geet 4 1 AD Project Files ose A ERU ERS 4 1 A le de die LEE EE EE 4 1 Optimization 5 1 5 1 PULP OSE e e edet le misce e ulis esl um Ve ped ee s V eut EE 5 1 5 2 Project Elles seu IRA EE uS cg VER Ie eu TERRE iam RAE RES 5 1 5 3 IDStrUCtlOFis mios he
71. ompiler gt Debug Options and set verify the following properties e Debugging model Full symbolic debug 13d Choose C6000 Compiler gt Include Options Under the Add dir to include search path add the following two paths e S STM_ROOT src e S STM ROOTJ include Note This ensures that any include references in the project s source files to header files located at these paths will be interpreted accurately 14 Inthe linker tab open file search path 15 Addthefollowing path STM_ROOT lib to the search path and the library stm c66xx elf lib to the library list 16 Clickthe OK button to save the project properties and close the Properties window 8 4 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x 8 3 Instructions Doc ID 122222 Chapter 8 STM Library and System Trace 17 Right click on the project and select Build Project A successful build will generate the following output on the console Linking Finished building target out Build Finished End of Procedure 8 1 Procedure 8 2 Connect to the EVM Step Action 1 Click the Open Perspective available right top corner of the CCS 2 Switchtothe Debug Perspective by selecting the CCS menu option Window Open Perspective CCS Debug 3 Selectthe CCS menu option View Target Configurations as shown in Figure 8 3 Figure 8 3 CCS Target Configurations ICES Debug CORE CO File Edit
72. onclusion The same logical addresses 0x9000 0000 and on have a different physical address for each core End of Procedure 7 1 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 7 5 Product Release MCSDK 2 x 73 Instructions Chapter 7 Using MPAX to Define Private Core Memory in DDR Doc ID 122222 7 3 1 Using Trace to Verify the Write Physical Address The next section describes how to use the trace facility to verify that each core actually writes to a different physical address Procedure 7 2 Connect to the Non debuggable Devices Esp CCTMS_0 Step Action 1 Afterlaunching the target right click on the upper line in the debug window for example evm6678Trace ccsml and choose show all cores 2 Goto non debuggable devices the bottom of the window right click and connect to target 3 Connect all the cores as well A Thedebug window should appear as shown in Figure 7 1 Figure 7 1 CCS Debug MPAX Utilities bu MP AXT I utilit File Edit View Project Tools Run Scripts Window Help ri Oi ty Ea 5bpe be mm oo e lp 0 a ED evm6678Trace ccxml Code Composer Studio Device Debugging 4 Ki Group 1 a gi Blackhawk XDS560v2 USB System Trace Emulator_0 C66xx_0 Suspended 0x20B01130 no symbols are defined for 0x20B01130 4 gf Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 1 Suspended 0x20B002A8 no symbols are defined for 0x20B002A8 a gf Blackhawk XDS560v2 USB System Trace Emula
73. one Multicore Workshop Lab Manual BooklD SPRP820 A 7 1 Product Release MCSDK 2 x 7 2 Overview Chapter 7 Using MPAX to Define Private Core Memory in DDR Doc ID 122222 7 2 Overview 7 2 1 Short Description of MPAX Memory Protection and Extension The C66x CorePac User s Guide Chapter 7 3 describes the MPAX unit The MPAX registers are used to translate a logical address 32 bit address into a physical address 36 bit address In this example translation registers are used to assign the different physical address of each core to the same logical address This that the same code will load the same structures to different physical locations for each core The MPAX registers manipulations used to achieve the different translation will be done in the main function The initialization of pre initialized global variables for example a declaration of global variable int x 6 is done before the start of main Thus pre initialized global variables are not allowed in the DDR private memory Note There may be way to configure the MPAX registers during boot but this exercise does not consider it 7 2 2 Coherency Discussion For cases where L1D is configured as a cache there is hardware coherency between L2 data and L1 D inside the C66x CorePac The hardware coherency guarantees that a variable that is defined in L2 and is cache by L1D has the same value in both places This guarantee does not hold true with private memory
74. ooooocooccccnccncnccnrnnc ee hehe he e hehehe eee 2 2 Procedure 2 3 Build the Project e RR ERR deb a EN De URNA S YR a oe E ide 2 3 Procedure 2 4 Corinectto the Target EVM 24 e Hee pee eR aor Ehre eR Eat det RF tU EUUSRR E E deelt e ENEE 2 4 Procedure 2 5 Load AMA Run the Program or ee d ee ore eer RU NEN NAT Cae SIR eee eee ERES ML 2 6 Procedure 3 1 Importthe Example Project eie de bias A EE Rhe aha M EE Ep 3 2 Procedure 3 2 Verify and Set Project Properties cece cece cece nee ee hehe heh hehe sene 3 2 Procedure 3 3 Loopback Mode visarna er p e RRRRx TE apeheagees URB TAS EN NL I ERA EEN 3 3 Procedure 3 4 Build the Project oe ee dev p rU ETC EX RE EEN UP E AR e ULL bere nud ge REESE 3 3 Procedure 3 5 Connecttothe EV Mio RR chic abs semen tienes A ERR EE ERE RES 3 4 Procedure 3 6 Load and Run th Progtarri A a edu ehe ees 3 4 Procedure 3 7 Board to board HyperLink dg Ne erret at Eee be plein tie sees her DOO Eiere tea BARTS UNIS 3 5 Procedure 4 1 Import the Project o vos vei EE EET A A AT SV DUE VI FERE UH RAE LEN 4 2 Procedure 4 2 Build the Project iiu ei E bebo chee EE 4 2 Procedure 4 3 Corinectto the EVM eoe wi ds ERU te d Saee ente a Y NS CU Ne a nal dg a E EROR SUE P E 4 3 Procedure 4 4 Load arid RUM silose erred Gout ne rr ee ies Ghee hed Moca RN IARE RE Gadde np RE E ER RESP EROS 4 4 Procedure 5 1 Build and Run the Project Lois AA en Ln ie de BE EN 5 2 Procedure 5 2 Connect to the E Mii a EEN EEN EA EEN EE s eR Sid
75. or this example are as follows e Bit 29 Expected to be always 0 e Bit 28 Expected to be always 1 e Bits 27 to 24 Expected to be the core number e Bits 23 to 20 Expected to be all zeros Click on Export Bits In the pull down menu see Figure 7 6 choose 29 20 Figure 7 6 Breakpoint Properties Address Mask Export Bits V Properties for pS Breakpoint Properties amp Breakpoint Properties Gs Properties Values 4 Transaction Type CPU Data Access iv true CPU Instruction Ac false DMA Access false Access Type Any 4 Export Configuration Export Access Status true Export New Request E iv true Export Last Burst Event false Address Mask Export Bits 29 20 4 Address Range Filter Export Bits 26 17 Start Location Export Bits 2718 Address Extension Export tts 20 19 End Location Export Bits 30 21 Exclusive Address Export Bits 31 22 EMU Trigger Filter Export Bits 32 23 4 Miscellaneous Export Bits 33 24 Export Bits 34 25 Export Bits 35 26 E Set the 10 bit of the address associated with Export Bits 36 27 Export Bits 37 28 Export Bits 38 29 Export Bits 39 30 Export Bits 40 31 Export Bits 41 32 Export Bits 42 33 Export Bits 43 34 TT Export Bits 44 35 3 Duration Summary ALL D Cache ca Kee A porum Export Bits 47 39 X TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 7 11 Product Release MCSDK 2 x 73 Instructions Chapter 7 Using MPAX to Define Private Core Memory in DDR Doc I
76. owse project Select optimization out by unwrapping the OptimizationRelease and click OK Click OK to load the application to the target Core 0 8 Runthe application by selecting the CCS menu option Run Resume 9 Asuccessful run should produce a console output as shown below Record the optimized cycle times for both natural C and intrinsic C versions C66xx 0 C66xx 0 C66xx 0 C66xx 0 C66xx 0 C66xx 0 natural C code size 32768 time 228698 intrinsic C code size 32768 time 1282213 no error was found DONE End of Procedure 5 4 QUESTIONS How much improvement is noted for the natural C code How much improvement is noted for the intrinsic code What issues exist within the code if any Note Consider how intrinsic functions utilize the processor TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x 5 5 5 3 Instructions Chapter 5 Optimization Doc ID 122222 Procedure 5 5 Enable Software Pipelining Step Action 1 In the CCS Project Explorer go to Build gt C6000 Compiler gt Advanced Options gt Assembler Options and check the box that says Keep the generated assembly language asm file 2 Rebuild the code 3 The generated assembly file will be located within the Release directory since you are building the project s release configuration QUESTIONS Open the intrinsicCFilter asm file and answer the following questions
77. pop up will appear with a default workspace Replace the default workspace with C ti workspace Once CCS starts verify that the perspective is set to CCS Edit Discover the new packages installed in folders other than CH 3a 3b 3c 3d 3e Select the CCS menu option Window Preferences In the pop up window that appears select Code Composer Studio gt RTSC gt Products Add the master folder into Tool Discover Path by clicking the Add in the upper right corner of the pop up window and select the master folder For example select CXiNMCSDK 2 1 2 6to add in the Tool Discovery Path Click Refresh to update the discovered tools list TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 2 1 Product Release MCSDK 2 x 2 2 Instructions Chapter 2 CCS Basics SRIO Loopback Doc ID 122222 A Importthe example project as follows Aa Select the CCS menu option Project gt Import Existing CCS Eclipse Project 4b Set Select search directory to locate the example projects available for your EVM e C6657L LE C ti mcsdk pdk_C6657_1_1_2_5 packages ti drv exampleProjects e C6678L LE C ti mcsdk pdk_C6678_1_1_2_5 packages ti drv exampleProjects 4c From the list of Discovered projects place a check mark in the box next to SRIO LoopbackDiolsrexampleproject Note There are multiple SRIO projects with similar names Verify that the project you import matches exactly with the name as shown above
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80. rget You notice that all devices are connected as shown in Figure 8 6 Figure 8 6 Non Debuggable Devices Connected 4 2 Non Debuggable Devices Blackhawk XDS560v2 USB System Trace Emulator_0 IcePick_D Blackhawk XDS560v2 USB System Trace Emulator_0 CS_DAP_DebugSS Blackhawk XDS560v2 USB System Trace Emulator_0 CSSTM_O Blackhawk XDS560v2 USB System Trace Emulator_0 TETB_STM 8 6 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x Doc ID 122222 8 3 Instructions Chapter 8 STM Library and System Trace 5 Next enable the Hardware Trace Analyzer as shown in Figure 8 7 Note These operations are different in CCSV5 3 The screen shots in this example are from CCSv5 4 Figure 8 7 Enable Hardware Trace Analyzer Memory Map zl GEL Files en Debugger Options ble Pin Connect Port Connect Save Memory Load Memory Fill Memory RTOS Object View ROV RTOS Analyzer System Analyzer d Hardware Trace Analyzer Graph gt Image Analyzer RE FR FR FR Es Profile XDAIS Tools D RTSC Tools runtime Log h deum Mia ke Suspended SW Breakpoint 1 Disconnected Unknown uu 2 Disconnected Unknown Disconnected Unknown 4 Disconnected Unknown Function Profiling Not applicable on selected CPUs Stall Profiling Not applicable on selected CPUs Cache Analysis Not applicable on selected
81. rpose vos ecu eed te eu eta re m rer dite ete ee decere ete Re doe ete aren Mater ed 8 1 8 2 Project Files eres e tette veloce nee E E Kee ee ex Pe dU DR px pese val ee 8 1 8 3 Instructions S oe tege talea etes id AA posa wane dete 8 2 REVISION History Nd rete dE Verb ep EPI A ra eve Vale eet alere ENEE Par nes pire Rd P OR eS 9 9 TMS320TCI66x Keystone Multicore Workshop Lab Manual BookID SPRP820 A Product Release MCSDK 2 x List of Tables List of Tables Table 1 1 No Boot Dipswitch Bettingen rotor ree nt RS EOS a RARE pas RC deed E ERE SEHE U A e sehen ees 1 2 Table 1 2 EVM Emulator Types ne EEN b Ar pu RC LEY V AEN ed dae Ru Ee Sie ad eee ERE d dieu Res e 1 2 Table 5 1 Clock Val es amp Cycle Counts sax uses dE E tis alone E E bd Re eR EE EEN eege 5 8 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A GIN Product Release MCSDK 2 x List of Figures List of Figures Figure 2 1 Figure 2 2 Figure 2 3 Figure 3 1 Figure 4 1 Figure 4 2 Figure 4 3 Figure 5 1 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure 6 6 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 Figure 7 5 Figure 7 6 Figure 7 7 Figure 7 8 Figure 7 9 Figure 7 10 Figure 7 11 Figure 8 1 Figure 8 2 Figure 8 3 Figure 8 4 Figure 8 5 Figure 8 6 Figure 8 7 Figure 8 8 Figure 8 9 C6000 Compiler Include Options 7 4 2 ENEE ENEE hme eee ey KENE E E MER ded HIER EN eI RS Mos palma d de 2 3 Launch Target Configuration
82. size 64 output 80001800 real 80007400 imag 80005400 C66xx 2 fft size 64 output 80002000 real 80007800 imag 80005800 C66xx 3 fft size 128 output 80002800 real 80007c00 imag 80005c00 C66xx 1 fft size 32 output 80001800 real 80007400 imag 80005400 C66xx 2 fft size 256 output 80002000 real 80007800 imag 80005800 C66xx 1 fft size 256 output C66xx 3 fft size 128 output C66xx 4 fft size 256 output C66xx 5 fft size 512 output C66xx 3 fft size 512 output C66xx 2 fft size 128 output 80001800 80002800 80003000 80003500 80002800 800020008 real 80007400 real 80007c80 real 80008000 real 80008400 real 80007c 0 real 80007800 imag 80005400 imag 800 5c 0 imag 80006000 imag 80006400 imag 800 5c imag 80005800 C66xx 1 fft size 64 output 80001800 real 80007400 imag 80005400 C66xx 6 fft size 32 output 80004000 real 80008800 imag 80006800 C66xx 1 fft size 32 output 80001800 real 80007400 imag 80005400 C66xx 2 fft size 64 output 80002000 real 80007800 imag 80005800 C66xx 1 fft size 128 output 80001800 real 80007400 imag 80005400 C66xx 4 fft size 128 output 80003000 real 80008000 imag 80006000 C66xx 2 fft size 128 output 80002000 real 80007800 imag 80005800 C66xx 1 fft size 32 output 80001800 real 80007400 imag 80005400 C66xx 3 fft size 256 output 80002800 real 80007c00 imag 80005co0 C66xx 1 fft size 512 output 80001800 real 80007400 imag 80005400 C66xx 2 fft size 64 output 80002000 real 80007800 imag
83. ss XID Ov Addr 0 210 DOR New Request GE 5 37124 9 128 CPTracer CPT New Request Masters GEMI Write Access A D Addrs O10 DDR New RequestGE 5 325 H 18 CPTracer CPT New Request Masterz GEM Write Access XIDz 0f Addrz 01110 DOR New Request GE 4 371249 0 128 CPTracer CPT New Request Masters GEMI Write Access XID Q7 Addr 0x 10 DDR New Request GE 5 ams 0 18 CPTracer CPT New Request Master G MI Write Access XIDz 098 Addr 0x110 oR New Request GE 5 1255 H 128 CP Tracer CPT New Request Master GEMI Write Access XID iS Addratxll0 DDR New Request GE 5 3071264 0 128 CPT racer CPT New Request Maier D M Write Accent XIDzOxa Addr 0x110 Dos New Request G 4 71 268 0 18 CPTracer CPT New Request Master GEM Write Access XID 0xb Addr 0 110 DOR New Request GE 5 30012773 H 128 CPT racer CPT New Request Marter G MI Write Access XID 0xc Addr 0x3 10 Dos New Request GE 5 39071278 0 128 CPTracer CPT New Request Master GEMI Wree Access XID Ovdt Addr Qd10 Dos New RequestGE 6 371284 H 128 CPTracer CPT New Request Masters GEMI Write Access ID One Addrs O10 DDR New RequestGE 3 3071287 H M8 CPT racer CPT New Request Masterz GEMI Witte Access Sieft Addr 0 110 DOR New Request GE 5 301292 H 128 CPTracer CPT New Request Masters GEMI Write Access XID 049 Addr 0xd 10 DDR New Request GE 6 mne 0 18 CPT racer CPT New Request Masterz GEMI Write Access XIDz 0x1 Addr 0 110 oR New Request GE 5 3071303 H 128 CPT racer CPT New Request Master GEM
84. strates the HyperLink connection between two C66x EVMs As a result this lab requires a second C66x EVM a HyperLink cable HL5CABLE and an optional EVM breakout card CIZEVMBOC One C66xx EVM acts as the sender Tx and the other acts as the receiver Rx The list of processes used in this example are as follows e Procedure 3 1 Import the Example Project e Procedure 3 2 Verify and Set Project Properties e Procedure 3 3 Loopback Mode e Procedure 3 4 Build the Project e Procedure 3 5 Connect to the EVM e Procedure 3 6 Load and Run the Program e Procedure 3 7 Board to board HyperLink TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 3 1 Product Release MCSDK 2 x 3 2 Instructions Chapter 3 HyperLink Communication Doc ID 122222 Procedure 3 1 Import the Example Project Step Action 1 Move to the CCS Edit Perspective 2 Importthe example project as follows 2a Select the CCS menu option Project Import Existing CCS Eclipse Project 2b Set Select search directory to locate the example projects available for your EVM e C6657L LE C ti mcsdk pdk_C6657_1_1_2_5 packages ti drv exampleProjects e C6678L LE C ti mcsdk pdk_C6678_1_1_2_5 packages ti drv exampleProjects 2c From the list of Discovered projects place a check mark in the box next to hyplnk exampleProject 2d Place a check mark on Copy projects into workspace 2e Clickthe Finish button 2f The hypink_example
85. te a new CCS Project KE Project name Donn Use default location Location C Users 20270985 WorkSpaces temp Browse Device Family C6000 zj Variant lt select or type filter text gt v Generic C66xx Device M Connection v Advanced settings Project templates and examples type filter text Creates an empty project fully initialized SS Tor the selected device 4 E Empty Projects Le Empty Project with main c Le Empty Assembly only Project Le Empty RTSC Project 4 E Basic Examples Le Hello World b E IPC and I O Examples d ES m lt Back Next gt Finish 7 Press Finish to create the new project 8 Inthe Project Explorer view right click on the newly created stm example project and click on Add Files 9 Browseto C ti labs code STM select all the files in this directory and click Open When prompted how files should be imported into the project leave it as default of Copy File 10 Ifafile main c was generated when you created the new project remove the main c file 11 Examine the code in StmMain c to understand the code TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 8 3 Product Release MCSDK 2 x 8 3 Instructions Chapter 8 STM Library and System Trace Doc ID 122222 12 Location of the STM library e The STM library is part of MCSDK 3 release If you have not installed MCSDK 3
86. tion Priority Level 3 P3 Your network performance is degraded Network functionality is noticeably impaired but most business operations continue Priority Level 2 P2 Your production network is severely degraded affecting significant aspects of business operations No workaround is available Priority Level 1 P1 Your production network is down and a critical impact to business operations will occur if service is not restored quickly No workaround is available TMS320TCI66x Keystone Multicore Workshop Lab Manual BookID SPRP820 A Product Release MCSDK 2 x Notices and Trademarks Notices and Trademarks Important Notice Texas Instruments Incorporated reserves the right to make changes to its products or discontinue any product or service without notice and to advise customers to obtain the latest version of relevant information to verify before placing orders that the information being relied upon is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability Customers are responsible for their applications using Texas Instruments Software Notice of Proprietary Information Information contained herein is subject to the terms of the Non disclosure Agreement between Texas Instruments Incorporated and your company and is of a highly sensitive na
87. tor 0 C66xx 2 Suspended 0x20B002A8 no symbols are defined for 0x20B002A8 4 gi Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 3 Suspended 0x20B002A8 no symbols are defined for 0x20B002A8 4 gf Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 4 Suspended 0x20B002A8 no symbols are defined for 0x20B002A8 4 gf Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 5 Suspended 020800248 no symbols are defined for 0x20B002A8 a g Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 6 Suspended 0x20B002A8 no symbols are defined for 0x20B002A8 a gf Blackhawk XDS560v2 USB System Trace Emulator 0 C66xx 7 Suspended 0x20B002A8 no symbols are defined for 0x20B002A8 4 Non Debuggable Devices Blackhawk XDS560v2 USB System Trace Emulator_0 IcePick_D Blackhawk XDS560v2 USB System Trace Emulator_0 CS_DAP_DebugSS Blackhawk XDS560v2 USB System Trace Emulator 0 CSSTM 0 9 Blackhawk XDS560v2 USB System Trace Emulator_0 TETB_STM End of Procedure 7 2 7 6 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x Doc ID 122222 7 3 Instructions Chapter 7 Using MPAX to Define Private Core Memory in DDR Procedure 7 3 Load the Code to the 8 Cores Step Action 1 To make the results easier change the number of elements Line 171 in test MPAX1 c to 10 2 Build the project again and load it o the 8 cores End of Procedure 7 3 Procedure 7
88. tput 80003000 real 80008000 imag 80006000 C66xx 2 fft size 128 output 80002000 real 80007800 imag 80005800 C66xx 1 fft size 32 output 80001800 real 80007400 imag 80005400 C66xx 3 fft size 256 output 80002800 real 80007c00 imag 80005c00 C66xx 1 fft size 512 output 80001800 real 80007400 imag 80005400 C66xx 2 fft size 64 output 80002000 real 80007800 imag 80005800 C66xx 4 fft size 32 output 80003000 real 80008000 imag 80006000 C66xx 5 fft size 128 output 80003800 real 80008400 imag 80006400 define TMS320C6600 diag warning 225 abi eabi z m SRIOSingleSRIO map warn sections i C ti ccs ccsv5 tools compiler c6000 lib ti ccs dsplib c66x 3 0 0 8 lib i C ti ccs ccsv5 tools compiler c6000 include reread libs rom model o SRIOSingleSRIO out l configPkg linker cmd srio drv obj slaveTask obj requestProcessingData obj qmss drv obj qmss device obj multicoreLoopback osal obj masterTask obj initialization obj gen twiddle fft16x16 obj Lig subair rures mk T fftRoutines obj z device srio loopback obj Anu Se res Ee ec examples cd mom a ne Licensed SRIOSingleSRIO Debug SRIOSingleSRIO out End of Procedure 4 3 Procedure 4 4 Load and Run Step Action 1 Select Group1 and connect all cores in the group 1a From the CCS Run menu select Connect Target OR 1b Right click on the group name and choose Connect Target OR 1c Click the Connect Target icon
89. tudio Device Debugging H v2 E a 3B Group A if Blackhawk XD556072 USB System Trace Emulator 0 C tm D Suspended ert at MABX uiiitses c 22 0400801840 E un at testMPAXI lt 178 0400801894 08000 at boct c173 0 00805BC4 the entry post was reached sP hawk XD5360 2 USB System Trace Emulator 0 C x 1 Suspended ent at MAPX utiites c22 000801820 INO at testMP AD 178 000801894 mg at boct c173 Q 00805BC4 the entry poirt was reached a aP Blackhawk XD55602 US8 System Trace Emulator Afen Suspended er at MAN utilities c22 000801845 vin at test MPA c 178 0400801894 t at boct c173 Q400805DCA the entry point was reached P Blackhawk XD 560 2 USB System Trace Emulator 0 C ba 3 Suspended EEN D enfant 7 D Memory Browser I Trace Display Blackhawk XDSS60v2 USB System Trace Emulator Q CSSTM 0 12 0 T a n Fd a B Showing 162 Samples all data Stopped by user upload complete Receiver Clock 87 5 MHz Trace Data Rate 2000145875 7 apaxl sr 1 lt Fa gt 53 sun mi pro cer cto emu 25 Delta Time Time Function Start MasterID Master Mame Channel Number Module Data Message n spaxl rAddr xx 5 0 o 132 3 3 DH 18 CPTracer CPT New Request Mas 1 5 8 o 128 CPTrecer CPT New Request Mas 134 CSL ME seOXPAXL index lapax beienee nae 5 n O 123 Pime CPT New Request Mar 1 6 19 o 128 CPTracer CPT New Request Mas 1 Disable the Cache de 5 a o 128 CPTracer CPT New Requ
90. ture and is confidential and proprietary to Texas Instruments Incorporated It shall not be distributed reproduced or disclosed orally or in written form in whole or in part to any party other than the direct recipients without the express written consent of Texas Instruments Incorporated Telogy Software VLYNQ PIQUA Software wONE PBCC Uni DSL Dynamic Adaptive Equalization Telinnovation TurboDSL Packet Accelerator interOps Test Labs TurboDOX and INCA are trademarks of Texas Instruments Incorporated All other brand names and trademarks mentioned in this document are the property of Texas Instruments Incorporated or their respective owners as applicable TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 9 iii Product Release MCSDK 2 x Release History Release History Release Date Chapter Topic Description Comments SPRP820 April 2014 All Initial release iv TMS320TCI66x Keystone Multicore Workshop Lab Manual BookID SPRP820 A Product Release MCSDK 2 x Preface About this Document This document is part of a document set prepared in support of the Texas Instruments Telogy Software TNETVxxxx x x product release About the Document Set Various books in the document set will be of interest to developers of voice over packet products according to their role e Project Managers e Hardware Engineers e Software Engineers e Test Engineers e Application Developers Tex
91. ubdir vars mk Bt ume ExampleSRIO cmd n Licensed SRIOSingleSRIO Debug SRIOSingleSRIO out End of Procedure 4 2 Procedure 4 3 Connect to the EVM Step Action 1 Cycle power on the EVM 2 Clickthe Open Perspective available right top corner of the CCS 3 Switch to the Debug Perspective by selecting the CCS menu option Window gt Open Perspective gt CCS Debug Use the target configuration that you created previously 5 Launch the target configuration as follows 5a Select the target configuration ccxml file 5b Right click and select Launch Selected Configuration This brings up the Debug window 7 Selectall cores right click and group them by selecting Group Core s as shown in Figure 4 2 The default name will be Group 1 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x 4 3 4 3 Instructions Chapter 4 SRIO Type 11 Doc ID 122222 Figure 4 2 CCS Debug Select and Group Cores ER r Stu File Edit View Search Project Tools Run Scripts Window Help n S8 DObe i0ikk 9 39 ES S CCS Debug ES CCS Edit X amp o mmi SS e Hy amp da Y 7 D eos Variables 53 4 Expressions D I Registers std Name Type Value Blackhawk XDS560v2 USB Mezzanine Emulator 0 C66xx 0 Disconnected Blackhawk XDS560v2 USB Mezzanine Emulator 0 C66xx 1 Disconnected Blackhawk XDS5
92. urere a rre Rea acp AD EE Rn tee T e REI up Le M n Rye dea a ate d 5 1 5 33 Cache Analysis 25 S vez tat Eu opto epe de kaka et e eod ur tee Ur nee RET RAG e ete die 5 8 5 3 2 Change the Code to Speed Upto k e eee hehe 5 8 Using Advanced Debug 6 1 6 1 Purpose A e Ree deemed ee eer dee 6 1 6 1 1 Why the Debug Version is Used 0 0 ccc cee cece ener n eee n ene ee ete hes he e hehehe 6 1 6 2 Instr ctioris uu cue ceo het tete ET aN ah e med le i andar E Ae e UNA Net 6 2 vii TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x Contents Chapter 7 Chapter 8 viii Using MPAX to Define Private Core Memory in DDR 7 1 SR d ig ele ve eie A P PAS E UT EN EHE E E A R EE d DR e 7 1 AZ OVE EW ccs ev m eH E CHER ER RE RR ERE US Ke A ERE RERUM et E RR 7 2 7 2 1 Short Description of MPAX Memory Protection and Extension 7 2 722 Coherency Discussion ees cs bois m here Er RA Ere reine I UE RE ER DEE EE E EET ees 7 2 7 2 3 Usage of EDMA to Move Data to and from Private Memory 0 cece eee e eee mene 7 2 7 2 4 Platform Configuration and the Memory Map 7 3 72 5 MAR RODIN er eei rua Nea E COE hr HE RN EE ENEE 7 4 VIAS TUCASA e eR qr epe ere ENEE 7 5 7 3 1 Using Trace to Verify the Write Physical Address 7 6 7 3 2 Additional Considerations ey RARE UN ER PIU VO nee NE M Rene EXE Ue A LE E Uda head melee step eua 7 15 STM Library and System Trace 8 1 8 1 Pu
93. wn in Figure 8 9 Figure 8 9 Trace Viewer CSSTM O EB Trace Viewer CSSTM 0 El Stopped by buffer full upload complete vm E Time Micro Secs Master Name Data Message Data Class 1 0 0 0000 2 2 0 0229 C66X_0 ivalue 2 Target function PutMSG 3 271 3 0971 C66X 0 al 34432 86 Target function PutMSG 4 422 4 8229 C66X 0 a3 258 Target function PutMSG 5 546 6 2400 C66X 0 End a IF changes Target function PutMSG 6 752 8 5943 C66X 0 DONE number 0 Target function PutMSG 7 922 10 5371 C66X_0 i value 4 Target function PutMSG 8 1188 13 5771 C66X 0 al 144 a2 36 Target function PutMSG 9 1337 15 2800 C66X 0 a3 108 Target function PutMSG 10 1461 16 6971 C66X 0 End a IF changes Target function PutMSG 11 1673 191200 C66X 0 DONE number 1 Target function PutMSG 12 1841 21 0400 C66X 0 ivalue 6 Target function PutMSG 13 2107 24 0800 C66X 0 al 184 a2 46 Target function PutMSG 14 2255 25 7714 C66X_0 a3 138 Target function PutMSG End of Procedure 8 4 8 8 TMS320TCI66x Keystone Multicore Workshop Lab Manual BookID SPRP820 A Product Release MCSDK 2 x Revision History Revision History TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A 9 9 Product Release MCSDK 2 x Revision History 9 10 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI
94. x 30 Lines L1D cache 0x008007C0 Ox008007FF 31 0 v E inputComplex 4 31 Lines L1D cache 0x00800800 0x0080083F 32 0 v inputComplex 32 Lines L1D cache 0x00800840 0x0080087F 33 0 v E inputComplex 4 33 Lines L1D cache 0x00800880 Ox008008BF 34 0 V E E inputComplex 34 Lines A Examine the first L1D line The address of the first L1D line is 0x0080 0000 which is the first line ofthe L2 memory and where the input vector resides Notice that the valid flag is set for this cache line 6 6 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x Doc ID 122222 6 2 Instructions Chapter 6 Using Advanced Debug 5 Next look at the last LTD cache line as shown in Figure 6 5 e The last line of the vector inputComples is line 255 with a starting address of 0x0080 3fCO e After this there are several DIRTY lines which indicate where the code changed some values e Remember that L1D cache line has 64 bytes 0x40 So the last byte of inputComplex in the cache is byte 0x00803fc0 0x40 1 0x00803fff This is the Line End address of line 255 Figure 6 5 CCS Debug IntrinsicCFilters L1D Cache Last Line 4K File Edit View Project Tools Run Scripts Window Help ri SG ty Dis B DO E Console Memory Map EB Table ec Cache Tag RAM Read complete 1536 Cache Lines read from target 33 after filtering Cache Line Start Adrs Line End Adrs Set Way Valid Dirty
95. yplnk exampleProject out Build Finished End of Procedure 3 4 TMS320TCI66x Keystone Multicore Workshop Lab Manual BookID SPRP820 A 3 3 Product Release MCSDK 2 x 3 2 Instructions Chapter 3 HyperLink Communication Doc ID 122222 QUESTIONS Was the file hypInk_exampleproject out generated Note From the CCS Edit perspective check the Binaries or Debug directory From the CCS Debug perspective check the Console Procedure 3 5 Connect to the EVM Step Action 1 Click the Open Perspective available right top corner of the CCS 2 Switch to the Debug Perspective by selecting the CCS menu option 3 Window gt Open Perspective gt CCS Debug 4 Selectthe CCS menu option View Target Configurations Select the target configuration you created 5 Launch the target configuration as follows 5a Select the target configuration ccxml file 5b Right click and select Launch Selected Configuration 6 This will bring up the Debug window 6a Select Core 0 C 6x 0 6b Right click and select Connect Target End of Procedure 3 5 Procedure 3 6 Load and Run the Program Step Action 1 Select Core 0 and load the out file created earlier in the lab A 5 1a Select the CCS menu option Run Load Load Program 1b Click Browse project 1c A pop up will appear with the projects names 1d Select hyplnk exampleProject le Click Debug then select hyplnk exampleProject out and click OK 1f Click OK to
96. ystone Multicore Workshop Lab Manual BooklD SPRP820 A 2 3 Product Release MCSDK 2 x 2 2 Instructions Chapter 2 CCS Basics SRIO Loopback Doc ID 122222 Procedure 2 4 Connect to the Target EVM Step Action 1 Click the Open Perspective available right top corner of the CCS 2 Switchtothe Debug Perspective by selecting the CCS menu option Window Open Perspective CCS Debug 3 Connect the power adapter to your EVM then connect your laptop to the emulator port on the EVM using the provided USB cable If you are using the XDS560v2 wait till the solid red light appears before proceeding to the next step Note The Windows Found New Hardware Wizard may pop up when you first connect the emulator via USB to the laptop Select Yes this time only gt Next gt Install the software automatically gt Next and allow the drivers to install on your system Then click Finish You may need to restart CCS at this point 4 Selectthe CCS menu option View Target Configurations Your newly created ccxml target configuration file should be available under User Defined target configurations 5 Ifmore than one target is configured select the target that you defined right click and set it as default 2 4 TMS320TCI66x Keystone Multicore Workshop Lab Manual BooklD SPRP820 A Product Release MCSDK 2 x 2 2 Instructions Doc ID 122222 Chapter 2 CCS Basics SRIO Loopback 6 Launch the target configuration as shown in Fi

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