Protocol adapter for passing diagnostic messages between a host
Contents
1. 14 FIG 3 is a schematic diagram of the 11708 trans ceiver circuit 50 and includes a voltage translator 68 and an input buffer 70 electrically interconnected as shown In one embodiment the voltage translator 68 is the model SN75176 well known to those skilled in the art Both the transceiver circuits 48 and 50 include transmit mailboxes for transmitting J1708 and J1939 messages to the networks 12 and receive mailboxes for receiving J1708 and 11939 messages from the networks 12 The protocol adapter 30 allows the user to customize each transmitted message The J1708 or J1939 message to be transmitted may include the relative time to the adapter timer when the message transmission is to begin the number of times the message is to be sent the desired time interval between transmissions the ID and data to be sent the conditions for a call back announcing a successful transmission the number of times the message should be sent before auto deletion occurs and whether to enable a call back announcing the time of message deletion The J1708 or J1939 message received may include which protocol to scan which bits should be masked by hardware level filtering which bits should be matched by hardware level filtering what information such as mailbox number time stamp identifier length of data etc should be sent to the host immediately upon receipt and how the appli cation will be notified when a message is received such as transparent up2. 28 2012 U S Patent 96 3M HSY i Jv U3dd ev _ US 8 255 587 B2 Sheet 7 of 9 Aug 28 2012 U S Patent H F e 19 ee UU Eee p Yd 04 N 09 199 10 1 1 U S Patent Aug 28 2012 Sheet 8 of 9 US 8 255 587 B2 WE Caco 2 aa FIG 8 110 lt xr O ON OD cc lt s ss ss E A gi 8 ex lt US 8 255 587 B2 Sheet 9 of 9 Aug 28 2012 U S Patent gt HY 86 bas 1008 gu NIS 19V US 8 255 587 B2 1 PROTOCOL ADAPTER FOR PASSING DIAGNOSTIC MESSAGES BETWEEN A HOST COMPUTER AND VEHICLE NETWORKS OPERATING IN J1939 OR J1708 PROTOCOL CROSS REFERENCE TO RELATED APPLICATIONS This application is a Continuation Application of U S Ser No 12 799 739 filed Apr 30 2010 which is a continuation of U S Ser No 12 002 427 filed Dec 17 2007 which is a Divisional Application of U S application Ser No 10 888 432 filed Jul 9 2004 which is a Continuation in Part Appli cation of U S application Ser No 09 532 718 filed Mar 22 2000 which claims the benefit of U S Provisional Patent Application Ser No 60 126 588 filed Mar 26 1999 BACKGROUND OF THE INV
3. be of any particular vehicle protocol including the J1708 protocol provided on line 20 and the 11939 protocol provide on line 22 According to the invention the protocol adapter 30 is com patible for both the 11708 protocol and the J1939 protocol The protocol adapter 30 provides a pass through interface so that various compliant applications from various develop ers can use any of the unique developer applications This allows all compliant software applications and hardware interface adapters to be interchangeable The protocol adapter 30 is capable of performing electronic control module ECM emulation analysis of network message loading simulation of message traffic loading of an in vehicle network inventory management ECM code testing a gateway between net works and vehicle maintenance status checks The protocol adapter 30 includes an I O sub assembly board 32 and a CPU sub assembly board 34 both of which will be described in detail below When the vehicle networks 12 use the 11708 protocol the protocol adapter 30 can operate ina pass through mode where the 11708 signals on the line 0 are passed through a voltage translator directly to an RS 232 transceiver in the I O board 32 With the J1708 protocol the protocol adapter 30 can also operate under the control of an embedded processor where the J1708 signals on the line 20 are passed through a voltage translator to be processed in the CPU board 34 and routed to an RS 232 tr
4. circuit 96 is used for communication of asyn chronous data to and from the programmable controller 14 The UART circuit 96 is used to convert parallel data from the CPU 100 to serial data to the host computer 14 and vice versa FIG 7 isa schematic diagram ofthe CPU 100 and includes a microprocessor 102 and two input output chips 104 and 106 electrically coupled as shown In this embodiment the micro processor 102 is the model 87C196CA and the chips 104 and 106 are the model 74HC573 In the pass through mode the microprocessor 102 delivers data directly to the 11708 trans ceiver circuit 50 to the RS 232 transceiver circuit 42 and 20 25 30 35 40 45 50 55 60 65 6 monitors the data so as to provide the 11708 defined timing signals on any or all of the RS 232 hardware handshake signals FIG 8 is a schematic diagram ofthe static RAM circuit 92 and includes a memory chip 110 and AND gates 112 114 and 116 electrically interconnected as shown In one embodi ment the memory chip 110 is the model TC551664BJ 20 well known to those skilled in the art The memory chip 110 is used for temporary data storage and is connected to the CPU 100 through the data and address channels Once a memory allocation area is specified through the address chan nel data can be read or written through the data channel Data signals D 0 15 are used to transfer data bi directionally between the CPU 100 and the memory chip 110 Addres
5. 54 2 8 2003 Lesesky et al 340 431 6 772 248 1 8 2004 McClure et al 6 181 992 1 2001 Gurne et al 7 337 245 B2 2 2008 McClure et al 6 189 057 2 2001 Schwanz et al 7 725 630 2 5 2010 McClure et al 6 193 359 1 2 2001 Patil etal 7 817 019 B2 10 2010 Lesesky 340 431 6 195 359 81 2 2001 Eng et al UR 6 321 151 Bl 11 2001 Shultz 6 526 340 2 2003 Reuletal 701 29 cited by examiner US 8 255 587 B2 Sheet 1 of 9 Aug 28 2012 U S Patent SHYOMLIN 3T0IH3A NI 1 9H 4 E 0 e 2002 150 3974015 2 US 8 255 587 B2 Sheet 2 of 9 Aug 28 2012 U S Patent 9H B0 lt gt CE US 8 255 587 B2 Sheet 3 of 9 Aug 28 2012 U S Patent 9H _ x WLW OL gt i E _ prea BOLE 51070 8 AR T 04 d Ol C 0 INI lt Ol US 8 255 587 B2 Sheet 4 of 9 Aug 28 2012 U S Patent 153 MOH P 413634 1001 ub py I goo Mr usu 1X3 gt Mild 308 Md HIA U S Patent Aug 28 2012 Sheet 5 of 9 US 8 255 587 B2 8 u 27 ty 7 3 LED_RUN LED 939 LED 708 LED PC US 8 255 587 B2 Sheet 6 of 9 Aug
6. ENTION 1 Field of the Invention This invention relates generally to a protocol adapter for passing diagnostic messages between networks within a vehicle and a host computer and more particularly to a protocol adapter for passing diagnostic messages between networks within a vehicle and a host computer where the protocol adapter includes a pass through mode of operation where the protocol adapter emulates legacy protocol adapters so that state of the art host computers can communicate with the vehicle networks using obsolete software 2 Discussion of the Related Art Vehicles employ various networks and systems for diag nostics analysis and monitoring of vehicle systems These various networks are generally selectively connectable to an external host computer so that the operation of the vehicle networks can be monitored by an external system These vehicle systems and networks operate under various proto cols such as the J1708 and the 11939 protocols Protocol adapters are known in the art that allow the host computer to communicate with the vehicle networks through the proto cols One known type of protocol adapter for this purpose is the 11708 protocol adapter The first generation of the J1708 protocol adapter used for diagnostic purposes included a volt age translator with a built in timer circuit that flagged the end of a message This protocol adapter design worked well for 11708 protocols because it and the standard serial com
7. FLASH_CS active low enable FLASH chip select RAM CS active low enable RAM chip select UART CS active low enable UART chip select D 0 15 data signal used to transfer data bi directionally between the processor and memory A 1 15 address signal used to select the desired memory allocation area LOWER active low chip enable for lower byte DE _LOWER active low data enable for lower byte WE LOWER active low write enable for lower byte UPPER active low chip enable for upper byte DE UPPER active low data enable for upper byte WE UPPER active low write enable for upper byte FLASH UPPER FLASH upper byte write enable FLASH CE active low FLASH chip enable FLASH DE active low FLASH data enable FLASH WE active low FLASH write enable A 1 3 address signal used to select the desired allocation area D 0 7 data signal used to transfer data bi directionally between the processor and memory CS active low chip select RESET signal used for reset INTR interrupt line to processor SOUT data out DTR active low enable data terminal ready RTS active low enable ready to send MBAUD used to set the processor in high speed mode Unused in this application SIN data in DSR active low enable data set ready CTS active low enable clear to send EPA3 input output for high speed for capture compare channels EPA8 input output for high speed for capture compare channels EPA9 input output for high speed for capture com
8. US008255587B2 United States Patent 10 Patent No US 8 255 587 B2 McClure et al 45 Date of Patent Aug 28 2012 PROTOCOL ADAPTER FOR PASSING 52 US CL s 710 16 710 73 710 74 701 24 54 DIAGNOSTIC MESSAGES BETWEEN A HOST 701 29 701 31 701 33 701 35 701 36 COMPUTER AND VEHICLE NETWORKS 701 53 OPERATING TN J1939 CRS PROTOCOL 58 Field of Classification Search 340 431 Inventors Robert E McClure Danville IN US DE 340 933 710 72 74 75 David M Such Greenwood IN US See application file for complete search history Assignee Dearborn Group Inc Farmington 56 References Cited 73 Hills MI US U S PATENT DOCUMENTS Notice Subject to any disclaimer the term of this 4 602 127 A 7 986 Neely et al patent is extended or adjusted under 35 4 975 846 12 1990 Abe etal U S C 154 b by 0 days 5 077 670 A 12 1991 Takai et al i 5 491418 A 2 1996 Alfaro etal 324 402 This patent is subject to a terminal dis 5 541 840 A 7 1996 Gurne et al claimer 5 555 498 A 9 1996 Berra et al A 7 1997 Alfaro et al 5 646 865 Appl No 13 199 340 5 870 573 2 1999 Johnson 21 A 4 1999 Butler et al 5 896 569 Filed Aug 26 2011 5 964 852 10 1999 Overton 22 26 Continued Prior Publication Data 65 US 2011 0314191 Al Dec 22 2011 TER n Dearborn Group Inc Dearborn Group Te
9. according to claim 9 further com prising a flash memory module said flash memory module providing permanent storage of application data and loader application information 14 The protocol adapter according to claim 9 further com prising a universal asynchronous receive and transmit UART circuit said circuit providing communication of asynchronous data to and from the host computer 15 The protocol adapter according to claim 9 further comprising a CPU I O interface circuit said CPU I O inter face circuit providing an interface between said CPU and the transceiver circuits 16 The protocol adapter according to claim 9 one of said plurality of transceiver circuits further comprising a 11708 transceiver circuit said 11708 transceiver circuit providing an interface between the vehicle network and the host computer when the vehicle network is operating in a J1708 protocol and the protocol adapter is operating in a pass through mode said 11708 transceiver circuit including the voltage translator for translating the voltage of the 11708 protocol signals
10. ansceiver discussed below in the I O board 32 If the vehicle networks 12 are using the newer J1939 protocol the 1939 signals on the line 22 are processed in the CPU board 34 to provide the J1939 compatibility The I O board 30 and the CPU board 34 use the following list of signals ACH 2 7 inputs for the analog digital converter RESET active low signal issued to reset the processor READY signal used to lengthen memory cycles for slow memory RD active low signal used for external memory reads WRH active low signal used to designate high byte writes 20 25 30 35 40 45 50 55 60 65 4 continued WR active low signal used for external writes EXTINT designates an external interrupt AD 0 15 address data lines to transfer between the processor and memory LA 0 15 latch address used to latch the desired memory bytes EPA3 input output for high speed capture compare channels EPA8 input output for high speed capture compare channels EPA9 input output for high speed capture compare channels SC0 clock pin for SSIOO SD0 data pin 0 SC1 clock pin for SSIOO SD1 data pin for 0 P2 4 standared bi directional ports for data transfer TXD used to transmit serial data RXD used to receive serial data TXCAN used to transmit CAN signal RXCAN used to receive CAN signal A 9 15 high level address for selecting large byte operations HDW_RST active love hardware reset FLASH_UPPER FLASH upper byte
11. chnology J1850 Network Related U S Application Data Analysis Tool JNAT User s Manual Version 5 0 1999 63 pages Continuation of application No 12 799 739 filed on Farmington Hills Michigan 60 Apr 30 2010 now Pat No 8 032 668 which is a continuation of application No 12 002 427 filed on Primary Examiner Tammara Peyton Dec 17 2007 now Pat No 7 725 630 which is a 74 Attorney Agent or Firm Warn Partners P C division of application No 10 888 432 filed on Jul 9 now Pat No 7 337 245 which is a 57 ABSTRACT 2004 continuation in part of application No 09 532 718 A protocol adapter for transferring diagnostic messages filed on Mar 22 2000 now Pat No 6 772 248 between networks within a vehicle and a host computer The Provisional application No 60 126 588 filed on Mar protocol adapter operates as a voltage translator to support 60 software The protocol adapter also recognizes when 11708 1999 26 the protocol adapter is connected to a host computer running Int CI the J1939 and or J1708 protocols and automatically switches 51 G06F 13 12 2006 01 to that protocol G06F 3 00 2006 01 G06F 15 173 2006 01 16 Claims 9 Drawing Sheets STORAGE HOST COMPUTER CPU BOARD YO BOARD E IN VEHICLE NETWORKS US 8 255 587 B2 Page2 U S PATENT DOCUMENTS 6 571 136 5 2003 Staiger 6 122 684 9 2000 Sakura 6 608 5
12. date receive call back polling etc FIG 4 is a schematic diagram of the power supply regula tor circuit 44 and includes a voltage regulator 60 intercon nected with other circuit elements as shown The power supply regulator circuit 44 converts a vehicle battery voltage to a regulated 5V DC for operation of the adapter 30 FIG 5 is a schematic diagram of the LED circuit 52 The LED circuit 52 includes four LED control lines coupled to four LEDs 72 74 76 and 78 through input buffers 80 82 84 and 86 respectively In this embodiment the LED 72 indi cates that the protocol adapter 30 being powered the LED 74 indicates a link to the RS 232 port 16 of the host computer 14 the LED 76 indicates that the protocol adapter 30 is operating in the J1939 protocol and the LED 78 indicates that the protocol adapter 30 is operating in the J1708 protocol FIG 6 is a schematic block diagram of the CPU board 34 CPU board 34 includes a CPU 100 a device decoder circuit 90 a static RAM circuit 92 a flash memory module 94 a UART circuit 96 and a CPU I O interface circuit 98 electrically interconnected as shown The flash memory mod ule 94 is used for program storage The module 94 is respon sible for the permanent storage of the application data and loader application information The module 94 allows the protocol adapter 30 to be updated with new firmware in the field The uploaded firmware is stored in the RAM circuit 92 The UART
13. erring diagnostic messages between a vehicle network in a vehicle and an external host computer said adapter comprising a plurality of transceiver circuits for providing an interface between the vehicle network and the host computer when the vehicle network is operating in one of a plu rality of protocols a central processing unit CPU said CPU controlling the operation of the plurality of transceiver circuits to auto matically switch between the plurality of transceiver 5 30 8 circuits depending on which ofthe plurality of protocols the host computer is using and a voltage translator for translating the voltage of one or more of said plurality of protocols said voltage transla tor being part of one of said plurality of transceiver circuits 10 The protocol adapter according to claim 9 one of said plurality of transceiver circuits further comprising an RS 232 transceiver said RS 232 transceiver circuit providing an interface to an RS 232 port on the host computer 11 The protocol adapter according to claim 9 further comprising a static random access memory RAM circuit said RAM circuit including a RAM that provides temporary data storage and is connected to said CPU through data and address channels 12 The protocol adapter according to claim 11 wherein the RAM circuit further provides redirection of mailbox data storage for oversized messages and the concatenation of small messages 13 The protocol adapter
14. ftware had to be paired with new hardware This required that each diagnostic shop own and maintain several diagnos tic tools It would be desirable to have a protocol adapter that could operate as an old voltage translator to support obsolete software using the J1708 protocol and recognize when the protocol adapter is connected to a host computer running new software to automatically switch to the J1939 protocol SUMMARY OF THE INVENTION In accordance with the teachings of the present invention a protocol adapter is disclosed for transferring diagnostic messages between networks within a vehicle and a host com puter The protocol adapter operates as a voltage translator to support J1708 software The protocol adapter also recognizes when the protocol adapter is connected to a host computer running the 11939 and or J1708 protocols and automatically switches to that protocol Inone embodiment the protocol adapter includes a control area network CAN transceiver circuit that provides an inter face between the vehicle network and the host computer when the vehicle network is operating in a 11939 protocol and a 11708 transceiver that provides an interface between the vehicle network and the host computer when the vehicle network is operating in a 11708 protocol The 11708 trans ceiver circuit includes a voltage translator for translating the voltage of the 11708 protocol signals The protocol adapter further includes a static random access me
15. g 2 The protocol adapter according to claim 1 one of said plurality of transceiver circuits further comprising an RS 232 transceiver said RS 232 transceiver circuit providing an interface to an RS 232 port on the host computer 3 The protocol adapter according to claim 1 further com prising a device decoder said device decoder decoding input signals sent to the CPU 4 The protocol adapter according to claim 1 further com prising a static random access memory circuit said RAM circuit including a RAM that provides temporary data storage and is connected to the CPU through data and address channels 5 The protocol adapter according to claim 4 wherein the RAM circuit further provides redirection of mailbox data storage for oversized messages and the concatenation of small messages 6 The protocol adapter according to claim 1 further com prising a flash memory module said flash memory module providing permanent storage of application data and loader application information 7 The protocol adapter according to claim 1 further com prising a universal asynchronous receive and transmit UART circuit said UART circuit providing communication of asynchronous data to and from the host computer 8 The protocol adapter according to claim 1 further com prising a CPU I O interface circuit said CPU I O interface circuit providing an interface between the CPU and the trans ceiver circuits 9 A protocol adapter for transf
16. mory RAM cir cuit that provides temporary data storage and is connected to the CPU through data and address channels a flash memory module that provides permanent storage of application data and loader application information and a universal asynchro nous receive and transmit UART circuit that provides com munication of asynchronous data to and from the host com puter Additional advantages and features of the present inven tion will become apparent from the following description and appended claims taken in conjunction with the accompany ing drawings BRIEF DESCRIPTION OF THE DRAWINGS FIG 1 is a block diagram of a protocol adapter system according to an embodiment of the present invention that transfers both 11708 and 11939 signals between a host com puter and a vehicle network FIG 2 is a schematic block diagram of an input output I O board in the protocol adapter shown in FIG 1 FIG 3 is a schematic diagram ofa 11708 transceiver circuit in the I O board shown in FIG 2 FIG 4 is a schematic diagram of a power supply regulator circuit in the I O board shown in FIG 2 FIG 5 is a schematic diagram of an LED indicator circuit in the I O board shown in FIG 2 FIG 6is a schematic block diagram of a central processing unit CPU board in the protocol adapter shown in FIG 1 FIG 7 is a schematic diagram of the central processing unit in the CPU board shown in FIG 6 FIG 8 is a schematic diagram of a static mem
17. mpatibility with their original software FIG 9 is a schematic diagram of the CPU interface circuit 98 and includes an interface chip 120 In one embodi ment the interface chip 120 is the model 74HC241 The interface circuit 98 provides interfacing between the CPU 100 and the I O board 32 The foregoing discussion discloses and describes merely exemplary embodiments ofthe present invention One skilled in the art will readily recognize from such discussion and from the accompanying drawings and claims that various changes modifications and variations can be made therein without departing from the spirit and scope ofthe invention as defined in the following claims What is claimed is 1 protocol adapter for transferring diagnostic messages between a vehicle network in a vehicle and an external host computer said adapter comprising a plurality of transceiver circuits for providing an interface between the vehicle network and the host computer when the vehicle network is operating in one of a plu rality of protocols wherein the adapter automatically switches to one or more of the plurality of protocols the host computer is using and further comprising a central processing unit CPU said CPU controlling the operation of the plurality of transceiver circuits to automatically switch between the US 8 255 587 B2 7 plurality of transceiver circuits depending on which of the plurality of protocols the host computer is usin
18. muni cation port of the host computer were based on universal asynchronous receive and transmit UART technology hav ing different physical interfaces i e different voltages The timer circuit was needed to allow the host computer to rec ognize the end of message as defined by the 11708 protocol Most host computers however did not have adequate resources to comply with the rigid timing requirements needed for end of message detection A second generation protocol for vehicle diagnostics pur poses is the J1939 protocol With the 11939 protocol there was no longer a basic compatibility between the known host computer serial communication port and the J1939 protocol It therefore became necessary for protocol adapters to use microprocessors in their diagnostic tools These micropro cessors would receive an entire message from one of the supported links and do message validation including end of message detection The microprocessor would then forward the message on to the appropriate communication channel if it did not detect an error This alleviated the need for the timer 10 20 30 40 45 60 65 2 to detect the end of message but also added an inherent delay between the vehicle data link and the host computer serial communication port The J1939 protocol required that software had to be matched to the diagnostic tool for which it was written Obso lete software had to be paired with legacy hardware and new so
19. ory module circuit in the CPU board shown in FIG 6 and US 8 255 587 B2 3 FIG 9 is a schematic diagram of an I O interface connector circuit in the CPU board shown in FIG 6 DETAILED DESCRIPTION OF THE EMBODIMENTS The following discussion ofthe embodiments ofthe inven tion directed to a protocol adapter for transferring both J1708 and J1939 protocol diagnostic messages between networks within a vehicle and a host computer is merely exemplary in nature and is in no way intended to limit the invention or its applications or uses FIG 1 is a block diagram of a system 10 for transferring diagnostic signals between vehicle networks 12 in a vehicle to an external host computer 14 through a protocol adapter 30 Such diagnostic messages can be any signals for monitoring any suitable vehicle network within the vehicle for diagnos tics and or maintenance purposes as would be well under stood to those skilled in the art The host computer 14 can be any host computer known in the art used for this purpose including state of the art host computers and obsolete host computers The host computer 14 includes an RS 232 I O port 16 that provides an RS 232 interface to the host computer 14 The RS 232 port 16 provides direct access to the J1708 RS 485 link The signals received and analyzed by the host computer 14 can be stored in any suitable storage device 18 such as a display or magnetic tape The signals used by the vehicle networks 12 can
20. pare channels P2 4 PC LED control UART SOUT UART data out UART DTR active low enable UART data terminal ready UART RTS active low enable UART ready to send UART_SIN UART data in UART DSR active low enable UART data set ready UART CTS active low enable UART clear to send FIG 2 is a schematic block diagram of the I O board 32 The I O board 32 includes an external I O interface circuit 40 an RS 232 transceiver circuit 42 a power supply regulator circuit 44 a controller area network CAN transceiver circuit 48 for the 11939 protocol J1708 transceiver circuit 50 including a voltage translator an LED indicator circuit 52 and input and output ports 54 and 56 interconnected as shown The external I O interface circuit 40 provides the interface connection between the various circuits in the I O board 32 and the connections to the host computer 14 and the vehicle networks 12 The RS 232 transceiver circuit 42 provides an RS 232 interface between the vehicle networks 12 and the host computer 14 The CAN transceiver circuit 48 provides a CAN interface between the vehicle networks 12 and the host computer 14 US 8 255 587 B2 5 when the vehicle networks 12 are operating in the J1939 protocol In one embodiment the CAN transceiver is the model 82025117 well known to those skilled in the art The 11708 transceiver circuit 50 provides the J1708 protocol interface between the vehicle networks 12 and the host com puter
21. s signals A 1 15 are used to select the desired memory allo cation area in the memory chip 110 The static RAM circuit 92 provides space reserved in the adapter s memory for the temporary storage of data for the transmit and receive mailboxes The static RAM circuit 92 provides flexibility for transmitting and receiving messages regardless of the 11708 or J1939 vehicle protocol by provid ing a temporary message storage location redirection of mailbox data storage for oversized messages such as J1939 transport protocol messages and the concatenation of small messages Sometimes both the 11708 and the 71939 protocols trans mit oversized messages A normal J1708 message may be up to 21 bytes long However special modes may utilize longer messages The protocol adapter 30 accommodates these over sized messages by putting the J1708 mailbox into extended mode and attaching it to a location in the static RAM circuit 92 The J1939 transport layer also makes use of the RAM circuit 92 to ensure that transport timing requirements are met The storing of multiple messages in the static RAM circuit 92 reduces multiple reads and writes to the adapter hardware The concatenation ofthese short messages reduces the overhead on the serial port The static RAM circuit 92 allows users to replace legacy hardware with an interface that can support existing software Consequently users can replace legacy hardware with the protocol adapter 30 and maintain co
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