unclassified______________ a signal averager interface
Contents
1. ERASE H i rE JD SUMLD L ee P SUMEN L SACYC L OWT H DATIO H i2 3 gt ADREN L 16 a x gt DATEN L DATEN H 9 10 4 55 6p g 1 MACLK L 13 R gt 16 L FP 6752 INIT L Figure 18 Master controller schematic 05 DEVMAS L ARM L INIT H 11 gt READY H USER REQST L Md fP 6757 Figure 19 Master controller schematic TS BIOMATION 6500 SA LSI 11 2 32Kx16 INTERFACE CPU MEMORY LSI 11 BUS DISK 4 SIO PORTS CONTROLLER Ui N Figure 20 Total system configuration 58 IC PARTS LIST Number Number 1 74LS74 3T 741527 2 7425 32 741502 3 74LS00 33 10 pole DIP switch 4 741574 34 DC005 5 74LS74 35 0005 6 7418244 36 0006 7 7418174 37 DC006 8 74LS221 38 74LS244 9 74LS221 39 74LS74 10 74LS10 40 74LS74 LE 74LS04 41 74LS74 12 74LS02 42 74LS221 13 741874 43 7418221 14 741551 44 741500 15 741500 45 741502 16 741502 46 741504 d 74LS74 47 7418132 18 7418244 48 741828 19 741800 49 741886 20 741502 50 7415273 21 7418221 SE 74S412 22 DC005 52 74S412 23 DC005 53 74LS273 24 5 pole DIP switch 54 74LS244 25 74LS240 55 7418244 26 0003 56 7418374 27 0 010 57 74LS283 28 74LS240 58 74LS283 29 DC004 59 74LS283 30 74LS27 60 74LS283 Number 61 62 63 64 65 66 67 68 69 70 LS 72. 1 2 3 2 37 2 5 1 4 7 1 5 1 330 680 MGI L REQ H 80M60 LP0MS not L AN TOS INIT L pagni BDMR L TOOUTM m DATN L 4 TDIN H MASTER H 5 ADREN H TSYNC Ha RPLY H 1000p ON QUAD BOARD 330 BDMGI BDMGO L 47 WCNTO H 2 18 T 1 DATA 13 12 9 RQSTB H FP 6753 Figure 13 DMA and program control schematics CSRWHB H 3 DATA 15 5 1K ADREN ATTN JE 2 Sacre H EVE REQH 9 T TOS INIT Reer i i oo oH v 46 CSRWHB 2 ma 44 9 1 ROSTA H DATA 15 x DATA 10 INIT L USER ROST L 34 4 DATA 11 2 5 REQ H CSRWHB 5 gt DATNL WCNTO H TOS INIT H Figure 14 DMA and program control schematics CSRRD L wo Do SEL4 L m MRPLY L 13090 csrwne 3 OUTHB L 4 1 lt H OUTLB L 3 De 25 10 DATEN L MRPLY L BT H OUTHB L QUTEBL 1 TDIN H XMIT H ADREN H 1 77 NA 2 REC H TRPLY H s si INWD 4 _ 4 BRPLY 4 0 16 RPLY H I I 1 TRPLYH 5 19 TDINH 0 14 RDIN H gt
3. 1 BSYNC I 8 19 I TSYNC H RSYNCH 1 19 BDOUT M I H 2 gt 18 Se 28 1 25 MASTER H 2 BSACK 6760 Figure 15 DMA and program control schematics 47 48 CSRWLB H DATA O 2 START H INIT L DATA 2 4 5 OWT H 7 gt DATA 4 5 XAD 17 2 gt R 1 DATA 6 14 15 MEMDSPLY H DATA 7 12 ERASE H 7 94 142 R RESET L 470p 951K 10 DATA 8 12 9 2 48 13 2 INIT L INITB L 14 gt 0 42 46 aD INIT H CSRWHB H 11 T A FP 6756 Figure 16 DMA and Program control schematics 1 ATTN Lit gt 1 pATA 0 19 I L READY H 17 3 DATA 1 LU DEST L 64 gt s 1 0A7A 2 1 LI OWT H 15 S s DATA 3 719 I 16 84 gt 12 DATA 4 1 I XAD 17 13 7 DATA 5 D i 1 MEMDSPLY H L 2 18 L DATA 6 1 i 1 ERASE 44 gt 167 DATA 7 91 16 d CSRRD L Figure 17 DMA and program control schematics INIT Hel 16 DATA 8 1 DATIO L 18 DATA 9 x i DATIN 5 52 10 719 B 34 DATA 11 21 I 1 I 12 DATA 12 14L DATA 13 ENAST H 1 9 14 i RQSTA H 13 DATA 15 19 l 738 l FP 6754
4. 8 FP 6750 Figure 9 ALU schematics 42 r 5 gerat gt 1 gt 5 15 reri E 12 17 are ini 8 EEE N E I an 44177 PERE N RTE p pasasqa i eed 3 x z Hr MEM 3 R 1 LoT 9 10 M tw px UA Eu E PE 020700 87 1 L 5 5 q 10 24 10 7T 5 10 10 5 your A 9 48 0 gt BLANK he XOUT MEMOSPLY 4 16 K 16 d RC 12 FP 6749 Figure 10 Memory and DAC schematic 1504 15 36K TN 100 1N914 4 FP 6755 Figure ll 12V inverter schematic 4 INWD H 9 n BWTBT L BSYNC L BDOUT L M H MRPLY L 2 ran an en D SELO L ens SEL4 L SEL2 L x Bee a SEL6 L n 1 L 559 L 38 RWHB H BIAKO L lt CSRWLB H BIAKI au ENAST ROSTB H ee DEAR toreh A L so gt INITB L Quod Boord 680 FP 6759 Figure 12 DMA and program control schematics 45 DATA 3 15 15 16 14 N n UTHB L is 12 i 5 Res ex 9 INWD L L2L 8 en WENTO H DATA 3 15
5. 4 CS SAsSCSR FC 9 173777 002000 9 SABUF 4030 FRIS SA CSR ATTN 200002 8 SAECSR RET FC SAREG Figure 7 Continued 38 ATTN MSGXXX DEC BEQ JSR RTS JSR RTS ASCIZ EVEN BIS JSR 5 RTS END SASCAN SAHALT PCy SASTRT RE EG Stee COMEL ETE 8 1 122 7SCANS COMPLETE f ah 50000 BRSASCHR FC 2 FCs SARSET PG Figure 7 Continued 39 5 330 6K DATA O 5 DATA 1 h EN DATA 2 5 EA 11 3 DATA 4 Slr 3 9 19 5 2 DATA 6 DATA 7 OSTBLB H OZERO L ADDAO SACYC H SACYC L ADDA 15 OSTBHB H DATA 8 DATA 9 1 5225 T gt DATA 11 fs I DATA 12 ett DATA 13 TF 2 que T 1 DATA 15 f FP 6751 Figure 8 ALU schematics 41 ADDA O ADD 7 1412 62151 5 31412 62151 5 4 10 41 10 7 USE PERTH gars Wr GENER Nh I II MEM 7 Z ALTE DI rl LL 22 u pepa um s DATA DEREN CCELI OUS MEMO af M DATLD H SUMLD L SUNEN 11 DATA 15 5 9 2 ia TE EEE 5 15 14 L DATA 8 16 M6M 8 7 COUT 57 121435 11152 ADD A 15
6. UNC s SECURITY CLASSIFICATION OF THIS PAGE When Data Entered REPORT DOCUMENTATION PAGE 4 TITLE and Subtitle 4 REPORT NUMBER 2 GOVT ACCESSION 3 RECIPIENT S CATALOG NUMBER A SIGNAL AVERAGER INTERFACE BETWEEN A BIOMATION 6500 TRANSIENT RECORDER AND Technical Report AUTHOR s 8 CONTRACT OR GRANT NUMBER s L T Specht N00014 79 C 0424 PERFORMING ORGANIZATION NAME AND ADDRESS TASK Coordinated Science Laboratory University of Illinois at Urbana Champaig Urbana IL 61801 CONTROLLING OFFICE NAME AND ADDRESS 12 REPORT DATE June 1980 T ME 55 MONITORING AGENCY ADDRESS if different from Controlling Office 15 SECURIT Y CLASS of this report UNCLASSIFIED 15a DECL 551 DOWNGRADING SCHEDULE DISTRIBUTION STATEMENT of this Report Approved for public release distribution unlimited DISTRIBUTION STATEMENT of the abstract entered in Block 20 if different from Report SUPPLEMENTARY NOTES KEY WORDS Continue on reverse side if necessary and identify by block number Signal averager Transient recorder Computer Interfacing ABSTRACT Continue on reverse side if necessary and identify by block number This report describes the design and implementation of a versatile and compact signal averager interface between a Biomation 6500 transient recorder and a LSI 11 microcomputer The design allows for f
7. by two on each transition of ADREN H The word count register WCR is loaded with the two s complement of the number of words to be transferred and is incremented on each transition of ADREN H also When the WCR overflows it generates WCNTO H which negates REQ H and terminates the DMA transaction WCNTO H also sets the B inter rupt flip flop which asserts RQSTB H so that if the B inter rupt channel has been enabled initiates an interrupt request Both the WCR and the BAR are contained in two DC006s cascaded to form two 16 bit registers SEL L selects the BAR while SEL2 L selects the WCR INWD L reads the selected register and OUTHB L and OUTLB L write the high and low byte into the selected register Data is transferred through the read only data input regis ter DATIR 74LS374 and the write only data output register 7415273 used to write data into the high and low byte of the DATOR and DATEN L is used to read data from the DATIR Under program control DATEN L is generated by SEL6 L and INWD L and during a DMA DATO or DATIO cycle by DATN H Also under program control CHANHB H and CHANLB H are generated by SEL6 L and MRPLY L together with OUTHB L and OUTLB L whereas during a DMA DATI or DATIO cycle CHANHB H and CHANLB H are both generated by TDIN H The control and status register CSR as its name implies is used to control and monitor the status of t
8. during DMA cycles to keep tract of the number of words transferred and to provide a memory address to or from which each word is trans ferred is loaded under program control with the 2 s complement of the number of words to be transferred and the BAR is loaded with the starting address The DATIR and DATOR can also be accessed under program control to read or write in formation out of or into the SA memory Each time either the DATIR or DATOR is accessed the memory address is advanced to the next location Normally the DATOR and DATIR are used during DMA cycles to buffer data into or out of the SA inter face The CSR is used to control and monitor the status of the SA interface A brief description of each of the 16 CSR 10 bit functions is given in Table 1 Each bit can be read or written under program control Bits 4 and 5 of the CSR are special in that they are the extended memory address bits XAD 16 and 17 making the SA interface compatible with the memory management unit MMU of the LSI 11 23 Two interrupt vectors are also selectable on the SA inter face They are typically used by interrupt requests generated at the end of a DMA cycle or due to an error condition to point to interrupt service routines A very simple program illustra ting the use of these registers and the interrupt vectors in normal operation is provided in Figure 7 Data can be transferred during a DATIO cycle in either single or double
9. of the memory contents 4 6 Software controllable and configurable see the soft ware section for the various options and configurations that may be implemented by the CSR 7 Ease of operation and extensive data manipulation this is basically a characteristic of the 151 11 system and corresponding software As a final note while the SA interface described here is specifically for use with the 6500 any other TR that uses a similar means of data transmission can be utilized as a front end unit Namely the 6500 uses a word serial bit parallel data transfer under a handshake control See the circuit description for more information if the SA interface is to be used with another TR 2 HARDWARE OVERVIEW The basic block diagram of the SA interface is illustrated in Figures 1 5 There are five major functional sections 1 arithmetic logic unit ALU 2 memory 3 x y DAC 4 DMA interrupt controller and 5 master controller Each of these five sections will now be briefly described a more complete discussion can be found in the circuit description section The ALU section is basically a 16 bit adder whose B input is the memory data bus MEM 0 15 and whose input can be either the 6500 data bus PERDATA 0 5 or the SA data bus DATA 0 15 Both the and B inputs can be set to zero via the data output register DATOR and the sum latch respectively The adder output is written into the sum latch whi
10. precision format Single precision format results in 16 bit signed 2 s complement fixed point integer INTEGER 2 whereas double precision format results in a 32 bit result INTEGER 4 Since the data is placed in standard integer format no premanipulation of the data is necessary The double precision format also allows very extensive signal averaging for long lengths of time without loss of precision Besides the normal DATO or DATIO cycle transfers data may also be transferred into the SA interface during a DATI or DATIB cycle This allows the SA memory to be used as a lk scratchpad area with the capability of either simple read write operation or single step add to memory operation It also allows loading the SA memory with information to be displayed using the x y monitor 4 CIRCUIT DESCRIPTION This section provides detailed description of each section of the SA interface While reading it may be useful to look at the appropriate schematic indicated for each sub section In this description the convention of placing an H or L after a signal mnemonic indicates either a high or low active signal 4 1 Arithmetic Logic Unit ALU Figures 8 and 9 The ALU section uses either the SA data bus DATA 0 16 or the 6500 data bus PERDATA 0 5 to perform one of three functions on the contents of the SA memory 1 add to memory 2 overwrite memory or 3 write zero to memory 6500 data bus is terminated wit
11. 4 75 76 77 78 79 80 81 82 83 All resistors are 5 w Type 74LS283 7415244 7415244 7418393 7415393 7418132 7415393 7418374 2114 2114 2114 2114 7415374 AD561 74LS02 4 pole DIP switch AD561 AD509 74LS374 AD509 7912 LM311 74LS02 All capacitors lt 1000 00 01 gt 1 1 1 5 carbon uf uf mica 5 ceramic disc monolythic 50V tantalum 54
12. ABEGN GLOBL SASTAT sSAFILL sSASTOFsSASTRT SASCAN T 2 SAS CSR 1746534 SASVECH SSO PRI7 340 FRIS S SABEGN FAREA 0LIST SA VEC BCS 2 FPROTECTHAREA y TSA VECTA BCS 2 MOV BESASVEC 2 MOV BESASVECT4 MOV C HESASVECTS CCC 23 RTS PG AREAS 10 DUIST SASCSRs 4000 SAnPLY MOV SASCSR SACSR JSR FO SARSET 5 000100 RTS FC SAERSE MOV kSASCSR SACSR JSR FC SARSET RIS 1000200 1 BIT 1000200 15 JSR FC SARSET MOV SACSRy B SASCSR RTS SARSET BIC 1050000 SASCSR BIS 1000400 18 BIT 000400 ENE 1 RTS FC SAFILL MOV QESASCSR SACSR JSR SARSET Figure 7 A simple interrupt handler routine SA ASTAT STATES MSG1 M502 MSGBLR MOV TST MOV MOV DEC BNE MOV JSR RTS MOV MOV MOV CLR SEC ROL RCS oP RINT BIT BNE BR FRINT Ant BR MOV RTS WORLD ASCIZ ASCIZ ASCII WORD ASCII WORT ASCII WORI ASCII WORI ASCII WORD ASCII WORD ASCII WORI ASCII WORT ASCII WORLD ASCII SF RS R gt RQ ACRI 1 LSF RO FC SADPFLY FC R29 SF ESAS CSR SACSR HMS
13. GBLKyR2 STATB STATE 55 R2 STATB SACSR 1 4 1 2 4562 22 2 3 5 2 PC 0 Z NOT SET SET ATTENTION FLAG 100200 SA DEVICE START 100200 DESTRUCTIVE READ 100200 DOUBLE FRECISION 100200 XM ADDRESS 16 100200 XM ADDRESS 17 100200 MEMORY DISPLAY 100200 ERASE 100200 8 DEVICE RESET 100200 READ MOD WRITE 100200 READ OUT Figure 7 Continued 37 SASTOF 15 24 RAS ue MSGINT SAINIT SAREG SASCAN 08 SACSR SABUFF SABUF SAIH WORI ASCII WORT WORD ASCII WORI ASCII WORT ASCII WORD EVEN MOV BIS MOV MOV MOV JSR RTS BIT BNE BIS RIS RTS BIC BR ASCIZ EVEN TST MOV MOV MOV MOV RTS WORI WORD WORI W RD WORT ELKW INTEN TST BMI BIT BEQ JSR JSR 100200 IMA REQUEST 100200 1 INTERRUPT 100200 INTERRUPT 2 100200 ERR INTERRUPT EN 100200 ERR INTERRUPT 100200 945 4000001 BESASCSR 4 5 00 4 RA 1 5 PC SARSET PC 120000 005649405 1 050000 015 000002 015 1200007 TMSGINT 2 SR SR PN INTERRUFT IS SET FOSSIELE ERROR RS SASCAN WOr SASCSR 2 SABUFF
14. analog converter section Figure 5 BBS7 L BINIT L BIAKI L BIAKO L BIRQ L BWTBT L BDOUT L BSYNC L BDAL 0 15 gt E xevas K DA DEVICE SWITCH m poen VA VECTOR SWITCH ADDRESS INTERRUPT LOGIC PROTOCOL LOGIC REG SELECT GST TPE K SBI DMA LOGIC ADREN H Direct memory address and interrupt section DATA BUS ADDER INPUT ADDER OUTPUT ATTN H READY H DEST L OWT H XAD 16 XAD 17 MEMDSPLY H ERASE H INIT L DATIO L DATIN L REQ H ENBST H RQSTB H ENAST H RQSTA H gt REGISTER DECODED BY BBS7 SWITCH SELECTABLE SELECTION 10 093087 65885 1 0 AI2 All AIO A9 A8 7 A6 5 4 CONTROL 24 6 254 P 33 2 5 24 5 24 5 33 1 33 3 33 5 DEVICE ADDRESS WCR IXXXXO BAR IXXXX2 CSR IXXXX4 DATIR DATOR 6 INTERRUPT SELECTION 3 T 6752473 I V8 V7 V6 V5 V4 V3 O 24 33 7 33 9 33 6 33 8 33 10 FIRST VECTOR XXO SECOND VECTOR 4 INTERRUPT VECTOR Figure 6 Device address and vector address format 36 PRELIMINARY SIGNAL AVERAGER UTILITY ROUTINES Ll gt gt we MCALL 4 REGIIEF MCALL 5 REGDEF GLOBL SAINIT SABUF I SADPL Y SAERSE SARSET S
15. ast signal averaging in excess of 1 kHz and is also easily software configurable and controllable The interface has been incorporated into an LSI 11 system using the RT 11 operating system and found to perform very satisfactorily DD Aet 1473 EDITION OF NOV 65 IS OBSOLETE UNCLASSIFIED 5 TYPE OF REPORT amp PERIOD COVERED SECURITY CLASSIFICATION OF THIS PAGE When Data Entered SECURITY CLASSIFICATION OF THIS PAGE When Data Entered SECURITY CLASSIFICATION OF THIS PAGE When Data Entered A SIGNAL AVERAGER INTERFACE BETWEEN A BIOMATION 6500 TRANSIENT RECORDER AND 151 11 MICROCOMPUTER by Specht This work was supported in part by the Joint Services Electronics Program U S Army U S Navy and U 5 Air Force under Contract 0014 79 0424 Reproduction in whole or in part is permitted for any purpose of the United States Government Approved for public release Distribution unlimited A SIGNAL AVERAGER INTERFACE BETWEEN A BIOMATION 6500 TRANSIENT RECORDER AND LSI 11 MICROCOMPUTER L T Specht Department of Electrical Engineering and Coordinated Science Laboratory Abstract This report describes the design and implementation of a versatile and compact signal averager interface between a Biomation 6500 transient recorder and 151 11 microcomputer The design allows for fast signal averaging in excess of 1 kHz and is also easily software configura
16. ble and controllable The interface has been incorporated into an 151 11 system using the 11 V3B operating system and found to perform very satisfactorily 1 INTRODUCTION This is the description of a versatile signal averaging system based around a Digital Equipment Corporation DEC LSI 11 microcomputer and a Biomation 6500 transient recorder TR With the widespread utilization of LSI ll s in various experi mental configurations it is convenient to have a signal averager SA plug in that would interface a transient recorder front end unit with the computing power of an LSI 11 This would elimin ate in many cases the need for an external signal averager mainframe in order to incorporate TR into an existing 151 11 based system Besides providing a rather large cost savings this results in a more compact system that is both versatile and easy to use The SA interface described herein is com patible with either the DEC 151 11 LSI 11 2 or LSI 11 23 CPU and any system based on one of these CPU s and which will hence forth be referred to as simply LSI 11 At this point a brief description of what is meant by a signal averager and transient recorder may be in order Basi cally a signal averager adds together waveforms that are present will add constructively whereas any incoherent features will add destructively In this way the ratio of signal to noise SNR or coherent to incoherent features can be increa
17. ch can be placed back on the memory data bus and the data input regis ter DATIR which can be placed back on the SA data bus This allows the ALU to operate on the 6500 data bus or the SA data bus in one of three ways 1 add to memory 2 overwrite memory or 3 write zero to memory The memory consists of four lkx4 bit static RAMs arranged as 1 16 bit words The memory address MA is generated by the memory address counter and stored in the memory address register For display purposes the MA counter may also be continuously clocked at a 1 MHz rate A x y CRT monitor output is available through two 10 bit DACs The x DAC monitors the memory address bus whereas the y DAC monitors the 9 least significant bits and the most signi ficant sign bit of the memory data bus assuming that data is stored as signed z s complement fixed point numbers Each channel provides 5 full scale output 12V inverter is provided for the DACs so that the only backplane voltages re quired are 5V and 12V A z blank output is also available The x y output can be used to monitor the memory contents either real time during signal averaging or under program control The DMA interrupt control section is capable of performing DATI DATIB DATO and DATIO bus cycles whichare input output and input output read modify write transfers between the 151 11 and the SA interface This section contains the 151 11 bus transceivers and log
18. e The results of averaging 512 scans from the 6500 is now stored in the SA memory and is ready to be transferred to the main memory of the 151 11 At this point the user can con figure the transfer in several different ways through the use of the CSR The transfer can be configured as either a DATO or DATIO though the use of the DATIN and DATIO CSR bits For a DATO transfer the contents of the SA memory can be reset to zero or left unchanged after the transfer by setting the destructive bit of the CSR For a DATIO transfer the resul tant word size in the main memory can be either 16 or 32 bits corresponding to either single or double precision integer 22 format contents of the SA memory are automatically reset to zero during a DATIO transfer In the normal SA operating mode a DATIO transfer would be performed with a 32 bit expansion of the stored 16 bit SA memory contents In this configuration the DATIO bit of the CSR is set which asserts DATIO H and the one word transfer bit is not set so that OWT H is set low When the first dress is placed on the bus ADREN L is asserted which toggles the double word flip flop which enables the sign bit SB and carry COUT latches to be loaded by SUMLD L The 200 ns SUMLD L pulse is generated by CHANHB H or CHANLB H in con junction with DIN H which also produces DSTBHB H and DSTBLB H to load the DATOR SUMLD L is then gated to produce DATLD H which loads the DATIR with the s
19. ention is called by operator inter vention to halt the device without destroying current contents For both 1 and 2 bit 14 must be set H to enable A interrupt Must be set H to enable bit 15 A interrupt request Otherwise A interrupt is ignored Sets H when word count overflows signifying the end of the DMA cycle generates interrupt request BS Must be set H to enable interrupt request B otherwise B interrupt is ignored Sets H when the device requires a DMA resets back L on word count overflow also on non existent address and INIT Determines R W status of SA memory H indicates DOUT cycle device to bus L indicates DIN cycle bus to device Determines R M W status of SA memory if set L causes DATIO cycle Resets device when set H 1 us RESET INIT pulse Erases SA memory when set H erase time v 1 ms Resets to L at end of ERASE cycle 28 BIT DESCRIPTION 1 1 0 6 If set H causes contents of memory to be clocked at 1 us word used to display memory contents on scope contents can be either SA result or data returned from the bus 5 Extend memory address bit 17 used to expand addressable memory from 32k words to 128k words used by MMU on LSI 11 23 4 Extended memory address bit 16 see bit 5 3 When set H inhibits 16 bit 32 bit increase in word size during DOUT cycle single word precision When set L causes 32 bit storage of data double word precision I 4 fo
20. es as the square root of the number of waveforms averaged In typical experimental configurations some form of addi tional data manipulation is usually required after the averaged 3 waveform has been obtained This may include addition subtraction of waveforms to remove undesirable coherent features integration differentiation Fourier transform graphical display handcopy output waveform storage etc When used in conjunction with an 151 11 system all of these features and more are readily programmable and changeable as the user s needs change Also since the SA interface is soft ware controllable it is readily amenable to incorporation into an automated environment In view of the above considerations the main features that the SA interface incorporates are as follows 1 Plug in capability everything is contained on a single quad size printed circuit board 2 High data taking rate this allows for a 1 1 5 kHz repetition rate for transferring a 1024 point acquired wave form 3 Low CPU dead time at the maximum repetition rate there is only approximately 2 dead time for any length of time 4 No premanipulation of stored data the signal averaged waveform is stored in either single precision 16 bit or double precision 32 bit integer format 5 analog outputs two 10 bit DAC CRT monitor outputs are provided for either real time viewing of the signal aver aged waveform or programmed display
21. ftware section for a description of each of the CSR bit functions The master control section provides the control structure for interconnecting the other sections of the SA interface This includes handling communication with the 6500 keeping track of the number of processed waveforms initiating DMA re quests and implementing the various configurations setup through the CSR 8 Typical cycle times 700 900 ns per word which for the 1024 word waveform stored in the 6500 allows a maximum repeti tion rate of 1 1 5 kHz At this rate a SNR improvement of 100 can be obtained in 10 seconds Also at the maximum rate a DMA cycle is requested every 5 seconds which takes approximately 8 ms for a double precision transfer thus giving rise to ap proximately 2 CPU dead time 3 SOFTWARE This section discusses the SA interface from a software point of view with the intention that the reader may learn how to use the SA interface without having to become familiar with all of the hardware is assumed that the reader is somewhat familiar with the 151 11 software if not one can consult the 51 11 Microcomputer Handbook 2 The SA interface is programmed through the five registers contained in the DMA interrupt section WCR BAR CSR DATIR and DATOR Each of these registers has a unique address established by the device address and as such each is acces sible under program control WCR and BAR are used
22. generated to latch the data into the DATOR Either DSTBHB H or DSTBLB H clocks the DZERO flip flop which negates DZERO L and triggers a 200 ns one shot to produce WP L which writes the resultant sum into the SA memory At the same time WCD L is also asserted to fetch the next word from the 6500 At the end of WP L MACLK L is asserted which loads the next address into the MAR and also increments the MAC The beginning of the 250 ns pulse also triggers a 400 ns one shot which reasserts DZERO L and holds off acknow ledgement of FLG H to allow for the 6500 s data lines to settle and allow for the next SA memory location to be accessed After the 400 ns one shot times out FLG H is honored and the 21 cycle repeats until RESET is generated from the RESET L negates L and SACYC and clocks the arm flip flop which asserts READY H to indicate that the device is ready to accept more data and produces the 150 ns RMA L pulse after 1 micro second delay to the 6500 to the trigger circuitry This permits a data output rate from the 6500 of x 700 ns per word which amounts to a signal averaging repetition rate of 1 1 5 kHz for the faster time bases Scans are continuously processed until the scans counter which is incremented after each record cycle reaches 512 scans At this point L is inhibited from being reasserted and at the end of the SA cycle NWOVE H is gated to generate REQ H which DMA cycl
23. h 150 ohms and goes to one input of a 16 bit 2 to 1 multiplexer MPX consisting of four 7415244 non inverting octal buffers and 3 state line drivers connected in series parallel The 74LS244 is used because of its 400 mV noise margin The other MPX input is the SA data bus which is selected by SACYC H The high byte and low byte of the MPX are latched by DSTBHB H and DSTBLB H respectively into the data output register DATOR 74LS273 The output of the DATOR ADDA 0 15 which may also be set to zero by asserting DZERO L goes to the A input of a 16 bit adder 74LS283 The adder s B input is the SA memory data MD bus MEM 9 15 which moni tors the contents of the SA memory The adder output is 12 latched into the data input register DATIR 74LS374 by DATLD and into the sum latch 745412 by SUMLD L out put of the DATIR goes onto the SA data bus when DATEN L is asserted and the output of the sum latch goes onto the SA MD bus when SUMEN L asserted SA MD bus is active pull down set to zero by asserting SUMCLR L on the sum latch The carry in and carry out of the adder are CIN and COUT respectively these are used for double work transfers during a DMA operation 4 2 Memory Figure 10 This section is based around a lk word by 16 bit memory array composed of four 2114 MCM2114L 1kx4 bit statis RAMs with typical access times from 200 450 ns The memory input and output is via
24. he device The CSR consists of 3 state drivers 74LS244 and D flip flops 74LS74 74LS175 DC003 that are incorporated in the logic throughout this section read and write operations of the CSR are governed by CSRRD L CSRWHB H and CSRWLB H SEL4 L selects the CSR INWD L generates CSRRD L CSRWHB H and CSRWLB H are generated by OUTHB L and OUTLB L together with MRPLY L A description of the function of each of the CSR bits is given in Table 1 4 5 Master Control Figures 18 and 19 This section handles the control lines to and from the Biomation 6500 as well as implementing the various configurations 19 established by the CSR 11 lines from the 6500 terminated with 150 ohms and go into line receivers 74LS244 for in creased noise immunity lines to the 6500 are through line drivers 74LS244 for the same reason Before discussing the master control section a brief description of the Biomation 6500 control structure is in order for more information consult the Biomation 6500 Oper ating Manual Before the 6500 may be triggered the trig ger circuitry must be armed this is done by asserting RMA L After being armed the next trigger pulse initiates the record cycle indicated by RCD L going low After the analog waveform has been recorded RCD L is negated L must then asserted within 10 microseconds from negation of RCD L to enter the digital output mode In the digital output mode t
25. he two hand shape control lines FLG H and WDC L are used to output the 1024 words of stored information FLG H is asserted to indicate that valid data is present the 6500 s output lines next word is then fetched when WDC L is asserted which negates FLG H for 350 ns 6500 s fetch time This continues until all of the memory locations have been accessed at which time OPT L is negated and the 6500 is rearmed by RMA L and the cycle repeats The signal averaging SA cycle begins by setting the start bit of the CSR which in turn asserts DEVMAS L if the attention bit of the CSR is not set DEVMAS L enables the line drivers and receivers 74LS244 for RCD L OPT L and RMA L DEVMAS L also triggers a l microsecond one shot which times out and triggers a 150 ns one shot to produce RMA L After being armed the next trigger pulse at the 6500 begins the record cycle signified by assertion of RCD L RCD L also resets the arm flip flop When the record cycle is complete RCD L is negated which sets the SA cycle flip flop to generate SACYC H and OPT L The negation of RCD L also increments the SA scans counter 74LS393 which is preset to a count of one by the application of INIT H SACYC L enables the line driver and receiver for FLG H and WDC L The 6500 responds to OPT L by asserting FLG H to signify that the first word has been placed on the 6500 data bus Approximately 100 ns after FLG H goes high DSTBHB H and DSTBLB H are
26. ic to implement interrupt requests address control protocol and DMA requests Also contained in this section are five registers 1 word count register WCR 2 bus address register BAR 3 control status regis ter CSR 4 data input register DATIR and 5 data output register DATOR The device address and interrupt vector are switch selectable as illustrated in Figure 6 thus establish ing the five register addresses and the two interrupt vectors A brief functional description of each of the five registers is given below 1 The WCR is used to control the number of words trans ferred during DMA cycle It is loaded with the 2 s complement of the number of words to be transferred and is incremented after each word is transferred The DMA cycle is terminated when the word count reaches zero 2 The BAR provides the memory address to or from which data is to be transferred It is loaded with the starting address of the transfer and is incremented after each word is transferred 3 The DATIR and DATOR are write only and read only registers sharing the same register address These registers as the others can be accessed under program control but are typically used during a DMA cycle to buffer data into or out of the SA interface 4 The CSR is used to control the functions and monitor the status of the SA interface The SA interface may be con figured in many different ways through the use of the CSR refer to the so
27. inverter is provided on board so that 12V and 5V are the only backplane voltage needed The inverter uses a 80 kHz charge pump oscillator built around a LM311 to pump a 1 mH inductor This is filtered to provide 15V which is then regulated to 12V with a 7912 regulator This voltage is used by both the AD561 and AD509 to provide XOUT and YOUT A TTL compatible z blank is also provided which can be used to blank the oscilloscope trace except during a SA cycle or when MEMDSPLY H is asserted A SA cycle is determined by SACYC H being asserted and MEMDSPLY H is used to provide a flicker free display of the uncharging SA memory contents 14 4 4 Direct Memory Access DMA and Program Control Figures 12 17 Since the implementation of this section is heavily based on the use of Digital s custom ICs CHIPKIT it is suggested that the reader unfamiliar with these ICs consult the CHIPKIT Users Manual 3 for further information and circuit descrip tions It is also assumed that the reader is familiar with the 151 11 microcomputer and if not to consult the 151 11 Microcomputer Handbook 2 The first part of this section will deal with those components that are common to both the DMA and program control data transfer whereas the latter part will deal with those that are unique to the DMA transfer Four DC005 transceivers are used to interface the 16 BDAL lines to the 16 SA data lines Their receive or transmit status
28. is determined by REC H or XMIT H being asserted re spectively with receive being the normally active state The transceivers also provide for device address and interrupt vector inputs determined by user selectable switches 12 and 8 3 These user configurable switch settings are illus trated in Figure 6 When the proper device address has been decoded by the DC005 the protocal logic DC004 is enabled to decode the proper bus synchronizing signals SA data lines 1 and 2 are decoded to produce SEL L SEL4 L which select one of four SA registers direction of transfer into or out of the SM Tite Er TI 95 0277 0 1 7 15 selected register is determined by INWD L OUTHB L and OUTLB L which generated by the control lines BWTBT L RSYNC L RDOUT L and RDIN L the latter three control lines are the buffered bus signals BSYNC L BDOUT L and BDIN L Two interrupt channels A and B are provided by DC003 with channel A having a higher priority than channel B The respective channel is enabled by asserting SA data lines 14 and 12 and then toggling CSRWHB H The status of either chan nel can be monitored by ENAST H and ENBST H which form part of the control status register CSR After being enabled the ap propriate channel interrupt request may be made by asserting RQSTA H or RQSTB H which in turn asserts BIRQ L The daisy chain bus signals BIAKI L and BIAKO L are then used to deter mi
29. ne the priority of the interrupting device After the priority has been determined the device vector is then placed on the BDAL lines Interrupt requests are provided for completion of a DMA request a bus timeout due to a non existant address and a user initiated request for device attention The DC003 also buffers BINIT L to provide a SA initialization signal INIT L Setting the CSR reset bit also generates a 1 microsecond INIT L pulse not hang up for more than 10 microseconds if a non existant address is placed on the bus When the address is placed on x The bus timeout interrupt is provided so that the bus will 16 the bus 10 microsecond one shot is clocked by ADREN H The one shot is then cleared when RPLY H goes high to signify that the address has been accepted RPLY H does not go high the one shot clocks the interrupt flip flop which pro duces TOS INIT H and negates REQ H to release the bus The A interrupt flip flop also sets RQSTA H to initiate interrupt request if the A interrupt channel has been enabled RQSTA H may also be set directly through the CSR or through the attention bit of the CSR Setting the attention bit asserts ATTN L which generates RQSTA H immediately if the device is in active or at the conclusion of the current DMA or SA cycles The logic necessary for DMA bus arbitration is contained in the DC010 A DMA request is made by asserting REQ H which generates BDMR L Afte
30. orary storage area utilized by a user routine Through the use of the CSR destructive bit it is possible to configure the SA memory so that incoming information either overwrites or adds to the present SA memory contents CHANHB H and CHANLB H are used in conjunction with TDIN H to generate DSTBHB H and DSTBLB H to latch the incoming data from the 151 11 bus into the DATOR DSTBHB H or DSTBLB H triggers the 200 ns SUMLD L pulse If DEST L is asserted SUMCLR L is also asserted so that the contents of the DATOR are added to zero If DEST L is negated SUMCLR L is not asserted and the contents of the DATOR are added to the contents 25 of the SA memory The trailing edge of SUMLD L clocks the 250 ns one shot to produce WP L and MACLK L which writes the result into the SA memory and clocks the MAC to the next memory location This continues until all the words are transferred and the DATI cycle terminates The SA memory may also be erased by setting the erase bit of the CSR which asserts ERASE H When ERASE H goes high it assets SUMCLR L SUMEN L and CS L which sets the SA MD bus to zero H also triggers SUMLD L which triggers the 250 ns one shot to produce WP L and MACLK L This writes zero into the current SA memory location and increments the MAC to the next location A 400 ns one shot is also triggered at the beginning of WP L which allows ERASE H to retrigger SUMLD L and repeat the above sequence of writing zero to memo
31. r the bus acknowledges the request the daisy chain signals BDMGI L and BDMGO L are used to determine the priority of the requesting device at which time the device becomes bus master control lines DATIN L DATIO L used to determine whether a DATI DATO or DATIO transfer is to take place For a DATI transfer DATIN L is set low and DATIO L is set high for a DATO transfer DATIN L is set high and DATIO is set high Fox a DATIO transfer DATIN L can be either high or low and DATIO L is set low When DATIO is asserted the falling edge of DATN H generates 70 pulse DATIOT L to the DCO10 to complete the output portion of the DATIO transfer 17 After every fourth word is transferred the bus 15 released for 1 2 microseconds to allow other devices to access the bus before bus mastership is regained and the transfer continues This feature be defeated by con necting CNT4 to 5V so that the device will transfer data in a continuous burst node Note that if this is done the memory refresh must be taken into account if volatile memory is being used 11 timing for the DC010 is provided by 8 MHz oscil lator 74LS132 Once the DC010 gains control of the bus it asserts ADREN H to the bus address register BAR to place the memory address of the data transfer on the SA data lines The BAR is loaded under program control with the starting address in memory of the data transfer and is incremented
32. rmat 2 When set L causes destructive read of memory during DOUT clears after read during DIN overwrites when set H causes non destructive readout During DOUT simple read during DIN does an add to SA memory No effect DATIO cycle 1 When set H starts the device 0 When H causes interrupt to set end of current SA cycle stops device 2 29 References L T Specht A Computer Based High Speed Digital Signal Averager M S Thesis University of Illinois May 1977 151 11 Microcomputer Handbook Digital Equipment Corporation Maynard 1978 User s Manual Digital Equipment Corporation Maynard MA 1979 Biomation 6500 Operating Manual Biomation Santa Clara CA 1978 6500 DATA BUS YOUT XOUT DATA BUS CONTROL LINES LSI 11 BUS Figure 1 Signal interface block diagram DSTBH LB H DZERO L SACYC H L ww 2 DATOR T A B ADDER SUM DATIR LATCH DATA BUS DATLD H SUMCLR L DATEN L SUMLD L SUMEN L Figure 2 Arithmetic logic unit section MEMORY 1K x 16 MA REGISTER MA COUNTER WP L CS L MACLK L NWOVF H MEMDSPLY H Figure 3 Memory section SACYC H 12 V BLANKING CIRCUI INVERTER MEMDSPLY H UIT Z BLANK BUS gt gt Figure 4 x y digital to
33. rminates For single precision transfers OWT H is asserted so that the double word flip flop is inhibited from being toggled by ADREN L Thus the sign bit and carry are ignored and the sum of the SA memory and main memory is truncated to 16 bits so that only 1024 words of main memory are needed for storage Note that overflows and underflows that may occur with single precision transfers are not corrected for during the transfer If a DATO transfer is requested setting the destructive bit of the CSR causes DEST L to be asserted which enables WP L to be asserted DATEN L is used to generate DATLD H which 24 loads the DATIR Since DZERO L is set the A adder input is zero and thus the DATIR is loaded with the unaltered contents of the SA memory DATEN L also asserts SUMCLR L and SUMEN L and triggers a 200 ns one shot which times out and triggers the 250 ns one shot to produce WP L L Since SUMCLR L and SUMEN L were both asserted this writes zero into the SA memory location from which the DATIR was loaded If the destructive bit of the CSR is not set then DEST L is negated and inhibits WP L Thus the contents of the SA memory are left unchanged during the transfer The SA may also be configured for a DATI cycle to trans fer data from the 151 11 to the SA This can be used for example to display on a scope acquired data that has been subsequently manipulated on by a user program or simply as a fast temp
34. ry This continues until all of the memory locations are cleared at which time RESET L is generated by the MAC and negates ERASE H to terminate the erase cycle The total erase cycle time is lt 1 millisecond 26 5 CONCLUSIONS Currently the SA interface is being used with an LSI 11 2 CPU using the RT 11 V3B operating system The total system configuration is depicted in Figure 20 Various MACRO and FORTRAN routines have been written for the device which pro vide most of the commonly needed such as SA handler SA command interpreter addition and subtraction of waveforms multiple waveform storage integration differentiation FFT curve fitting extended graphics package diagnostics and others as dictated by the user s needs The SA command inter preter allows all of the above features to be accessed inter actively through the keyboard via simple four letter mnemonics Additional commands can be readily incorporated into the SA command interpreter as the user s needs change Thus one has at their disposal a system that is both powerful and easy to use 27 Table I CSR OPERATIONAL STATUS BIT 15 14 1 3 12 T 10 DESCRIPTION 1 1 0 Sets H when 1 bus does not reply 10 us after addressed non existent address prevents bus hangup 2 attention is called for not device originated and a SA cycle or DMA cycle are not being processed if so it sets at cycle com pletion Normally att
35. sed from that which it is for any given waveform Typically the synchronized in time so that any coherent features that are addition is done digitally which necessitates the need to be able to digitally represent the original analog signal This is done by digitizing the analog signal at N time intervals of At each with an analog to digital converter ADC so that the total time sampled is NAt Thus for each sampled point the time resolution is defined by At and the amplitude resolution is determined from the number of bits in the ADC For fast signals the sampling interval At is usually too short for any type of real time processing so that some form of buffer memory is used to temporarily store the digitized waveform before it can be processed This combination of ADC sampling clock and buffer memory is referred to as a transient recorder For the Biomation 6500 transient recorder the main specifications are 1 minimum sampling interval of 2 ns 2 total of 1024 sampled points 3 ADC resolution of 6 bits and 4 maximum output rate for the stored waveform 1024 words of 6 bits each of 500 ns word As an aside one should note that the above restriction of non real time signal processing of fast signals can be eliminated by incorporating a transient recorder and signal averager into one integral unit The main impetus for real time processing is to obtain the maximum repetition rate possible since the SNR improv
36. the 3 state SA MD bus with the memory being abled by CS L Information is written into memory by applica tion of WP L The memory address MA is provided by the MA register 74LS374 which is loaded by MACLK L which also in crements the MA counter 7415393 to the next MA location When the MA counter reaches 1024 it generates 100 ns pulses NWOVF H and RESET L which reset the MA counter to zero The SA memory may also be reduced from 1024 words to 512 256 or 128 words by setting the memory size switch S1 to the appropriate position For displaying purposes the MA counter may also be continuously cycled at a l MHz rate by application of MEMDSPLY H see DAC section 13 4 3 Digital to Analog Converter DAC Figures 10 and 11 Two analog outputs XOUT and YOUT are provided for monitoring the contents of the SA memory on a x y oscilloscope XOUT is produced by applying the MA lines to the input of a 10 bit DAC AD561 which in turn drives a fast settling op amp AD509 This provides a full scale output of 5 00 V to 4 99 V for MA values of 0 through 1023 respectively YOUT is produced by applying the 9 LSBs and the inverted MSB sign bit of the SA MD bus to the input of another 10 bit DAC and op amp combination This provides a full scale output of 5 00 V to 4 99 V for SA MD bus values of 512 to 511 respec tively This output does not correct for rollover caused by the SA MD bus exceeding these values 12
37. um of the SA memory and the main memory The DATIR is then written back into the same location in main memory by DATEN L The next address is then placed on the bus by ADREN L which toggles the double word flip flop back again This inhibits the SB and COUT latches and gates their outputs to produce SUMCLR L and CIN and also negates CS L If a carry was produced by the previous addition then CIN is set high otherwise CIN is low Likewise if the SB was high for the previous addition indicating a negative number then SUMCLR L is not asserted otherwise SUMCLR L is asserted DATOR is then loaded by DSTBHB H and DSTBLB H with the contents of the second main memory location This is then x 23 added to the contents of the SA MD bus which is either all zeros positive add or all ones negative add together with the carry from the previous addition This result is then loaded into the DATIR by DATLD H and is written back into the same location in main memory by DATEN L to form the second half upper 16 MSBs of the 32 bit expanded word On the second word DATEN L is gated through to produce SUMCLR L SUMEN L and CS L At the same time it triggers the 200 ns one shot which in turn triggers the 250 ns one shot to produce WP L MACLK L which writes zero into the current SA memory location and increments the MAC to the next location This continues until all of the SA memory locations have been trans ferred and the DATIO cycle te
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