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PCI-EK01 Register Level Application Guide

1. Init Value Ox3E7h 999d 5 STATUS DAC STATUS Register Bit Position amp meaning 31 10 9 8 7 6 5 4 3 2 1 0 Reserved AQ FIFO Addess AO Bit Name Description Default Value 9 0 FIFO Represents the 10 bit FIFO address If Auto bit All Address of COMMAND register is 0 it represents the Write address If it is l it represents the Read address ADC output value 31 10 Reserved For future use All 0 2005 DAQ system all rights reserved http www daqsystem com D A Application Note AN203 SYSTEM PCI EKO1 Register Level Application Guide 11 Digital l O 82C55 Usage PCI EKO1 s Digital Input Output functions are implemented using the 82C55 In case of the 82C55 the peripheral device control chip of early Intel x86 family have been used Function T G Register Description AOh PORTA 82C55 Port A Register A4h PORTB 82C55 Port B Register 1 O0 82C55 S A8h PORTC 82C55 Port C Register ACh CONTROL 82C55 Control Register Write Only To control the 82C55 port it must be all setup through the control register For all setup the most significant bit will be set to 1 and writes to the control register If the most significant bit is 0 it is a command of PORTC bit description For more information refer to 82C55 manual When the first power all port will be
2. 2005 DAQ system all rights reserved http www daqsystem com D A Application Note AN203 SYSTEM PCI EKO1 Register Level Application Guide processing 5 Timer 1 If it is I the Timer 2 requests the Interrupt 0 processing 6 UART Reserved 0 7 VGA Reserved 0 8 ADC Reserved 0 9 DAC Reserved 0 10 8255 Reserved 0 11 Interrupt Reserved Q 12 EXTO Reserved 0 13 EXT1 Reserved SUS 14 EXT2 Reserved 0 15 Global When any of the above Interrupt sources need REN to process it will be changed 1 31 16 Reserved For future use All 0 When the interrupt processing ends the interrupt status bit for each corresponding bit should be cleared After the bit that want to be cleared write 1 the Interrupt status of corresponding bit is cleared After the bit that want to be cleared writes 1 the Interrupt status of corresponding bit is cleared Bit 15 is reset Reset so all status bits are cleared at the same time 2 INT_SEL Determines whether to an edge triggered or level triggered interrupt for each device that requires the interrupt processing INTERRUPT Select Register Bit Position amp meaning 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved M14 Interrupt Mode Mo The Interrupt mode selects until from
3. PD Low Active Power Down In other words if it is 0 the DAC is a low power mode In normal operation it should be always 1 A1 AO It is an address to select one of the four DAC A1 A0 DAC Output 0 0 DAC 0 011 DAC 1 1 0 DAC 2 111 DAC 2 In read operation it represents the value of the FIFO For more information refer to chip AD5324 manual 2005 DAQ system all rights reserved http www daqsystem com D A Application Note AN203 SYSTEM PCI EKO1 Register Level Application Guide 2 COMMAND DAC Command Register Bit Position amp meaning 31 7 6 3 2 1 0 Reserved M Reserved RII Bit Name Description Default Value U Auto If it is 1 Waveform generation works Down Q Counter At this time DAC value uses the internal FIFO 1 Int_en If it is 1 Interrupt Enable works Q When internal FIFO address value reaches the F Limit value Interrupt is generated Applied later It should be set always 0 2 Reset If it is 1 it initializes the DAC If it is 0 it 0 makes the normal operation mode When reset there was no change internal FIFO value but you can record DAC value from the beginning because of initialization of FIFO pointer 6 3 Reserved For future use LIT T Manual If it is 1 the value of DAC can be set for each GK channel by manual Refer t
4. SYSTEM PCI EKO1 Register Level Application Guide 1 PCI BUS Address Space As it uses CPU of the x86 system which we use mainly it can classify greatly it to memory and I O area In order to support Plug amp Play in case of PCI bus that has a special Configuration It can save the resource and device state control register etc 4G Memory Area 64K UO Area 64DWORD Configuration Area The PCI EKO1 use a memory and I O that have been assigned to system for operation the contents are as follows that they required Address Area Requirements Remark Memory Maximum 64MByte VO 256 Byte Configuration 128 Byte 2005 DAQ system all rights reserved http www daqsystem com D A Application Note AN203 SYSTEM PCI EKO1 Register Level Application Guide 2 PCI EKO1 Functional Block Diagram An area of assigned address in PCI EKO1 is used like Figure 3 3 All peripheral device s control and status register located in I O area only high speed SRAM located in memory area This can not be used in most applications because of allocation of resources for the system at boot time only in Configuration area ee PCI EK01 INTERNAL BLOCK FPGA oca BHS Local Bus Address Data Mem 1 0 Dr 0 z Counter 1 PCI T 0x10 Rig Counter 2 0x20 Timer 0 0x30 BUS Mux A w 1 H 1 1 1 H 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A
5. hardware SAM_CH indicates the channel number In SE mode bit 0 2 means three bits and bits 7 3 are available for up to add future capabilities In Differential mode bits O and 1 is meaningful only shows the channel number For example if you want to convert the hardware channel only O and 6 SAM_CHO0 2 4 6 will be written to 0 SAM_CH1 3 5 7 will be written to 6 If you want to convert all of the channels each SAM_CH will be written channel numbers that want to convert The conversion order follow in order to record the number 2005 DAQ system all rights reserved http www daqsystem com D A Application Note AN203 SYSTEM PCI EKO1 Register Level Application Guide 5 ADC Read Pointer Converted Chip ADC value is stored in the high speed RAM Two high speed RAM size is 1K 16 bit words Previously method stored in the external RAM is not used in version 1 1 There are continuously sampling in version 1 1 to read the ADC address value can be known the ADC read pointer to write the ADC pointer can be known the Status register ADC Read Pointer 31 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Read Pointer address 6 ADC_PRD ADC Sampling period register Bit Position amp meaning 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved D15 Sampling Period Value DO The maximum conver
6. meaning 31 16 15 14 138 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved R TA HC LC TP Reg_sel E TLoad AIDIOIM Bit Name Description Default Value U Manual If it is 1 it control the ADC by Manual 0 If it is O it is Free running lt Notice 1 gt 1 Operation I is Normal mode trigger 0 is Auto mode REN 2 DIFF If it is 1 it is a Differential mode If it is 0 it o is a Single Ended mode 3 AMODE Setup the Input Range to Analog mode 0 Refer to chip manual 6 4 Trg load Trigger pace load 000 T Ext External trigger Q 10 8 Reg sel Register select 000 11 Trg Pol Register select oLol lt 69 2 gt O 12 Low Clear Low RAM full clear write only 0 13 High Clear High RAM full clear write only 07 14 Trg arm Trigger Arm write only 0 15 RESET Initialize the ADC operation write only U 31 16 Reserved For future use All 0 Notice 1 Manual bit ADC values that converted to automatic mode are stored high speed RAM of internal chip The RAM is composed two 1024WORD 16 bit So total 2048 16 bit WORD is stored If the top level address of the internal RAM is stored it is saved by moving to the first address again the value of the data that was previously recorded will be lost Notice 2 reg_sel By reg_sel value of b
7. 16 Reserved For future upgrade All OQ 2005 DAQ system all rights reserved http www daqsystem com D A Application Note AN203 SYSTEM PCI EKO1 Register Level Application Guide 10 DAC Usage PCI EKO1 has 4 DAC Digital to Analog Converter The maximum update speed is 1M sapling sec output range is form O to 3 3V a resolution is 12 bit It has 1K word 16 bit FIFO for Waveform Generation function Function T fata Register Description 90h DATA 32Bit DAC data 94h COMMAND DAC Control command Register DAC 98h DIV_VAL DAC auto reload interval value 9Ch LIMIT_ADDR DAC auto reload buffer limit address Write only 9Ch STATUS DAC operation status Register Read only 1 DATA Data values that are written to the data register can be used Waveform generation in the automation mode by automatically written to the internal DAC output FIFO DAC Data Register Bit Position amp meaning 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved A1 A0 PD LD D11 DAC DATA DO DAC DATA DAC data of 12 bit resolution LD Low Active Load ADC In other words if it is 1 simply store the value of the data in the DAC buffer If it is 0 the value in the buffer outputs to the DAC Thus three DAC buffer record the value if the record at the same time the last to 1 four DAC value can be output
8. A Timer 1 0x40 C Timer 2 3 0x50 eee ees eee MEM Decoder To each IO Module w 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A Q a T gt sees e neee en w 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A eee eee CLOCK syn 10 82C55 Interrupt Oxa0 Controler Oxb0 4 Ext Address Data Control INT sources in Chip ed MEM Decoder 4 From Ext Note PCI EK01 A don t have these functions In the above picture PCI EKO1 A B is represented by the function block and dotted lines feature of PCI EKO1 A has not been implemented yet Notice UART or VGA functionality is available for future upgrades 2005 DAQ system all rights reserved http www daqsystem com DAQ SYSTEM 3 I O Address Usage The below table the address of the I O area indicates the base address of the peripheral device All I O registers are 32 bit input output processing Application Note AN203 PCI EKO1 Register Level Application Guide E Function Description Comment 00h Counter 0 32bit counter 0 10h Counter 1 32bit counter 1 PCI EK01 B Only 20h Counter 2 32bit counter 2 PCI EK01 B Only 30h Timer 0 32bit Timer 0 40h Timer 1 32bit Timer 1 PCI EK01 B Only 50h Timer 2 32bit Timer 2 PCI EK01 B Only 60h UART Universal asynchronous receiver tran
9. Auto reload mode Represents in terms of frequency are as follows Frequency 25M TMR_SET 1 When a time out output is 20nSEC pulse ALT 1 in Auto reload mode Represents in terms of frequency are as follows Frequency 50M TMR_SET 1 The TMR_SET value should be at least one or more Init Value OXFFFFFFFFh 2005 DAQ system all rights reserved http www daqsystem com D A Application Note AN203 SYSTEM PCI EKO1 Register Level Application Guide 3 COMMAND Counter COMMAND Register Bit Position amp Usage 31 cri els IT H T TD H Reserved Used Bit Name Description Default Value U Enable If it is 1 the Timer operates Down Counter 0 1 Clear If it is P the TMR_CUR value initializes 0 Ox00000000h 2 Auto If it is 1 the Timer value automatically reload RIN the TMR_SET value when the timer occurs time out 3 Alt If it is 0 the time out output value will be 0 inverted in every time time out occurs If it is 1 20OnSEC High Active Pulse is caused to Timer output when time out occurs 4 OutSel If it is 1 the time out output can be used as Q the general I O and this time output is OutVal If it is 0 send the one shot or reversed output with depending on the timer value 5 OutVal It is an output value when the time out output 0 can be used as the gen
10. D A Application Note AN203 SYSTEM PCI EKO1 Register Level Application Guide PCI EKO1 Register Level Application Guide Ver1 1 Windows Windows2000 Windows NT and Windows XP are trademarks of Microsoft We acknowledge that the trademarks or service names of all other organizations mentioned in this document as their own property Information furnished by DAQ system is believed to be accurate and reliable However no responsibility is assumed by DAQ system for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or copyrights of DAQ system The information in this document is subject to change without notice and no part of this document may be copied or reproduced without the prior written consent Copyrights 2005 DAQ system All rights reserved 2005 DAQ system all rights reserved http www daqsystem com Application Note AN203 DAQ SYSTEM PCI EKO1 Register Level Application Guide he o o N M M eM UN KA e KA b e O Contents PCI BUS Address Space PCI EKO1 Functional Block Diagram I O Address Usage Memory Address Usage Counter Usage Timer Usage UART Usage VGA Usage ADC Usage DAC Usage Digital I O 82C55 Usage Interrupt Controller Usage References 2005 DAQ system all rights reserved http www daqsystem com D A Application Note AN203
11. KO1 B model I O Address par Function Offset Register Description 70h Register 0 For future use 74h Register 1 For future use VGA 78h Register 2 For future use 7Ch Register 3 For future use 2005 DAQ system all rights reserved http www daqsystem com D A Application Note AN203 SYSTEM PCI EKO1 Register Level Application Guide 9 ADC Usage PCI EKO1 has 8 SE Single Ended ADC Analog to Digital Converter channels If it use Differential method it can be used 4 channels The maximum sampling speed is 200Ksps the input range is different to depending on the options the value is from O to Vref or from Vref 2 to Vref 2 Vref value is 2 5V it can select 3 3V A resolution is 12 bit READ POINTER ADC_PRD TRG_POS TRG_LEVEL CH_SELO CH_SEL1 CH_SEL2 CH_SELS3 is located in the same I O address however it can be accessed differently depending on the reg_sel value of COMMAND register Function T tas Register Description 80h DATA 32Bit ADC data Read Write 84h COMMAND ADC Control command Register Read Write 88h READ POINTER ADC FIFO READ Pointer Read only reg_sel 000 88h ADC_PRD ADC sampling period register Read Write reg_sel 001 88h TRG_POS Read H W Trigger position Read only reg_sel 010 ADC 88h TRG_LEVEL Set H W Trigger level Read Write reg_sel 011 88h CH_SELO ADC Channel Sel
12. alue Counter 0 08h COMMAND Counter Control Command OCh STATUS Counter Operation Status 10h CNT_CUR Current 32bit counter value 14h CNT_TAR Target 32bit counter value Counter 1 18h COMMAND Counter Control Command 1Ch STATUS Counter Operation Status 20h CNT_CUR Current 32bit counter value 24h CNT_TAR Target 32bit counter value Counter 2 28h COMMAND Counter Control Command 2Ch STATUS Counter Operation Status 1 CNT_CUR Save the current 32 bit counter value Init Value 0x00000000h 2 CNT_TAR The user set up 32 bit Counter value If set the counter value is greater than or equal to the current value a bit of the STATUS register will be displayed Init Value OXFFFFFFFFh 3 COMMAND Counter COMMAND Register Bit Position amp Usage 31 2 110 Reserved Use Bit Name Description Default Value U Enable In case of 1 should be Counter operation Q 1 Clear In case of 1 the CNT CUR value initialize 0 0x00000000h 31 2 Reserved For future use All Q 2005 DAQ system all rights reserved http www daqsystem com D A Application Note AN203 SYSTEM PCI EKO1 Register Level Application Guide 4 STATUS Counter STATUS Register Bit Position amp Usage 31 2 110 Reserved Use Bit Name Description Default Value U CNT_IN External counter pin indicates current port External status value 1 Over CNT_CUR va
13. bit O to 14 If it is O it is a Level Trigger If it is 1 it is a Edge trigger All bit is 0 by default 2005 DAQ system all rights reserved http www daqsystem com D A Application Note AN203 SYSTEM PCI EKO1 Register Level Application Guide 3 INT EN Each Interrupt source is to enable the Interrupt INTERRUPT Enable Register Bit Position amp meaning 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved G E14 Enable EO If each bit is 1 it is enabled the device Interrupt of corresponding bit Because bit 15 is the Global Interrupt Enable bit This bit is set 1 to enable all Interrupts 4 INT_SRC INT_STA register represents that each interrupt request output of the device is latched at the rising edge of the signal Thus it is the display of Edge triggered rather than Level triggered Therefore it requests and cleares the Interrupt On the other hand INT_SRC represents that the state of the current output request Interrupt device INTERRUPT Source Indicator Bit Position amp meaning 31 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved S14 Interrupt Source So 2005 DAQ system all rights reserved http www daqsystem com D A Application Note AN203 SYSTEM PCI EKO1 Register Level Application Guide References 1 AD7859 Data Sheet
14. ect register 0 Read Write reg_sel 100 88h CH_SEL1 ADC Channel Select register 1 Read Write reg_sel 101 88h CH_SEL2 ADC Channel Select register 2 Read Write reg_sel 110 88h CH_SEL3 ADC Channel Select register 3 Read Write reg_sel 111 8Ch STATUS ADC Status register Read only reg_sel 00 8Ch READ POINTER Set FIFO READ point Address Write only 1 DATA The data value written to the data register directly control the ADC chip which is connected 16 bit data bus of ADC chip through local bus on the board All I O and memory access of PCI EKO1 is 32 bit but upper 16 bit don t use it When the ADC chip was controlled by the manual ADC internal register can control to refer chip manual The most used command is OxEO10 this is command to convert to the SE mode for O channel After the conversion when a read operation on DATA register ADC conversion value can be read Refer to chip AD7859AS manual for more information ADC Data Register Bit Position amp meaning 31 16 1511411291191001 9181716181431210 Reserved D15 ADC Data Bus DO If you use an ADC chip as the manual the Manual bit of COMMAND register should be set ale 2005 DAQ system all rights reserved http www daqsystem com D A Application Note AN203 SYSTEM PCI EKO1 Register Level Application Guide 2 COMMAND ADC Command Register Bit Position amp
15. eral I O 6 Reserved For future use Q 7 Load If it is 1 the TMR_SET value will be loaded to Q TMR_CUR value If it is 0 the Timer can operate when the timer Enable set value is A 31 8 Reserved For future use All Q 2005 DAQ system all rights reserved http www daqsystem com D A Application Note AN203 SYSTEM PCI EKO1 Register Level Application Guide 4 STATUS Counter STATUS Register Bit Position amp Usage 31 1 0 Reserved Use Bit Name Description Default Value U TimeOut When time out occurs TMR_CUR value is 0 ellie it will be 1 31 1 Reserved For future use All OQ 2005 DAQ system all rights reserved http www daqsystem com DAQ lt r Application Note AN203 PCI EKO1 Register Level Application Guide 7 UART Usage This feature is not currently implemented it will be supported to PCI EKO1 B model UO Address ae Function Offset Register Description 60h Register 0 For future use 64h Register 1 For future use UART 68h Register 2 For future use 6Ch Register 3 For future use 2005 DAQ system all rights reserved http www daqsystem com DAQsyscem Application Note AN203 PCI EKO1 Register Level Application Guide 8 VGA Usage This feature is not currently implemented it will be supported to PCI E
16. he Status register bits 10 0 of the program by setting the read pointer is to be read in a specific address 2005 DAQ system all rights reserved http www daqsystem com D A Application Note AN203 SYSTEM PCI EKO1 Register Level Application Guide 4 CH_SELO 1 2 3 When ADC operates the Hardware SCAN AUTO mode specific channel that want to get an analog value can convert selectively This function is available through the Channel Select register Each Channel Select register store the sampling channel number from 0 to 7 Sample order is performed repeatedly from SAM_CHO to SAM_CH7 Currently only the lower three bits of each sample channel is used ADC CH SELO Register Bit Position amp meaning 31 16 EIS 14 93 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SAM_CH1 SAM CHO ADC CH SEL1 Register Bit Position amp meaning 31 16 KIS 14 93 12 11 10 9 8 7 6 5 4 38 2 1 0 Reserved SAM_CH3 SAM_CH2 ADC CH SEL2 Register Bit Position amp meaning 31 16 15 74 93 42 11 10 9 8 7 6 5 4 38 2 1 T Reserved SAM_CH5 SAM_CH4 ADC CH SEL3 Register Bit Position amp meaning 31 16 15 14 93 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SAM_CH7 SAM_CH6 The structure of the 8 bit
17. input and the operation mode will be 0 Group A Control Bits Group B Control Bits fe a Definition of input 0 Output output of low order 1 Input 4 bits of port C Definition of input D lt Output output of 8 bits of 1 Input port B Mode definition of 0 Mode 0 group B 1 Mode 1 Definition of input E output of high order fe ot 4 bits of port C Definition of input 0 lt Output output of 8 bits of 1 Input porta Mode definition of group A Control word Identification flag Be sure to set 1 for the contro word to define a mode and input output ine set to 0 it becomes the control word for bit set reset 2005 DAQ system all rights reserved http www daqsystem com D A Application Note AN203 SYSTEM PCI EKO1 Register Level Application Guide 12 Interrupt Controller Usage PCI EKO1 has the interrupt controller for each I O device by using hardware When you use these interrupts overhead of the process can be reduced r UO Address R Function Offset Register Description BOh INT_STA Interrupt Status Register Read Interrupt Status Clear Write B4h INT_SEL Interrupt Select Read Write INTERRUPT B8h INT_EN Interrupt Enable Register Read Write BCh INT_SRC Interrupt Source Indicatior Read Only To control the 82C55 port it must be all setup through the control register For all setup the most significant bit will be
18. it 10 8 reading writing changes to a specific register at I O offset address 88h The table below shows the Register value selected by the reg_sel For example to write a value to CH_SELO reg_sel record 100 When read write 88h read write to CH_SELO 2005 DAQ system all rights reserved http www daqsystem com D A Application Note AN203 SYSTEM PCI EKO1 Register Level Application Guide Reg_ sel Selected Register 000 Read Pointer 001 ADC_PRD 010 TRG_POS 011 TRG_LEVEL 100 CH_SELO 101 CH_SEL1 110 CH_SEL2 111 CH_SEL3 3 STATUS ADC indicates the operating status ADC STATUS Register Bit Position amp meaning 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved B ITD HFILFITA ADC FIFO Pointer Bit Name Description Default Value 10 0 FIFO Ptr Represents the ADC FIFO Pointer Read 0 Read pointer is set to high speed RAM Write lt Notice 1 gt 11 Trg Arm If it is 1 wait for Trigger occurrence Q 12 Low Full If it is 1 full lower RAM 0 13 High Full If it is 1 full upper RAM Q 14 Trg Done If it is 1 Trigger done U 15 Busy If it is 1 represents the ADC operation 0 31 16 Reserved For future use All 0 If it has write operation to t
19. lue is greater than or equal to 0 CNT_TAR value it will be 1 31 2 Reserved For future use All 0 2005 DAQ system all rights reserved http www daqsystem com D A Application Note AN203 SYSTEM PCI EKO1 Register Level Application Guide 6 Timer Usage PCI EKO1 can use the three 32 bit Timer The timer use 50MHz clock on the board the resolution can be set in units 20nSEC Therefore from the minimum 40nSEC up to maximum 85 899 345 900nSEC about 86 seconds can be set I O Address een Function Offset Register Description 30h TMR_CUR Current 32bit Timer value 34h TMR_SET Setted 32bit Timer value Timer 0 38h COMMAND Counter Control Command 3Ch STATUS Counter Operation Status 40h TMR_CUR Current 32bit Timer value 7 j 44h TMR_SET Setted 32bit Timer value imer 48h COMMAND Counter Control Command 4Ch STATUS Counter Operation Status 50h TMR_CUR Current 32bit Timer value 54h TMR_SET Setted 32bit Timer value Timer 2 58h COMMAND Counter Control Command 5Ch STATUS Counter Operation Status 1 TMR_CUR The current 32 bit Timer value is stored The Counter is Down Counter If all bit is 0 a timeout occurs This can be found in the status register Init Value 0x00000000h 2 TMR_SET The user set the 32 bit Timer value Set the Timer value is loaded to TMR_CUR register When a time out output is reversed ALT 0 in
20. o Data Register 31 8 Reserved For future use All 0 Reference If Divide is 0 the period of DAC update is 1uSEC If it is 1 it depends on DIV_VAL value Notice If the actions were changed from automatic mode to manual mode the reset operation must be once operation 3 DIV_VAL If DIV_VAL is 0 the period is 2uSEC If it is 1 it is 4uSEC If it is 2 it is 6buSEC If it is 3 it is 8uSEC That way it represents equation update cycle is 2uSEC x DIV_VAL 1 DAC DIV VAL Register Bit Position amp meaning 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved D11 Divide Value DO Init Value OxOOOOh 2005 DAQ system all rights reserved http www daqsystem com D A Application Note AN203 SYSTEM PCI EKO1 Register Level Application Guide 4 LIMIT_ADDR If you create the Waveform by using internal FIFO a specific address should be move first address in order to make any periodic Waveform Limit Address are to be used for this In other words if you only create a waveform at FIFO address from O to 233 and then LIMIT_ADDR value records 233 after that the DAC will be output only to address 233 and move to the first address 0 DAC LIMIT_ADDR Register Bit Position amp meaning 31 10 9 8 7 6 5 4 3 2 1 0 Reserved AQ FIFO Address limit value AO
21. s Rev A Analog Device Inc 2 AD5304 53 14 5324 Data Sheets Rev D Analog Device Inc 3 PCI EK01 A B User s Manual DAQ system 4 82C55 chip manual Intel corp 2005 DAQ system all rights reserved http www daqsystem com
22. set to 1 and writes to the control register If the most significant bit is 0 it is a command of PORTC bit description For more information refer to 82C55 manual When the first power all port will be input and the operation mode will be 0 1 INT_STA Interrupt Status Indicates devices that are currently required Interrupt To appear in the status register will have to make the handle Read The Status bitINT_STA of each devices that require the Interrupt are eliminated Write The interrupt handling device that requires a bit of a write operation must be one and the corresponding status bit is cleared Edge triggered Interrupt For level triggered interrupt request for each device must be cleared directly INTERRUPT Status Register Bit Position amp meaning 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved G S14 Status SO Bit Name Description Default Value U Counter O If it is 1 the Counter O requests the Interrupt 0 processing 1 Counter 1 If it is 1 the Counter 1 requests the Interrupt Q7 processing 2 Counter 2 If it is 1 the Counter 2 requests the Interrupt 0 processing 3 Timer 0 If it is I the Timer O requests the Interrupt 0 processing 4 Timer 1 If it is I the Timer 1 requests the Interrupt 0
23. sion rate of the ADC is 200KSPS 5uSEC cycle If the ADC_PRD value of O 1 it is successively ADC conversion by the maximum speed However if ADC_PRD has a another value than not or 1 it can be used by decreasing sampling speed period In case of 2 sampling period is 7 5uSEC in case of 3 sampling period is LOuSEC the sampling period represented by the equation is as follows Sampling Period 5 0uSEC ADC_PRD 1 x 2 5uSEC When the ADC_PRD values O and 1 the maximum sampling period of the exception is 5 0uSEC 7 Trigger position When H W Trigger occurs ADC address value is stored Future Function ADC Trigger position Register 31 11 10 9 8 7 6 5 4 3 2 1 0 Reserved H W Trigger position 2005 DAQ system all rights reserved http www daqsystem com D A Application Note AN203 SYSTEM PCI EKO1 Register Level Application Guide 8 Trigger control H W trigger level can be set Future Function ADC Trigger Level Register 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SL TRG_CH H W Trigger position Bit Name Description Default Value 11 0 Trigger Set the trigger level Q Level 14 12 TRG ch Set the channel of the trigger 000 15 Slope If it is O it is a rising edge If it is 1 it is a REI falling edge 31
24. smitter RS232C PCI EK01 B Only 70h VGA VGA Display PCI EK01 B Only 80h ADC Analog to Digital converter 90h DAC Digital to Analog converter AOh I O 8255 Digital Input Output 82055 Boh Interrupt Interrupt controller BOh FFh Reserved Reserved space for future upgrade 4 Memory Address Usage Only high speed SRAM is located in the memory area memory area is always 32 bit input output The memory is 32 bit processing in the PCI EKO1 A the lower 16 bit is only memory value the upper 16 bit is only displayed 0 PCI EKO1 B is 32 bit Memory read write can operate up to maximum 33M cycles Memory Address fart Sones Model Description Comment Oh 100000h PCI EK01 A 16Bit Bus width High 16bit space is not used Total 512K Byte Oh 100000h PCI EKO1 B 32Bit Bus width Total 1M Byte 2005 DAQ system all rights reserved http www daqsystem com D A Application Note AN203 SYSTEM PCI EKO1 Register Level Application Guide 5 Counter Usage PCI EKO1 can use three 32 bit counter can be reduced the overhead of the program in 16 bitcounter The counter is increased rising edge of the counter LOW gt HIGH Transition the interface is a 3 3V CMOS logic levels The maximum count frequency is 20Mhz UO Address E Function Offset Register Description 00h CNT_CUR Current 32bit counter value 04h CNT_TAR Target 32bit counter v

PCI-EK01 Register Level Application Guide

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