EVBUM2148 - ON Semiconductor
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1. discharged while powering down the converter If the capacitor remains charged after power down it may damage the converter First the resonant tank between Celamp and Lmac used for ZVS during normal operation will continue to resonate after power down as long as energy is stored in the capacitor Second a long reset time is applied to the transformer during power up as duty ratio slowly increases from 0 If the capacitor is charged during power up the maximum V sec of the transformer may be exceeded This will push the transformer far into the third quadrant of the B H curve possibly saturating the transformer The NCP1562 solves these problems by using a novel approach called soft stop Soft stop reduces the duty ratio until it reaches 046 prior to turn off Duty ratio is reduced by discharging the capacitor on the SS pin using a 90 uA current source The voltage of the clamp capacitor is given by Equation 42 It can be observed that the clamp capacitor voltage will approach zero as duty ratio approaches zero Vin 3 D 1 D Empirically it is determined that a 0 1 uF is sufficient to discharge the clamp capacitor under all operating conditions The worst case condition for soft stop is light load at high line During this condition Vga is at its lowest making the achievable soft stop time a minimum for a given capacitance Figure 21 shows the drain of the main switch during power down at high line and no load As expected soft stop provide2. including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PU
3. 0 2 4 6 8 10 12 14 16 18 CLAMP CAPACITANCE nF Figure 6 Vps ripgie and Normalized Peak Flux vs Cclamp The magnetizing current charges and discharges the active clamp capacitor every cycle and is given by Equation 4 gt Vin D MAG fsw LMAG It is absolutely critical to consider the ripple current rating in the selection of Celamp Otherwise the capacitor may overheat The minimum ripple current rating of Celamp is determined by the magnetizing rms current Assuming the magnetizing current reverses direction halfway during the off time the clamp capacitor rms current is approximated by Equation 5 eq 4 Wm DH 1 D l eq 5 Cclamp rms Foy LMAG 2 eq 5 The worst case condition is at high line Using the Design Tool an rms magnetizing current of 0 294 A is calculated A ceramic capacitor is preferred due its low equivalent series resistance ESR TDK s C3216X7R2J103M is used Although maximum drain voltage of this design is 150 V a 630 V capacitor is used as it is readily available Output L C Filter The output L C Lout Cout filter averages the square wave signal at the transformer output The output inductor Lout is sized such that it operates in continuous conduction mode at the minimum output current lou mig using Equation 6 Sw eq 6 where D min is the minimum duty ratio Solving Equation 6 3 3 449271 23 7 using the D min provided by the Design Tool a minimum inductance
4. D 179 eve D I 20808 ANV The om A DCH GE D rz 3 SCH g L doo ob X Ls A so en Vo vo PL OSw 0S4 3 v Ler ATL T D Le 8 Xv Ls 99 60 r Kz nina oss 1 9a z Ger ER Lee EI PA vleasw 2 N zs a L szd gt AW T NN y Kz lame oss szw 5 D Eai D ea uedo E sszem sve zu P ECH ii AOL ery ou vo szo vo E 89 KG E VZ9SLdON 8H ER ea ei E ae A Ee Zen Fee gt qi dog uedo SCH DNAS E zuo KS b D ae 19 5 dbiso an9 AN ji zu s P E mei D en sre zano so LX es 9500 x92 3 I pa mm 539 osy szo oza g wo A dios d vzo E M C 19 Sum k d t ras A wale 2a ajoja g uno om Fy apu SEH 3 a akil a n m loo Wr ze 61H N60ZtSJINLN uge zz 001 door 7 R 912 vu zu Td 8 oa uo oz L AAA T D een z f i 9 lt so u vo s L s were ED e e xo 1 ezo Di D a tx 5 ory 302i Ws E 2 S La z D L A p 2 x ta XAYA ird NeOZVSJIWLN S Sr i Ak 5 100 gt AM r xor f z I ilb Tr Siu puta S ARF 3 PIN sa E D 920 e I vr E D os ost ost zw A To 2 g CG 6 1 e ga zr g g F F io oz Tea Tea ato ae EI 9x ER La Sx S Se PRA zou 2z f E oz lee e st ole o o eza e e t 7 4 4 T 4 e A 4 4 4 e z Has n er A A I n monede LY Md 23s Nz ly ly o Dt F F za S 010 zo ieo rl6asWn UR EC Ahhh 1 xnv s9919 za Hno 89 IL 1 Figure 28 Circuit Schematic onsemi com http 16 NCP1562 100WGEVB Table 3 BILL OF MATERIAL FOR THE NCP1562 EV
5. continued Manufacturer Substitution Lead Designator Qty Description Value Tolerance Footprint Manufacturer Part Number Allowed Free 80 mils Mill Max 3231 2 00 34 00 00 08 0 N A Payton 51665 TSSOP 16 ON Semiconductor NCP1562ADBR2G PS2703 1 M A Transformer PWM Controller N A N A N A No Yes Shunt Reference N A SOT 23 ON Semiconductor TLV431ASNT1G MOSFET 30 V 104A SO8 FL ON Semiconductor NTMFS4835NT1G SOT 23 3 ON Semiconductor BC817 25LT1G NPN Transistor BC817 25 PNP Bipolar BC807 25 SOT 23 3 ON Semiconductor BC807 25LT1G Transistor The converter performance is evaluated and compared to 40 180 our original goals The evaluation criteria includes jas 1 Open loop frequency response 0 2 Efficiency 20 Simulated Phase 90 3 Line and load regulation a 4 Step load response m 10 Measured Gain 45 e 5 Output voltage ripple 3 0 0 D The open loop response is measured injecting an AC z ET Measured F hase Jaen signal across R19 using a network analyzer and an isolation transformer as shown in Figure 29 The open loop response 20 Simulated Gaint 790 is the ratio of B to A 30 135 Lout e 1 10 100 To Converter lt FREQUENCY kHz Figure 30 Measured and Calculated Open Loop Frequency Responses The full load efficiency of the converter is measur
6. poles and zeros are listed in Table 2 The simulated open loop frequency response is shown in Figure 15 The simulated frequency response does not show the complex zeros or Pio Ac as they are dependent on the operating conditions Table 2 SYSTEM POLES AND ZEROS Parameter Frequency kHz 5 6 200 Magnitude dB P1 2 LC Z ESR P1 2 AC Gmop Gopto hitp onsemi com 10 NCP1562 100WGEVB 50 0 40 20 30 40 amp 20 60 w 10 80 d 0 100 10 120 20 140 30 160 40 180 50 200 0 01 0 1 1 10 100 FREQUENCY kHz Figure 15 Simulated Open Loop Frequency Response The maximum achievable bandwidth is limited by Pi2 AC at low line Therefore the system crossover frequency fco should be set lower than p1 2 ac In this design fco is set at 20 kHz Several EA configurations are available A type II error amplifier as the one shown in Figure 16 is used in this design as it provides adequate phase margin A type II error amplifier has 2 poles and 2 zeros The first pole is at the origin The frequency of the remaining pole and zeros are calculated using Equations 33 through 35 Vout v R19 R20 C25 R30 EA Vref EA Figure 16 Type Il Error Amplifier 1 fp2 33 P2 2x C29 R21 R30 PS 1 fz1 2n C29 R21 eq 34
7. sets the minimum capacitance to comply with the capacitor input ripple current rating Additional capacitance may be needed to insure the system is stable over the complete operating range The input filter is implemented using a 1 5 uH inductor with four 2 2 uF capacitors in parallel Figure 10 shows the L C filter output impedance and the approximated converter input impedance over frequency obtained with the Design Tool As the capacitor ESR changes over frequency the ESR at the filter corner frequency is used for the analysis 50 40 30 20 Input Filter IMPEDANCE dBQ o 0 1 1 10 100 1000 FREQUENCY kHz Figure 10 Input Filter Output Impedance and Approximated Converter Input Impedance TX1 NCP1562 OUT1 OUT2 In general if the system oscillates the input filter output impedance can be decreased as in most cases the converter input impedance is dictated by the system specifications This can be accomplished adding a damping network Synchronous Rectification Low output voltage converters require synchronous rectification to achieve high efficiency If a diode is used for rectification the forward voltage drop becomes a significant portion of the output voltage thus severely affecting the efficiency The active clamp topology lends itself for synchronous rectificatio
8. 4 mQ The value of the sense resistor is set at 33 mQ The NCP1562 incorporates a 75 ns leading edge blanking circuit to mask the leading edge spike of the current signal The evaluation board also provides external blanking time using a simple RC low pass filter comprised of R10 and C11 The cutoff frequency of the low pass filter is selected several orders of magnitude greater than the operating frequency to Rsense eq 38 avoid distortion of the current sense signal The value of R10 is set at 100 Q and C11 is set at 100 pF The complete current sense circuit is shown in Figure 19 Main Switch R10 To CS Pin gt Figure 19 Current Sense Circuit The converter enters the cycle skip current mode if a continuous over current condition is exists Once a current limit event is detected a 90 uA current source begins charging the capacitor on the CSKIP pin If the capacitor charges to 3 V the converter enters a soft stop mode A cycle skip period of 330 us is set with a 0 01 uF capacitor Under and Over Voltage Detector The NCP1562 facilitates design by incorporating tightly controlled undervoltage UV detector In addition it incorporates an independent overvoltage OV detector in the same pin The pin is biased using a resistor divider as shown in Figure 20 Vin v R1 To UVOV Pin C16 R4 Figure 20 UVOV Bias Circuit The minimum operating voltage of the system is controlled by comparing the voltage on t
9. ALUATION BOARD Designator Qty Description Value Tolerance Part Number Allowed Free m DI Les oc p me o sr Lomp Is ve es es es es Ce s es es s Yes e e f f 7 Resistor 10 kQ 1 0805 Vishay CRCW080510KOFKEA Yes es es o es o es es Ye 1 Ye 1 Ye ojojo Si o ojojo o Ye Ye Ye o o ol o Y N Coilcraft DO1606T 105MLB Y ci ca 4 Capacitor 2 2 uF 100 V 2096 TDK N Capacito 1 000 pF 50 V 596 Vishay Ye C6 C8 C9 es Capacito 100 nF 50 V 1096 0805 Vishay VJOB05Y104KXAAT Y C28 Yes Yes Capaci 300 pF 50 V VJ0805A301JXAAT o N A N A A 0 l o e Yes Yes Yes C13 C16 Capaci 10 nF 50V VJO805Y 103KXAAT Yes Yes C14 Capaci 18 nF 50V VJ0805Y183KXAAT Ye es Yes es Yes TDK C17 C18 Capaci 47 uF 6 3 V 3225 TDK C3225X5R0J476M Ye C19 C21 Capaci 150 uF 6 3 V Custom Kemet T520B157M006ATE045 No Yes C22 C31 Capaci 47 uF 16 V Custom Vishay 595D476X9016C4T No Yes 0 1 uF 100 V 3216 T C3216X7R2A104K Ye DK es Yes Yes Yes 10 nF 630 V 20 3216 TDK C3216X7R2J103M Capaci 2 200 pF 2 kV 1096 4532 TDK C4532X7R3D222K Yes Yes 27 pF 50 V 0805 VJOB05A270JXAAT POWERMI ON Semiconductor MBRM120ET1G TE N A Yes Yes SOD123 ON Semiconductor MMSD914T1G 40 mils Mill Max 3103 2 00 21 00 00 08 0 J1 J2 J5 3 Pins N A http onsemi com 17 NCP1562 100WGEVB Table 3 BILL OF MATERIAL FOR THE NCP1562 EVALUATION BOARD
10. BLICATION ORDERING INFORMATION LITERATURE FULFILLMENT Literature Distribution Center for ON Semiconductor P O Box 5163 Denver Colorado 80217 USA Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Email orderlit onsemi com N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com USA Canada Europe Middle East and Africa Technical Support Phone 421 33 790 2910 Japan Customer Focus Center Phone 81 3 5817 1050 Order Literature http www onsemi com orderlit Sales Representative EVBUM2148 D For additional information please contact your local
11. Equation 12 l 2 IP RMS q rex IP PK IP VL d D eq 12 The turn on switching loss of the main switch is approximated by Equation 13 VDS IP VL tSW on fs w PSW Qmain 6 eq 13 where Vps is the drain voltage at which the main switch turns On tsw on is the switch turn on time The main switch turn off switching losses are very small and are ignored In an active clamp converter the main switch achieves Zero Volt Switching ZVS under specific operating conditions ZVS is affected by input voltage and output load Even if ZVS is not achieved reduced voltage switching is obtained As a first approximation the input voltage is used as the switch voltage at turn on for our calculations The capacitance at the drain voltage should be minimized to facilitate ZVS That includes the main and active clamp switches output capacitance Coss and transformer capacitance Therefore Coss should also be considered in addition to the typical Rps on and gate charge parameters for the selection of the main switch Fairchild s FDD2582 is selected for this design as it provides the best tradeoff between Rps on and Cogs It is a 150 V N channel MOSFET with an Rps on of 58 mQ Using the Design Tool the power dissipation of the main switch at high and low line assuming a 50 ns turn on time is calculated to be 1 49 W and 1 56 W respectively Power dissipation of the main switch is dominated at low line by conductio
12. NCP1562 100WGEVB NCP1562 100 W 48 V DC DC Converter Evaluation Board User s Manual Introduction The NCP1562 PWM controller contains all the features and flexibility needed to implement an active clamp forward dc dc converter This IC operates from an input supply up to 150 V thus covering the input voltages usually found in telecom datacom and 42 V automotive systems One can also note that the NCP1562 can be used in mains related applications e g desktop server flat TVs as it can be supplied by an auxiliary power supply The NCP1562 is the ideal choice for new generation isolated fixed switching frequency dc dc converters using the active clamp topology with synchronous rectification to achieve extremely high conversion efficiency This controller will help designers cope with their daily challenge small form factor highly protected module through the following features Dual Outputs with Adjustable Overlap Delay provide design flexibility Output 1 OUT1 drives the main switch in a forward or flyback converter topology Output 2 OUT2 can be used to drive an active clamp reset switch a synchronous rectifier switch or both OUT2 has an adjustable overlap delay to prevent simultaneous conduction of the switching elements Soft Stop discharges the active clamp capacitor prior to turn off to eliminate unwanted oscillations An Internal Startup Regulator provides power to the NCP1562 during startup Once the syst
13. Power Supply Maximum voltage rating of 85 V and maximum current rating of 4 A 3 Multimeters Maximum current rating of 10 A and maximum voltage rating of 100 V Electronic Load with current display and maximum current capability of 35 A Oscilloscope Test Procedure 1 Configure Multimeter 1 MM1 for measuring current Connect Power Supply terminal to MM1 current measurement terminal 2 Connect MM1 ground terminal to evaluation board Vin terminal 3 Connect Power Supply terminal to evaluation board Vig terminal hitp onsemi com an N oo Nel 10 1 12 13 NCP1562 100WGEVB Configure Multimeter 2 MM2 for measuring voltage Connect MM2 voltage measurement terminal to evaluation board Vout terminal Connect MM2 ground terminal to evaluation board Vout_ terminal Verify MM2 terminals are connected to evaluation board terminals Connect electronic load EL to evaluation board output Connect EL terminal to evaluation board Vout terminal Connect EL terminal to evaluation board Voyt_ terminal Set load current lout to 0 A Configure Multimeter 3 MM3 for measuring voltage Connect MM3 voltage measurement terminal to evaluation board Vout terminal Connect MMG ground terminal to evaluation board Vout_ terminal Verify MM3 terminals are connected to the evaluation board terminals and not electronic load terminals Otherwise the
14. Transformer A power transformer TX1 is used to step down the voltage and provide voltage isolation between the input supply and the load The transformer in this design has three windings primary secondary and auxiliary Contrary to a traditional forward transformer an active clamp transformer is designed with low magnetizing inductance The stored magnetizing energy is used to discharge the drain capacitance and facilitate ZVS as explained earlier In addition Lmag affects the loop response as it affects a pair of complex zeros introduced by the active clamp stage It is discussed later in the feedback loop section The input to output voltage relationship is described by Equation 2 Vin VDS on Vout N on where N is the primary to secondary turns ratio Vps on is the voltage drop across Qmain V QREC is the voltage drop across Oppe D is the duty ratio and Vin is the input voltage Equation 2 is used to select N given a target maximum duty ratio An additional factor to consider in the selection of N is the drain voltage of the main switch Vps during the off time as it depends on the duty ratio Equation 3 shows the relationship between Vps and D Vin VDS SE eq 3 The NCP1562 Excel based design tool downloadable from http www onsemi com provides an easy way to evaluate the interaction between the turns ratio duty ratio and maximum drain voltage as shown in Figure 5 The drain voltage is almost constant ov
15. V P channel MOSFET with an on resistance of 2 4 Q Only conduction losses are considered for the power dissipation of the active clamp switch Solving Equation 11 hitp onsemi com 6 NCP1562 100WGEVB a power dissipation of 0 58 W is calculated for a Ty max of 79 C The designer may be tempted to use a lower on resistance switch to reduce conduction losses However this may counterproductive The active clamp switch has to turn off quickly to divert the magnetizing current and discharge the drain capacitance to achieve ZVS If not the magnetizing current will keep flowing through the switch preventing the drain capacitance to be discharged and achieve ZVS A larger active clamp switch will have lower conduction losses but may increase switching losses on the main switch if ZVS is affected The low side active clamp circuit is easier to implement as it is compatible with a ground referenced gate drive signal However it requires a negative voltage to turn on the P channel MOSFET It is generated using a level shift circuit as the one shown in Figure2 Active clamp forward converter It consists of a diode and an ac coupling capacitor Cc The ac coupling capacitor is selected using Equation 15 V pv 1 D D AVC RGS tow QG 15 Es eq 15 Cc where Og is the total gate charge of the switch Vpgy is the gate drive voltage AVc is the gate voltage ripple should be 10 Vpgy and Rags is the gate to source res
16. d later in the Feedback Loop Section For this design Cout is set at 544 uF using a parallel combination of tantalum capacitors for bulk capacitance and ceramic capacitors for Resp reduction Main Switch A MOSFET is used as the main switch Several factors including current voltage stress and power dissipation are considered for the MOSFET selection The shape of the primary current is shown in Figure 8 It consists of the primary magnetizing and reflected output currents The valley of the primary current Ip yr is approximated to the inductor current divided by the turns ratio In practice Ipyr is slightly less as the magnetizing current starts negative due to the resonant transition But it is a good approximation as the magnetizing current is significantly smaller than the reflected output inductor current IMAG Y IP Pk lout N IP vL Y 9 al pt T4 Figure 8 Primary Current Waveform The primary peak current Ip pk is given by Equation 10 The maximum Ip pk occurs at high line when the output inductor ripple current is at its highest lout 4 Eu Vp D IP PK N n LMAG fsw The main switch experiences conduction and switching losses The conduction losses are given by Equation 11 eq 11 eq 10 Pcon IP rms RDS on where Rps on is the switch on resistance and Ip rms is the primary rms current The primary rms current is given by
17. derations and benefits provided by the active clamp topology as described below 1 Facilitates zero volt switching ZVS or low voltage soft switching of the main and active clamp switches 2 The ability to operate above 5046 duty ratio with a high turns ratio without a penalty on drain voltage 3 A high turns ratio reduces a The reflected output current component on the primary side allowing the use of a smaller Qmain b The secondary voltage allowing the use of lower voltage rectification elements 4 Lower output inductance is required due to the higher duty ratio 5 Signals for driving a synchronous rectifier are readily available The operation of the active clamp forward is discussed in detail with the use of Figure 4 This figure shows the power stage waveforms of an active clamp forward converter in steady state One switch cycle is divided in several time intervals to facilitate the analysis OUT1 OUT2 VDS lQ main IP t2 BER tO t1t3 t4 t5 t6 Figure 4 Active Clamp Forward Waveforms Time interval t0 tl The main switch turns on at t0 The active clamp switch remains off The primary current Ip flows through the transformer and the main switch This current is the sum of the transformer magnetizing Imac and reflected secondary currents No current flows through Qclamp and current flows in the secondary side through the forward rectif
18. ductor NCP1562 Active Clamp V Mode Rev 3B e x Si Ca x a Ae L jo 99 cio LS n a g OX M C20 1 NI 1X6 CR 4 BE t D 3 4 5 o neunid A9 NOYA s m 21 7 EM m 1090 ae 092 z98 9 1N3lvd J LE ATUM 00507 SO9IS N d cr 27 P an Figure 1 NCP1562 Evaluation Board Publication Order Number EVBUM2148 D NCP1562 100WGEVB DESIGN SPECIFICATIONS The flexibility of the NCP1562 is demonstrated by examining a detailed design of a dc dc converter for the telecom system The converter delivers up to 100 W at 3 3 V The converter specifications are listed in Table 1 A forward active clamp topology is selected for the converter as it provides very high efficiency Table 1 DESIGN SPECIFICATIONS Parameter Su ege xw Tele Frequency ET 350 typ Full Load Efficiency n 96 90 Duty Ratio 6596 Output Voltage Vout V 3 267 3 333 Output Voltage Ripple Vout rip mV 50 Output Current lout m 3 30 DU Power Le 100 Derating Factor DCN NCP1562 OUT1 OUT2 Active Clamp Forward Topology The active clamp forward ACF topology has multiple advantages compared to a traditional forward converter The benefits of the active clamp topology can be easily maximized once the unique characteristics of this topology are fully understood Figure 2 shows a simplified schematic of an active clamp forward topology The transformer model TX1 con
19. e Error Amplifier Voltage Reference The error amplifier reference voltage Vref ga is generated using ON Semiconductor s TLV431 as shown in Figure 18 d Vref EA Figure 18 Error Amplifier Reference Voltage The error amplifier reference voltage is set at 3 3 V using R27 and R28 This eliminates the need of a bias resistor between the EA inverting input and ground The voltage across R28 is regulated at 1 25 V by the TLV431 Assuming a bias current Ibias of 500 uA R28 is set at 2 49 KQ Resistor R27 is set by calculating the difference between Vregga and 1 25 V and dividing it by http onsemi com 11 NCP1562 100WGEVB Ibias It is set at 4 22 KQ Capacitor C5 provides noise immunity for Vreta It is set at 1 000 pF The maximum voltage of either A or B provides the voltage supply for the EA and the TLV431 Signals A and B are taken from the dot A and non dot B ends of the secondary winding of the main transformer The NCP1562 Design Tool shows a minimum voltage of approximately 7 V The maximum value of R7 is calculated using Equation 37 i VA or B 0 7 V IK Ibias where V is the diode drop of D3 or D6 and Ix is the TLV431 minimum cathode current Solving 37 with an Ig of 80 uA sets the maximum value of R7 at 10 9 kQ The value of R7 is set at 4 22 kQ The switching noise at nodes A and B is attenuated by placing a small resistor R12 in series with D3 and D6 The value of R12 is set at 49 9 The c
20. ed To Error Amplifier REF above 91 across the complete input voltage range A Network ae Analyzer Figure 31 shows the efficiency vs output current at 36 V 48 V and 72 V The peak efficiency is measured at 92 8 inverting Input i B Figure 29 Open Loop Frequency Response Measurement Setup The measured and calculated open loop responses are shown in Figure 30 The measured phase margin is 57 and the crossover frequency is 16 7 kHz A good correlation is Observed between the simulated and calculated responses up to around 30 kHz The simulated tool does not show the complex zeros and Di ac of the active clamp 0 5 10 15 20 25 30 lout OUTPUT CURRENT A Figure 31 Efficiency vs Output Current http onsemi com 18 NCP1562 Line and load regulation are calculated using 43 and 44 respectively AV Reg line Avie eq 43 Vout no load Vout full load Reg load eq 44 Vout no load Line regulation is measured below 0 01 and load regulation is measured below 0 23 The dynamic response of the converter at 48 V is evaluated stepping the load current from 50 to 75 and from 75 to 50 of Iou max The step load response is shown in Figure 32 100mVv 5 Figure 32 Output Voltage Response to a Step Load from 22 5 A to 15 A The output voltage ripple is measured at 16 mV at high line and full load It is significantly bel
21. em powers up the regulator is disabled thus reducing power consumption The regulator can be powered directly from the input line Soft Start allows the system to turn on in a controlled manner and reduce stress on system components Adjustable Maximum Duty Ratio allows the design to be optimized without a penalty on drain voltage Duty ratio is controlled within 5 Adjustable Volt second Limit prevents transformer saturation and improve transient response Semiconductor Components Industries LLC 2012 October 2012 Rev 2 ON Semiconductor hitp onsemi com EVAL BOARD USER S MANUAL Line Feedforward adjusts the duty ratio inversely proportional to line voltage allowing the controller to respond in the same cycle to line voltage changes It provides the controller some advantages of current mode control while eliminating noise susceptibility low power jitter and the need for ramp compensation Dual Mode Overcurrent Protection Circuit handles momentary and continuous overcurrent conditions differently to provide the best tradeoff in system performance and safety Line Under Overvoltage Detector circuits enable the device when the line voltage is within the pre selected voltage range A resistor divider from the input line biases the under and overvoltage detectors The accurate UV limit allows the converter to operate at high duty ratio without creating additional component stresses ON Semicon
22. er the complete operating range high turns ratio is desired to reduce the primary current and the secondary voltage However it causes the drain voltage to increase very rapidly at low line The ideal turns ratio is the one that achieves equal drain voltages at low and high line Vy arc D eq 2 150 N a eo o N a a o Vps DRAIN VOLTAGE V z M ol nN a 0 30 40 50 60 70 80 Vin INPUT VOLTAGE V Figure 5 Clamp Voltage vs Input Voltage for Several Turns Ratios Using the design tool a turns ratio of 6 is selected for a maximum duty ratio of 63 The ideal turns ratio is 6 5 but it would have increased the complexity of the transformer In high current output converters it is desired to keep the secondary turns at the lowest level e g 1 turn to reduce conduction losses The primary turns Np are set at 6 and the secondary turns Ns are set at 1 A 12 2 Np Ns ratio could have been used to reduce core losses Low core losses are beneficial when conduction losses are low as can be the case when operation at high line The magnetizing inductance is set at 120 uH to reduce conduction losses A planar transformer is selected due to its low profile and repeatable characteristics The custom transformer is manufactured by Payton Planar Magnetics and can be easily ordered under part number 51665 Active Clamp Stage The active clamp topology recycles
23. fz2 l eq 35 2x C25 R20 Resistor R19 is added to provide an injection point to measure the frequency response A small resistor value 10 to 20 Q is used for R19 so it does not affect the dc operating point Diode D5 clamps the output of the error amplifier during startup to improve the transient response The selection of the compensation network components begins by determining the error amplifier gain GgA using Equation 36 GEA 20 log 722 eq 36 R21 The system open loop gain in Figure 15 Simulated Open Loop Frequency Response at the desired crossover frequency of 15 kHz is 5 dB Therefore the EA gain is set at 8 77 dB to achieve a gain of 0 dB at approximately 15 kHz Resistors R20 and R21 are set at 5 9 kQ and 16 2 kQ respectively One compensation zero is placed before and one after Daten at 482 Hz and 9 8 kHz respectively Capacitors C25 and C29 are set at 0 056 uF and 1 000 pF respectively The second pole is set at a 457 kHz setting R30 at 348 Q The simulated frequency response is shown in Figure 17 The simulated crossover frequency is around 15 kHz with a 60 phase margin 40 TTTIT T T TT 1 80 Measured Phase 30 135 20 90 ao z 2 ez ty 10f Measured Gain pss 2 po DE z D O E 10 45 20 90 30 135 40 180 0 1 1 10 100 FREQUENCY kHz Figure 17 Simulated System Frequency Respons
24. has the higher duty ratio and thus the higher power dissipation as shown in Figure 34 At high line Oggc has the higher duty ratio and thus the higher power dissipation as shown in Figure 36 The NCP1562 evaluation board thermal performance can be optimized by using heatsinks integrating magnetic components on the board using additional layers and placing the synchronous rectifiers farther away from each other Please keep in mind that this is a evaluation board to showcase the flexibility of the NCP1562 A commercially available dc dc converter will use advanced packaging and manufacturing techniques to maximize power dissipation of critical components Summary A 100 W converter is designed and built using the active clamp forward topology The converter is implemented using the NCP1562 The full load efficiency is measured above 9146 over the complete operating range The converter provides excellent transient response Output voltage ripple is measured at 16 mV Phase margin and crossover frequency are measured at 57 and 16 7 kHz respectively This evaluation board is designed to demonstrate the features and flexibility of the NCP1562 This design should not be used for production or manufacturing purposes TEST PROCEDURE Power Supply Multimeter 1 Multimeter 2 MM2 OC Electronic Load NCP1562 Evaluation Board Vour G Multimeter 3 Q MM3 Figure 38 Test Setup Required Equipment
25. he UVOV pin to a 2 V reference Voy The system turn on threshold Vin uv is determined by the ratio of the resistor divider on the UV pin as shown in Equation 39 R1 Ra H4 The maximum operating voltage Vin ov is controlled by comparing the voltage on the UVOV pin to an internal 3 V reference Voy An internal current source loffse uvov sinks 50 uA into the UVOV pin once the UVOV voltage exceeds 2 5 V The voltage offset introduced by this current source allows independent adjustment of Matin and Vin ov patent pending The OV threshold depends on the ratio of the resistor divider as well as the absolute value of R1 as shown in Equation 40 R1 Ra Ra Ya loffset UVOV R1 eq 40 eq 39 Vin UV VUV Vin Ov Vov http onsemi com 12 NCP1562 100WGEVB A small capacitor of at least 1 000 pF is required on the UVOV to provide noise immunity and filter turn ON and turn OFF transitions on the input line The Design Tool suggests using an R1 of 504 kQ and an R2 of 32 4 kQ Used values are 523 Q and 32 4 kQ for R1 and R4 respectively The calculated operating voltage range is between 35 31 V and 80 15 V with Vi increasing and between 32 52 V and 75 V with Vin decreasing Maximum Duty Ratio As shown in Figure 5 the drain voltage of the main switch of an active clamp converter increases rapidly at low input voltages Accurate duty ratio control allows the designer to fully optimize the syste
26. ier Oppe The primary current continues to build while Qmain is on Time interval t1 t2 The main switch turns off at t1 The forward rectifier turns off at t1 eliminating the reflected secondary current component from Ip if the leakage inductance effect is neglected The primary current is now the magnetizing current It continues to flow in the same direction charging the drain capacitance Cgrain Time interval t2 t3 At time t2 the drain voltage reaches the clamp capacitor voltage The primary current charges both the drain capacitance and Comp The primary current flows through the body diode of Qclamp The clamp capacitor is several orders of magnitude larger Cgrain causing the voltage slope to drop The drain ripple voltage is determined by the resonance between LyAg and Colamp Time interval t3 t4 The active clamp switch can turn on at any time between t2 and t4 under ZVS conditions Once Qclamp turns on current flows through its channel The magnitude of Ip is decreasing and reaches zero at t4 It is imperative for Qclamp to be on at t4 Otherwise Ip will not have a path to reverse its direction Time interval t4 15 The primary current has reversed direction and is now discharging Cclamp The drain voltage begins to decrease The magnetizing current continues to build up in the reverse direction Time interval t5 t6 The active clamp switch turns off at t5 It is critical to achieve a fast turn off Qclam
27. istor A 0 01 uF is used for a 12 V gate voltage with an Rgs of 10 KQ Auxiliary Supply Regulator The NCP1562 has an internal startup circuit It charges the supply capacitor Caux on the Vaux pin until the startup threshold is reached The startup circuit is then disabled and the controller is biased by Caux The auxiliary capacitor is sized to store enough energy to maintain Vaux above its turnoff threshold Vaux otf2 An auxiliary supply biases Vaux under normal operating conditions to prevent the converter from turning off The auxiliary supply can be generated from a winding on the transformer or on the output inductor The main difference is the speed at which the supply voltage builds up The supply from the transformer builds up quickly where as the output inductor supply builds up with Vout However the output inductor supply is inherently regulated In this design the auxiliary supply is implemented from the transformer to reduce the value of Cayx An L C filter Laux Caux is used to average the voltage from the auxiliary winding as shown in Figure 9 Laux Mr TX1 Figure 9 Auxiliary Supply Architecture The number of auxiliary turns NAux is calculated using Equation 16 V N AU Wan Ve Solving Equation 16 3 6 turns are required for a Vaux of 12 V and a Vg of 0 7 V The turns are rounded up to 4 for a VAUX of 13 35 V The LC filter averages the voltage as long as the inductor operates in continuous conductio
28. m without risking exceeding the voltage rating of the main switch The NCP1562 incorporates an extremely accurate duty ratio control It is trimmed during manufacturing to achieve better that 5 accuracy over the complete temperature and process range Duty ratio and frequency are controlled using a timing resistor Ry and capacitor Cy on the RTCT pin The resistor is connected between the VREF and RTCT pins and the capacitor is connected between the RTCT and GND pins The converter is designed to operate at 350 kHz with a maximum duty ratio of 6346 Taking into account the overlap time delay the required oscillator duty ratio is 66 The Design Tool suggests initial values for Rr and Cr of 14 5 and 320 pF respectively Final values of Ry and Cy are set at 15 kQ and 300 pF Volt Second Limit and Feedforward A forward converter regulates the output voltage by maintain a constant Volt second V sec product If the maximum V sec product is exceeded the transformer will saturate and possibly damage to the system Therefore it is critical to accurately control the V sec product in a forward converter The NCP1562 implements V sec limit by generating a Feedforward FF Ramp proportional to Vin and comparing it to a 3 V reference The ramp is generated by charging an external capacitor Cpp with a resistor Rpp from Vin Feedforward is achieved by changing the slope of the FF Ramp while maintaining a constant error voltage Feedforward
29. maximum power dissipation given by Equation 14 The maximum power dissipation of Oggc occurs at low line and for Opw at high line The conduction losses for Qrec and Opw are given by Equations 23 and 24 respectively Pcond REC lout rms D RpS on eg 23 Pcond FW out rms 1 D RpS on eq 24 The gate charge losses of the driver and body diode conduction losses are given by 25 and 26 respectively Pariver fsw QG TOT Vgate eq 25 Pbd Vbd lout fsw tdead eq 26 Figure 13 shows the synchronous rectification losses calculated by the NCP1562 Design Tool Freewheeling MOSFET _ Rectification MOSFET POWER W Mi o 30 40 50 60 70 80 Vin INPUT VOLTAGE V Figure 13 Synchronous Rectification Losses The full load losses for Ogw and Oppe are 3 6 W and 3 4 W respectively Two MOSFETS are used in parallel for each of Opw and Oggc However it is apparent that external cooling or a heatsink is required to deliver full power Alternatively a larger number of MOSFETS in parallel could have been used Almost no ringing is observed on the drain of the synchronous rectifiers This is due to the minimum parasitic inductance and capacitance of the SO 8 FL package and the tight layout of the output power stage No R C snubbers are required across the synchronous rectifiers Optocoupler and Vea Circuit The output voltage is reg
30. n as it has signals readily available that may be used for driving a synchronous rectifier The synchronous rectifiers are driven from the main transformer output winding as shown in Figure 11 This configuration is known as self driven synchronous rectification SD SR The voltage of the transformer output when the main switch is on Vfw and off Vreo are given by Equations 21 and 22 Vin VFW N eq 21 V VREC came eq 22 Before SD SR can be used the voltage at the transformer output needs to be calculated to ensure it is high enough to turn on the rectification MOSFETs but it does not exceed its maximum gate voltage Using the NCP1562 Design Tool the range for Vrw and Vrgc is calculated between 4 7 V and 12 7 V as shown in Figure 12 A MOSFET characterized with a 4 5 V gate voltage should be used to ensure the rectification MOSFET turn on Lout QFW Cout QREC Cclamp Qclamp Figure 11 Synchronous Rectification Circuit hitp onsemi com NCP1562 100WGEVB 6 VREC STRESS VOLTAGE V 2 0 30 40 50 60 70 80 Vin INPUT VOLTAGE V Figure 12 Synchronous Rectifier Gate Voltage If the secondary voltage is not compatible with the MOSFET gate voltage a few alternatives are available as listed below 1 Use a lower transformer turns ratio 2 Add an extra winding or use a stacked winding on the transformer secondary 3 Drive the MOSFETs from the
31. n losses and at high line by switching losses The maximum power dissipation of the main switch is calculated using Equation 14 _ TJ max TA max R JA where RgjA is the junction to ambient thermal resistance and Ty max and TA max are the maximum junction and ambient temperatures respectively Please keep in mind that Equation 14 assumes there are no other heat sources in the system However this is not the case in a real system As specified in Table 1 TA max is 50 C Solving Equation 14 for Ty maxy at high line a maximum Ty of 131 C is calculated The maximum allowed Ty is 158 C assuming an 90 derating for Tj max of the FDD2582 Power dissipation of the main switch is high and should be verified during design validation to make sure it is still within acceptable limits However keep in mind that this is a worst case scenario as the provided Boa does not include airflow Also it is for a lower copper weight than the one used on this board The thermal resistance of the main switch can be reduced by maximizing the copper area around the package A heatsink can also be added on top of the package P eq 14 Active Clamp Switch The active clamp switch experiences low conduction losses because only the magnetizing current flows through it Switching losses are negligible because the active clamp switch is turned on after the body diode is conducting IR s IRF6217PBF is used for the active clamp switch It is a 150
32. n mode The auxiliary inductor value is selected in the same manner as the output inductor using Equation 6 by replacing the out subscript with AUX The auxiliary current IAux is calculated using Equation 17 lAUX lAUX3 f gt QT main QT clamp eq 16 NAUX eq 17 where IAuxa is the controller bias current refer to the NCP1562 datasheet and Or main and QT clamp are the total gate charge of the main and active clamp switches respectively Solving Equation 17 an IAux of 23 2 mA is obtained The required inductor for an IAUX min of 15 of IAux is 694 uH Coilcraft s DO1606T series is selected for the auxiliary inductor This series is very rugged and has a very low profile The next size up in the DO1606T series is used It is 1000 uH As previously discussed Cayx must be sized to maintain Vaux above Vaux off2 during startup The NCP1562 reduces the Cayx requirement by turning on the startup circuit if an intermediate threshold Vaux off1 is reached This in addition to the other factors that affect the auxiliary supply load current soft start period etc make the selection of Vaux non trivial Empirically it was found that 88 uF works well under all operating conditions However 116 uF was used as the components were readily available from distribution The Vayx capacitance consists of one 22 uF ceramic capacitor across the NCP1562 to reduce noise and two 47 uF tantalum capacitors for bulk st
33. n of 45 under all line and load conditions This is accomplished by shaping the open loop response using an error amplifier The first step is to determine the open loop frequency response of the converter An active clamp forward converter operating in voltage mode has two poles p1 2 1 C due to the output LC filter and one zero zgsg due to the output capacitor series resistance In addition it has two complex zeros introduced by the active clamp network The complex zeros are not shown due to their great complexity The complex zeros happen before the system poles P1 AC The system crossover frequency should be selected below P15 AC to avoid the complex poles Equations 28 through 30 show the system poles and zeros 1 P1 2 LC 2 eg 2n dLout Cout d 1 ZESR 27 Been Cout eq 29 1 D P1 2 AC eq 30 27 LMAG Cclamp The ESR of the output capacitors is very low lt 1 mQ pushing Zgsg above 100 kHz The worst case of the active clamp RHP is at low line In this design it is around 41 1 kHz The controller or modulator gain Gyop is given by Equation 31 RFF Lou CFF GMOD N Using the values calculated earlier GMop is 1 86 dB The gain of the optocoupler is given by Equation 32 REA CTR R13 eq 31 GOPTO eq 32 where CTR is the optocoupler transfer ratio R3 is the resistor at the optocoupler anode Assuming a CTR of 1 the gain is 18 7 dB The controller gain and system
34. nd line conditions Line Regulation should not exceed 0 1 under all load and line conditions NCP1562 100WGEVB REFERENCES 1 Pressman Abraham I Switching Power Supply Design 2nd ed New York NY MacGraw Hill 2 Ridley Ray The Evolution of Power Electronics Switching Power Magazine 3 Dennis Solley Improving Opto Coupler Bandwidth AND8271 D www onsemi com 4 High Performance Active Clamp Reset PWM Controller Datasheet NCP1562A D www onsemi com 5 Dhaval Dalal and Larry Wofford Novel Control IC for Single Ended Active Clamp Converters in HFPC 95 Conf Proc pp 136 146 1995 6 G Stojcic F Lee and S Hiti Small Signal Characterization of Active Clamp PWM Converters in VPEC Seminar Conf Proc pp 237 245 1995 ON Semiconductor and are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability
35. of 1 15 uH is required A custom 1 5 uH inductor from Payton Planar Magnetics is used It can be easily ordered under part number 51666 The inductor ripple current Iout rip reaches its maximum value at high line and it is given by Equation 7 Lout Es 1 15 uH Vout 1 ton min pA SW lout rip Eo eq 7 Solving Equation 7 33 120 271 lout rip lur 458A a maximum ripple current of 4 58 A is obtained Figure 7 shows the inductor current at low and high line as provided by the Design Tool 33 C N Low Lin A IL INDUCTOR CURRENT A w E 29 28 27 0 0 5 1 0 1 5 2 0 2 5 3 0 Time us Figure 7 Calculated Output Inductor Current at Low and High Conditions The minimum output capacitance required to maintain the output voltage ripple below our target of 50 mV is calculated using Equation 8 lout rip 8 Loun Vout rip Cout Ge eq 8 A minimum capacitance of 33 uF is required The capacitor ESR also affects the output voltage ripple as shown in Equation 9 Vout rip lout rip RESR eq 9 In order to maintain Vout rip below our target Resp has to be below 10 9 mQ Please consider that Equation 8 provides a minimum value to maintain Vout rip within target In most cases a higher Cout is required to meet voltage holdup requirements and shape the frequency response of the converter as it is http onsemi com 5 NCP1562 100WGEVB describe
36. omponents of the peak detector D3 D6 R12 and C9 are placed close to each other but away from the EA to keep noise low A bypass capacitor C6 is placed across the supply terminals of the EA Both C9 and C6 are set at 0 1 uF R7 eq 37 Current Limit Circuit This converter is designed to deliver 100 W under normal operating conditions However under a fault condition the current may increase significantly and permanently damage the system The NCP1562 incorporates an extremely accurate current limit circuit to protect the system while a current limit condition is present A low propagation delay combined with an extremely accurate current limit threshold limit the maximum power delivered under a current limit condition This allows the designer to have a robust and safe system without excessive over design The NCP1562 has two overcurrent protection methods cycle by cycle and cycle skip In cycle by cycle the conduction period ends once the current limit threshold is reached Cycle skip is enabled if the converter is in a continuous current limit for a user programmed time While in cycle skip mode the converter power downs and restart after a user determined time The NCP1562A is used in this design It has a current limit voltage threshold Vr y of 0 2 V A current sense resistor is used to reduce system cost and complexity It is calculated using 38 VILIM IP PK Using Ipcpxy calculated earlier Rgense is calculated at 3
37. orage Input Filter An input L C Lin Gin filter is used to reduce EMI and provide a solid input voltage to the converter The input filter design is constrained by stability and power rating criteria Oscillation will occur if the converter input impedance Zin is lower than the filter output impedance Zout The converter closed loop input impedance is ultimately determined by the converter feedback loop However the converter input impedance can be approximated as a negative resistor using 18 Zin dB9 20log L t eq 18 lout The L C filter output impedance is given by 19 R Zout dBQ Lin n Cin ESR eq 19 where n is the number of capacitors in parallel The input inductor is selected to handle the converter average input current Coilcraft s DS3316P 152 is used as the input inductor http onsemi com 7 NCP1562 100WGEVB The input capacitors are selected based on the input ripple current given by 20 Ceramic capacitors are preferred due their low ESR and high ripple current capability TDK s C4532X7R2A225MT are used as the input capacitors ae lin rms P tee IPIPK IP VL IPPK MA eq 20 Equation 20 is an approximation and assumes the magnetizing current reverse directions halfway during the off time It can be observed that equations 12 and 20 are very similar The main difference is the ripple component added by the active clamp during the reset of the transformer Equation 20
38. ow the 50 mV target The output voltage ripple waveform at high line and full load is shown in Figure 33 Figure 33 Output Voltage Ripple at High Line and Full Load 100WGEVB Thermal Performance This evaluation board is designed to operate with airflow as in a telecom system Airflow is required if the converter operates above 5046 of its rated power Optimum cooling is achieved when air flows from the output side to the input side The thermal performance of the board is evaluated using an infrared camera Figure 34 through Figure 37 show several images of the board at full load Images include top and bottom layers at low and high line All images were taken with airflow from the output side to the input side Air Flow Figure 34 Thermal Image of the Top of the Board at Low Line and Full Load Condition 50 0 C 40 30 Air Flow Figure 35 Thermal Image of the Bottom of the Board at Low Line and Full Load Condition LI Air Flow Figure 36 Thermal Image of the Top of the Board at High Line and Full Load Condition 70 0 C 60 50 40 30 22 3 http onsemi com 19 NCP1562 100WGEVB 65 0 C Air Flow 22 2 Figure 37 Thermal Image of the Bottom of the Board at High Line and Full Load Condition Most of the losses on the board are on the main switch and synchronous rectifiers The synchronous rectifier losses are dominated by conduction losses At low line Qpw
39. p to force the magnetizing current to discharge the drain capacitance Otherwise current will continue flowing through Qclamp The drain voltage decays as the drain capacitance is discharged The minimum drain voltage is determined by the inductive energy Er stored in the magnetizing and leakage inductances If the inductive energy is greater than the capacitive energy stored in the drain capacitance ZVS is achieved If the magnetizing energy is not enough an external inductor can be added to facilitate ZVS The inductive energy is increased by reducing LAG This might be counter intuitive But let me explain Let s start with the magnetizing energy equation given by Equation 1 EL MAG LMAG IMAG eq 1 For a given voltage and on time the Lyac and IMAG product is constant That is if LAG decreases by 1 2 IMAG increases by 2 As Imag is squared the net effect is an increase in energy http onsemi com 3 NCP1562 100WGEVB Design Procedure The converter design is divided in several steps to ease the design process The process begins with the power stage as it determines most of the system components The design continues with the feedback loop followed by the setup of the controller the NCP1562 Finally the system performance is evaluated and compared to the design target Throughout this application note operation at the minimum and maximum input voltages are referred as low and high line respectively
40. primary side OUT1 and OUT2 using a gate drive transformer The selection of the rectification MOSFETs in an SD SR configuration is not trivial Both conduction and switching losses should be optimized for the best overall efficiency Contrary to traditional belief the lowest RDs on MOSFET will not always provide the best overall efficiency The incremental reduction in conduction losses of a low Rps on MOSFET may be overcome by an increase in switching losses ON Semiconductor s NTMFS4835N is selected for both Qrec and Qrw MOSFETs It is a 30 V MOSFET with a maximum Rpgs on of 5 0 mQ and a maximum gate charge of 39 nC at 4 5 V The NTMFS4835N is housed in a SO 8 Flat Lead FL package The SO 8 FL is a leadless package with an exposed tab to reduce thermal resistance and parasitic inductance and capacitance The maximum power dissipation of the SD SR MOSFETs is calculated using Equation 14 The NTMFS4835 datasheet provides an RgjA of 55 1 C W and a Tymax of 150 C Telecom products are usually designed for a TA max of 50 C Solving Equation 14 with 90 derating on Ty max each MOSFET can dissipate 1 54 W If higher power dissipation is required a heatsink can be added to the MOSFET to reduce its Resa The converter high output current requires multiple MOSFETs to be used in parallel due to the high conduction losses The number of MOSFETs for Opw and Oppe is determined by calculating the losses of each one and dividing it by the
41. races for high current connections 3 Use a single ground connection 4 Keep sensitive nodes away from noisy nodes such as drain of power switches Place decoupling capacitors close to ICs Sense output voltage at the output terminal to Figure 23 Inner Layer 2 improve load regulation gu A The layers are numbered 1 through 4 from top to bottom and are shown in Figure 22 through Figure 25 The top and bottom layers show the component location http onsemi com 14 NCP1562 100WGEVB Design Validation The top and bottom view of the board are shown in Figure 26 and Figure 27 respectively Figure 24 Inner Layer 3 Figure 27 NCP1562 Evaluation Board Bottom View SECONDARY SIDE The circuit schematic is shown in Figure 28 and the bill of Figure 25 Layer 4 Bottom material is listed in Table 3 The layout files may be available Please contact your sales representative for availability http onsemi com 15 NCP1562 100WGEVB zu
42. reduces line voltage variations and provides a frequency gain independent of Vin making the system easier to compensate The peak voltage of the ramp is set below 3 V under normal operating conditions The margin allows the converter to quickly respond during a transient The FF components are calculated starting with the desired maximum FF charge current Ipp Given Ipp Rpr is calculated by dividing the maximum input voltage by Ipr The FF capacitor is calculated using Equation 41 IFF V SeC max 3V Our transformer has a V seC max of 62 4 V usec Selecting an arbitrarily Ipp of 1 75 mA the Design Tool suggest values of 43 4 KQ and 479 pF for Rpp and Cpp respectively Final values are 45 3 kQ for Rpp and 470 pF for Cpp As duty ratio control is very important the tolerances for Rpp and Cer are set at 1 and 5 respectively eq 41 CFF Soft Start Soft start slowly starts the converter and reduces stress during power up The NCP1562 implements soft start by comparing the voltage in the SS pin to the FF Ramp Soft start is adjusted by placing an external capacitor Css between the SS pin and ground The capacitor is charged with a constant 10 uA current source The peak voltage of the FF Ramp is 3 V Therefore soft start ends once the SS voltage exceeds the FF Ramp or it exceeds 3 V Under steady state conditions the SS capacitor is charged to 3 8 V Soft Stop The clamp capacitor in a forward topology needs to be
43. s a controlled turn off without any unwanted oscillations on the drain voltage eq 42 Vclamp hitp onsemi com 13 NCP1562 100WGEVB ON Semiconductor NCP1562 Active Clamp V Moda Rev 38 DM ia soogs Chi ay Figure 21 Converter Power Down using Soft Stop The same capacitor is used for soft start and soft stop The minimum soft start time is determined by the required soft stop period A soft start to soft stop ratio of 1 10 is set with the internal charge and discharge currents If a different ratio is required a resistor can be placed between the VREF and SS pins to increase the SS charge current Figure 22 Layer 1 Top Board Layout The converter is built to validate the design using a 4 layer FR4 double sided board The converter meets the industry standard half brick 2 3 in x 2 4 in footprint and pinout Power components are placed on the top layer primary and control components on the bottom secondary layer The board is constructed using 2 oz copper The top and bottom layers are plated to 3 oz to improve power dissipation The two inner layers are used for ground and signal routing During the layout process care was taken to 1 Minimize trace length especially for high current loops 2 Use wide t
44. sists of an ideal transformer magnetizing LAG and leakage Ligo inductances The active clamp network consists of the P channel clamp switch Qelamp and clamp capacitor Clamp This configuration is known as low side active clamp A high side clamp could have been implemented using an N channel MOSFET and clamp capacitor in parallel with the transformer primary However it requires a floating gate drive signal increasing system cost and complexity ere ban Synchronous Rectifier Control Cout Qrec Cclamp Qclamp Figure 2 Active Clamp Fe Forward Converter The differences between traditional and active clamp forward converters are during the main switch off time In the active clamp topology the transformer is reset at a lower voltage during the complete off time instead of a higher voltage during a shorter period of time Figure 3 shows a comparison between the drain waveforms of both topologies The traditional forward waveform was taken with a primary reset winding ratio of 5 3 instead of 1 1 The 5 3 ratio allowed operation above 50 duty cycle Reset Winding Active Clamp Wh 20 0V amp 20 0V wM1 00gs Chi 7 54 8V Figure 3 Drain Voltage Waveforms for Traditional and Active Clamp Forward Topologies hitp onsemi com NCP1562 100WGEVB The differences go beyond the replacement of the reset winding and catch diode with a clamp capacitor and a clamp switch There are many system consi
45. the transformer magnetizing energy using a resonant circuit This resonant circuit is composed of the magnetizing inductance and clamp capacitor The parasitic drain capacitance and leakage inductance are ignored as they are very small The resonant frequency of LyAg and Celamp is selected low enough to maintain a constant voltage during the main switch off time That is the resonant period is significantly larger than the switching period of the controller The clamp capacitor determines the drain ripple voltage Vps ippie during the main switch off time The ripple voltage is inversely proportional to Ccjamp The active clamp capacitor also affects the loop response as it contributes to a pair of complex zeros introduced by the active clamp stage It is discussed later in the Feedback Loop Section If duty hitp onsemi com 4 NCP1562 100WGEVB ratio changes rapidly the voltage across Cclamp has to change accordingly Otherwise the transformer may saturate Therefore a tradeoff between ripple voltage and transient response has to be considered in the selection of Cclamp The design tool facilitates the selection of Cojamp by plotting Vps rippie and the normalized peak flux excursion VS Celamp as shown in Figure 6 S60 3 0 H le Voltage at High Line n 2 5x Oo 50 5 m ir 540 20x at Low Line W H D O LI 30 150 z N zal 20 1 03 a c E o 10 0 5Z d a gt 0 0
46. ulated by comparing the error signal in the VgA pin to the feedforward FF ramp An optocoupler transmits the error signal across the isolation boundary Typically optocouplers introduce a pole around 10 kHz This pole limits the system bandwidth and complicates the frequency compensation of the converter as it occurs at the desired crossover frequency range The pole is due to the impedance and capacitance at the collector terminal Fortunately there are a few tricks to move the optocoupler pole to a higher frequency and increase the system bandwidth First a cascode stage using a bipolar transistor O1 is placed between the optocoupler pull up resistor RgA and the collector of the optocoupler as shown in Figure 14 The http onsemi com 9 NCP1562 100WGEVB collector impedance is now the impedance looking into the emitter of the bipolar transistor which is very small The optocoupler pole is effectively moved to a higher frequency gt 50 kHz Vref EA y lt Feedback R13 Figure 14 High Bandwidth Optocoupler Biasing Configuration Second the optocoupler diode is driven with an ideal current source This arrangement works very well during transients and power up As the diode is driven with a current instead of a voltage source the error amplifier output does not have to swing too far during a transient This arrangement is also immune to supply voltage variations The optocoupler gain changes with its bias c
47. urrent Iopto It is not uncommon for an optocoupler to have a gain variation of 10 or more over the operating current range As the optocoupler bias current changes from low to high line it presents a design challenge In addition optocoupler performance changes with age and temperature A low gain optocoupler is preferred to minimize its impact in the overall system gain NEC s PS2703 1 M optocoupler is used in this design The optocoupler manufacturer recommends biasing the optocoupler at 1 mA Our optocoupler is designed to operate at 1 mA at nominal input voltage 48 V However the bias current at low or high line will be slightly different Equation 27 relates the duty ratio to optocoupler bias current VREF 3 D 0 9 REA lopto eq 27 where Vggr is the voltage reference of the controller The NCP1562 Design Tool suggests a duty ratio of 0 43 at nominal input voltage Solving Equation 27 an RgA of 2 81 KQ is suggested An Rga of 3 01 KQ is used The base of the O1 is biased at approximately 1 5 V using R6 and R11 That insures the optocoupler collector emitter voltage is kept above its saturation voltage of 0 3 V Feedback Loop The converter regulates the output voltage by adjusting the duty ratio using a negative feedback loop If the loop is not stable the converter will oscillate To insure the loop is stable and has adequate transient response the closed loop response should have a minimum phase margi
48. voltage drop on the EL terminals will affect your measurements The complete test setup should be similar to Figure 38 Slowly ramp the input voltage Vin to 10 V If input current exceeds 30 mA verify the setup If connection is correct stop testing Board needs to be repaired Increase the input voltage to 25 V The NCP1562 start up circuit should be operating Probe terminal 16 of U1 The waveform should look similar to Figure 39 If not stop testing Board needs to be repaired Increase the input voltage to 36 V The evaluation board output should be between 3 135 V and 3 465 V If not stop testing Board needs to be repaired Measure and collect input current lin and voltage as well as output current and voltage Vout Increase load current in steps of 10 A 14 Figure 39 Start up Circuit Waveform Calculate efficiency m load REGioaq and line regulation REG jne using Equations 45 46 and 47 Vout x lout x 100 eq 45 Vin x1 in REG V out noload V out loaded x 100 eq 46 SS V out noload V say V REG D out Vin1 out Vin2 x 100 eq 47 E Vint Vine 15 Set load current to 0 A 16 17 18 19 hitp onsemi com 21 Repeat steps 13 14 and 15 for input voltages of 48 V and 76 V Minimum Efficiency should not drop below 90 under all load and line conditions Load Regulation should not exceed 1 under all load a
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